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[/] [openverifla/] [trunk/] [openverifla_2.4/] [verilog/] [verifla/] [computer_input_of_verifla.v] - Blame information for rev 46

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1 46 laurentiud 
/*
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file: computer_input_of_verifla.v
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license: GNU GPL
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Revision history
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- 20180827-1700
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allow only USERCMD_RUN.
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revision date: 2007/Sep/03; author: Laurentiu DUCA
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- USERCMD_RESET
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revision date: 2007/Jul/4; author: Laurentiu DUCA
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- v01
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*/
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module computer_input_of_verifla (clk, rst_l,
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        rec_dataH, rec_readyH, user_run);
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// user commands
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parameter USERCMD_RUN = 8'h01;
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// CI_states
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parameter       CI_STATES_BITS=4,
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        CI_STATE_IDLE=0,
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        CI_STATE_START_OF_NEW_CMD=1;
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// input
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input clk, rst_l;
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input rec_readyH;
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input [7:0] rec_dataH;
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// output
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output user_run;
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reg user_run;
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// locals
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reg [CI_STATES_BITS-1:0] ci_state, next_ci_state;
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reg [7:0] ci_indata, next_ci_indata;
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wire ci_new_octet_received;
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// T(clk)<<T(uart_clk)
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single_pulse_of_verifla sp1(.clk(clk), .rst_l(rst_l), .ub(rec_readyH), .ubsing(ci_new_octet_received));
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// set up next value
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always @(posedge clk or negedge rst_l)
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begin
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        if(~rst_l)
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        begin
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                ci_state=CI_STATE_IDLE;
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                ci_indata=0;
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        end
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        else
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        begin
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                ci_state=next_ci_state;
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                ci_indata=next_ci_indata;
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        end
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end
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// state machine
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always @(ci_new_octet_received or rec_dataH or ci_state or ci_indata)
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begin
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        // implicit
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        next_ci_state=ci_state;
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        next_ci_indata=0;
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        user_run=0;
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        // state dependent
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        case(ci_state)
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        CI_STATE_IDLE:
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        begin
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                if(ci_new_octet_received)
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                begin
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                        next_ci_indata=rec_dataH;
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                        next_ci_state=CI_STATE_START_OF_NEW_CMD;
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                end
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                else
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                        next_ci_state=CI_STATE_IDLE;
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        end
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        CI_STATE_START_OF_NEW_CMD:
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        begin
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                next_ci_state=CI_STATE_IDLE;
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                if(ci_indata == USERCMD_RUN)
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                        user_run=1;
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        end
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        default: // should never get here
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        begin
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                next_ci_state=CI_STATE_IDLE;
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        end
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        endcase
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end
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endmodule

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