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[/] [openverifla/] [trunk/] [openverifla_2.4/] [verilog/] [verifla/] [uart_of_verifla.v] - Blame information for rev 46

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1 46 laurentiud 
/*
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Update: Laurentiu Duca, 20180808_1200:
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        - consider baud_clk_posedge
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*/
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module uart_of_verifla  (       sys_clk,
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                                sys_rst_l,
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                                baud_clk_posedge,
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                                // Transmitter
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                                uart_XMIT_dataH,
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                                xmitH,
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                                xmit_dataH,
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                                xmit_doneH,
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                                // Receiver
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                                uart_REC_dataH,
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                                rec_dataH,
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                                rec_readyH
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                        );
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input                   sys_clk;
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input                   sys_rst_l;
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output          baud_clk_posedge;
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// Trasmitter
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output                  uart_XMIT_dataH;
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input                   xmitH;
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input   [7:0]    xmit_dataH;
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output                  xmit_doneH;
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// Receiver
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input                   uart_REC_dataH;
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output  [7:0]    rec_dataH;
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output                  rec_readyH;
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wire                    baud_clk_posedge;
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wire    [7:0]    rec_dataH;
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wire                    rec_readyH;
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// Instantiate the Transmitter
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u_xmit_of_verifla txd1 (
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                .clk_i(sys_clk),
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                .rst_i(!sys_rst_l),
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                .baud_clk_posedge(baud_clk_posedge),
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                .data_i(xmit_dataH),
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                .wen_i(xmitH),
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                .txd_o(uart_XMIT_dataH),
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                .tre_o(xmit_doneH)
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        );
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/*
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u_xmit  iXMIT(  .sys_clk(baud_clk),
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                                .sys_rst_l(sys_rst_l),
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                                .uart_xmitH(uart_XMIT_dataH),
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                                .xmitH(xmitH),
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                                .xmit_dataH(xmit_dataH),
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                                .xmit_doneH(xmit_doneH)
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                        );
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*/
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// Instantiate the Receiver
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u_rec_of_verifla rxd1(
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                .clk_i(sys_clk),
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                .rst_i(!sys_rst_l),//system signal
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                .baud_clk_posedge(baud_clk_posedge),
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                .rxd_i(uart_REC_dataH),//serial data in
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                .rdy_o (rec_readyH), .data_o(rec_dataH) //data ready and parallel data out signal
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                );
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/*
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u_rec iRECEIVER (// system connections
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                                .sys_rst_l(sys_rst_l),
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                                .sys_clk(baud_clk),
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                                // uart
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                                .uart_dataH(uart_REC_dataH),
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                                .rec_dataH(rec_dataH),
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                                .rec_readyH(rec_readyH)
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                                );
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*/
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// Instantiate the Baud Rate Generator
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baud_of_verifla baud1(  .sys_clk(sys_clk),
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                        .sys_rst_l(sys_rst_l),
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                        .baud_clk_posedge(baud_clk_posedge)
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                );
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/*
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reg [2:0] baud_clk_vec=0;
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always @(posedge sys_clk or negedge sys_rst_l)
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begin
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        if(~sys_rst_l)
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                baud_clk_vec = 0;
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        else
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                baud_clk_vec = {baud_clk_vec[1:0], baud_clk};
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end
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wire baud_clk_posedge;
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assign baud_clk_posedge=baud_clk_vec[2:1]==2'b01;
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*/
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endmodule

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