| 1 |
46 |
laurentiud |
-- Author: Laurentiu Duca
|
| 2 |
|
|
-- License: GNU GPL
|
| 3 |
|
|
-- 20181016-1225
|
| 4 |
|
|
-- LA_TRACE_MASK
|
| 5 |
|
|
-- 20180826-1740
|
| 6 |
|
|
-- split mon_run in sys_run and user_run
|
| 7 |
|
|
-- 20180820-1500
|
| 8 |
|
|
-- first source
|
| 9 |
|
|
-----------------------------------------------------
|
| 10 |
|
|
|
| 11 |
|
|
library IEEE;
|
| 12 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 13 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
| 14 |
|
|
--use ieee.std_logic_arith.all;
|
| 15 |
|
|
--use ieee.std_logic_unsigned.all;
|
| 16 |
|
|
use work.common_internal_verifla.all;
|
| 17 |
|
|
|
| 18 |
|
|
-----------------------------------------------------
|
| 19 |
|
|
|
| 20 |
|
|
entity monitor_of_verifla is
|
| 21 |
|
|
port (clk, rst_l: in std_logic;
|
| 22 |
|
|
sys_run, user_run: in std_logic;
|
| 23 |
|
|
data_in: in std_logic_vector(LA_DATA_INPUT_WORDLEN_BITS-1 downto 0);
|
| 24 |
|
|
mem_port_A_address: out std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
|
| 25 |
|
|
mem_port_A_data_in: out std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
|
| 26 |
|
|
mem_port_A_wen: out std_logic;
|
| 27 |
|
|
ack_sc_run, sc_done: in std_logic;
|
| 28 |
|
|
sc_run: out std_logic);
|
| 29 |
|
|
end monitor_of_verifla;
|
| 30 |
|
|
|
| 31 |
|
|
-----------------------------------------------------
|
| 32 |
|
|
|
| 33 |
|
|
architecture monitor_of_verifla_arch of monitor_of_verifla is
|
| 34 |
|
|
|
| 35 |
|
|
constant LA_MEM_FIRST_ADDR_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
|
| 36 |
|
|
:= std_logic_vector(to_unsigned(LA_MEM_FIRST_ADDR, LA_MEM_ADDRESS_BITS));
|
| 37 |
|
|
constant LA_MEM_LAST_ADDR_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
|
| 38 |
|
|
:= std_logic_vector(to_unsigned(LA_MEM_LAST_ADDR, LA_MEM_ADDRESS_BITS));
|
| 39 |
|
|
constant LA_BT_QUEUE_TAIL_ADDRESS_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
|
| 40 |
|
|
:= LA_MEM_LAST_ADDR_SLV;
|
| 41 |
|
|
constant LA_TRIGGER_MATCH_MEM_ADDR_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
|
| 42 |
|
|
:= std_logic_vector(to_unsigned(LA_TRIGGER_MATCH_MEM_ADDR, LA_MEM_ADDRESS_BITS));
|
| 43 |
|
|
constant LA_MEM_LAST_ADDR_BEFORE_TRIGGER_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
|
| 44 |
|
|
:= std_logic_vector(to_unsigned(LA_MEM_LAST_ADDR_BEFORE_TRIGGER, LA_MEM_ADDRESS_BITS));
|
| 45 |
|
|
|
| 46 |
|
|
--type state_type is (MON_STATE_IDLE, MON_STATE_DO_MEM_CLEAN, MON_STATE_PREPARE_RUN,
|
| 47 |
|
|
--MON_STATE_WAIT_TRIGGER_MATCH, MON_STATE_AFTER_TRIGGER, MON_STATE_AFTER_TRIGGER,
|
| 48 |
|
|
--MON_STATE_CLEAN_REMAINING_MEMORY1,MON_STATE_CLEAN_REMAINING_MEMORY2,MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS,
|
| 49 |
|
|
--MON_STATE_SC_RUN, MON_STATE_WAIT_SC_DONE);
|
| 50 |
|
|
-- This way, at reset we can set any start state.
|
| 51 |
|
|
constant MON_STATE_IDLE: integer :=0;
|
| 52 |
|
|
constant MON_STATE_DO_MEM_CLEAN: integer :=1;
|
| 53 |
|
|
constant MON_STATE_PREPARE_RUN: integer :=2;
|
| 54 |
|
|
constant MON_STATE_WAIT_TRIGGER_MATCH: integer :=3;
|
| 55 |
|
|
constant MON_STATE_AFTER_TRIGGER: integer :=4;
|
| 56 |
|
|
constant MON_STATE_CLEAN_REMAINING_MEMORY1: integer :=5;
|
| 57 |
|
|
constant MON_STATE_CLEAN_REMAINING_MEMORY2: integer :=6;
|
| 58 |
|
|
constant MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS: integer :=7;
|
| 59 |
|
|
constant MON_STATE_SC_RUN: integer :=8;
|
| 60 |
|
|
constant MON_STATE_WAIT_SC_DONE: integer :=9;
|
| 61 |
|
|
|
| 62 |
|
|
signal sys_run_reg: std_logic;
|
| 63 |
|
|
signal sc_run_aux, next_sc_run_aux: std_logic;
|
| 64 |
|
|
signal mon_state, next_mon_state: integer; -- state_type;
|
| 65 |
|
|
signal next_mon_samples_after_trigger, mon_samples_after_trigger:
|
| 66 |
|
|
std_logic_vector(LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1 downto 0);
|
| 67 |
|
|
signal next_mon_write_address, mon_write_address:
|
| 68 |
|
|
std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
|
| 69 |
|
|
signal next_bt_queue_tail_address, bt_queue_tail_address: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
|
| 70 |
|
|
signal next_bt_cycled, bt_cycled: std_logic;
|
| 71 |
|
|
signal mon_old_data_in, mon_current_data_in: std_logic_vector(LA_DATA_INPUT_WORDLEN_BITS-1 downto 0);
|
| 72 |
|
|
signal mon_clones_nr, next_mon_clones_nr: std_logic_vector(LA_IDENTICAL_SAMPLES_BITS-1 downto 0);
|
| 73 |
|
|
signal one_plus_mon_write_address:std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
|
| 74 |
|
|
signal oneplus_mon_clones_nr:std_logic_vector(LA_IDENTICAL_SAMPLES_BITS-1 downto 0);
|
| 75 |
|
|
signal data_in_changed: std_logic;
|
| 76 |
|
|
signal last_mem_addr_before_trigger: std_logic;
|
| 77 |
|
|
signal not_maximum_mon_clones_nr: std_logic;
|
| 78 |
|
|
|
| 79 |
|
|
begin
|
| 80 |
|
|
|
| 81 |
|
|
-- Register the input data
|
| 82 |
|
|
-- such that mon_current_data_in is constant the full clock period.
|
| 83 |
|
|
register_input_data: process(clk, rst_l)
|
| 84 |
|
|
begin
|
| 85 |
|
|
if (rst_l='0') then
|
| 86 |
|
|
mon_old_data_in <= (others => '0');
|
| 87 |
|
|
mon_current_data_in <= (others => '0');
|
| 88 |
|
|
sys_run_reg <= '0';
|
| 89 |
|
|
elsif (rising_edge(clk)) then
|
| 90 |
|
|
mon_old_data_in <= mon_current_data_in;
|
| 91 |
|
|
mon_current_data_in <= data_in;
|
| 92 |
|
|
sys_run_reg <= sys_run;
|
| 93 |
|
|
end if;
|
| 94 |
|
|
end process;
|
| 95 |
|
|
|
| 96 |
|
|
-- set new values
|
| 97 |
|
|
state_reg: process(clk, rst_l)
|
| 98 |
|
|
begin
|
| 99 |
|
|
if (rst_l='0') then
|
| 100 |
|
|
mon_state <= MON_STATE_IDLE;
|
| 101 |
|
|
sc_run_aux <= '0';
|
| 102 |
|
|
mon_write_address <= std_logic_vector(to_unsigned(LA_MEM_FIRST_ADDR, LA_MEM_ADDRESS_BITS));
|
| 103 |
|
|
bt_queue_tail_address <= (others => '0');
|
| 104 |
|
|
bt_cycled <= '0';
|
| 105 |
|
|
mon_samples_after_trigger <= (others => '0');
|
| 106 |
|
|
mon_clones_nr <= ((LA_IDENTICAL_SAMPLES_BITS-1) downto 1 => '0', others => '1');
|
| 107 |
|
|
elsif (rising_edge(clk)) then
|
| 108 |
|
|
mon_state <= next_mon_state;
|
| 109 |
|
|
sc_run_aux <= next_sc_run_aux;
|
| 110 |
|
|
mon_write_address <= next_mon_write_address;
|
| 111 |
|
|
bt_queue_tail_address <= next_bt_queue_tail_address;
|
| 112 |
|
|
bt_cycled <= next_bt_cycled;
|
| 113 |
|
|
mon_samples_after_trigger <= next_mon_samples_after_trigger;
|
| 114 |
|
|
mon_clones_nr <= next_mon_clones_nr;
|
| 115 |
|
|
end if;
|
| 116 |
|
|
end process;
|
| 117 |
|
|
|
| 118 |
|
|
-- continuous assignments
|
| 119 |
|
|
one_plus_mon_write_address <=
|
| 120 |
|
|
std_logic_vector(to_unsigned(to_integer(unsigned(mon_write_address)) + 1, LA_MEM_ADDRESS_BITS));
|
| 121 |
|
|
oneplus_mon_clones_nr <=
|
| 122 |
|
|
std_logic_vector(to_unsigned(to_integer(unsigned(mon_clones_nr)) + 1, LA_IDENTICAL_SAMPLES_BITS));
|
| 123 |
|
|
data_in_changed <= '1' when ((mon_current_data_in and LA_TRACE_MASK) /= (mon_old_data_in and LA_TRACE_MASK)) else '0';
|
| 124 |
|
|
last_mem_addr_before_trigger <=
|
| 125 |
|
|
'1' when (to_integer(unsigned(mon_write_address)) = LA_MEM_LAST_ADDR_BEFORE_TRIGGER) else '0';
|
| 126 |
|
|
not_maximum_mon_clones_nr <=
|
| 127 |
|
|
'1' when (to_integer(unsigned(mon_clones_nr)) < LA_MAX_IDENTICAL_SAMPLES) else '0';
|
| 128 |
|
|
sc_run <= sc_run_aux;
|
| 129 |
|
|
|
| 130 |
|
|
-- state machine
|
| 131 |
|
|
comb_logic: process(mon_state, sys_run_reg, user_run, ack_sc_run, sc_done, sc_run_aux,
|
| 132 |
|
|
mon_write_address, bt_queue_tail_address, bt_cycled, mon_samples_after_trigger,
|
| 133 |
|
|
mon_current_data_in, mon_old_data_in, mon_clones_nr,
|
| 134 |
|
|
data_in_changed, oneplus_mon_clones_nr, one_plus_mon_write_address,
|
| 135 |
|
|
not_maximum_mon_clones_nr, last_mem_addr_before_trigger)
|
| 136 |
|
|
begin
|
| 137 |
|
|
-- implicit
|
| 138 |
|
|
next_mon_state <= mon_state;
|
| 139 |
|
|
next_sc_run_aux <= sc_run_aux;
|
| 140 |
|
|
next_mon_write_address <= mon_write_address;
|
| 141 |
|
|
next_bt_queue_tail_address <= bt_queue_tail_address;
|
| 142 |
|
|
next_bt_cycled <= bt_cycled;
|
| 143 |
|
|
next_mon_samples_after_trigger <= mon_samples_after_trigger;
|
| 144 |
|
|
next_mon_clones_nr <= mon_clones_nr;
|
| 145 |
|
|
mem_port_A_address <= (others => '0');
|
| 146 |
|
|
mem_port_A_data_in <= (others => '0');
|
| 147 |
|
|
mem_port_A_wen <= '0';
|
| 148 |
|
|
case mon_state is
|
| 149 |
|
|
when MON_STATE_IDLE =>
|
| 150 |
|
|
next_bt_cycled <= '0';
|
| 151 |
|
|
if((sys_run_reg = '1') or (user_run = '1')) then
|
| 152 |
|
|
if(user_run = '1') then
|
| 153 |
|
|
next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 154 |
|
|
next_mon_state <= MON_STATE_DO_MEM_CLEAN;
|
| 155 |
|
|
else
|
| 156 |
|
|
-- mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN
|
| 157 |
|
|
-- we share the same clock as memory.
|
| 158 |
|
|
mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 159 |
|
|
mem_port_A_data_in <=
|
| 160 |
|
|
std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
|
| 161 |
|
|
--{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in};
|
| 162 |
|
|
mem_port_A_wen <= '1';
|
| 163 |
|
|
next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 164 |
|
|
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
|
| 165 |
|
|
next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
|
| 166 |
|
|
end if;
|
| 167 |
|
|
else
|
| 168 |
|
|
next_mon_state <= MON_STATE_IDLE;
|
| 169 |
|
|
end if;
|
| 170 |
|
|
when MON_STATE_DO_MEM_CLEAN =>
|
| 171 |
|
|
mem_port_A_address <= mon_write_address;
|
| 172 |
|
|
mem_port_A_data_in <= LA_MEM_EMPTY_SLOT;
|
| 173 |
|
|
mem_port_A_wen <= '1';
|
| 174 |
|
|
if(to_integer(unsigned(mon_write_address)) < LA_MEM_LAST_ADDR) then
|
| 175 |
|
|
next_mon_write_address <= std_logic_vector(to_unsigned(to_integer(unsigned(mon_write_address)) + 1,
|
| 176 |
|
|
LA_MEM_ADDRESS_BITS));
|
| 177 |
|
|
next_mon_state <= MON_STATE_DO_MEM_CLEAN;
|
| 178 |
|
|
else
|
| 179 |
|
|
-- at the new posedge clock, will clean memory at its last address
|
| 180 |
|
|
next_mon_state <= MON_STATE_PREPARE_RUN;
|
| 181 |
|
|
end if;
|
| 182 |
|
|
when MON_STATE_PREPARE_RUN =>
|
| 183 |
|
|
-- mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN
|
| 184 |
|
|
-- we share the same clock as memory.
|
| 185 |
|
|
mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 186 |
|
|
mem_port_A_data_in <=
|
| 187 |
|
|
std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
|
| 188 |
|
|
--{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in};
|
| 189 |
|
|
mem_port_A_wen <= '1';
|
| 190 |
|
|
next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 191 |
|
|
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
|
| 192 |
|
|
next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
|
| 193 |
|
|
when MON_STATE_WAIT_TRIGGER_MATCH =>
|
| 194 |
|
|
-- circular queue
|
| 195 |
|
|
if((mon_current_data_in and LA_TRIGGER_MASK) /= (LA_TRIGGER_VALUE and LA_TRIGGER_MASK)) then
|
| 196 |
|
|
next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
|
| 197 |
|
|
mem_port_A_wen <= '1';
|
| 198 |
|
|
if(data_in_changed = '1') then
|
| 199 |
|
|
if(last_mem_addr_before_trigger = '1') then
|
| 200 |
|
|
mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 201 |
|
|
else
|
| 202 |
|
|
mem_port_A_address <= one_plus_mon_write_address;
|
| 203 |
|
|
end if;
|
| 204 |
|
|
else
|
| 205 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 206 |
|
|
mem_port_A_address <= mon_write_address;
|
| 207 |
|
|
else
|
| 208 |
|
|
if(last_mem_addr_before_trigger = '1') then
|
| 209 |
|
|
mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 210 |
|
|
else
|
| 211 |
|
|
mem_port_A_address <= one_plus_mon_write_address;
|
| 212 |
|
|
end if;
|
| 213 |
|
|
end if;
|
| 214 |
|
|
end if;
|
| 215 |
|
|
if(data_in_changed = '1') then
|
| 216 |
|
|
mem_port_A_data_in <=
|
| 217 |
|
|
std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
|
| 218 |
|
|
--{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in}
|
| 219 |
|
|
else
|
| 220 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 221 |
|
|
mem_port_A_data_in <= mon_clones_nr & mon_current_data_in;
|
| 222 |
|
|
else
|
| 223 |
|
|
mem_port_A_data_in <=
|
| 224 |
|
|
std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
|
| 225 |
|
|
-- {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in}
|
| 226 |
|
|
end if;
|
| 227 |
|
|
end if;
|
| 228 |
|
|
if(data_in_changed = '1') then
|
| 229 |
|
|
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
|
| 230 |
|
|
else
|
| 231 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 232 |
|
|
next_mon_clones_nr <= oneplus_mon_clones_nr;
|
| 233 |
|
|
else
|
| 234 |
|
|
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
|
| 235 |
|
|
end if;
|
| 236 |
|
|
end if;
|
| 237 |
|
|
if(data_in_changed = '1') then
|
| 238 |
|
|
if(last_mem_addr_before_trigger = '1') then
|
| 239 |
|
|
next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 240 |
|
|
else
|
| 241 |
|
|
next_mon_write_address <= one_plus_mon_write_address;
|
| 242 |
|
|
end if;
|
| 243 |
|
|
else
|
| 244 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 245 |
|
|
next_mon_write_address <= mon_write_address;
|
| 246 |
|
|
else
|
| 247 |
|
|
if(last_mem_addr_before_trigger = '1') then
|
| 248 |
|
|
next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
|
| 249 |
|
|
else
|
| 250 |
|
|
next_mon_write_address <= one_plus_mon_write_address;
|
| 251 |
|
|
end if;
|
| 252 |
|
|
end if;
|
| 253 |
|
|
end if;
|
| 254 |
|
|
if(bt_cycled /= '1') then
|
| 255 |
|
|
if(((data_in_changed = '1') and (last_mem_addr_before_trigger = '1')) or
|
| 256 |
|
|
((data_in_changed = '0') and (not_maximum_mon_clones_nr = '0') and (last_mem_addr_before_trigger = '1'))) then
|
| 257 |
|
|
next_bt_cycled <= '1';
|
| 258 |
|
|
end if;
|
| 259 |
|
|
end if;
|
| 260 |
|
|
else
|
| 261 |
|
|
-- trigger matched
|
| 262 |
|
|
next_mon_state <= MON_STATE_AFTER_TRIGGER;
|
| 263 |
|
|
mem_port_A_address <= LA_TRIGGER_MATCH_MEM_ADDR_SLV;
|
| 264 |
|
|
mem_port_A_data_in <=
|
| 265 |
|
|
std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
|
| 266 |
|
|
-- {{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1}, mon_current_data_in};
|
| 267 |
|
|
mem_port_A_wen <= '1';
|
| 268 |
|
|
next_mon_write_address <= LA_TRIGGER_MATCH_MEM_ADDR_SLV;
|
| 269 |
|
|
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
|
| 270 |
|
|
next_bt_queue_tail_address <= mon_write_address;
|
| 271 |
|
|
next_mon_samples_after_trigger <= std_logic_vector(to_unsigned(1, LA_MAX_SAMPLES_AFTER_TRIGGER_BITS));
|
| 272 |
|
|
end if;
|
| 273 |
|
|
when MON_STATE_AFTER_TRIGGER =>
|
| 274 |
|
|
if((to_integer(unsigned(mon_samples_after_trigger)) < LA_MAX_SAMPLES_AFTER_TRIGGER) and
|
| 275 |
|
|
(to_integer(unsigned(mon_write_address)) < LA_MEM_LAST_ADDR)) then
|
| 276 |
|
|
mem_port_A_wen <= '1';
|
| 277 |
|
|
if(data_in_changed = '1') then
|
| 278 |
|
|
mem_port_A_address <= one_plus_mon_write_address;
|
| 279 |
|
|
else
|
| 280 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 281 |
|
|
mem_port_A_address <= mon_write_address;
|
| 282 |
|
|
else
|
| 283 |
|
|
mem_port_A_address <= one_plus_mon_write_address;
|
| 284 |
|
|
end if;
|
| 285 |
|
|
end if;
|
| 286 |
|
|
if(data_in_changed = '1') then
|
| 287 |
|
|
mem_port_A_data_in <=
|
| 288 |
|
|
std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
|
| 289 |
|
|
--{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} :
|
| 290 |
|
|
else
|
| 291 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 292 |
|
|
mem_port_A_data_in <= mon_clones_nr & mon_current_data_in;
|
| 293 |
|
|
else
|
| 294 |
|
|
mem_port_A_data_in <=
|
| 295 |
|
|
std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
|
| 296 |
|
|
--{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in});
|
| 297 |
|
|
end if;
|
| 298 |
|
|
end if;
|
| 299 |
|
|
if(data_in_changed = '1') then
|
| 300 |
|
|
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
|
| 301 |
|
|
else
|
| 302 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 303 |
|
|
next_mon_clones_nr <= oneplus_mon_clones_nr;
|
| 304 |
|
|
else
|
| 305 |
|
|
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
|
| 306 |
|
|
end if;
|
| 307 |
|
|
end if;
|
| 308 |
|
|
if(data_in_changed = '1') then
|
| 309 |
|
|
next_mon_write_address <= one_plus_mon_write_address;
|
| 310 |
|
|
else
|
| 311 |
|
|
if(not_maximum_mon_clones_nr = '1') then
|
| 312 |
|
|
next_mon_write_address <= mon_write_address;
|
| 313 |
|
|
else
|
| 314 |
|
|
next_mon_write_address <= one_plus_mon_write_address;
|
| 315 |
|
|
end if;
|
| 316 |
|
|
end if;
|
| 317 |
|
|
next_mon_samples_after_trigger <=
|
| 318 |
|
|
std_logic_vector(to_unsigned(to_integer(unsigned(mon_samples_after_trigger)+1),
|
| 319 |
|
|
LA_MAX_SAMPLES_AFTER_TRIGGER_BITS));
|
| 320 |
|
|
next_mon_state <= MON_STATE_AFTER_TRIGGER;
|
| 321 |
|
|
else
|
| 322 |
|
|
mem_port_A_wen <= '0';
|
| 323 |
|
|
if (to_integer(unsigned(mon_write_address)) < LA_MEM_LAST_ADDR) then
|
| 324 |
|
|
next_mon_write_address <= one_plus_mon_write_address;
|
| 325 |
|
|
next_mon_state <= MON_STATE_CLEAN_REMAINING_MEMORY1;
|
| 326 |
|
|
else
|
| 327 |
|
|
next_mon_state <= MON_STATE_CLEAN_REMAINING_MEMORY2;
|
| 328 |
|
|
end if;
|
| 329 |
|
|
end if;
|
| 330 |
|
|
|
| 331 |
|
|
when MON_STATE_CLEAN_REMAINING_MEMORY1 =>
|
| 332 |
|
|
if(to_integer(unsigned(mon_write_address)) < LA_MEM_LAST_ADDR) then
|
| 333 |
|
|
mem_port_A_data_in <= LA_MEM_EMPTY_SLOT;
|
| 334 |
|
|
mem_port_A_wen <= '1';
|
| 335 |
|
|
mem_port_A_address <= mon_write_address;
|
| 336 |
|
|
next_mon_write_address <= one_plus_mon_write_address;
|
| 337 |
|
|
else
|
| 338 |
|
|
mem_port_A_wen <= '0';
|
| 339 |
|
|
if(bt_cycled = '1') then
|
| 340 |
|
|
next_mon_state <= MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS;
|
| 341 |
|
|
else
|
| 342 |
|
|
next_mon_write_address <= std_logic_vector
|
| 343 |
|
|
(to_unsigned(to_integer(unsigned(bt_queue_tail_address)) + 1, LA_MEM_ADDRESS_BITS));
|
| 344 |
|
|
next_mon_state <= MON_STATE_CLEAN_REMAINING_MEMORY2;
|
| 345 |
|
|
end if;
|
| 346 |
|
|
end if;
|
| 347 |
|
|
|
| 348 |
|
|
when MON_STATE_CLEAN_REMAINING_MEMORY2 =>
|
| 349 |
|
|
if(to_integer(unsigned(mon_write_address)) < LA_TRIGGER_MATCH_MEM_ADDR) then
|
| 350 |
|
|
mem_port_A_data_in <= LA_MEM_EMPTY_SLOT;
|
| 351 |
|
|
mem_port_A_wen <= '1';
|
| 352 |
|
|
mem_port_A_address <= mon_write_address;
|
| 353 |
|
|
next_mon_write_address <= one_plus_mon_write_address;
|
| 354 |
|
|
else
|
| 355 |
|
|
mem_port_A_wen <= '0';
|
| 356 |
|
|
next_mon_state <= MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS;
|
| 357 |
|
|
end if;
|
| 358 |
|
|
|
| 359 |
|
|
when MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS =>
|
| 360 |
|
|
-- Save bt_queue_tail_address
|
| 361 |
|
|
mem_port_A_address <= LA_BT_QUEUE_TAIL_ADDRESS_SLV;
|
| 362 |
|
|
mem_port_A_data_in <=
|
| 363 |
|
|
std_logic_vector(to_unsigned(0, LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS)) & bt_queue_tail_address;
|
| 364 |
|
|
-- {{(LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS){1'b0}}, bt_queue_tail_address};
|
| 365 |
|
|
mem_port_A_wen <= '1';
|
| 366 |
|
|
next_mon_state <= MON_STATE_SC_RUN;
|
| 367 |
|
|
when MON_STATE_SC_RUN =>
|
| 368 |
|
|
next_mon_state <= MON_STATE_WAIT_SC_DONE;
|
| 369 |
|
|
next_sc_run_aux <= '1';
|
| 370 |
|
|
when MON_STATE_WAIT_SC_DONE =>
|
| 371 |
|
|
-- sc_run must already be 1.
|
| 372 |
|
|
if(ack_sc_run = '1') then
|
| 373 |
|
|
next_sc_run_aux <= '0';
|
| 374 |
|
|
end if;
|
| 375 |
|
|
if((sc_run_aux = '0') and (sc_done = '1')) then
|
| 376 |
|
|
next_mon_state <= MON_STATE_IDLE;
|
| 377 |
|
|
else
|
| 378 |
|
|
next_mon_state <= MON_STATE_WAIT_SC_DONE;
|
| 379 |
|
|
end if;
|
| 380 |
|
|
when others =>
|
| 381 |
|
|
-- this is forced by the vhdl compiler
|
| 382 |
|
|
end case;
|
| 383 |
|
|
end process;
|
| 384 |
|
|
|
| 385 |
|
|
end monitor_of_verifla_arch;
|
