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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_alu.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.13  2004/05/09 19:49:03  lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.12  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11  2003/04/24 00:16:07  lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.10  2002/09/08 05:52:16  lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.9  2002/09/07 19:16:10  lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.8  2002/09/07 05:42:02  lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6  2002/03/29 16:40:10  lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5  2002/03/29 16:33:59  lampret
// Added again just recently removed full_case directive
//
// Revision 1.4  2002/03/29 15:16:53  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu_cm2(
                clk_i_cml_1,
 
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
 
input clk_i_cml_1;
reg [ 32 - 1 : 0 ] a_cml_1;
reg [ 32 - 1 : 0 ] b_cml_1;
reg [ 4 - 1 : 0 ] alu_op_cml_1;
reg [ 4 - 1 : 0 ] comp_op_cml_1;
reg [ 32 : 0 ] cy_sum_result_sum_cml_1;
reg [ 32 : 0 ] cy_csum_result_csum_cml_1;
 
 
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
reg                             cyforw;
 
//
// Combinatorial logic
//
 
// SynEDA CoreMultiplier
// assignment(s): comp_a
// replace(s): a, comp_op
assign comp_a = {a_cml_1[width-1] ^ comp_op_cml_1[3] , a_cml_1[width-2:0]};
 
// SynEDA CoreMultiplier
// assignment(s): comp_b
// replace(s): b, comp_op
assign comp_b = {b_cml_1[width-1] ^ comp_op_cml_1[3] , b_cml_1[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
wire    [width:0]                cy_sum_result_sum;
//assign {cy_sum, result_sum} = a + b;
assign cy_sum_result_sum = a + b;
 
// SynEDA CoreMultiplier
// assignment(s): cy_sum
// replace(s): cy_sum_result_sum
assign cy_sum = cy_sum_result_sum_cml_1[32];
assign result_sum = cy_sum_result_sum[31:0];
`ifdef OR1200_IMPL_ADDC
wire    [width:0]                cy_csum_result_csum;
//assign {cy_csum, result_csum} = a + b + {32'd0, carry};
assign cy_csum_result_csum = a + b + {32'd0, carry};
 
// SynEDA CoreMultiplier
// assignment(s): cy_csum
// replace(s): cy_csum_result_csum
assign cy_csum = cy_csum_result_csum_cml_1[32];
assign result_csum = cy_csum_result_csum[31:0];
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
`else
        casex (alu_op)          // synopsys full_case parallel_case
`endif
    `OR1200_ALUOP_FF1: begin
        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
    end
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
                end
`endif
    `OR1200_ALUOP_CMOV: begin
        result = flag ? a : b;
    end
 
`ifdef OR1200_CASE_DEFAULT
    default: begin
`else
    `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
    begin
`endif
      result=result_and;
    end
        endcase
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casex (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casex (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
 
// SynEDA CoreMultiplier
// assignment(s): flagforw
// replace(s): alu_op
always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                end
                default: begin
                        flagforw = 1'b0;
                end
        endcase
end
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flag_we = 1'b1;
                end
                default: begin
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
 
// SynEDA CoreMultiplier
// assignment(s): cyforw
// replace(s): alu_op
always @(alu_op_cml_1 or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                end
        endcase
end
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op_cml_1 or a_eq_b or a_lt_b) begin
        case(comp_op_cml_1[2:0]) // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
 
// SynEDA CoreMultiplier
// assignment(s): flagcomp
// replace(s): comp_op
always @(comp_op_cml_1 or comp_a or comp_b) begin
        case(comp_op_cml_1[2:0]) // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
 
always @ (posedge clk_i_cml_1) begin
a_cml_1 <= a;
b_cml_1 <= b;
alu_op_cml_1 <= alu_op;
comp_op_cml_1 <= comp_op;
cy_sum_result_sum_cml_1 <= cy_sum_result_sum;
cy_csum_result_csum_cml_1 <= cy_csum_result_csum;
end
endmodule
 

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_alu.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.14 2004/06/08 18:17:36 lampret`
48			`// Non-functional changes. Coding style fixes.`
49			`//`
50			`// Revision 1.13 2004/05/09 19:49:03 lampret`
51			`// Added some l.cust5 custom instructions as example`
52			`//`
53			`// Revision 1.12 2004/04/05 08:29:57 lampret`
54			`// Merged branch_qmem into main tree.`
55			`//`
56			`// Revision 1.11 2003/04/24 00:16:07 lampret`
57			`// No functional changes. Added defines to disable implementation of multiplier/MAC`
58			`//`
59			`// Revision 1.10 2002/09/08 05:52:16 lampret`
60			`// Added optional l.div/l.divu insns. By default they are disabled.`
61			`//`
62			`// Revision 1.9 2002/09/07 19:16:10 lampret`
63			`// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].`
64			`//`
65			`// Revision 1.8 2002/09/07 05:42:02 lampret`
66			`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
67			`//`
68			`// Revision 1.7 2002/09/03 22:28:21 lampret`
69			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
70			`//`
71			`// Revision 1.6 2002/03/29 16:40:10 lampret`
72			`// Added a directive to ignore signed division variables that are only used in simulation.`
73			`//`
74			`// Revision 1.5 2002/03/29 16:33:59 lampret`
75			`// Added again just recently removed full_case directive`
76			`//`
77			`// Revision 1.4 2002/03/29 15:16:53 lampret`
78			`// Some of the warnings fixed.`
79			`//`
80			`// Revision 1.3 2002/01/28 01:15:59 lampret`
81			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
82			`//`
83			`// Revision 1.2 2002/01/14 06:18:22 lampret`
84			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
85			`//`
86			`// Revision 1.1 2002/01/03 08:16:15 lampret`
87			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
88			`//`
89			`// Revision 1.10 2001/11/12 01:45:40 lampret`
90			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
91			`//`
92			`// Revision 1.9 2001/10/21 17:57:16 lampret`
93			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
94			`//`
95			`// Revision 1.8 2001/10/19 23:28:45 lampret`
96			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
97			`//`
98			`// Revision 1.7 2001/10/14 13:12:09 lampret`
99			`// MP3 version.`
100			`//`
101			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
102			`// no message`
103			`//`
104			`// Revision 1.2 2001/08/09 13:39:33 lampret`
105			`// Major clean-up.`
106			`//`
107			`// Revision 1.1 2001/07/20 00:46:03 lampret`
108			`// Development version of RTL. Libraries are missing.`
109			`//`
110			`//`
111
112			`// synopsys translate_off`
113			`include "timescale.v"
114			`// synopsys translate_on`
115			`include "or1200_defines.v"
116
117			`module or1200_alu_cm2(`
118			`clk_i_cml_1,`
119
120			`a, b, mult_mac_result, macrc_op,`
121			`alu_op, shrot_op, comp_op,`
122			`cust5_op, cust5_limm,`
123			`result, flagforw, flag_we,`
124			`cyforw, cy_we, carry, flag`
125			`);`
126
127
128			`input clk_i_cml_1;`
129			`reg [ 32 - 1 : 0 ] a_cml_1;`
130			`reg [ 32 - 1 : 0 ] b_cml_1;`
131			`reg [ 4 - 1 : 0 ] alu_op_cml_1;`
132			`reg [ 4 - 1 : 0 ] comp_op_cml_1;`
133			`reg [ 32 : 0 ] cy_sum_result_sum_cml_1;`
134			`reg [ 32 : 0 ] cy_csum_result_csum_cml_1;`
135
136
137
138			parameter width = `OR1200_OPERAND_WIDTH;
139
140			`//`
141			`// I/O`
142			`//`
143			`input [width-1:0] a;`
144			`input [width-1:0] b;`
145			`input [width-1:0] mult_mac_result;`
146			`input macrc_op;`
147			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
148			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
149			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
150			`input [4:0] cust5_op;`
151			`input [5:0] cust5_limm;`
152			`output [width-1:0] result;`
153			`output flagforw;`
154			`output flag_we;`
155			`output cyforw;`
156			`output cy_we;`
157			`input carry;`
158			`input flag;`
159
160			`//`
161			`// Internal wires and regs`
162			`//`
163			`reg [width-1:0] result;`
164			`reg [width-1:0] shifted_rotated;`
165			`reg [width-1:0] result_cust5;`
166			`reg flagforw;`
167			`reg flagcomp;`
168			`reg flag_we;`
169			`reg cy_we;`
170			`wire [width-1:0] comp_a;`
171			`wire [width-1:0] comp_b;`
172			`ifdef OR1200_IMPL_ALU_COMP1
173			`wire a_eq_b;`
174			`wire a_lt_b;`
175			`endif
176			`wire [width-1:0] result_sum;`
177			`ifdef OR1200_IMPL_ADDC
178			`wire [width-1:0] result_csum;`
179			`wire cy_csum;`
180			`endif
181			`wire [width-1:0] result_and;`
182			`wire cy_sum;`
183			`reg cyforw;`
184
185			`//`
186			`// Combinatorial logic`
187			`//`
188
189			`// SynEDA CoreMultiplier`
190			`// assignment(s): comp_a`
191			`// replace(s): a, comp_op`
192			`assign comp_a = {a_cml_1[width-1] ^ comp_op_cml_1[3] , a_cml_1[width-2:0]};`
193
194			`// SynEDA CoreMultiplier`
195			`// assignment(s): comp_b`
196			`// replace(s): b, comp_op`
197			`assign comp_b = {b_cml_1[width-1] ^ comp_op_cml_1[3] , b_cml_1[width-2:0]};`
198			`ifdef OR1200_IMPL_ALU_COMP1
199			`assign a_eq_b = (comp_a == comp_b);`
200			`assign a_lt_b = (comp_a < comp_b);`
201			`endif
202			`wire [width:0] cy_sum_result_sum;`
203			`//assign {cy_sum, result_sum} = a + b;`
204			`assign cy_sum_result_sum = a + b;`
205
206			`// SynEDA CoreMultiplier`
207			`// assignment(s): cy_sum`
208			`// replace(s): cy_sum_result_sum`
209			`assign cy_sum = cy_sum_result_sum_cml_1[32];`
210			`assign result_sum = cy_sum_result_sum[31:0];`
211			`ifdef OR1200_IMPL_ADDC
212			`wire [width:0] cy_csum_result_csum;`
213			`//assign {cy_csum, result_csum} = a + b + {32'd0, carry};`
214			`assign cy_csum_result_csum = a + b + {32'd0, carry};`
215
216			`// SynEDA CoreMultiplier`
217			`// assignment(s): cy_csum`
218			`// replace(s): cy_csum_result_csum`
219			`assign cy_csum = cy_csum_result_csum_cml_1[32];`
220			`assign result_csum = cy_csum_result_csum[31:0];`
221			`endif
222			`assign result_and = a & b;`
223
224			`//`
225			`// Simulation check for bad ALU behavior`
226			`//`
227			`ifdef OR1200_WARNINGS
228			`// synopsys translate_off`
229			`always @(result) begin`
230			`if (result === 32'bx)`
231			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
232			`end`
233			`// synopsys translate_on`
234			`endif
235
236			`//`
237			`// Central part of the ALU`
238			`//`
239			`always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin`
240			`ifdef OR1200_CASE_DEFAULT
241			`casex (alu_op) // synopsys parallel_case`
242			`else
243			`casex (alu_op) // synopsys full_case parallel_case`
244			`endif
245			`OR1200_ALUOP_FF1: begin
246			`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
247			`end`
248			`OR1200_ALUOP_CUST5 : begin
249			`result = result_cust5;`
250			`end`
251			`OR1200_ALUOP_SHROT : begin
252			`result = shifted_rotated;`
253			`end`
254			`OR1200_ALUOP_ADD : begin
255			`result = result_sum;`
256			`end`
257			`ifdef OR1200_IMPL_ADDC
258			`OR1200_ALUOP_ADDC : begin
259			`result = result_csum;`
260			`end`
261			`endif
262			`OR1200_ALUOP_SUB : begin
263			`result = a - b;`
264			`end`
265			`OR1200_ALUOP_XOR : begin
266			`result = a ^ b;`
267			`end`
268			`OR1200_ALUOP_OR : begin
269			`result = a \| b;`
270			`end`
271			`OR1200_ALUOP_IMM : begin
272			`result = b;`
273			`end`
274			`OR1200_ALUOP_MOVHI : begin
275			`if (macrc_op) begin`
276			`result = mult_mac_result;`
277			`end`
278			`else begin`
279			`result = b << 16;`
280			`end`
281			`end`
282			`ifdef OR1200_MULT_IMPLEMENTED
283			`ifdef OR1200_IMPL_DIV
284			`OR1200_ALUOP_DIV,
285			`OR1200_ALUOP_DIVU,
286			`endif
287			`OR1200_ALUOP_MUL : begin
288			`result = mult_mac_result;`
289			`end`
290			`endif
291			`OR1200_ALUOP_CMOV: begin
292			`result = flag ? a : b;`
293			`end`
294
295			`ifdef OR1200_CASE_DEFAULT
296			`default: begin`
297			`else
298			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
299			`begin`
300			`endif
301			`result=result_and;`
302			`end`
303			`endcase`
304			`end`
305
306			`//`
307			`// l.cust5 custom instructions`
308			`//`
309			`// Examples for move byte, set bit and clear bit`
310			`//`
311			`always @(cust5_op or cust5_limm or a or b) begin`
312			`casex (cust5_op) // synopsys parallel_case`
313			`5'h1 : begin`
314			`casex (cust5_limm[1:0])`
315			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
316			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
317			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
318			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
319			`endcase`
320			`end`
321			`5'h2 :`
322			`result_cust5 = a \| (1 << cust5_limm);`
323			`5'h3 :`
324			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
325			`//`
326			`// * Put here new l.cust5 custom instructions *`
327			`//`
328			`default: begin`
329			`result_cust5 = a;`
330			`end`
331			`endcase`
332			`end`
333
334			`//`
335			`// Generate flag and flag write enable`
336			`//`
337
338			`// SynEDA CoreMultiplier`
339			`// assignment(s): flagforw`
340			`// replace(s): alu_op`
341			`always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin`
342			`casex (alu_op_cml_1) // synopsys parallel_case`
343			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
344			`OR1200_ALUOP_ADD : begin
345			`flagforw = (result_sum == 32'h0000_0000);`
346			`end`
347			`ifdef OR1200_IMPL_ADDC
348			`OR1200_ALUOP_ADDC : begin
349			`flagforw = (result_csum == 32'h0000_0000);`
350			`end`
351			`endif
352			`OR1200_ALUOP_AND: begin
353			`flagforw = (result_and == 32'h0000_0000);`
354			`end`
355			`endif
356			`OR1200_ALUOP_COMP: begin
357			`flagforw = flagcomp;`
358			`end`
359			`default: begin`
360			`flagforw = 1'b0;`
361			`end`
362			`endcase`
363			`end`
364			`always @(alu_op or result_sum or result_and or flagcomp) begin`
365			`casex (alu_op) // synopsys parallel_case`
366			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
367			`OR1200_ALUOP_ADD : begin
368			`flag_we = 1'b1;`
369			`end`
370			`ifdef OR1200_IMPL_ADDC
371			`OR1200_ALUOP_ADDC : begin
372			`flag_we = 1'b1;`
373			`end`
374			`endif
375			`OR1200_ALUOP_AND: begin
376			`flag_we = 1'b1;`
377			`end`
378			`endif
379			`OR1200_ALUOP_COMP: begin
380			`flag_we = 1'b1;`
381			`end`
382			`default: begin`
383			`flag_we = 1'b0;`
384			`end`
385			`endcase`
386			`end`
387
388			`//`
389			`// Generate SR[CY] write enable`
390			`//`
391
392			`// SynEDA CoreMultiplier`
393			`// assignment(s): cyforw`
394			`// replace(s): alu_op`
395			`always @(alu_op_cml_1 or cy_sum`
396			`ifdef OR1200_IMPL_ADDC
397			`or cy_csum`
398			`endif
399			`) begin`
400			`casex (alu_op_cml_1) // synopsys parallel_case`
401			`ifdef OR1200_IMPL_CY
402			`OR1200_ALUOP_ADD : begin
403			`cyforw = cy_sum;`
404			`end`
405			`ifdef OR1200_IMPL_ADDC
406			`OR1200_ALUOP_ADDC: begin
407			`cyforw = cy_csum;`
408			`end`
409			`endif
410			`endif
411			`default: begin`
412			`cyforw = 1'b0;`
413			`end`
414			`endcase`
415			`end`
416			`always @(alu_op or cy_sum`
417			`ifdef OR1200_IMPL_ADDC
418			`or cy_csum`
419			`endif
420			`) begin`
421			`casex (alu_op) // synopsys parallel_case`
422			`ifdef OR1200_IMPL_CY
423			`OR1200_ALUOP_ADD : begin
424			`cy_we = 1'b1;`
425			`end`
426			`ifdef OR1200_IMPL_ADDC
427			`OR1200_ALUOP_ADDC: begin
428			`cy_we = 1'b1;`
429			`end`
430			`endif
431			`endif
432			`default: begin`
433			`cy_we = 1'b0;`
434			`end`
435			`endcase`
436			`end`
437
438			`//`
439			`// Shifts and rotation`
440			`//`
441			`always @(shrot_op or a or b) begin`
442			`case (shrot_op) // synopsys parallel_case`
443			`OR1200_SHROTOP_SLL :
444			`shifted_rotated = (a << b[4:0]);`
445			`OR1200_SHROTOP_SRL :
446			`shifted_rotated = (a >> b[4:0]);`
447
448			`ifdef OR1200_IMPL_ALU_ROTATE
449			`OR1200_SHROTOP_ROR :
450			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
451			`endif
452			`default:`
453			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
454			`endcase`
455			`end`
456
457			`//`
458			`// First type of compare implementation`
459			`//`
460			`ifdef OR1200_IMPL_ALU_COMP1
461			`always @(comp_op_cml_1 or a_eq_b or a_lt_b) begin`
462			`case(comp_op_cml_1[2:0]) // synopsys parallel_case`
463			`OR1200_COP_SFEQ:
464			`flagcomp = a_eq_b;`
465			`OR1200_COP_SFNE:
466			`flagcomp = ~a_eq_b;`
467			`OR1200_COP_SFGT:
468			`flagcomp = ~(a_eq_b \| a_lt_b);`
469			`OR1200_COP_SFGE:
470			`flagcomp = ~a_lt_b;`
471			`OR1200_COP_SFLT:
472			`flagcomp = a_lt_b;`
473			`OR1200_COP_SFLE:
474			`flagcomp = a_eq_b \| a_lt_b;`
475			`default:`
476			`flagcomp = 1'b0;`
477			`endcase`
478			`end`
479			`endif
480
481			`//`
482			`// Second type of compare implementation`
483			`//`
484			`ifdef OR1200_IMPL_ALU_COMP2
485
486			`// SynEDA CoreMultiplier`
487			`// assignment(s): flagcomp`
488			`// replace(s): comp_op`
489			`always @(comp_op_cml_1 or comp_a or comp_b) begin`
490			`case(comp_op_cml_1[2:0]) // synopsys parallel_case`
491			`OR1200_COP_SFEQ:
492			`flagcomp = (comp_a == comp_b);`
493			`OR1200_COP_SFNE:
494			`flagcomp = (comp_a != comp_b);`
495			`OR1200_COP_SFGT:
496			`flagcomp = (comp_a > comp_b);`
497			`OR1200_COP_SFGE:
498			`flagcomp = (comp_a >= comp_b);`
499			`OR1200_COP_SFLT:
500			`flagcomp = (comp_a < comp_b);`
501			`OR1200_COP_SFLE:
502			`flagcomp = (comp_a <= comp_b);`
503			`default:`
504			`flagcomp = 1'b0;`
505			`endcase`
506			`end`
507			`endif
508
509
510			`always @ (posedge clk_i_cml_1) begin`
511			`a_cml_1 <= a;`
512			`b_cml_1 <= b;`
513			`alu_op_cml_1 <= alu_op;`
514			`comp_op_cml_1 <= comp_op;`
515			`cy_sum_result_sum_cml_1 <= cy_sum_result_sum;`
516			`cy_csum_result_csum_cml_1 <= cy_csum_result_csum;`
517			`end`
518			`endmodule`
519