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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_du.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's Debug Unit                                         ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Basic OR1200 debug unit.                                    ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - make it smaller and faster                               ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: not supported by cvs2svn $
47 
// Revision 1.11  2005/01/07 09:35:08  andreje
48 
// du_hwbkpt disabled when debug unit not implemented
49 
//
50 
// Revision 1.10  2004/04/05 08:29:57  lampret
51 
// Merged branch_qmem into main tree.
52 
//
53 
// Revision 1.9.4.4  2004/02/11 01:40:11  lampret
54 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
55 
//
56 
// Revision 1.9.4.3  2004/01/18 10:08:00  simons
57 
// Error fixed.
58 
//
59 
// Revision 1.9.4.2  2004/01/17 21:14:14  simons
60 
// Errors fixed.
61 
//
62 
// Revision 1.9.4.1  2004/01/15 06:46:38  markom
63 
// interface to debug changed; no more opselect; stb-ack protocol
64 
//
65 
// Revision 1.9  2003/01/22 03:23:47  lampret
66 
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
67 
//
68 
// Revision 1.8  2002/09/08 19:31:52  lampret
69 
// Fixed a typo, reported by Taylor Su.
70 
//
71 
// Revision 1.7  2002/07/14 22:17:17  lampret
72 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
73 
//
74 
// Revision 1.6  2002/03/14 00:30:24  lampret
75 
// Added alternative for critical path in DU.
76 
//
77 
// Revision 1.5  2002/02/11 04:33:17  lampret
78 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
79 
//
80 
// Revision 1.4  2002/01/28 01:16:00  lampret
81 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
82 
//
83 
// Revision 1.3  2002/01/18 07:56:00  lampret
84 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
85 
//
86 
// Revision 1.2  2002/01/14 06:18:22  lampret
87 
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
88 
//
89 
// Revision 1.1  2002/01/03 08:16:15  lampret
90 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
91 
//
92 
// Revision 1.12  2001/11/30 18:58:00  simons
93 
// Trap insn couses break after exits ex_insn.
94 
//
95 
// Revision 1.11  2001/11/23 08:38:51  lampret
96 
// Changed DSR/DRR behavior and exception detection.
97 
//
98 
// Revision 1.10  2001/11/20 21:25:44  lampret
99 
// Fixed dbg_is_o assignment width.
100 
//
101 
// Revision 1.9  2001/11/20 18:46:14  simons
102 
// Break point bug fixed
103 
//
104 
// Revision 1.8  2001/11/18 08:36:28  lampret
105 
// For GDB changed single stepping and disabled trap exception.
106 
//
107 
// Revision 1.7  2001/10/21 18:09:53  lampret
108 
// Fixed sensitivity list.
109 
//
110 
// Revision 1.6  2001/10/14 13:12:09  lampret
111 
// MP3 version.
112 
//
113 
//
114 
 
115 
// synopsys translate_off
116 
`include "timescale.v"
117 
// synopsys translate_on
118 
`include "or1200_defines.v"
119 
 
120 
//
121 
// Debug unit
122 
//
123 
 
124 
module or1200_du_cm2(
125 
                clk_i_cml_1,
126 
 
127 
        // RISC Internal Interface
128 
        clk, rst,
129 
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
130 
        dcpu_dat_dc, icpu_cycstb_i,
131 
        ex_freeze, branch_op, ex_insn, id_pc,
132 
        spr_dat_npc, rf_dataw,
133 
        du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
134 
        du_read, du_write, du_except, du_hwbkpt,
135 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
136 
 
137 
        // External Debug Interface
138 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
139 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
140 
);
141 
 
142 
 
143 
input clk_i_cml_1;
144 
reg [ 3 - 1 : 0 ] branch_op_cml_1;
145 
reg [ 32 - 1 : 0 ] ex_insn_cml_1;
146 
reg  spr_write_cml_1;
147 
reg [ 32 - 1 : 0 ] spr_addr_cml_1;
148 
reg [ 32 - 1 : 0 ] spr_dat_i_cml_1;
149 
reg [ 1 : 0 ] dbg_is_o_cml_1;
150 
reg  dbg_stb_i_cml_1;
151 
reg  dbg_ack_o_cml_1;
152 
reg [ 24 : 0 ] dmr1_cml_1;
153 
reg [ 14 - 1 : 0 ] dsr_cml_1;
154 
reg [ 13 : 0 ] drr_cml_1;
155 
reg  dbg_bp_r_cml_1;
156 
 
157 
 
158 
 
159 
parameter dw = `OR1200_OPERAND_WIDTH;
160 
parameter aw = `OR1200_OPERAND_WIDTH;
161 
 
162 
//
163 
// I/O
164 
//
165 
 
166 
//
167 
// RISC Internal Interface
168 
//
169 
input                           clk;            // Clock
170 
input                           rst;            // Reset
171 
input                           dcpu_cycstb_i;  // LSU status
172 
input                           dcpu_we_i;      // LSU status
173 
input   [31:0]                   dcpu_adr_i;     // LSU addr
174 
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
175 
input   [31:0]                   dcpu_dat_dc;    // LSU load data
176 
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
177 
input                           ex_freeze;      // EX stage freeze
178 
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
179 
input   [dw-1:0]         ex_insn;        // EX insn
180 
input   [31:0]                   id_pc;          // insn fetch EA
181 
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
182 
input   [31:0]                   rf_dataw;       // ALU result (for trace)
183 
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
184 
output                          du_stall;       // Debug Unit Stall
185 
output  [aw-1:0]         du_addr;        // Debug Unit Address
186 
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
187 
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
188 
output                          du_read;        // Debug Unit Read Enable
189 
output                          du_write;       // Debug Unit Write Enable
190 
input   [12:0]                   du_except;      // Exception masked by DSR
191 
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
192 
input                           spr_cs;         // SPR Chip Select
193 
input                           spr_write;      // SPR Read/Write
194 
input   [aw-1:0]         spr_addr;       // SPR Address
195 
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
196 
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
197 
 
198 
//
199 
// External Debug Interface
200 
//
201 
input                   dbg_stall_i;    // External Stall Input
202 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
203 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
204 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
205 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
206 
output                  dbg_bp_o;       // Breakpoint Output
207 
input                   dbg_stb_i;      // External Address/Data Strobe
208 
input                   dbg_we_i;       // External Write Enable
209 
input   [aw-1:0] dbg_adr_i;      // External Address Input
210 
input   [dw-1:0] dbg_dat_i;      // External Data Input
211 
output  [dw-1:0] dbg_dat_o;      // External Data Output
212 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
213 
 
214 
 
215 
//
216 
// Some connections go directly from the CPU through DU to Debug I/F
217 
//
218 
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
219 
assign dbg_lss_o = 4'b0000;
220 
 
221 
reg     [1:0]                    dbg_is_o;
222 
//
223 
// Show insn activity (temp, must be removed)
224 
//
225 
 
226 
// SynEDA CoreMultiplier
227 
// assignment(s): dbg_is_o
228 
// replace(s): ex_insn, dbg_is_o
229 
always @(posedge clk or posedge rst)
230 
        if (rst)
231 
                dbg_is_o <= #1 2'b00;
232 
        else begin  dbg_is_o <= dbg_is_o_cml_1; if (!ex_freeze &
233 
                ~((ex_insn_cml_1[31:26] == `OR1200_OR32_NOP) & ex_insn_cml_1[16]))
234 
                dbg_is_o <= #1 ~dbg_is_o_cml_1; end
235 
`ifdef UNUSED
236 
assign dbg_is_o = 2'b00;
237 
`endif
238 
`else
239 
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
240 
assign dbg_is_o = {1'b0, icpu_cycstb_i};
241 
`endif
242 
assign dbg_wp_o = 11'b000_0000_0000;
243 
assign dbg_dat_o = du_dat_i;
244 
 
245 
//
246 
// Some connections go directly from Debug I/F through DU to the CPU
247 
//
248 
assign du_stall = dbg_stall_i;
249 
assign du_addr = dbg_adr_i;
250 
assign du_dat_o = dbg_dat_i;
251 
assign du_read = dbg_stb_i && !dbg_we_i;
252 
assign du_write = dbg_stb_i && dbg_we_i;
253 
 
254 
//
255 
// Generate acknowledge -- just delay stb signal
256 
//
257 
reg dbg_ack_o;
258 
 
259 
// SynEDA CoreMultiplier
260 
// assignment(s): dbg_ack_o
261 
// replace(s): dbg_stb_i, dbg_ack_o
262 
always @(posedge clk or posedge rst)
263 
        if (rst)
264 
                dbg_ack_o <= #1 1'b0;
265 
        else begin  dbg_ack_o <= dbg_ack_o_cml_1;
266 
                dbg_ack_o <= #1 dbg_stb_i_cml_1; end
267 
 
268 
`ifdef OR1200_DU_IMPLEMENTED
269 
 
270 
//
271 
// Debug Mode Register 1
272 
//
273 
`ifdef OR1200_DU_DMR1
274 
reg     [24:0]                   dmr1;           // DMR1 implemented
275 
`else
276 
wire    [24:0]                   dmr1;           // DMR1 not implemented
277 
`endif
278 
 
279 
//
280 
// Debug Mode Register 2
281 
//
282 
`ifdef OR1200_DU_DMR2
283 
reg     [23:0]                   dmr2;           // DMR2 implemented
284 
`else
285 
wire    [23:0]                   dmr2;           // DMR2 not implemented
286 
`endif
287 
 
288 
//
289 
// Debug Stop Register
290 
//
291 
`ifdef OR1200_DU_DSR
292 
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
293 
`else
294 
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
295 
`endif
296 
 
297 
//
298 
// Debug Reason Register
299 
//
300 
`ifdef OR1200_DU_DRR
301 
reg     [13:0]                   drr;            // DRR implemented
302 
`else
303 
wire    [13:0]                   drr;            // DRR not implemented
304 
`endif
305 
 
306 
//
307 
// Debug Value Register N
308 
//
309 
`ifdef OR1200_DU_DVR0
310 
reg     [31:0]                   dvr0;
311 
`else
312 
wire    [31:0]                   dvr0;
313 
`endif
314 
 
315 
//
316 
// Debug Value Register N
317 
//
318 
`ifdef OR1200_DU_DVR1
319 
reg     [31:0]                   dvr1;
320 
`else
321 
wire    [31:0]                   dvr1;
322 
`endif
323 
 
324 
//
325 
// Debug Value Register N
326 
//
327 
`ifdef OR1200_DU_DVR2
328 
reg     [31:0]                   dvr2;
329 
`else
330 
wire    [31:0]                   dvr2;
331 
`endif
332 
 
333 
//
334 
// Debug Value Register N
335 
//
336 
`ifdef OR1200_DU_DVR3
337 
reg     [31:0]                   dvr3;
338 
`else
339 
wire    [31:0]                   dvr3;
340 
`endif
341 
 
342 
//
343 
// Debug Value Register N
344 
//
345 
`ifdef OR1200_DU_DVR4
346 
reg     [31:0]                   dvr4;
347 
`else
348 
wire    [31:0]                   dvr4;
349 
`endif
350 
 
351 
//
352 
// Debug Value Register N
353 
//
354 
`ifdef OR1200_DU_DVR5
355 
reg     [31:0]                   dvr5;
356 
`else
357 
wire    [31:0]                   dvr5;
358 
`endif
359 
 
360 
//
361 
// Debug Value Register N
362 
//
363 
`ifdef OR1200_DU_DVR6
364 
reg     [31:0]                   dvr6;
365 
`else
366 
wire    [31:0]                   dvr6;
367 
`endif
368 
 
369 
//
370 
// Debug Value Register N
371 
//
372 
`ifdef OR1200_DU_DVR7
373 
reg     [31:0]                   dvr7;
374 
`else
375 
wire    [31:0]                   dvr7;
376 
`endif
377 
 
378 
//
379 
// Debug Control Register N
380 
//
381 
`ifdef OR1200_DU_DCR0
382 
reg     [7:0]                    dcr0;
383 
`else
384 
wire    [7:0]                    dcr0;
385 
`endif
386 
 
387 
//
388 
// Debug Control Register N
389 
//
390 
`ifdef OR1200_DU_DCR1
391 
reg     [7:0]                    dcr1;
392 
`else
393 
wire    [7:0]                    dcr1;
394 
`endif
395 
 
396 
//
397 
// Debug Control Register N
398 
//
399 
`ifdef OR1200_DU_DCR2
400 
reg     [7:0]                    dcr2;
401 
`else
402 
wire    [7:0]                    dcr2;
403 
`endif
404 
 
405 
//
406 
// Debug Control Register N
407 
//
408 
`ifdef OR1200_DU_DCR3
409 
reg     [7:0]                    dcr3;
410 
`else
411 
wire    [7:0]                    dcr3;
412 
`endif
413 
 
414 
//
415 
// Debug Control Register N
416 
//
417 
`ifdef OR1200_DU_DCR4
418 
reg     [7:0]                    dcr4;
419 
`else
420 
wire    [7:0]                    dcr4;
421 
`endif
422 
 
423 
//
424 
// Debug Control Register N
425 
//
426 
`ifdef OR1200_DU_DCR5
427 
reg     [7:0]                    dcr5;
428 
`else
429 
wire    [7:0]                    dcr5;
430 
`endif
431 
 
432 
//
433 
// Debug Control Register N
434 
//
435 
`ifdef OR1200_DU_DCR6
436 
reg     [7:0]                    dcr6;
437 
`else
438 
wire    [7:0]                    dcr6;
439 
`endif
440 
 
441 
//
442 
// Debug Control Register N
443 
//
444 
`ifdef OR1200_DU_DCR7
445 
reg     [7:0]                    dcr7;
446 
`else
447 
wire    [7:0]                    dcr7;
448 
`endif
449 
 
450 
//
451 
// Debug Watchpoint Counter Register 0
452 
//
453 
`ifdef OR1200_DU_DWCR0
454 
reg     [31:0]                   dwcr0;
455 
`else
456 
wire    [31:0]                   dwcr0;
457 
`endif
458 
 
459 
//
460 
// Debug Watchpoint Counter Register 1
461 
//
462 
`ifdef OR1200_DU_DWCR1
463 
reg     [31:0]                   dwcr1;
464 
`else
465 
wire    [31:0]                   dwcr1;
466 
`endif
467 
 
468 
//
469 
// Internal wires
470 
//
471 
wire                            dmr1_sel;       // DMR1 select
472 
wire                            dmr2_sel;       // DMR2 select
473 
wire                            dsr_sel;        // DSR select
474 
wire                            drr_sel;        // DRR select
475 
wire                            dvr0_sel,
476 
                                dvr1_sel,
477 
                                dvr2_sel,
478 
                                dvr3_sel,
479 
                                dvr4_sel,
480 
                                dvr5_sel,
481 
                                dvr6_sel,
482 
                                dvr7_sel;       // DVR selects
483 
wire                            dcr0_sel,
484 
                                dcr1_sel,
485 
                                dcr2_sel,
486 
                                dcr3_sel,
487 
                                dcr4_sel,
488 
                                dcr5_sel,
489 
                                dcr6_sel,
490 
                                dcr7_sel;       // DCR selects
491 
wire                            dwcr0_sel,
492 
                                dwcr1_sel;      // DWCR selects
493 
reg                             dbg_bp_r;
494 
`ifdef OR1200_DU_HWBKPTS
495 
reg     [31:0]                   match_cond0_ct;
496 
reg     [31:0]                   match_cond1_ct;
497 
reg     [31:0]                   match_cond2_ct;
498 
reg     [31:0]                   match_cond3_ct;
499 
reg     [31:0]                   match_cond4_ct;
500 
reg     [31:0]                   match_cond5_ct;
501 
reg     [31:0]                   match_cond6_ct;
502 
reg     [31:0]                   match_cond7_ct;
503 
reg                             match_cond0_stb;
504 
reg                             match_cond1_stb;
505 
reg                             match_cond2_stb;
506 
reg                             match_cond3_stb;
507 
reg                             match_cond4_stb;
508 
reg                             match_cond5_stb;
509 
reg                             match_cond6_stb;
510 
reg                             match_cond7_stb;
511 
reg                             match0;
512 
reg                             match1;
513 
reg                             match2;
514 
reg                             match3;
515 
reg                             match4;
516 
reg                             match5;
517 
reg                             match6;
518 
reg                             match7;
519 
reg                             wpcntr0_match;
520 
reg                             wpcntr1_match;
521 
reg                             incr_wpcntr0;
522 
reg                             incr_wpcntr1;
523 
reg     [10:0]                   wp;
524 
`endif
525 
wire                            du_hwbkpt;
526 
`ifdef OR1200_DU_READREGS
527 
reg     [31:0]                   spr_dat_o;
528 
`endif
529 
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
530 
`ifdef OR1200_DU_TB_IMPLEMENTED
531 
wire                            tb_enw;
532 
reg     [7:0]                    tb_wadr;
533 
reg [31:0]                       tb_timstmp;
534 
`endif
535 
wire    [31:0]                   tbia_dat_o;
536 
wire    [31:0]                   tbim_dat_o;
537 
wire    [31:0]                   tbar_dat_o;
538 
wire    [31:0]                   tbts_dat_o;
539 
 
540 
//
541 
// DU registers address decoder
542 
//
543 
`ifdef OR1200_DU_DMR1
544 
 
545 
// SynEDA CoreMultiplier
546 
// assignment(s): dmr1_sel
547 
// replace(s): spr_addr
548 
assign dmr1_sel = (spr_cs && (spr_addr_cml_1[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
549 
`endif
550 
`ifdef OR1200_DU_DMR2
551 
assign dmr2_sel = (spr_cs && (spr_addr_cml_1[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
552 
`endif
553 
`ifdef OR1200_DU_DSR
554 
 
555 
// SynEDA CoreMultiplier
556 
// assignment(s): dsr_sel
557 
// replace(s): spr_addr
558 
assign dsr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
559 
`endif
560 
`ifdef OR1200_DU_DRR
561 
 
562 
// SynEDA CoreMultiplier
563 
// assignment(s): drr_sel
564 
// replace(s): spr_addr
565 
assign drr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
566 
`endif
567 
`ifdef OR1200_DU_DVR0
568 
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
569 
`endif
570 
`ifdef OR1200_DU_DVR1
571 
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
572 
`endif
573 
`ifdef OR1200_DU_DVR2
574 
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
575 
`endif
576 
`ifdef OR1200_DU_DVR3
577 
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
578 
`endif
579 
`ifdef OR1200_DU_DVR4
580 
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
581 
`endif
582 
`ifdef OR1200_DU_DVR5
583 
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
584 
`endif
585 
`ifdef OR1200_DU_DVR6
586 
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
587 
`endif
588 
`ifdef OR1200_DU_DVR7
589 
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
590 
`endif
591 
`ifdef OR1200_DU_DCR0
592 
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
593 
`endif
594 
`ifdef OR1200_DU_DCR1
595 
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
596 
`endif
597 
`ifdef OR1200_DU_DCR2
598 
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
599 
`endif
600 
`ifdef OR1200_DU_DCR3
601 
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
602 
`endif
603 
`ifdef OR1200_DU_DCR4
604 
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
605 
`endif
606 
`ifdef OR1200_DU_DCR5
607 
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
608 
`endif
609 
`ifdef OR1200_DU_DCR6
610 
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
611 
`endif
612 
`ifdef OR1200_DU_DCR7
613 
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
614 
`endif
615 
`ifdef OR1200_DU_DWCR0
616 
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
617 
`endif
618 
`ifdef OR1200_DU_DWCR1
619 
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
620 
`endif
621 
 
622 
//
623 
// Decode started exception
624 
//
625 
always @(du_except) begin
626 
        except_stop = 14'b0000_0000_0000;
627 
        casex (du_except)
628 
                13'b1_xxxx_xxxx_xxxx:
629 
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
630 
                13'b0_1xxx_xxxx_xxxx: begin
631 
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
632 
                end
633 
                13'b0_01xx_xxxx_xxxx: begin
634 
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
635 
                end
636 
                13'b0_001x_xxxx_xxxx:
637 
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
638 
                13'b0_0001_xxxx_xxxx: begin
639 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
640 
                end
641 
                13'b0_0000_1xxx_xxxx:
642 
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
643 
                13'b0_0000_01xx_xxxx: begin
644 
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
645 
                end
646 
                13'b0_0000_001x_xxxx: begin
647 
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
648 
                end
649 
                13'b0_0000_0001_xxxx:
650 
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
651 
                13'b0_0000_0000_1xxx:
652 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
653 
                13'b0_0000_0000_01xx: begin
654 
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
655 
                end
656 
                13'b0_0000_0000_001x: begin
657 
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
658 
                end
659 
                13'b0_0000_0000_0001:
660 
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
661 
                default:
662 
                        except_stop = 14'b0000_0000_0000;
663 
        endcase
664 
end
665 
 
666 
//
667 
// dbg_bp_o is registered
668 
//
669 
 
670 
// SynEDA CoreMultiplier
671 
// assignment(s): dbg_bp_o
672 
// replace(s): dbg_bp_r
673 
assign dbg_bp_o = dbg_bp_r_cml_1;
674 
 
675 
//
676 
// Breakpoint activation register
677 
//
678 
 
679 
// SynEDA CoreMultiplier
680 
// assignment(s): dbg_bp_r
681 
// replace(s): branch_op, ex_insn, dmr1, dbg_bp_r
682 
always @(posedge clk or posedge rst)
683 
        if (rst)
684 
                dbg_bp_r <= #1 1'b0;
685 
        else begin  dbg_bp_r <= dbg_bp_r_cml_1; if (!ex_freeze)
686 
                dbg_bp_r <= #1 |except_stop
687 
`ifdef OR1200_DU_DMR1_ST
688 
                        | ~((ex_insn_cml_1[31:26] == `OR1200_OR32_NOP) & ex_insn_cml_1[16]) & dmr1_cml_1[`OR1200_DU_DMR1_ST]
689 
`endif
690 
`ifdef OR1200_DU_DMR1_BT
691 
                        | (branch_op_cml_1 != `OR1200_BRANCHOP_NOP) & dmr1_cml_1[`OR1200_DU_DMR1_BT]
692 
`endif
693 
                        ;
694 
        else
695 
                dbg_bp_r <= #1 |except_stop; end
696 
 
697 
//
698 
// Write to DMR1
699 
//
700 
`ifdef OR1200_DU_DMR1
701 
 
702 
// SynEDA CoreMultiplier
703 
// assignment(s): dmr1
704 
// replace(s): spr_write, spr_dat_i, dmr1
705 
always @(posedge clk or posedge rst)
706 
        if (rst)
707 
                dmr1 <= 25'h000_0000;
708 
        else begin  dmr1 <= dmr1_cml_1; if (dmr1_sel && spr_write_cml_1)
709 
`ifdef OR1200_DU_HWBKPTS
710 
                dmr1 <= #1 spr_dat_i_cml_1[24:0];
711 
`else
712 
                dmr1 <= #1 {1'b0, spr_dat_i_cml_1[23:22], 22'h00_0000}; end
713 
`endif
714 
`else
715 
assign dmr1 = 25'h000_0000;
716 
`endif
717 
 
718 
//
719 
// Write to DMR2
720 
//
721 
`ifdef OR1200_DU_DMR2
722 
always @(posedge clk or posedge rst)
723 
        if (rst)
724 
                dmr2 <= 24'h00_0000;
725 
        else if (dmr2_sel && spr_write)
726 
                dmr2 <= #1 spr_dat_i[23:0];
727 
`else
728 
assign dmr2 = 24'h00_0000;
729 
`endif
730 
 
731 
//
732 
// Write to DSR
733 
//
734 
`ifdef OR1200_DU_DSR
735 
 
736 
// SynEDA CoreMultiplier
737 
// assignment(s): dsr
738 
// replace(s): spr_write, spr_dat_i, dsr
739 
always @(posedge clk or posedge rst)
740 
        if (rst)
741 
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
742 
        else begin  dsr <= dsr_cml_1; if (dsr_sel && spr_write_cml_1)
743 
                dsr <= #1 spr_dat_i_cml_1[`OR1200_DU_DSR_WIDTH-1:0]; end
744 
`else
745 
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
746 
`endif
747 
 
748 
//
749 
// Write to DRR
750 
//
751 
`ifdef OR1200_DU_DRR
752 
 
753 
// SynEDA CoreMultiplier
754 
// assignment(s): drr
755 
// replace(s): spr_write, spr_dat_i, drr
756 
always @(posedge clk or posedge rst)
757 
        if (rst)
758 
                drr <= 14'b0;
759 
        else begin  drr <= drr_cml_1; if (drr_sel && spr_write_cml_1)
760 
                drr <= #1 spr_dat_i_cml_1[13:0];
761 
        else
762 
                drr <= #1 drr_cml_1 | except_stop; end
763 
`else
764 
assign drr = 14'b0;
765 
`endif
766 
 
767 
//
768 
// Write to DVR0
769 
//
770 
`ifdef OR1200_DU_DVR0
771 
always @(posedge clk or posedge rst)
772 
        if (rst)
773 
                dvr0 <= 32'h0000_0000;
774 
        else if (dvr0_sel && spr_write)
775 
                dvr0 <= #1 spr_dat_i[31:0];
776 
`else
777 
assign dvr0 = 32'h0000_0000;
778 
`endif
779 
 
780 
//
781 
// Write to DVR1
782 
//
783 
`ifdef OR1200_DU_DVR1
784 
always @(posedge clk or posedge rst)
785 
        if (rst)
786 
                dvr1 <= 32'h0000_0000;
787 
        else if (dvr1_sel && spr_write)
788 
                dvr1 <= #1 spr_dat_i[31:0];
789 
`else
790 
assign dvr1 = 32'h0000_0000;
791 
`endif
792 
 
793 
//
794 
// Write to DVR2
795 
//
796 
`ifdef OR1200_DU_DVR2
797 
always @(posedge clk or posedge rst)
798 
        if (rst)
799 
                dvr2 <= 32'h0000_0000;
800 
        else if (dvr2_sel && spr_write)
801 
                dvr2 <= #1 spr_dat_i[31:0];
802 
`else
803 
assign dvr2 = 32'h0000_0000;
804 
`endif
805 
 
806 
//
807 
// Write to DVR3
808 
//
809 
`ifdef OR1200_DU_DVR3
810 
always @(posedge clk or posedge rst)
811 
        if (rst)
812 
                dvr3 <= 32'h0000_0000;
813 
        else if (dvr3_sel && spr_write)
814 
                dvr3 <= #1 spr_dat_i[31:0];
815 
`else
816 
assign dvr3 = 32'h0000_0000;
817 
`endif
818 
 
819 
//
820 
// Write to DVR4
821 
//
822 
`ifdef OR1200_DU_DVR4
823 
always @(posedge clk or posedge rst)
824 
        if (rst)
825 
                dvr4 <= 32'h0000_0000;
826 
        else if (dvr4_sel && spr_write)
827 
                dvr4 <= #1 spr_dat_i[31:0];
828 
`else
829 
assign dvr4 = 32'h0000_0000;
830 
`endif
831 
 
832 
//
833 
// Write to DVR5
834 
//
835 
`ifdef OR1200_DU_DVR5
836 
always @(posedge clk or posedge rst)
837 
        if (rst)
838 
                dvr5 <= 32'h0000_0000;
839 
        else if (dvr5_sel && spr_write)
840 
                dvr5 <= #1 spr_dat_i[31:0];
841 
`else
842 
assign dvr5 = 32'h0000_0000;
843 
`endif
844 
 
845 
//
846 
// Write to DVR6
847 
//
848 
`ifdef OR1200_DU_DVR6
849 
always @(posedge clk or posedge rst)
850 
        if (rst)
851 
                dvr6 <= 32'h0000_0000;
852 
        else if (dvr6_sel && spr_write)
853 
                dvr6 <= #1 spr_dat_i[31:0];
854 
`else
855 
assign dvr6 = 32'h0000_0000;
856 
`endif
857 
 
858 
//
859 
// Write to DVR7
860 
//
861 
`ifdef OR1200_DU_DVR7
862 
always @(posedge clk or posedge rst)
863 
        if (rst)
864 
                dvr7 <= 32'h0000_0000;
865 
        else if (dvr7_sel && spr_write)
866 
                dvr7 <= #1 spr_dat_i[31:0];
867 
`else
868 
assign dvr7 = 32'h0000_0000;
869 
`endif
870 
 
871 
//
872 
// Write to DCR0
873 
//
874 
`ifdef OR1200_DU_DCR0
875 
always @(posedge clk or posedge rst)
876 
        if (rst)
877 
                dcr0 <= 8'h00;
878 
        else if (dcr0_sel && spr_write)
879 
                dcr0 <= #1 spr_dat_i[7:0];
880 
`else
881 
assign dcr0 = 8'h00;
882 
`endif
883 
 
884 
//
885 
// Write to DCR1
886 
//
887 
`ifdef OR1200_DU_DCR1
888 
always @(posedge clk or posedge rst)
889 
        if (rst)
890 
                dcr1 <= 8'h00;
891 
        else if (dcr1_sel && spr_write)
892 
                dcr1 <= #1 spr_dat_i[7:0];
893 
`else
894 
assign dcr1 = 8'h00;
895 
`endif
896 
 
897 
//
898 
// Write to DCR2
899 
//
900 
`ifdef OR1200_DU_DCR2
901 
always @(posedge clk or posedge rst)
902 
        if (rst)
903 
                dcr2 <= 8'h00;
904 
        else if (dcr2_sel && spr_write)
905 
                dcr2 <= #1 spr_dat_i[7:0];
906 
`else
907 
assign dcr2 = 8'h00;
908 
`endif
909 
 
910 
//
911 
// Write to DCR3
912 
//
913 
`ifdef OR1200_DU_DCR3
914 
always @(posedge clk or posedge rst)
915 
        if (rst)
916 
                dcr3 <= 8'h00;
917 
        else if (dcr3_sel && spr_write)
918 
                dcr3 <= #1 spr_dat_i[7:0];
919 
`else
920 
assign dcr3 = 8'h00;
921 
`endif
922 
 
923 
//
924 
// Write to DCR4
925 
//
926 
`ifdef OR1200_DU_DCR4
927 
always @(posedge clk or posedge rst)
928 
        if (rst)
929 
                dcr4 <= 8'h00;
930 
        else if (dcr4_sel && spr_write)
931 
                dcr4 <= #1 spr_dat_i[7:0];
932 
`else
933 
assign dcr4 = 8'h00;
934 
`endif
935 
 
936 
//
937 
// Write to DCR5
938 
//
939 
`ifdef OR1200_DU_DCR5
940 
always @(posedge clk or posedge rst)
941 
        if (rst)
942 
                dcr5 <= 8'h00;
943 
        else if (dcr5_sel && spr_write)
944 
                dcr5 <= #1 spr_dat_i[7:0];
945 
`else
946 
assign dcr5 = 8'h00;
947 
`endif
948 
 
949 
//
950 
// Write to DCR6
951 
//
952 
`ifdef OR1200_DU_DCR6
953 
always @(posedge clk or posedge rst)
954 
        if (rst)
955 
                dcr6 <= 8'h00;
956 
        else if (dcr6_sel && spr_write)
957 
                dcr6 <= #1 spr_dat_i[7:0];
958 
`else
959 
assign dcr6 = 8'h00;
960 
`endif
961 
 
962 
//
963 
// Write to DCR7
964 
//
965 
`ifdef OR1200_DU_DCR7
966 
always @(posedge clk or posedge rst)
967 
        if (rst)
968 
                dcr7 <= 8'h00;
969 
        else if (dcr7_sel && spr_write)
970 
                dcr7 <= #1 spr_dat_i[7:0];
971 
`else
972 
assign dcr7 = 8'h00;
973 
`endif
974 
 
975 
//
976 
// Write to DWCR0
977 
//
978 
`ifdef OR1200_DU_DWCR0
979 
always @(posedge clk or posedge rst)
980 
        if (rst)
981 
                dwcr0 <= 32'h0000_0000;
982 
        else if (dwcr0_sel && spr_write)
983 
                dwcr0 <= #1 spr_dat_i[31:0];
984 
        else if (incr_wpcntr0)
985 
                dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
986 
`else
987 
assign dwcr0 = 32'h0000_0000;
988 
`endif
989 
 
990 
//
991 
// Write to DWCR1
992 
//
993 
`ifdef OR1200_DU_DWCR1
994 
always @(posedge clk or posedge rst)
995 
        if (rst)
996 
                dwcr1 <= 32'h0000_0000;
997 
        else if (dwcr1_sel && spr_write)
998 
                dwcr1 <= #1 spr_dat_i[31:0];
999 
        else if (incr_wpcntr1)
1000 
                dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
1001 
`else
1002 
assign dwcr1 = 32'h0000_0000;
1003 
`endif
1004 
 
1005 
//
1006 
// Read DU registers
1007 
//
1008 
`ifdef OR1200_DU_READREGS
1009 
 
1010 
// SynEDA CoreMultiplier
1011 
// assignment(s): spr_dat_o
1012 
// replace(s): spr_addr, dmr1, dsr, drr
1013 
always @(spr_addr_cml_1 or dsr_cml_1 or drr_cml_1 or dmr1_cml_1 or dmr2
1014 
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
1015 
        or dvr5 or dvr6 or dvr7
1016 
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
1017 
        or dcr5 or dcr6 or dcr7
1018 
        or dwcr0 or dwcr1
1019 
`ifdef OR1200_DU_TB_IMPLEMENTED
1020 
        or tb_wadr or tbia_dat_o or tbim_dat_o
1021 
        or tbar_dat_o or tbts_dat_o
1022 
`endif
1023 
        )
1024 
        casex (spr_addr_cml_1[`OR1200_DUOFS_BITS]) // synopsys parallel_case
1025 
`ifdef OR1200_DU_DVR0
1026 
                `OR1200_DU_DVR0:
1027 
                        spr_dat_o = dvr0;
1028 
`endif
1029 
`ifdef OR1200_DU_DVR1
1030 
                `OR1200_DU_DVR1:
1031 
                        spr_dat_o = dvr1;
1032 
`endif
1033 
`ifdef OR1200_DU_DVR2
1034 
                `OR1200_DU_DVR2:
1035 
                        spr_dat_o = dvr2;
1036 
`endif
1037 
`ifdef OR1200_DU_DVR3
1038 
                `OR1200_DU_DVR3:
1039 
                        spr_dat_o = dvr3;
1040 
`endif
1041 
`ifdef OR1200_DU_DVR4
1042 
                `OR1200_DU_DVR4:
1043 
                        spr_dat_o = dvr4;
1044 
`endif
1045 
`ifdef OR1200_DU_DVR5
1046 
                `OR1200_DU_DVR5:
1047 
                        spr_dat_o = dvr5;
1048 
`endif
1049 
`ifdef OR1200_DU_DVR6
1050 
                `OR1200_DU_DVR6:
1051 
                        spr_dat_o = dvr6;
1052 
`endif
1053 
`ifdef OR1200_DU_DVR7
1054 
                `OR1200_DU_DVR7:
1055 
                        spr_dat_o = dvr7;
1056 
`endif
1057 
`ifdef OR1200_DU_DCR0
1058 
                `OR1200_DU_DCR0:
1059 
                        spr_dat_o = {24'h00_0000, dcr0};
1060 
`endif
1061 
`ifdef OR1200_DU_DCR1
1062 
                `OR1200_DU_DCR1:
1063 
                        spr_dat_o = {24'h00_0000, dcr1};
1064 
`endif
1065 
`ifdef OR1200_DU_DCR2
1066 
                `OR1200_DU_DCR2:
1067 
                        spr_dat_o = {24'h00_0000, dcr2};
1068 
`endif
1069 
`ifdef OR1200_DU_DCR3
1070 
                `OR1200_DU_DCR3:
1071 
                        spr_dat_o = {24'h00_0000, dcr3};
1072 
`endif
1073 
`ifdef OR1200_DU_DCR4
1074 
                `OR1200_DU_DCR4:
1075 
                        spr_dat_o = {24'h00_0000, dcr4};
1076 
`endif
1077 
`ifdef OR1200_DU_DCR5
1078 
                `OR1200_DU_DCR5:
1079 
                        spr_dat_o = {24'h00_0000, dcr5};
1080 
`endif
1081 
`ifdef OR1200_DU_DCR6
1082 
                `OR1200_DU_DCR6:
1083 
                        spr_dat_o = {24'h00_0000, dcr6};
1084 
`endif
1085 
`ifdef OR1200_DU_DCR7
1086 
                `OR1200_DU_DCR7:
1087 
                        spr_dat_o = {24'h00_0000, dcr7};
1088 
`endif
1089 
`ifdef OR1200_DU_DMR1
1090 
                `OR1200_DU_DMR1:
1091 
                        spr_dat_o = {7'h00, dmr1_cml_1};
1092 
`endif
1093 
`ifdef OR1200_DU_DMR2
1094 
                `OR1200_DU_DMR2:
1095 
                        spr_dat_o = {8'h00, dmr2};
1096 
`endif
1097 
`ifdef OR1200_DU_DWCR0
1098 
                `OR1200_DU_DWCR0:
1099 
                        spr_dat_o = dwcr0;
1100 
`endif
1101 
`ifdef OR1200_DU_DWCR1
1102 
                `OR1200_DU_DWCR1:
1103 
                        spr_dat_o = dwcr1;
1104 
`endif
1105 
`ifdef OR1200_DU_DSR
1106 
                `OR1200_DU_DSR:
1107 
                        spr_dat_o = {18'b0, dsr_cml_1};
1108 
`endif
1109 
`ifdef OR1200_DU_DRR
1110 
                `OR1200_DU_DRR:
1111 
                        spr_dat_o = {18'b0, drr_cml_1};
1112 
`endif
1113 
`ifdef OR1200_DU_TB_IMPLEMENTED
1114 
                `OR1200_DU_TBADR:
1115 
                        spr_dat_o = {24'h000000, tb_wadr};
1116 
                `OR1200_DU_TBIA:
1117 
                        spr_dat_o = tbia_dat_o;
1118 
                `OR1200_DU_TBIM:
1119 
                        spr_dat_o = tbim_dat_o;
1120 
                `OR1200_DU_TBAR:
1121 
                        spr_dat_o = tbar_dat_o;
1122 
                `OR1200_DU_TBTS:
1123 
                        spr_dat_o = tbts_dat_o;
1124 
`endif
1125 
                default:
1126 
                        spr_dat_o = 32'h0000_0000;
1127 
        endcase
1128 
`endif
1129 
 
1130 
//
1131 
// DSR alias
1132 
//
1133 
assign du_dsr = dsr;
1134 
 
1135 
`ifdef OR1200_DU_HWBKPTS
1136 
 
1137 
//
1138 
// Compare To What (Match Condition 0)
1139 
//
1140 
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1141 
        or dcpu_dat_lsu or dcpu_we_i)
1142 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1143 
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1144 
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1145 
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1146 
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1147 
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1148 
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1149 
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1150 
        endcase
1151 
 
1152 
//
1153 
// When To Compare (Match Condition 0)
1154 
//
1155 
always @(dcr0 or dcpu_cycstb_i)
1156 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1157 
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1158 
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1159 
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1160 
        endcase
1161 
 
1162 
//
1163 
// Match Condition 0
1164 
//
1165 
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1166 
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1167 
                4'b0_xxx,
1168 
                4'b1_000,
1169 
                4'b1_111: match0 = 1'b0;
1170 
                4'b1_001: match0 =
1171 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
1172 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1173 
                4'b1_010: match0 =
1174 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
1175 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1176 
                4'b1_011: match0 =
1177 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
1178 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1179 
                4'b1_100: match0 =
1180 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
1181 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1182 
                4'b1_101: match0 =
1183 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
1184 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1185 
                4'b1_110: match0 =
1186 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
1187 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1188 
        endcase
1189 
 
1190 
//
1191 
// Watchpoint 0
1192 
//
1193 
always @(dmr1 or match0)
1194 
        case (dmr1[`OR1200_DU_DMR1_CW0])
1195 
                2'b00: wp[0] = match0;
1196 
                2'b01: wp[0] = match0;
1197 
                2'b10: wp[0] = match0;
1198 
                2'b11: wp[0] = 1'b0;
1199 
        endcase
1200 
 
1201 
//
1202 
// Compare To What (Match Condition 1)
1203 
//
1204 
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1205 
        or dcpu_dat_lsu or dcpu_we_i)
1206 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1207 
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1208 
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1209 
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1210 
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1211 
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1212 
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1213 
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1214 
        endcase
1215 
 
1216 
//
1217 
// When To Compare (Match Condition 1)
1218 
//
1219 
always @(dcr1 or dcpu_cycstb_i)
1220 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1221 
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1222 
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1223 
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1224 
        endcase
1225 
 
1226 
//
1227 
// Match Condition 1
1228 
//
1229 
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1230 
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1231 
                4'b0_xxx,
1232 
                4'b1_000,
1233 
                4'b1_111: match1 = 1'b0;
1234 
                4'b1_001: match1 =
1235 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
1236 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1237 
                4'b1_010: match1 =
1238 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
1239 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1240 
                4'b1_011: match1 =
1241 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
1242 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1243 
                4'b1_100: match1 =
1244 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
1245 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1246 
                4'b1_101: match1 =
1247 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
1248 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1249 
                4'b1_110: match1 =
1250 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
1251 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1252 
        endcase
1253 
 
1254 
//
1255 
// Watchpoint 1
1256 
//
1257 
always @(dmr1 or match1 or wp)
1258 
        case (dmr1[`OR1200_DU_DMR1_CW1])
1259 
                2'b00: wp[1] = match1;
1260 
                2'b01: wp[1] = match1 & wp[0];
1261 
                2'b10: wp[1] = match1 | wp[0];
1262 
                2'b11: wp[1] = 1'b0;
1263 
        endcase
1264 
 
1265 
//
1266 
// Compare To What (Match Condition 2)
1267 
//
1268 
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1269 
        or dcpu_dat_lsu or dcpu_we_i)
1270 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1271 
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1272 
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1273 
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1274 
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1275 
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1276 
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1277 
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1278 
        endcase
1279 
 
1280 
//
1281 
// When To Compare (Match Condition 2)
1282 
//
1283 
always @(dcr2 or dcpu_cycstb_i)
1284 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1285 
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1286 
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1287 
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1288 
        endcase
1289 
 
1290 
//
1291 
// Match Condition 2
1292 
//
1293 
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1294 
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1295 
                4'b0_xxx,
1296 
                4'b1_000,
1297 
                4'b1_111: match2 = 1'b0;
1298 
                4'b1_001: match2 =
1299 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
1300 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1301 
                4'b1_010: match2 =
1302 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
1303 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1304 
                4'b1_011: match2 =
1305 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
1306 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1307 
                4'b1_100: match2 =
1308 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
1309 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1310 
                4'b1_101: match2 =
1311 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
1312 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1313 
                4'b1_110: match2 =
1314 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
1315 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1316 
        endcase
1317 
 
1318 
//
1319 
// Watchpoint 2
1320 
//
1321 
always @(dmr1 or match2 or wp)
1322 
        case (dmr1[`OR1200_DU_DMR1_CW2])
1323 
                2'b00: wp[2] = match2;
1324 
                2'b01: wp[2] = match2 & wp[1];
1325 
                2'b10: wp[2] = match2 | wp[1];
1326 
                2'b11: wp[2] = 1'b0;
1327 
        endcase
1328 
 
1329 
//
1330 
// Compare To What (Match Condition 3)
1331 
//
1332 
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1333 
        or dcpu_dat_lsu or dcpu_we_i)
1334 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1335 
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1336 
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1337 
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1338 
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1339 
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1340 
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1341 
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1342 
        endcase
1343 
 
1344 
//
1345 
// When To Compare (Match Condition 3)
1346 
//
1347 
always @(dcr3 or dcpu_cycstb_i)
1348 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1349 
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1350 
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1351 
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1352 
        endcase
1353 
 
1354 
//
1355 
// Match Condition 3
1356 
//
1357 
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1358 
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1359 
                4'b0_xxx,
1360 
                4'b1_000,
1361 
                4'b1_111: match3 = 1'b0;
1362 
                4'b1_001: match3 =
1363 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
1364 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1365 
                4'b1_010: match3 =
1366 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
1367 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1368 
                4'b1_011: match3 =
1369 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
1370 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1371 
                4'b1_100: match3 =
1372 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
1373 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1374 
                4'b1_101: match3 =
1375 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
1376 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1377 
                4'b1_110: match3 =
1378 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
1379 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1380 
        endcase
1381 
 
1382 
//
1383 
// Watchpoint 3
1384 
//
1385 
always @(dmr1 or match3 or wp)
1386 
        case (dmr1[`OR1200_DU_DMR1_CW3])
1387 
                2'b00: wp[3] = match3;
1388 
                2'b01: wp[3] = match3 & wp[2];
1389 
                2'b10: wp[3] = match3 | wp[2];
1390 
                2'b11: wp[3] = 1'b0;
1391 
        endcase
1392 
 
1393 
//
1394 
// Compare To What (Match Condition 4)
1395 
//
1396 
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1397 
        or dcpu_dat_lsu or dcpu_we_i)
1398 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1399 
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1400 
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1401 
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1402 
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1403 
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1404 
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1405 
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1406 
        endcase
1407 
 
1408 
//
1409 
// When To Compare (Match Condition 4)
1410 
//
1411 
always @(dcr4 or dcpu_cycstb_i)
1412 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1413 
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1414 
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1415 
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1416 
        endcase
1417 
 
1418 
//
1419 
// Match Condition 4
1420 
//
1421 
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1422 
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1423 
                4'b0_xxx,
1424 
                4'b1_000,
1425 
                4'b1_111: match4 = 1'b0;
1426 
                4'b1_001: match4 =
1427 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
1428 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1429 
                4'b1_010: match4 =
1430 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
1431 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1432 
                4'b1_011: match4 =
1433 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
1434 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1435 
                4'b1_100: match4 =
1436 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
1437 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1438 
                4'b1_101: match4 =
1439 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
1440 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1441 
                4'b1_110: match4 =
1442 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
1443 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1444 
        endcase
1445 
 
1446 
//
1447 
// Watchpoint 4
1448 
//
1449 
always @(dmr1 or match4 or wp)
1450 
        case (dmr1[`OR1200_DU_DMR1_CW4])
1451 
                2'b00: wp[4] = match4;
1452 
                2'b01: wp[4] = match4 & wp[3];
1453 
                2'b10: wp[4] = match4 | wp[3];
1454 
                2'b11: wp[4] = 1'b0;
1455 
        endcase
1456 
 
1457 
//
1458 
// Compare To What (Match Condition 5)
1459 
//
1460 
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1461 
        or dcpu_dat_lsu or dcpu_we_i)
1462 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1463 
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1464 
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1465 
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1466 
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1467 
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1468 
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1469 
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1470 
        endcase
1471 
 
1472 
//
1473 
// When To Compare (Match Condition 5)
1474 
//
1475 
always @(dcr5 or dcpu_cycstb_i)
1476 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1477 
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1478 
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1479 
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1480 
        endcase
1481 
 
1482 
//
1483 
// Match Condition 5
1484 
//
1485 
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1486 
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1487 
                4'b0_xxx,
1488 
                4'b1_000,
1489 
                4'b1_111: match5 = 1'b0;
1490 
                4'b1_001: match5 =
1491 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
1492 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1493 
                4'b1_010: match5 =
1494 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
1495 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1496 
                4'b1_011: match5 =
1497 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
1498 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1499 
                4'b1_100: match5 =
1500 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
1501 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1502 
                4'b1_101: match5 =
1503 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
1504 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1505 
                4'b1_110: match5 =
1506 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
1507 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1508 
        endcase
1509 
 
1510 
//
1511 
// Watchpoint 5
1512 
//
1513 
always @(dmr1 or match5 or wp)
1514 
        case (dmr1[`OR1200_DU_DMR1_CW5])
1515 
                2'b00: wp[5] = match5;
1516 
                2'b01: wp[5] = match5 & wp[4];
1517 
                2'b10: wp[5] = match5 | wp[4];
1518 
                2'b11: wp[5] = 1'b0;
1519 
        endcase
1520 
 
1521 
//
1522 
// Compare To What (Match Condition 6)
1523 
//
1524 
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1525 
        or dcpu_dat_lsu or dcpu_we_i)
1526 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1527 
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1528 
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1529 
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1530 
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1531 
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1532 
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1533 
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1534 
        endcase
1535 
 
1536 
//
1537 
// When To Compare (Match Condition 6)
1538 
//
1539 
always @(dcr6 or dcpu_cycstb_i)
1540 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1541 
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1542 
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1543 
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1544 
        endcase
1545 
 
1546 
//
1547 
// Match Condition 6
1548 
//
1549 
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1550 
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1551 
                4'b0_xxx,
1552 
                4'b1_000,
1553 
                4'b1_111: match6 = 1'b0;
1554 
                4'b1_001: match6 =
1555 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
1556 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1557 
                4'b1_010: match6 =
1558 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
1559 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1560 
                4'b1_011: match6 =
1561 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
1562 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1563 
                4'b1_100: match6 =
1564 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
1565 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1566 
                4'b1_101: match6 =
1567 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
1568 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1569 
                4'b1_110: match6 =
1570 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
1571 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1572 
        endcase
1573 
 
1574 
//
1575 
// Watchpoint 6
1576 
//
1577 
always @(dmr1 or match6 or wp)
1578 
        case (dmr1[`OR1200_DU_DMR1_CW6])
1579 
                2'b00: wp[6] = match6;
1580 
                2'b01: wp[6] = match6 & wp[5];
1581 
                2'b10: wp[6] = match6 | wp[5];
1582 
                2'b11: wp[6] = 1'b0;
1583 
        endcase
1584 
 
1585 
//
1586 
// Compare To What (Match Condition 7)
1587 
//
1588 
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1589 
        or dcpu_dat_lsu or dcpu_we_i)
1590 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1591 
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1592 
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1593 
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1594 
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1595 
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1596 
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1597 
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1598 
        endcase
1599 
 
1600 
//
1601 
// When To Compare (Match Condition 7)
1602 
//
1603 
always @(dcr7 or dcpu_cycstb_i)
1604 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1605 
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1606 
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1607 
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1608 
        endcase
1609 
 
1610 
//
1611 
// Match Condition 7
1612 
//
1613 
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1614 
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1615 
                4'b0_xxx,
1616 
                4'b1_000,
1617 
                4'b1_111: match7 = 1'b0;
1618 
                4'b1_001: match7 =
1619 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
1620 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1621 
                4'b1_010: match7 =
1622 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
1623 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1624 
                4'b1_011: match7 =
1625 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
1626 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1627 
                4'b1_100: match7 =
1628 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
1629 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1630 
                4'b1_101: match7 =
1631 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
1632 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1633 
                4'b1_110: match7 =
1634 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
1635 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1636 
        endcase
1637 
 
1638 
//
1639 
// Watchpoint 7
1640 
//
1641 
always @(dmr1 or match7 or wp)
1642 
        case (dmr1[`OR1200_DU_DMR1_CW7])
1643 
                2'b00: wp[7] = match7;
1644 
                2'b01: wp[7] = match7 & wp[6];
1645 
                2'b10: wp[7] = match7 | wp[6];
1646 
                2'b11: wp[7] = 1'b0;
1647 
        endcase
1648 
 
1649 
//
1650 
// Increment Watchpoint Counter 0
1651 
//
1652 
always @(wp or dmr2)
1653 
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1654 
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1655 
        else
1656 
                incr_wpcntr0 = 1'b0;
1657 
 
1658 
//
1659 
// Match Condition Watchpoint Counter 0
1660 
//
1661 
always @(dwcr0)
1662 
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1663 
                wpcntr0_match = 1'b1;
1664 
        else
1665 
                wpcntr0_match = 1'b0;
1666 
 
1667 
 
1668 
//
1669 
// Watchpoint 8
1670 
//
1671 
always @(dmr1 or wpcntr0_match or wp)
1672 
        case (dmr1[`OR1200_DU_DMR1_CW8])
1673 
                2'b00: wp[8] = wpcntr0_match;
1674 
                2'b01: wp[8] = wpcntr0_match & wp[7];
1675 
                2'b10: wp[8] = wpcntr0_match | wp[7];
1676 
                2'b11: wp[8] = 1'b0;
1677 
        endcase
1678 
 
1679 
 
1680 
//
1681 
// Increment Watchpoint Counter 1
1682 
//
1683 
always @(wp or dmr2)
1684 
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1685 
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1686 
        else
1687 
                incr_wpcntr1 = 1'b0;
1688 
 
1689 
//
1690 
// Match Condition Watchpoint Counter 1
1691 
//
1692 
always @(dwcr1)
1693 
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1694 
                wpcntr1_match = 1'b1;
1695 
        else
1696 
                wpcntr1_match = 1'b0;
1697 
 
1698 
//
1699 
// Watchpoint 9
1700 
//
1701 
always @(dmr1 or wpcntr1_match or wp)
1702 
        case (dmr1[`OR1200_DU_DMR1_CW9])
1703 
                2'b00: wp[9] = wpcntr1_match;
1704 
                2'b01: wp[9] = wpcntr1_match & wp[8];
1705 
                2'b10: wp[9] = wpcntr1_match | wp[8];
1706 
                2'b11: wp[9] = 1'b0;
1707 
        endcase
1708 
 
1709 
//
1710 
// Watchpoint 10
1711 
//
1712 
always @(dmr1 or dbg_ewt_i or wp)
1713 
        case (dmr1[`OR1200_DU_DMR1_CW10])
1714 
                2'b00: wp[10] = dbg_ewt_i;
1715 
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1716 
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1717 
                2'b11: wp[10] = 1'b0;
1718 
        endcase
1719 
 
1720 
`endif
1721 
 
1722 
//
1723 
// Watchpoints can cause trap exception
1724 
//
1725 
`ifdef OR1200_DU_HWBKPTS
1726 
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
1727 
`else
1728 
assign du_hwbkpt = 1'b0;
1729 
`endif
1730 
 
1731 
`ifdef OR1200_DU_TB_IMPLEMENTED
1732 
//
1733 
// Simple trace buffer
1734 
// (right now hardcoded for Xilinx Virtex FPGAs)
1735 
//
1736 
// Stores last 256 instruction addresses, instruction
1737 
// machine words and ALU results
1738 
//
1739 
 
1740 
//
1741 
// Trace buffer write enable
1742 
//
1743 
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1744 
 
1745 
//
1746 
// Trace buffer write address pointer
1747 
//
1748 
always @(posedge clk or posedge rst)
1749 
        if (rst)
1750 
                tb_wadr <= #1 8'h00;
1751 
        else if (tb_enw)
1752 
                tb_wadr <= #1 tb_wadr + 8'd1;
1753 
 
1754 
//
1755 
// Free running counter (time stamp)
1756 
//
1757 
always @(posedge clk or posedge rst)
1758 
        if (rst)
1759 
                tb_timstmp <= #1 32'h00000000;
1760 
        else if (!dbg_bp_r)
1761 
                tb_timstmp <= #1 tb_timstmp + 32'd1;
1762 
 
1763 
//
1764 
// Trace buffer RAMs
1765 
//
1766 
 
1767 
or1200_dpram_256x32 tbia_ram(
1768 
        .clk_a(clk),
1769 
        .rst_a(rst),
1770 
        .addr_a(spr_addr[7:0]),
1771 
        .ce_a(1'b1),
1772 
        .oe_a(1'b1),
1773 
        .do_a(tbia_dat_o),
1774 
 
1775 
        .clk_b(clk),
1776 
        .rst_b(rst),
1777 
        .addr_b(tb_wadr),
1778 
        .di_b(spr_dat_npc),
1779 
        .ce_b(1'b1),
1780 
        .we_b(tb_enw)
1781 
 
1782 
);
1783 
 
1784 
or1200_dpram_256x32 tbim_ram(
1785 
        .clk_a(clk),
1786 
        .rst_a(rst),
1787 
        .addr_a(spr_addr[7:0]),
1788 
        .ce_a(1'b1),
1789 
        .oe_a(1'b1),
1790 
        .do_a(tbim_dat_o),
1791 
 
1792 
        .clk_b(clk),
1793 
        .rst_b(rst),
1794 
        .addr_b(tb_wadr),
1795 
        .di_b(ex_insn),
1796 
        .ce_b(1'b1),
1797 
        .we_b(tb_enw)
1798 
);
1799 
 
1800 
or1200_dpram_256x32 tbar_ram(
1801 
        .clk_a(clk),
1802 
        .rst_a(rst),
1803 
        .addr_a(spr_addr[7:0]),
1804 
        .ce_a(1'b1),
1805 
        .oe_a(1'b1),
1806 
        .do_a(tbar_dat_o),
1807 
 
1808 
        .clk_b(clk),
1809 
        .rst_b(rst),
1810 
        .addr_b(tb_wadr),
1811 
        .di_b(rf_dataw),
1812 
        .ce_b(1'b1),
1813 
        .we_b(tb_enw)
1814 
);
1815 
 
1816 
or1200_dpram_256x32 tbts_ram(
1817 
        .clk_a(clk),
1818 
        .rst_a(rst),
1819 
        .addr_a(spr_addr[7:0]),
1820 
        .ce_a(1'b1),
1821 
        .oe_a(1'b1),
1822 
        .do_a(tbts_dat_o),
1823 
 
1824 
        .clk_b(clk),
1825 
        .rst_b(rst),
1826 
        .addr_b(tb_wadr),
1827 
        .di_b(tb_timstmp),
1828 
        .ce_b(1'b1),
1829 
        .we_b(tb_enw)
1830 
);
1831 
 
1832 
`else
1833 
 
1834 
assign tbia_dat_o = 32'h0000_0000;
1835 
assign tbim_dat_o = 32'h0000_0000;
1836 
assign tbar_dat_o = 32'h0000_0000;
1837 
assign tbts_dat_o = 32'h0000_0000;
1838 
 
1839 
`endif  // OR1200_DU_TB_IMPLEMENTED
1840 
 
1841 
`else   // OR1200_DU_IMPLEMENTED
1842 
 
1843 
//
1844 
// When DU is not implemented, drive all outputs as would when DU is disabled
1845 
//
1846 
assign dbg_bp_o = 1'b0;
1847 
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1848 
assign du_hwbkpt = 1'b0;
1849 
 
1850 
//
1851 
// Read DU registers
1852 
//
1853 
`ifdef OR1200_DU_READREGS
1854 
assign spr_dat_o = 32'h0000_0000;
1855 
`ifdef OR1200_DU_UNUSED_ZERO
1856 
`endif
1857 
`endif
1858 
 
1859 
`endif
1860 
 
1861 
 
1862 
always @ (posedge clk_i_cml_1) begin
1863 
branch_op_cml_1 <= branch_op;
1864 
ex_insn_cml_1 <= ex_insn;
1865 
spr_write_cml_1 <= spr_write;
1866 
spr_addr_cml_1 <= spr_addr;
1867 
spr_dat_i_cml_1 <= spr_dat_i;
1868 
dbg_is_o_cml_1 <= dbg_is_o;
1869 
dbg_stb_i_cml_1 <= dbg_stb_i;
1870 
dbg_ack_o_cml_1 <= dbg_ack_o;
1871 
dmr1_cml_1 <= dmr1;
1872 
dsr_cml_1 <= dsr;
1873 
drr_cml_1 <= drr;
1874 
dbg_bp_r_cml_1 <= dbg_bp_r;
1875 
end
1876 
endmodule
1877 
 

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