URL https://opencores.org/ocsvn/or1200_hp/or1200_hp/trunk

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_genpc.v] - Blame information for rev 2

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.3  2003/12/17 13:43:38  simons
// Exception prefix configuration changed.
//
// Revision 1.7.4.2  2003/12/04 23:44:31  lampret
// Static exception prefix.
//
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.7  2003/04/20 22:23:57  lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.6  2002/03/29 15:16:55  lampret
// Some of the warnings fixed.
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc_cm2(
                clk_i_cml_1,
 
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
        icpu_rty_i, icpu_adr_i,
 
        // Internal i/f
        branch_op, except_type, except_prefix,
        branch_addrofs, lr_restor, flag, taken, except_start,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, genpc_stop_prefetch, no_more_dslot
);
 
 
input clk_i_cml_1;
reg  icpu_rty_i_cml_1;
reg  except_prefix_cml_1;
reg  except_start_cml_1;
reg [ 31 : 0 ] spr_dat_i_cml_1;
reg  spr_pc_we_cml_1;
reg  genpc_refetch_cml_1;
reg  no_more_dslot_cml_1;
reg [ 31 : 2 ] pcreg_cml_1;
reg [ 31 : 0 ] pc_cml_1;
reg  genpc_refetch_r_cml_1;
 
 
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cycstb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_rty_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input   [31:2]                  branch_addrofs;
input   [31:0]                   lr_restor;
input                           flag;
output                          taken;
input                           except_start;
input   [31:2]                  binsn_addr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_stop_prefetch;
input                           genpc_freeze;
input                           no_more_dslot;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             genpc_refetch_r;
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// genpc_freeze_r
//
 
// SynEDA CoreMultiplier
// assignment(s): genpc_refetch_r
// replace(s): genpc_refetch, genpc_refetch_r
always @(posedge clk or posedge rst)
        if (rst)
                genpc_refetch_r <= #1 1'b0;
        else begin  genpc_refetch_r <= genpc_refetch_r_cml_1; if (genpc_refetch_cml_1)
                genpc_refetch_r <= #1 1'b1;
        else
                genpc_refetch_r <= #1 1'b0; end
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 30'd1, 2'b0};
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {branch_addrofs, 2'b0};
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
                        pc = lr_restor;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {binsn_addr + branch_addrofs, 2'b0};
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 30'd1, 2'b0};
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                pc = {pcreg + 30'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                end
        endcase
end
 
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
                                taken = 1'b1;
                        end
                        else begin
                                taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                taken = 1'b0;
                        end
                        else begin
                                taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
                        taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
                        taken = 1'b1;
                end
                default: begin
                        taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
 
// SynEDA CoreMultiplier
// assignment(s): pcreg
// replace(s): icpu_rty_i, except_prefix, except_start, spr_dat_i, spr_pc_we, genpc_refetch, no_more_dslot, pcreg, pc
always @(posedge clk or posedge rst)
        if (rst)
//              pcreg <= #1 30'd63;
                pcreg <= #1 ({(except_prefix_cml_1 ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
        else begin  pcreg <= pcreg_cml_1; if (spr_pc_we_cml_1)
                pcreg <= #1 spr_dat_i_cml_1[31:2];
        else if (no_more_dslot_cml_1 | except_start_cml_1 | !genpc_freeze & !icpu_rty_i_cml_1 & !genpc_refetch_cml_1)
//      else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
                pcreg <= #1 pc_cml_1[31:2]; end
 
 
always @ (posedge clk_i_cml_1) begin
icpu_rty_i_cml_1 <= icpu_rty_i;
except_prefix_cml_1 <= except_prefix;
except_start_cml_1 <= except_start;
spr_dat_i_cml_1 <= spr_dat_i;
spr_pc_we_cml_1 <= spr_pc_we;
genpc_refetch_cml_1 <= genpc_refetch;
no_more_dslot_cml_1 <= no_more_dslot;
pcreg_cml_1 <= pcreg;
pc_cml_1 <= pc;
genpc_refetch_r_cml_1 <= genpc_refetch_r;
end
endmodule
 

Browse

Tools

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_genpc.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's generate PC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.9 2004/04/05 08:29:57 lampret`
48			`// Merged branch_qmem into main tree.`
49			`//`
50			`// Revision 1.7.4.3 2003/12/17 13:43:38 simons`
51			`// Exception prefix configuration changed.`
52			`//`
53			`// Revision 1.7.4.2 2003/12/04 23:44:31 lampret`
54			`// Static exception prefix.`
55			`//`
56			`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`
57			`// Added embedded memory QMEM.`
58			`//`
59			`// Revision 1.7 2003/04/20 22:23:57 lampret`
60			`// No functional change. Only added customization for exception vectors.`
61			`//`
62			`// Revision 1.6 2002/03/29 15:16:55 lampret`
63			`// Some of the warnings fixed.`
64			`//`
65			`// Revision 1.5 2002/02/11 04:33:17 lampret`
66			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
67			`//`
68			`// Revision 1.4 2002/01/28 01:16:00 lampret`
69			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
70			`//`
71			`// Revision 1.3 2002/01/18 07:56:00 lampret`
72			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
73			`//`
74			`// Revision 1.2 2002/01/14 06:18:22 lampret`
75			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
76			`//`
77			`// Revision 1.1 2002/01/03 08:16:15 lampret`
78			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
79			`//`
80			`// Revision 1.10 2001/11/20 18:46:15 simons`
81			`// Break point bug fixed`
82			`//`
83			`// Revision 1.9 2001/11/18 09:58:28 lampret`
84			`// Fixed some l.trap typos.`
85			`//`
86			`// Revision 1.8 2001/11/18 08:36:28 lampret`
87			`// For GDB changed single stepping and disabled trap exception.`
88			`//`
89			`// Revision 1.7 2001/10/21 17:57:16 lampret`
90			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
91			`//`
92			`// Revision 1.6 2001/10/14 13:12:09 lampret`
93			`// MP3 version.`
94			`//`
95			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
96			`// no message`
97			`//`
98			`// Revision 1.1 2001/08/09 13:39:33 lampret`
99			`// Major clean-up.`
100			`//`
101			`//`
102
103			`// synopsys translate_off`
104			`include "timescale.v"
105			`// synopsys translate_on`
106			`include "or1200_defines.v"
107
108			`module or1200_genpc_cm2(`
109			`clk_i_cml_1,`
110
111			`// Clock and reset`
112			`clk, rst,`
113
114			`// External i/f to IC`
115			`icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,`
116			`icpu_rty_i, icpu_adr_i,`
117
118			`// Internal i/f`
119			`branch_op, except_type, except_prefix,`
120			`branch_addrofs, lr_restor, flag, taken, except_start,`
121			`binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
122			`genpc_freeze, genpc_stop_prefetch, no_more_dslot`
123			`);`
124
125
126			`input clk_i_cml_1;`
127			`reg icpu_rty_i_cml_1;`
128			`reg except_prefix_cml_1;`
129			`reg except_start_cml_1;`
130			`reg [ 31 : 0 ] spr_dat_i_cml_1;`
131			`reg spr_pc_we_cml_1;`
132			`reg genpc_refetch_cml_1;`
133			`reg no_more_dslot_cml_1;`
134			`reg [ 31 : 2 ] pcreg_cml_1;`
135			`reg [ 31 : 0 ] pc_cml_1;`
136			`reg genpc_refetch_r_cml_1;`
137
138
139
140			`//`
141			`// I/O`
142			`//`
143
144			`//`
145			`// Clock and reset`
146			`//`
147			`input clk;`
148			`input rst;`
149
150			`//`
151			`// External i/f to IC`
152			`//`
153			`output [31:0] icpu_adr_o;`
154			`output icpu_cycstb_o;`
155			`output [3:0] icpu_sel_o;`
156			`output [3:0] icpu_tag_o;`
157			`input icpu_rty_i;`
158			`input [31:0] icpu_adr_i;`
159
160			`//`
161			`// Internal i/f`
162			`//`
163			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
164			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
165			`input except_prefix;`
166			`input [31:2] branch_addrofs;`
167			`input [31:0] lr_restor;`
168			`input flag;`
169			`output taken;`
170			`input except_start;`
171			`input [31:2] binsn_addr;`
172			`input [31:0] epcr;`
173			`input [31:0] spr_dat_i;`
174			`input spr_pc_we;`
175			`input genpc_refetch;`
176			`input genpc_stop_prefetch;`
177			`input genpc_freeze;`
178			`input no_more_dslot;`
179
180			`//`
181			`// Internal wires and regs`
182			`//`
183			`reg [31:2] pcreg;`
184			`reg [31:0] pc;`
185			`reg taken; /* Set to in case of jump or taken branch */`
186			`reg genpc_refetch_r;`
187
188			`//`
189			`// Address of insn to be fecthed`
190			`//`
191			`assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
192			`// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
193
194			`//`
195			`// Control access to IC subsystem`
196			`//`
197			`// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;`
198			`assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store`
199			`//assign icpu_cycstb_o = !(genpc_freeze \| genpc_refetch & genpc_refetch_r);`
200			`//assign icpu_cycstb_o = !(genpc_freeze \| genpc_stop_prefetch);`
201			`assign icpu_sel_o = 4'b1111;`
202			assign icpu_tag_o = `OR1200_ITAG_NI;
203
204			`//`
205			`// genpc_freeze_r`
206			`//`
207
208			`// SynEDA CoreMultiplier`
209			`// assignment(s): genpc_refetch_r`
210			`// replace(s): genpc_refetch, genpc_refetch_r`
211			`always @(posedge clk or posedge rst)`
212			`if (rst)`
213			`genpc_refetch_r <= #1 1'b0;`
214			`else begin genpc_refetch_r <= genpc_refetch_r_cml_1; if (genpc_refetch_cml_1)`
215			`genpc_refetch_r <= #1 1'b1;`
216			`else`
217			`genpc_refetch_r <= #1 1'b0; end`
218
219			`//`
220			`// Async calculation of new PC value. This value is used for addressing the IC.`
221			`//`
222			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
223			`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin`
224			`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
225			{2'b00, `OR1200_BRANCHOP_NOP}: begin
226			`pc = {pcreg + 30'd1, 2'b0};`
227			`end`
228			{2'b00, `OR1200_BRANCHOP_J}: begin
229			`ifdef OR1200_VERBOSE
230			`// synopsys translate_off`
231			`$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);`
232			`// synopsys translate_on`
233			`endif
234			`pc = {branch_addrofs, 2'b0};`
235			`end`
236			{2'b00, `OR1200_BRANCHOP_JR}: begin
237			`ifdef OR1200_VERBOSE
238			`// synopsys translate_off`
239			`$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);`
240			`// synopsys translate_on`
241			`endif
242			`pc = lr_restor;`
243			`end`
244			{2'b00, `OR1200_BRANCHOP_BAL}: begin
245			`ifdef OR1200_VERBOSE
246			`// synopsys translate_off`
247			`$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
248			`// synopsys translate_on`
249			`endif
250			`pc = {binsn_addr + branch_addrofs, 2'b0};`
251			`end`
252			{2'b00, `OR1200_BRANCHOP_BF}:
253			`if (flag) begin`
254			`ifdef OR1200_VERBOSE
255			`// synopsys translate_off`
256			`$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
257			`// synopsys translate_on`
258			`endif
259			`pc = {binsn_addr + branch_addrofs, 2'b0};`
260			`end`
261			`else begin`
262			`ifdef OR1200_VERBOSE
263			`// synopsys translate_off`
264			`$display("%t: BRANCHOP_BF: not taken", $time);`
265			`// synopsys translate_on`
266			`endif
267			`pc = {pcreg + 30'd1, 2'b0};`
268			`end`
269			{2'b00, `OR1200_BRANCHOP_BNF}:
270			`if (flag) begin`
271			`pc = {pcreg + 30'd1, 2'b0};`
272			`ifdef OR1200_VERBOSE
273			`// synopsys translate_off`
274			`$display("%t: BRANCHOP_BNF: not taken", $time);`
275			`// synopsys translate_on`
276			`endif
277			`end`
278			`else begin`
279			`ifdef OR1200_VERBOSE
280			`// synopsys translate_off`
281			`$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
282			`// synopsys translate_on`
283			`endif
284			`pc = {binsn_addr + branch_addrofs, 2'b0};`
285			`end`
286			{2'b00, `OR1200_BRANCHOP_RFE}: begin
287			`ifdef OR1200_VERBOSE
288			`// synopsys translate_off`
289			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
290			`// synopsys translate_on`
291			`endif
292			`pc = epcr;`
293			`end`
294			`{2'b01, 3'bxxx}: begin`
295			`ifdef OR1200_VERBOSE
296			`// synopsys translate_off`
297			`$display("Starting exception: %h.", except_type);`
298			`// synopsys translate_on`
299			`endif
300			pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
301			`end`
302			`default: begin`
303			`ifdef OR1200_VERBOSE
304			`// synopsys translate_off`
305			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
306			`// synopsys translate_on`
307			`endif
308			`pc = spr_dat_i;`
309			`end`
310			`endcase`
311			`end`
312
313			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
314			`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin`
315			`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
316			{2'b00, `OR1200_BRANCHOP_NOP}: begin
317			`taken = 1'b0;`
318			`end`
319			{2'b00, `OR1200_BRANCHOP_J}: begin
320			`taken = 1'b1;`
321			`end`
322			{2'b00, `OR1200_BRANCHOP_JR}: begin
323			`taken = 1'b1;`
324			`end`
325			{2'b00, `OR1200_BRANCHOP_BAL}: begin
326			`taken = 1'b1;`
327			`end`
328			{2'b00, `OR1200_BRANCHOP_BF}:
329			`if (flag) begin`
330			`taken = 1'b1;`
331			`end`
332			`else begin`
333			`taken = 1'b0;`
334			`end`
335			{2'b00, `OR1200_BRANCHOP_BNF}:
336			`if (flag) begin`
337			`taken = 1'b0;`
338			`end`
339			`else begin`
340			`taken = 1'b1;`
341			`end`
342			{2'b00, `OR1200_BRANCHOP_RFE}: begin
343			`taken = 1'b1;`
344			`end`
345			`{2'b01, 3'bxxx}: begin`
346			`taken = 1'b1;`
347			`end`
348			`default: begin`
349			`taken = 1'b0;`
350			`end`
351			`endcase`
352			`end`
353
354			`//`
355			`// PC register`
356			`//`
357
358			`// SynEDA CoreMultiplier`
359			`// assignment(s): pcreg`
360			`// replace(s): icpu_rty_i, except_prefix, except_start, spr_dat_i, spr_pc_we, genpc_refetch, no_more_dslot, pcreg, pc`
361			`always @(posedge clk or posedge rst)`
362			`if (rst)`
363			`// pcreg <= #1 30'd63;`
364			pcreg <= #1 ({(except_prefix_cml_1 ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
365			`else begin pcreg <= pcreg_cml_1; if (spr_pc_we_cml_1)`
366			`pcreg <= #1 spr_dat_i_cml_1[31:2];`
367			`else if (no_more_dslot_cml_1 \| except_start_cml_1 \| !genpc_freeze & !icpu_rty_i_cml_1 & !genpc_refetch_cml_1)`
368			`// else if (except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
369			`pcreg <= #1 pc_cml_1[31:2]; end`
370
371
372			`always @ (posedge clk_i_cml_1) begin`
373			`icpu_rty_i_cml_1 <= icpu_rty_i;`
374			`except_prefix_cml_1 <= except_prefix;`
375			`except_start_cml_1 <= except_start;`
376			`spr_dat_i_cml_1 <= spr_dat_i;`
377			`spr_pc_we_cml_1 <= spr_pc_we;`
378			`genpc_refetch_cml_1 <= genpc_refetch;`
379			`no_more_dslot_cml_1 <= no_more_dslot;`
380			`pcreg_cml_1 <= pcreg;`
381			`pc_cml_1 <= pc;`
382			`genpc_refetch_r_cml_1 <= genpc_refetch_r;`
383			`end`
384			`endmodule`
385