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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_if.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.2  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_if_cm2(
                clk_i_cml_1,
 
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
 
        // Internal i/f
        if_freeze, if_insn, if_pc, flushpipe,
        if_stall, no_more_dslot, genpc_refetch, rfe,
        except_itlbmiss, except_immufault, except_ibuserr
);
 
 
input clk_i_cml_1;
reg  icpu_ack_i_cml_1;
reg [ 31 : 0 ] icpu_adr_i_cml_1;
reg  no_more_dslot_cml_1;
reg [ 31 : 0 ] insn_saved_cml_1;
reg [ 31 : 0 ] addr_saved_cml_1;
reg  saved_cml_1;
 
 
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
input   [31:0]                   icpu_dat_i;
input                           icpu_ack_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
input   [3:0]                    icpu_tag_i;
 
//
// Internal i/f
//
input                           if_freeze;
output  [31:0]                   if_insn;
output  [31:0]                   if_pc;
input                           flushpipe;
output                          if_stall;
input                           no_more_dslot;
output                          genpc_refetch;
input                           rfe;
output                          except_itlbmiss;
output                          except_immufault;
output                          except_ibuserr;
 
//
// Internal wires and regs
//
reg     [31:0]                   insn_saved;
reg     [31:0]                   addr_saved;
reg                             saved;
 
//
// IF stage insn
//
 
// SynEDA CoreMultiplier
// assignment(s): if_insn
// replace(s): icpu_ack_i, no_more_dslot, insn_saved, saved
assign if_insn = icpu_err_i | no_more_dslot_cml_1 | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved_cml_1 ? insn_saved_cml_1 : icpu_ack_i_cml_1 ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : icpu_adr_i;
// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
 
// SynEDA CoreMultiplier
// assignment(s): if_stall
// replace(s): icpu_ack_i, saved
assign if_stall = !icpu_err_i & !icpu_ack_i_cml_1 & !saved_cml_1;
assign genpc_refetch = saved & icpu_ack_i;
 
// SynEDA CoreMultiplier
// assignment(s): except_itlbmiss
// replace(s): no_more_dslot
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot_cml_1;
 
// SynEDA CoreMultiplier
// assignment(s): except_immufault
// replace(s): no_more_dslot
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot_cml_1;
 
// SynEDA CoreMultiplier
// assignment(s): except_ibuserr
// replace(s): no_more_dslot
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot_cml_1;
 
//
// Flag for saved insn/address
//
 
// SynEDA CoreMultiplier
// assignment(s): saved
// replace(s): icpu_ack_i, saved
always @(posedge clk or posedge rst)
        if (rst)
                saved <= #1 1'b0;
        else begin  saved <= saved_cml_1; if (flushpipe)
                saved <= #1 1'b0;
        else if (icpu_ack_i_cml_1 & if_freeze & !saved_cml_1)
                saved <= #1 1'b1;
        else if (!if_freeze)
                saved <= #1 1'b0; end
 
//
// Store fetched instruction
//
 
// SynEDA CoreMultiplier
// assignment(s): insn_saved
// replace(s): icpu_ack_i, insn_saved, saved
always @(posedge clk or posedge rst)
        if (rst)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
        else begin  insn_saved <= insn_saved_cml_1; if (flushpipe)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
        else if (icpu_ack_i_cml_1 & if_freeze & !saved_cml_1)
                insn_saved <= #1 icpu_dat_i;
        else if (!if_freeze)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; end
 
//
// Store fetched instruction's address
//
 
// SynEDA CoreMultiplier
// assignment(s): addr_saved
// replace(s): icpu_ack_i, icpu_adr_i, addr_saved, saved
always @(posedge clk or posedge rst)
        if (rst)
                addr_saved <= #1 32'h00000000;
        else begin  addr_saved <= addr_saved_cml_1; if (flushpipe)
                addr_saved <= #1 32'h00000000;
        else if (icpu_ack_i_cml_1 & if_freeze & !saved_cml_1)
                addr_saved <= #1 icpu_adr_i_cml_1;
        else if (!if_freeze)
                addr_saved <= #1 icpu_adr_i_cml_1; end
 
 
always @ (posedge clk_i_cml_1) begin
icpu_ack_i_cml_1 <= icpu_ack_i;
icpu_adr_i_cml_1 <= icpu_adr_i;
no_more_dslot_cml_1 <= no_more_dslot;
insn_saved_cml_1 <= insn_saved;
addr_saved_cml_1 <= addr_saved;
saved_cml_1 <= saved;
end
endmodule
 

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_if.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's instruction fetch ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, instruction fetch, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.3 2002/03/29 15:16:56 lampret`
48			`// Some of the warnings fixed.`
49			`//`
50			`// Revision 1.2 2002/01/28 01:16:00 lampret`
51			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
52			`//`
53			`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56			`// Revision 1.10 2001/11/20 18:46:15 simons`
57			`// Break point bug fixed`
58			`//`
59			`// Revision 1.9 2001/11/18 09:58:28 lampret`
60			`// Fixed some l.trap typos.`
61			`//`
62			`// Revision 1.8 2001/11/18 08:36:28 lampret`
63			`// For GDB changed single stepping and disabled trap exception.`
64			`//`
65			`// Revision 1.7 2001/10/21 17:57:16 lampret`
66			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
67			`//`
68			`// Revision 1.6 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.1 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`module or1200_if_cm2(`
85			`clk_i_cml_1,`
86
87			`// Clock and reset`
88			`clk, rst,`
89
90			`// External i/f to IC`
91			`icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,`
92
93			`// Internal i/f`
94			`if_freeze, if_insn, if_pc, flushpipe,`
95			`if_stall, no_more_dslot, genpc_refetch, rfe,`
96			`except_itlbmiss, except_immufault, except_ibuserr`
97			`);`
98
99
100			`input clk_i_cml_1;`
101			`reg icpu_ack_i_cml_1;`
102			`reg [ 31 : 0 ] icpu_adr_i_cml_1;`
103			`reg no_more_dslot_cml_1;`
104			`reg [ 31 : 0 ] insn_saved_cml_1;`
105			`reg [ 31 : 0 ] addr_saved_cml_1;`
106			`reg saved_cml_1;`
107
108
109
110			`//`
111			`// I/O`
112			`//`
113
114			`//`
115			`// Clock and reset`
116			`//`
117			`input clk;`
118			`input rst;`
119
120			`//`
121			`// External i/f to IC`
122			`//`
123			`input [31:0] icpu_dat_i;`
124			`input icpu_ack_i;`
125			`input icpu_err_i;`
126			`input [31:0] icpu_adr_i;`
127			`input [3:0] icpu_tag_i;`
128
129			`//`
130			`// Internal i/f`
131			`//`
132			`input if_freeze;`
133			`output [31:0] if_insn;`
134			`output [31:0] if_pc;`
135			`input flushpipe;`
136			`output if_stall;`
137			`input no_more_dslot;`
138			`output genpc_refetch;`
139			`input rfe;`
140			`output except_itlbmiss;`
141			`output except_immufault;`
142			`output except_ibuserr;`
143
144			`//`
145			`// Internal wires and regs`
146			`//`
147			`reg [31:0] insn_saved;`
148			`reg [31:0] addr_saved;`
149			`reg saved;`
150
151			`//`
152			`// IF stage insn`
153			`//`
154
155			`// SynEDA CoreMultiplier`
156			`// assignment(s): if_insn`
157			`// replace(s): icpu_ack_i, no_more_dslot, insn_saved, saved`
158			assign if_insn = icpu_err_i \| no_more_dslot_cml_1 \| rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved_cml_1 ? insn_saved_cml_1 : icpu_ack_i_cml_1 ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
159			`assign if_pc = saved ? addr_saved : icpu_adr_i;`
160			`// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;`
161
162			`// SynEDA CoreMultiplier`
163			`// assignment(s): if_stall`
164			`// replace(s): icpu_ack_i, saved`
165			`assign if_stall = !icpu_err_i & !icpu_ack_i_cml_1 & !saved_cml_1;`
166			`assign genpc_refetch = saved & icpu_ack_i;`
167
168			`// SynEDA CoreMultiplier`
169			`// assignment(s): except_itlbmiss`
170			`// replace(s): no_more_dslot`
171			assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot_cml_1;
172
173			`// SynEDA CoreMultiplier`
174			`// assignment(s): except_immufault`
175			`// replace(s): no_more_dslot`
176			assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot_cml_1;
177
178			`// SynEDA CoreMultiplier`
179			`// assignment(s): except_ibuserr`
180			`// replace(s): no_more_dslot`
181			assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot_cml_1;
182
183			`//`
184			`// Flag for saved insn/address`
185			`//`
186
187			`// SynEDA CoreMultiplier`
188			`// assignment(s): saved`
189			`// replace(s): icpu_ack_i, saved`
190			`always @(posedge clk or posedge rst)`
191			`if (rst)`
192			`saved <= #1 1'b0;`
193			`else begin saved <= saved_cml_1; if (flushpipe)`
194			`saved <= #1 1'b0;`
195			`else if (icpu_ack_i_cml_1 & if_freeze & !saved_cml_1)`
196			`saved <= #1 1'b1;`
197			`else if (!if_freeze)`
198			`saved <= #1 1'b0; end`
199
200			`//`
201			`// Store fetched instruction`
202			`//`
203
204			`// SynEDA CoreMultiplier`
205			`// assignment(s): insn_saved`
206			`// replace(s): icpu_ack_i, insn_saved, saved`
207			`always @(posedge clk or posedge rst)`
208			`if (rst)`
209			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
210			`else begin insn_saved <= insn_saved_cml_1; if (flushpipe)`
211			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
212			`else if (icpu_ack_i_cml_1 & if_freeze & !saved_cml_1)`
213			`insn_saved <= #1 icpu_dat_i;`
214			`else if (!if_freeze)`
215			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; end
216
217			`//`
218			`// Store fetched instruction's address`
219			`//`
220
221			`// SynEDA CoreMultiplier`
222			`// assignment(s): addr_saved`
223			`// replace(s): icpu_ack_i, icpu_adr_i, addr_saved, saved`
224			`always @(posedge clk or posedge rst)`
225			`if (rst)`
226			`addr_saved <= #1 32'h00000000;`
227			`else begin addr_saved <= addr_saved_cml_1; if (flushpipe)`
228			`addr_saved <= #1 32'h00000000;`
229			`else if (icpu_ack_i_cml_1 & if_freeze & !saved_cml_1)`
230			`addr_saved <= #1 icpu_adr_i_cml_1;`
231			`else if (!if_freeze)`
232			`addr_saved <= #1 icpu_adr_i_cml_1; end`
233
234
235			`always @ (posedge clk_i_cml_1) begin`
236			`icpu_ack_i_cml_1 <= icpu_ack_i;`
237			`icpu_adr_i_cml_1 <= icpu_adr_i;`
238			`no_more_dslot_cml_1 <= no_more_dslot;`
239			`insn_saved_cml_1 <= insn_saved;`
240			`addr_saved_cml_1 <= addr_saved;`
241			`saved_cml_1 <= saved;`
242			`end`
243			`endmodule`
244