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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/03/28 19:14:10  lampret
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mem2reg_cm2(
                clk_i_cml_1,
                addr, lsu_op, memdata, regdata);
 
 
input clk_i_cml_1;
reg [ 4 - 1 : 0 ] lsu_op_cml_1;
 
 
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// In the past faster implementation of mem2reg (today probably slower)
//
`ifdef OR1200_IMPL_MEM2REG2
 
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [3:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b01x, 2'b00}:                        // lbz/lbs 0
                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
                {3'b01x, 2'b01},                        // lbz/lbs 1
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
                {3'b01x, 2'b10}:                        // lbz/lbs 2
                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
                default:                                // all other cases
                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx}:                        // lbz
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00}:                        // lbs 0
                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10}:                        // lbs 2
                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
                default:                                // all other cases
                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr}) // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte0) // synopsys parallel_case infer_mux
`else
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte0) // synopsys parallel_case
`else
        case(sel_byte0) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_BYTE0: begin
                                regdata_ll = memdata[7:0];
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_ll = memdata[15:8];
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_ll = memdata[23:16];
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_BYTE3: begin
`endif
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte1) // synopsys parallel_case infer_mux
`else
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte1) // synopsys parallel_case
`else
        case(sel_byte1) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_lh = 8'h00;
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_lh = memdata[15:8];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_lh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_lh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_lh = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_lh = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte2) // synopsys parallel_case infer_mux
`else
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte2) // synopsys parallel_case
`else
        case(sel_byte2) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hl = 8'h00;
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_hl = memdata[23:16];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hl = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hl = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_hl = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte3) // synopsys parallel_case infer_mux
`else
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte3) // synopsys parallel_case
`else
        case(sel_byte3) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hh = 8'h00;
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_hh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hh = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                `OR1200_M2R_EXTB3: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_hh = {8{memdata[31]}};
                        end
        endcase
end
 
`else
 
//
// Straightforward implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(addr) // synopsys parallel_case infer_mux
`else
        case(addr) // synopsys parallel_case
`endif
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
 
// SynEDA CoreMultiplier
// assignment(s): regdata
// replace(s): lsu_op
always @(lsu_op_cml_1 or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(lsu_op_cml_1) // synopsys parallel_case infer_mux
`else
        case(lsu_op_cml_1) // synopsys parallel_case
`endif
                `OR1200_LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `OR1200_LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `OR1200_LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `OR1200_LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
 
always @ (posedge clk_i_cml_1) begin
lsu_op_cml_1 <= lsu_op;
end
endmodule
 

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.4 2002/03/29 15:16:56 lampret`
48			`// Some of the warnings fixed.`
49			`//`
50			`// Revision 1.3 2002/03/28 19:14:10 lampret`
51			`// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2`
52			`//`
53			`// Revision 1.2 2002/01/14 06:18:22 lampret`
54			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
55			`//`
56			`// Revision 1.1 2002/01/03 08:16:15 lampret`
57			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
58			`//`
59			`// Revision 1.9 2001/10/21 17:57:16 lampret`
60			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
61			`//`
62			`// Revision 1.8 2001/10/19 23:28:46 lampret`
63			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
64			`//`
65			`// Revision 1.7 2001/10/14 13:12:09 lampret`
66			`// MP3 version.`
67			`//`
68			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
69			`// no message`
70			`//`
71			`// Revision 1.2 2001/08/09 13:39:33 lampret`
72			`// Major clean-up.`
73			`//`
74			`// Revision 1.1 2001/07/20 00:46:03 lampret`
75			`// Development version of RTL. Libraries are missing.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`module or1200_mem2reg_cm2(`
85			`clk_i_cml_1,`
86			`addr, lsu_op, memdata, regdata);`
87
88
89			`input clk_i_cml_1;`
90			`reg [ 4 - 1 : 0 ] lsu_op_cml_1;`
91
92
93
94			parameter width = `OR1200_OPERAND_WIDTH;
95
96			`//`
97			`// I/O`
98			`//`
99			`input [1:0] addr;`
100			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
101			`input [width-1:0] memdata;`
102			`output [width-1:0] regdata;`
103
104
105			`//`
106			`// In the past faster implementation of mem2reg (today probably slower)`
107			`//`
108			`ifdef OR1200_IMPL_MEM2REG2
109
110			`define OR1200_M2R_BYTE0 4'b0000
111			`define OR1200_M2R_BYTE1 4'b0001
112			`define OR1200_M2R_BYTE2 4'b0010
113			`define OR1200_M2R_BYTE3 4'b0011
114			`define OR1200_M2R_EXTB0 4'b0100
115			`define OR1200_M2R_EXTB1 4'b0101
116			`define OR1200_M2R_EXTB2 4'b0110
117			`define OR1200_M2R_EXTB3 4'b0111
118			`define OR1200_M2R_ZERO 4'b0000
119
120			`reg [7:0] regdata_hh;`
121			`reg [7:0] regdata_hl;`
122			`reg [7:0] regdata_lh;`
123			`reg [7:0] regdata_ll;`
124			`reg [width-1:0] aligned;`
125			`reg [3:0] sel_byte0, sel_byte1,`
126			`sel_byte2, sel_byte3;`
127
128			`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
129
130			`//`
131			`// Byte select 0`
132			`//`
133			`always @(addr or lsu_op) begin`
134			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
135			`{3'b01x, 2'b00}: // lbz/lbs 0`
136			sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
137			`{3'b01x, 2'b01}, // lbz/lbs 1`
138			`{3'b10x, 2'b00}: // lhz/lhs 0`
139			sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
140			`{3'b01x, 2'b10}: // lbz/lbs 2`
141			sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
142			`default: // all other cases`
143			sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
144			`endcase`
145			`end`
146
147			`//`
148			`// Byte select 1`
149			`//`
150			`always @(addr or lsu_op) begin`
151			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
152			`{3'b010, 2'bxx}: // lbz`
153			sel_byte1 = `OR1200_M2R_ZERO; // zero extend
154			`{3'b011, 2'b00}: // lbs 0`
155			sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
156			`{3'b011, 2'b01}: // lbs 1`
157			sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
158			`{3'b011, 2'b10}: // lbs 2`
159			sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
160			`{3'b011, 2'b11}: // lbs 3`
161			sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
162			`{3'b10x, 2'b00}: // lhz/lhs 0`
163			sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
164			`default: // all other cases`
165			sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
166			`endcase`
167			`end`
168
169			`//`
170			`// Byte select 2`
171			`//`
172			`always @(addr or lsu_op) begin`
173			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
174			`{3'b010, 2'bxx}, // lbz`
175			`{3'b100, 2'bxx}: // lhz`
176			sel_byte2 = `OR1200_M2R_ZERO; // zero extend
177			`{3'b011, 2'b00}, // lbs 0`
178			`{3'b101, 2'b00}: // lhs 0`
179			sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
180			`{3'b011, 2'b01}: // lbs 1`
181			sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
182			`{3'b011, 2'b10}, // lbs 2`
183			`{3'b101, 2'b10}: // lhs 0`
184			sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
185			`{3'b011, 2'b11}: // lbs 3`
186			sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
187			`default: // all other cases`
188			sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
189			`endcase`
190			`end`
191
192			`//`
193			`// Byte select 3`
194			`//`
195			`always @(addr or lsu_op) begin`
196			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
197			`{3'b010, 2'bxx}, // lbz`
198			`{3'b100, 2'bxx}: // lhz`
199			sel_byte3 = `OR1200_M2R_ZERO; // zero extend
200			`{3'b011, 2'b00}, // lbs 0`
201			`{3'b101, 2'b00}: // lhs 0`
202			sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
203			`{3'b011, 2'b01}: // lbs 1`
204			sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
205			`{3'b011, 2'b10}, // lbs 2`
206			`{3'b101, 2'b10}: // lhs 0`
207			sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
208			`{3'b011, 2'b11}: // lbs 3`
209			sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
210			`default: // all other cases`
211			sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
212			`endcase`
213			`end`
214
215			`//`
216			`// Byte 0`
217			`//`
218			`always @(sel_byte0 or memdata) begin`
219			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
220			`ifdef OR1200_CASE_DEFAULT
221			`case(sel_byte0) // synopsys parallel_case infer_mux`
222			`else
223			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
224			`endif
225			`else
226			`ifdef OR1200_CASE_DEFAULT
227			`case(sel_byte0) // synopsys parallel_case`
228			`else
229			`case(sel_byte0) // synopsys full_case parallel_case`
230			`endif
231			`endif
232			`OR1200_M2R_BYTE0: begin
233			`regdata_ll = memdata[7:0];`
234			`end`
235			`OR1200_M2R_BYTE1: begin
236			`regdata_ll = memdata[15:8];`
237			`end`
238			`OR1200_M2R_BYTE2: begin
239			`regdata_ll = memdata[23:16];`
240			`end`
241			`ifdef OR1200_CASE_DEFAULT
242			`default: begin`
243			`else
244			`OR1200_M2R_BYTE3: begin
245			`endif
246			`regdata_ll = memdata[31:24];`
247			`end`
248			`endcase`
249			`end`
250
251			`//`
252			`// Byte 1`
253			`//`
254			`always @(sel_byte1 or memdata) begin`
255			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
256			`ifdef OR1200_CASE_DEFAULT
257			`case(sel_byte1) // synopsys parallel_case infer_mux`
258			`else
259			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
260			`endif
261			`else
262			`ifdef OR1200_CASE_DEFAULT
263			`case(sel_byte1) // synopsys parallel_case`
264			`else
265			`case(sel_byte1) // synopsys full_case parallel_case`
266			`endif
267			`endif
268			`OR1200_M2R_ZERO: begin
269			`regdata_lh = 8'h00;`
270			`end`
271			`OR1200_M2R_BYTE1: begin
272			`regdata_lh = memdata[15:8];`
273			`end`
274			`OR1200_M2R_BYTE3: begin
275			`regdata_lh = memdata[31:24];`
276			`end`
277			`OR1200_M2R_EXTB0: begin
278			`regdata_lh = {8{memdata[7]}};`
279			`end`
280			`OR1200_M2R_EXTB1: begin
281			`regdata_lh = {8{memdata[15]}};`
282			`end`
283			`OR1200_M2R_EXTB2: begin
284			`regdata_lh = {8{memdata[23]}};`
285			`end`
286			`ifdef OR1200_CASE_DEFAULT
287			`default: begin`
288			`else
289			`OR1200_M2R_EXTB3: begin
290			`endif
291			`regdata_lh = {8{memdata[31]}};`
292			`end`
293			`endcase`
294			`end`
295
296			`//`
297			`// Byte 2`
298			`//`
299			`always @(sel_byte2 or memdata) begin`
300			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
301			`ifdef OR1200_CASE_DEFAULT
302			`case(sel_byte2) // synopsys parallel_case infer_mux`
303			`else
304			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
305			`endif
306			`else
307			`ifdef OR1200_CASE_DEFAULT
308			`case(sel_byte2) // synopsys parallel_case`
309			`else
310			`case(sel_byte2) // synopsys full_case parallel_case`
311			`endif
312			`endif
313			`OR1200_M2R_ZERO: begin
314			`regdata_hl = 8'h00;`
315			`end`
316			`OR1200_M2R_BYTE2: begin
317			`regdata_hl = memdata[23:16];`
318			`end`
319			`OR1200_M2R_EXTB0: begin
320			`regdata_hl = {8{memdata[7]}};`
321			`end`
322			`OR1200_M2R_EXTB1: begin
323			`regdata_hl = {8{memdata[15]}};`
324			`end`
325			`OR1200_M2R_EXTB2: begin
326			`regdata_hl = {8{memdata[23]}};`
327			`end`
328			`ifdef OR1200_CASE_DEFAULT
329			`default: begin`
330			`else
331			`OR1200_M2R_EXTB3: begin
332			`endif
333			`regdata_hl = {8{memdata[31]}};`
334			`end`
335			`endcase`
336			`end`
337
338			`//`
339			`// Byte 3`
340			`//`
341			`always @(sel_byte3 or memdata) begin`
342			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
343			`ifdef OR1200_CASE_DEFAULT
344			`case(sel_byte3) // synopsys parallel_case infer_mux`
345			`else
346			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
347			`endif
348			`else
349			`ifdef OR1200_CASE_DEFAULT
350			`case(sel_byte3) // synopsys parallel_case`
351			`else
352			`case(sel_byte3) // synopsys full_case parallel_case`
353			`endif
354			`endif
355			`OR1200_M2R_ZERO: begin
356			`regdata_hh = 8'h00;`
357			`end`
358			`OR1200_M2R_BYTE3: begin
359			`regdata_hh = memdata[31:24];`
360			`end`
361			`OR1200_M2R_EXTB0: begin
362			`regdata_hh = {8{memdata[7]}};`
363			`end`
364			`OR1200_M2R_EXTB1: begin
365			`regdata_hh = {8{memdata[15]}};`
366			`end`
367			`OR1200_M2R_EXTB2: begin
368			`regdata_hh = {8{memdata[23]}};`
369			`end`
370			`ifdef OR1200_CASE_DEFAULT
371			`OR1200_M2R_EXTB3: begin
372			`else
373			`OR1200_M2R_EXTB3: begin
374			`endif
375			`regdata_hh = {8{memdata[31]}};`
376			`end`
377			`endcase`
378			`end`
379
380			`else
381
382			`//`
383			`// Straightforward implementation of mem2reg`
384			`//`
385
386			`reg [width-1:0] regdata;`
387			`reg [width-1:0] aligned;`
388
389			`//`
390			`// Alignment`
391			`//`
392			`always @(addr or memdata) begin`
393			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
394			`case(addr) // synopsys parallel_case infer_mux`
395			`else
396			`case(addr) // synopsys parallel_case`
397			`endif
398			`2'b00:`
399			`aligned = memdata;`
400			`2'b01:`
401			`aligned = {memdata[23:0], 8'b0};`
402			`2'b10:`
403			`aligned = {memdata[15:0], 16'b0};`
404			`2'b11:`
405			`aligned = {memdata[7:0], 24'b0};`
406			`endcase`
407			`end`
408
409			`//`
410			`// Bytes`
411			`//`
412
413			`// SynEDA CoreMultiplier`
414			`// assignment(s): regdata`
415			`// replace(s): lsu_op`
416			`always @(lsu_op_cml_1 or aligned) begin`
417			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
418			`case(lsu_op_cml_1) // synopsys parallel_case infer_mux`
419			`else
420			`case(lsu_op_cml_1) // synopsys parallel_case`
421			`endif
422			`OR1200_LSUOP_LBZ: begin
423			`regdata[7:0] = aligned[31:24];`
424			`regdata[31:8] = 24'b0;`
425			`end`
426			`OR1200_LSUOP_LBS: begin
427			`regdata[7:0] = aligned[31:24];`
428			`regdata[31:8] = {24{aligned[31]}};`
429			`end`
430			`OR1200_LSUOP_LHZ: begin
431			`regdata[15:0] = aligned[31:16];`
432			`regdata[31:16] = 16'b0;`
433			`end`
434			`OR1200_LSUOP_LHS: begin
435			`regdata[15:0] = aligned[31:16];`
436			`regdata[31:16] = {16{aligned[31]}};`
437			`end`
438			`default:`
439			`regdata = aligned;`
440			`endcase`
441			`end`
442
443			`endif
444
445
446			`always @ (posedge clk_i_cml_1) begin`
447			`lsu_op_cml_1 <= lsu_op;`
448			`end`
449			`endmodule`
450