URL https://opencores.org/ocsvn/or1200_hp/or1200_hp/trunk

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm3/] [verilog/] [or1200_qmem_top.v] - Blame information for rev 2

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Embedded Memory                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Embedded Memory               .                             ////
////                                                              ////
////  To Do:                                                      ////
////   - QMEM and IC/DC muxes can be removed except for cycstb    ////
////     (now are is there for easier debugging)                  ////
////   - currently arbitration is slow and stores take 2 clocks   ////
////     (final debugged version will be faster)                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2003 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2004/04/05 08:40:26  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.1.2.4  2004/01/11 22:45:46  andreje
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
//
// Revision 1.1.2.3  2003/12/17 13:36:58  simons
// Qmem mbist signals fixed.
//
// Revision 1.1.2.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.1.2.1  2003/07/08 15:45:26  lampret
// Added embedded memory QMEM.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_QMEMFSM_IDLE     3'd0
`define OR1200_QMEMFSM_STORE    3'd1
`define OR1200_QMEMFSM_LOAD     3'd2
`define OR1200_QMEMFSM_FETCH    3'd3
 
//
// Embedded memory
//
module or1200_qmem_top_cm3(
                clk_i_cml_1,
                clk_i_cml_2,
 
        // Rst, clk and clock control
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // QMEM and CPU/IMMU
        qmemimmu_adr_i,
        qmemimmu_cycstb_i,
        qmemimmu_ci_i,
        qmemicpu_sel_i,
        qmemicpu_tag_i,
        qmemicpu_dat_o,
        qmemicpu_ack_o,
        qmemimmu_rty_o,
        qmemimmu_err_o,
        qmemimmu_tag_o,
 
        // QMEM and IC
        icqmem_adr_o,
        icqmem_cycstb_o,
        icqmem_ci_o,
        icqmem_sel_o,
        icqmem_tag_o,
        icqmem_dat_i,
        icqmem_ack_i,
        icqmem_rty_i,
        icqmem_err_i,
        icqmem_tag_i,
 
        // QMEM and CPU/DMMU
        qmemdmmu_adr_i,
        qmemdmmu_cycstb_i,
        qmemdmmu_ci_i,
        qmemdcpu_we_i,
        qmemdcpu_sel_i,
        qmemdcpu_tag_i,
        qmemdcpu_dat_i,
        qmemdcpu_dat_o,
        qmemdcpu_ack_o,
        qmemdcpu_rty_o,
        qmemdmmu_err_o,
        qmemdmmu_tag_o,
 
        // QMEM and DC
        dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,
        dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,
        dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i
 
);
 
 
input clk_i_cml_1;
input clk_i_cml_2;
reg  icqmem_err_i_cml_1;
reg  qmemdmmu_ci_i_cml_1;
reg  qmemdcpu_we_i_cml_2;
 
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// QMEM and CPU/IMMU
//
input   [31:0]                   qmemimmu_adr_i;
input                           qmemimmu_cycstb_i;
input                           qmemimmu_ci_i;
input   [3:0]                    qmemicpu_sel_i;
input   [3:0]                    qmemicpu_tag_i;
output  [31:0]                   qmemicpu_dat_o;
output                          qmemicpu_ack_o;
output                          qmemimmu_rty_o;
output                          qmemimmu_err_o;
output  [3:0]                    qmemimmu_tag_o;
 
//
// QMEM and IC
//
output  [31:0]                   icqmem_adr_o;
output                          icqmem_cycstb_o;
output                          icqmem_ci_o;
output  [3:0]                    icqmem_sel_o;
output  [3:0]                    icqmem_tag_o;
input   [31:0]                   icqmem_dat_i;
input                           icqmem_ack_i;
input                           icqmem_rty_i;
input                           icqmem_err_i;
input   [3:0]                    icqmem_tag_i;
 
//
// QMEM and CPU/DMMU
//
input   [31:0]                   qmemdmmu_adr_i;
input                           qmemdmmu_cycstb_i;
input                           qmemdmmu_ci_i;
input                           qmemdcpu_we_i;
input   [3:0]                    qmemdcpu_sel_i;
input   [3:0]                    qmemdcpu_tag_i;
input   [31:0]                   qmemdcpu_dat_i;
output  [31:0]                   qmemdcpu_dat_o;
output                          qmemdcpu_ack_o;
output                          qmemdcpu_rty_o;
output                          qmemdmmu_err_o;
output  [3:0]                    qmemdmmu_tag_o;
 
//
// QMEM and DC
//
output  [31:0]                   dcqmem_adr_o;
output                          dcqmem_cycstb_o;
output                          dcqmem_ci_o;
output                          dcqmem_we_o;
output  [3:0]                    dcqmem_sel_o;
output  [3:0]                    dcqmem_tag_o;
output  [dw-1:0]         dcqmem_dat_o;
input   [dw-1:0]         dcqmem_dat_i;
input                           dcqmem_ack_i;
input                           dcqmem_rty_i;
input                           dcqmem_err_i;
input   [3:0]                    dcqmem_tag_i;
 
`ifdef OR1200_QMEM_IMPLEMENTED
 
//
// Internal regs and wires
//
wire                            iaddr_qmem_hit;
wire                            daddr_qmem_hit;
reg     [2:0]                    state;
reg                             qmem_dack;
reg                             qmem_iack;
wire    [31:0]                   qmem_di;
wire    [31:0]                   qmem_do;
wire                            qmem_en;
wire                            qmem_we;
`ifdef OR1200_QMEM_BSEL
wire  [3:0]       qmem_sel;
`endif
wire    [31:0]                   qmem_addr;
`ifdef OR1200_QMEM_ACK
wire              qmem_ack;
`else
wire              qmem_ack = 1'b1;
`endif
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;
assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;
assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;
assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;
assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;
assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;
assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;
assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;
assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;
assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
 
//
// Address comparison whether QMEM was hit
//
`ifdef OR1200_QMEM_IADDR
assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) == `OR1200_QMEM_IADDR;
`else
assign iaddr_qmem_hit = 1'b0;
`endif
 
`ifdef OR1200_QMEM_DADDR
assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) == `OR1200_QMEM_DADDR;
`else
assign daddr_qmem_hit = 1'b0;
`endif
 
//
//
//
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
`ifdef OR1200_QMEM_BSEL
assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i : qmemicpu_sel_i;
`endif
assign qmem_di = qmemdcpu_dat_i;
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
 
//
// QMEM control FSM
//
always @(posedge rst or posedge clk)
        if (rst) begin
                state <= #1 `OR1200_QMEMFSM_IDLE;
                qmem_dack <= #1 1'b0;
                qmem_iack <= #1 1'b0;
        end
        else case (state)       // synopsys parallel_case
                `OR1200_QMEMFSM_IDLE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_STORE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_LOAD: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                `OR1200_QMEMFSM_FETCH: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_iack <= #1 1'b0;
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_dack <= #1 1'b0;
                        end
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_iack <= #1 1'b0;
                        end
                end
                default: begin
                        state <= #1 `OR1200_QMEMFSM_IDLE;
                        qmem_dack <= #1 1'b0;
                        qmem_iack <= #1 1'b0;
                end
        endcase
 
//
// Instantiation of embedded memory
//
or1200_spram_2048x32 or1200_qmem_ram(
        .clk(clk),
        .rst(rst),
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .addr(qmem_addr[12:2]),
`ifdef OR1200_QMEM_BSEL
        .sel(qmem_sel),
`endif
`ifdef OR1200_QMEM_ACK
  .ack(qmem_ack),
`endif
  .ce(qmem_en),
        .we(qmem_we),
        .oe(1'b1),
        .di(qmem_di),
        .doq(qmem_do)
);
 
`else  // OR1200_QMEM_IMPLEMENTED
 
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = icqmem_dat_i;
assign qmemicpu_ack_o = icqmem_ack_i;
assign qmemimmu_rty_o = icqmem_rty_i;
 
// SynEDA CoreMultiplier
// assignment(s): qmemimmu_err_o
// replace(s): icqmem_err_i
assign qmemimmu_err_o = icqmem_err_i_cml_1;
assign qmemimmu_tag_o = icqmem_tag_i;
 
//
// QMEM and IC
//
assign icqmem_adr_o = qmemimmu_adr_i;
assign icqmem_cycstb_o = qmemimmu_cycstb_i;
assign icqmem_ci_o = qmemimmu_ci_i;
assign icqmem_sel_o = qmemicpu_sel_i;
assign icqmem_tag_o = qmemicpu_tag_i;
 
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = dcqmem_dat_i;
assign qmemdcpu_ack_o = dcqmem_ack_i;
assign qmemdcpu_rty_o = dcqmem_rty_i;
assign qmemdmmu_err_o = dcqmem_err_i;
assign qmemdmmu_tag_o = dcqmem_tag_i;
 
//
// QMEM and DC
//
assign dcqmem_adr_o = qmemdmmu_adr_i;
assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;
 
// SynEDA CoreMultiplier
// assignment(s): dcqmem_ci_o
// replace(s): qmemdmmu_ci_i
assign dcqmem_ci_o = qmemdmmu_ci_i_cml_1;
 
// SynEDA CoreMultiplier
// assignment(s): dcqmem_we_o
// replace(s): qmemdcpu_we_i
assign dcqmem_we_o = qmemdcpu_we_i_cml_2;
assign dcqmem_sel_o = qmemdcpu_sel_i;
assign dcqmem_tag_o = qmemdcpu_tag_i;
assign dcqmem_dat_o = qmemdcpu_dat_i;
 
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`endif
 
 
always @ (posedge clk_i_cml_1) begin
icqmem_err_i_cml_1 <= icqmem_err_i;
qmemdmmu_ci_i_cml_1 <= qmemdmmu_ci_i;
end
always @ (posedge clk_i_cml_2) begin
qmemdcpu_we_i_cml_2 <= qmemdcpu_we_i;
end
endmodule
 

Browse

Tools

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm3/] [verilog/] [or1200_qmem_top.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Embedded Memory ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Embedded Memory . ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - QMEM and IC/DC muxes can be removed except for cycstb ////`
13			`//// (now are is there for easier debugging) ////`
14			`//// - currently arbitration is slow and stores take 2 clocks ////`
15			`//// (final debugged version will be faster) ////`
16			`//// ////`
17			`//// Author(s): ////`
18			`//// - Damjan Lampret, lampret@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2003 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`// Revision 1.2 2004/04/05 08:40:26 lampret`
51			`// Merged branch_qmem into main tree.`
52			`//`
53			`// Revision 1.1.2.4 2004/01/11 22:45:46 andreje`
54			`// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added`
55			`//`
56			`// Revision 1.1.2.3 2003/12/17 13:36:58 simons`
57			`// Qmem mbist signals fixed.`
58			`//`
59			`// Revision 1.1.2.2 2003/12/09 11:46:48 simons`
60			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
61			`//`
62			`// Revision 1.1.2.1 2003/07/08 15:45:26 lampret`
63			`// Added embedded memory QMEM.`
64			`//`
65			`//`
66
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "or1200_defines.v"
71
72			`define OR1200_QMEMFSM_IDLE 3'd0
73			`define OR1200_QMEMFSM_STORE 3'd1
74			`define OR1200_QMEMFSM_LOAD 3'd2
75			`define OR1200_QMEMFSM_FETCH 3'd3
76
77			`//`
78			`// Embedded memory`
79			`//`
80			`module or1200_qmem_top_cm3(`
81			`clk_i_cml_1,`
82			`clk_i_cml_2,`
83
84			`// Rst, clk and clock control`
85			`clk, rst,`
86
87			`ifdef OR1200_BIST
88			`// RAM BIST`
89			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
90			`endif
91
92			`// QMEM and CPU/IMMU`
93			`qmemimmu_adr_i,`
94			`qmemimmu_cycstb_i,`
95			`qmemimmu_ci_i,`
96			`qmemicpu_sel_i,`
97			`qmemicpu_tag_i,`
98			`qmemicpu_dat_o,`
99			`qmemicpu_ack_o,`
100			`qmemimmu_rty_o,`
101			`qmemimmu_err_o,`
102			`qmemimmu_tag_o,`
103
104			`// QMEM and IC`
105			`icqmem_adr_o,`
106			`icqmem_cycstb_o,`
107			`icqmem_ci_o,`
108			`icqmem_sel_o,`
109			`icqmem_tag_o,`
110			`icqmem_dat_i,`
111			`icqmem_ack_i,`
112			`icqmem_rty_i,`
113			`icqmem_err_i,`
114			`icqmem_tag_i,`
115
116			`// QMEM and CPU/DMMU`
117			`qmemdmmu_adr_i,`
118			`qmemdmmu_cycstb_i,`
119			`qmemdmmu_ci_i,`
120			`qmemdcpu_we_i,`
121			`qmemdcpu_sel_i,`
122			`qmemdcpu_tag_i,`
123			`qmemdcpu_dat_i,`
124			`qmemdcpu_dat_o,`
125			`qmemdcpu_ack_o,`
126			`qmemdcpu_rty_o,`
127			`qmemdmmu_err_o,`
128			`qmemdmmu_tag_o,`
129
130			`// QMEM and DC`
131			`dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,`
132			`dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,`
133			`dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i`
134
135			`);`
136
137
138			`input clk_i_cml_1;`
139			`input clk_i_cml_2;`
140			`reg icqmem_err_i_cml_1;`
141			`reg qmemdmmu_ci_i_cml_1;`
142			`reg qmemdcpu_we_i_cml_2;`
143
144
145
146			parameter dw = `OR1200_OPERAND_WIDTH;
147
148			`//`
149			`// I/O`
150			`//`
151
152			`//`
153			`// Clock and reset`
154			`//`
155			`input clk;`
156			`input rst;`
157
158			`ifdef OR1200_BIST
159			`//`
160			`// RAM BIST`
161			`//`
162			`input mbist_si_i;`
163			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
164			`output mbist_so_o;`
165			`endif
166
167			`//`
168			`// QMEM and CPU/IMMU`
169			`//`
170			`input [31:0] qmemimmu_adr_i;`
171			`input qmemimmu_cycstb_i;`
172			`input qmemimmu_ci_i;`
173			`input [3:0] qmemicpu_sel_i;`
174			`input [3:0] qmemicpu_tag_i;`
175			`output [31:0] qmemicpu_dat_o;`
176			`output qmemicpu_ack_o;`
177			`output qmemimmu_rty_o;`
178			`output qmemimmu_err_o;`
179			`output [3:0] qmemimmu_tag_o;`
180
181			`//`
182			`// QMEM and IC`
183			`//`
184			`output [31:0] icqmem_adr_o;`
185			`output icqmem_cycstb_o;`
186			`output icqmem_ci_o;`
187			`output [3:0] icqmem_sel_o;`
188			`output [3:0] icqmem_tag_o;`
189			`input [31:0] icqmem_dat_i;`
190			`input icqmem_ack_i;`
191			`input icqmem_rty_i;`
192			`input icqmem_err_i;`
193			`input [3:0] icqmem_tag_i;`
194
195			`//`
196			`// QMEM and CPU/DMMU`
197			`//`
198			`input [31:0] qmemdmmu_adr_i;`
199			`input qmemdmmu_cycstb_i;`
200			`input qmemdmmu_ci_i;`
201			`input qmemdcpu_we_i;`
202			`input [3:0] qmemdcpu_sel_i;`
203			`input [3:0] qmemdcpu_tag_i;`
204			`input [31:0] qmemdcpu_dat_i;`
205			`output [31:0] qmemdcpu_dat_o;`
206			`output qmemdcpu_ack_o;`
207			`output qmemdcpu_rty_o;`
208			`output qmemdmmu_err_o;`
209			`output [3:0] qmemdmmu_tag_o;`
210
211			`//`
212			`// QMEM and DC`
213			`//`
214			`output [31:0] dcqmem_adr_o;`
215			`output dcqmem_cycstb_o;`
216			`output dcqmem_ci_o;`
217			`output dcqmem_we_o;`
218			`output [3:0] dcqmem_sel_o;`
219			`output [3:0] dcqmem_tag_o;`
220			`output [dw-1:0] dcqmem_dat_o;`
221			`input [dw-1:0] dcqmem_dat_i;`
222			`input dcqmem_ack_i;`
223			`input dcqmem_rty_i;`
224			`input dcqmem_err_i;`
225			`input [3:0] dcqmem_tag_i;`
226
227			`ifdef OR1200_QMEM_IMPLEMENTED
228
229			`//`
230			`// Internal regs and wires`
231			`//`
232			`wire iaddr_qmem_hit;`
233			`wire daddr_qmem_hit;`
234			`reg [2:0] state;`
235			`reg qmem_dack;`
236			`reg qmem_iack;`
237			`wire [31:0] qmem_di;`
238			`wire [31:0] qmem_do;`
239			`wire qmem_en;`
240			`wire qmem_we;`
241			`ifdef OR1200_QMEM_BSEL
242			`wire [3:0] qmem_sel;`
243			`endif
244			`wire [31:0] qmem_addr;`
245			`ifdef OR1200_QMEM_ACK
246			`wire qmem_ack;`
247			`else
248			`wire qmem_ack = 1'b1;`
249			`endif
250
251			`//`
252			`// QMEM and CPU/IMMU`
253			`//`
254			`assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;`
255			`assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;`
256			`assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;`
257			`assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;`
258			`assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;`
259
260			`//`
261			`// QMEM and IC`
262			`//`
263			`assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;`
264			`assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;`
265			`assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;`
266			`assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;`
267			`assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;`
268
269			`//`
270			`// QMEM and CPU/DMMU`
271			`//`
272			`assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;`
273			`assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;`
274			`assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;`
275			`assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;`
276			`assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;`
277
278			`//`
279			`// QMEM and DC`
280			`//`
281			`assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;`
282			`assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;`
283			`assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;`
284			`assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;`
285			`assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;`
286			`assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;`
287			`assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;`
288
289			`//`
290			`// Address comparison whether QMEM was hit`
291			`//`
292			`ifdef OR1200_QMEM_IADDR
293			assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) == `OR1200_QMEM_IADDR;
294			`else
295			`assign iaddr_qmem_hit = 1'b0;`
296			`endif
297
298			`ifdef OR1200_QMEM_DADDR
299			assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) == `OR1200_QMEM_DADDR;
300			`else
301			`assign daddr_qmem_hit = 1'b0;`
302			`endif
303
304			`//`
305			`//`
306			`//`
307			`assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i \| daddr_qmem_hit & qmemdmmu_cycstb_i;`
308			`assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;`
309			`ifdef OR1200_QMEM_BSEL
310			`assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i : qmemicpu_sel_i;`
311			`endif
312			`assign qmem_di = qmemdcpu_dat_i;`
313			`assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;`
314
315			`//`
316			`// QMEM control FSM`
317			`//`
318			`always @(posedge rst or posedge clk)`
319			`if (rst) begin`
320			state <= #1 `OR1200_QMEMFSM_IDLE;
321			`qmem_dack <= #1 1'b0;`
322			`qmem_iack <= #1 1'b0;`
323			`end`
324			`else case (state) // synopsys parallel_case`
325			`OR1200_QMEMFSM_IDLE: begin
326			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
327			state <= #1 `OR1200_QMEMFSM_STORE;
328			`qmem_dack <= #1 1'b1;`
329			`qmem_iack <= #1 1'b0;`
330			`end`
331			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
332			state <= #1 `OR1200_QMEMFSM_LOAD;
333			`qmem_dack <= #1 1'b1;`
334			`qmem_iack <= #1 1'b0;`
335			`end`
336			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
337			state <= #1 `OR1200_QMEMFSM_FETCH;
338			`qmem_iack <= #1 1'b1;`
339			`qmem_dack <= #1 1'b0;`
340			`end`
341			`end`
342			`OR1200_QMEMFSM_STORE: begin
343			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
344			state <= #1 `OR1200_QMEMFSM_STORE;
345			`qmem_dack <= #1 1'b1;`
346			`qmem_iack <= #1 1'b0;`
347			`end`
348			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
349			state <= #1 `OR1200_QMEMFSM_LOAD;
350			`qmem_dack <= #1 1'b1;`
351			`qmem_iack <= #1 1'b0;`
352			`end`
353			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
354			state <= #1 `OR1200_QMEMFSM_FETCH;
355			`qmem_iack <= #1 1'b1;`
356			`qmem_dack <= #1 1'b0;`
357			`end`
358			`else begin`
359			state <= #1 `OR1200_QMEMFSM_IDLE;
360			`qmem_dack <= #1 1'b0;`
361			`qmem_iack <= #1 1'b0;`
362			`end`
363			`end`
364			`OR1200_QMEMFSM_LOAD: begin
365			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
366			state <= #1 `OR1200_QMEMFSM_STORE;
367			`qmem_dack <= #1 1'b1;`
368			`qmem_iack <= #1 1'b0;`
369			`end`
370			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
371			state <= #1 `OR1200_QMEMFSM_LOAD;
372			`qmem_dack <= #1 1'b1;`
373			`qmem_iack <= #1 1'b0;`
374			`end`
375			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
376			state <= #1 `OR1200_QMEMFSM_FETCH;
377			`qmem_iack <= #1 1'b1;`
378			`qmem_dack <= #1 1'b0;`
379			`end`
380			`else begin`
381			state <= #1 `OR1200_QMEMFSM_IDLE;
382			`qmem_dack <= #1 1'b0;`
383			`qmem_iack <= #1 1'b0;`
384			`end`
385			`end`
386			`OR1200_QMEMFSM_FETCH: begin
387			`if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin`
388			state <= #1 `OR1200_QMEMFSM_STORE;
389			`qmem_dack <= #1 1'b1;`
390			`qmem_iack <= #1 1'b0;`
391			`end`
392			`else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin`
393			state <= #1 `OR1200_QMEMFSM_LOAD;
394			`qmem_dack <= #1 1'b1;`
395			`qmem_iack <= #1 1'b0;`
396			`end`
397			`else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin`
398			state <= #1 `OR1200_QMEMFSM_FETCH;
399			`qmem_iack <= #1 1'b1;`
400			`qmem_dack <= #1 1'b0;`
401			`end`
402			`else begin`
403			state <= #1 `OR1200_QMEMFSM_IDLE;
404			`qmem_dack <= #1 1'b0;`
405			`qmem_iack <= #1 1'b0;`
406			`end`
407			`end`
408			`default: begin`
409			state <= #1 `OR1200_QMEMFSM_IDLE;
410			`qmem_dack <= #1 1'b0;`
411			`qmem_iack <= #1 1'b0;`
412			`end`
413			`endcase`
414
415			`//`
416			`// Instantiation of embedded memory`
417			`//`
418			`or1200_spram_2048x32 or1200_qmem_ram(`
419			`.clk(clk),`
420			`.rst(rst),`
421			`ifdef OR1200_BIST
422			`// RAM BIST`
423			`.mbist_si_i(mbist_si_i),`
424			`.mbist_so_o(mbist_so_o),`
425			`.mbist_ctrl_i(mbist_ctrl_i),`
426			`endif
427			`.addr(qmem_addr[12:2]),`
428			`ifdef OR1200_QMEM_BSEL
429			`.sel(qmem_sel),`
430			`endif
431			`ifdef OR1200_QMEM_ACK
432			`.ack(qmem_ack),`
433			`endif
434			`.ce(qmem_en),`
435			`.we(qmem_we),`
436			`.oe(1'b1),`
437			`.di(qmem_di),`
438			`.doq(qmem_do)`
439			`);`
440
441			`else // OR1200_QMEM_IMPLEMENTED
442
443			`//`
444			`// QMEM and CPU/IMMU`
445			`//`
446			`assign qmemicpu_dat_o = icqmem_dat_i;`
447			`assign qmemicpu_ack_o = icqmem_ack_i;`
448			`assign qmemimmu_rty_o = icqmem_rty_i;`
449
450			`// SynEDA CoreMultiplier`
451			`// assignment(s): qmemimmu_err_o`
452			`// replace(s): icqmem_err_i`
453			`assign qmemimmu_err_o = icqmem_err_i_cml_1;`
454			`assign qmemimmu_tag_o = icqmem_tag_i;`
455
456			`//`
457			`// QMEM and IC`
458			`//`
459			`assign icqmem_adr_o = qmemimmu_adr_i;`
460			`assign icqmem_cycstb_o = qmemimmu_cycstb_i;`
461			`assign icqmem_ci_o = qmemimmu_ci_i;`
462			`assign icqmem_sel_o = qmemicpu_sel_i;`
463			`assign icqmem_tag_o = qmemicpu_tag_i;`
464
465			`//`
466			`// QMEM and CPU/DMMU`
467			`//`
468			`assign qmemdcpu_dat_o = dcqmem_dat_i;`
469			`assign qmemdcpu_ack_o = dcqmem_ack_i;`
470			`assign qmemdcpu_rty_o = dcqmem_rty_i;`
471			`assign qmemdmmu_err_o = dcqmem_err_i;`
472			`assign qmemdmmu_tag_o = dcqmem_tag_i;`
473
474			`//`
475			`// QMEM and DC`
476			`//`
477			`assign dcqmem_adr_o = qmemdmmu_adr_i;`
478			`assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;`
479
480			`// SynEDA CoreMultiplier`
481			`// assignment(s): dcqmem_ci_o`
482			`// replace(s): qmemdmmu_ci_i`
483			`assign dcqmem_ci_o = qmemdmmu_ci_i_cml_1;`
484
485			`// SynEDA CoreMultiplier`
486			`// assignment(s): dcqmem_we_o`
487			`// replace(s): qmemdcpu_we_i`
488			`assign dcqmem_we_o = qmemdcpu_we_i_cml_2;`
489			`assign dcqmem_sel_o = qmemdcpu_sel_i;`
490			`assign dcqmem_tag_o = qmemdcpu_tag_i;`
491			`assign dcqmem_dat_o = qmemdcpu_dat_i;`
492
493			`ifdef OR1200_BIST
494			`assign mbist_so_o = mbist_si_i;`
495			`endif
496
497			`endif
498
499
500			`always @ (posedge clk_i_cml_1) begin`
501			`icqmem_err_i_cml_1 <= icqmem_err_i;`
502			`qmemdmmu_ci_i_cml_1 <= qmemdmmu_ci_i;`
503			`end`
504			`always @ (posedge clk_i_cml_2) begin`
505			`qmemdcpu_we_i_cml_2 <= qmemdcpu_we_i;`
506			`end`
507			`endmodule`
508