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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_dmmu_tlb.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Data TLB                                           ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of DTLB.                                      ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.6  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.4.4.1  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.4  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.3  2002/02/11 04:33:17  lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.2  2002/01/28 01:16:00  lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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//
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// Data TLB
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//
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module or1200_dmmu_tlb(
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        // Rst and clk
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        clk, rst,
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        // I/F for translation
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        tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
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`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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        // SPR access
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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108
//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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//
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// I/F for translation
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//
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input                           tlb_en;
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input   [aw-1:0]         vaddr;
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output                          hit;
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output  [31:`OR1200_DMMU_PS]    ppn;
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output                          uwe;
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output                          ure;
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output                          swe;
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output                          sre;
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output                          ci;
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127
`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// SPR access
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//
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input                           spr_cs;
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input                           spr_write;
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input   [31:0]                   spr_addr;
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input   [31:0]                   spr_dat_i;
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output  [31:0]                   spr_dat_o;
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145
//
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// Internal wires and regs
147
//
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wire    [`OR1200_DTLB_TAG]      vpn;
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wire                            v;
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wire    [`OR1200_DTLB_INDXW-1:0] tlb_index;
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wire                            tlb_mr_en;
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wire                            tlb_mr_we;
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wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_in;
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wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_out;
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wire                            tlb_tr_en;
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wire                            tlb_tr_we;
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wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_in;
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wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_out;
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`ifdef OR1200_BIST
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//
161
// RAM BIST
162
//
163
wire                            mbist_mr_so;
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wire                            mbist_tr_so;
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wire                            mbist_mr_si = mbist_si_i;
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wire                            mbist_tr_si = mbist_mr_so;
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assign                          mbist_so_o = mbist_tr_so;
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`endif
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170
//
171
// Implemented bits inside match and translate registers
172
//
173
// dtlbwYmrX: vpn 31-19  v 0
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// dtlbwYtrX: ppn 31-13  swe 9  sre 8  uwe 7  ure 6
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//
176
// dtlb memory width:
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// 19 bits for ppn
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// 13 bits for vpn
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// 1 bit for valid
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// 4 bits for protection
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// 1 bit for cache inhibit
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183
//
184
// Enable for Match registers
185
//
186
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
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188
//
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// Write enable for Match registers
190
//
191
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
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193
//
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// Enable for Translate registers
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//
196
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
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198
//
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// Write enable for Translate registers
200
//
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assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
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203
//
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// Output to SPRS unit
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//
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assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
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                        {vpn, tlb_index & {`OR1200_DTLB_INDXW{v}}, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
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                (spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
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                        {ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
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                        32'h00000000;
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212
//
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// Assign outputs from Match registers
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//
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//assign {vpn, v} = tlb_mr_ram_out;
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assign vpn = tlb_mr_ram_out[13:1];
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assign v = tlb_mr_ram_out[0];
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//
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// Assign to Match registers inputs
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//
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assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
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//
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// Assign outputs from Translate registers
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//
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//assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;
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assign ppn = tlb_tr_ram_out[23:5];
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assign swe = tlb_tr_ram_out[4];
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assign sre = tlb_tr_ram_out[3];
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assign uwe = tlb_tr_ram_out[2];
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assign ure = tlb_tr_ram_out[1];
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assign ci = tlb_tr_ram_out[0];
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//
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// Assign to Translate registers inputs
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//
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assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
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                        spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
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                        spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
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                        spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
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                        spr_dat_i[`OR1200_DTLBTR_URE_BITS],
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                        spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
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245
//
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// Generate hit
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//
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assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
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250
//
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// TLB index is normally vaddr[18:13]. If it is SPR access then index is
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// spr_addr[5:0].
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//
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assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
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`ifdef OR1200_RAM_MODELS_VIRTEX
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//
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//      Non-generic FPGA model instantiations
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//
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wire tlb_mr_en_wire;
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wire [0 : 0] tlb_mr_we_wire;
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wire [5 : 0] tlb_index_wire;
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wire [13 : 0] tlb_mr_ram_in_wire;
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assign tlb_mr_en_wire = tlb_mr_en;
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assign tlb_mr_we_wire = tlb_mr_we;
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assign tlb_index_wire = tlb_index;
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assign tlb_mr_ram_in_wire = tlb_mr_ram_in;
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dtlb_mr_sub dtlb_ram (
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        .clka(clk),
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        .ena(tlb_mr_en_wire),
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        .wea(tlb_mr_we_wire), // Bus [0 : 0] 
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        .addra(tlb_index_wire), // Bus [5 : 0] 
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        .dina(tlb_mr_ram_in_wire), // Bus [13 : 0] 
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        .clkb(clk),
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        .addrb(tlb_index_wire),
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        .doutb(tlb_mr_ram_out)); // Bus [13 : 0]
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282
wire tlb_tr_en_wire;
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wire [0 : 0] tlb_tr_we_wire;
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wire [23 : 0] tlb_tr_ram_in_wire;
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assign tlb_tr_en_wire = tlb_tr_en;
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assign tlb_tr_we_wire = tlb_tr_we;
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assign tlb_tr_ram_in_wire = tlb_tr_ram_in;
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dtlb_tr_sub dtlb_tr_ram (
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        .clka(clk),
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        .ena(tlb_tr_en_wire),
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        .wea(tlb_tr_we_wire), // Bus [0 : 0] 
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        .addra(tlb_index_wire), // Bus [5 : 0] 
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        .dina(tlb_tr_ram_in_wire), // Bus [23 : 0] 
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        .clkb(clk),
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        .addrb(tlb_index_wire),
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        .doutb(tlb_tr_ram_out)); // Bus [23 : 0] 
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300
`else
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302
//
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// Instantiation of DTLB Match Registers
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//
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or1200_spram_64x14 dtlb_mr_ram(
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        .clk(clk),
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        .rst(rst),
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`ifdef OR1200_BIST
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        // RAM BIST
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        .mbist_si_i(mbist_mr_si),
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        .mbist_so_o(mbist_mr_so),
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        .mbist_ctrl_i(mbist_ctrl_i),
313
`endif
314
        .ce(tlb_mr_en),
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        .we(tlb_mr_we),
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        .oe(1'b1),
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        .addr(tlb_index),
318
        .di(tlb_mr_ram_in),
319
        .doq(tlb_mr_ram_out)
320
);
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322
//
323
// Instantiation of DTLB Translate Registers
324
//
325
or1200_spram_64x24 dtlb_tr_ram(
326
        .clk(clk),
327
        .rst(rst),
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`ifdef OR1200_BIST
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        // RAM BIST
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        .mbist_si_i(mbist_tr_si),
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        .mbist_so_o(mbist_tr_so),
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        .mbist_ctrl_i(mbist_ctrl_i),
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`endif
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        .ce(tlb_tr_en),
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        .we(tlb_tr_we),
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        .oe(1'b1),
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        .addr(tlb_index),
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        .di(tlb_tr_ram_in),
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        .doq(tlb_tr_ram_out)
340
);
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`endif
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endmodule

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