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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_ic_tag.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC TAGs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of instruction cache tag rams                  ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2002/10/24 22:19:04  mohor
// Signal scanb_eni renamed to scanb_en
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_ic_tag(
        // Clock and reset
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, tag_v, tag
);
 
parameter dw = `OR1200_ICTAG_W;
parameter aw = `OR1200_ICTAG;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Internal i/f
//
input   [aw-1:0]         addr;
input                           en;
input                           we;
input   [dw-1:0]         datain;
output                          tag_v;
output  [dw-2:0]         tag;
 
`ifdef OR1200_NO_IC
 
//
// Insn cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
`ifdef OR1200_RAM_MODELS_VIRTEX
 
//
//      Non-generic FPGA model instantiations
//
 
wire [19:0] doutb;
assign tag = doutb[19:1];
assign tag_v = doutb[0];
 
ic_tag_sub ic_tag0 (
        .clka(clk),
        .ena(en),
        .wea(we), // Bus [0 : 0] 
        .addra(addr), // Bus [7 : 0] 
        .dina(datain), // Bus [19 : 0]
        .clkb(clk),
        .addrb(addr),
        .doutb(doutb)); // Bus [19 : 0] 
 
`else
 
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_32x24 ic_tag0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_256x21 ic_tag0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_512x20 ic_tag0(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we),
        .oe(1'b1),
        .addr(addr),
        .di(datain),
        .doq({tag, tag_v})
);
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC TAGs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instatiation of instruction cache tag rams ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.6 2004/04/08 11:00:46 simont`
48			`// Add support for 512B instruction cache.`
49			`//`
50			`// Revision 1.5 2004/04/05 08:29:57 lampret`
51			`// Merged branch_qmem into main tree.`
52			`//`
53			`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
54			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
55			`//`
56			`// Revision 1.3 2002/10/24 22:19:04 mohor`
57			`// Signal scanb_eni renamed to scanb_en`
58			`//`
59			`// Revision 1.2 2002/10/17 20:04:40 lampret`
60			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
61			`//`
62			`// Revision 1.1 2002/01/03 08:16:15 lampret`
63			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
64			`//`
65			`// Revision 1.8 2001/10/21 17:57:16 lampret`
66			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
67			`//`
68			`// Revision 1.7 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.2 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`// Revision 1.1 2001/07/20 00:46:03 lampret`
78			`// Development version of RTL. Libraries are missing.`
79			`//`
80			`//`
81
82			`// synopsys translate_off`
83			`include "timescale.v"
84			`// synopsys translate_on`
85			`include "or1200_defines.v"
86
87			`module or1200_ic_tag(`
88			`// Clock and reset`
89			`clk, rst,`
90
91			`ifdef OR1200_BIST
92			`// RAM BIST`
93			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
94			`endif
95
96			`// Internal i/f`
97			`addr, en, we, datain, tag_v, tag`
98			`);`
99
100			parameter dw = `OR1200_ICTAG_W;
101			parameter aw = `OR1200_ICTAG;
102
103			`//`
104			`// I/O`
105			`//`
106
107			`//`
108			`// Clock and reset`
109			`//`
110			`input clk;`
111			`input rst;`
112
113			`ifdef OR1200_BIST
114			`//`
115			`// RAM BIST`
116			`//`
117			`input mbist_si_i;`
118			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
119			`output mbist_so_o;`
120			`endif
121
122			`//`
123			`// Internal i/f`
124			`//`
125			`input [aw-1:0] addr;`
126			`input en;`
127			`input we;`
128			`input [dw-1:0] datain;`
129			`output tag_v;`
130			`output [dw-2:0] tag;`
131
132			`ifdef OR1200_NO_IC
133
134			`//`
135			`// Insn cache not implemented`
136			`//`
137			`assign tag = {dw-1{1'b0}};`
138			`assign tag_v = 1'b0;`
139			`ifdef OR1200_BIST
140			`assign mbist_so_o = mbist_si_i;`
141			`endif
142
143			`else
144
145			`ifdef OR1200_RAM_MODELS_VIRTEX
146
147			`//`
148			`// Non-generic FPGA model instantiations`
149			`//`
150
151			`wire [19:0] doutb;`
152			`assign tag = doutb[19:1];`
153			`assign tag_v = doutb[0];`
154
155			`ic_tag_sub ic_tag0 (`
156			`.clka(clk),`
157			`.ena(en),`
158			`.wea(we), // Bus [0 : 0]`
159			`.addra(addr), // Bus [7 : 0]`
160			`.dina(datain), // Bus [19 : 0]`
161			`.clkb(clk),`
162			`.addrb(addr),`
163			`.doutb(doutb)); // Bus [19 : 0]`
164
165			`else
166
167			`//`
168			`// Instantiation of TAG RAM block`
169			`//`
170			`ifdef OR1200_IC_1W_512B
171			`or1200_spram_32x24 ic_tag0(`
172			`endif
173			`ifdef OR1200_IC_1W_4KB
174			`or1200_spram_256x21 ic_tag0(`
175			`endif
176			`ifdef OR1200_IC_1W_8KB
177			`or1200_spram_512x20 ic_tag0(`
178			`endif
179			`ifdef OR1200_BIST
180			`// RAM BIST`
181			`.mbist_si_i(mbist_si_i),`
182			`.mbist_so_o(mbist_so_o),`
183			`.mbist_ctrl_i(mbist_ctrl_i),`
184			`endif
185			`.clk(clk),`
186			`.rst(rst),`
187			`.ce(en),`
188			`.we(we),`
189			`.oe(1'b1),`
190			`.addr(addr),`
191			`.di(datain),`
192			`.doq({tag, tag_v})`
193			`);`
194			`endif
195
196			`endif
197
198			`endmodule`

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_ic_tag.v] - Blame information for rev 2