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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_pic.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Programmable Interrupt Controller                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PIC according to OR1K architectural specification.          ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.2  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_pic(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        pic_wakeup, intr,
 
        // PIC Interface
        pic_int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          pic_wakeup;     // Wakeup to the PM
output          intr;           // interrupt
                                // exception request
 
//
// PIC Interface
//
input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs
 
`ifdef OR1200_PIC_IMPLEMENTED
 
//
// PIC Mask Register bits (or no register)
//
`ifdef OR1200_PIC_PICMR
reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits
`else
wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register
`endif
 
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits
`else
wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register
`endif
 
//
// Internal wires & regs
//
wire            picmr_sel;      // PICMR select
wire            picsr_sel;      // PICSR select
wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
 
//
// Write to PICMR
//
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
        if (rst)
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
        else if (picmr_sel && spr_write) begin
                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
        end
`else
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
 
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
        if (rst)
                picsr <= {`OR1200_PIC_INTS{1'b0}};
        else if (picsr_sel && spr_write) begin
                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
        end else begin
                picsr <= #1 picsr | um_ints;
        end
`else
assign picsr = pic_int;
`endif
 
//
// Read PIC registers
//
always @(spr_addr or picmr or picsr)
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
`ifdef OR1200_PIC_READREGS
                `OR1200_PIC_OFS_PICMR: begin
                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                                end
`endif
                default: begin
                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
                        end
        endcase
 
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
 
//
// Generate intr
//
assign intr = |um_ints;
 
//
// Assert pic_wakeup when intr is asserted
//
assign pic_wakeup = intr;
 
`else
 
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign intr = pic_int[1] | pic_int[0];
assign pic_wakeup= intr;
 
//
// Read PIC registers
//
`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif
`endif
 
`endif
 
endmodule

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_pic.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Programmable Interrupt Controller ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PIC according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.3 2002/03/29 15:16:56 lampret`
48			`// Some of the warnings fixed.`
49			`//`
50			`// Revision 1.2 2002/01/18 07:56:00 lampret`
51			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
52			`//`
53			`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56			`// Revision 1.8 2001/10/21 17:57:16 lampret`
57			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
58			`//`
59			`// Revision 1.7 2001/10/14 13:12:10 lampret`
60			`// MP3 version.`
61			`//`
62			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
63			`// no message`
64			`//`
65			`// Revision 1.2 2001/08/09 13:39:33 lampret`
66			`// Major clean-up.`
67			`//`
68			`// Revision 1.1 2001/07/20 00:46:21 lampret`
69			`// Development version of RTL. Libraries are missing.`
70			`//`
71			`//`
72
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			`include "or1200_defines.v"
77
78			`module or1200_pic(`
79			`// RISC Internal Interface`
80			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
81			`pic_wakeup, intr,`
82
83			`// PIC Interface`
84			`pic_int`
85			`);`
86
87			`//`
88			`// RISC Internal Interface`
89			`//`
90			`input clk; // Clock`
91			`input rst; // Reset`
92			`input spr_cs; // SPR CS`
93			`input spr_write; // SPR Write`
94			`input [31:0] spr_addr; // SPR Address`
95			`input [31:0] spr_dat_i; // SPR Write Data`
96			`output [31:0] spr_dat_o; // SPR Read Data`
97			`output pic_wakeup; // Wakeup to the PM`
98			`output intr; // interrupt`
99			`// exception request`
100
101			`//`
102			`// PIC Interface`
103			`//`
104			input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs
105
106			`ifdef OR1200_PIC_IMPLEMENTED
107
108			`//`
109			`// PIC Mask Register bits (or no register)`
110			`//`
111			`ifdef OR1200_PIC_PICMR
112			reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
113			`else
114			wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
115			`endif
116
117			`//`
118			`// PIC Status Register bits (or no register)`
119			`//`
120			`ifdef OR1200_PIC_PICSR
121			reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
122			`else
123			wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
124			`endif
125
126			`//`
127			`// Internal wires & regs`
128			`//`
129			`wire picmr_sel; // PICMR select`
130			`wire picsr_sel; // PICSR select`
131			wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
132			`reg [31:0] spr_dat_o; // SPR data out`
133
134			`//`
135			`// PIC registers address decoder`
136			`//`
137			assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
138			assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
139
140			`//`
141			`// Write to PICMR`
142			`//`
143			`ifdef OR1200_PIC_PICMR
144			`always @(posedge clk or posedge rst)`
145			`if (rst)`
146			picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
147			`else if (picmr_sel && spr_write) begin`
148			picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
149			`end`
150			`else
151			assign picmr = (`OR1200_PIC_INTS)'b1;
152			`endif
153
154			`//`
155			`// Write to PICSR, both CPU and external ints`
156			`//`
157			`ifdef OR1200_PIC_PICSR
158			`always @(posedge clk or posedge rst)`
159			`if (rst)`
160			picsr <= {`OR1200_PIC_INTS{1'b0}};
161			`else if (picsr_sel && spr_write) begin`
162			picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] \| um_ints;
163			`end else begin`
164			`picsr <= #1 picsr \| um_ints;`
165			`end`
166			`else
167			`assign picsr = pic_int;`
168			`endif
169
170			`//`
171			`// Read PIC registers`
172			`//`
173			`always @(spr_addr or picmr or picsr)`
174			case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case
175			`ifdef OR1200_PIC_READREGS
176			`OR1200_PIC_OFS_PICMR: begin
177			spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
178			`ifdef OR1200_PIC_UNUSED_ZERO
179			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
180			`endif
181			`end`
182			`endif
183			`default: begin`
184			spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
185			`ifdef OR1200_PIC_UNUSED_ZERO
186			spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
187			`endif
188			`end`
189			`endcase`
190
191			`//`
192			`// Unmasked interrupts`
193			`//`
194			`assign um_ints = pic_int & {picmr, 2'b11};`
195
196			`//`
197			`// Generate intr`
198			`//`
199			`assign intr = \|um_ints;`
200
201			`//`
202			`// Assert pic_wakeup when intr is asserted`
203			`//`
204			`assign pic_wakeup = intr;`
205
206			`else
207
208			`//`
209			`// When PIC is not implemented, drive all outputs as would when PIC is disabled`
210			`//`
211			`assign intr = pic_int[1] \| pic_int[0];`
212			`assign pic_wakeup= intr;`
213
214			`//`
215			`// Read PIC registers`
216			`//`
217			`ifdef OR1200_PIC_READREGS
218			assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
219			`ifdef OR1200_PIC_UNUSED_ZERO
220			assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
221			`endif
222			`endif
223
224			`endif
225
226			`endmodule`