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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_virtex_orig/] [verilog/] [dc_ram_sub.v] - Blame information for rev 2

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/*******************************************************************************
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*     This file is owned and controlled by Xilinx and must be used             *
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*     solely for design, simulation, implementation and creation of            *
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*     design files limited to Xilinx devices or technologies. Use              *
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*     with non-Xilinx devices or technologies is expressly prohibited          *
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*     and immediately terminates your license.                                 *
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*                                                                              *
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*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
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*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
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*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
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*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
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*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
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*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
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*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
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*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
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*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
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*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
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*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
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*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
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*     FOR A PARTICULAR PURPOSE.                                                *
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*                                                                              *
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*     Xilinx products are not intended for use in life support                 *
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*     appliances, devices, or systems. Use in such applications are            *
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*     expressly prohibited.                                                    *
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*                                                                              *
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*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
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*     All rights reserved.                                                     *
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*******************************************************************************/
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// The synthesis directives "translate_off/translate_on" specified below are
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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// You must compile the wrapper file dc_ram_blk.v when simulating
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// the core, dc_ram_blk. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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`timescale 1ns/1ps
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module dc_ram_sub(
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        clka,
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        ena,
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        wea,
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        addra,
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        dina,
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        clkb,
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        addrb,
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        doutb);
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input clka;
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input ena;
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input [3 : 0] wea;
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input [10 : 0] addra;
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input [31 : 0] dina;
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input clkb;
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input [10 : 0] addrb;
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output [31 : 0] doutb;
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wire ena_wire;
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wire [3 : 0] wea_wire;
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wire [10 : 0] addra_wire;
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wire [31 : 0] dina_wire;
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wire [10 : 0] addrb_wire;
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assign ena_wire = ena;
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assign wea_wire = wea;
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assign addra_wire = addra;
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assign dina_wire = dina;
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assign addrb_wire = addrb;
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dc_ram_blk dc_ram_blki(
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        .clka(clka),
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        .ena(ena_wire),
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        .wea(wea_wire),
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        .addra(addra_wire),
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        .dina(dina_wire),
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        .clkb(clkb),
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        .addrb(addrb_wire),
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        .doutb(doutb));
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endmodule
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