OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

Subversion Repositories or1200_soc

[/] [or1200_soc/] [trunk/] [boards/] [de1_board/] [libs/] [wb_conmax.mpf] - Blame information for rev 21

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 qaztronic
[Library]
2
 
3
; Altera specific primitive library mappings
4
 
5
vital2000 = $MODEL_TECH/../vital2000
6
ieee = $MODEL_TECH/../ieee
7
verilog = $MODEL_TECH/../verilog
8
std = $MODEL_TECH/../std
9
std_developerskit = $MODEL_TECH/../std_developerskit
10
synopsys = $MODEL_TECH/../synopsys
11
modelsim_lib = $MODEL_TECH/../modelsim_lib
12
apex20k = $MODEL_TECH/../altera/vhdl/apex20k
13
apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
14
apexii = $MODEL_TECH/../altera/vhdl/apexii
15
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
16
altera = $MODEL_TECH/../altera/vhdl/altera
17
lpm = $MODEL_TECH/../altera/vhdl/220model
18
220model = $MODEL_TECH/../altera/vhdl/220model
19
alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
20
flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
21
flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
22
max = $MODEL_TECH/../altera/vhdl/max
23
maxii = $MODEL_TECH/../altera/vhdl/maxii
24
stratix = $MODEL_TECH/../altera/vhdl/stratix
25
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
26
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
27
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
28
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
29
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
30
hcstratix = $MODEL_TECH/../altera/vhdl/hcstratix
31
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
32
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
33
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
34
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
35
sgate = $MODEL_TECH/../altera/vhdl/sgate
36
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
37
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
38
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
39
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
40
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
41
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
42
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
43
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
44
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
45
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
46
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
47
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
48
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
49
apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
50
apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
51
apexii_ver = $MODEL_TECH/../altera/verilog/apexii
52
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
53
altera_ver = $MODEL_TECH/../altera/verilog/altera
54
lpm_ver = $MODEL_TECH/../altera/verilog/220model
55
220model_ver = $MODEL_TECH/../altera/verilog/220model
56
alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
57
flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
58
flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
59
max_ver = $MODEL_TECH/../altera/verilog/max
60
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
61
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
62
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
63
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
64
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
65
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
66
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
67
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
68
hcstratix_ver = $MODEL_TECH/../altera/verilog/hcstratix
69
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
70
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
71
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
72
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
73
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
74
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
75
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
76
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
77
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
78
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
79
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
80
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
81
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
82
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
83
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
84
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
85
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
86
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
87
work = wb_conmax
88
[vcom]
89
; Turn on VHDL-1993 as the default. Normally is off.
90
; VHDL93 = 1
91
 
92
; Show source line containing error. Default is off.
93
; Show_source = 1
94
 
95
; Turn off unbound-component warnings. Default is on.
96
; Show_Warning1 = 0
97
 
98
; Turn off process-without-a-wait-statement warnings. Default is on.
99
; Show_Warning2 = 0
100
 
101
; Turn off null-range warnings. Default is on.
102
; Show_Warning3 = 0
103
 
104
; Turn off no-space-in-time-literal warnings. Default is on.
105
; Show_Warning4 = 0
106
 
107
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
108
; Show_Warning5 = 0
109
 
110
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
111
; Optimize_1164 = 0
112
 
113
; Turn on resolving of ambiguous function overloading in favor of the
114
; "explicit" function declaration (not the one automatically created by
115
; the compiler for each type declaration). Default is off.
116
; .ini file has Explict enable so that std_logic_signed/unsigned
117
; will match synthesis tools behavior.
118
 Explicit = 1
119
 
120
; Turn off VITAL compliance checking. Default is checking on.
121
; NoVitalCheck = 1
122
 
123
; Ignore VITAL compliance checking errors. Default is to not ignore.
124
; IgnoreVitalErrors = 1
125
 
126
; Turn off VITAL compliance checking warnings. Default is to show warnings.
127
; Show_VitalChecksWarnings = false
128
 
129
; Turn off acceleration of the VITAL packages. Default is to accelerate.
130
; NoVital = 1
131
 
132
; Turn off inclusion of debugging info within design units. Default is to include.
133
; NoDebug = 1
134
 
135
; Turn off "loading..." messages. Default is messages on.
136
; Quiet = 1
137
 
138
; Turn on some limited synthesis rule compliance checking. Checks only:
139
;       -- signals used (read) by a process must be in the sensitivity list
140
; CheckSynthesis = 1
141
 
142
; Require the user to specify a configuration for all bindings,
143
; and do not generate a compile time default binding for the
144
; component. This will result in an elaboration error of
145
; 'component not bound' if the user fails to do so. Avoids the rare
146
; issue of a false dependency upon the unused default binding.
147
 
148
; RequireConfigForAllDefaultBinding = 1
149
 
150
[vlog]
151
 
152
; Turn off inclusion of debugging info within design units. Default is to include.
153
; NoDebug = 1
154
 
155
; Turn off "loading..." messages. Default is messages on.
156
; Quiet = 1
157
 
158
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
159
; Default is off.
160
; Hazard = 1
161
 
162
; Turn on converting regular Verilog identifiers to uppercase. Allows case
163
; insensitivity for module names. Default is no conversion.
164
; UpCase = 1
165
 
166
; Turns on incremental compilation of modules
167
; Incremental = 1
168
 
169
[vsim]
170
; Simulator resolution
171
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
172
Resolution = ps
173
 
174
; User time unit for run commands
175
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
176
; unit specified for Resolution. For example, if Resolution is 100ps,
177
; then UserTimeUnit defaults to ps.
178
UserTimeUnit = default
179
 
180
; Default run length
181
RunLength = 100
182
 
183
; Maximum iterations that can be run without advancing simulation time
184
IterationLimit = 5000
185
 
186
; Directive to license manager:
187
; vhdl          Immediately reserve a VHDL license
188
; vlog          Immediately reserve a Verilog license
189
; plus          Immediately reserve a VHDL and Verilog license
190
; nomgc         Do not look for Mentor Graphics Licenses
191
; nomti         Do not look for Model Technology Licenses
192
; noqueue       Do not wait in the license queue when a license isn't available
193
; License = plus
194
 
195
; Stop the simulator after an assertion message
196
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
197
BreakOnAssertion = 3
198
 
199
; Assertion Message Format
200
; %S - Severity Level
201
; %R - Report Message
202
; %T - Time of assertion
203
; %D - Delta
204
; %I - Instance or Region pathname (if available)
205
; %% - print '%' character
206
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
207
 
208
; Assertion File - alternate file for storing assertion messages
209
; AssertFile = assert.log
210
 
211
; Default radix for all windows and commands...
212
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
213
DefaultRadix = symbolic
214
 
215
; VSIM Startup command
216
; Startup = do startup.do
217
 
218
; File for saving command transcript
219
TranscriptFile = transcript
220
 
221
; File for saving command history
222
;CommandHistory = cmdhist.log
223
 
224
; Specify whether paths in simulator commands should be described
225
; in VHDL or Verilog format. For VHDL, PathSeparator = /
226
; for Verilog, PathSeparator = .
227
PathSeparator = /
228
 
229
; Specify the dataset separator for fully rooted contexts.
230
; The default is ':'. For example, sim:/top
231
; Must not be the same character as PathSeparator.
232
DatasetSeparator = :
233
 
234
; Disable assertion messages
235
; IgnoreNote = 1
236
; IgnoreWarning = 1
237
; IgnoreError = 1
238
; IgnoreFailure = 1
239
 
240
; Default force kind. May be freeze, drive, or deposit
241
; or in other terms, fixed, wired or charged.
242
; DefaultForceKind = freeze
243
 
244
; If zero, open files when elaborated
245
; else open files on first read or write
246
; DelayFileOpen = 0
247
 
248
; Control VHDL files opened for write
249
;   0 = Buffered, 1 = Unbuffered
250
UnbufferedOutput = 0
251
 
252
; Control number of VHDL files open concurrently
253
;   This number should always be less then the
254
;   current ulimit setting for max file descriptors
255
;   0 = unlimited
256
ConcurrentFileLimit = 40
257
 
258
; This controls the number of hierarchical regions displayed as
259
; part of a signal name shown in the waveform window.  The default
260
; value or a value of zero tells VSIM to display the full name.
261
; WaveSignalNameWidth = 0
262
 
263
; Turn off warnings from the std_logic_arith, std_logic_unsigned
264
; and std_logic_signed packages.
265
; StdArithNoWarnings = 1
266
 
267
; Turn off warnings from the IEEE numeric_std and numeric_bit
268
; packages.
269
; NumericStdNoWarnings = 1
270
 
271
; Control the format of a generate statement label. Don't quote it.
272
; GenerateFormat = %s__%d
273
 
274
; Specify whether checkpoint files should be compressed.
275
; The default is to be compressed.
276
; CheckpointCompressMode = 0
277
 
278
; List of dynamically loaded objects for Verilog PLI applications
279
; Veriuser = veriuser.sl
280
[Project]
281
Project_Version = 6
282
Project_DefaultLib = wb_conmax
283
Project_SortMethod = unused
284
Project_Files_Count = 8
285
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
286
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
287
Project_File_1 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_msel.v
288
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
289
Project_File_2 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v
290
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
291
Project_File_3 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
292
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
293
Project_File_4 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v
294
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
295
Project_File_5 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_top.v
296
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
297
Project_File_6 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_rf.v
298
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
299
Project_File_7 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
300
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
301
Project_Sim_Count = 0
302
Project_Folder_Count = 0
303
Echo_Compile_Output = 0
304
Save_Compile_Report = 1
305
Project_Opt_Count = 0
306
ForceSoftPaths = 0
307
ReOpenSourceFiles = 1
308
CloseSourceFiles = 1
309
ProjectStatusDelay = 5000
310
VERILOG_DoubleClick = Edit
311
VERILOG_CustomDoubleClick =
312
SYSTEMVERILOG_DoubleClick = Edit
313
SYSTEMVERILOG_CustomDoubleClick =
314
VHDL_DoubleClick = Edit
315
VHDL_CustomDoubleClick =
316
PSL_DoubleClick = Edit
317
PSL_CustomDoubleClick =
318
TEXT_DoubleClick = Edit
319
TEXT_CustomDoubleClick =
320
SYSTEMC_DoubleClick = Edit
321
SYSTEMC_CustomDoubleClick =
322
TCL_DoubleClick = Edit
323
TCL_CustomDoubleClick =
324
MACRO_DoubleClick = Edit
325
MACRO_CustomDoubleClick =
326
VCD_DoubleClick = Edit
327
VCD_CustomDoubleClick =
328
SDF_DoubleClick = Edit
329
SDF_CustomDoubleClick =
330
XML_DoubleClick = Edit
331
XML_CustomDoubleClick =
332
LOGFILE_DoubleClick = Edit
333
LOGFILE_CustomDoubleClick =
334
UCDB_DoubleClick = Edit
335
UCDB_CustomDoubleClick =
336
EditorState =
337
Project_Major_Version = 6
338
Project_Minor_Version = 4

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.