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[/] [or1200_soc/] [trunk/] [boards/] [de1_board/] [sim/] [models/] [S29al032d_00/] [utilities/] [CreateSDF/] [testbench.vhd] - Blame information for rev 21

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1 21 qaztronic
------------------------------------------------------------------------------
2
--  File name : testbench_640.vhd
3
-------------------------------------------------------------------------------
4
--  Copyright (C) 2003 AMD.
5
--
6
--  MODIFICATION HISTORY :
7
--
8
--  version: | author:     | mod date: | changes made:
9
--    V0.1    M.Marinkovic  11 July 03  Initial
10
--    v0.2    M.Marinkovic  28 Aug  03  Changed protected sector selection
11
--
12
-------------------------------------------------------------------------------
13
--  PART DESCRIPTION:
14
--
15
--  Description:
16
--              Generic test enviroment for verification of AMD flash memory
17
--              VITAL models.my_mem
18
--
19
-------------------------------------------------------------------------------
20
--  Note:   VHDL code formating not done
21
--          For High/Low sector protection selection change:
22
--             TimingModel constant and TimingModel generic value
23
--
24
-------------------------------------------------------------------------------
25
LIBRARY IEEE;
26
    USE IEEE.std_logic_1164.ALL;
27
--USE IEEE.VITAL_timing.ALL;
28
--USE IEEE.VITAL_primitives.ALL;
29
    USE STD.textio.ALL;
30
 
31
LIBRARY VITAL2000;
32
    USE VITAL2000.vital_timing.ALL;
33
    USE VITAL2000.vital_primitives.ALL;
34
 
35
LIBRARY FMF;
36
    USE FMF.gen_utils.ALL;
37
    USE FMF.conversions.ALL;
38
 
39
 
40
LIBRARY work;
41
    USE work.amd_tc_pkg.ALL;
42
 
43
-------------------------------------------------------------------------------
44
-- ENTITY DECLARATION
45
-------------------------------------------------------------------------------
46
ENTITY testbench_640 IS
47
END testbench_640;
48
 
49
 
50
-------------------------------------------------------------------------------
51
-- ARCHITECTURE DECLARATION
52
-------------------------------------------------------------------------------
53
ARCHITECTURE vhdl_behavioral of testbench_640 IS
54
    COMPONENT my_mem
55
    GENERIC (
56
        -- tipd delays: interconnect path delays
57
        tipd_A0             : VitalDelayType01 := VitalZeroDelay01; --
58
        tipd_A1             : VitalDelayType01 := VitalZeroDelay01; --
59
        tipd_A2             : VitalDelayType01 := VitalZeroDelay01; --
60
        tipd_A3             : VitalDelayType01 := VitalZeroDelay01; --
61
        tipd_A4             : VitalDelayType01 := VitalZeroDelay01; --
62
        tipd_A5             : VitalDelayType01 := VitalZeroDelay01; --
63
        tipd_A6             : VitalDelayType01 := VitalZeroDelay01; --
64
        tipd_A7             : VitalDelayType01 := VitalZeroDelay01; --
65
        tipd_A8             : VitalDelayType01 := VitalZeroDelay01; --
66
        tipd_A9             : VitalDelayType01 := VitalZeroDelay01; --address
67
        tipd_A10            : VitalDelayType01 := VitalZeroDelay01; --lines
68
        tipd_A11            : VitalDelayType01 := VitalZeroDelay01; --
69
        tipd_A12            : VitalDelayType01 := VitalZeroDelay01; --
70
        tipd_A13            : VitalDelayType01 := VitalZeroDelay01; --
71
        tipd_A14            : VitalDelayType01 := VitalZeroDelay01; --
72
        tipd_A15            : VitalDelayType01 := VitalZeroDelay01; --
73
        tipd_A16            : VitalDelayType01 := VitalZeroDelay01; --
74
        tipd_A17            : VitalDelayType01 := VitalZeroDelay01; --
75
        tipd_A18            : VitalDelayType01 := VitalZeroDelay01; --
76
        tipd_A19            : VitalDelayType01 := VitalZeroDelay01; --
77
        tipd_A20            : VitalDelayType01 := VitalZeroDelay01; --
78
        tipd_A21            : VitalDelayType01 := VitalZeroDelay01; --
79
 
80
        tipd_DQ0            : VitalDelayType01 := VitalZeroDelay01; --
81
        tipd_DQ1            : VitalDelayType01 := VitalZeroDelay01; --
82
        tipd_DQ2            : VitalDelayType01 := VitalZeroDelay01; --
83
        tipd_DQ3            : VitalDelayType01 := VitalZeroDelay01; --
84
        tipd_DQ4            : VitalDelayType01 := VitalZeroDelay01; --
85
        tipd_DQ5            : VitalDelayType01 := VitalZeroDelay01; --
86
        tipd_DQ6            : VitalDelayType01 := VitalZeroDelay01; -- data
87
        tipd_DQ7            : VitalDelayType01 := VitalZeroDelay01; -- lines
88
        tipd_DQ8            : VitalDelayType01 := VitalZeroDelay01; --
89
        tipd_DQ9            : VitalDelayType01 := VitalZeroDelay01; --
90
        tipd_DQ10           : VitalDelayType01 := VitalZeroDelay01; --
91
        tipd_DQ11           : VitalDelayType01 := VitalZeroDelay01; --
92
        tipd_DQ12           : VitalDelayType01 := VitalZeroDelay01; --
93
        tipd_DQ13           : VitalDelayType01 := VitalZeroDelay01; --
94
        tipd_DQ14           : VitalDelayType01 := VitalZeroDelay01; --
95
 
96
        tipd_DQ15           : VitalDelayType01 := VitalZeroDelay01; -- DQ15/A-1
97
 
98
        tipd_CENeg          : VitalDelayType01 := VitalZeroDelay01;
99
        tipd_OENeg          : VitalDelayType01 := VitalZeroDelay01;
100
        tipd_WENeg          : VitalDelayType01 := VitalZeroDelay01;
101
        tipd_RESETNeg       : VitalDelayType01 := VitalZeroDelay01;
102
        tipd_WPNeg          : VitalDelayType01 := VitalZeroDelay01; --WP#/ACC
103
        tipd_BYTENeg        : VitalDelayType01 := VitalZeroDelay01;
104
 
105
        -- tpd delays
106
        tpd_A0_DQ0          : VitalDelayType01 := UnitDelay01;--tACC
107
        tpd_A0_DQ1          : VitalDelayType01 := UnitDelay01;--tPACC
108
        tpd_CENeg_DQ0       : VitalDelayType01Z := UnitDelay01Z;
109
        --(tCE,tCE,tDF,-,tDF,-)
110
        tpd_OENeg_DQ0       : VitalDelayType01Z := UnitDelay01Z;
111
        --(tOE,tOE,tDF,-,tDF,-)
112
        tpd_RESETNeg_DQ0    : VitalDelayType01Z := UnitDelay01Z;
113
        --(-,-,0,-,0,-)
114
        tpd_CENeg_RY        : VitalDelayType01 := UnitDelay01; --tBUSY
115
        tpd_WENeg_RY        : VitalDelayType01 := UnitDelay01; --tBUSY
116
 
117
        --tsetup values
118
        tsetup_A0_CENeg     : VitalDelayType := UnitDelay;  --tAS edge \
119
        tsetup_A0_OENeg     : VitalDelayType := UnitDelay;  --tASO edge \
120
        tsetup_DQ0_CENeg    : VitalDelayType := UnitDelay;  --tDS edge /
121
 
122
        --thold values
123
        thold_CENeg_RESETNeg: VitalDelayType := UnitDelay;   --tRH  edge /
124
        thold_OENeg_WENeg   : VitalDelayType := UnitDelay;   --tOEH edge /
125
        thold_A0_CENeg      : VitalDelayType := UnitDelay;   --tAH  edge \
126
        thold_A0_OENeg      : VitalDelayType := UnitDelay;   --tAHT edge \
127
        thold_DQ0_CENeg     : VitalDelayType := UnitDelay;   --tDH edge /
128
        thold_WENeg_OENeg   : VitalDelayType := UnitDelay;   --tGHWL edge /
129
 
130
        --tpw values: pulse width
131
        tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP
132
        tpw_OENeg_posedge   : VitalDelayType := UnitDelay; --tOEPH
133
        tpw_WENeg_negedge   : VitalDelayType := UnitDelay; --tWP
134
        tpw_WENeg_posedge   : VitalDelayType := UnitDelay; --tWPH
135
        tpw_CENeg_negedge   : VitalDelayType := UnitDelay; --tCP
136
        tpw_CENeg_posedge   : VitalDelayType := UnitDelay; --tCEPH
137
        tpw_A0_negedge      : VitalDelayType := UnitDelay; --tWC tRC
138
 
139
 
140
        -- tdevice values: values for internal delays
141
            --Effective Write Buffer Program Operation  tWHWH1
142
        tdevice_WBPB        : VitalDelayType    := 11 us;
143
            --Program Operation
144
        tdevice_POB         : VitalDelayType    := 100 us;
145
            --Sector Erase Operation    tWHWH2
146
        tdevice_SEO         : VitalDelayType    := 500 ms;
147
            --Timing Limit Exceeded
148
        tdevice_HANG        : VitalDelayType    := 400 ms; --?
149
            --program/erase suspend timeout
150
        tdevice_START_T1    : VitalDelayType    := 5 us;
151
            --sector erase command sequence timeout
152
        tdevice_CTMOUT      : VitalDelayType    := 50 us;
153
            --device ready after Hardware reset(during embeded algorithm)
154
        tdevice_READY       : VitalDelayType    := 20 us; --tReady
155
 
156
        -- generic control parameters
157
        InstancePath        : STRING    := DefaultInstancePath;
158
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
159
        MsgOn               : BOOLEAN   := DefaultMsgOn;
160
        XOn                 : BOOLEAN   := DefaultXon;
161
        -- memory file to be loaded
162
        mem_file_name       : STRING    ;--:= "am29lv640m.mem";
163
        prot_file_name      : STRING    ;--:= "am29lv640m_prot.mem";
164
        secsi_file_name     : STRING    ;--:= "am29lv_secsi.mem";
165
 
166
        UserPreload         : BOOLEAN   ;--:= TRUE;
167
        LongTimming         : BOOLEAN   ;--:= TRUE;
168
 
169
        -- For FMF SDF technology file usage
170
        TimingModel         : STRING    --:= "AM29LV640MH90R"
171
    );
172
    PORT (
173
        A21             : IN    std_logic := 'U'; --
174
        A20             : IN    std_logic := 'U'; --
175
        A19             : IN    std_logic := 'U'; --
176
        A18             : IN    std_logic := 'U'; --
177
        A17             : IN    std_logic := 'U'; --
178
        A16             : IN    std_logic := 'U'; --
179
        A15             : IN    std_logic := 'U'; --
180
        A14             : IN    std_logic := 'U'; --
181
        A13             : IN    std_logic := 'U'; --address
182
        A12             : IN    std_logic := 'U'; --lines
183
        A11             : IN    std_logic := 'U'; --
184
        A10             : IN    std_logic := 'U'; --
185
        A9              : IN    std_logic := 'U'; --
186
        A8              : IN    std_logic := 'U'; --
187
        A7              : IN    std_logic := 'U'; --
188
        A6              : IN    std_logic := 'U'; --
189
        A5              : IN    std_logic := 'U'; --
190
        A4              : IN    std_logic := 'U'; --
191
        A3              : IN    std_logic := 'U'; --
192
        A2              : IN    std_logic := 'U'; --
193
        A1              : IN    std_logic := 'U'; --
194
        A0              : IN    std_logic := 'U'; --
195
 
196
        DQ15            : INOUT std_logic := 'U'; -- DQ15/A-1
197
        DQ14            : INOUT std_logic := 'U'; --
198
        DQ13            : INOUT std_logic := 'U'; --
199
        DQ12            : INOUT std_logic := 'U'; --
200
        DQ11            : INOUT std_logic := 'U'; --
201
        DQ10            : INOUT std_logic := 'U'; --
202
        DQ9             : INOUT std_logic := 'U'; -- data
203
        DQ8             : INOUT std_logic := 'U'; -- lines
204
        DQ7             : INOUT std_logic := 'U'; --
205
        DQ6             : INOUT std_logic := 'U'; --
206
        DQ5             : INOUT std_logic := 'U'; --
207
        DQ4             : INOUT std_logic := 'U'; --
208
        DQ3             : INOUT std_logic := 'U'; --
209
        DQ2             : INOUT std_logic := 'U'; --
210
        DQ1             : INOUT std_logic := 'U'; --
211
        DQ0             : INOUT std_logic := 'U'; --
212
 
213
        CENeg           : IN    std_logic := 'U';
214
        OENeg           : IN    std_logic := 'U';
215
        WENeg           : IN    std_logic := 'U';
216
        RESETNeg        : IN    std_logic := 'U';
217
        WPNeg           : IN    std_logic := 'U'; --WP#/ACC
218
        BYTENeg         : IN    std_logic := 'U';
219
        RY              : OUT   std_logic := 'U'  --RY/BY#
220
    );
221
    END COMPONENT;
222
 
223
    FOR ALL: my_mem USE ENTITY WORK.my_mem(VHDL_BEHAVIORAL);
224
 
225
    ---------------------------------------------------------------------------
226
    --memory configuration
227
    ---------------------------------------------------------------------------
228
    CONSTANT MaxData        :   NATURAL :=  16#FF#; --255;
229
    CONSTANT SecSize        :   NATURAL :=  16#FFFF#; --65535
230
    CONSTANT SecSiSize      :   NATURAL :=  255;
231
    CONSTANT SecNum         :   NATURAL :=  127;
232
    CONSTANT HiAddrBit      :   NATURAL :=  21;
233
    --Address of the Protected Sector
234
--    CONSTANT ProtSecNum     :   NATURAL :=  SecNum;
235
 
236
    ---------------------------------------------------------------------------
237
    --model configuration
238
    ---------------------------------------------------------------------------
239
    CONSTANT mem_file       :   STRING  := "am29lv640m.mem";
240
    CONSTANT prot_file      :   STRING  := "am29lv640m_prot.mem";
241
    CONSTANT secsi_file     :   STRING  := "am29lv_secsi.mem";
242
 
243
    CONSTANT UserPreload    :   boolean :=  TRUE;
244
    CONSTANT DebugInfo      :   boolean :=  FALSE;
245
    CONSTANT LongTimming    :   boolean :=  TRUE;
246
    CONSTANT TimingModel    :   STRING  :=  "MY_MEM";
247
                                             -- "AM29LV640MH90R";--High sect prot.
248
                                         -- "AM29LV128ML93R";--Low sect. prot.
249
    ---------------------------------------------------------------------------
250
    SIGNAL ProtSecNum       :   NATURAL :=  SecNum ;
251
 
252
    --Flash Memory Array
253
    TYPE SecType  IS ARRAY (0 TO SecSize) OF
254
                     INTEGER RANGE -1 TO MaxData;
255
    TYPE MemArray IS ARRAY (0 TO SecNum) OF
256
                     SecType;
257
 
258
    --Common Flash Interface Query codes
259
    TYPE CFItype  IS ARRAY (16#10# TO 16#50#) OF
260
                    NATURAL RANGE 0 TO 16#FF#;
261
 
262
    --SecSi Sector
263
    TYPE SecSiType  IS ARRAY ( 0 TO SecSiSize) OF
264
                     INTEGER RANGE -1 TO MaxData;
265
 
266
    ---------------------------------------------------------------------------
267
    --  memory declaration
268
    ---------------------------------------------------------------------------
269
    --             -- Mem(SecAddr)(Address)....
270
    SHARED  VARIABLE Mem            : MemArray := (OTHERS => (OTHERS=> MaxData));
271
    SHARED  VARIABLE CFI_array      : CFItype   :=(OTHERS=>0);
272
    SHARED  VARIABLE SecSi          : SecSiType :=(OTHERS=>0);
273
 
274
    --command sequence
275
    SHARED VARIABLE cmd_seq         : cmd_seq_type;
276
 
277
    SIGNAL          status          : status_type := none;
278
    SIGNAL          sts_check       : std_logic_vector(7 downto 0);
279
 
280
 
281
    SIGNAL check_err      :   std_logic := '0';
282
    SIGNAL ErrorInTest    :   std_logic := '0'; --
283
    ----------------------------------------------------------------------------
284
    --Personality module:
285
    --
286
    --  instanciates the DUT module and adapts generic test signals to it
287
    --  TBD: block port
288
    ----------------------------------------------------------------------------
289
    --DUT port
290
    SIGNAL T_DQ       : std_logic_vector(15 downto 0) := (OTHERS=>'U');
291
    SIGNAL T_A        : std_logic_vector(HiAddrBit downto 0) := (OTHERS=>'U');
292
    SIGNAL T_RESETNeg : std_logic                     := 'U';
293
    SIGNAL T_CENeg    : std_logic                     := 'U';
294
    SIGNAL T_WENeg    : std_logic                     := 'U';
295
    SIGNAL T_OENeg    : std_logic                     := 'U';
296
    SIGNAL T_WPNeg    : std_logic                     := 'U';
297
    SIGNAL T_BYTENeg  : std_logic                     := 'U';
298
    SIGNAL T_RY       : std_logic                     := 'U';
299
 
300
    ---------------------------------------------------------------------------
301
    --
302
    ---------------------------------------------------------------------------
303
    --SecSi ProtectionStatus
304
    SHARED VARIABLE FactoryProt     : std_logic := '1';
305
    --Sector Protection Status
306
    SHARED VARIABLE Sec_Prot        : std_logic_vector (SecNum downto 0) :=
307
                                                        (OTHERS => '0');
308
    SHARED VARIABLE Sect            : NATURAL RANGE 0 TO SecNum  := 0;
309
    SHARED VARIABLE Addr            : NATURAL RANGE 0 TO SecSize := 0;
310
    SHARED VARIABLE WriteData       : NATURAL RANGE 0 TO MaxData := 0;
311
 
312
 
313
    --CONSTANT
314
    --timming parameters
315
    CONSTANT RESETNeg_pw            : time    :=  500 ns; --tRP
316
 
317
    SIGNAL pwron                    : std_logic := '0';
318
 
319
    SIGNAL Tseries                  : NATURAL;
320
    SIGNAL Tcase                    : NATURAL;
321
 
322
    SHARED VARIABLE ts_cnt  :   NATURAL RANGE 1 TO 30:=1; -- testseries counter
323
    SHARED VARIABLE tc_cnt  :   NATURAL RANGE 0 TO 10:=0;    -- testcase counter
324
 
325
 
326
    BEGIN
327
        DUT : my_mem
328
        GENERIC MAP (
329
            -- tipd delays: interconnect path delays
330
            tipd_A0             => VitalZeroDelay01, --
331
            tipd_A1             => VitalZeroDelay01, --
332
            tipd_A2             => VitalZeroDelay01, --
333
            tipd_A3             => VitalZeroDelay01, --
334
            tipd_A4             => VitalZeroDelay01, --
335
            tipd_A5             => VitalZeroDelay01, --
336
            tipd_A6             => VitalZeroDelay01, --
337
            tipd_A7             => VitalZeroDelay01, --
338
            tipd_A8             => VitalZeroDelay01, --
339
            tipd_A9             => VitalZeroDelay01, --address
340
            tipd_A10            => VitalZeroDelay01, --lines
341
            tipd_A11            => VitalZeroDelay01, --
342
            tipd_A12            => VitalZeroDelay01, --
343
            tipd_A13            => VitalZeroDelay01, --
344
            tipd_A14            => VitalZeroDelay01, --
345
            tipd_A15            => VitalZeroDelay01, --
346
            tipd_A16            => VitalZeroDelay01, --
347
            tipd_A17            => VitalZeroDelay01, --
348
            tipd_A18            => VitalZeroDelay01, --
349
            tipd_A19            => VitalZeroDelay01, --
350
            tipd_A20            => VitalZeroDelay01, --
351
            tipd_A21            => VitalZeroDelay01, --
352
 
353
            tipd_DQ0            => VitalZeroDelay01, --
354
            tipd_DQ1            => VitalZeroDelay01, --
355
            tipd_DQ2            => VitalZeroDelay01, --
356
            tipd_DQ3            => VitalZeroDelay01, --
357
            tipd_DQ4            => VitalZeroDelay01, --
358
            tipd_DQ5            => VitalZeroDelay01, --
359
            tipd_DQ6            => VitalZeroDelay01, -- data
360
            tipd_DQ7            => VitalZeroDelay01, -- lines
361
            tipd_DQ8            => VitalZeroDelay01, --
362
            tipd_DQ9            => VitalZeroDelay01, --
363
            tipd_DQ10           => VitalZeroDelay01, --
364
            tipd_DQ11           => VitalZeroDelay01, --
365
            tipd_DQ12           => VitalZeroDelay01, --
366
            tipd_DQ13           => VitalZeroDelay01, --
367
            tipd_DQ14           => VitalZeroDelay01, --
368
 
369
            tipd_DQ15           => VitalZeroDelay01, -- DQ15/A-1
370
 
371
            tipd_CENeg          => VitalZeroDelay01,
372
            tipd_OENeg          => VitalZeroDelay01,
373
            tipd_WENeg          => VitalZeroDelay01,
374
            tipd_RESETNeg       => VitalZeroDelay01,
375
            tipd_WPNeg          => VitalZeroDelay01,--WP#/ACC
376
            tipd_BYTENeg        => VitalZeroDelay01,
377
 
378
            -- tpd delays
379
            tpd_A0_DQ0          => UnitDelay01,--tACC
380
            tpd_A0_DQ1          => UnitDelay01,--tPACC
381
            tpd_CENeg_DQ0       => UnitDelay01Z,
382
            --(tCE,tCE,tDF,-,tDF
383
            tpd_OENeg_DQ0       => UnitDelay01Z,
384
            --(tOE,tOE,tDF,-,tDF
385
            tpd_RESETNeg_DQ0    => UnitDelay01Z,
386
            --(-,-,0,-,0,-)
387
            tpd_CENeg_RY        => UnitDelay01, --tBUSY
388
            tpd_WENeg_RY        => UnitDelay01, --tBUSY
389
 
390
            --tsetup values
391
            tsetup_A0_CENeg     => UnitDelay,  --tAS edge \
392
            tsetup_A0_OENeg     => UnitDelay,  --tASO edge \
393
            tsetup_DQ0_CENeg    => UnitDelay,  --tDS edge /
394
 
395
            --thold values
396
            thold_CENeg_RESETNeg=> UnitDelay,   --tRH  edge /
397
            thold_OENeg_WENeg   => UnitDelay,   --tOEH edge /
398
            thold_A0_CENeg      => UnitDelay,   --tAH  edge \
399
            thold_A0_OENeg      => UnitDelay,   --tAHT edge \
400
            thold_DQ0_CENeg     => UnitDelay,   --tDH edge /
401
            thold_WENeg_OENeg   => UnitDelay,   --tGHVL edge /
402
 
403
            --tpw values: pulse width
404
            tpw_RESETNeg_negedge=> UnitDelay, --tRP
405
            tpw_OENeg_posedge   => UnitDelay, --tOEPH
406
            tpw_WENeg_negedge   => UnitDelay, --tWP
407
            tpw_WENeg_posedge   => UnitDelay, --tWPH
408
            tpw_CENeg_negedge   => UnitDelay, --tCP
409
            tpw_CENeg_posedge   => UnitDelay, --tCEPH
410
            tpw_A0_negedge      => UnitDelay, --tWC tRC
411
            -- tdevice values: values for internal delays
412
                --Effective Write Buffer Program Operation  tWHWH1
413
            tdevice_WBPB        => 11 us,
414
                --Program Operation
415
            tdevice_POB         => 100 us,
416
                --Sector Erase Operation    tWHWH2
417
            tdevice_SEO         => 500 ms,
418
                --Timing Limit Exceeded
419
            tdevice_HANG        => 400 ms, --?
420
                --program/erase suspend timeout
421
            tdevice_START_T1    => 5 us,
422
                --sector erase command sequence timeout
423
            tdevice_CTMOUT      => 50 us,
424
                --device ready after Hardware reset(during embeded algorithm)
425
            tdevice_READY       => 20 us, --tReady
426
 
427
            -- generic control parameters
428
            InstancePath        => DefaultInstancePath,
429
            TimingChecksOn      => TRUE,--DefaultTimingChecks,
430
            MsgOn               => DefaultMsgOn,
431
            XOn                 => DefaultXon,
432
            -- memory file to be loaded
433
            mem_file_name       => mem_file,
434
            prot_file_name      => prot_file ,
435
            secsi_file_name     => secsi_file,
436
 
437
            UserPreload         => UserPreload,
438
            LongTimming         => LongTimming,
439
            -- For FMF SDF technology file usage
440
            TimingModel         => "AM29LV640MH90R" -- TimingModel
441
        )
442
        PORT MAP(
443
            A21        => T_A(21), --
444
            A20        => T_A(20), --
445
            A19        => T_A(19), --
446
            A18        => T_A(18), --
447
            A17        => T_A(17), --
448
            A16        => T_A(16), --
449
            A15        => T_A(15), --
450
            A14        => T_A(14), --
451
            A13        => T_A(13), --address
452
            A12        => T_A(12), --lines
453
            A11        => T_A(11), --
454
            A10        => T_A(10), --
455
            A9         => T_A(9), --
456
            A8         => T_A(8), --
457
            A7         => T_A(7), --
458
            A6         => T_A(6), --
459
            A5         => T_A(5),--
460
            A4         => T_A(4),--
461
            A3         => T_A(3), --
462
            A2         => T_A(2), --
463
            A1         => T_A(1), --
464
            A0         => T_A(0), --
465
 
466
            DQ15       => T_DQ(15), -- DQ15/A-1
467
            DQ14       => T_DQ(14), --
468
            DQ13       => T_DQ(13), --
469
            DQ12       => T_DQ(12), --
470
            DQ11       => T_DQ(11), --
471
            DQ10       => T_DQ(10), --
472
            DQ9        => T_DQ(9), -- data
473
            DQ8        => T_DQ(8), -- lines
474
            DQ7        => T_DQ(7), --
475
            DQ6        => T_DQ(6), --
476
            DQ5        => T_DQ(5), --
477
            DQ4        => T_DQ(4), --
478
            DQ3        => T_DQ(3), --
479
            DQ2        => T_DQ(2), --
480
            DQ1        => T_DQ(1), --
481
            DQ0        => T_DQ(0), --
482
 
483
            CENeg      => T_CENeg,
484
            OENeg      => T_OENeg,
485
            WENeg      => T_WENeg,
486
            RESETNeg   => T_RESETNeg,
487
            WPNeg      => T_WPNeg, --WP#/ACC
488
            BYTENeg    => T_BYTENeg,
489
            RY         => T_RY  --RY/BY#
490
        );
491
 
492
    ---------------------------------------------------------------------------
493
    --protected sector
494
    ---------------------------------------------------------------------------
495
    ProtSecNum <= SecNum WHEN  TimingModel(11) = 'H' ELSE
496
 
497
 
498
    pwron <= '0', '1' after 1 ns;
499
 
500
--At the end of the simulation, if ErrorInTest='0' there were no errors
501
err_ctrl : PROCESS ( check_err  )
502
    BEGIN
503
        IF check_err = '1' THEN
504
            ErrorInTest <= '1';
505
        END IF;
506
    END PROCESS err_ctrl;
507
 
508
tb  :PROCESS
509
 
510
    --------------------------------------------------------------------------
511
    --= PROCEDURE to select TC
512
    -- can be modified to read TC list from file, or to generate random list
513
    --------------------------------------------------------------------------
514
    PROCEDURE   Pick_TC
515
        (Model   :  IN  STRING  := "AM29LV640MH90R"  )
516
    IS
517
    BEGIN
518
        IF TC_cnt < tc(TS_cnt) THEN
519
            TC_cnt := TC_cnt+1;
520
        ELSE
521
            TC_cnt:=1;
522
            IF TS_cnt<30 THEN
523
                TS_cnt := TS_cnt+1;
524
            ELSE
525
                -- end test
526
                IF ErrorInTest='0' THEN
527
                    REPORT "Test Ended without errors"
528
                    SEVERITY note;
529
                ELSE
530
                    REPORT "There were errors in test"
531
                    SEVERITY note;
532
                END IF;
533
                WAIT;
534
            END IF;
535
        END IF;
536
    END PROCEDURE Pick_TC;
537
 
538
   ---------------------------------------------------------------------------
539
    --bus commands, device specific implementation
540
    ---------------------------------------------------------------------------
541
    TYPE bus_type IS (bus_idle,
542
                      bus_standby,  --CE# deasseretd, others are don't care
543
                      bus_enable,   --CE# asserted, others deasserted
544
                      bus_output_disable,
545
                      bus_reset,
546
                      bus_write,
547
                      bus_read);
548
 
549
    --bus drive for specific command sequence cycle
550
    PROCEDURE bus_cycle(
551
        bus_cmd :IN   bus_type := bus_idle;
552
        byte    :IN   boolean                      ;
553
        data    :IN   INTEGER RANGE -2 TO MaxData  := -2; -- -1 for all Z
554
        dataHi  :IN   INTEGER RANGE -2 TO MaxData  := -2; -- -2 for ignore
555
        sector  :IN   INTEGER RANGE -1 TO SecNum   := -1; -- -1 for ignore addr
556
        address :IN   NATURAL RANGE  0 TO SecSize  := 0;
557
        disable :IN   boolean                      := false;
558
        violate :IN   boolean                      := false;
559
        tm      :IN   TIME                         := 10 ns)
560
    IS
561
 
562
        VARIABLE tmp : std_logic_vector(15 downto 0);
563
    BEGIN
564
 
565
        IF data=-1 THEN -- HiZ
566
            T_DQ(7 downto 0) <= (OTHERS => 'Z');
567
        END IF;
568
 
569
        IF (NOT byte)THEN --word access
570
            IF dataHi=-1 THEN -- HiZ
571
                T_DQ(15 downto 8) <= (OTHERS => 'Z');
572
            END IF;
573
            T_BYTENeg <= '1';
574
        ELSE                 --byte access
575
            T_BYTENeg <= '0';
576
            T_DQ(14 downto 8) <= (OTHERS => 'Z');
577
        END IF;
578
 
579
        IF sector > -1 THEN
580
            T_A(HiAddrBit downto 15) <= to_slv(sector, HiAddrbit-14);
581
            tmp := to_slv(address, 16);
582
            IF byte THEN
583
                T_A(14 downto 0) <= tmp(15 downto 1);
584
                T_DQ(15) <= tmp(0);
585
            ELSE
586
                T_A(14 downto 0) <= tmp(14 downto 0);
587
            END IF;
588
 
589
        END IF;
590
 
591
        wait for 1 ns;
592
 
593
        CASE bus_cmd IS
594
            WHEN bus_output_disable    =>
595
                T_OENeg    <= '1';
596
                WAIT FOR 20 ns;
597
 
598
            WHEN bus_idle       =>
599
                T_RESETNeg <= '1';
600
                T_WENeg    <= '1';
601
                T_CENeg    <= '1';
602
                T_OENeg    <= '1';
603
                IF disable THEN
604
                    T_WPNeg <= '0';
605
                ELSE
606
                    T_WPNeg <= '1';
607
                END IF;
608
                WAIT FOR 30 ns;
609
 
610
            WHEN bus_standby             =>
611
                T_CENeg    <= '1';
612
                WAIT FOR 30 ns;
613
 
614
            WHEN bus_reset               =>
615
                T_RESETNeg <= '0', '1' AFTER tm ;
616
                -- WAIT FOR 500 ns should follow this bus cmd for reset to
617
                --complete
618
                WAIT FOR 30 ns;
619
 
620
            WHEN bus_enable              =>
621
                T_WENeg    <= '1' AFTER 50 ns;   ---
622
                T_CENeg    <= '0' AFTER 50 ns;   ---
623
                T_OENeg    <= '1' AFTER 30 ns;   ---
624
 
625
                WAIT FOR tm ;
626
 
627
            WHEN bus_write  =>
628
                T_OENeg <= '1' ;-- AFTER 5 ns;
629
                T_CENeg <= '0' AFTER 10 ns ;
630
                T_WENeg <= '0' AFTER 20 ns;
631
 
632
                IF data>-1 THEN
633
                    T_DQ(7 downto 0) <= to_slv(data,8);
634
                END IF;
635
                IF NOT byte THEN
636
                    IF dataHi>-1 THEN
637
                        T_DQ(15 downto 8) <= to_slv(dataHi,8);
638
                    END IF;
639
                END IF;
640
 
641
                IF violate THEN
642
                    T_WENeg <= '1';
643
                    WAIT FOR 50 ns;
644
                    T_WENeg <= '0', '1' AFTER tm;
645
                    WAIT FOR 50 ns;
646
                ELSE
647
                    WAIT FOR 100 ns;
648
                END IF;
649
 
650
            WHEN bus_read  =>
651
 
652
                T_CENeg     <= '0' ;
653
                T_WENeg     <= '1'AFTER 10 ns;
654
                IF NOT disable  THEN
655
                    T_OENeg <= '0' AFTER 15 ns;
656
                ELSE
657
                    T_OENeg <= '1';
658
                END IF;
659
 
660
                IF NOT byte THEN
661
                    T_DQ(15 downto 8) <= (OTHERS => 'Z');
662
                END IF;
663
                T_DQ(7 downto 0)      <= (OTHERS => 'Z');
664
 
665
                WAIT FOR 100 ns;
666
 
667
                -- T_OENeg <= '1' ; -----------
668
 
669
        END CASE;
670
 
671
 
672
    END PROCEDURE;
673
 
674
 
675
   ---------------------------------------------------------------------------
676
    --procedure to decode commands into specific bus command sequence
677
    ---------------------------------------------------------------------------
678
    PROCEDURE cmd_dc
679
        (   command  :   IN  cmd_rec   )
680
    IS
681
        VARIABLE    D_hi    : NATURAL ;--RANGE 0 to MaxData;
682
        VARIABLE    D_lo    : NATURAL RANGE 0 to MaxData;
683
        VARIABLE    Addr    : NATURAL RANGE 0 to SecSize  :=0;
684
        VARIABLE    Addrfix : NATURAL RANGE 0 to SecSize/2:=0;
685
        VARIABLE    Sect    : INTEGER RANGE -1 to SecNum  :=0;
686
        VARIABLE    slv_1, slv_2 : std_logic_vector(7 downto 0);
687
        VARIABLE    byte    : boolean;
688
        VARIABLE    i       : NATURAL;
689
    BEGIN
690
        CASE command.cmd IS
691
            WHEN    idle        =>
692
                bus_cycle(bus_cmd => bus_idle,
693
                          byte    => command.byte,
694
                          disable => command.aux=disable);
695
 
696
            WHEN    h_reset     =>
697
                bus_cycle(bus_cmd => bus_reset,
698
                          byte    => command.byte,
699
                          tm      => command.wtime);
700
 
701
            WHEN    rd        =>
702
                bus_cycle(bus_cmd => bus_enable,
703
                          byte    => command.byte,
704
                          data    => -1,
705
                          sector  => command.sect,
706
                          address => command.addr,
707
                          tm      => 90 ns);
708
 
709
                bus_cycle(bus_cmd => bus_read,
710
                          byte    => command.byte,
711
                          data    => -1,
712
                          dataHi  => -1,
713
                          sector  => command.sect,
714
                          address => command.addr,
715
                          disable => command.aux=disable);
716
 
717
                bus_cycle(bus_cmd => bus_output_disable,
718
                          byte    => command.byte);
719
 
720
            WHEN    rd_page     =>
721
                bus_cycle(bus_cmd => bus_enable,
722
                          byte    => command.byte,
723
                          data    => -1,
724
                          sector  => 0,
725
                          address => 0,
726
                          tm      => 90 ns);
727
 
728
                Addr :=  command.addr;
729
                Sect :=  command.sect;
730
                byte :=  command.byte;
731
                ---- 08July----
732
                WAIT FOR 10 ns;
733
                --------------
734
                i := 0;
735
                WHILE i < command.d_hi LOOP
736
 
737
                    IF command.wtime > 0 ns THEN
738
 
739
                        bus_cycle(bus_cmd => bus_output_disable,  ----
740
                                  byte    => byte);       ----
741
 
742
                        --byte toggle mode
743
                        bus_cycle(bus_cmd => bus_enable,
744
                                  byte    => byte,
745
                                  data    => -1,
746
                                  sector  => -1,
747
                                  tm      => 10 ns);
748
                        byte := false;
749
                        bus_cycle(bus_cmd => bus_enable,
750
                                  byte    => byte,
751
                                  data    => -1,
752
                                  sector  => -1,
753
                                  tm      => 10 ns);
754
                        Addrfix := Addr /2;
755
                        IF Addr < SecSize THEN
756
                            Addr := Addr+1;
757
                        ELSE
758
                            Addr := 0;
759
                            IF Sect < SecNum THEN
760
                                Sect := Sect+1;
761
                            ELSE
762
                                REPORT "No more locations to read !!!"
763
                                SEVERITY warning;
764
                            END IF;
765
                        END IF;
766
                        --word read;
767
                        bus_cycle(bus_cmd => bus_read,
768
                                  byte    => byte,
769
                                  data    => -1,
770
                                  dataHi  => -1,
771
                                  sector  => Sect,
772
                                  address => Addrfix);
773
 
774
                        bus_cycle(bus_cmd => bus_output_disable,  ----
775
                                  byte    => byte);       ----
776
 
777
                        bus_cycle(bus_cmd => bus_enable,
778
                                  byte    => byte,
779
                                  data    => -1,
780
                                  sector  => -1,
781
                                  tm      => 10 ns);
782
                        byte := true;
783
                        bus_cycle(bus_cmd => bus_enable,
784
                                  byte    => byte,
785
                                  data    => -1,
786
                                  sector  => -1,
787
                                  tm      => 30 ns);
788
 
789
                        --first byte read
790
                        bus_cycle(bus_cmd => bus_read,
791
                                  byte    => byte,
792
                                  data    => -1,
793
                                  dataHi  => -1,
794
                                  sector  => Sect,
795
                                  address => Addr);
796
 
797
                        bus_cycle(bus_cmd => bus_output_disable,  ----
798
                                  byte    => byte);       ----
799
 
800
                        IF Addr < SecSize THEN
801
                            Addr := Addr+1;
802
                        ELSE
803
                            Addr := 0;
804
                            IF Sect < SecNum THEN
805
                                Sect := Sect+1;
806
                            ELSE
807
                                REPORT "No more locations to read !!!"
808
                                SEVERITY warning;
809
                            END IF;
810
                        END IF;
811
                        i := i +3;
812
                        wait for 10 ns; -------
813
                    ELSE
814
                        byte :=  command.byte;
815
                    END IF;
816
                    --second byte read in byte toggle mode
817
                    bus_cycle(bus_cmd => bus_read,
818
                              byte    => byte,
819
                              data    => -1,
820
                              dataHi  => -1,
821
                              sector  => Sect,
822
                              address => Addr);
823
 
824
 
825
                    IF Addr < SecSize THEN
826
                        Addr := Addr+1;
827
                    ELSE
828
                        Addr := 0;
829
                        IF Sect < SecNum THEN
830
                            Sect := Sect+1;
831
                        ELSE
832
                            REPORT "No more locations to read !!!"
833
                            SEVERITY warning;
834
                        END IF;
835
                    END IF;
836
                    i := i +1;
837
                    WAIT FOR 10 ns;
838
                END LOOP;
839
                bus_cycle(bus_cmd => bus_output_disable,
840
                          byte    => command.byte);
841
 
842
 
843
 
844
            WHEN    w_cycle     =>
845
 
846
                D_lo    :=  16#AA# ; --first command data
847
                Addr    :=  16#AAA#; --first command byte address
848
                D_hi    :=  16#55#;  --second command data
849
                Addrfix :=  16#555#; --second command byte address
850
                IF NOT command.byte THEN
851
                    --if word addressing
852
                    Addr    := 16#555#; --first command byte address
853
                    Addrfix := 16#2AA#; --second command byte address
854
                END IF;
855
 
856
                bus_cycle(bus_cmd => bus_write,
857
                         byte    => command.byte,
858
                         data    => D_lo,
859
                         dataHi  => 0,
860
                         sector  => 0,
861
                         address => Addr,
862
                         violate => command.aux=violate,
863
                         tm      => command.wtime);
864
 
865
                bus_cycle(bus_cmd => bus_standby,
866
                         byte    => command.byte);
867
 
868
                bus_cycle(bus_cmd => bus_write,
869
                         byte    => command.byte,
870
                         data    => D_hi,
871
                         dataHi  => 0,
872
                         sector  => 0,
873
                         address => Addrfix);
874
 
875
                bus_cycle(bus_cmd => bus_standby,
876
                         byte    => command.byte);
877
 
878
 
879
            WHEN    w_reset | w_prog | w_erase | w_unlock |
880
                    w_autoselect | w_enter_sec   =>
881
                Addr    :=  16#AAA#;
882
                IF NOT command.byte THEN
883
                    --if word addressing
884
                    Addr    := 16#555#; --first command byte address
885
                END IF;
886
 
887
                CASE  command.cmd IS
888
                    WHEN w_reset =>
889
                        d_lo := 16#F0#;
890
                    WHEN w_prog =>
891
                        d_lo := 16#A0#;
892
                    WHEN w_erase =>
893
                        d_lo := 16#80#;
894
                    WHEN w_unlock =>
895
                        d_lo := 16#20#;
896
                    WHEN w_autoselect  =>
897
                        d_lo := 16#90#;
898
                    WHEN w_enter_sec =>
899
                        d_lo := 16#88#;
900
                    WHEN OTHERS  =>
901
                        d_lo :=  0;
902
                END CASE;
903
 
904
                bus_cycle(bus_cmd => bus_write,
905
                         byte    => command.byte,
906
                         data    => d_lo,
907
                         dataHi  => 0,
908
                         sector  => 0,
909
                         address => Addr);
910
                bus_cycle(bus_cmd => bus_standby,
911
                         byte    => command.byte);
912
 
913
 
914
 
915
            WHEN w_unlock_reset =>
916
                Addr    :=  16#AAA#; --first command byte address
917
                IF NOT command.byte THEN
918
                    --if word addressing
919
                    Addr    := 16#555#; --first command byte address
920
                END IF;
921
                bus_cycle(bus_cmd => bus_write,
922
                         byte    => command.byte,
923
                         data    => 16#90#,
924
                         dataHi  => 0,
925
                         sector  => 0,
926
                         address => Addr);
927
 
928
                bus_cycle(bus_cmd => bus_standby,
929
                         byte    => command.byte);
930
 
931
                bus_cycle(bus_cmd => bus_write,
932
                         byte    => command.byte,
933
                         data    => 16#F0#,
934
                         dataHi  => 0,
935
                         sector  => 0,
936
                         address => Addr);
937
 
938
                bus_cycle(bus_cmd => bus_standby,
939
                         byte    => command.byte);
940
 
941
            WHEN w_chip_ers =>
942
                Addr    :=  16#AAA#; --first command byte address
943
                IF NOT command.byte THEN
944
                    --if word addressing
945
                    Addr    := 16#555#; --first command byte address
946
                END IF;
947
                bus_cycle(bus_cmd => bus_write,
948
                         byte    => command.byte,
949
                         data    => 16#10#,
950
                         dataHi  => 0,
951
                         sector  => 0,
952
                         Address => Addr);
953
                FOR i IN 0 TO SecNum LOOP
954
                    IF Sec_Prot(i)/='1' THEN
955
                        mem(i) := (OTHERS=>16#FF#);
956
                    END IF;
957
                END LOOP;
958
                bus_cycle(bus_cmd => bus_standby,
959
                         byte    => command.byte);
960
 
961
 
962
            WHEN w_cfi =>
963
                Addr    :=  16#AA#; --first command byte address
964
                IF NOT command.byte THEN
965
                    --if word addressing
966
                    Addr    := 16#55#; --first command byte address
967
                END IF;
968
                bus_cycle(bus_cmd => bus_write,
969
                         byte    => command.byte,
970
                         data    => 16#98#,
971
                         dataHi  => 0,
972
                         sector  => 0,
973
                         Address => Addr);
974
 
975
                bus_cycle(bus_cmd => bus_standby,
976
                         byte    => command.byte);
977
 
978
 
979
 
980
            WHEN w_suspend =>
981
                bus_cycle(bus_cmd => bus_write,
982
                         byte    => command.byte,
983
                         data    => 16#B0#,
984
                         dataHi  => 0,
985
                         sector  => -1);
986
 
987
                bus_cycle(bus_cmd => bus_standby,
988
                         byte    => command.byte);
989
 
990
            WHEN w_resume =>
991
                bus_cycle(bus_cmd => bus_write,
992
                         byte    => command.byte,
993
                         data    => 16#30#,
994
                         dataHi  => 0,
995
                         sector  => -1);
996
 
997
                bus_cycle(bus_cmd => bus_standby,
998
                         byte    => command.byte);
999
 
1000
 
1001
            WHEN w_data =>
1002
 
1003
                D_hi :=  command.d_hi MOD 16#100#;
1004
                D_lo :=  command.d_lo ;
1005
                Addr :=  command.addr;
1006
                Sect :=  command.sect;
1007
 
1008
                bus_cycle(bus_cmd => bus_write,
1009
                         byte     => command.byte,
1010
                         data     => D_lo,
1011
                         dataHi   => D_hi,
1012
                         sector   => Sect,
1013
                         address  => Addr);
1014
 
1015
                bus_cycle(bus_cmd => bus_standby,
1016
                         byte    => command.byte);
1017
 
1018
 
1019
                IF NOT command.byte THEN
1020
                    Addr := Addr*2;
1021
                END IF;
1022
 
1023
                --write value(s) in default mem
1024
                IF status = erase_active AND Sec_Prot(Sect)/='1'THEN
1025
                    --sector should be erased
1026
                    mem(Sect) := (OTHERS=>16#FF#);
1027
 
1028
                ELSIF status = erase_na AND Sec_Prot(Sect)/='1'THEN
1029
                    --sector erase terminated = data integrity violated
1030
                    mem(Sect) := (OTHERS=>-1);
1031
 
1032
                ELSIF status = readX AND Sec_Prot(Sect)/='1' THEN
1033
                    mem(Sect)(Addr) := -1;
1034
                    IF NOT command.byte THEN
1035
                        mem(Sect)(Addr+1) := -1;
1036
                    END IF;
1037
 
1038
                -- Write to Secure Silicon Sector Region
1039
                ELSIF status = rd_SecSi AND FactoryProt/='1' THEN
1040
                    slv_1 := to_slv(d_lo,8);
1041
                    IF SecSi(Addr)>-1 THEN
1042
                        slv_2 := to_slv(SecSi(Addr),8);
1043
                    ELSE
1044
                        slv_2 := (OTHERS=>'X');
1045
                    END IF;
1046
 
1047
                    FOR i IN 0 to 7 LOOP
1048
                        IF slv_2(i)='0' THEN
1049
                            slv_1(i):='0';
1050
                        END IF;
1051
                    END LOOP;
1052
                    SecSi(Addr) := to_nat(slv_1);
1053
                    IF NOT command.byte THEN
1054
                        slv_1 := to_slv(d_hi,8);
1055
                        IF SecSi(Addr+1)>-1 THEN
1056
                            slv_2 := to_slv(SecSi(Addr+1),8);
1057
                        ELSE
1058
                            slv_2 := (OTHERS=>'X');
1059
                        END IF;
1060
                        FOR i IN 0 to 7 LOOP
1061
                            IF slv_2(i)='0' THEN
1062
                                slv_1(i):='0';
1063
                            END IF;
1064
                        END LOOP;
1065
                        SecSi(Addr+1) := to_nat(slv_1);
1066
                    END IF;
1067
 
1068
                ELSIF status=buff_wr_busy THEN
1069
                    --Write to Buffer command cycle
1070
                    null;
1071
 
1072
                ELSIF status=erase_na THEN
1073
                    --sector erase command sequence violation
1074
                    null;
1075
 
1076
                -- Write to Flash Memory Array
1077
                ELSIF status /= err AND Sec_Prot(Sect)/='1'THEN
1078
                    slv_1 := to_slv(d_lo,8);
1079
                    IF mem(Sect)(Addr)>-1 THEN
1080
                        slv_2 := to_slv(mem(Sect)(Addr),8);
1081
                    ELSE
1082
                        slv_2 := (OTHERS=>'X');
1083
                    END IF;
1084
 
1085
                    FOR i IN 0 to 7 LOOP
1086
                        IF slv_2(i)='0' THEN
1087
                            slv_1(i):='0';
1088
                        END IF;
1089
                    END LOOP;
1090
                    mem(Sect)(Addr) := to_nat(slv_1);
1091
                    IF NOT command.byte THEN
1092
                        slv_1 := to_slv(d_hi,8);
1093
                        IF mem(Sect)(Addr+1)>-1 THEN
1094
                            slv_2 := to_slv(mem(Sect)(Addr+1),8);
1095
                        ELSE
1096
                            slv_2 := (OTHERS=>'X');
1097
                        END IF;
1098
                        FOR i IN 0 to 7 LOOP
1099
                            IF slv_2(i)='0' THEN
1100
                                slv_1(i):='0';
1101
                            END IF;
1102
                        END LOOP;
1103
                        mem(Sect)(Addr+1) := to_nat(slv_1);
1104
                    END IF;
1105
                END IF;
1106
 
1107
 
1108
            WHEN    wt          =>
1109
                WAIT FOR command.wtime;
1110
 
1111
            WHEN    wt_rdy      =>
1112
                IF T_RY/='1' THEN
1113
                    WAIT UNTIL rising_edge(T_RY) FOR command.wtime;
1114
                END IF;
1115
 
1116
            WHEN    wt_bsy      =>
1117
                IF T_RY='1' THEN
1118
                    WAIT UNTIL falling_edge(T_RY) FOR command.wtime;
1119
                END IF;
1120
 
1121
            WHEN    OTHERS  =>  null;
1122
        END CASE;
1123
    END PROCEDURE;
1124
 
1125
 
1126
    VARIABLE cmd_cnt    :   NATURAL;
1127
    VARIABLE command    :   cmd_rec;  --
1128
 
1129
BEGIN
1130
    Pick_TC (Model   =>  "AM29LV640MH90R"   );
1131
 
1132
    Tseries <=  ts_cnt  ;
1133
    Tcase   <=  tc_cnt  ;
1134
 
1135
    Generate_TC
1136
        (Model       => "AM29LV640MH90R"  ,
1137
         Series      => ts_cnt,
1138
         TestCase    => tc_cnt,
1139
         command_seq => cmd_seq);
1140
 
1141
 
1142
    cmd_cnt := 1;
1143
    WHILE cmd_seq(cmd_cnt).cmd/=done LOOP
1144
        command:= cmd_seq(cmd_cnt);
1145
        IF command.sect = -1 THEN
1146
            command.sect := ProtSecNum;
1147
        END IF;
1148
        status   <=  command.status;
1149
        sts_check<=  to_slv(command.d_lo,8); --used only for toggle/status check
1150
        cmd_dc(command);
1151
        cmd_cnt :=cmd_cnt +1;
1152
 
1153
    END LOOP;
1154
 
1155
END PROCESS tb;
1156
 
1157
--process to monitor WP#
1158
PROCESS(T_WPNeg)
1159
VARIABLE reg : std_logic;
1160
BEGIN
1161
    IF falling_edge(T_WPNeg) THEN
1162
        reg := Sec_Prot(ProtSecNum);
1163
        Sec_Prot(ProtSecNum) := '1';
1164
    ELSIF rising_edge(T_WPNeg) THEN
1165
        Sec_Prot(ProtSecNum) := reg;
1166
    END IF;
1167
END PROCESS;
1168
 
1169
--------------------------------------------------------------------------------
1170
-- Checker process,
1171
-- Bus transition extractor: when bus cycle is read samples addr and data
1172
-- Transition checker      : verifies correct read data using default memory
1173
--------------------------------------------------------------------------------
1174
checker: PROCESS
1175
    VARIABLE RAddr      :   NATURAL;
1176
    VARIABLE RSect      :   NATURAL;
1177
    VARIABLE longread   :   boolean;
1178
    VARIABLE shortread  :   boolean;
1179
    VARIABLE toggle     :   boolean:=false;
1180
    VARIABLE toggle_sts :   std_logic_vector(7 downto 0);
1181
 
1182
BEGIN
1183
--    Transition extractor
1184
    IF (T_CENeg='0'AND T_OENeg='0'AND T_WENeg='1') THEN
1185
        IF T_BYTENeg='1' THEN
1186
            RAddr := to_nat(T_A(14 downto 0)&'0');
1187
        ELSE
1188
            RAddr := to_nat(T_A(14 downto 0)&T_DQ(15));
1189
        END IF;
1190
        RSect := to_nat(T_A(HiAddrBit downto 15));
1191
 
1192
        shortread:= false;
1193
        longread := false;
1194
 
1195
        --DUT specific timing
1196
        IF (T_CENeg'EVENT OR T_WENeg'EVENT OR T_A(HiAddrBit downto 2)'EVENT)AND   --
1197
           (status=read OR status=rd_cfi OR status=rd_secsi) THEN --OR status=readX)
1198
            longread := true;
1199
            CASE TimingModel IS
1200
                WHEN    "AM29LV640MH90R"    |
1201
                        "AM29LV640ML90R"   =>  WAIT FOR 95 ns;
1202
--                WHEN  "AM29LV640MH101"  |
1203
--                        "AM29LV640ML101"   =>  WAIT FOR 105 ns;
1204
--                WHEN  "AM29LV640MH101R" |
1205
--                        "AM29LV640ML101R"  =>  WAIT FOR 105 ns;
1206
--                WHEN  "AM29LV640MH112"  |
1207
--                      "AM29LV640ML112"   =>  WAIT FOR 115 ns;
1208
--                WHEN  "AM29LV640MH112R" |
1209
--                      "AM29LV640ML112R"  =>  WAIT FOR 115 ns;
1210
--                WHEN  "AM29LV640MH120"  |
1211
--                      "AM29LV640ML120"   =>  WAIT FOR 125 ns;
1212
--                WHEN  "AM29LV640MH120R" |
1213
--                      "AM29LV640ML120R"  =>  WAIT FOR 125 ns;
1214
                WHEN OTHERS                 =>
1215
                    REPORT "Timing model NOT supported : "&TimingModel
1216
                    SEVERITY error;
1217
            END CASE;
1218
 
1219
        ELSIF T_A(1 downto 0)'EVENT OR
1220
             (T_DQ(15)'EVENT AND T_BYTENeg='0')OR
1221
             (T_BYTENeg'EVENT) OR
1222
              T_OENeg'EVENT OR
1223
              (status/=read AND status/=rd_cfi AND
1224
               status/=rd_secsi)  THEN  --AND status/=readX)
1225
            shortread:=true;
1226
            CASE TimingModel IS
1227
                WHEN    "AM29LV640MH90R"    |
1228
                 "AM29LV640ML90R"   =>  WAIT FOR 30 ns;
1229
--                WHEN  "AM29LV640MH101"  |
1230
--                        "AM29LV640ML101"   =>  WAIT FOR 40 ns;
1231
--                WHEN  "AM29LV640MH101R" |
1232
--                        "AM29LV640ML101R"  =>  WAIT FOR 40 ns;
1233
--                WHEN  "AM29LV640MH112"  |
1234
--                        "AM29LV640ML112"   =>  WAIT FOR 45 ns;
1235
--                WHEN  "AM29LV640MH112R" |
1236
--                        "AM29LV640ML112R"  =>  WAIT FOR 45 ns;
1237
--                WHEN  "AM29LV640MH120"  |
1238
--                       "AM29LV640ML120"   =>  WAIT FOR 45 ns;
1239
--                WHEN  "AM29LV640MH120R" |
1240
--                      "AM29LV640ML120R"  =>  WAIT FOR 45 ns;
1241
                WHEN OTHERS                 =>
1242
                    REPORT "Timing model NOT supported : "&TimingModel
1243
                    SEVERITY error;
1244
            END CASE;
1245
 
1246
        END IF;
1247
 
1248
 
1249
 
1250
        --Checker
1251
        IF longread OR shortread THEN
1252
 
1253
            CASE status IS
1254
                WHEN none       =>
1255
                    toggle := false;
1256
 
1257
                -- read memory array data
1258
                WHEN read       =>
1259
                    toggle := false;
1260
                    Check_read (
1261
                        DQ       => T_DQ,
1262
                        D_lo     => mem(RSect)(RAddr),
1263
                        D_hi     => mem(RSect)(RAddr+1),
1264
                        Byte     => T_BYTENeg,
1265
                        check_err=> check_err);
1266
 
1267
                -- read secure silicon region
1268
                WHEN rd_secsi =>
1269
                    toggle := false;
1270
                    Check_SecSi (
1271
                        DQ       => T_DQ,
1272
                        D_lo     => SecSi(RAddr),
1273
                        D_hi     => SecSi(RAddr+1),
1274
                        Byte     => T_BYTENeg,
1275
                        check_err=>check_err);
1276
 
1277
 
1278
                --read CFI query codes
1279
                WHEN rd_cfi =>
1280
                    RAddr := to_nat(T_A(14 downto 0));   --x16 addressing
1281
                    toggle := false;
1282
                    Check_CFI (
1283
                        DQ       => T_DQ,
1284
                        D_lo     => CFI_array(RAddr) ,
1285
                        D_hi     => 0 ,
1286
                        Byte     => T_BYTENeg,
1287
                        check_err=>check_err);
1288
 
1289
 
1290
 
1291
                -- read Autoselect codes
1292
                WHEN rd_AS =>
1293
                    RAddr := to_nat(T_A(14 downto 0));   --x16 addressing
1294
                    toggle := false;
1295
                    Check_AS (
1296
                        DQ       => T_DQ,
1297
                        addr     => RAddr,
1298
                        ProtSecNum=>ProtSecNum,
1299
                        secProt  => Sec_Prot(RSect),
1300
                        FactoryProt=>FactoryProt ,
1301
                        Byte     => T_BYTENeg,
1302
                        AS_E     => to_slv(16#0C#,8),
1303
                        AS_F     => to_slv(1,8),
1304
 
1305
                        check_err=>check_err);
1306
 
1307
 
1308
                WHEN rd_HiZ   =>
1309
                    toggle:=false;
1310
                    Check_Z (
1311
                        DQ       => T_DQ,
1312
                        check_err=>check_err);
1313
 
1314
 
1315
 
1316
                WHEN readX   =>
1317
                    toggle:=false;
1318
                    Check_X (
1319
                        DQ       => T_DQ,
1320
                        check_err=>check_err);
1321
 
1322
 
1323
                WHEN erase_na  | erase_active  =>
1324
                    IF toggle THEN
1325
                        Check_Erase (
1326
                            DQ       => T_DQ(7 downto 0),
1327
                            sts      => status,
1328
                            toggle   => toggle_sts,
1329
                            sts_check=>sts_check,
1330
                            RY       => T_RY,
1331
                            check_err=>check_err);
1332
 
1333
                        toggle_sts := T_DQ(7 downto 0); --update toggle check
1334
                    END IF;
1335
 
1336
                WHEN ers_susp_e  =>
1337
                    IF toggle THEN
1338
                        Check_Ers_Susp (
1339
                            DQ       => T_DQ(7 downto 0),
1340
                            sts      => status,
1341
                            toggle   => toggle_sts,
1342
                            sts_check=>sts_check,
1343
                            RY       => T_RY,
1344
                            check_err=>check_err);
1345
 
1346
 
1347
                        toggle_sts := T_DQ(7 downto 0); --update toggle check
1348
                    END IF;
1349
 
1350
--
1351
 
1352
                WHEN ers_susp_prog_na  | ers_susp_prog  =>
1353
                    IF toggle THEN
1354
                        Check_Ers_Susp_Prog (
1355
                            DQ       => T_DQ(7 downto 0),
1356
                            sts      => status,
1357
                            toggle   => toggle_sts,
1358
                            sts_check=>sts_check,
1359
                            RY       => T_RY,
1360
                            check_err=>check_err);
1361
 
1362
                        toggle_sts := T_DQ(7 downto 0); --update toggle check
1363
                    END IF;
1364
 
1365
--
1366
 
1367
                WHEN prog_na  | prog_active  =>
1368
                    IF toggle THEN
1369
                        Check_Progr (
1370
                            DQ       => T_DQ(7 downto 0),
1371
                            sts      => status,
1372
                            toggle   => toggle_sts,
1373
                            sts_check=>sts_check,
1374
                            RY       => T_RY,
1375
                            check_err=>check_err);
1376
 
1377
                        toggle_sts := T_DQ(7 downto 0); --update toggle check
1378
                    END IF;
1379
 
1380
                WHEN buff_wr_busy  | buff_wr_N_busy  =>
1381
                    IF toggle THEN
1382
                        Check_Buff_Busy (
1383
                            DQ       => T_DQ(7 downto 0),
1384
                            sts      => status,
1385
                            toggle   => toggle_sts,
1386
                            sts_check=>sts_check,
1387
                            RY       => T_RY,
1388
                            check_err=>check_err);
1389
 
1390
                        toggle_sts := T_DQ(7 downto 0); --update toggle check
1391
                    END IF;
1392
 
1393
                WHEN buff_abort =>
1394
                    IF toggle THEN
1395
                        Check_Abort (
1396
                            DQ       => T_DQ(7 downto 0),
1397
                            sts      => status,
1398
                            toggle   => toggle_sts,
1399
                            sts_check=>sts_check,
1400
                            RY       => T_RY,
1401
                            check_err=>check_err);
1402
 
1403
                        toggle_sts := T_DQ(7 downto 0); --update toggle check
1404
                    END IF;
1405
                WHEN OTHERS     =>  null;
1406
            END CASE;
1407
 
1408
            -- get firs data for toggle check
1409
            CASE status IS
1410
                WHEN prog_active      | prog_na      |
1411
                     erase_active     | erase_na     |
1412
                     ers_susp_e       |
1413
                     ers_susp_prog    | ers_susp_prog_na |
1414
                     buff_wr_busy     | buff_wr_N_busy |
1415
                     buff_abort       | get_toggle   =>
1416
 
1417
                     IF (NOT toggle) OR (status=get_toggle) THEN
1418
                        toggle:=true;
1419
                        toggle_sts := T_DQ(7 downto 0);
1420
                     END IF;
1421
 
1422
                WHEN OTHERS => null;
1423
            END CASE;
1424
 
1425
 
1426
        END IF;
1427
 
1428
    END IF;
1429
 
1430
    WAIT ON T_A, T_CENeg, T_OENeg, T_WENeg, T_DQ(15), T_BYTENeg;
1431
 
1432
END PROCESS checker;
1433
 
1434
 
1435
default:    PROCESS
1436
        -- text file input variables
1437
        FILE mem_f          : text  is  mem_file;
1438
        FILE prot_f         : text  is  prot_file;
1439
        FILE secsi_f        : text  is  secsi_file;
1440
 
1441
        VARIABLE S_ind         : NATURAL RANGE 0 TO SecNum:= 0;
1442
        VARIABLE ind           : NATURAL RANGE 0 TO SecSize:= 0;
1443
        VARIABLE buf           : line;
1444
 
1445
BEGIN
1446
    --Preload Control
1447
    -----------------------------------------------------------------------
1448
    -- File Read Section
1449
    -----------------------------------------------------------------------
1450
    IF UserPreload THEN
1451
            --- Sector protection preload
1452
            IF (prot_file /= "none" ) THEN
1453
                ind   := 0;
1454
                FactoryProt := '0';
1455
                Sec_Prot := (OTHERS => '0');
1456
                WHILE (not ENDFILE (prot_f)) LOOP
1457
                    READLINE (prot_f, buf);
1458
                    IF buf(1) = '/' THEN
1459
                        NEXT;
1460
                    ELSIF buf(1) = '@' THEN
1461
                        ind := h(buf(2 to 3)); --address
1462
                    ELSE
1463
                        IF ind > SecNum THEN
1464
                            --SecSi Factory protect preload
1465
                            IF buf(1)='1' THEN
1466
                                FactoryProt := '1';
1467
                            END IF;
1468
                        ELSE
1469
                            -- Standard Sector prload
1470
                            IF buf(1)='1' THEN
1471
                                Sec_Prot(ind):= '1';
1472
                            END IF;
1473
                            ind := ind + 1;
1474
                        END IF;
1475
                    END IF;
1476
                END LOOP;
1477
            END IF;
1478
 
1479
            -- Secure Silicon Sector Region preload
1480
            IF (SecSi_file /= "none" ) THEN
1481
                SecSi := (OTHERS => MaxData);
1482
                ind := 0;
1483
                WHILE (not ENDFILE (SecSi_f)) LOOP
1484
                    READLINE (SecSi_f, buf);
1485
                    IF buf(1) = '/' THEN
1486
                        NEXT;
1487
                    ELSIF buf(1) = '@' THEN
1488
                        ind := h(buf(2 to 3)); --address
1489
                    ELSE
1490
                        IF ind <= SecSiSize THEN
1491
                            SecSi(ind) := h(buf(1 TO 2));
1492
                            ind := ind + 1;
1493
                        END IF;
1494
                    END IF;
1495
                END LOOP;
1496
            END IF;
1497
 
1498
            --- Memory Preload
1499
            IF (mem_file /= "none" ) THEN
1500
                ind   := 0;
1501
                Mem := (OTHERS => (OTHERS => MaxData));
1502
                -- load sector 0
1503
                WHILE (not ENDFILE (mem_f)) LOOP
1504
                    READLINE (mem_f, buf);
1505
                    IF buf(1) = '/' THEN
1506
                        NEXT;
1507
                    ELSIF buf(1) = '@' THEN
1508
                        ind := h(buf(2 to 5)); --address
1509
                    ELSE
1510
                        IF ind <= SecSize THEN
1511
                            Mem(0)(ind) := h(buf(1 to 2));
1512
                            ind := ind + 1;
1513
                        END IF;
1514
                    END IF;
1515
                END LOOP;
1516
                -- load other sectors
1517
                FOR i IN 1 TO SecNum LOOP
1518
                    Mem(i) := Mem(0);
1519
                END LOOP;
1520
            END IF;
1521
 
1522
    END IF;
1523
    -----------------------------------------------------------------------
1524
    --CFI array data / AM29LV640MH90R !!! DEVICE SPECIFIC
1525
    -----------------------------------------------------------------------
1526
    --CFI query identification string
1527
    -- !!!!!! WORD ADDRESSES (x16) - for x8 addressing double addr
1528
    --CFI query identification string
1529
    CFI_array(16#10#) := 16#51#;
1530
    CFI_array(16#11#) := 16#52#;
1531
    CFI_array(16#12#) := 16#59#;
1532
    CFI_array(16#13#) := 16#02#;
1533
    CFI_array(16#14#) := 16#00#;
1534
    CFI_array(16#15#) := 16#40#;
1535
    CFI_array(16#16#) := 16#00#;
1536
    CFI_array(16#17#) := 16#00#;
1537
    CFI_array(16#18#) := 16#00#;
1538
    CFI_array(16#19#) := 16#00#;
1539
    CFI_array(16#1A#) := 16#00#;
1540
    --system interface string
1541
    CFI_array(16#1B#) := 16#27#;
1542
    CFI_array(16#1C#) := 16#36#;
1543
    CFI_array(16#1D#) := 16#00#;
1544
    CFI_array(16#1E#) := 16#00#;
1545
    CFI_array(16#1F#) := 16#07#;
1546
    CFI_array(16#20#) := 16#07#;
1547
    CFI_array(16#21#) := 16#0A#;
1548
    CFI_array(16#22#) := 16#00#;
1549
    CFI_array(16#23#) := 16#01#;
1550
    CFI_array(16#24#) := 16#05#;
1551
    CFI_array(16#25#) := 16#04#;
1552
    CFI_array(16#26#) := 16#00#;
1553
    --device geometry definition
1554
    CFI_array(16#27#) := 16#17#;
1555
    CFI_array(16#28#) := 16#02#;
1556
    CFI_array(16#29#) := 16#00#;
1557
    CFI_array(16#2A#) := 16#05#;
1558
    CFI_array(16#2B#) := 16#00#;
1559
    CFI_array(16#2C#) := 16#01#;
1560
    CFI_array(16#2D#) := 16#7F#;
1561
    CFI_array(16#2E#) := 16#00#;
1562
    CFI_array(16#2F#) := 16#00#;
1563
    CFI_array(16#30#) := 16#01#;
1564
    CFI_array(16#31#) := 16#00#;
1565
    CFI_array(16#32#) := 16#00#;
1566
    CFI_array(16#33#) := 16#00#;
1567
    CFI_array(16#34#) := 16#00#;
1568
    CFI_array(16#35#) := 16#00#;
1569
    CFI_array(16#36#) := 16#00#;
1570
    CFI_array(16#37#) := 16#00#;
1571
    CFI_array(16#38#) := 16#00#;
1572
    CFI_array(16#39#) := 16#00#;
1573
    CFI_array(16#3A#) := 16#00#;
1574
    CFI_array(16#3B#) := 16#00#;
1575
    CFI_array(16#3C#) := 16#00#;
1576
    --primary vendor-specific extended query
1577
    CFI_array(16#40#) := 16#50#;
1578
    CFI_array(16#41#) := 16#52#;
1579
    CFI_array(16#42#) := 16#49#;
1580
    CFI_array(16#43#) := 16#31#;
1581
    CFI_array(16#44#) := 16#33#;
1582
    CFI_array(16#45#) := 16#08#;
1583
    CFI_array(16#46#) := 16#02#;
1584
    CFI_array(16#47#) := 16#01#;
1585
    CFI_array(16#48#) := 16#01#;
1586
    CFI_array(16#49#) := 16#04#;
1587
    CFI_array(16#4A#) := 16#00#;
1588
    CFI_array(16#4B#) := 16#00#;
1589
    CFI_array(16#4C#) := 16#01#;
1590
    CFI_array(16#4D#) := 16#B5#;
1591
    CFI_array(16#4E#) := 16#C5#;
1592
    IF TimingModel(11) = 'L' THEN
1593
        CFI_array(16#4F#) := 16#04#;
1594
    ELSE
1595
        CFI_array(16#4F#) := 16#05#; --uniform sectors top protect
1596
    END IF;
1597
    CFI_array(16#50#) := 16#01#;
1598
 
1599
    WAIT;
1600
 
1601
END PROCESS default;
1602
 
1603
 
1604
 
1605
END vhdl_behavioral;
1606
 

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