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URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

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[/] [or1200_soc/] [trunk/] [src/] [soc_top.v] - Blame information for rev 21

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Line No. Rev Author Line
1 21 qaztronic
// --------------------------------------------------------------------
2
//
3
// --------------------------------------------------------------------
4
 
5
 
6
`include "timescale.v"
7
`include "or1200_defines.v"
8
`include "soc_defines.v"
9
 
10
 
11
module soc_top
12
(
13
  ////////////////////////////  UART  ////////////////////////////
14
  output          uart_txd_0,       //  UART Transmitter
15
  input           uart_rxd_0,       //  UART Receiver
16
  ///////////////////////   SDRAM Interface ////////////////////////
17
//   inout [15:0]    dram_dq,        //  sdram data bus 16 bits
18
//   output  [11:0]  dram_addr,      //  sdram address bus 12 bits
19
//   output          dram_ldqm,      //  sdram low-byte data mask
20
//   output          dram_udqm,      //  sdram high-byte data mask
21
//   output          dram_we_n,      //  sdram write enable
22
//   output          dram_cas_n,     //  sdram column address strobe
23
//   output          dram_ras_n,     //  sdram row address strobe
24
//   output          dram_cs_n,      //  sdram chip select
25
//   output          dram_ba_0,      //  sdram bank address 0
26
//   output          dram_ba_1,      //  sdram bank address 0
27
//   output          dram_clk,       //  sdram clock
28
//   output          dram_cke,       //  sdram clock enable
29
  ////////////////////////  Flash Interface ////////////////////////
30
  inout [7:0]     fl_dq,          //  flash data bus 8 bits
31
  output  [21:0]  fl_addr,        //  flash address bus 22 bits
32
  output          fl_we_n,        //  flash write enable
33
  output          fl_rst_n,       //  flash reset
34
  output          fl_oe_n,        //  flash output enable
35
  output          fl_ce_n,        //  flash chip enable
36
  ////////////////////////  sram interface  ////////////////////////
37
  inout   [15:0]  sram_dq,        //  sram data bus 16 bits
38
  output  [17:0]  sram_addr,      //  sram address bus 18 bits
39
  output          sram_ub_n,      //  sram high-byte data mask
40
  output          sram_lb_n,      //  sram low-byte data mask
41
  output          sram_we_n,      //  sram write enable
42
  output          sram_ce_n,      //  sram chip enable
43
  output          sram_oe_n,      //  sram output enable
44
 
45
  input   [31:0]  gpio_a_aux_i,
46
  input   [31:0]  gpio_a_ext_pad_i,
47
  output  [31:0]  gpio_a_ext_pad_o,
48
  output  [31:0]  gpio_a_ext_padoe_o,
49
 
50
  input   [31:0]  gpio_b_aux_i,
51
  input   [31:0]  gpio_b_ext_pad_i,
52
  output  [31:0]  gpio_b_ext_pad_o,
53
  output  [31:0]  gpio_b_ext_padoe_o,
54
 
55
  input   [31:0]  gpio_c_aux_i,
56
  input   [31:0]  gpio_c_ext_pad_i,
57
  output  [31:0]  gpio_c_ext_pad_o,
58
  output  [31:0]  gpio_c_ext_padoe_o,
59
 
60
  input   [31:0]  gpio_d_aux_i,
61
  input   [31:0]  gpio_d_ext_pad_i,
62
  output  [31:0]  gpio_d_ext_pad_o,
63
  output  [31:0]  gpio_d_ext_padoe_o,
64
 
65
  input   [31:0]  gpio_e_aux_i,
66
  input   [31:0]  gpio_e_ext_pad_i,
67
  output  [31:0]  gpio_e_ext_pad_o,
68
  output  [31:0]  gpio_e_ext_padoe_o,
69
 
70
  input   [31:0]  gpio_f_aux_i,
71
  input   [31:0]  gpio_f_ext_pad_i,
72
  output  [31:0]  gpio_f_ext_pad_o,
73
  output  [31:0]  gpio_f_ext_padoe_o,
74
 
75
  input   [31:0]  gpio_g_aux_i,
76
  input   [31:0]  gpio_g_ext_pad_i,
77
  output  [31:0]  gpio_g_ext_pad_o,
78
  output  [31:0]  gpio_g_ext_padoe_o,
79
 
80
  input [3:0]     boot_strap,
81
 
82
`ifdef USE_DEBUG_0
83
  output [255:0]  debug_0,
84
`endif
85
 
86
  input           sys_clk,
87
  input           sys_rst
88
);
89
 
90
 
91
  //---------------------------------------------------
92
  // or1200_top
93
  //---------------------------------------------------
94
  parameter dw = `OR1200_OPERAND_WIDTH;
95
  parameter aw = `OR1200_OPERAND_WIDTH;
96
 
97
 
98
  // System
99
  wire      clk_i = sys_clk;
100
  wire      rst_i = sys_rst;
101
 
102
  //---------------------------------------------------
103
  // Instruction WISHBONE interface
104
  wire            iwb_clk_i = sys_clk;
105
  wire            iwb_rst_i = sys_rst;
106
  wire            iwb_ack_i;
107
  wire            iwb_err_i;
108
  wire            iwb_rty_i;
109
  wire  [dw-1:0]  iwb_dat_i;
110
  wire            iwb_cyc_o;
111
  wire  [aw-1:0]  iwb_adr_o;
112
  wire            iwb_stb_o;
113
  wire            iwb_we_o;
114
  wire  [3:0]     iwb_sel_o;
115
  wire  [dw-1:0]  iwb_dat_o;
116
  wire            iwb_cab_o;
117
 
118
  //---------------------------------------------------
119
  // Data WISHBONE interface
120
  wire            dwb_clk_i = sys_clk;
121
  wire            dwb_rst_i = sys_rst;
122
  wire            dwb_ack_i;
123
  wire            dwb_err_i;
124
  wire            dwb_rty_i;
125
  wire  [dw-1:0]  dwb_dat_i;
126
  wire            dwb_cyc_o;
127
  wire  [aw-1:0]  dwb_adr_o;
128
  wire            dwb_stb_o;
129
  wire            dwb_we_o;
130
  wire  [3:0]     dwb_sel_o;
131
  wire  [dw-1:0]  dwb_dat_o;
132
  wire            dwb_cab_o;
133
 
134
  or1200_top i_or1200_top(
135
                          //---------------------------------------------------
136
                          // Instruction WISHBONE interface
137
                          .iwb_clk_i(iwb_clk_i),  // clock input
138
                          .iwb_rst_i(iwb_rst_i),  // reset input
139
                          .iwb_ack_i(iwb_ack_i),  // normal termination
140
                          .iwb_err_i(iwb_err_i),  // termination w/ error
141
                          .iwb_rty_i(iwb_rty_i),  // termination w/ retry
142
                          .iwb_dat_i(iwb_dat_i),  // input data bus
143
                          .iwb_cyc_o(iwb_cyc_o),  // cycle valid output
144
                          .iwb_adr_o(iwb_adr_o),  // address bus outputs
145
                          .iwb_stb_o(iwb_stb_o),  // strobe output
146
                          .iwb_we_o(iwb_we_o),  // indicates write transfer
147
                          .iwb_sel_o(iwb_sel_o),  // byte select outputs
148
                          .iwb_dat_o(iwb_dat_o),  // output data bus
149
  `ifdef OR1200_WB_CAB
150
                          .iwb_cab_o(iwb_cab_o),  // indicates consecutive address burst
151
  `endif
152
  `ifdef OR1200_WB_B3
153
                          .iwb_cti_o(iwb_cti_o),  // cycle type identifier
154
                          .iwb_bte_o(iwb_bte_o),  // burst type extension
155
  `endif
156
 
157
                          //---------------------------------------------------
158
                          // Data WISHBONE interface
159
                          .dwb_clk_i(dwb_clk_i),  // clock input
160
                          .dwb_rst_i(dwb_rst_i),  // reset input
161
                          .dwb_ack_i(dwb_ack_i),  // normal termination
162
                          .dwb_err_i(dwb_err_i),  // termination w/ error
163
                          .dwb_rty_i(dwb_rty_i),  // termination w/ retry
164
                          .dwb_dat_i(dwb_dat_i),  // input data bus
165
                          .dwb_cyc_o(dwb_cyc_o),  // cycle valid output
166
                          .dwb_adr_o(dwb_adr_o),  // address bus outputs
167
                          .dwb_stb_o(dwb_stb_o),  // strobe output
168
                          .dwb_we_o(dwb_we_o),  // indicates write transfer
169
                          .dwb_sel_o(dwb_sel_o),  // byte select outputs
170
                          .dwb_dat_o(dwb_dat_o),  // output data bus
171
  `ifdef OR1200_WB_CAB
172
                          .dwb_cab_o(dwb_cab_o),  // indicates consecutive address burst
173
  `endif
174
  `ifdef OR1200_WB_B3
175
                          .dwb_cti_o(dwb_cti_o),  // cycle type identifier
176
                          .dwb_bte_o(dwb_bte_o),  // burst type extension
177
  `endif
178
 
179
                          //---------------------------------------------------
180
                          // External Debug Interface
181
                          .dbg_stall_i(1'b0), // External Stall Input
182
//                           .dbg_ewt_i(dbg_ewt_i), // External Watchpoint Trigger Input
183
//                           .dbg_lss_o(dbg_lss_o), // External Load/Store Unit Status
184
//                           .dbg_is_o(dbg_is_o), // External Insn Fetch Status
185
//                           .dbg_wp_o(dbg_wp_o), // Watchpoints Outputs
186
//                           .dbg_bp_o(dbg_bp_o), // Breakpoint Output
187
//                           .dbg_stb_i(dbg_stb_i),      // External Address/Data Strobe
188
//                           .dbg_we_i(dbg_we_i),       // External Write Enable
189
//                           .dbg_adr_i(dbg_adr_i), // External Address Input
190
//                           .dbg_dat_i(dbg_dat_i), // External Data Input
191
//                           .dbg_dat_o(dbg_dat_o), // External Data Output
192
//                           .dbg_ack_o(dbg_ack_o), // External Data Acknowledge (not WB compatible)
193
 
194
 
195
                          //---------------------------------------------------
196
                          // RAM BIST
197
  `ifdef OR1200_BIST
198
                          .mbist_si_i(mbist_si_i),
199
                          .mbist_ctrl_i(mbist_ctrl_i),
200
                          .mbist_so_o(mbist_so_o),
201
  `endif
202
 
203
                        //---------------------------------------------------
204
                        // Power Management
205
//                         .pm_cpustall_i(pm_cpustall_i),
206
//                         .pm_clksd_o(pm_clksd_o),
207
//                         .pm_dc_gate_o(pm_dc_gate_o),
208
//                         .pm_ic_gate_o(pm_ic_gate_o),
209
//                         .pm_dmmu_gate_o(pm_dmmu_gate_o),
210
//                         .pm_immu_gate_o(pm_immu_gate_o),
211
//                         .pm_tt_gate_o(pm_tt_gate_o),
212
//                         .pm_cpu_gate_o(pm_cpu_gate_o),
213
//                         .pm_wakeup_o(pm_wakeup_o),
214
//                         .pm_lvolt_o(pm_lvolt_o),
215
//
216
                        //---------------------------------------------------
217
                        // System
218
//                         .clmode_i(clmode_i), // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
219
//                         .pic_ints_i(pic_ints_i),
220
                          .clk_i(clk_i),
221
                          .rst_i(rst_i)
222
                        );
223
 
224
  //---------------------------------------------------
225
  // remap mux
226
  wire [1:0] boot_remap;
227
 
228
  // instruction wb remap mux
229
  reg  [1:0] iwb_remap_select;
230
  reg  [3:0] iwb_remap_nibble;
231
 
232
  wire [31:0] iwb_remap_adr_o = { iwb_remap_nibble, iwb_adr_o[27:0] };
233
 
234
  always @(*)
235
    casez( { boot_remap, iwb_adr_o[31:28] } )
236
      6'b00_????: iwb_remap_select = 2'b00;
237
      6'b01_0000: iwb_remap_select = 2'b01;
238
      6'b10_0000: iwb_remap_select = 2'b10;
239
      6'b11_0000: iwb_remap_select = 2'b11;
240
      default:    iwb_remap_select = 2'b00;
241
    endcase
242
 
243
  always @(*)
244
    case( iwb_remap_select )
245
      2'b00: iwb_remap_nibble = iwb_adr_o[31:28];
246
      2'b01: iwb_remap_nibble = 4'b0001;
247
      2'b10: iwb_remap_nibble = 4'b0010;
248
      2'b11: iwb_remap_nibble = 4'b0011;
249
    endcase
250
 
251
  // data wb remap mux
252
  reg  [1:0] dwb_remap_select;
253
  reg  [3:0] dwb_remap_nibble;
254
 
255
  wire [31:0] dwb_remap_adr_o = { dwb_remap_nibble, dwb_adr_o[27:0] };
256
 
257
  always @(*)
258
    casez( { boot_remap, dwb_adr_o[31:28] } )
259
      6'b00_????: dwb_remap_select = 2'b00;
260
      6'b01_0000: dwb_remap_select = 2'b01;
261
      6'b10_0000: dwb_remap_select = 2'b10;
262
      6'b11_0000: dwb_remap_select = 2'b11;
263
      default:    dwb_remap_select = 2'b00;
264
    endcase
265
 
266
  always @(*)
267
    case( dwb_remap_select )
268
      2'b00: dwb_remap_nibble = dwb_adr_o[31:28];
269
      2'b01: dwb_remap_nibble = 4'b0001;
270
      2'b10: dwb_remap_nibble = 4'b0010;
271
      2'b11: dwb_remap_nibble = 4'b0011;
272
    endcase
273
 
274
 
275
  //---------------------------------------------------
276
  // wb_conmax_top
277
 
278
  // Slave 0 Interface
279
  parameter   sw = dw / 8;  // Number of Select Lines
280
 
281
  wire  [dw-1:0]  s0_data_i;
282
  wire  [dw-1:0]  s0_data_o;
283
  wire  [aw-1:0]  s0_addr_o;
284
  wire  [sw-1:0]  s0_sel_o;
285
  wire            s0_we_o;
286
  wire            s0_cyc_o;
287
  wire            s0_stb_o;
288
  wire            s0_ack_i;
289
  wire            s0_err_i;
290
  wire            s0_rty_i;
291
 
292
  wire  [dw-1:0]  s1_data_i;
293
  wire  [dw-1:0]  s1_data_o;
294
  wire  [aw-1:0]  s1_addr_o;
295
  wire  [sw-1:0]  s1_sel_o;
296
  wire            s1_we_o;
297
  wire            s1_cyc_o;
298
  wire            s1_stb_o;
299
  wire            s1_ack_i;
300
  wire            s1_err_i;
301
  wire            s1_rty_i;
302
 
303
  wire  [dw-1:0]  s2_data_i;
304
  wire  [dw-1:0]  s2_data_o;
305
  wire  [aw-1:0]  s2_addr_o;
306
  wire  [sw-1:0]  s2_sel_o;
307
  wire            s2_we_o;
308
  wire            s2_cyc_o;
309
  wire            s2_stb_o;
310
  wire            s2_ack_i;
311
  wire            s2_err_i;
312
  wire            s2_rty_i;
313
 
314
  wire  [dw-1:0]  s3_data_i;
315
  wire  [dw-1:0]  s3_data_o;
316
  wire  [aw-1:0]  s3_addr_o;
317
  wire  [sw-1:0]  s3_sel_o;
318
  wire            s3_we_o;
319
  wire            s3_cyc_o;
320
  wire            s3_stb_o;
321
  wire            s3_ack_i;
322
  wire            s3_err_i;
323
  wire            s3_rty_i;
324
 
325
  wire  [dw-1:0]  s4_data_i;
326
  wire  [dw-1:0]  s4_data_o;
327
  wire  [aw-1:0]  s4_addr_o;
328
  wire  [sw-1:0]  s4_sel_o;
329
  wire            s4_we_o;
330
  wire            s4_cyc_o;
331
  wire            s4_stb_o;
332
  wire            s4_ack_i;
333
  wire            s4_err_i;
334
  wire            s4_rty_i;
335
 
336
  wire  [dw-1:0]  s5_data_i;
337
  wire  [dw-1:0]  s5_data_o;
338
  wire  [aw-1:0]  s5_addr_o;
339
  wire  [sw-1:0]  s5_sel_o;
340
  wire            s5_we_o;
341
  wire            s5_cyc_o;
342
  wire            s5_stb_o;
343
  wire            s5_ack_i;
344
  wire            s5_err_i;
345
  wire            s5_rty_i;
346
 
347
  wire  [dw-1:0]  s6_data_i;
348
  wire  [dw-1:0]  s6_data_o;
349
  wire  [aw-1:0]  s6_addr_o;
350
  wire  [sw-1:0]  s6_sel_o;
351
  wire            s6_we_o;
352
  wire            s6_cyc_o;
353
  wire            s6_stb_o;
354
  wire            s6_ack_i;
355
  wire            s6_err_i;
356
  wire            s6_rty_i;
357
 
358
  wb_conmax_top
359
    i_wb_conmax_top(
360
                      // Master 0 Interface
361
                      .m0_data_i(iwb_dat_o),
362
                      .m0_data_o(iwb_dat_i),
363
                      .m0_addr_i( iwb_remap_adr_o ),
364
//                       .m0_addr_i( iwb_adr_o ),
365
                      .m0_sel_i(iwb_sel_o),
366
                      .m0_we_i(iwb_we_o),
367
                      .m0_cyc_i(iwb_cyc_o),
368
                      .m0_stb_i(iwb_stb_o),
369
                      .m0_ack_o(iwb_ack_i),
370
                      .m0_err_o(iwb_err_i),
371
                      .m0_rty_o(iwb_rty_i),
372
                      // Master 1 Interface 
373
                      .m1_data_i(dwb_dat_o),
374
                      .m1_data_o(dwb_dat_i),
375
                      .m1_addr_i(dwb_remap_adr_o),
376
//                       .m1_addr_i(dwb_adr_o),
377
                      .m1_sel_i(dwb_sel_o),
378
                      .m1_we_i(dwb_we_o),
379
                      .m1_cyc_i(dwb_cyc_o),
380
                      .m1_stb_i(dwb_stb_o),
381
                      .m1_ack_o(dwb_ack_i),
382
                      .m1_err_o(dwb_err_i),
383
                      .m1_rty_o(dwb_rty_i),
384
                      // Master 2 Interface
385
                      .m2_data_i(32'h0000_0000),
386
                      .m2_addr_i(32'h0000_0000),
387
                      .m2_sel_i(4'h0),
388
                      .m2_we_i(1'b0),
389
                      .m2_cyc_i(1'b0),
390
                      .m2_stb_i(1'b0),
391
                      // Master 3 Interface
392
                      .m3_data_i(32'h0000_0000),
393
                      .m3_addr_i(32'h0000_0000),
394
                      .m3_sel_i(4'h0),
395
                      .m3_we_i(1'b0),
396
                      .m3_cyc_i(1'b0),
397
                      .m3_stb_i(1'b0),
398
                      // Master 4 Interface
399
                      .m4_data_i(32'h0000_0000),
400
                      .m4_addr_i(32'h0000_0000),
401
                      .m4_sel_i(4'h0),
402
                      .m4_we_i(1'b0),
403
                      .m4_cyc_i(1'b0),
404
                      .m4_stb_i(1'b0),
405
                      // Master 5 Interface
406
                      .m5_data_i(32'h0000_0000),
407
                      .m5_addr_i(32'h0000_0000),
408
                      .m5_sel_i(4'h0),
409
                      .m5_we_i(1'b0),
410
                      .m5_cyc_i(1'b0),
411
                      .m5_stb_i(1'b0),
412
                      // Master 6 Interface
413
                      .m6_data_i(32'h0000_0000),
414
                      .m6_addr_i(32'h0000_0000),
415
                      .m6_sel_i(4'h0),
416
                      .m6_we_i(1'b0),
417
                      .m6_cyc_i(1'b0),
418
                      .m6_stb_i(1'b0),
419
                      // Master 7 Interface
420
                      .m7_data_i(32'h0000_0000),
421
                      .m7_addr_i(32'h0000_0000),
422
                      .m7_sel_i(4'h0),
423
                      .m7_we_i(1'b0),
424
                      .m7_cyc_i(1'b0),
425
                      .m7_stb_i(1'b0),
426
 
427
                      // Slave 0 Interface
428
                      .s0_data_i(s0_data_i),
429
                      .s0_data_o(s0_data_o),
430
                      .s0_addr_o(s0_addr_o),
431
                      .s0_sel_o(s0_sel_o),
432
                      .s0_we_o(s0_we_o),
433
                      .s0_cyc_o(s0_cyc_o),
434
                      .s0_stb_o(s0_stb_o),
435
                      .s0_ack_i(s0_ack_i),
436
                      .s0_err_i(s0_err_i),
437
                      .s0_rty_i(s0_rty_i),
438
                      // Slave 1 Interface
439
                      .s1_data_i(s1_data_i),
440
                      .s1_data_o(s1_data_o),
441
                      .s1_addr_o(s1_addr_o),
442
                      .s1_sel_o(s1_sel_o),
443
                      .s1_we_o(s1_we_o),
444
                      .s1_cyc_o(s1_cyc_o),
445
                      .s1_stb_o(s1_stb_o),
446
                      .s1_ack_i(s1_ack_i),
447
                      .s1_err_i(s1_err_i),
448
                      .s1_rty_i(s1_rty_i),
449
                      // Slave 2 Interface
450
                      .s2_data_i(s2_data_i),
451
                      .s2_data_o(s2_data_o),
452
                      .s2_addr_o(s2_addr_o),
453
                      .s2_sel_o(s2_sel_o),
454
                      .s2_we_o(s2_we_o),
455
                      .s2_cyc_o(s2_cyc_o),
456
                      .s2_stb_o(s2_stb_o),
457
                      .s2_ack_i(s2_ack_i),
458
                      .s2_err_i(s2_err_i),
459
                      .s2_rty_i(s2_rty_i),
460
                      // Slave 3 Interface
461
                      .s3_data_i(s3_data_i),
462
                      .s3_data_o(s3_data_o),
463
                      .s3_addr_o(s3_addr_o),
464
                      .s3_sel_o(s3_sel_o),
465
                      .s3_we_o(s3_we_o),
466
                      .s3_cyc_o(s3_cyc_o),
467
                      .s3_stb_o(s3_stb_o),
468
                      .s3_ack_i(s3_ack_i),
469
                      .s3_err_i(s3_err_i),
470
                      .s3_rty_i(s3_rty_i),
471
                      // Slave 4 Interface
472
                      .s4_data_i(s4_data_i),
473
                      .s4_data_o(s4_data_o),
474
                      .s4_addr_o(s4_addr_o),
475
                      .s4_sel_o(s4_sel_o),
476
                      .s4_we_o(s4_we_o),
477
                      .s4_cyc_o(s4_cyc_o),
478
                      .s4_stb_o(s4_stb_o),
479
                      .s4_ack_i(s4_ack_i),
480
                      .s4_err_i(s4_err_i),
481
                      .s4_rty_i(s4_rty_i),
482
                      // Slave 5 Interface
483
                      .s5_data_i(s5_data_i),
484
                      .s5_data_o(s5_data_o),
485
                      .s5_addr_o(s5_addr_o),
486
                      .s5_sel_o(s5_sel_o),
487
                      .s5_we_o(s5_we_o),
488
                      .s5_cyc_o(s5_cyc_o),
489
                      .s5_stb_o(s5_stb_o),
490
                      .s5_ack_i(s5_ack_i),
491
                      .s5_err_i(s5_err_i),
492
                      .s5_rty_i(s5_rty_i),
493
                      // Slave 6 Interface
494
                      .s6_data_i(s6_data_i),
495
                      .s6_data_o(s6_data_o),
496
                      .s6_addr_o(s6_addr_o),
497
                      .s6_sel_o(s6_sel_o),
498
                      .s6_we_o(s6_we_o),
499
                      .s6_cyc_o(s6_cyc_o),
500
                      .s6_stb_o(s6_stb_o),
501
                      .s6_ack_i(s6_ack_i),
502
                      .s6_err_i(s6_err_i),
503
                      .s6_rty_i(s6_rty_i),
504
                      // Slave 7 Interface
505
                      .s7_data_i(32'h0000_0000),
506
                      .s7_ack_i(1'b0),
507
                      .s7_err_i(1'b0),
508
                      .s7_rty_i(1'b0),
509
                      // Slave 8 Interface
510
                      .s8_data_i(32'h0000_0000),
511
                      .s8_ack_i(1'b0),
512
                      .s8_err_i(1'b0),
513
                      .s8_rty_i(1'b0),
514
                      // Slave 9 Interface
515
                      .s9_data_i(32'h0000_0000),
516
                      .s9_ack_i(1'b0),
517
                      .s9_err_i(1'b0),
518
                      .s9_rty_i(1'b0),
519
                      // Slave 10 Interface
520
                      .s10_data_i(32'h0000_0000),
521
                      .s10_ack_i(1'b0),
522
                      .s10_err_i(1'b0),
523
                      .s10_rty_i(1'b0),
524
                      // Slave 11 Interface
525
                      .s11_data_i(32'h0000_0000),
526
                      .s11_ack_i(1'b0),
527
                      .s11_err_i(1'b0),
528
                      .s11_rty_i(1'b0),
529
                      // Slave 12 Interface
530
                      .s12_data_i(32'h0000_0000),
531
                      .s12_ack_i(1'b0),
532
                      .s12_err_i(1'b0),
533
                      .s12_rty_i(1'b0),
534
                      // Slave 13 Interface
535
                      .s13_data_i(32'h0000_0000),
536
                      .s13_ack_i(1'b0),
537
                      .s13_err_i(1'b0),
538
                      .s13_rty_i(1'b0),
539
                      // Slave 14 Interface
540
                      .s14_data_i(32'h0000_0000),
541
                      .s14_ack_i(1'b0),
542
                      .s14_err_i(1'b0),
543
                      .s14_rty_i(1'b0),
544
                      // Slave 15 Interface
545
                      .s15_data_i(32'h0000_0000),
546
                      .s15_ack_i(1'b0),
547
                      .s15_err_i(1'b0),
548
                      .s15_rty_i(1'b0),
549
 
550
                      .clk_i(clk_i),
551
                      .rst_i(rst_i)
552
                    );
553
 
554
  //---------------------------------------------------
555
  // soc_boot
556
  wire  [1:0] boot_select;
557
 
558
  soc_boot i_soc_boot(
559
                      .mem_data_i(s0_data_o),
560
                      .mem_data_o(s0_data_i),
561
                      .mem_addr_i(s0_addr_o),
562
                      .mem_sel_i(s0_sel_o),
563
                      .mem_we_i(s0_we_o),
564
                      .mem_cyc_i(s0_cyc_o),
565
                      .mem_stb_i(s0_stb_o),
566
                      .mem_ack_o(s0_ack_i),
567
                      .mem_err_o(s0_err_i),
568
                      .mem_rty_o(s0_rty_i),
569
 
570
                      .boot_select(boot_select),
571
 
572
                      .mem_clk_i(clk_i),
573
                      .mem_rst_i(rst_i)
574
                    );
575
 
576
 
577
  //---------------------------------------------------
578
  // soc_mem_bank_1
579
  soc_mem_bank_1
580
    i_soc_mem_bank_1(
581
                      .mem_data_i(s1_data_o),
582
                      .mem_data_o(s1_data_i),
583
                      .mem_addr_i(s1_addr_o),
584
                      .mem_sel_i(s1_sel_o),
585
                      .mem_we_i(s1_we_o),
586
                      .mem_cyc_i(s1_cyc_o),
587
                      .mem_stb_i(s1_stb_o),
588
                      .mem_ack_o(s1_ack_i),
589
                      .mem_err_o(s1_err_i),
590
                      .mem_rty_o(s1_rty_i),
591
 
592
                      .mem_clk_i(clk_i),
593
                      .mem_rst_i(rst_i)
594
                    );
595
 
596
  //---------------------------------------------------
597
  // soc_mem_bank_2
598
  soc_mem_bank_2
599
    i_soc_mem_bank_2(
600
                      .mem_data_i(s2_data_o),
601
                      .mem_data_o(s2_data_i),
602
                      .mem_addr_i(s2_addr_o),
603
                      .mem_sel_i(s2_sel_o),
604
                      .mem_we_i(s2_we_o),
605
                      .mem_cyc_i(s2_cyc_o),
606
                      .mem_stb_i(s2_stb_o),
607
                      .mem_ack_o(s2_ack_i),
608
                      .mem_err_o(s2_err_i),
609
                      .mem_rty_o(s2_rty_i),
610
 
611
                      .fl_dq(fl_dq),
612
                      .fl_addr(fl_addr),
613
                      .fl_we_n(fl_we_n),
614
                      .fl_rst_n(fl_rst_n),
615
                      .fl_oe_n(fl_oe_n),
616
                      .fl_ce_n(fl_ce_n),
617
 
618
                      .mem_clk_i(clk_i),
619
                      .mem_rst_i(rst_i)
620
                    );
621
 
622
  //---------------------------------------------------
623
  // soc_mem_bank_3
624
  soc_mem_bank_3
625
    i_soc_mem_bank_3(
626
                      .mem_data_i(s3_data_o),
627
                      .mem_data_o(s3_data_i),
628
                      .mem_addr_i(s3_addr_o),
629
                      .mem_sel_i(s3_sel_o),
630
                      .mem_we_i(s3_we_o),
631
                      .mem_cyc_i(s3_cyc_o),
632
                      .mem_stb_i(s3_stb_o),
633
                      .mem_ack_o(s3_ack_i),
634
                      .mem_err_o(s3_err_i),
635
                      .mem_rty_o(s3_rty_i),
636
 
637
                      .sram_dq(sram_dq),
638
                      .sram_addr(sram_addr),
639
                      .sram_ub_n(sram_ub_n),
640
                      .sram_lb_n(sram_lb_n),
641
                      .sram_we_n(sram_we_n),
642
                      .sram_ce_n(sram_ce_n),
643
                      .sram_oe_n(sram_oe_n),
644
 
645
                      .mem_clk_i(clk_i),
646
                      .mem_rst_i(rst_i)
647
                    );
648
 
649
  //---------------------------------------------------
650
  // soc_system
651
  soc_system
652
    i_soc_system(
653
                  .sys_data_i(s4_data_o),
654
                  .sys_data_o(s4_data_i),
655
                  .sys_addr_i(s4_addr_o),
656
                  .sys_sel_i(s4_sel_o),
657
                  .sys_we_i(s4_we_o),
658
                  .sys_cyc_i(s4_cyc_o),
659
                  .sys_stb_i(s4_stb_o),
660
                  .sys_ack_o(s4_ack_i),
661
                  .sys_err_o(s4_err_i),
662
                  .sys_rty_o(s4_rty_i),
663
 
664
                  .boot_strap(boot_strap),
665
                  .boot_select(boot_select),
666
                  .boot_remap(boot_remap),
667
 
668
                  .sys_clk_i(clk_i),
669
                  .sys_rst_i(rst_i)
670
                );
671
 
672
  //---------------------------------------------------
673
  // peripherals
674
  soc_peripherals
675
    i_soc_peripherals(
676
                        .peri_data_i(s5_data_o),
677
                        .peri_data_o(s5_data_i),
678
                        .peri_addr_i(s5_addr_o),
679
                        .peri_sel_i(s5_sel_o),
680
                        .peri_we_i(s5_we_o),
681
                        .peri_cyc_i(s5_cyc_o),
682
                        .peri_stb_i(s5_stb_o),
683
                        .peri_ack_o(s5_ack_i),
684
                        .peri_err_o(s5_err_i),
685
                        .peri_rty_o(s5_rty_i),
686
 
687
                        .uart_txd_0(uart_txd_0),
688
                        .uart_rxd_0(uart_rxd_0),
689
 
690
                        .peri_clk_i(clk_i),
691
                        .peri_rst_i(rst_i)
692
                      );
693
 
694
  //---------------------------------------------------
695
  // gpio
696
  soc_gpio
697
    i_soc_gpio(
698
                  .gpio_data_i(s6_data_o),
699
                  .gpio_data_o(s6_data_i),
700
                  .gpio_addr_i(s6_addr_o),
701
                  .gpio_sel_i(s6_sel_o),
702
                  .gpio_we_i(s6_we_o),
703
                  .gpio_cyc_i(s6_cyc_o),
704
                  .gpio_stb_i(s6_stb_o),
705
                  .gpio_ack_o(s6_ack_i),
706
                  .gpio_err_o(s6_err_i),
707
                  .gpio_rty_o(s6_rty_i),
708
 
709
                  .gpio_a_aux_i(gpio_a_aux_i),
710
                  .gpio_a_ext_pad_i(gpio_a_ext_pad_i),
711
                  .gpio_a_ext_pad_o(gpio_a_ext_pad_o),
712
                  .gpio_a_ext_padoe_o(gpio_a_ext_padoe_o),
713
                  .gpio_a_inta_o(),
714
 
715
                  .gpio_b_aux_i(gpio_b_aux_i),
716
                  .gpio_b_ext_pad_i(gpio_b_ext_pad_i),
717
                  .gpio_b_ext_pad_o(gpio_b_ext_pad_o),
718
                  .gpio_b_ext_padoe_o(gpio_b_ext_padoe_o),
719
                  .gpio_b_inta_o(),
720
 
721
                  .gpio_c_aux_i(gpio_c_aux_i),
722
                  .gpio_c_ext_pad_i(gpio_c_ext_pad_i),
723
                  .gpio_c_ext_pad_o(gpio_c_ext_pad_o),
724
                  .gpio_c_ext_padoe_o(gpio_c_ext_padoe_o),
725
                  .gpio_c_inta_o(),
726
 
727
                  .gpio_d_aux_i(gpio_d_aux_i),
728
                  .gpio_d_ext_pad_i(gpio_d_ext_pad_i),
729
                  .gpio_d_ext_pad_o(gpio_d_ext_pad_o),
730
                  .gpio_d_ext_padoe_o(gpio_d_ext_padoe_o),
731
                  .gpio_d_inta_o(),
732
 
733
                  .gpio_e_aux_i(gpio_e_aux_i),
734
                  .gpio_e_ext_pad_i(gpio_e_ext_pad_i),
735
                  .gpio_e_ext_pad_o(gpio_e_ext_pad_o),
736
                  .gpio_e_ext_padoe_o(gpio_e_ext_padoe_o),
737
                  .gpio_e_inta_o(),
738
 
739
                  .gpio_f_aux_i(gpio_f_aux_i),
740
                  .gpio_f_ext_pad_i(gpio_f_ext_pad_i),
741
                  .gpio_f_ext_pad_o(gpio_f_ext_pad_o),
742
                  .gpio_f_ext_padoe_o(gpio_f_ext_padoe_o),
743
                  .gpio_f_inta_o(),
744
 
745
                  .gpio_g_aux_i(gpio_g_aux_i),
746
                  .gpio_g_ext_pad_i(gpio_g_ext_pad_i),
747
                  .gpio_g_ext_pad_o(gpio_g_ext_pad_o),
748
                  .gpio_g_ext_padoe_o(gpio_g_ext_padoe_o),
749
                  .gpio_g_inta_o(),
750
 
751
                  .gpio_clk_i(clk_i),
752
                  .gpio_rst_i(rst_i)
753
                );
754
 
755
  //---------------------------------------------------
756
  // debug_0
757
`ifdef USE_DEBUG_0
758
  assign debug_0 = {
759
                      iwb_clk_i,
760
                      iwb_rst_i,
761
                      iwb_ack_i,
762
                      iwb_err_i,
763
                      iwb_rty_i,
764
                      iwb_cyc_o,
765
                      iwb_stb_o,
766
                      iwb_we_o,
767
                      iwb_sel_o,
768
                      iwb_cab_o,
769
                      dwb_clk_i,
770
                      dwb_rst_i,
771
                      dwb_ack_i,
772
                      dwb_err_i,
773
                      dwb_rty_i,
774
                      dwb_cyc_o,
775
                      dwb_stb_o,
776
                      dwb_we_o,
777
                      dwb_sel_o,
778
                      dwb_cab_o,
779
                      iwb_adr_o,
780
                      iwb_dat_i,
781
                      iwb_dat_o,
782
                      dwb_adr_o,
783
                      dwb_dat_i,
784
                      dwb_dat_o
785
                    };
786
`endif
787
 
788
endmodule
789
 
790
 

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