Subversion Repositories p9813_rgb_led_string_driver

--

-- Test Bench

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library work;

use work.function_pack.all;

use work.pull_pack_sim.all;

use work.sim_control_port_pack.all;

entity testbench is

--

--the testbench is a closed entity

--

end testbench;

architecture struct of testbench is

  ----------------------------------------------------------------------

  -- NOTE: Some of these constants are duplicated inside the modules under test.

  --       Synthesizable code should not contain simulation constants.

  ----------------------------------------------------------------------

  -- System Constants and Settings

  constant TEST_CLKRATE    : integer := 124990000; -- The clock rate at which the stimulus logic runs

  constant DUT_REF_CLKRATE : integer :=  50000000; -- The clock rate at which the test device runs

  constant TEST_BAUDRATE   : integer :=    921600; -- Serial Link Baud rate

  constant TEST_PARITY     : integer :=         0; -- 0=none, 1=even, 2=odd

  constant CMD_LINE_SIZE   : integer :=        80; -- Length of buffer to hold file input bytes

  constant PPSGEN_PERIOD   : time    := 1001000 * 1 us;

  ----------------------------------------------------------------------

  -- Component Declarations

  -----------------------------------

  component fpga

  port (

    -- System Clock & Reset_n

    sys_clk_ref  : in   std_logic;

    sys_rst_n_i  : in   std_logic;

    -- Standardized Board Inputs / Outputs

    switch       : in  unsigned(7 downto 0);

    led          : out unsigned(7 downto 0);

    exp_io       : inout unsigned(39 downto 1);

    -- TTL serial interface

    uart_0_tx_o  : out std_logic;

    uart_0_rx_i  : in  std_logic

  );

  end component;

  -----------------------------------------------------------------------------

  -- Internal signal declarations

    -- Common Signals

  signal sys_rst       : std_logic;

  signal sys_rst_n     : std_logic;

  signal sys_clk       : std_logic;

  signal dut_ref_clk   : std_logic := '0';

    -- Signals for uart_control_port

  signal uart_cmd      : std_logic;

  signal uart_resp     : std_logic;

    -- Signals from unit under test, so they show up in testbench

    -- Board Inputs / Outputs

  signal switch        : unsigned(7 downto 0);

  signal led           : unsigned(7 downto 0);

  signal exp_io        : unsigned(39 downto 1);

begin

  ------------------------------------------------------------------------

  -- Set up low asserted reset

  sys_rst_n <= not sys_rst;

  ------------------------------------------------------------------------

  -- Set up independent DUT reference clock

  dut_ref_clk_proc : process

    variable PS_PER_SECOND : real := 1.0E+12;

    variable half_period : time := integer(PS_PER_SECOND/(2.0*real(DUT_REF_CLKRATE))) * 1 ps;

  begin

     --wait for 1/2 of the clock period;

     wait for half_period;

     dut_ref_clk <= not dut_ref_clk;

  end process;

  ------------------------------------------------------------------------

  -- Instantiate a UART Control Port

  ucp0 : sim_uart_control_port

  generic map(

    INPUT_FILE     => ".\rs232_test_in.txt",

    OUTPUT_FILE    => ".\rs232_test_out.txt",

    POR_DURATION   =>        500 ns,  -- Duration of internal reset signal activity

    POR_ASSERT_LOW =>         false,  -- Determine polarity of reset signal

    CLKRATE        =>  TEST_CLKRATE,  -- Control Port clock rate default.

    UART_BAUDRATE  => TEST_BAUDRATE,  -- UART Speed, in bits per second.

    UART_PARITY    =>   TEST_PARITY,

    LINE_LENGTH    => CMD_LINE_SIZE   -- Length of buffer to hold file input bytes

  )

  port map (

    test_rst => sys_rst,

    test_clk => sys_clk,

    uart_tx  => uart_cmd,

    uart_rx  => uart_resp

  );

  ------------------------------------------------------------------------

  -- Instantiate Unit Under Test

  dut_0 : fpga

  port map(

    -- System Clock & Reset_n

    sys_clk_ref  => dut_ref_clk,

    sys_rst_n_i  => sys_rst_n,

    -- Standardized Board Inputs / Outputs

    switch       => switch,

    led          => led,

    exp_io       => exp_io,

    -- TTL serial interface

    uart_0_tx_o  => uart_resp,

    uart_0_rx_i  => uart_cmd

  );

-- Assign pins

  -- Feed the randomized PN sequence data into the unit under test.

  exp_io(32) <= exp_io(1);

-- Apply a value to the inputs

switch <= "11111101"; -- low is 'on'

-- Create pullups as needed

  exp_io_loop: for i in exp_io'length downto 1 generate

    i_pu : pullup1

      port map (

          pin => exp_io(i)

      );

  end generate exp_io_loop;

  pu1: pullup1 PORT MAP (pin => uart_cmd);

  pu2: pullup1 PORT MAP (pin => uart_resp);

--    eight_loop: for i in 7 downto 0 GENERATE

--      i_pu8 : pullup1

--        PORT MAP (

--            pin => PC(i)            --Pullups on the Mod IRQ lines

--          );

--    END GENERATE eight_loop;

end struct;