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[/] [pc_fpga_com/] [trunk/] [PC_FPGA_PLATFPORM/] [HARDWARE/] [PC_COM.vhd] - Blame information for rev 2

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-----------------------------------------------------------------------------------------
-- Copyright (C) 2010 Nikolaos Ch. Alachiotis                                                                                                           --
--                                                                                                                                                                                                                                      --
-- Engineer:                            Nikolaos Ch. Alachiotis                                                                                                         --
--                                                                                                                                                                                                                                      --
-- Contact:                                     n.alachiotis@gmail.com                                                                                                          --
--                                                                                                                                                                                                                              --
-- Create Date:                 04/03/2011                                                                                                                                              --
-- Project Name:        PC-FPGA Communication Platform                                 --
-- Module Name:                 PC_COM                                                                                                                                                  --
-- Target Devices:              Virtex 5 FPGAs                                                                                                                          --
--                                                                                     --        
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PC_COM is
    Port (
                          rst : in  STD_LOGIC; -- active high
           clk : in  STD_LOGIC; -- emac clk                       
 
                          UDP_IP_Core_locked : out  STD_LOGIC;
 
                          -- FPGA to PC
                          FPGA2PC_transmission_enable : in  STD_LOGIC;
                          FPGA2PC_transmission_type : in  STD_LOGIC_VECTOR(2 downto 0);
                          FPGA2PC_transmission_length : in  STD_LOGIC_VECTOR(15 downto 0);
 
           FPGA2PC_transmission_read_address : out  STD_LOGIC_VECTOR(31 downto 0);
                          FPGA2PC_transmission_bus8  : in STD_LOGIC_VECTOR (7 downto 0);
                          FPGA2PC_transmission_bus16 : in STD_LOGIC_VECTOR (15 downto 0);
                          FPGA2PC_transmission_bus32 : in STD_LOGIC_VECTOR (31 downto 0);
                          FPGA2PC_transmission_bus64 : in STD_LOGIC_VECTOR (63 downto 0);
                          FPGA2PC_transmission_over : out STD_LOGIC;
 
                          -- PC to FPGA
                          PC2FPGA_tranmission_start_of_data : out  STD_LOGIC;
                          PC2FPGA_tranmission_end_of_data : out  STD_LOGIC;
                          PC2FPGA_tranmission_valid_data : out  STD_LOGIC;
                          PC2FPGA_transmission_type  : out  STD_LOGIC_VECTOR(2 downto 0);
                          PC2FPGA_transmission_bus8  : out  STD_LOGIC_VECTOR(7 downto 0);
                          PC2FPGA_transmission_bus16 : out  STD_LOGIC_VECTOR(15 downto 0);
                          PC2FPGA_transmission_bus32 : out  STD_LOGIC_VECTOR(31 downto 0);
                          PC2FPGA_transmission_bus64 : out  STD_LOGIC_VECTOR(63 downto 0);
 
                          -- TX INTERFACE
           tx_sof : out  STD_LOGIC;
           tx_eof : out  STD_LOGIC;
           tx_src_rdy : out  STD_LOGIC;
                          tx_dst_rdy : in  STD_LOGIC;
                          tx_data : out  STD_LOGIC_VECTOR(7 downto 0);
 
                          -- RX INTERFACE
                          rx_sof : in  STD_LOGIC;
                          rx_eof : in  STD_LOGIC;
                          rx_src_rdy : in  STD_LOGIC;
                          rx_dst_rdy : out  STD_LOGIC;
                          rx_data : in  STD_LOGIC_VECTOR(7 downto 0)
 
                         );
end PC_COM;
 
architecture Behavioral of PC_COM is
 
component UDP_IP_Core is
    Port ( rst : in  STD_LOGIC;
           clk_125MHz : in  STD_LOGIC;
 
                          -- Transmit signals
                          transmit_start_enable : in  STD_LOGIC;
           transmit_data_length : in  STD_LOGIC_VECTOR (15 downto 0);
                          usr_data_trans_phase_on : out STD_LOGIC;
           transmit_data_input_bus : in  STD_LOGIC_VECTOR (7 downto 0);
           start_of_frame_O : out  STD_LOGIC;
                          end_of_frame_O : out  STD_LOGIC;
                          source_ready : out STD_LOGIC;
                          transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
 
                          --Receive Signals
                          rx_sof : in  STD_LOGIC;
           rx_eof : in  STD_LOGIC;
           input_bus : in  STD_LOGIC_VECTOR(7 downto 0);
           valid_out_usr_data : out  STD_LOGIC;
           usr_data_output_bus : out  STD_LOGIC_VECTOR (7 downto 0);
 
 
                          locked : out  STD_LOGIC
                          );
end component;
 
component PC2FPGA is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
 
           locked : in  STD_LOGIC;
 
                          rx_sof : in  STD_LOGIC;
                          rx_eof : in  STD_LOGIC;
                          vld_i : in  STD_LOGIC;
                          val_i : in  STD_LOGIC_VECTOR(7 downto 0);
 
                          sod_o : out  STD_LOGIC;
                          eod_o : out  STD_LOGIC;
 
                          type_o : out  STD_LOGIC_VECTOR(2 downto 0); -- 000: no transmission
                                                                                                                                                 -- 001: receiving characters
                                                                                                                                                 -- 010: receiving short integers
                                                                                                                                                 -- 011: receiving integers
                                                                                                                                                 -- 100: receiving floats
                                                                                                                                                 -- 101: receiving doubles
 
                          vld_o : out  STD_LOGIC;
 
                          val_o_char : out  STD_LOGIC_VECTOR(7 downto 0);
                          val_o_short : out  STD_LOGIC_VECTOR(15 downto 0);
                          val_o_int_float : out  STD_LOGIC_VECTOR(31 downto 0);
                          val_o_long_double : out  STD_LOGIC_VECTOR(63 downto 0)
 
                          );
end component;
 
component FPGA2PC is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
 
           locked : in  STD_LOGIC;
 
           trans_en : in  STD_LOGIC;
           d_type : in  STD_LOGIC_VECTOR (2 downto 0);
           d_len : in  STD_LOGIC_VECTOR (15 downto 0);
 
                          rd_addr : out  STD_LOGIC_VECTOR (31 downto 0);
 
           data_in_8 : in  STD_LOGIC_VECTOR (7 downto 0);   -- type 001
                          data_in_16 : in  STD_LOGIC_VECTOR (15 downto 0); -- type 010
           data_in_32 : in  STD_LOGIC_VECTOR (31 downto 0); -- type 011 or 100
           data_in_64 : in  STD_LOGIC_VECTOR (63 downto 0); -- type 101
 
                          start_trans : out  STD_LOGIC;
                          trans_length : out  STD_LOGIC_VECTOR(15 downto 0);
                          usr_data_phase_on : in  STD_LOGIC;
                          usr_data_to_trasmit : out  STD_LOGIC_VECTOR(7 downto 0);
 
           tx_eof_in: in STD_LOGIC;
                          trans_ov : out  STD_LOGIC);
end component;
 
component MATCH_CMD is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           sof : in  STD_LOGIC;
           vld_i : in  STD_LOGIC;
           val_i : in  STD_LOGIC_VECTOR (7 downto 0);
                          cmd_to_match : in  STD_LOGIC_VECTOR(7 downto 0);
           cmd_match : out  STD_LOGIC);
end component;
 
signal locked: std_logic;
signal vld_in_usr_data: std_logic;
signal val_in_usr_data,val_in_usr_data_reg: std_logic_vector(7 downto 0);
signal loc_st_trans: std_logic;
signal loc_le_trans: std_logic_vector(15 downto 0);
signal usr_out_type_t: std_logic_vector(1 downto 0);
signal usr_o_data_en: std_logic;
signal usr_o_data, usr_o_data_reg1: std_logic_Vector(7 downto 0);
signal test_en: std_logic;
signal tx_eof_t, sel_op: std_logic;
signal selected_data, sel_def, sel_stat, status_next: std_logic_vector(7 downto 0);
signal selected_length: std_logic_Vector(15 downto 0);
signal selected_start,status_enable_r, status_enable_t: std_logic;
signal start_transmission, rreq_en, loc_trans_en, rreq_en_reg: std_logic;
signal transmission_data, cmd_to_match_rreq, val_in_usr_data_reg_2: std_logic_Vector(7 downto 0);
signal transmission_length, tmplength: std_logic_vector(15 downto 0);
signal loc_trans_type: std_logic_Vector(2 downto 0);
signal loc_trans_length: std_logic_vector(15 downto 0);
 
begin
 
cmd_to_match_rreq(7 downto 3) <= val_in_usr_data(7 downto 3);
cmd_to_match_rreq(2 downto 0) <= "000";
 
MATCH_RREQ_CODE: MATCH_CMD Port Map
( rst => rst,
  clk => clk,
  sof => rx_sof,
  vld_i => vld_in_usr_data,
  val_i => cmd_to_match_rreq,
  cmd_to_match => "01111000",
  cmd_match => rreq_en
);
 
process(clk)
begin
if clk'event and clk='1' then
        val_in_usr_data_reg <= val_in_usr_data;
        val_in_usr_data_reg_2 <= val_in_usr_data_reg;
        rreq_en_reg <= rreq_en;
end if;
end process;
 
tmplength(15 downto 8) <= val_in_usr_data_reg;
tmplength(7 downto 0) <= val_in_usr_data;
 
loc_trans_en <= FPGA2PC_transmission_enable or rreq_en_reg;
loc_trans_length <= FPGA2PC_transmission_length or tmplength;
loc_trans_type <= FPGA2PC_transmission_type or val_in_usr_data_reg_2(2 downto 0);
 
 
UDP_IP_CORE_INST: UDP_IP_Core Port Map
(
        rst => rst,
        clk_125MHz => clk,
        transmit_start_enable => start_transmission,
        transmit_data_length => transmission_length,
        usr_data_trans_phase_on => usr_o_data_en,
        transmit_data_input_bus => transmission_data,
        start_of_frame_O => tx_sof,
        end_of_frame_O => tx_eof_t,
        source_ready => tx_src_rdy,
        transmit_data_output_bus =>tx_data,
        rx_sof => rx_sof,
        rx_eof => rx_eof,
        input_bus => rx_data,
        valid_out_usr_data => vld_in_usr_data,
        usr_data_output_bus => val_in_usr_data,
        locked => locked
);
 
tx_eof <=tx_eof_t;
 
UDP_IP_Core_locked <= locked;
 
rx_dst_rdy  <= tx_dst_rdy;
 
PC2FPGA_C: PC2FPGA Port Map
(
        rst => rst,
        clk => clk,
        locked => locked,
        rx_sof => rx_sof,
        rx_eof => rx_eof,
        vld_i => vld_in_usr_data,
        val_i => val_in_usr_data,
        sod_o => PC2FPGA_tranmission_start_of_data,
        eod_o => PC2FPGA_tranmission_end_of_data,
        type_o => PC2FPGA_transmission_type,
        vld_o => PC2FPGA_tranmission_valid_data,
        val_o_char => PC2FPGA_transmission_bus8,
        val_o_short => PC2FPGA_transmission_bus16,
        val_o_int_float => PC2FPGA_transmission_bus32,
        val_o_long_double => PC2FPGA_transmission_bus64
);
 
FPGA2PC_C: FPGA2PC Port Map
(
        rst => rst,
   clk => clk,
        locked => locked,
        trans_en => loc_trans_en,
        d_type => loc_trans_type,
        d_len => loc_trans_length,
        rd_addr => FPGA2PC_transmission_read_address,
        data_in_8 => FPGA2PC_transmission_bus8,
        data_in_16 => FPGA2PC_transmission_bus16,
        data_in_32 => FPGA2PC_transmission_bus32,
   data_in_64 => FPGA2PC_transmission_bus64,
        start_trans => start_transmission,
        trans_length => transmission_length,
        usr_data_phase_on => usr_o_data_en,
        usr_data_to_trasmit => transmission_data,
        tx_eof_in => tx_eof_t,
   trans_ov => FPGA2PC_transmission_over
);
 
end Behavioral;
 

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Subversion Repositories pc_fpga_com

[/] [pc_fpga_com/] [trunk/] [PC_FPGA_PLATFPORM/] [HARDWARE/] [PC_COM.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	NikosAl	`-----------------------------------------------------------------------------------------`
2			`-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --`
3			`-- --`
4			`-- Engineer: Nikolaos Ch. Alachiotis --`
5			`-- --`
6			`-- Contact: n.alachiotis@gmail.com --`
7			`-- --`
8			`-- Create Date: 04/03/2011 --`
9			`-- Project Name: PC-FPGA Communication Platform --`
10			`-- Module Name: PC_COM --`
11			`-- Target Devices: Virtex 5 FPGAs --`
12			`-- --`
13			`-----------------------------------------------------------------------------------------`
14			`library IEEE;`
15			`use IEEE.STD_LOGIC_1164.ALL;`
16			`use IEEE.STD_LOGIC_ARITH.ALL;`
17			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
18
19			`---- Uncomment the following library declaration if instantiating`
20			`---- any Xilinx primitives in this code.`
21			`--library UNISIM;`
22			`--use UNISIM.VComponents.all;`
23
24			`entity PC_COM is`
25			`Port (`
26			`rst : in STD_LOGIC; -- active high`
27			`clk : in STD_LOGIC; -- emac clk`
28
29			`UDP_IP_Core_locked : out STD_LOGIC;`
30
31			`-- FPGA to PC`
32			`FPGA2PC_transmission_enable : in STD_LOGIC;`
33			`FPGA2PC_transmission_type : in STD_LOGIC_VECTOR(2 downto 0);`
34			`FPGA2PC_transmission_length : in STD_LOGIC_VECTOR(15 downto 0);`
35
36			`FPGA2PC_transmission_read_address : out STD_LOGIC_VECTOR(31 downto 0);`
37			`FPGA2PC_transmission_bus8 : in STD_LOGIC_VECTOR (7 downto 0);`
38			`FPGA2PC_transmission_bus16 : in STD_LOGIC_VECTOR (15 downto 0);`
39			`FPGA2PC_transmission_bus32 : in STD_LOGIC_VECTOR (31 downto 0);`
40			`FPGA2PC_transmission_bus64 : in STD_LOGIC_VECTOR (63 downto 0);`
41			`FPGA2PC_transmission_over : out STD_LOGIC;`
42
43			`-- PC to FPGA`
44			`PC2FPGA_tranmission_start_of_data : out STD_LOGIC;`
45			`PC2FPGA_tranmission_end_of_data : out STD_LOGIC;`
46			`PC2FPGA_tranmission_valid_data : out STD_LOGIC;`
47			`PC2FPGA_transmission_type : out STD_LOGIC_VECTOR(2 downto 0);`
48			`PC2FPGA_transmission_bus8 : out STD_LOGIC_VECTOR(7 downto 0);`
49			`PC2FPGA_transmission_bus16 : out STD_LOGIC_VECTOR(15 downto 0);`
50			`PC2FPGA_transmission_bus32 : out STD_LOGIC_VECTOR(31 downto 0);`
51			`PC2FPGA_transmission_bus64 : out STD_LOGIC_VECTOR(63 downto 0);`
52
53			`-- TX INTERFACE`
54			`tx_sof : out STD_LOGIC;`
55			`tx_eof : out STD_LOGIC;`
56			`tx_src_rdy : out STD_LOGIC;`
57			`tx_dst_rdy : in STD_LOGIC;`
58			`tx_data : out STD_LOGIC_VECTOR(7 downto 0);`
59
60			`-- RX INTERFACE`
61			`rx_sof : in STD_LOGIC;`
62			`rx_eof : in STD_LOGIC;`
63			`rx_src_rdy : in STD_LOGIC;`
64			`rx_dst_rdy : out STD_LOGIC;`
65			`rx_data : in STD_LOGIC_VECTOR(7 downto 0)`
66
67			`);`
68			`end PC_COM;`
69
70			`architecture Behavioral of PC_COM is`
71
72			`component UDP_IP_Core is`
73			`Port ( rst : in STD_LOGIC;`
74			`clk_125MHz : in STD_LOGIC;`
75
76			`-- Transmit signals`
77			`transmit_start_enable : in STD_LOGIC;`
78			`transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);`
79			`usr_data_trans_phase_on : out STD_LOGIC;`
80			`transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);`
81			`start_of_frame_O : out STD_LOGIC;`
82			`end_of_frame_O : out STD_LOGIC;`
83			`source_ready : out STD_LOGIC;`
84			`transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);`
85
86			`--Receive Signals`
87			`rx_sof : in STD_LOGIC;`
88			`rx_eof : in STD_LOGIC;`
89			`input_bus : in STD_LOGIC_VECTOR(7 downto 0);`
90			`valid_out_usr_data : out STD_LOGIC;`
91			`usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);`
92
93
94			`locked : out STD_LOGIC`
95			`);`
96			`end component;`
97
98			`component PC2FPGA is`
99			`Port ( rst : in STD_LOGIC;`
100			`clk : in STD_LOGIC;`
101
102			`locked : in STD_LOGIC;`
103
104			`rx_sof : in STD_LOGIC;`
105			`rx_eof : in STD_LOGIC;`
106			`vld_i : in STD_LOGIC;`
107			`val_i : in STD_LOGIC_VECTOR(7 downto 0);`
108
109			`sod_o : out STD_LOGIC;`
110			`eod_o : out STD_LOGIC;`
111
112			`type_o : out STD_LOGIC_VECTOR(2 downto 0); -- 000: no transmission`
113			`-- 001: receiving characters`
114			`-- 010: receiving short integers`
115			`-- 011: receiving integers`
116			`-- 100: receiving floats`
117			`-- 101: receiving doubles`
118
119			`vld_o : out STD_LOGIC;`
120
121			`val_o_char : out STD_LOGIC_VECTOR(7 downto 0);`
122			`val_o_short : out STD_LOGIC_VECTOR(15 downto 0);`
123			`val_o_int_float : out STD_LOGIC_VECTOR(31 downto 0);`
124			`val_o_long_double : out STD_LOGIC_VECTOR(63 downto 0)`
125
126			`);`
127			`end component;`
128
129			`component FPGA2PC is`
130			`Port ( rst : in STD_LOGIC;`
131			`clk : in STD_LOGIC;`
132
133			`locked : in STD_LOGIC;`
134
135			`trans_en : in STD_LOGIC;`
136			`d_type : in STD_LOGIC_VECTOR (2 downto 0);`
137			`d_len : in STD_LOGIC_VECTOR (15 downto 0);`
138
139			`rd_addr : out STD_LOGIC_VECTOR (31 downto 0);`
140
141			`data_in_8 : in STD_LOGIC_VECTOR (7 downto 0); -- type 001`
142			`data_in_16 : in STD_LOGIC_VECTOR (15 downto 0); -- type 010`
143			`data_in_32 : in STD_LOGIC_VECTOR (31 downto 0); -- type 011 or 100`
144			`data_in_64 : in STD_LOGIC_VECTOR (63 downto 0); -- type 101`
145
146			`start_trans : out STD_LOGIC;`
147			`trans_length : out STD_LOGIC_VECTOR(15 downto 0);`
148			`usr_data_phase_on : in STD_LOGIC;`
149			`usr_data_to_trasmit : out STD_LOGIC_VECTOR(7 downto 0);`
150
151			`tx_eof_in: in STD_LOGIC;`
152			`trans_ov : out STD_LOGIC);`
153			`end component;`
154
155			`component MATCH_CMD is`
156			`Port ( rst : in STD_LOGIC;`
157			`clk : in STD_LOGIC;`
158			`sof : in STD_LOGIC;`
159			`vld_i : in STD_LOGIC;`
160			`val_i : in STD_LOGIC_VECTOR (7 downto 0);`
161			`cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0);`
162			`cmd_match : out STD_LOGIC);`
163			`end component;`
164
165			`signal locked: std_logic;`
166			`signal vld_in_usr_data: std_logic;`
167			`signal val_in_usr_data,val_in_usr_data_reg: std_logic_vector(7 downto 0);`
168			`signal loc_st_trans: std_logic;`
169			`signal loc_le_trans: std_logic_vector(15 downto 0);`
170			`signal usr_out_type_t: std_logic_vector(1 downto 0);`
171			`signal usr_o_data_en: std_logic;`
172			`signal usr_o_data, usr_o_data_reg1: std_logic_Vector(7 downto 0);`
173			`signal test_en: std_logic;`
174			`signal tx_eof_t, sel_op: std_logic;`
175			`signal selected_data, sel_def, sel_stat, status_next: std_logic_vector(7 downto 0);`
176			`signal selected_length: std_logic_Vector(15 downto 0);`
177			`signal selected_start,status_enable_r, status_enable_t: std_logic;`
178			`signal start_transmission, rreq_en, loc_trans_en, rreq_en_reg: std_logic;`
179			`signal transmission_data, cmd_to_match_rreq, val_in_usr_data_reg_2: std_logic_Vector(7 downto 0);`
180			`signal transmission_length, tmplength: std_logic_vector(15 downto 0);`
181			`signal loc_trans_type: std_logic_Vector(2 downto 0);`
182			`signal loc_trans_length: std_logic_vector(15 downto 0);`
183
184			`begin`
185
186			`cmd_to_match_rreq(7 downto 3) <= val_in_usr_data(7 downto 3);`
187			`cmd_to_match_rreq(2 downto 0) <= "000";`
188
189			`MATCH_RREQ_CODE: MATCH_CMD Port Map`
190			`( rst => rst,`
191			`clk => clk,`
192			`sof => rx_sof,`
193			`vld_i => vld_in_usr_data,`
194			`val_i => cmd_to_match_rreq,`
195			`cmd_to_match => "01111000",`
196			`cmd_match => rreq_en`
197			`);`
198
199			`process(clk)`
200			`begin`
201			`if clk'event and clk='1' then`
202			`val_in_usr_data_reg <= val_in_usr_data;`
203			`val_in_usr_data_reg_2 <= val_in_usr_data_reg;`
204			`rreq_en_reg <= rreq_en;`
205			`end if;`
206			`end process;`
207
208			`tmplength(15 downto 8) <= val_in_usr_data_reg;`
209			`tmplength(7 downto 0) <= val_in_usr_data;`
210
211			`loc_trans_en <= FPGA2PC_transmission_enable or rreq_en_reg;`
212			`loc_trans_length <= FPGA2PC_transmission_length or tmplength;`
213			`loc_trans_type <= FPGA2PC_transmission_type or val_in_usr_data_reg_2(2 downto 0);`
214
215
216			`UDP_IP_CORE_INST: UDP_IP_Core Port Map`
217			`(`
218			`rst => rst,`
219			`clk_125MHz => clk,`
220			`transmit_start_enable => start_transmission,`
221			`transmit_data_length => transmission_length,`
222			`usr_data_trans_phase_on => usr_o_data_en,`
223			`transmit_data_input_bus => transmission_data,`
224			`start_of_frame_O => tx_sof,`
225			`end_of_frame_O => tx_eof_t,`
226			`source_ready => tx_src_rdy,`
227			`transmit_data_output_bus =>tx_data,`
228			`rx_sof => rx_sof,`
229			`rx_eof => rx_eof,`
230			`input_bus => rx_data,`
231			`valid_out_usr_data => vld_in_usr_data,`
232			`usr_data_output_bus => val_in_usr_data,`
233			`locked => locked`
234			`);`
235
236			`tx_eof <=tx_eof_t;`
237
238			`UDP_IP_Core_locked <= locked;`
239
240			`rx_dst_rdy <= tx_dst_rdy;`
241
242			`PC2FPGA_C: PC2FPGA Port Map`
243			`(`
244			`rst => rst,`
245			`clk => clk,`
246			`locked => locked,`
247			`rx_sof => rx_sof,`
248			`rx_eof => rx_eof,`
249			`vld_i => vld_in_usr_data,`
250			`val_i => val_in_usr_data,`
251			`sod_o => PC2FPGA_tranmission_start_of_data,`
252			`eod_o => PC2FPGA_tranmission_end_of_data,`
253			`type_o => PC2FPGA_transmission_type,`
254			`vld_o => PC2FPGA_tranmission_valid_data,`
255			`val_o_char => PC2FPGA_transmission_bus8,`
256			`val_o_short => PC2FPGA_transmission_bus16,`
257			`val_o_int_float => PC2FPGA_transmission_bus32,`
258			`val_o_long_double => PC2FPGA_transmission_bus64`
259			`);`
260
261			`FPGA2PC_C: FPGA2PC Port Map`
262			`(`
263			`rst => rst,`
264			`clk => clk,`
265			`locked => locked,`
266			`trans_en => loc_trans_en,`
267			`d_type => loc_trans_type,`
268			`d_len => loc_trans_length,`
269			`rd_addr => FPGA2PC_transmission_read_address,`
270			`data_in_8 => FPGA2PC_transmission_bus8,`
271			`data_in_16 => FPGA2PC_transmission_bus16,`
272			`data_in_32 => FPGA2PC_transmission_bus32,`
273			`data_in_64 => FPGA2PC_transmission_bus64,`
274			`start_trans => start_transmission,`
275			`trans_length => transmission_length,`
276			`usr_data_phase_on => usr_o_data_en,`
277			`usr_data_to_trasmit => transmission_data,`
278			`tx_eof_in => tx_eof_t,`
279			`trans_ov => FPGA2PC_transmission_over`
280			`);`
281
282			`end Behavioral;`
283