| 1 |
2 |
NikosAl |
=================================================================================
|
| 2 |
|
|
PC-FPGA COMMUNICATION PLATFORM and VERSATILE UDP/IP CORE IMPLEMENTATION FOR FPGAs
|
| 3 |
|
|
=================================================================================
|
| 4 |
|
|
|
| 5 |
|
|
Release date: March 21th, 2011
|
| 6 |
|
|
|
| 7 |
|
|
|
| 8 |
|
|
Description
|
| 9 |
|
|
-----------
|
| 10 |
|
|
|
| 11 |
|
|
This package provides an open-source VHDL implementation of a UDP/IP core architecture
|
| 12 |
|
|
and a PC-FPGA interface for transmission of basic C types (chars, 16/32/64-bit integers, floats and doubles).
|
| 13 |
|
|
|
| 14 |
|
|
|
| 15 |
|
|
Package Structure
|
| 16 |
|
|
-----------------
|
| 17 |
|
|
|
| 18 |
|
|
This package contains the following files and folder:
|
| 19 |
|
|
|
| 20 |
|
|
-README : This file
|
| 21 |
|
|
|
| 22 |
|
|
-UDP_IP_CORE_FLEX_Spartan3 : This folder contains VHDL, XCO and NGC files for Spartan3 devices.
|
| 23 |
|
|
|
| 24 |
|
|
-UDP_IP_CORE_FLEX_Virtex5 : This folder contains VHDL, XCO and NGC files for Virtex5 devices.
|
| 25 |
|
|
|
| 26 |
|
|
-PC_FPGA_PLATFPORM : This folder contains VHDL, XCO and NGC files for Virtex5 devices as well as C/C++ files.
|
| 27 |
|
|
|
| 28 |
|
|
-PAPER : This folder contains a paper that describes in detail the design and implementation of the core and the platform.
|
| 29 |
|
|
|
| 30 |
|
|
|
| 31 |
|
|
|
| 32 |
|
|
Verification Details
|
| 33 |
|
|
--------------------
|
| 34 |
|
|
|
| 35 |
|
|
The development board HTG-V5-PCIE by HiTech Global populated with a V5SX95T-1 FPGA was used to verify the correct behavior of the platform and the core.
|
| 36 |
|
|
|
| 37 |
|
|
|
| 38 |
|
|
Citation
|
| 39 |
|
|
--------
|
| 40 |
|
|
|
| 41 |
|
|
By using this component in any architecture design and associated publication, you agree to cite it as:
|
| 42 |
|
|
"A Versatile UDP/IP based PC-FPGA Communication Platform", by Nikolaos Alachiotis, Simon A. Berger and Alexandros Stamatakis,
|
| 43 |
|
|
submitted to FPL2011.
|
| 44 |
|
|
|
| 45 |
|
|
|
| 46 |
|
|
Authors and Contact Details
|
| 47 |
|
|
---------------------------
|
| 48 |
|
|
|
| 49 |
|
|
Nikos Alachiotis n.alachiotis@gmail.com, nikolaos.alachiotis@h-its.org
|
| 50 |
|
|
Simon A. Berger simon.berger@h-its.org
|
| 51 |
|
|
Alexandros Stamatakis alexandros.stamatakis@h-its.org
|
| 52 |
|
|
|
| 53 |
|
|
|
| 54 |
|
|
Scientific Computing Group (Exelixis Lab)
|
| 55 |
|
|
Heidelberg Institute for Theoretical Studies (HITS gGmbH)
|
| 56 |
|
|
|
| 57 |
|
|
Schloss-Wolfsbrunnenweg 35
|
| 58 |
|
|
D-69118 Heidelberg
|
| 59 |
|
|
Germany
|
| 60 |
|
|
|
| 61 |
|
|
|
| 62 |
|
|
Copyright
|
| 63 |
|
|
---------
|
| 64 |
|
|
|
| 65 |
|
|
This component is free. In case you use it for any purpose, particularly
|
| 66 |
|
|
when publishing work relying on this component you must cite it as: N. Alachiotis, S.A. Berger, A. Stamatakis: "A Versatile UDP/IP based PC-FPGA Communication Platform".
|
| 67 |
|
|
|
| 68 |
|
|
You can redistribute it and/or modify
|
| 69 |
|
|
it under the terms of the GNU Lesser General Public License as published by
|
| 70 |
|
|
the Free Software Foundation; either version 2 of the License, or
|
| 71 |
|
|
(at your option) any later version.
|
| 72 |
|
|
|
| 73 |
|
|
This component is distributed in the hope that it will be useful,
|
| 74 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 75 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 76 |
|
|
GNU General Public License for more details.
|
| 77 |
|
|
|
| 78 |
|
|
|
| 79 |
|
|
|
| 80 |
|
|
Release Notes
|
| 81 |
|
|
-------------
|
| 82 |
|
|
|
| 83 |
|
|
Release date: March 21th, 2011
|
