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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Spartan3/] [dist_mem_64x8.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.39
--  \   \         Application: netgen
--  /   /         Filename: dist_mem_64x8.vhd
-- /___/   /\     Timestamp: Mon May 09 14:16:57 2011
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.vhd" 
-- Device       : 3s200pq208-4
-- Input file   : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.ngc
-- Output file  : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.vhd
-- # of Entities        : 1
-- Design Name  : dist_mem_64x8
-- Xilinx       : C:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity dist_mem_64x8 is
  port (
    clk : in STD_LOGIC := 'X';
    we : in STD_LOGIC := 'X';
    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
    d : in STD_LOGIC_VECTOR ( 7 downto 0 );
    qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
end dist_mem_64x8;
 
architecture STRUCTURE of dist_mem_64x8 is
  signal N0 : STD_LOGIC;
  signal N1 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4 : STD_LOGIC;
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2 : STD_LOGIC;
  signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal d_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qspo_4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
  a_2(5) <= a(5);
  a_2(4) <= a(4);
  a_2(3) <= a(3);
  a_2(2) <= a(2);
  a_2(1) <= a(1);
  a_2(0) <= a(0);
  d_3(7) <= d(7);
  d_3(6) <= d(6);
  d_3(5) <= d(5);
  d_3(4) <= d(4);
  d_3(3) <= d(3);
  d_3(2) <= d(2);
  d_3(1) <= d(1);
  d_3(0) <= d(0);
  qspo(7) <= qspo_4(7);
  qspo(6) <= qspo_4(6);
  qspo(5) <= qspo_4(5);
  qspo(4) <= qspo_4(4);
  qspo(3) <= qspo_4(3);
  qspo(2) <= qspo_4(2);
  qspo(1) <= qspo_4(1);
  qspo(0) <= qspo_4(0);
  VCC_0 : VCC
    port map (
      P => N1
    );
  GND_1 : GND
    port map (
      G => N0
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => a_2(5),
      I1 => we,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(0),
      Q => qspo_4(0)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(1),
      Q => qspo_4(1)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(2),
      Q => qspo_4(2)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(3),
      Q => qspo_4(3)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(4),
      Q => qspo_4(4)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(5),
      Q => qspo_4(5)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(6),
      Q => qspo_4(6)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(7),
      Q => qspo_4(7)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => a_2(5),
      I1 => we,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram1 : RAM32X1S
    generic map(
      INIT => X"00804000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(0),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram2 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(0),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram3 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(1),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram6 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(2),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram4 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(1),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram5 : RAM32X1S
    generic map(
      INIT => X"00014000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(2),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram9 : RAM32X1S
    generic map(
      INIT => X"00800000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(4),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram7 : RAM32X1S
    generic map(
      INIT => X"00001000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(3),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram8 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(3),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram12 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(5),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram10 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(4),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram11 : RAM32X1S
    generic map(
      INIT => X"00010000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(5),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram15 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(7),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram13 : RAM32X1S
    generic map(
      INIT => X"00504000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(6),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram14 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(6),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram16 : RAM32X1S
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      D => d_3(7),
      WCLK => clk,
      WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX711 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(7)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX611 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(6)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX511 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(5)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX411 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(4)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX311 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(3)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX211 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(2)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX111 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(1)
    );
  BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX11 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => a_2(5),
      I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2,
      I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4,
      O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(0)
    );
  BU2_XST_GND : GND
    port map (
      G => BU2_qdpo(0)
    );
 
end STRUCTURE;
 
-- synthesis translate_on

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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Spartan3/] [dist_mem_64x8.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	NikosAl	`--------------------------------------------------------------------------------`
2			`-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.`
3			`--------------------------------------------------------------------------------`
4			`-- ____ ____`
5			`-- / /\/ /`
6			`-- /___/ \ / Vendor: Xilinx`
7			`-- \ \ \/ Version: K.39`
8			`-- \ \ Application: netgen`
9			`-- / / Filename: dist_mem_64x8.vhd`
10			`-- /___/ /\ Timestamp: Mon May 09 14:16:57 2011`
11			`-- \ \ / \`
12			`-- \___\/\___\`
13			`--`
14			`-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.vhd"`
15			`-- Device : 3s200pq208-4`
16			`-- Input file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.ngc`
17			`-- Output file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.vhd`
18			`-- # of Entities : 1`
19			`-- Design Name : dist_mem_64x8`
20			`-- Xilinx : C:\Xilinx\10.1\ISE`
21			`--`
22			`-- Purpose:`
23			`-- This VHDL netlist is a verification model and uses simulation`
24			`-- primitives which may not represent the true implementation of the`
25			`-- device, however the netlist is functionally correct and should not`
26			`-- be modified. This file cannot be synthesized and should only be used`
27			`-- with supported simulation tools.`
28			`--`
29			`-- Reference:`
30			`-- Development System Reference Guide, Chapter 23`
31			`-- Synthesis and Simulation Design Guide, Chapter 6`
32			`--`
33			`--------------------------------------------------------------------------------`
34
35
36			`-- synthesis translate_off`
37			`library IEEE;`
38			`use IEEE.STD_LOGIC_1164.ALL;`
39			`library UNISIM;`
40			`use UNISIM.VCOMPONENTS.ALL;`
41			`use UNISIM.VPKG.ALL;`
42
43			`entity dist_mem_64x8 is`
44			`port (`
45			`clk : in STD_LOGIC := 'X';`
46			`we : in STD_LOGIC := 'X';`
47			`a : in STD_LOGIC_VECTOR ( 5 downto 0 );`
48			`d : in STD_LOGIC_VECTOR ( 7 downto 0 );`
49			`qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )`
50			`);`
51			`end dist_mem_64x8;`
52
53			`architecture STRUCTURE of dist_mem_64x8 is`
54			`signal N0 : STD_LOGIC;`
55			`signal N1 : STD_LOGIC;`
56			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50 : STD_LOGIC;`
57			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49 : STD_LOGIC;`
58			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32 : STD_LOGIC;`
59			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30 : STD_LOGIC;`
60			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28 : STD_LOGIC;`
61			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26 : STD_LOGIC;`
62			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24 : STD_LOGIC;`
63			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22 : STD_LOGIC;`
64			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20 : STD_LOGIC;`
65			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18 : STD_LOGIC;`
66			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16 : STD_LOGIC;`
67			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14 : STD_LOGIC;`
68			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12 : STD_LOGIC;`
69			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10 : STD_LOGIC;`
70			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8 : STD_LOGIC;`
71			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6 : STD_LOGIC;`
72			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4 : STD_LOGIC;`
73			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2 : STD_LOGIC;`
74			`signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );`
75			`signal d_3 : STD_LOGIC_VECTOR ( 7 downto 0 );`
76			`signal qspo_4 : STD_LOGIC_VECTOR ( 7 downto 0 );`
77			`signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 );`
78			`signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );`
79			`begin`
80			`a_2(5) <= a(5);`
81			`a_2(4) <= a(4);`
82			`a_2(3) <= a(3);`
83			`a_2(2) <= a(2);`
84			`a_2(1) <= a(1);`
85			`a_2(0) <= a(0);`
86			`d_3(7) <= d(7);`
87			`d_3(6) <= d(6);`
88			`d_3(5) <= d(5);`
89			`d_3(4) <= d(4);`
90			`d_3(3) <= d(3);`
91			`d_3(2) <= d(2);`
92			`d_3(1) <= d(1);`
93			`d_3(0) <= d(0);`
94			`qspo(7) <= qspo_4(7);`
95			`qspo(6) <= qspo_4(6);`
96			`qspo(5) <= qspo_4(5);`
97			`qspo(4) <= qspo_4(4);`
98			`qspo(3) <= qspo_4(3);`
99			`qspo(2) <= qspo_4(2);`
100			`qspo(1) <= qspo_4(1);`
101			`qspo(0) <= qspo_4(0);`
102			`VCC_0 : VCC`
103			`port map (`
104			`P => N1`
105			`);`
106			`GND_1 : GND`
107			`port map (`
108			`G => N0`
109			`);`
110			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl : LUT2`
111			`generic map(`
112			`INIT => X"4"`
113			`)`
114			`port map (`
115			`I0 => a_2(5),`
116			`I1 => we,`
117			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50`
118			`);`
119			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_0 : FD`
120			`generic map(`
121			`INIT => '0'`
122			`)`
123			`port map (`
124			`C => clk,`
125			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(0),`
126			`Q => qspo_4(0)`
127			`);`
128			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_1 : FD`
129			`generic map(`
130			`INIT => '0'`
131			`)`
132			`port map (`
133			`C => clk,`
134			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(1),`
135			`Q => qspo_4(1)`
136			`);`
137			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_2 : FD`
138			`generic map(`
139			`INIT => '0'`
140			`)`
141			`port map (`
142			`C => clk,`
143			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(2),`
144			`Q => qspo_4(2)`
145			`);`
146			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_3 : FD`
147			`generic map(`
148			`INIT => '0'`
149			`)`
150			`port map (`
151			`C => clk,`
152			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(3),`
153			`Q => qspo_4(3)`
154			`);`
155			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_4 : FD`
156			`generic map(`
157			`INIT => '0'`
158			`)`
159			`port map (`
160			`C => clk,`
161			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(4),`
162			`Q => qspo_4(4)`
163			`);`
164			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_5 : FD`
165			`generic map(`
166			`INIT => '0'`
167			`)`
168			`port map (`
169			`C => clk,`
170			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(5),`
171			`Q => qspo_4(5)`
172			`);`
173			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_6 : FD`
174			`generic map(`
175			`INIT => '0'`
176			`)`
177			`port map (`
178			`C => clk,`
179			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(6),`
180			`Q => qspo_4(6)`
181			`);`
182			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_7 : FD`
183			`generic map(`
184			`INIT => '0'`
185			`)`
186			`port map (`
187			`C => clk,`
188			`D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(7),`
189			`Q => qspo_4(7)`
190			`);`
191			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1 : LUT2`
192			`generic map(`
193			`INIT => X"8"`
194			`)`
195			`port map (`
196			`I0 => a_2(5),`
197			`I1 => we,`
198			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49`
199			`);`
200			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram1 : RAM32X1S`
201			`generic map(`
202			`INIT => X"00804000"`
203			`)`
204			`port map (`
205			`A0 => a_2(0),`
206			`A1 => a_2(1),`
207			`A2 => a_2(2),`
208			`A3 => a_2(3),`
209			`A4 => a_2(4),`
210			`D => d_3(0),`
211			`WCLK => clk,`
212			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
213			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2`
214			`);`
215			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram2 : RAM32X1S`
216			`generic map(`
217			`INIT => X"00000000"`
218			`)`
219			`port map (`
220			`A0 => a_2(0),`
221			`A1 => a_2(1),`
222			`A2 => a_2(2),`
223			`A3 => a_2(3),`
224			`A4 => a_2(4),`
225			`D => d_3(0),`
226			`WCLK => clk,`
227			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
228			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4`
229			`);`
230			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram3 : RAM32X1S`
231			`generic map(`
232			`INIT => X"00000000"`
233			`)`
234			`port map (`
235			`A0 => a_2(0),`
236			`A1 => a_2(1),`
237			`A2 => a_2(2),`
238			`A3 => a_2(3),`
239			`A4 => a_2(4),`
240			`D => d_3(1),`
241			`WCLK => clk,`
242			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
243			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6`
244			`);`
245			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram6 : RAM32X1S`
246			`generic map(`
247			`INIT => X"00000000"`
248			`)`
249			`port map (`
250			`A0 => a_2(0),`
251			`A1 => a_2(1),`
252			`A2 => a_2(2),`
253			`A3 => a_2(3),`
254			`A4 => a_2(4),`
255			`D => d_3(2),`
256			`WCLK => clk,`
257			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
258			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12`
259			`);`
260			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram4 : RAM32X1S`
261			`generic map(`
262			`INIT => X"00000000"`
263			`)`
264			`port map (`
265			`A0 => a_2(0),`
266			`A1 => a_2(1),`
267			`A2 => a_2(2),`
268			`A3 => a_2(3),`
269			`A4 => a_2(4),`
270			`D => d_3(1),`
271			`WCLK => clk,`
272			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
273			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8`
274			`);`
275			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram5 : RAM32X1S`
276			`generic map(`
277			`INIT => X"00014000"`
278			`)`
279			`port map (`
280			`A0 => a_2(0),`
281			`A1 => a_2(1),`
282			`A2 => a_2(2),`
283			`A3 => a_2(3),`
284			`A4 => a_2(4),`
285			`D => d_3(2),`
286			`WCLK => clk,`
287			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
288			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10`
289			`);`
290			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram9 : RAM32X1S`
291			`generic map(`
292			`INIT => X"00800000"`
293			`)`
294			`port map (`
295			`A0 => a_2(0),`
296			`A1 => a_2(1),`
297			`A2 => a_2(2),`
298			`A3 => a_2(3),`
299			`A4 => a_2(4),`
300			`D => d_3(4),`
301			`WCLK => clk,`
302			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
303			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18`
304			`);`
305			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram7 : RAM32X1S`
306			`generic map(`
307			`INIT => X"00001000"`
308			`)`
309			`port map (`
310			`A0 => a_2(0),`
311			`A1 => a_2(1),`
312			`A2 => a_2(2),`
313			`A3 => a_2(3),`
314			`A4 => a_2(4),`
315			`D => d_3(3),`
316			`WCLK => clk,`
317			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
318			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14`
319			`);`
320			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram8 : RAM32X1S`
321			`generic map(`
322			`INIT => X"00000000"`
323			`)`
324			`port map (`
325			`A0 => a_2(0),`
326			`A1 => a_2(1),`
327			`A2 => a_2(2),`
328			`A3 => a_2(3),`
329			`A4 => a_2(4),`
330			`D => d_3(3),`
331			`WCLK => clk,`
332			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
333			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16`
334			`);`
335			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram12 : RAM32X1S`
336			`generic map(`
337			`INIT => X"00000000"`
338			`)`
339			`port map (`
340			`A0 => a_2(0),`
341			`A1 => a_2(1),`
342			`A2 => a_2(2),`
343			`A3 => a_2(3),`
344			`A4 => a_2(4),`
345			`D => d_3(5),`
346			`WCLK => clk,`
347			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
348			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24`
349			`);`
350			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram10 : RAM32X1S`
351			`generic map(`
352			`INIT => X"00000000"`
353			`)`
354			`port map (`
355			`A0 => a_2(0),`
356			`A1 => a_2(1),`
357			`A2 => a_2(2),`
358			`A3 => a_2(3),`
359			`A4 => a_2(4),`
360			`D => d_3(4),`
361			`WCLK => clk,`
362			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
363			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20`
364			`);`
365			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram11 : RAM32X1S`
366			`generic map(`
367			`INIT => X"00010000"`
368			`)`
369			`port map (`
370			`A0 => a_2(0),`
371			`A1 => a_2(1),`
372			`A2 => a_2(2),`
373			`A3 => a_2(3),`
374			`A4 => a_2(4),`
375			`D => d_3(5),`
376			`WCLK => clk,`
377			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
378			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22`
379			`);`
380			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram15 : RAM32X1S`
381			`generic map(`
382			`INIT => X"00000000"`
383			`)`
384			`port map (`
385			`A0 => a_2(0),`
386			`A1 => a_2(1),`
387			`A2 => a_2(2),`
388			`A3 => a_2(3),`
389			`A4 => a_2(4),`
390			`D => d_3(7),`
391			`WCLK => clk,`
392			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
393			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30`
394			`);`
395			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram13 : RAM32X1S`
396			`generic map(`
397			`INIT => X"00504000"`
398			`)`
399			`port map (`
400			`A0 => a_2(0),`
401			`A1 => a_2(1),`
402			`A2 => a_2(2),`
403			`A3 => a_2(3),`
404			`A4 => a_2(4),`
405			`D => d_3(6),`
406			`WCLK => clk,`
407			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,`
408			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26`
409			`);`
410			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram14 : RAM32X1S`
411			`generic map(`
412			`INIT => X"00000000"`
413			`)`
414			`port map (`
415			`A0 => a_2(0),`
416			`A1 => a_2(1),`
417			`A2 => a_2(2),`
418			`A3 => a_2(3),`
419			`A4 => a_2(4),`
420			`D => d_3(6),`
421			`WCLK => clk,`
422			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
423			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28`
424			`);`
425			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram16 : RAM32X1S`
426			`generic map(`
427			`INIT => X"00000000"`
428			`)`
429			`port map (`
430			`A0 => a_2(0),`
431			`A1 => a_2(1),`
432			`A2 => a_2(2),`
433			`A3 => a_2(3),`
434			`A4 => a_2(4),`
435			`D => d_3(7),`
436			`WCLK => clk,`
437			`WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,`
438			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32`
439			`);`
440			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX711 : LUT3`
441			`generic map(`
442			`INIT => X"E4"`
443			`)`
444			`port map (`
445			`I0 => a_2(5),`
446			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30,`
447			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32,`
448			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(7)`
449			`);`
450			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX611 : LUT3`
451			`generic map(`
452			`INIT => X"E4"`
453			`)`
454			`port map (`
455			`I0 => a_2(5),`
456			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26,`
457			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28,`
458			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(6)`
459			`);`
460			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX511 : LUT3`
461			`generic map(`
462			`INIT => X"E4"`
463			`)`
464			`port map (`
465			`I0 => a_2(5),`
466			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22,`
467			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24,`
468			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(5)`
469			`);`
470			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX411 : LUT3`
471			`generic map(`
472			`INIT => X"E4"`
473			`)`
474			`port map (`
475			`I0 => a_2(5),`
476			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18,`
477			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20,`
478			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(4)`
479			`);`
480			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX311 : LUT3`
481			`generic map(`
482			`INIT => X"E4"`
483			`)`
484			`port map (`
485			`I0 => a_2(5),`
486			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14,`
487			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16,`
488			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(3)`
489			`);`
490			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX211 : LUT3`
491			`generic map(`
492			`INIT => X"E4"`
493			`)`
494			`port map (`
495			`I0 => a_2(5),`
496			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10,`
497			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12,`
498			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(2)`
499			`);`
500			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX111 : LUT3`
501			`generic map(`
502			`INIT => X"E4"`
503			`)`
504			`port map (`
505			`I0 => a_2(5),`
506			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6,`
507			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8,`
508			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(1)`
509			`);`
510			`BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX11 : LUT3`
511			`generic map(`
512			`INIT => X"E4"`
513			`)`
514			`port map (`
515			`I0 => a_2(5),`
516			`I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2,`
517			`I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4,`
518			`O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(0)`
519			`);`
520			`BU2_XST_GND : GND`
521			`port map (`
522			`G => BU2_qdpo(0)`
523			`);`
524
525			`end STRUCTURE;`
526
527			`-- synthesis translate_on`