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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Spartan3/] [wraddr_lut_mem.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: K.39
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: wraddr_lut_mem.vhd
10 
-- /___/   /\     Timestamp: Mon May 09 14:17:18 2011
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.vhd"
15 
-- Device       : 3s200pq208-4
16 
-- Input file   : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.ngc
17 
-- Output file  : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : wraddr_lut_mem
20 
-- Xilinx       : C:\Xilinx\10.1\ISE
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
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--     Development System Reference Guide, Chapter 23
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--     Synthesis and Simulation Design Guide, Chapter 6
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--
33 
--------------------------------------------------------------------------------
34 
 
35 
 
36 
-- synthesis translate_off
37 
library IEEE;
38 
use IEEE.STD_LOGIC_1164.ALL;
39 
library UNISIM;
40 
use UNISIM.VCOMPONENTS.ALL;
41 
use UNISIM.VPKG.ALL;
42 
 
43 
entity wraddr_lut_mem is
44 
  port (
45 
    clk : in STD_LOGIC := 'X';
46 
    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
47 
    qspo : out STD_LOGIC_VECTOR ( 5 downto 0 )
48 
  );
49 
end wraddr_lut_mem;
50 
 
51 
architecture STRUCTURE of wraddr_lut_mem is
52 
  signal N0 : STD_LOGIC;
53 
  signal N1 : STD_LOGIC;
54 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311 : STD_LOGIC;
55 
  signal BU2_N35 : STD_LOGIC;
56 
  signal BU2_N34 : STD_LOGIC;
57 
  signal BU2_N33 : STD_LOGIC;
58 
  signal BU2_N32 : STD_LOGIC;
59 
  signal BU2_N31 : STD_LOGIC;
60 
  signal BU2_N30 : STD_LOGIC;
61 
  signal BU2_N29 : STD_LOGIC;
62 
  signal BU2_N28 : STD_LOGIC;
63 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031 : STD_LOGIC;
64 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f51 : STD_LOGIC;
65 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002_22 : STD_LOGIC;
66 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001_21 : STD_LOGIC;
67 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_20 : STD_LOGIC;
68 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000 : STD_LOGIC;
69 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_18 : STD_LOGIC;
70 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17 : STD_LOGIC;
71 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_16 : STD_LOGIC;
72 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_15 : STD_LOGIC;
73 
  signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6_14 : STD_LOGIC;
74 
  signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
75 
  signal qspo_3 : STD_LOGIC_VECTOR ( 5 downto 0 );
76 
  signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
77 
begin
78 
  a_2(5) <= a(5);
79 
  a_2(4) <= a(4);
80 
  a_2(3) <= a(3);
81 
  a_2(2) <= a(2);
82 
  a_2(1) <= a(1);
83 
  a_2(0) <= a(0);
84 
  qspo(5) <= qspo_3(5);
85 
  qspo(4) <= qspo_3(4);
86 
  qspo(3) <= qspo_3(3);
87 
  qspo(2) <= qspo_3(2);
88 
  qspo(1) <= qspo_3(1);
89 
  qspo(0) <= qspo_3(0);
90 
  VCC_0 : VCC
91 
    port map (
92 
      P => N1
93 
    );
94 
  GND_1 : GND
95 
    port map (
96 
      G => N0
97 
    );
98 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311_f5 : MUXF5
99 
    port map (
100 
      I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311,
101 
      I1 => BU2_qdpo(0),
102 
      S => a_2(5),
103 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031
104 
    );
105 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00003111 : LUT4
106 
    generic map(
107 
      INIT => X"101C"
108 
    )
109 
    port map (
110 
      I0 => a_2(4),
111 
      I1 => a_2(1),
112 
      I2 => a_2(2),
113 
      I3 => a_2(3),
114 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311
115 
    );
116 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_G : LUT4
117 
    generic map(
118 
      INIT => X"0B3D"
119 
    )
120 
    port map (
121 
      I0 => a_2(1),
122 
      I1 => a_2(4),
123 
      I2 => a_2(5),
124 
      I3 => a_2(3),
125 
      O => BU2_N35
126 
    );
127 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_F : LUT4
128 
    generic map(
129 
      INIT => X"5351"
130 
    )
131 
    port map (
132 
      I0 => a_2(5),
133 
      I1 => a_2(1),
134 
      I2 => a_2(4),
135 
      I3 => a_2(3),
136 
      O => BU2_N34
137 
    );
138 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011 : MUXF5
139 
    port map (
140 
      I0 => BU2_N34,
141 
      I1 => BU2_N35,
142 
      S => a_2(2),
143 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_15
144 
    );
145 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_G : LUT4
146 
    generic map(
147 
      INIT => X"0B2C"
148 
    )
149 
    port map (
150 
      I0 => a_2(1),
151 
      I1 => a_2(4),
152 
      I2 => a_2(5),
153 
      I3 => a_2(3),
154 
      O => BU2_N33
155 
    );
156 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_F : LUT3
157 
    generic map(
158 
      INIT => X"26"
159 
    )
160 
    port map (
161 
      I0 => a_2(4),
162 
      I1 => a_2(5),
163 
      I2 => a_2(1),
164 
      O => BU2_N32
165 
    );
166 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004 : MUXF5
167 
    port map (
168 
      I0 => BU2_N32,
169 
      I1 => BU2_N33,
170 
      S => a_2(2),
171 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17
172 
    );
173 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_G : LUT4
174 
    generic map(
175 
      INIT => X"1656"
176 
    )
177 
    port map (
178 
      I0 => a_2(5),
179 
      I1 => a_2(3),
180 
      I2 => a_2(4),
181 
      I3 => a_2(1),
182 
      O => BU2_N31
183 
    );
184 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_F : LUT4
185 
    generic map(
186 
      INIT => X"1528"
187 
    )
188 
    port map (
189 
      I0 => a_2(5),
190 
      I1 => a_2(3),
191 
      I2 => a_2(1),
192 
      I3 => a_2(4),
193 
      O => BU2_N30
194 
    );
195 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005 : MUXF5
196 
    port map (
197 
      I0 => BU2_N30,
198 
      I1 => BU2_N31,
199 
      S => a_2(2),
200 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_18
201 
    );
202 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_G : LUT4
203 
    generic map(
204 
      INIT => X"1656"
205 
    )
206 
    port map (
207 
      I0 => a_2(5),
208 
      I1 => a_2(3),
209 
      I2 => a_2(4),
210 
      I3 => a_2(2),
211 
      O => BU2_N29
212 
    );
213 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_F : LUT4
214 
    generic map(
215 
      INIT => X"1653"
216 
    )
217 
    port map (
218 
      I0 => a_2(5),
219 
      I1 => a_2(2),
220 
      I2 => a_2(4),
221 
      I3 => a_2(3),
222 
      O => BU2_N28
223 
    );
224 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021 : MUXF5
225 
    port map (
226 
      I0 => BU2_N28,
227 
      I1 => BU2_N29,
228 
      S => a_2(1),
229 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_16
230 
    );
231 
  BU2_U0_gen_rom_rom_inst_qspo_int_3 : FDS
232 
    generic map(
233 
      INIT => '0'
234 
    )
235 
    port map (
236 
      C => clk,
237 
      D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031,
238 
      S => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17,
239 
      Q => qspo_3(3)
240 
    );
241 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6 : MUXF6
242 
    port map (
243 
      I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f51,
244 
      I1 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_20,
245 
      S => a_2(5),
246 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6_14
247 
    );
248 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_0 : MUXF5
249 
    port map (
250 
      I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002_22,
251 
      I1 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001_21,
252 
      S => a_2(4),
253 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f51
254 
    );
255 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00003 : LUT3
256 
    generic map(
257 
      INIT => X"F8"
258 
    )
259 
    port map (
260 
      I0 => a_2(3),
261 
      I1 => a_2(2),
262 
      I2 => a_2(0),
263 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002_22
264 
    );
265 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002 : LUT4
266 
    generic map(
267 
      INIT => X"9DDF"
268 
    )
269 
    port map (
270 
      I0 => a_2(3),
271 
      I1 => a_2(0),
272 
      I2 => a_2(2),
273 
      I3 => a_2(1),
274 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001_21
275 
    );
276 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5 : MUXF5
277 
    port map (
278 
      I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000,
279 
      I1 => BU2_qdpo(0),
280 
      S => a_2(4),
281 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_20
282 
    );
283 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001 : LUT4
284 
    generic map(
285 
      INIT => X"544E"
286 
    )
287 
    port map (
288 
      I0 => a_2(3),
289 
      I1 => a_2(0),
290 
      I2 => a_2(2),
291 
      I3 => a_2(1),
292 
      O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000
293 
    );
294 
  BU2_U0_gen_rom_rom_inst_qspo_int_5 : FD
295 
    generic map(
296 
      INIT => '0'
297 
    )
298 
    port map (
299 
      C => clk,
300 
      D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_18,
301 
      Q => qspo_3(5)
302 
    );
303 
  BU2_U0_gen_rom_rom_inst_qspo_int_4 : FD
304 
    generic map(
305 
      INIT => '0'
306 
    )
307 
    port map (
308 
      C => clk,
309 
      D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17,
310 
      Q => qspo_3(4)
311 
    );
312 
  BU2_U0_gen_rom_rom_inst_qspo_int_2 : FD
313 
    generic map(
314 
      INIT => '0'
315 
    )
316 
    port map (
317 
      C => clk,
318 
      D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_16,
319 
      Q => qspo_3(2)
320 
    );
321 
  BU2_U0_gen_rom_rom_inst_qspo_int_1 : FD
322 
    generic map(
323 
      INIT => '0'
324 
    )
325 
    port map (
326 
      C => clk,
327 
      D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_15,
328 
      Q => qspo_3(1)
329 
    );
330 
  BU2_U0_gen_rom_rom_inst_qspo_int_0 : FD
331 
    generic map(
332 
      INIT => '0'
333 
    )
334 
    port map (
335 
      C => clk,
336 
      D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6_14,
337 
      Q => qspo_3(0)
338 
    );
339 
  BU2_XST_GND : GND
340 
    port map (
341 
      G => BU2_qdpo(0)
342 
    );
343 
 
344 
end STRUCTURE;
345 
 
346 
-- synthesis translate_on

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