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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Virtex5/] [IPV4_PACKET_TRANSMITTER.vhd] - Blame information for rev 2

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-----------------------------------------------------------------------------------------
-- Copyright (C) 2010 Nikolaos Ch. Alachiotis                                                                                                           --
--                                                                                                                                                                                                                                      --
-- Engineer:                            Nikolaos Ch. Alachiotis                                                                                                         --
--                                                                                                                                                                                                                                      --
-- Contact:                                     alachiot@cs.tum.edu                                                                                                                     --
--                                                              n.alachiotis@gmail.com                                                                                                          --
--                                                                                                                                                                                                                              --
-- Create Date:                 14:45:39 11/27/2009                                                                                                             --
-- Module Name:                 IPV4_PACKET_TRANSMITTER                                                                                                         --
-- Target Devices:              Virtex 5 FPGAs                                                                                                                          --
-- Tool versions:               ISE 10.1                                                                                                                                                        --
-- Description:                         This component can be used to send IPv4 Ethernet Packets.               --
-- Additional Comments: The look-up table contains the header fields of the IP packet, --
--                                                              so please keep in mind that you have to reinitialize this LUT. --
--                                                                                                                                                                                                                                      --
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity IPV4_PACKET_TRANSMITTER is
    Port ( rst : in  STD_LOGIC;
           clk_125MHz : in  STD_LOGIC;
           transmit_start_enable : in  STD_LOGIC;
           transmit_data_length : in  STD_LOGIC_VECTOR (15 downto 0);
                          usr_data_trans_phase_on : out STD_LOGIC;
           transmit_data_input_bus : in  STD_LOGIC_VECTOR (7 downto 0);
           start_of_frame_O : out  STD_LOGIC;
                          end_of_frame_O : out  STD_LOGIC;
                          source_ready : out STD_LOGIC;
                          transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
 
                          flex_wren: in STD_LOGIC;
                          flex_wraddr: in STD_LOGIC_VECTOR(5 downto 0);
                          flex_wrdata: in STD_LOGIC_VECTOR(7 downto 0);
 
                          flex_checksum_baseval: in std_logic_vector(15 downto 0)
                          );
end IPV4_PACKET_TRANSMITTER;
 
architecture Behavioral of IPV4_PACKET_TRANSMITTER is
 
 
-----------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------
-- IPv4 PACKET STRUCTURE :                                                                                                                                                                                                                                                                                                      --
--                                                                                      Size            |               Description                                                                                     |               Transmission Order              |  Position             --
--                                                                              -----------------------------------------------------------------------------------------------------------
--                                                                                      6 bytes |       Destin MAC Address (PC)                                                         |               0 1 2 3 4 5                             |       LUT                             --
--                                                                                                              |       X-X-X-X-X-X                                                                                             |                                                                       |                                               --
--                                                                                                              |                                                                                                                               |                                                                       |                                               --
--                                                                                      6 bytes |       Source MAC Address (FPGA)                                                       |          6 7 8 9 10 11                        |       LUT                             --
--                                                                                                              |       11111111-11111111-11111111-11111111-...         |                                                                       |                                               --
--                                                                                      2 bytes  |      Ethernet Type *                                                                                 |               12 13                                           |       LUT                             --
--                                                                                                              |       (fixed to 00001000-00000000 :=>                                 |                                                                       |                                               --
--                                                                                                              |        Internet Protocol, Version 4 (IPv4))                   |                                                                       |                                               --
-- -- Start of IPv4 Packet ** - -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       --      |                                               --
--                                                                                      1 byte  |       4 MSBs = Version , 4 LSBs = Header Length               |               14                                                      |       LUT                             --
--                                                       |  0100                                0101                                                                    |                                                                       |                                               --
--                                                                                      1 byte  |       Differentiated Services                                                         |               15                                                      |       LUT                             --
--                                                                                                              |       00000000                                                                                                        |                                                                       |                                               --
--                                                                                      2 bytes |       Total Length                                                                                    |               16 17                                           |       REG                             --
--                                                                                                              |       00000000-00100100 (base: 20 + 8 + datalength)|                                                                  |                                               --
--                                                                                      2 bytes |       Identification                                                                                  |               18 19                                           |       LUT                             --
--                                                                                                              |       00000000-00000000                                                                               |                                                                       |                                               --
--                                                                                      2 bytes |       3 MSBs = Flags , 13 LSBs = Fragment Offset      |               20 21                                           |       LUT                             --
--                                                                                                              |       010 - 0000000000000                                                                     |                                                                       |                                               --
--                                                                                      1 byte  |       Time to Live                                                                                    |               22                                                      |       LUT                             --
--                                                                                                              |       01000000                                                                                                        |                                                                       |                                               --
--                                                                                      1 byte  |       Protocol                                                                                                        |               23                                                      |       LUT                             --
--                                                                                                              |       00010001                                                                                                        |                                                                       |                                               --
--                                                                                      2 bytes |  Header Checksum                                                                              |               24 25                                           |       REG                             --
--                                                                                                              |       10110111 01111101 (base value)                                  |                                                                       |                                               --
--                                                                                      4 bytes |       Source IP Address                                                                               |               26 27 28 29                             |       LUT                             --
--                                                                                                              |       X-X-X-X                                                                          - FPGA |                                                                       |                                               --
--                                                                                      4 bytes |       Destin IP Address                                                                               |               30 31 32 33                             |       LUT                             --
--                                                                                                              |       X-X-X-X                                                                          - PC           |                                                                       |                                               --
--      -- Start of UDP Packet *** -    -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -       -- |                                            --
--                                                                                      2 bytes |  Source Port                                                                                          |               34 35                                           |       LUT                             --
--                                                                                                              |       X-X                                                                                                             |                                                                       |                                               --
--                                                                                      2 bytes |       Destination Port                                                                                |               36 37                                           |       LUT                             --
--                                                                                                              |       X-X                                                                                                             |                                                                       |                                               --
--                                                                                      2 bytes |       Length                                                                                                  |               38 39                                           |       REG                             --
--                                                                                                              |       00000000 - 00010000   (8 + # data bytes)                |                                                                       |                                               --
--                                                                                      2 bytes |       Checksum                                                                                                        |               40 41                                           |       LUT                             --
--                                                                                                              |       00000000 - 00000000                                                                     |                                                                       |                                               --
--                                                                                      X bytes |       Data                                                                                                            |               42 .. X                                 |  from input           --
--                                                                                                              |                                                                                                                               |                                                                       |                                               --
-----------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------
 
--  *  More details about the Ethernet Type value you can find here:
--     http://en.wikipedia.org/wiki/Ethertype
 
-- **  More details about the Internet Protocol, Version 4 (IPv4) you can find here:
--     http://en.wikipedia.org/wiki/IPv4
 
-- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
--     http://en.wikipedia.org/wiki/User_Datagram_Protocol
 
-----------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------------
-- COMPONENT DECLARATION
--------------------------------------------------------------------------------------
 
component REG_16B_WREN is
    Port ( rst : in  STD_LOGIC;
                          clk : in  STD_LOGIC;
           wren : in  STD_LOGIC;
           input : in  STD_LOGIC_VECTOR (15 downto 0);
           output : out  STD_LOGIC_VECTOR (15 downto 0));
end component;
 
component IPV4_LUT_INDEXER is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           transmit_enable : in  STD_LOGIC;
           LUT_index : out  STD_LOGIC_VECTOR (5 downto 0));
end component;
 
--component dist_mem_64x8 is
--  port (
--    clk : in STD_LOGIC := 'X'; 
--    a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
--    qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
--  );
--end component;
 
component dist_mem_64x8 is
  port (
    clk : in STD_LOGIC := 'X';
    we : in STD_LOGIC := 'X';
    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
    d : in STD_LOGIC_VECTOR ( 7 downto 0 );
    qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
end component;
 
component OVERRIDE_LUT_CONTROL is
    Port ( clk : in  STD_LOGIC;
                input_addr : in  STD_LOGIC_VECTOR (5 downto 0);
           sel_total_length_MSBs : out  STD_LOGIC;
                          sel_total_length_LSBs : out  STD_LOGIC;
                          sel_header_checksum_MSBs : out  STD_LOGIC;
                          sel_header_checksum_LSBs : out  STD_LOGIC;
                          sel_length_MSBs : out  STD_LOGIC;
                          sel_length_LSBs : out  STD_LOGIC
           );
end component;
 
component TARGET_EOF is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           start : in  STD_LOGIC;
                          total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
           eof_O : out  STD_LOGIC);
end component;
 
component ENABLE_USER_DATA_TRANSMISSION is
    Port ( rst : in STD_LOGIC;
                          clk : in  STD_LOGIC;
           start_usr_data_trans : in  STD_LOGIC;
           stop_usr_data_trans : in  STD_LOGIC;
           usr_data_sel : out  STD_LOGIC);
end component;
 
component ALLOW_ZERO_UDP_CHECKSUM is
    Port ( clk : in  STD_LOGIC;
           input : in  STD_LOGIC;
                          output_to_readen  : out STD_LOGIC;
           output_to_datasel : out  STD_LOGIC);
end component;
 
 
--------------------------------------------------------------------------------------
-- SIGNAL DECLARATION
--------------------------------------------------------------------------------------
 
signal transmit_start_enable_tmp,
                 sel_total_length_MSBs,
                 sel_total_length_LSBs,
                 sel_header_checksum_MSBs,
                 sel_header_checksum_LSBs,
                 sel_length_MSBs,
                 sel_length_LSBs,
                 lut_out_sel,
                 source_ready_previous_value,
                 end_of_frame_O_tmp,
                 transmit_start_enable_reg,
                 usr_data_sel_sig,
                 start_usr_data_read,
                 start_usr_data_trans                                                           :       STD_LOGIC;
 
signal LUT_addr,
                 LUT_addr_dual,
                 sel_rd,
                 sel_wr:        STD_LOGIC_VECTOR(5 downto 0);
 
signal transmit_data_input_bus_tmp,
                 transmit_data_output_bus_tmp,
                 sel_total_length_MSBs_vec,
                 sel_total_length_LSBs_vec,
                 sel_header_checksum_MSBs_vec,
                 sel_header_checksum_LSBs_vec,
                 sel_length_MSBs_vec,
                 sel_length_LSBs_vec,
                 lut_out_sel_vec,
                 transmit_data_output_bus_no_usr_data,
                 usr_data_not_sel_vec,
                 usr_data_sel_vec                                                                               :       STD_LOGIC_VECTOR(7 downto 0);
 
signal transmit_data_length_tmp,
                 data_length_regout,
                 tmp_total_length,
                 tmp_header_checksum,
                 tmp_header_checksum_baseval,
                 tmp_length                                                                                             :       STD_LOGIC_VECTOR(15 downto 0);
 
 
begin
 
transmit_start_enable_tmp<=transmit_start_enable;
 
transmit_data_length_tmp<=transmit_data_length;
 
transmit_data_input_bus_tmp<=transmit_data_input_bus;
 
----------------------------------------------------------------------------------------------------
-- start_of_frame_O signal
----------------------------------------------------------------------------------------------------
-- Description:  start_of_frame_O is active low
--                                        We connect it to the delayed for one clock cycle transmit_start_enable input signal
--                                        through a NOT gate since transmit_start_enable is active high.
 
process(clk_125MHz)
begin
if clk_125MHz'event and clk_125MHz='1' then
        transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle.
end if;
end process;
 
start_of_frame_O<=not transmit_start_enable_reg;
 
----------------------------------------------------------------------------------------------------
-- end_of_frame_O signal
----------------------------------------------------------------------------------------------------
-- Description:  end_of_frame_O is active low
--                                        The TARGET_EOF module targets the last byte of the packet that is being transmitted
--                                        based on a counter that counts the number of transmitted bytes and a comparator that
--                                        detects the last byte which is the <tmp_total_length>th byte.
 
TARGET_EOF_port_map: TARGET_EOF  port map
(
        rst =>rst,
   clk =>clk_125MHz,
   start =>transmit_start_enable_reg,
        total_length_from_reg =>tmp_total_length,
   eof_O =>end_of_frame_O_tmp
);
 
--* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the 
--       IPv4 packet. (MAC addresses + Ethernet Type)
 
end_of_frame_O<=end_of_frame_O_tmp;
 
----------------------------------------------------------------------------------------------------
-- source_ready signal
----------------------------------------------------------------------------------------------------
-- Description:  source_ready is active low
--                                        This signal is idle(high). (based on rst and end_of_frame_O_tmp). 
--                                        This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp).
 
process(clk_125MHz)
begin
if rst='1' then
        source_ready<='1';
        source_ready_previous_value<='1';
else
        if clk_125MHz'event and clk_125MHz='1' then
                if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then
                        source_ready<='0';
                        source_ready_previous_value<='0';
                else
                        if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then
                                source_ready<='1';
                           source_ready_previous_value<='1';
                        end if;
                end if;
        end if;
end if;
end process;
 
----------------------------------------------------------------------------------------------------
-- transmit_data_output_bus 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Component Name:      REG_16B_WREN
-- Instance Name:       NUMBER_OR_DATA_IN_BYTES_REGISTER
-- Description:                 Register that holds the number of bytes of input data 
--                                                      that will be transmitted in the packet.
----------------------------------------------------------------------------------------------------
NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map
(
        rst =>rst,
        clk =>clk_125MHz,
        wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren.
        input =>transmit_data_length_tmp,
        output =>data_length_regout
);
----------------------------------------------------------------------------------------------------
 
tmp_total_length<="0000000000011100" + data_length_regout;
 
 
tmp_header_checksum_baseval<=flex_checksum_baseval;
--tmp_header_checksum_baseval<="1011011101111101";      -- CHANGE VALUE! : You have to change this value!
tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout;
 
tmp_length<="0000000000001000" + data_length_regout;
 
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name:      IPV4_LUT_INDEXER
-- Instance Name:       IPV4_LUT_INDEXER_port_map
-- Description:                 When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the
--                                                      addresses to the LUT that contains the header section of the IP packet.
----------------------------------------------------------------------------------------------------
IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map
(
        rst =>rst,
   clk =>clk_125MHz,
   transmit_enable =>transmit_start_enable_tmp,
   LUT_index =>LUT_addr
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name:      dist_mem_64x8
-- Instance Name:       LUT_MEM
-- Description:                 LUT that contains the header section.
----------------------------------------------------------------------------------------------------
LUT_addr_dual <= (LUT_addr and sel_rd) or (flex_wraddr and sel_wr);
 
sel_rd <= (others=> not flex_wren);
sel_wr <= (others=>     flex_wren);
 
LUT_MEM : dist_mem_64x8 port map
(
        --clk =>clk_125MHz,
   --a =>LUT_addr_dual,
   --qspo =>transmit_data_output_bus_tmp
 
    clk =>clk_125MHz,
    we =>flex_wren,
    a => LUT_addr_dual,
    d => flex_wrdata,
    qspo =>transmit_data_output_bus_tmp
 
 
);
 
 
 
 
 
 
 
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name:      OVERRIDE_LUT_CONTROL
-- Instance Name:       OVERRIDE_LUT_CONTROL_port_map
-- Description:                 Decides whether the output byte will come from the LUT or not.
----------------------------------------------------------------------------------------------------
OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map
(
        clk =>clk_125MHz,
        input_addr =>LUT_addr,
        sel_total_length_MSBs =>sel_total_length_MSBs,
        sel_total_length_LSBs =>sel_total_length_LSBs,
        sel_header_checksum_MSBs =>sel_header_checksum_MSBs,
        sel_header_checksum_LSBs =>sel_header_checksum_LSBs,
        sel_length_MSBs =>sel_length_MSBs,
        sel_length_LSBs =>sel_length_LSBs
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- MUX 7 to 1
sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs);
sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs);
sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs);
sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs);
sel_length_MSBs_vec<=(others=>sel_length_MSBs);
sel_length_LSBs_vec<=(others=>sel_length_LSBs);
lut_out_sel_vec <= (others=>lut_out_sel);
 
lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and
                                 (not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and
                                 (not sel_length_MSBs) and (not sel_length_LSBs);
 
-- MUX output
transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or
                                                                                                  (tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or
                                                                                                  (tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or
                                                                                                  (tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or
                                                                                                  (tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or
                                                                                                  (tmp_length(15 downto 8) and sel_length_MSBs_vec) or
                                                                                                  (tmp_length(7 downto 0) and sel_length_LSBs_vec);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name:      ALLOW_ZERO_UDP_CHECKSUM
-- Instance Name:       ALLOW_ZERO_UDP_CHECKSUM_port_map
-- Description:                 Delays the user data transmition phase in order to transmit two bytes with zero
--                                                      first.
----------------------------------------------------------------------------------------------------
ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map
(
        clk =>clk_125MHz,
        input =>sel_length_LSBs,
        output_to_readen =>start_usr_data_read,
        output_to_datasel =>start_usr_data_trans
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name:      ENABLE_USER_DATA_TRANSMISSION
-- Instance Name:       ENABLE_USER_DATA_READ_port_map
-- Description:                 Sets usr_data_trans_phase_on signal one cycle before the transmittion of the 
--                                                      first user byte.
----------------------------------------------------------------------------------------------------
ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map
(       rst =>rst,
   clk =>clk_125MHz,
   start_usr_data_trans =>start_usr_data_read,
   stop_usr_data_trans =>end_of_frame_O_tmp,
   usr_data_sel =>usr_data_trans_phase_on
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name:      ENABLE_USER_DATA_TRANSMISSION
-- Instance Name:       ENABLE_USER_DATA_TRANSMISSION_port_map
-- Description:                 Sets usr_data_sel_sig signal to select user data for transmittion.
----------------------------------------------------------------------------------------------------
ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map
(       rst =>rst,
   clk =>clk_125MHz,
   start_usr_data_trans =>start_usr_data_trans,
   stop_usr_data_trans =>end_of_frame_O_tmp,
   usr_data_sel =>usr_data_sel_sig
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- MUX 2 to 1
usr_data_not_sel_vec<=(others=>not usr_data_sel_sig);
usr_data_sel_vec<=(others=>usr_data_sel_sig);
 
-- MUX output
transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or
                                                                 (transmit_data_input_bus and usr_data_sel_vec);
----------------------------------------------------------------------------------------------------
 
end Behavioral;

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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Virtex5/] [IPV4_PACKET_TRANSMITTER.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	NikosAl	`-----------------------------------------------------------------------------------------`
2			`-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --`
3			`-- --`
4			`-- Engineer: Nikolaos Ch. Alachiotis --`
5			`-- --`
6			`-- Contact: alachiot@cs.tum.edu --`
7			`-- n.alachiotis@gmail.com --`
8			`-- --`
9			`-- Create Date: 14:45:39 11/27/2009 --`
10			`-- Module Name: IPV4_PACKET_TRANSMITTER --`
11			`-- Target Devices: Virtex 5 FPGAs --`
12			`-- Tool versions: ISE 10.1 --`
13			`-- Description: This component can be used to send IPv4 Ethernet Packets. --`
14			`-- Additional Comments: The look-up table contains the header fields of the IP packet, --`
15			`-- so please keep in mind that you have to reinitialize this LUT. --`
16			`-- --`
17			`-----------------------------------------------------------------------------------------`
18			`library IEEE;`
19			`use IEEE.STD_LOGIC_1164.ALL;`
20			`use IEEE.STD_LOGIC_ARITH.ALL;`
21			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
22
23			`---- Uncomment the following library declaration if instantiating`
24			`---- any Xilinx primitives in this code.`
25			`--library UNISIM;`
26			`--use UNISIM.VComponents.all;`
27
28			`entity IPV4_PACKET_TRANSMITTER is`
29			`Port ( rst : in STD_LOGIC;`
30			`clk_125MHz : in STD_LOGIC;`
31			`transmit_start_enable : in STD_LOGIC;`
32			`transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);`
33			`usr_data_trans_phase_on : out STD_LOGIC;`
34			`transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);`
35			`start_of_frame_O : out STD_LOGIC;`
36			`end_of_frame_O : out STD_LOGIC;`
37			`source_ready : out STD_LOGIC;`
38			`transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);`
39
40			`flex_wren: in STD_LOGIC;`
41			`flex_wraddr: in STD_LOGIC_VECTOR(5 downto 0);`
42			`flex_wrdata: in STD_LOGIC_VECTOR(7 downto 0);`
43
44			`flex_checksum_baseval: in std_logic_vector(15 downto 0)`
45			`);`
46			`end IPV4_PACKET_TRANSMITTER;`
47
48			`architecture Behavioral of IPV4_PACKET_TRANSMITTER is`
49
50
51			`-----------------------------------------------------------------------------------------------------------------------------------------`
52			`-----------------------------------------------------------------------------------------------------------------------------------------`
53			`-- IPv4 PACKET STRUCTURE : --`
54			`-- Size \| Description \| Transmission Order \| Position --`
55			`-- -----------------------------------------------------------------------------------------------------------`
56			`-- 6 bytes \| Destin MAC Address (PC) \| 0 1 2 3 4 5 \| LUT --`
57			`-- \| X-X-X-X-X-X \| \| --`
58			`-- \| \| \| --`
59			`-- 6 bytes \| Source MAC Address (FPGA) \| 6 7 8 9 10 11 \| LUT --`
60			`-- \| 11111111-11111111-11111111-11111111-... \| \| --`
61			`-- 2 bytes \| Ethernet Type * \| 12 13 \| LUT --`
62			`-- \| (fixed to 00001000-00000000 :=> \| \| --`
63			`-- \| Internet Protocol, Version 4 (IPv4)) \| \| --`
64			`-- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- \| --`
65			`-- 1 byte \| 4 MSBs = Version , 4 LSBs = Header Length \| 14 \| LUT --`
66			`-- \| 0100 0101 \| \| --`
67			`-- 1 byte \| Differentiated Services \| 15 \| LUT --`
68			`-- \| 00000000 \| \| --`
69			`-- 2 bytes \| Total Length \| 16 17 \| REG --`
70			`-- \| 00000000-00100100 (base: 20 + 8 + datalength)\| \| --`
71			`-- 2 bytes \| Identification \| 18 19 \| LUT --`
72			`-- \| 00000000-00000000 \| \| --`
73			`-- 2 bytes \| 3 MSBs = Flags , 13 LSBs = Fragment Offset \| 20 21 \| LUT --`
74			`-- \| 010 - 0000000000000 \| \| --`
75			`-- 1 byte \| Time to Live \| 22 \| LUT --`
76			`-- \| 01000000 \| \| --`
77			`-- 1 byte \| Protocol \| 23 \| LUT --`
78			`-- \| 00010001 \| \| --`
79			`-- 2 bytes \| Header Checksum \| 24 25 \| REG --`
80			`-- \| 10110111 01111101 (base value) \| \| --`
81			`-- 4 bytes \| Source IP Address \| 26 27 28 29 \| LUT --`
82			`-- \| X-X-X-X - FPGA \| \| --`
83			`-- 4 bytes \| Destin IP Address \| 30 31 32 33 \| LUT --`
84			`-- \| X-X-X-X - PC \| \| --`
85			`-- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- \| --`
86			`-- 2 bytes \| Source Port \| 34 35 \| LUT --`
87			`-- \| X-X \| \| --`
88			`-- 2 bytes \| Destination Port \| 36 37 \| LUT --`
89			`-- \| X-X \| \| --`
90			`-- 2 bytes \| Length \| 38 39 \| REG --`
91			`-- \| 00000000 - 00010000 (8 + # data bytes) \| \| --`
92			`-- 2 bytes \| Checksum \| 40 41 \| LUT --`
93			`-- \| 00000000 - 00000000 \| \| --`
94			`-- X bytes \| Data \| 42 .. X \| from input --`
95			`-- \| \| \| --`
96			`-----------------------------------------------------------------------------------------------------------------------------------------`
97			`-----------------------------------------------------------------------------------------------------------------------------------------`
98
99			`-- * More details about the Ethernet Type value you can find here:`
100			`-- http://en.wikipedia.org/wiki/Ethertype`
101
102			`-- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here:`
103			`-- http://en.wikipedia.org/wiki/IPv4`
104
105			`-- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here:`
106			`-- http://en.wikipedia.org/wiki/User_Datagram_Protocol`
107
108			`-----------------------------------------------------------------------------------------------------------------------------------------`
109			`-----------------------------------------------------------------------------------------------------------------------------------------`
110
111
112
113			`--------------------------------------------------------------------------------------`
114			`-- COMPONENT DECLARATION`
115			`--------------------------------------------------------------------------------------`
116
117			`component REG_16B_WREN is`
118			`Port ( rst : in STD_LOGIC;`
119			`clk : in STD_LOGIC;`
120			`wren : in STD_LOGIC;`
121			`input : in STD_LOGIC_VECTOR (15 downto 0);`
122			`output : out STD_LOGIC_VECTOR (15 downto 0));`
123			`end component;`
124
125			`component IPV4_LUT_INDEXER is`
126			`Port ( rst : in STD_LOGIC;`
127			`clk : in STD_LOGIC;`
128			`transmit_enable : in STD_LOGIC;`
129			`LUT_index : out STD_LOGIC_VECTOR (5 downto 0));`
130			`end component;`
131
132			`--component dist_mem_64x8 is`
133			`-- port (`
134			`-- clk : in STD_LOGIC := 'X';`
135			`-- a : in STD_LOGIC_VECTOR ( 5 downto 0 );`
136			`-- qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )`
137			`-- );`
138			`--end component;`
139
140			`component dist_mem_64x8 is`
141			`port (`
142			`clk : in STD_LOGIC := 'X';`
143			`we : in STD_LOGIC := 'X';`
144			`a : in STD_LOGIC_VECTOR ( 5 downto 0 );`
145			`d : in STD_LOGIC_VECTOR ( 7 downto 0 );`
146			`qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )`
147			`);`
148			`end component;`
149
150			`component OVERRIDE_LUT_CONTROL is`
151			`Port ( clk : in STD_LOGIC;`
152			`input_addr : in STD_LOGIC_VECTOR (5 downto 0);`
153			`sel_total_length_MSBs : out STD_LOGIC;`
154			`sel_total_length_LSBs : out STD_LOGIC;`
155			`sel_header_checksum_MSBs : out STD_LOGIC;`
156			`sel_header_checksum_LSBs : out STD_LOGIC;`
157			`sel_length_MSBs : out STD_LOGIC;`
158			`sel_length_LSBs : out STD_LOGIC`
159			`);`
160			`end component;`
161
162			`component TARGET_EOF is`
163			`Port ( rst : in STD_LOGIC;`
164			`clk : in STD_LOGIC;`
165			`start : in STD_LOGIC;`
166			`total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);`
167			`eof_O : out STD_LOGIC);`
168			`end component;`
169
170			`component ENABLE_USER_DATA_TRANSMISSION is`
171			`Port ( rst : in STD_LOGIC;`
172			`clk : in STD_LOGIC;`
173			`start_usr_data_trans : in STD_LOGIC;`
174			`stop_usr_data_trans : in STD_LOGIC;`
175			`usr_data_sel : out STD_LOGIC);`
176			`end component;`
177
178			`component ALLOW_ZERO_UDP_CHECKSUM is`
179			`Port ( clk : in STD_LOGIC;`
180			`input : in STD_LOGIC;`
181			`output_to_readen : out STD_LOGIC;`
182			`output_to_datasel : out STD_LOGIC);`
183			`end component;`
184
185
186			`--------------------------------------------------------------------------------------`
187			`-- SIGNAL DECLARATION`
188			`--------------------------------------------------------------------------------------`
189
190			`signal transmit_start_enable_tmp,`
191			`sel_total_length_MSBs,`
192			`sel_total_length_LSBs,`
193			`sel_header_checksum_MSBs,`
194			`sel_header_checksum_LSBs,`
195			`sel_length_MSBs,`
196			`sel_length_LSBs,`
197			`lut_out_sel,`
198			`source_ready_previous_value,`
199			`end_of_frame_O_tmp,`
200			`transmit_start_enable_reg,`
201			`usr_data_sel_sig,`
202			`start_usr_data_read,`
203			`start_usr_data_trans : STD_LOGIC;`
204
205			`signal LUT_addr,`
206			`LUT_addr_dual,`
207			`sel_rd,`
208			`sel_wr: STD_LOGIC_VECTOR(5 downto 0);`
209
210			`signal transmit_data_input_bus_tmp,`
211			`transmit_data_output_bus_tmp,`
212			`sel_total_length_MSBs_vec,`
213			`sel_total_length_LSBs_vec,`
214			`sel_header_checksum_MSBs_vec,`
215			`sel_header_checksum_LSBs_vec,`
216			`sel_length_MSBs_vec,`
217			`sel_length_LSBs_vec,`
218			`lut_out_sel_vec,`
219			`transmit_data_output_bus_no_usr_data,`
220			`usr_data_not_sel_vec,`
221			`usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0);`
222
223			`signal transmit_data_length_tmp,`
224			`data_length_regout,`
225			`tmp_total_length,`
226			`tmp_header_checksum,`
227			`tmp_header_checksum_baseval,`
228			`tmp_length : STD_LOGIC_VECTOR(15 downto 0);`
229
230
231			`begin`
232
233			`transmit_start_enable_tmp<=transmit_start_enable;`
234
235			`transmit_data_length_tmp<=transmit_data_length;`
236
237			`transmit_data_input_bus_tmp<=transmit_data_input_bus;`
238
239			`----------------------------------------------------------------------------------------------------`
240			`-- start_of_frame_O signal`
241			`----------------------------------------------------------------------------------------------------`
242			`-- Description: start_of_frame_O is active low`
243			`-- We connect it to the delayed for one clock cycle transmit_start_enable input signal`
244			`-- through a NOT gate since transmit_start_enable is active high.`
245
246			`process(clk_125MHz)`
247			`begin`
248			`if clk_125MHz'event and clk_125MHz='1' then`
249			`transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle.`
250			`end if;`
251			`end process;`
252
253			`start_of_frame_O<=not transmit_start_enable_reg;`
254
255			`----------------------------------------------------------------------------------------------------`
256			`-- end_of_frame_O signal`
257			`----------------------------------------------------------------------------------------------------`
258			`-- Description: end_of_frame_O is active low`
259			`-- The TARGET_EOF module targets the last byte of the packet that is being transmitted`
260			`-- based on a counter that counts the number of transmitted bytes and a comparator that`
261			`-- detects the last byte which is the <tmp_total_length>th byte.`
262
263			`TARGET_EOF_port_map: TARGET_EOF port map`
264			`(`
265			`rst =>rst,`
266			`clk =>clk_125MHz,`
267			`start =>transmit_start_enable_reg,`
268			`total_length_from_reg =>tmp_total_length,`
269			`eof_O =>end_of_frame_O_tmp`
270			`);`
271
272			`--* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the`
273			`-- IPv4 packet. (MAC addresses + Ethernet Type)`
274
275			`end_of_frame_O<=end_of_frame_O_tmp;`
276
277			`----------------------------------------------------------------------------------------------------`
278			`-- source_ready signal`
279			`----------------------------------------------------------------------------------------------------`
280			`-- Description: source_ready is active low`
281			`-- This signal is idle(high). (based on rst and end_of_frame_O_tmp).`
282			`-- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp).`
283
284			`process(clk_125MHz)`
285			`begin`
286			`if rst='1' then`
287			`source_ready<='1';`
288			`source_ready_previous_value<='1';`
289			`else`
290			`if clk_125MHz'event and clk_125MHz='1' then`
291			`if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then`
292			`source_ready<='0';`
293			`source_ready_previous_value<='0';`
294			`else`
295			`if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then`
296			`source_ready<='1';`
297			`source_ready_previous_value<='1';`
298			`end if;`
299			`end if;`
300			`end if;`
301			`end if;`
302			`end process;`
303
304			`----------------------------------------------------------------------------------------------------`
305			`-- transmit_data_output_bus`
306			`----------------------------------------------------------------------------------------------------`
307			`----------------------------------------------------------------------------------------------------`
308			`-- Component Name: REG_16B_WREN`
309			`-- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER`
310			`-- Description: Register that holds the number of bytes of input data`
311			`-- that will be transmitted in the packet.`
312			`----------------------------------------------------------------------------------------------------`
313			`NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map`
314			`(`
315			`rst =>rst,`
316			`clk =>clk_125MHz,`
317			`wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren.`
318			`input =>transmit_data_length_tmp,`
319			`output =>data_length_regout`
320			`);`
321			`----------------------------------------------------------------------------------------------------`
322
323			`tmp_total_length<="0000000000011100" + data_length_regout;`
324
325
326			`tmp_header_checksum_baseval<=flex_checksum_baseval;`
327			`--tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value!`
328			`tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout;`
329
330			`tmp_length<="0000000000001000" + data_length_regout;`
331
332			`----------------------------------------------------------------------------------------------------`
333
334			`----------------------------------------------------------------------------------------------------`
335			`-- Component Name: IPV4_LUT_INDEXER`
336			`-- Instance Name: IPV4_LUT_INDEXER_port_map`
337			`-- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the`
338			`-- addresses to the LUT that contains the header section of the IP packet.`
339			`----------------------------------------------------------------------------------------------------`
340			`IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map`
341			`(`
342			`rst =>rst,`
343			`clk =>clk_125MHz,`
344			`transmit_enable =>transmit_start_enable_tmp,`
345			`LUT_index =>LUT_addr`
346			`);`
347			`----------------------------------------------------------------------------------------------------`
348
349			`----------------------------------------------------------------------------------------------------`
350			`-- Component Name: dist_mem_64x8`
351			`-- Instance Name: LUT_MEM`
352			`-- Description: LUT that contains the header section.`
353			`----------------------------------------------------------------------------------------------------`
354			`LUT_addr_dual <= (LUT_addr and sel_rd) or (flex_wraddr and sel_wr);`
355
356			`sel_rd <= (others=> not flex_wren);`
357			`sel_wr <= (others=> flex_wren);`
358
359			`LUT_MEM : dist_mem_64x8 port map`
360			`(`
361			`--clk =>clk_125MHz,`
362			`--a =>LUT_addr_dual,`
363			`--qspo =>transmit_data_output_bus_tmp`
364
365			`clk =>clk_125MHz,`
366			`we =>flex_wren,`
367			`a => LUT_addr_dual,`
368			`d => flex_wrdata,`
369			`qspo =>transmit_data_output_bus_tmp`
370
371
372			`);`
373
374
375
376
377
378
379
380			`----------------------------------------------------------------------------------------------------`
381
382			`----------------------------------------------------------------------------------------------------`
383			`-- Component Name: OVERRIDE_LUT_CONTROL`
384			`-- Instance Name: OVERRIDE_LUT_CONTROL_port_map`
385			`-- Description: Decides whether the output byte will come from the LUT or not.`
386			`----------------------------------------------------------------------------------------------------`
387			`OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map`
388			`(`
389			`clk =>clk_125MHz,`
390			`input_addr =>LUT_addr,`
391			`sel_total_length_MSBs =>sel_total_length_MSBs,`
392			`sel_total_length_LSBs =>sel_total_length_LSBs,`
393			`sel_header_checksum_MSBs =>sel_header_checksum_MSBs,`
394			`sel_header_checksum_LSBs =>sel_header_checksum_LSBs,`
395			`sel_length_MSBs =>sel_length_MSBs,`
396			`sel_length_LSBs =>sel_length_LSBs`
397			`);`
398			`----------------------------------------------------------------------------------------------------`
399
400			`----------------------------------------------------------------------------------------------------`
401			`-- MUX 7 to 1`
402			`sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs);`
403			`sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs);`
404			`sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs);`
405			`sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs);`
406			`sel_length_MSBs_vec<=(others=>sel_length_MSBs);`
407			`sel_length_LSBs_vec<=(others=>sel_length_LSBs);`
408			`lut_out_sel_vec <= (others=>lut_out_sel);`
409
410			`lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and`
411			`(not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and`
412			`(not sel_length_MSBs) and (not sel_length_LSBs);`
413
414			`-- MUX output`
415			`transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or`
416			`(tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or`
417			`(tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or`
418			`(tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or`
419			`(tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or`
420			`(tmp_length(15 downto 8) and sel_length_MSBs_vec) or`
421			`(tmp_length(7 downto 0) and sel_length_LSBs_vec);`
422			`----------------------------------------------------------------------------------------------------`
423
424			`----------------------------------------------------------------------------------------------------`
425			`-- Component Name: ALLOW_ZERO_UDP_CHECKSUM`
426			`-- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map`
427			`-- Description: Delays the user data transmition phase in order to transmit two bytes with zero`
428			`-- first.`
429			`----------------------------------------------------------------------------------------------------`
430			`ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map`
431			`(`
432			`clk =>clk_125MHz,`
433			`input =>sel_length_LSBs,`
434			`output_to_readen =>start_usr_data_read,`
435			`output_to_datasel =>start_usr_data_trans`
436			`);`
437			`----------------------------------------------------------------------------------------------------`
438
439			`----------------------------------------------------------------------------------------------------`
440			`-- Component Name: ENABLE_USER_DATA_TRANSMISSION`
441			`-- Instance Name: ENABLE_USER_DATA_READ_port_map`
442			`-- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the`
443			`-- first user byte.`
444			`----------------------------------------------------------------------------------------------------`
445			`ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map`
446			`( rst =>rst,`
447			`clk =>clk_125MHz,`
448			`start_usr_data_trans =>start_usr_data_read,`
449			`stop_usr_data_trans =>end_of_frame_O_tmp,`
450			`usr_data_sel =>usr_data_trans_phase_on`
451			`);`
452			`----------------------------------------------------------------------------------------------------`
453
454			`----------------------------------------------------------------------------------------------------`
455			`-- Component Name: ENABLE_USER_DATA_TRANSMISSION`
456			`-- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map`
457			`-- Description: Sets usr_data_sel_sig signal to select user data for transmittion.`
458			`----------------------------------------------------------------------------------------------------`
459			`ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map`
460			`( rst =>rst,`
461			`clk =>clk_125MHz,`
462			`start_usr_data_trans =>start_usr_data_trans,`
463			`stop_usr_data_trans =>end_of_frame_O_tmp,`
464			`usr_data_sel =>usr_data_sel_sig`
465			`);`
466			`----------------------------------------------------------------------------------------------------`
467
468			`----------------------------------------------------------------------------------------------------`
469			`-- MUX 2 to 1`
470			`usr_data_not_sel_vec<=(others=>not usr_data_sel_sig);`
471			`usr_data_sel_vec<=(others=>usr_data_sel_sig);`
472
473			`-- MUX output`
474			`transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or`
475			`(transmit_data_input_bus and usr_data_sel_vec);`
476			`----------------------------------------------------------------------------------------------------`
477
478			`end Behavioral;`