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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.39
--  \   \         Application: netgen
--  /   /         Filename: dist_mem_64x8.vhd
-- /___/   /\     Timestamp: Sat Feb 12 17:26:42 2011
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.vhd" 
-- Device       : 5vsx95tff1136-1
-- Input file   : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.ngc
-- Output file  : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.vhd
-- # of Entities        : 1
-- Design Name  : dist_mem_64x8
-- Xilinx       : C:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity dist_mem_64x8 is
  port (
    clk : in STD_LOGIC := 'X';
    we : in STD_LOGIC := 'X';
    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
    d : in STD_LOGIC_VECTOR ( 7 downto 0 );
    qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
end dist_mem_64x8;
 
architecture STRUCTURE of dist_mem_64x8 is
  signal N0 : STD_LOGIC;
  signal N1 : STD_LOGIC;
  signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal d_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qspo_4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal BU2_U0_gen_sp_ram_spram_inst_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
  a_2(5) <= a(5);
  a_2(4) <= a(4);
  a_2(3) <= a(3);
  a_2(2) <= a(2);
  a_2(1) <= a(1);
  a_2(0) <= a(0);
  d_3(7) <= d(7);
  d_3(6) <= d(6);
  d_3(5) <= d(5);
  d_3(4) <= d(4);
  d_3(3) <= d(3);
  d_3(2) <= d(2);
  d_3(1) <= d(1);
  d_3(0) <= d(0);
  qspo(7) <= qspo_4(7);
  qspo(6) <= qspo_4(6);
  qspo(5) <= qspo_4(5);
  qspo(4) <= qspo_4(4);
  qspo(3) <= qspo_4(3);
  qspo(2) <= qspo_4(2);
  qspo(1) <= qspo_4(1);
  qspo(0) <= qspo_4(0);
  VCC_0 : VCC
    port map (
      P => N1
    );
  GND_1 : GND
    port map (
      G => N0
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram8 : RAM64X1S
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(7),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(7)
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram7 : RAM64X1S
    generic map(
      INIT => X"0000000000504000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(6),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(6)
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram6 : RAM64X1S
    generic map(
      INIT => X"0000000000010000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(5),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(5)
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram5 : RAM64X1S
    generic map(
      INIT => X"0000000000800000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(4),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(4)
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram4 : RAM64X1S
    generic map(
      INIT => X"0000000000001000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(3),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(3)
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram3 : RAM64X1S
    generic map(
      INIT => X"0000000000014000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(2),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(2)
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram2 : RAM64X1S
    generic map(
      INIT => X"0000000000000000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(1),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(1)
    );
  BU2_U0_gen_sp_ram_spram_inst_Mram_ram1 : RAM64X1S
    generic map(
      INIT => X"0000000000804000"
    )
    port map (
      A0 => a_2(0),
      A1 => a_2(1),
      A2 => a_2(2),
      A3 => a_2(3),
      A4 => a_2(4),
      A5 => a_2(5),
      D => d_3(0),
      WCLK => clk,
      WE => we,
      O => BU2_U0_gen_sp_ram_spram_inst_spo_int(0)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(7),
      Q => qspo_4(7)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(6),
      Q => qspo_4(6)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(5),
      Q => qspo_4(5)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(4),
      Q => qspo_4(4)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(3),
      Q => qspo_4(3)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(2),
      Q => qspo_4(2)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(1),
      Q => qspo_4(1)
    );
  BU2_U0_gen_sp_ram_spram_inst_qspo_int_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => BU2_U0_gen_sp_ram_spram_inst_spo_int(0),
      Q => qspo_4(0)
    );
  BU2_XST_GND : GND
    port map (
      G => BU2_qdpo(0)
    );
 
end STRUCTURE;
 
-- synthesis translate_on

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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Virtex5/] [dist_mem_64x8.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	NikosAl	`--------------------------------------------------------------------------------`
2			`-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.`
3			`--------------------------------------------------------------------------------`
4			`-- ____ ____`
5			`-- / /\/ /`
6			`-- /___/ \ / Vendor: Xilinx`
7			`-- \ \ \/ Version: K.39`
8			`-- \ \ Application: netgen`
9			`-- / / Filename: dist_mem_64x8.vhd`
10			`-- /___/ /\ Timestamp: Sat Feb 12 17:26:42 2011`
11			`-- \ \ / \`
12			`-- \___\/\___\`
13			`--`
14			`-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.vhd"`
15			`-- Device : 5vsx95tff1136-1`
16			`-- Input file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.ngc`
17			`-- Output file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.vhd`
18			`-- # of Entities : 1`
19			`-- Design Name : dist_mem_64x8`
20			`-- Xilinx : C:\Xilinx\10.1\ISE`
21			`--`
22			`-- Purpose:`
23			`-- This VHDL netlist is a verification model and uses simulation`
24			`-- primitives which may not represent the true implementation of the`
25			`-- device, however the netlist is functionally correct and should not`
26			`-- be modified. This file cannot be synthesized and should only be used`
27			`-- with supported simulation tools.`
28			`--`
29			`-- Reference:`
30			`-- Development System Reference Guide, Chapter 23`
31			`-- Synthesis and Simulation Design Guide, Chapter 6`
32			`--`
33			`--------------------------------------------------------------------------------`
34
35
36			`-- synthesis translate_off`
37			`library IEEE;`
38			`use IEEE.STD_LOGIC_1164.ALL;`
39			`library UNISIM;`
40			`use UNISIM.VCOMPONENTS.ALL;`
41			`use UNISIM.VPKG.ALL;`
42
43			`entity dist_mem_64x8 is`
44			`port (`
45			`clk : in STD_LOGIC := 'X';`
46			`we : in STD_LOGIC := 'X';`
47			`a : in STD_LOGIC_VECTOR ( 5 downto 0 );`
48			`d : in STD_LOGIC_VECTOR ( 7 downto 0 );`
49			`qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )`
50			`);`
51			`end dist_mem_64x8;`
52
53			`architecture STRUCTURE of dist_mem_64x8 is`
54			`signal N0 : STD_LOGIC;`
55			`signal N1 : STD_LOGIC;`
56			`signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );`
57			`signal d_3 : STD_LOGIC_VECTOR ( 7 downto 0 );`
58			`signal qspo_4 : STD_LOGIC_VECTOR ( 7 downto 0 );`
59			`signal BU2_U0_gen_sp_ram_spram_inst_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 );`
60			`signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );`
61			`begin`
62			`a_2(5) <= a(5);`
63			`a_2(4) <= a(4);`
64			`a_2(3) <= a(3);`
65			`a_2(2) <= a(2);`
66			`a_2(1) <= a(1);`
67			`a_2(0) <= a(0);`
68			`d_3(7) <= d(7);`
69			`d_3(6) <= d(6);`
70			`d_3(5) <= d(5);`
71			`d_3(4) <= d(4);`
72			`d_3(3) <= d(3);`
73			`d_3(2) <= d(2);`
74			`d_3(1) <= d(1);`
75			`d_3(0) <= d(0);`
76			`qspo(7) <= qspo_4(7);`
77			`qspo(6) <= qspo_4(6);`
78			`qspo(5) <= qspo_4(5);`
79			`qspo(4) <= qspo_4(4);`
80			`qspo(3) <= qspo_4(3);`
81			`qspo(2) <= qspo_4(2);`
82			`qspo(1) <= qspo_4(1);`
83			`qspo(0) <= qspo_4(0);`
84			`VCC_0 : VCC`
85			`port map (`
86			`P => N1`
87			`);`
88			`GND_1 : GND`
89			`port map (`
90			`G => N0`
91			`);`
92			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram8 : RAM64X1S`
93			`generic map(`
94			`INIT => X"0000000000000000"`
95			`)`
96			`port map (`
97			`A0 => a_2(0),`
98			`A1 => a_2(1),`
99			`A2 => a_2(2),`
100			`A3 => a_2(3),`
101			`A4 => a_2(4),`
102			`A5 => a_2(5),`
103			`D => d_3(7),`
104			`WCLK => clk,`
105			`WE => we,`
106			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(7)`
107			`);`
108			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram7 : RAM64X1S`
109			`generic map(`
110			`INIT => X"0000000000504000"`
111			`)`
112			`port map (`
113			`A0 => a_2(0),`
114			`A1 => a_2(1),`
115			`A2 => a_2(2),`
116			`A3 => a_2(3),`
117			`A4 => a_2(4),`
118			`A5 => a_2(5),`
119			`D => d_3(6),`
120			`WCLK => clk,`
121			`WE => we,`
122			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(6)`
123			`);`
124			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram6 : RAM64X1S`
125			`generic map(`
126			`INIT => X"0000000000010000"`
127			`)`
128			`port map (`
129			`A0 => a_2(0),`
130			`A1 => a_2(1),`
131			`A2 => a_2(2),`
132			`A3 => a_2(3),`
133			`A4 => a_2(4),`
134			`A5 => a_2(5),`
135			`D => d_3(5),`
136			`WCLK => clk,`
137			`WE => we,`
138			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(5)`
139			`);`
140			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram5 : RAM64X1S`
141			`generic map(`
142			`INIT => X"0000000000800000"`
143			`)`
144			`port map (`
145			`A0 => a_2(0),`
146			`A1 => a_2(1),`
147			`A2 => a_2(2),`
148			`A3 => a_2(3),`
149			`A4 => a_2(4),`
150			`A5 => a_2(5),`
151			`D => d_3(4),`
152			`WCLK => clk,`
153			`WE => we,`
154			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(4)`
155			`);`
156			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram4 : RAM64X1S`
157			`generic map(`
158			`INIT => X"0000000000001000"`
159			`)`
160			`port map (`
161			`A0 => a_2(0),`
162			`A1 => a_2(1),`
163			`A2 => a_2(2),`
164			`A3 => a_2(3),`
165			`A4 => a_2(4),`
166			`A5 => a_2(5),`
167			`D => d_3(3),`
168			`WCLK => clk,`
169			`WE => we,`
170			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(3)`
171			`);`
172			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram3 : RAM64X1S`
173			`generic map(`
174			`INIT => X"0000000000014000"`
175			`)`
176			`port map (`
177			`A0 => a_2(0),`
178			`A1 => a_2(1),`
179			`A2 => a_2(2),`
180			`A3 => a_2(3),`
181			`A4 => a_2(4),`
182			`A5 => a_2(5),`
183			`D => d_3(2),`
184			`WCLK => clk,`
185			`WE => we,`
186			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(2)`
187			`);`
188			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram2 : RAM64X1S`
189			`generic map(`
190			`INIT => X"0000000000000000"`
191			`)`
192			`port map (`
193			`A0 => a_2(0),`
194			`A1 => a_2(1),`
195			`A2 => a_2(2),`
196			`A3 => a_2(3),`
197			`A4 => a_2(4),`
198			`A5 => a_2(5),`
199			`D => d_3(1),`
200			`WCLK => clk,`
201			`WE => we,`
202			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(1)`
203			`);`
204			`BU2_U0_gen_sp_ram_spram_inst_Mram_ram1 : RAM64X1S`
205			`generic map(`
206			`INIT => X"0000000000804000"`
207			`)`
208			`port map (`
209			`A0 => a_2(0),`
210			`A1 => a_2(1),`
211			`A2 => a_2(2),`
212			`A3 => a_2(3),`
213			`A4 => a_2(4),`
214			`A5 => a_2(5),`
215			`D => d_3(0),`
216			`WCLK => clk,`
217			`WE => we,`
218			`O => BU2_U0_gen_sp_ram_spram_inst_spo_int(0)`
219			`);`
220			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_7 : FD`
221			`generic map(`
222			`INIT => '0'`
223			`)`
224			`port map (`
225			`C => clk,`
226			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(7),`
227			`Q => qspo_4(7)`
228			`);`
229			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_6 : FD`
230			`generic map(`
231			`INIT => '0'`
232			`)`
233			`port map (`
234			`C => clk,`
235			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(6),`
236			`Q => qspo_4(6)`
237			`);`
238			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_5 : FD`
239			`generic map(`
240			`INIT => '0'`
241			`)`
242			`port map (`
243			`C => clk,`
244			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(5),`
245			`Q => qspo_4(5)`
246			`);`
247			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_4 : FD`
248			`generic map(`
249			`INIT => '0'`
250			`)`
251			`port map (`
252			`C => clk,`
253			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(4),`
254			`Q => qspo_4(4)`
255			`);`
256			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_3 : FD`
257			`generic map(`
258			`INIT => '0'`
259			`)`
260			`port map (`
261			`C => clk,`
262			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(3),`
263			`Q => qspo_4(3)`
264			`);`
265			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_2 : FD`
266			`generic map(`
267			`INIT => '0'`
268			`)`
269			`port map (`
270			`C => clk,`
271			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(2),`
272			`Q => qspo_4(2)`
273			`);`
274			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_1 : FD`
275			`generic map(`
276			`INIT => '0'`
277			`)`
278			`port map (`
279			`C => clk,`
280			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(1),`
281			`Q => qspo_4(1)`
282			`);`
283			`BU2_U0_gen_sp_ram_spram_inst_qspo_int_0 : FD`
284			`generic map(`
285			`INIT => '0'`
286			`)`
287			`port map (`
288			`C => clk,`
289			`D => BU2_U0_gen_sp_ram_spram_inst_spo_int(0),`
290			`Q => qspo_4(0)`
291			`);`
292			`BU2_XST_GND : GND`
293			`port map (`
294			`G => BU2_qdpo(0)`
295			`);`
296
297			`end STRUCTURE;`
298
299			`-- synthesis translate_on`