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<!--# include virtual="/ssi/ssi_start.shtml" -->
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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<p><table align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top">
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<tbody><tr bgcolor=#bbccff> <td align=center valign=center>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a> |
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<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a> |
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<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a> |
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<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a> |
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<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a> |
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<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a> |
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<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a> |
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<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a> |
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<a href="http://www.opencores.org/cores/pci/references.shtml">References</a> |
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<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a> |
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<a href="mailto:pci@opencores.org">Mailing list</a> |
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<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>
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</td></tr></tbody>
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</table>
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<table border=0 cellPadding=0 cellSpacing=0 width="100%">
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<tbody><tr><td>
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<p><center><font color="#bf0000" size=+3><b>Documentation</b></font></center>
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</p></td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Summary<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>
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The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI
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local bus. It consists of two independent units, one handling transactions originating on the
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PCI bus, the other one handling transactions originating on the WISHBONE bus.
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<br><br>
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The core has been designed to offer as much flexibility as possible to all kinds of applications.
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The following lists the main features of the PCI IP core:
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<br><br>
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<ul>
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<li type=circle>32-bit PCI interface
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<li type=circle>Fully PCI 2.2 compliant (with 66 MHz PCI specification)
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<li type=circle>Separated initiator and target functional blocks
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<li type=circle>Supported initiator commands and functions:
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<li type=disc> Memory Read, Memory Write
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<li type=disc> Memory Read Multiple (MRM)
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<li type=disc> Memory Read Line (MRL)
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<li type=disc> I/O Read, I/O Write
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<li type=disc> Configuration Read, Configuration Write
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<li type=disc> Bus Parking
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<li type=disc> Interrupt Acknowledge
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<li type=disc> Host Bridging
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<li type=circle>Supported target commands and functions:
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<li type=disc> Type 0 Configuration Space Header<br>
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(Type 0 is used to configure agents on the same bus segment)<br>
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(Type 1 is used to configure across PCI-to-PCI bridges)
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<li type=disc> Parity Generation (PAR), Parity Error Detection (PERR# and SERR#)
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<li type=disc> Memory Read, Memory Write
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<li type=disc> Memory Read Multiple (MRM)
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<li type=disc> Memory Read Line (MRL)
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<li type=disc> Memory Write and Invalidate (MWI)
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<li type=disc> I/O Read, I/O Write
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<li type=disc> Configuration Read, Configuration Write
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<li type=disc> Target Abort, Target Retry, Target Disconnect
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<li type=disc> Full Command/Status registers
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<li type=circle>WISHBONE SoC Interconnection Rev. B compliant interface on processor side (master with Target PCI and slave with Initiator PCI interface)
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<li type=circle>Configurable on-chip FIFOs
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</ul>
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<br><br>
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A detailed PCI IP Core Spcification is available on the following link:<br>
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<h3><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/pci/doc/pci_specification.pdf">PCI
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Bridge IP Core Specification, Rev 0.5</a> (616 kB) PDF document</h3>
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<br><br>
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</font>
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</td></tr>
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</table><!--# include virtual="/ssi/ssi_end.shtml" -->
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