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peio |
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--| |
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--| Fileo: pciwbsequ.vhd |
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--| |
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--| Project: pci32tLite |
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--| |
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--| Description: FSM controling pci to whisbone transactions. |
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--| |
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--+-------------------------------------------------------------------------------------------------+
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--+-----------------------------------------------------------------+
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--| |
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--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
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--| |
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--| This source file may be used and distributed without |
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--| restriction provided that this copyright statement is not |
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--| removed from the file and that any derivative work contains |
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--| the original copyright notice and the associated disclaimer. |
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--| |
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--| This source file is free software; you can redistribute it |
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--| and/or modify it under the terms of the GNU Lesser General |
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--| Public License as published by the Free Software Foundation; |
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--| either version 2.1 of the License, or (at your option) any |
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--| later version. |
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--| |
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--| This source is distributed in the hope that it will be |
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--| useful, but WITHOUT ANY WARRANTY; without even the implied |
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--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
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--| PURPOSE. See the GNU Lesser General Public License for more |
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--| details. |
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--| |
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--| You should have received a copy of the GNU Lesser General |
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--| Public License along with this source; if not, download it |
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--| from http://www.opencores.org/lgpl.shtml |
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--| |
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--+-----------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| LIBRARIES |
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--+-----------------------------------------------------------------------------+
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library ieee;
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use ieee.std_logic_1164.all;
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library onalib;
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use onalib.onapackage.all;
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--+-----------------------------------------------------------------------------+
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--| ENTITY |
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--+-----------------------------------------------------------------------------+
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entity pciwbsequ is
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generic (
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BARS : string := "1BARMEM";
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WBSIZE : integer := 16;
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WBENDIAN : string := "BIG"
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);
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port (
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-- General
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clk_i : in std_logic;
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rst_i : in std_logic;
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-- pci
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cmd_i : in std_logic_vector(3 downto 0);
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cbe_i : in std_logic_vector(3 downto 0);
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frame_i : in std_logic;
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irdy_i : in std_logic;
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devsel_o : out std_logic;
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trdy_o : out std_logic;
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stop_o : out std_logic;
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-- control
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adrcfg_i : in std_logic;
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adrmem_i : in std_logic;
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pciadrLD_o : out std_logic;
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pcidOE_o : out std_logic;
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parOE_o : out std_logic;
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wbdatLD_o : out std_logic;
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wrcfg_o : out std_logic;
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rdcfg_o : out std_logic;
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-- whisbone
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wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
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wb_we_o : out std_logic;
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wb_stb_o : out std_logic;
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wb_cyc_o : out std_logic;
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wb_ack_i : in std_logic;
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wb_rty_i : in std_logic;
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wb_err_i : in std_logic
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);
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end pciwbsequ;
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architecture rtl of pciwbsequ is
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--+-----------------------------------------------------------------------------+
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--| COMPONENTS |
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--+-----------------------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| CONSTANTS |
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--+-----------------------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| SIGNALS |
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--+-----------------------------------------------------------------------------+
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type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, BACKOFF, TURN_ARL, TURN_ARE );
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signal pst_pci : PciFSM;
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signal nxt_pci : PciFSM;
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signal bbusy : std_logic;
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signal idle : std_logic;
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signal sdata1 : std_logic;
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signal sdata2 : std_logic;
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signal sdata1NX : std_logic;
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signal sdata2NX : std_logic;
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signal turnarlNX : std_logic;
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signal turnarl : std_logic;
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signal devselNX_n : std_logic;
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signal trdyNX_n : std_logic;
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signal stopNx_n : std_logic;
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signal devsel : std_logic;
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signal trdy : std_logic;
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signal stop : std_logic;
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signal adrpci : std_logic;
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signal acking : std_logic;
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signal retrying : std_logic;
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signal rdcfg : std_logic;
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signal targOE : std_logic;
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signal pcidOE : std_logic;
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signal pcidOE_s : std_logic;
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begin
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--+-------------------------------------------------------------------------+
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--| PCI-Whisbone Sequencer |
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--+-------------------------------------------------------------------------+
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--+-------------------------------------------------------------+
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--| FSM PCI-Whisbone |
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--+-------------------------------------------------------------+
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PCIFSM_CLOCKED: process( rst_i, clk_i, nxt_pci )
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begin
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if( rst_i = '1' ) then
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pst_pci <= PCIIDLE;
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elsif( rising_edge(clk_i) ) then
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pst_pci <= nxt_pci;
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end if;
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end process PCIFSM_CLOCKED;
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PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking, retrying )
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begin
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devselNX_n <= '1';
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trdyNX_n <= '1';
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stopNX_n <= '1';
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case pst_pci is
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when PCIIDLE =>
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if ( frame_i = '0' ) then
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nxt_pci <= B_BUSY;
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else
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nxt_pci <= PCIIDLE;
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end if;
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when B_BUSY =>
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if ( adrpci = '0' ) then
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nxt_pci <= TURN_ARE;
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else
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nxt_pci <= S_DATA1;
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devselNX_n <= '0';
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end if;
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when S_DATA1 =>
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if (acking = '1') then
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if (frame_i = '0') then
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stopNX_n <= '0';
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end if;
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nxt_pci <= S_DATA2;
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devselNX_n <= '0';
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trdyNX_n <= '0';
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elsif (retrying = '1') then
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nxt_pci <= BACKOFF;
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devselNX_n <= '0';
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stopNX_n <= '0';
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else
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nxt_pci <= S_DATA1;
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devselNX_n <= '0';
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end if;
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when S_DATA2 =>
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nxt_pci <= TURN_ARL;
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when BACKOFF =>
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if ( frame_i = '1' and irdy_i = '0' ) then
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nxt_pci <= TURN_ARL;
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else
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nxt_pci <= BACKOFF;
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devselNX_n <= '0';
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stopNX_n <= '0';
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end if;
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when TURN_ARL =>
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if (frame_i = '0') then
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nxt_pci <= B_BUSY;
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else
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nxt_pci <= PCIIDLE;
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end if;
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when TURN_ARE =>
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if (frame_i = '0') then
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nxt_pci <= TURN_ARE;
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else
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nxt_pci <= PCIIDLE;
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end if;
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end case;
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end process PCIFSM_COMB;
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--+-------------------------------------------------------------+
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--| FSM control signals |
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--+-------------------------------------------------------------+
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adrpci <= adrmem_i or adrcfg_i;
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acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and irdy_i = '0')
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else '0';
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retrying <= '1' when ( wb_rty_i = '1' ) else '0';
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--+-------------------------------------------------------------+
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--| FSM derived Control signals |
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--+-------------------------------------------------------------+
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idle <= '1' when ( pst_pci = PCIIDLE ) else '0';
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bbusy <= '1' when ( pst_pci = B_BUSY ) else '0';
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sdata1 <= '1' when ( pst_pci = S_DATA1 ) else '0';
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sdata2 <= '1' when ( pst_pci = S_DATA2 ) else '0';
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--turnar <= '1' when ( pst_pci = TURN_AR ) else '0';
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turnarl <= '1' when ( pst_pci = TURN_ARL ) else '0';
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sdata1NX <= '1' when ( nxt_pci = S_DATA1 ) else '0';
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sdata2NX <= '1' when ( nxt_pci = S_DATA2 ) else '0';
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--turnarNX <= '1' when ( nxt_pci = TURN_AR ) else '0';
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turnarlNX <= '1' when ( nxt_pci = TURN_ARL ) else '0';
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--+-------------------------------------------------------------+
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--| PCI Data Output Enable |
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--+-------------------------------------------------------------+
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PCIDOE_P: process( rst_i, clk_i, cmd_i(0), sdata1NX, turnarlNX )
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begin
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if ( rst_i = '1' ) then
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pcidOE <= '0';
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elsif ( rising_edge(clk_i) ) then
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if ( sdata1NX = '1' and cmd_i(0) = '0' ) then
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pcidOE <= '1';
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elsif ( turnarlNX = '1' ) then
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pcidOE <= '0';
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end if;
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end if;
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end process PCIDOE_P;
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pcidOE_o <= pcidOE;
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--+-------------------------------------------------------------+
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--| PAR Output Enable |
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--| PCI Read data phase |
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--| PAR is valid 1 cicle after data is valid |
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--+-------------------------------------------------------------+
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uu1: syncl port map ( clk => clk_i, rst => rst_i, d => pcidOE, q => pcidOE_s );
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parOE_o <= pcidOE_s;
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--+-------------------------------------------------------------+
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--| Target s/t/s signals OE control |
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--+-------------------------------------------------------------+
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TARGOE_P: process( rst_i, clk_i, sdata1NX, turnarl )
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begin
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if ( rst_i = '1' ) then
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targOE <= '0';
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elsif ( rising_edge(clk_i) ) then
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if ( sdata1NX = '1' ) then
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targOE <= '1';
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elsif ( turnarl = '1' ) then
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targOE <= '0';
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end if;
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end if;
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end process TARGOE_P;
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--+-------------------------------------------------------------------------+
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--| WHISBONE outs |
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--+-------------------------------------------------------------------------+
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cyc_p: process(rst_i, clk_i, adrmem_i, bbusy, acking, retrying, frame_i)
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begin
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if ( rst_i = '1' ) then
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wb_cyc_o <= '0';
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elsif ( rising_edge(clk_i) ) then
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if (adrmem_i = '1' and bbusy = '1' ) then
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wb_cyc_o <= '1';
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elsif ((acking = '1' or retrying = '1') and frame_i = '1') then
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wb_cyc_o <= '0';
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end if;
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end if;
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end process cyc_p;
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wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0';
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wb_we_o <= cmd_i(0);
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--+-----------------------------------------+
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--| wb_sel_o generation depending on WBSIZE |
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--| and WBENDIAN "generics" configuration |
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--+-----------------------------------------+
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sel32: if (WBSIZE = 32) generate
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wb_sel_o(3) <= not cbe_i(3);
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wb_sel_o(2) <= not cbe_i(2);
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wb_sel_o(1) <= not cbe_i(1);
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wb_sel_o(0) <= not cbe_i(0);
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end generate;
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sel16b: if (WBSIZE = 16 and WBENDIAN = "BIG") generate
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wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2));
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wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3));
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end generate;
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sel16l: if (WBSIZE = 16 and WBENDIAN = "LITTLE") generate
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wb_sel_o(1) <= (not cbe_i(1)) or (not cbe_i(3));
|
| 341 |
|
|
wb_sel_o(0) <= (not cbe_i(0)) or (not cbe_i(2));
|
| 342 |
|
|
end generate;
|
| 343 |
|
|
|
| 344 |
|
|
sel8: if (WBSIZE = 8) generate
|
| 345 |
|
|
wb_sel_o(0) <= not (cbe_i(0) and cbe_i(1) and cbe_i(2) and cbe_i(3));
|
| 346 |
|
|
end generate;
|
| 347 |
|
|
|
| 348 |
|
|
|
| 349 |
|
|
--+-------------------------------------------------------------------------+
|
| 350 |
|
|
--| Syncronized PCI outs |
|
| 351 |
|
|
--+-------------------------------------------------------------------------+
|
| 352 |
|
|
|
| 353 |
|
|
PCISIG: process( rst_i, clk_i, devselNX_n, trdyNX_n, stopNX_n)
|
| 354 |
|
|
begin
|
| 355 |
|
|
if( rst_i = '1' ) then
|
| 356 |
|
|
devsel <= '1';
|
| 357 |
|
|
trdy <= '1';
|
| 358 |
|
|
stop <= '1';
|
| 359 |
|
|
elsif( rising_edge(clk_i) ) then
|
| 360 |
|
|
devsel <= devselNX_n;
|
| 361 |
|
|
trdy <= trdyNX_n;
|
| 362 |
|
|
stop <= stopNX_n;
|
| 363 |
|
|
end if;
|
| 364 |
|
|
end process PCISIG;
|
| 365 |
|
|
|
| 366 |
|
|
devsel_o <= devsel when ( targOE = '1' ) else 'Z';
|
| 367 |
|
|
trdy_o <= trdy when ( targOE = '1' ) else 'Z';
|
| 368 |
|
|
stop_o <= stop when ( targOE = '1' ) else 'Z';
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
|
|
--+-------------------------------------------------------------------------+
|
| 372 |
|
|
--| Other outs |
|
| 373 |
|
|
--+-------------------------------------------------------------------------+
|
| 374 |
|
|
|
| 375 |
|
|
-- rd/wr Configuration Space Registers
|
| 376 |
|
|
wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0';
|
| 377 |
|
|
rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0';
|
| 378 |
|
|
rdcfg_o <= rdcfg;
|
| 379 |
|
|
|
| 380 |
|
|
-- LoaD enable signals
|
| 381 |
|
|
--pciadrLD_o <= '1' when(frame_i = '0' and idle = '1') else '0';
|
| 382 |
|
|
-- added turnarl to support Fast Back to Back
|
| 383 |
|
|
pciadrLD_o <= '1' when(frame_i = '0' and (idle = '1' or turnarl = '1')) else '0';
|
| 384 |
|
|
wbdatLD_o <= wb_ack_i;
|
| 385 |
|
|
|
| 386 |
|
|
end rtl;
|
