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dsmv |
-------------------------------------------------------------------------------
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--
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-- Title : ctrl_ram_cmd
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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53 |
dsmv |
-- Version : 1.5
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2 |
dsmv |
--
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-------------------------------------------------------------------------------
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--
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-- Description : Узел управления памятью
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--
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-------------------------------------------------------------------------------
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--
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53 |
dsmv |
-- Version 1.5 07.03.2016
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-- Исправлено формирование ram_adrb при is_dsp48=0
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--
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-------------------------------------------------------------------------------
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--
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2 |
dsmv |
-- Version 1.4 09.04.2012
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-- Исправлено формирование
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-- ch0_next_block, ch1_next_block
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.3 06.12.2011
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-- Добавлен local_adr_we
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.2 05.04.2010
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-- Добавлен параметр is_dsp48 - разрешение использования
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-- блоков DSP48
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.1 02.09.2009
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-- Исправлен сброс ch1_adr_hi
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package ctrl_ram_cmd_pkg is
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component ctrl_ram_cmd is
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generic(
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is_dsp48 : in integer:=1 -- 1 - использовать DSP48, 0 - не использовать DSP48
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);
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port(
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---- Global ----
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reset : in std_logic; -- 0 - сброс
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clk : in std_logic; --! Тактовая частота ядра - 250 МГц
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aclk : in std_logic; --! Тактовая частота локальной шины - 266 МГц
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---- Picoblaze ----
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dma_chn : in std_logic; -- номер канала DMA
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reg_ch0_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_ch1_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_write_E0 : in std_logic; -- 1 - смена блока памяти
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dma0_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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dma1_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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loc_adr_we : in std_logic; -- 1 - запись локального адреса
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---- PLB_BUS ----
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dmar0 : in std_logic; -- 1 - запрос DMA 0
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dmar1 : in std_logic; -- 1 - запрос DMA 1
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request_wr : out std_logic; --! 1 - запрос на запись в регистр
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request_rd : out std_logic; --! 1 - запрос на чтение из регистра
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allow_wr : in std_logic; --! 1 - разрешение записи
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pb_complete : in std_logic; --! 1 - завершение обмена по шине PLD_BUS
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pf_repack_we : in std_logic; -- 1 - запись в память
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pf_ram_rd_out : out std_logic; -- 1 - чтение из памяти
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---- Память ----
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ram_adra_a9 : out std_logic; -- разряд 9 адреса памяти
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ram_adrb : out std_logic_vector( 10 downto 0 )
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);
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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use work.ctrl_ram_cmd_pb_pkg.all;
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entity ctrl_ram_cmd is
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generic(
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is_dsp48 : in integer:=1 -- 1 - использовать DSP48, 0 - не использовать DSP48
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);
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port(
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---- Global ----
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reset : in std_logic; -- 0 - сброс
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clk : in std_logic; --! Тактовая частота ядра - 250 МГц
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aclk : in std_logic; --! Тактовая частота локальной шины - 266 МГц
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---- Picoblaze ----
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dma_chn : in std_logic; -- номер канала DMA
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reg_ch0_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_ch1_ctrl : in std_logic_vector( 7 downto 0 ); -- регистр управления
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reg_write_E0 : in std_logic; -- 1 - смена блока памяти
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dma0_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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dma1_transfer_rdy : out std_logic; -- 1 - блок памяти готов к обмену
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loc_adr_we : in std_logic; -- 1 - запись локального адреса
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---- PLB_BUS ----
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dmar0 : in std_logic; -- 1 - запрос DMA 0
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dmar1 : in std_logic; -- 1 - запрос DMA 1
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request_wr : out std_logic; --! 1 - запрос на запись в регистр
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request_rd : out std_logic; --! 1 - запрос на чтение из регистра
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allow_wr : in std_logic; --! 1 - разрешение записи
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pb_complete : in std_logic; --! 1 - завершение обмена по шине PLD_BUS
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pf_repack_we : in std_logic; -- 1 - запись в память
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pf_ram_rd_out : out std_logic; -- 1 - чтение из памяти
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---- Память ----
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ram_adra_a9 : out std_logic; -- разряд 9 адреса памяти
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ram_adrb : out std_logic_vector( 10 downto 0 )
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);
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end ctrl_ram_cmd;
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architecture ctrl_ram_cmd of ctrl_ram_cmd is
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signal pb_current_block: std_logic_vector( 1 downto 0 );
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signal flag_data : std_logic_vector( 3 downto 0 );
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signal cb : std_logic;
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signal pb_flag_set : std_logic_vector( 3 downto 0 );
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signal pb_flag_clr : std_logic_vector( 3 downto 0 );
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signal pf_flag_set : std_logic_vector( 3 downto 0 );
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signal pf_flag_clr : std_logic_vector( 3 downto 0 );
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signal pb_fclr : std_logic;
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signal pb_fset : std_logic;
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signal reg_write_E0_z : std_logic;
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signal reg_write_E0_z1 : std_logic;
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signal pf_chn : std_logic;
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signal pf0_act : std_logic;
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signal pf0_rdy : std_logic;
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signal pf1_act : std_logic;
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signal pf1_rdy : std_logic;
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type stp_type is ( s0, s1, s2, s3 );
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signal stp : stp_type;
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signal rst_p : std_logic;
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signal rst_p0 : std_logic;
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signal pf0_cb : std_logic;
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signal pf0_dma_wr_rdy : std_logic;
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signal pf0_dma_rd_rdy : std_logic;
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signal pf1_cb : std_logic;
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signal pf1_dma_wr_rdy : std_logic;
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signal pf1_dma_rd_rdy : std_logic;
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signal ram0_transfer_rdy : std_logic;
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signal ram1_transfer_rdy : std_logic;
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signal port_a : std_logic_vector( 17 downto 0 );
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signal port_b : std_logic_vector( 17 downto 0 );
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signal port_c : std_logic_vector( 47 downto 0 );
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signal port_p : std_logic_vector( 47 downto 0 );
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signal opmode : std_logic_vector( 6 downto 0 );
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signal carry : std_logic;
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signal cnt_rstp : std_logic;
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signal ch0_adr_hi : std_logic_vector( 1 downto 0 );
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signal ch1_adr_hi : std_logic_vector( 1 downto 0 );
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signal ch0_next_block : std_logic;
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signal ch1_next_block : std_logic;
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signal ch0_adr_hi_wr : std_logic;
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signal ch1_adr_hi_wr : std_logic;
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signal pf_ram_rd : std_logic;
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signal pf_dma_wr_rdy : std_logic;
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signal pf_dma_rd_rdy : std_logic;
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signal pf_stop_rd : std_logic;
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signal loc_adr_ch0_we : std_logic;
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signal loc_adr_ch1_we : std_logic;
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begin
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cb <= pb_current_block( conv_integer( dma_chn ) );
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ram_adra_a9 <= cb;
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reg_write_E0_z <= reg_write_E0 after 1 ns when rising_edge( clk );
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reg_write_E0_z1 <= reg_write_E0_z after 1 ns when rising_edge( clk );
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pb_flag_clr(0) <= reg_ch0_ctrl(4) or ( reg_write_E0_z and reg_ch0_ctrl(2) and not dma_chn and not pb_current_block(0) ) after 1 ns when rising_edge( clk );
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pb_flag_clr(1) <= reg_ch0_ctrl(4) or ( reg_write_E0_z and reg_ch0_ctrl(2) and not dma_chn and pb_current_block(0) ) after 1 ns when rising_edge( clk );
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pb_flag_clr(2) <= reg_ch1_ctrl(4) or ( reg_write_E0_z and reg_ch1_ctrl(2) and dma_chn and not pb_current_block(1) ) after 1 ns when rising_edge( clk );
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pb_flag_clr(3) <= reg_ch1_ctrl(4) or ( reg_write_E0_z and reg_ch1_ctrl(2) and dma_chn and pb_current_block(1) ) after 1 ns when rising_edge( clk );
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pb_flag_set(0) <= reg_write_E0_z and not reg_ch0_ctrl(2) and not dma_chn and not pb_current_block(0) after 1 ns when rising_edge( clk );
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pb_flag_set(1) <= reg_write_E0_z and not reg_ch0_ctrl(2) and not dma_chn and pb_current_block(0) after 1 ns when rising_edge( clk );
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pb_flag_set(2) <= reg_write_E0_z and not reg_ch1_ctrl(2) and dma_chn and not pb_current_block(1) after 1 ns when rising_edge( clk );
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pb_flag_set(3) <= reg_write_E0_z and not reg_ch1_ctrl(2) and dma_chn and pb_current_block(1) after 1 ns when rising_edge( clk );
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pr_current_block0: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch0_ctrl(4)='1' ) then
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pb_current_block(0) <= '0' after 1 ns;
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elsif( reg_write_E0_z1='1' and dma_chn='0' ) then
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pb_current_block(0) <= not pb_current_block(0) after 1 ns;
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end if;
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end if;
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end process;
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pr_current_block1: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch1_ctrl(4)='1' ) then
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pb_current_block(1) <= '0' after 1 ns;
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elsif( reg_write_E0_z1='1' and dma_chn='1' ) then
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pb_current_block(1) <= not pb_current_block(1) after 1 ns;
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end if;
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end if;
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end process;
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gen_flag: for ii in 0 to 3 generate
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process( clk ) begin
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if( rising_edge( clk ) ) then
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if( pb_flag_clr(ii)='1' or pf_flag_clr(ii)='1' or rst_p='1' ) then
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flag_data(ii) <= '0' after 1 ns;
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elsif( pb_flag_set(ii)='1' or pf_flag_set(ii)='1' ) then
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flag_data(ii) <= '1' after 1 ns;
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end if;
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end if;
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end process;
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end generate;
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---- Формирование готовности блока к обмену ----
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pr0_transfer_rdy: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch0_ctrl(2)='1' and flag_data( conv_integer(pb_current_block(0)) )='1' ) then
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ram0_transfer_rdy <= reg_ch0_ctrl(0) and not reg_ch0_ctrl(3) after 1 ns;
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elsif( reg_ch0_ctrl(2)='0' and flag_data( conv_integer(pb_current_block(0)) )='0' ) then
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ram0_transfer_rdy <= reg_ch0_ctrl(0) and not reg_ch0_ctrl(3) after 1 ns;
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else
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ram0_transfer_rdy <= '0' after 1 ns;
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end if;
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end if;
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end process;
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pr1_transfer_rdy: process( clk ) begin
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if( rising_edge( clk ) ) then
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if( reg_ch1_ctrl(2)='1' and flag_data( 2+conv_integer(pb_current_block(1)) )='1' ) then
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ram1_transfer_rdy <= reg_ch1_ctrl(0) and not reg_ch1_ctrl(3) after 1 ns;
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elsif( reg_ch1_ctrl(2)='0' and flag_data( 2+conv_integer(pb_current_block(1)) )='0' ) then
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ram1_transfer_rdy <= reg_ch1_ctrl(0) and not reg_ch1_ctrl(3) after 1 ns;
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else
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ram1_transfer_rdy <= '0' after 1 ns;
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end if;
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end if;
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end process;
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dma0_transfer_rdy <= ram0_transfer_rdy;
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dma1_transfer_rdy <= ram1_transfer_rdy;
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--ram_transfer_rdy <= (ram0_transfer_rdy and not dma_chn) or (ram1_transfer_rdy and dma_chn) after 1 ns
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-- when rising_edge( clk );
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| 297 |
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---- Перебор каналов DMA ----
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|
|
rst_p0 <= not reset after 1 ns when rising_edge( aclk );
|
| 300 |
|
|
rst_p <= rst_p0 after 1 ns when rising_edge( aclk );
|
| 301 |
|
|
|
| 302 |
|
|
pr_state: process( aclk ) begin
|
| 303 |
|
|
if( rising_edge( aclk ) ) then
|
| 304 |
|
|
|
| 305 |
|
|
case( stp ) is
|
| 306 |
|
|
when s0 =>
|
| 307 |
|
|
cnt_rstp <= '0' after 1 ns;
|
| 308 |
|
|
pf_chn <= '0' after 1 ns;
|
| 309 |
|
|
pf0_act <= '1' after 1 ns;
|
| 310 |
|
|
pf1_act <= '0' after 1 ns;
|
| 311 |
|
|
if( pf0_rdy='1' ) then
|
| 312 |
|
|
stp <= s1 after 1 ns;
|
| 313 |
|
|
end if;
|
| 314 |
|
|
|
| 315 |
|
|
when s1 =>
|
| 316 |
|
|
cnt_rstp <= '1' after 1 ns;
|
| 317 |
|
|
pf0_act <= '0' after 1 ns;
|
| 318 |
|
|
if( pf0_rdy='0' ) then
|
| 319 |
|
|
stp <= s2 after 1 ns;
|
| 320 |
|
|
end if;
|
| 321 |
|
|
|
| 322 |
|
|
when s2 =>
|
| 323 |
|
|
cnt_rstp <= '0' after 1 ns;
|
| 324 |
|
|
pf_chn <= '1' after 1 ns;
|
| 325 |
|
|
pf1_act <= '1' after 1 ns;
|
| 326 |
|
|
if( pf1_rdy='1' ) then
|
| 327 |
|
|
stp <= s3 after 1 ns;
|
| 328 |
|
|
end if;
|
| 329 |
|
|
|
| 330 |
|
|
when s3 =>
|
| 331 |
|
|
cnt_rstp <= '1' after 1 ns;
|
| 332 |
|
|
pf1_act <= '0' after 1 ns;
|
| 333 |
|
|
if( pf1_rdy='0' ) then
|
| 334 |
|
|
stp <= s0 after 1 ns;
|
| 335 |
|
|
end if;
|
| 336 |
|
|
|
| 337 |
|
|
end case;
|
| 338 |
|
|
|
| 339 |
|
|
if( rst_p='1' ) then
|
| 340 |
|
|
stp <= s0 after 1 ns;
|
| 341 |
|
|
pf0_act <= '0' after 1 ns;
|
| 342 |
|
|
cnt_rstp <= '1' after 1 ns;
|
| 343 |
|
|
|
| 344 |
|
|
end if;
|
| 345 |
|
|
|
| 346 |
|
|
end if;
|
| 347 |
|
|
end process;
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
|
| 351 |
|
|
cmd0: ctrl_ram_cmd_pb
|
| 352 |
|
|
port map(
|
| 353 |
|
|
---- Global ----
|
| 354 |
|
|
reset => reset, -- 0 - сброс
|
| 355 |
|
|
clk => clk, -- тактовая частота 250 МГц
|
| 356 |
|
|
aclk => aclk, -- тактовая частота 266 МГц
|
| 357 |
|
|
|
| 358 |
|
|
act => pf0_act, -- 1 - разрешение цикла обработки
|
| 359 |
|
|
rdy => pf0_rdy, -- 1 - завершение цикла обработки
|
| 360 |
|
|
|
| 361 |
|
|
loc_adr_we => loc_adr_ch0_we, -- 1 - запись локального адреса
|
| 362 |
|
|
flag_data => flag_data( 1 downto 0 ), -- 1 - наличие данных в блоке
|
| 363 |
|
|
|
| 364 |
|
|
flag_set => pf_flag_set( 1 downto 0 ), -- 1 - установка флага наличия данных
|
| 365 |
|
|
flag_clr => pf_flag_clr( 1 downto 0 ), -- 1 - сброс флага наличия данных
|
| 366 |
|
|
next_block => ch0_next_block, -- 1 - признак достижения блока 4 килобайта
|
| 367 |
|
|
adr_hi_wr => ch0_adr_hi_wr, -- 1 - увеличение старших разрядов адреса для блока
|
| 368 |
|
|
|
| 369 |
|
|
reg_ctrl => reg_ch0_ctrl( 7 downto 0 ), -- регистр управления
|
| 370 |
|
|
|
| 371 |
|
|
dmar => dmar0, -- 1 - запрос DMA
|
| 372 |
|
|
|
| 373 |
|
|
pf_cb => pf0_cb, -- номер текущего блока для обмена с шиной
|
| 374 |
|
|
pf_dma_wr_rdy => pf0_dma_wr_rdy, -- 1 - готовность передать 128 слов
|
| 375 |
|
|
pf_dma_rd_rdy => pf0_dma_rd_rdy, -- 1 - готовность принять 128 слов
|
| 376 |
|
|
|
| 377 |
|
|
pf_ram_rd => pf_ram_rd, -- 1 - чтение данных из памяти
|
| 378 |
|
|
pf_repack_we => pf_repack_we -- 1 - запись в память
|
| 379 |
|
|
);
|
| 380 |
|
|
|
| 381 |
|
|
cmd1: ctrl_ram_cmd_pb
|
| 382 |
|
|
port map(
|
| 383 |
|
|
---- Global ----
|
| 384 |
|
|
reset => reset, -- 0 - сброс
|
| 385 |
|
|
clk => clk, -- тактовая частота 250 МГц
|
| 386 |
|
|
aclk => aclk, -- тактовая частота 266 МГц
|
| 387 |
|
|
|
| 388 |
|
|
act => pf1_act, -- 1 - разрешение цикла обработки
|
| 389 |
|
|
rdy => pf1_rdy, -- 1 - завершение цикла обработки
|
| 390 |
|
|
|
| 391 |
|
|
loc_adr_we => loc_adr_ch1_we, -- 1 - запись локального адреса
|
| 392 |
|
|
flag_data => flag_data( 3 downto 2 ), -- 1 - наличие данных в блоке
|
| 393 |
|
|
|
| 394 |
|
|
flag_set => pf_flag_set( 3 downto 2 ), -- 1 - установка флага наличия данных
|
| 395 |
|
|
flag_clr => pf_flag_clr( 3 downto 2 ), -- 1 - сброс флага наличия данных
|
| 396 |
|
|
next_block => ch1_next_block, -- 1 - признак достижения блока 4 килобайта
|
| 397 |
|
|
adr_hi_wr => ch1_adr_hi_wr, -- 1 - увеличение старших разрядов адреса для блока
|
| 398 |
|
|
|
| 399 |
|
|
reg_ctrl => reg_ch1_ctrl( 7 downto 0 ), -- регистр управления
|
| 400 |
|
|
|
| 401 |
|
|
dmar => dmar1, -- 1 - запрос DMA
|
| 402 |
|
|
|
| 403 |
|
|
pf_cb => pf1_cb, -- номер текущего блока для обмена с шиной
|
| 404 |
|
|
pf_dma_wr_rdy => pf1_dma_wr_rdy, -- 1 - готовность передать 128 слов
|
| 405 |
|
|
pf_dma_rd_rdy => pf1_dma_rd_rdy, -- 1 - готовность принять 128 слов
|
| 406 |
|
|
|
| 407 |
|
|
pf_ram_rd => pf_ram_rd, -- 1 - чтение данных из памяти
|
| 408 |
|
|
pf_repack_we => pf_repack_we -- 1 - запись в память
|
| 409 |
|
|
);
|
| 410 |
|
|
|
| 411 |
|
|
pf_dma_wr_rdy <= pf0_dma_wr_rdy or pf1_dma_wr_rdy;
|
| 412 |
|
|
pf_dma_rd_rdy <= pf0_dma_rd_rdy or pf1_dma_rd_rdy;
|
| 413 |
|
|
|
| 414 |
|
|
request_wr <= pf_dma_wr_rdy;
|
| 415 |
|
|
request_rd <= pf_dma_rd_rdy;
|
| 416 |
|
|
|
| 417 |
|
|
ram_adrb(10) <= pf_chn;
|
| 418 |
|
|
ram_adrb(9) <= pf0_cb when pf_chn='0' else pf1_cb;
|
| 419 |
|
|
|
| 420 |
|
|
--ram_adrb( 8 downto 7 ) <= ch0_adr_hi when pf_chn='0' else ch1_adr_hi;
|
| 421 |
|
|
--
|
| 422 |
|
|
--ram_adrb( 6 downto 0 ) <= port_p( 6 downto 0 ) after 1 ns;
|
| 423 |
|
|
|
| 424 |
|
|
ram_adrb( 8 downto 0 ) <= port_p( 8 downto 0 ) after 1 ns;
|
| 425 |
|
|
|
| 426 |
|
|
opmode <= "0100000";
|
| 427 |
|
|
carry <= pf_repack_we or pf_ram_rd;
|
| 428 |
|
|
|
| 429 |
|
|
pr_pf_ram_rd: process( aclk ) begin
|
| 430 |
|
|
if( rising_edge( aclk ) ) then
|
| 431 |
|
|
if( cnt_rstp='1' or port_p( 8 downto 0 )="111111111" ) or pf_stop_rd='1' or allow_wr='0' then
|
| 432 |
|
|
pf_ram_rd <= '0' after 1 ns;
|
| 433 |
|
|
elsif( pf_dma_wr_rdy='1' and allow_wr='1' ) then
|
| 434 |
|
|
pf_ram_rd <= '1' after 1 ns;
|
| 435 |
|
|
end if;
|
| 436 |
|
|
end if;
|
| 437 |
|
|
end process;
|
| 438 |
|
|
|
| 439 |
|
|
pr_stop_rd: process( aclk ) begin
|
| 440 |
|
|
if( rising_edge( aclk ) ) then
|
| 441 |
|
|
if( cnt_rstp='1' ) then
|
| 442 |
|
|
pf_stop_rd <= '0' after 1 ns;
|
| 443 |
|
|
elsif( port_p( 8 downto 0 )="111111111" ) then
|
| 444 |
|
|
pf_stop_rd <= '1' after 1 ns;
|
| 445 |
|
|
end if;
|
| 446 |
|
|
end if;
|
| 447 |
|
|
end process;
|
| 448 |
|
|
|
| 449 |
|
|
--pf_ram_rd_out <= pf_ram_rd;
|
| 450 |
|
|
pf_ram_rd_out <= pf_ram_rd and allow_wr;
|
| 451 |
|
|
|
| 452 |
|
|
|
| 453 |
|
|
port_b <= x"0000" & "00";
|
| 454 |
|
|
port_a <= x"0000" & "00";
|
| 455 |
|
|
|
| 456 |
|
|
port_c <= port_p;
|
| 457 |
|
|
|
| 458 |
|
|
|
| 459 |
|
|
gen_dsp48: if( is_dsp48=1 ) generate
|
| 460 |
|
|
|
| 461 |
|
|
dsp: DSP48
|
| 462 |
|
|
generic map(
|
| 463 |
|
|
|
| 464 |
|
|
AREG => 1,
|
| 465 |
|
|
B_INPUT => "DIRECT",
|
| 466 |
|
|
BREG => 1,
|
| 467 |
|
|
CARRYINREG => 0,
|
| 468 |
|
|
CARRYINSELREG => 1,
|
| 469 |
|
|
CREG => 1,
|
| 470 |
|
|
LEGACY_MODE => "NONE",
|
| 471 |
|
|
MREG => 1,
|
| 472 |
|
|
OPMODEREG => 1,
|
| 473 |
|
|
PREG => 1,
|
| 474 |
|
|
SUBTRACTREG => 0
|
| 475 |
|
|
)
|
| 476 |
|
|
|
| 477 |
|
|
port map(
|
| 478 |
|
|
--BCOUT : out std_logic_vector(17 downto 0);
|
| 479 |
|
|
P => port_p,
|
| 480 |
|
|
--PCOUT : out std_logic_vector(47 downto 0);
|
| 481 |
|
|
|
| 482 |
|
|
A => port_a,
|
| 483 |
|
|
B => port_b,
|
| 484 |
|
|
BCIN => (others=>'0'),
|
| 485 |
|
|
C => port_c,
|
| 486 |
|
|
CARRYIN => carry,
|
| 487 |
|
|
CARRYINSEL => "00",
|
| 488 |
|
|
CEA => '1',
|
| 489 |
|
|
CEB => '1',
|
| 490 |
|
|
CEC => '1',
|
| 491 |
|
|
CECARRYIN => '1',
|
| 492 |
|
|
CECINSUB => '1',
|
| 493 |
|
|
CECTRL => '1',
|
| 494 |
|
|
CEM => '1',
|
| 495 |
|
|
CEP => '1',
|
| 496 |
|
|
CLK => aclk,
|
| 497 |
|
|
OPMODE => opmode,
|
| 498 |
|
|
PCIN => (others=>'0'),
|
| 499 |
|
|
RSTA => '0',
|
| 500 |
|
|
RSTB => '0',
|
| 501 |
|
|
RSTC => '0',
|
| 502 |
|
|
RSTCARRYIN => '0',
|
| 503 |
|
|
RSTCTRL => '0',
|
| 504 |
|
|
RSTM => '0',
|
| 505 |
|
|
RSTP => cnt_rstp,
|
| 506 |
|
|
SUBTRACT => '0'
|
| 507 |
|
|
);
|
| 508 |
|
|
|
| 509 |
|
|
end generate;
|
| 510 |
|
|
|
| 511 |
|
|
gen_ndsp48: if( is_dsp48=0 ) generate
|
| 512 |
|
|
|
| 513 |
|
|
port_p( 47 downto 9 ) <= (others=>'0');
|
| 514 |
|
|
|
| 515 |
53 |
dsmv |
pr_dsp: process( aclk ) begin
|
| 516 |
|
|
if( rising_edge( aclk ) ) then
|
| 517 |
2 |
dsmv |
if( cnt_rstp='1' ) then
|
| 518 |
|
|
port_p( 8 downto 0 ) <= (others=>'0' ) after 1 ns;
|
| 519 |
|
|
elsif( carry='1' ) then
|
| 520 |
|
|
port_p( 8 downto 0 ) <= port_p( 8 downto 0 ) + 1 after 1 ns;
|
| 521 |
|
|
end if;
|
| 522 |
|
|
end if;
|
| 523 |
|
|
end process;
|
| 524 |
|
|
|
| 525 |
|
|
end generate;
|
| 526 |
|
|
|
| 527 |
|
|
|
| 528 |
|
|
pr_ch0_adr_hi: process( clk ) begin
|
| 529 |
|
|
if( rising_edge( clk ) ) then
|
| 530 |
|
|
if( reset='0' or reg_ch0_ctrl(4)='1' ) then
|
| 531 |
|
|
ch0_adr_hi <= "00" after 1 ns;
|
| 532 |
|
|
elsif( ch0_adr_hi_wr='1' ) then
|
| 533 |
|
|
ch0_adr_hi <= ch0_adr_hi + 1 after 1 ns;
|
| 534 |
|
|
end if;
|
| 535 |
|
|
end if;
|
| 536 |
|
|
end process;
|
| 537 |
|
|
|
| 538 |
|
|
pr_ch1_adr_hi: process( clk ) begin
|
| 539 |
|
|
if( rising_edge( clk ) ) then
|
| 540 |
|
|
if( reset='0' or reg_ch1_ctrl(4)='1' ) then
|
| 541 |
|
|
ch1_adr_hi <= "00" after 1 ns;
|
| 542 |
|
|
elsif( ch1_adr_hi_wr='1' ) then
|
| 543 |
|
|
ch1_adr_hi <= ch1_adr_hi + 1 after 1 ns;
|
| 544 |
|
|
end if;
|
| 545 |
|
|
end if;
|
| 546 |
|
|
end process;
|
| 547 |
|
|
|
| 548 |
|
|
--ch0_next_block <= ch0_adr_hi(0) and ch0_adr_hi(1);
|
| 549 |
|
|
--ch1_next_block <= ch1_adr_hi(0) and ch1_adr_hi(1);
|
| 550 |
|
|
|
| 551 |
|
|
--ch0_next_block <= '1';
|
| 552 |
|
|
--ch1_next_block <= '1';
|
| 553 |
|
|
|
| 554 |
|
|
ch0_next_block <= pb_complete and pf0_act;
|
| 555 |
|
|
ch1_next_block <= pb_complete and pf1_act;
|
| 556 |
|
|
|
| 557 |
|
|
loc_adr_ch0_we <= loc_adr_we and not dma_chn;
|
| 558 |
|
|
loc_adr_ch1_we <= loc_adr_we and dma_chn;
|
| 559 |
|
|
|
| 560 |
|
|
|
| 561 |
|
|
end ctrl_ram_cmd;
|
