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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4.vhd
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dsmv |
-- Version : 1.11
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dsmv |
--
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-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
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--
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--
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity cl_a7pcie_x4 is
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generic (
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CFG_VEND_ID : std_logic_vector := X"10EE";
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CFG_DEV_ID : std_logic_vector := X"7024";
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CFG_REV_ID : std_logic_vector := X"00";
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CFG_SUBSYS_VEND_ID : std_logic_vector := X"10EE";
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CFG_SUBSYS_ID : std_logic_vector := X"0007";
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ALLOW_X8_GEN2 : string := "FALSE";
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PIPE_PIPELINE_STAGES : integer := 1;
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AER_BASE_PTR : bit_vector := X"000";
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AER_CAP_ECRC_CHECK_CAPABLE : string := "FALSE";
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AER_CAP_ECRC_GEN_CAPABLE : string := "FALSE";
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AER_CAP_MULTIHEADER : string := "FALSE";
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AER_CAP_NEXTPTR : bit_vector := X"000";
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AER_CAP_OPTIONAL_ERR_SUPPORT : bit_vector := X"000000";
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AER_CAP_ON : string := "FALSE";
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AER_CAP_PERMIT_ROOTERR_UPDATE : string := "FALSE";
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BAR0 : bit_vector := X"FFE00000";
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BAR1 : bit_vector := X"FFE00000";
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BAR2 : bit_vector := X"00000000";
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BAR3 : bit_vector := X"00000000";
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BAR4 : bit_vector := X"00000000";
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BAR5 : bit_vector := X"00000000";
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C_DATA_WIDTH : integer := 64;
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CARDBUS_CIS_POINTER : bit_vector := X"00000000";
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dsmv |
CLASS_CODE : bit_vector := X"058000";
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dsmv |
CMD_INTX_IMPLEMENTED : string := "TRUE";
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CPL_TIMEOUT_DISABLE_SUPPORTED : string := "FALSE";
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CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"2";
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DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
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DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
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DEV_CAP_EXT_TAG_SUPPORTED : string := "FALSE";
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dsmv |
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
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dsmv |
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
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DEV_CAP2_ARI_FORWARDING_SUPPORTED : string := "FALSE";
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DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED : string := "FALSE";
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DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED : string := "FALSE";
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DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED : string := "FALSE";
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DEV_CAP2_CAS128_COMPLETER_SUPPORTED : string := "FALSE";
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DEV_CAP2_TPH_COMPLETER_SUPPORTED : bit_vector := X"00";
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DEV_CONTROL_EXT_TAG_DEFAULT : string := "FALSE";
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DISABLE_LANE_REVERSAL : string := "FALSE";
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DISABLE_RX_POISONED_RESP : string := "FALSE";
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DISABLE_SCRAMBLING : string := "FALSE";
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DSN_BASE_PTR : bit_vector := X"100";
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DSN_CAP_NEXTPTR : bit_vector := X"000";
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DSN_CAP_ON : string := "TRUE";
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ENABLE_MSG_ROUTE : bit_vector := "00000000000";
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dsmv |
ENABLE_RX_TD_ECRC_TRIM : string := "FALSE";
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dsmv |
EXPANSION_ROM : bit_vector := X"00000000";
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EXT_CFG_CAP_PTR : bit_vector := X"3F";
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EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
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HEADER_TYPE : bit_vector := X"00";
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INTERRUPT_PIN : bit_vector := X"1";
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LAST_CONFIG_DWORD : bit_vector := X"3FF";
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LINK_CAP_ASPM_OPTIONALITY : string := "FALSE";
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LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : string := "FALSE";
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LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : string := "FALSE";
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LINK_CAP_MAX_LINK_SPEED : bit_vector := X"2";
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LINK_CAP_MAX_LINK_SPEED_int : integer := 2;
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LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"04";
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LINK_CAP_MAX_LINK_WIDTH_int : integer := 4;
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LINK_CTRL2_DEEMPHASIS : string := "FALSE";
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LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : string := "FALSE";
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LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
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LINK_STATUS_SLOT_CLOCK_CONFIG : string := "TRUE";
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LL_ACK_TIMEOUT : bit_vector := X"0000";
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LL_ACK_TIMEOUT_EN : string := "FALSE";
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LL_ACK_TIMEOUT_FUNC : integer := 0;
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LL_REPLAY_TIMEOUT : bit_vector := X"0000";
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LL_REPLAY_TIMEOUT_EN : string := "FALSE";
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LL_REPLAY_TIMEOUT_FUNC : integer := 1;
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LTSSM_MAX_LINK_WIDTH : bit_vector := X"04";
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MSI_CAP_MULTIMSGCAP : integer := 0;
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MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
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dsmv |
MSI_CAP_ON : string := "TRUE";
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dsmv |
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : string := "FALSE";
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MSI_CAP_64_BIT_ADDR_CAPABLE : string := "TRUE";
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MSIX_CAP_ON : string := "FALSE";
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MSIX_CAP_PBA_BIR : integer := 0;
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MSIX_CAP_PBA_OFFSET : bit_vector := X"0";
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MSIX_CAP_TABLE_BIR : integer := 0;
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MSIX_CAP_TABLE_OFFSET : bit_vector := X"0";
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MSIX_CAP_TABLE_SIZE : bit_vector := X"0";
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PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0";
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PCIE_CAP_NEXTPTR : bit_vector := X"00";
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dsmv |
PM_CAP_DSI : string := "FALSE";
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dsmv |
PM_CAP_D1SUPPORT : string := "FALSE";
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PM_CAP_D2SUPPORT : string := "FALSE";
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dsmv |
PM_CAP_NEXTPTR : bit_vector := X"48";
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dsmv |
PM_CAP_PMESUPPORT : bit_vector := X"0F";
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PM_CSR_NOSOFTRST : string := "TRUE";
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171 |
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172 |
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PM_DATA_SCALE0 : bit_vector := X"0";
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PM_DATA_SCALE1 : bit_vector := X"0";
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PM_DATA_SCALE2 : bit_vector := X"0";
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PM_DATA_SCALE3 : bit_vector := X"0";
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PM_DATA_SCALE4 : bit_vector := X"0";
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PM_DATA_SCALE5 : bit_vector := X"0";
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PM_DATA_SCALE6 : bit_vector := X"0";
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PM_DATA_SCALE7 : bit_vector := X"0";
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180 |
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PM_DATA0 : bit_vector := X"00";
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PM_DATA1 : bit_vector := X"00";
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PM_DATA2 : bit_vector := X"00";
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PM_DATA3 : bit_vector := X"00";
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PM_DATA4 : bit_vector := X"00";
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PM_DATA5 : bit_vector := X"00";
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PM_DATA6 : bit_vector := X"00";
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188 |
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PM_DATA7 : bit_vector := X"00";
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189 |
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RBAR_BASE_PTR : bit_vector := X"000";
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RBAR_CAP_CONTROL_ENCODEDBAR0 : bit_vector := X"00";
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RBAR_CAP_CONTROL_ENCODEDBAR1 : bit_vector := X"00";
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RBAR_CAP_CONTROL_ENCODEDBAR2 : bit_vector := X"00";
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RBAR_CAP_CONTROL_ENCODEDBAR3 : bit_vector := X"00";
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RBAR_CAP_CONTROL_ENCODEDBAR4 : bit_vector := X"00";
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196 |
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RBAR_CAP_CONTROL_ENCODEDBAR5 : bit_vector := X"00";
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RBAR_CAP_INDEX0 : bit_vector := X"0";
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RBAR_CAP_INDEX1 : bit_vector := X"0";
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RBAR_CAP_INDEX2 : bit_vector := X"0";
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RBAR_CAP_INDEX3 : bit_vector := X"0";
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RBAR_CAP_INDEX4 : bit_vector := X"0";
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RBAR_CAP_INDEX5 : bit_vector := X"0";
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RBAR_CAP_ON : string := "FALSE";
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RBAR_CAP_SUP0 : bit_vector := X"00001";
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RBAR_CAP_SUP1 : bit_vector := X"00001";
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RBAR_CAP_SUP2 : bit_vector := X"00001";
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RBAR_CAP_SUP3 : bit_vector := X"00001";
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RBAR_CAP_SUP4 : bit_vector := X"00001";
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RBAR_CAP_SUP5 : bit_vector := X"00001";
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210 |
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RBAR_NUM : bit_vector := X"0";
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211 |
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212 |
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RECRC_CHK : integer := 0;
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213 |
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RECRC_CHK_TRIM : string := "FALSE";
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214 |
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REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz
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215 |
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--KEEP_WIDTH : integer := C_DATA_WIDTH / 8;
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217 |
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218 |
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TL_RX_RAM_RADDR_LATENCY : integer := 0;
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219 |
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TL_RX_RAM_RDATA_LATENCY : integer := 2;
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220 |
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TL_RX_RAM_WRITE_LATENCY : integer := 0;
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221 |
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TL_TX_RAM_RADDR_LATENCY : integer := 0;
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222 |
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TL_TX_RAM_RDATA_LATENCY : integer := 2;
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223 |
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TL_TX_RAM_WRITE_LATENCY : integer := 0;
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224 |
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TRN_NP_FC : string := "TRUE";
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225 |
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TRN_DW : string := "FALSE";
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226 |
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227 |
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UPCONFIG_CAPABLE : string := "TRUE";
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228 |
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UPSTREAM_FACING : string := "TRUE";
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229 |
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UR_ATOMIC : string := "FALSE";
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230 |
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UR_INV_REQ : string := "TRUE";
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231 |
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UR_PRS_RESPONSE : string := "TRUE";
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232 |
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USER_CLK_FREQ : integer := 3;
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233 |
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USER_CLK2_DIV2 : string := "FALSE";
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234 |
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VC_BASE_PTR : bit_vector := X"000";
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236 |
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VC_CAP_NEXTPTR : bit_vector := X"000";
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237 |
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VC_CAP_ON : string := "FALSE";
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238 |
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VC_CAP_REJECT_SNOOP_TRANSACTIONS : string := "FALSE";
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239 |
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240 |
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VC0_CPL_INFINITE : string := "TRUE";
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241 |
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dsmv |
VC0_RX_RAM_LIMIT : bit_vector := X"7FF";
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242 |
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VC0_TOTAL_CREDITS_CD : integer := 461;
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243 |
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VC0_TOTAL_CREDITS_CH : integer := 36;
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244 |
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VC0_TOTAL_CREDITS_NPH : integer := 12;
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245 |
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VC0_TOTAL_CREDITS_NPD : integer := 24;
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246 |
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VC0_TOTAL_CREDITS_PD : integer := 437;
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247 |
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VC0_TOTAL_CREDITS_PH : integer := 32;
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248 |
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VC0_TX_LASTPACKET : integer := 29;
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249 |
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dsmv |
|
250 |
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VSEC_BASE_PTR : bit_vector := X"000";
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251 |
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VSEC_CAP_NEXTPTR : bit_vector := X"000";
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252 |
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VSEC_CAP_ON : string := "FALSE";
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253 |
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254 |
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DISABLE_ASPM_L1_TIMER : string := "FALSE";
|
255 |
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DISABLE_BAR_FILTERING : string := "FALSE";
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256 |
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DISABLE_ID_CHECK : string := "FALSE";
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257 |
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DISABLE_RX_TC_FILTER : string := "FALSE";
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258 |
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DNSTREAM_LINK_NUM : bit_vector := X"00";
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259 |
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260 |
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DSN_CAP_ID : bit_vector := X"0003";
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261 |
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DSN_CAP_VERSION : bit_vector := X"1";
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262 |
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ENTER_RVRY_EI_L0 : string := "TRUE";
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263 |
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INFER_EI : bit_vector := X"00";
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264 |
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IS_SWITCH : string := "FALSE";
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265 |
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266 |
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LINK_CAP_ASPM_SUPPORT : integer := 1;
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267 |
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LINK_CAP_CLOCK_POWER_MANAGEMENT : string := "FALSE";
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268 |
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LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
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269 |
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LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
|
270 |
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LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
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271 |
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LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
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272 |
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LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
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273 |
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LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
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274 |
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LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
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275 |
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LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
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276 |
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LINK_CAP_RSVD_23 : integer := 0;
|
277 |
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LINK_CONTROL_RCB : integer := 0;
|
278 |
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279 |
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MSI_BASE_PTR : bit_vector := X"48";
|
280 |
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MSI_CAP_ID : bit_vector := X"05";
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281 |
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MSI_CAP_NEXTPTR : bit_vector := X"60";
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282 |
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MSIX_BASE_PTR : bit_vector := X"9c";
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283 |
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MSIX_CAP_ID : bit_vector := X"11";
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284 |
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MSIX_CAP_NEXTPTR : bit_vector := X"00";
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285 |
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286 |
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N_FTS_COMCLK_GEN1 : integer := 255;
|
287 |
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N_FTS_COMCLK_GEN2 : integer := 255;
|
288 |
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N_FTS_GEN1 : integer := 255;
|
289 |
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N_FTS_GEN2 : integer := 255;
|
290 |
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291 |
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PCIE_BASE_PTR : bit_vector := X"60";
|
292 |
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PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
|
293 |
|
|
PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
|
294 |
|
|
PCIE_CAP_ON : string := "TRUE";
|
295 |
|
|
PCIE_CAP_RSVD_15_14 : integer := 0;
|
296 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED : string := "FALSE";
|
297 |
|
|
PCIE_REVISION : integer := 2;
|
298 |
|
|
|
299 |
|
|
PL_AUTO_CONFIG : integer := 0;
|
300 |
|
|
PL_FAST_TRAIN : string := "FALSE";
|
301 |
48 |
dsmv |
|
302 |
46 |
dsmv |
PCIE_EXT_CLK : string := "TRUE";
|
303 |
|
|
|
304 |
|
|
PM_BASE_PTR : bit_vector := X"40";
|
305 |
|
|
PM_CAP_AUXCURRENT : integer := 0;
|
306 |
|
|
PM_CAP_ID : bit_vector := X"01";
|
307 |
|
|
PM_CAP_ON : string := "TRUE";
|
308 |
|
|
PM_CAP_PME_CLOCK : string := "FALSE";
|
309 |
|
|
PM_CAP_RSVD_04 : integer := 0;
|
310 |
|
|
PM_CAP_VERSION : integer := 3;
|
311 |
|
|
PM_CSR_BPCCEN : string := "FALSE";
|
312 |
|
|
PM_CSR_B2B3 : string := "FALSE";
|
313 |
|
|
|
314 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY : string := "FALSE";
|
315 |
|
|
SELECT_DLL_IF : string := "FALSE";
|
316 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT : string := "FALSE";
|
317 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT : string := "FALSE";
|
318 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT : string := "FALSE";
|
319 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE : string := "FALSE";
|
320 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE : string := "FALSE";
|
321 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT : string := "FALSE";
|
322 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : string := "FALSE";
|
323 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
|
324 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT : string := "FALSE";
|
325 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT : string := "FALSE";
|
326 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
|
327 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
|
328 |
|
|
|
329 |
|
|
SPARE_BIT0 : integer := 0;
|
330 |
|
|
|
331 |
|
|
SPARE_BIT1 : integer := 0;
|
332 |
|
|
SPARE_BIT2 : integer := 0;
|
333 |
|
|
SPARE_BIT3 : integer := 0;
|
334 |
|
|
SPARE_BIT4 : integer := 0;
|
335 |
|
|
SPARE_BIT5 : integer := 0;
|
336 |
|
|
SPARE_BIT6 : integer := 0;
|
337 |
|
|
SPARE_BIT7 : integer := 0;
|
338 |
|
|
SPARE_BIT8 : integer := 0;
|
339 |
|
|
SPARE_BYTE0 : bit_vector := X"00";
|
340 |
|
|
SPARE_BYTE1 : bit_vector := X"00";
|
341 |
|
|
SPARE_BYTE2 : bit_vector := X"00";
|
342 |
|
|
SPARE_BYTE3 : bit_vector := X"00";
|
343 |
|
|
SPARE_WORD0 : bit_vector := X"00000000";
|
344 |
|
|
SPARE_WORD1 : bit_vector := X"00000000";
|
345 |
|
|
SPARE_WORD2 : bit_vector := X"00000000";
|
346 |
|
|
SPARE_WORD3 : bit_vector := X"00000000";
|
347 |
|
|
|
348 |
|
|
TL_RBYPASS : string := "FALSE";
|
349 |
|
|
TL_TFC_DISABLE : string := "FALSE";
|
350 |
|
|
TL_TX_CHECKS_DISABLE : string := "FALSE";
|
351 |
|
|
EXIT_LOOPBACK_ON_EI : string := "TRUE";
|
352 |
|
|
|
353 |
|
|
CFG_ECRC_ERR_CPLSTAT : integer := 0;
|
354 |
|
|
CAPABILITIES_PTR : bit_vector := X"40";
|
355 |
|
|
CRM_MODULE_RSTS : bit_vector := X"00";
|
356 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : string := "TRUE";
|
357 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : string := "TRUE";
|
358 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : string := "FALSE";
|
359 |
|
|
DEV_CAP_ROLE_BASED_ERROR : string := "TRUE";
|
360 |
|
|
DEV_CAP_RSVD_14_12 : integer := 0;
|
361 |
|
|
DEV_CAP_RSVD_17_16 : integer := 0;
|
362 |
|
|
DEV_CAP_RSVD_31_29 : integer := 0;
|
363 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED : string := "FALSE";
|
364 |
|
|
|
365 |
|
|
VC_CAP_ID : bit_vector := X"0002";
|
366 |
|
|
VC_CAP_VERSION : bit_vector := X"1";
|
367 |
|
|
VSEC_CAP_HDR_ID : bit_vector := X"1234";
|
368 |
|
|
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
|
369 |
|
|
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
|
370 |
|
|
VSEC_CAP_ID : bit_vector := X"000b";
|
371 |
|
|
VSEC_CAP_IS_LINK_VISIBLE : string := "TRUE";
|
372 |
|
|
VSEC_CAP_VERSION : bit_vector := X"1";
|
373 |
|
|
|
374 |
|
|
DISABLE_ERR_MSG : string := "FALSE";
|
375 |
|
|
DISABLE_LOCKED_FILTER : string := "FALSE";
|
376 |
|
|
DISABLE_PPM_FILTER : string := "FALSE";
|
377 |
|
|
ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED : string := "FALSE";
|
378 |
|
|
INTERRUPT_STAT_AUTO : string := "TRUE";
|
379 |
|
|
MPS_FORCE : string := "FALSE";
|
380 |
|
|
PM_ASPML0S_TIMEOUT : bit_vector := X"0000";
|
381 |
|
|
PM_ASPML0S_TIMEOUT_EN : string := "FALSE";
|
382 |
|
|
PM_ASPML0S_TIMEOUT_FUNC : integer := 0;
|
383 |
|
|
PM_ASPM_FASTEXIT : string := "FALSE";
|
384 |
|
|
PM_MF : string := "FALSE";
|
385 |
|
|
|
386 |
|
|
RP_AUTO_SPD : bit_vector := X"1";
|
387 |
|
|
RP_AUTO_SPD_LOOPCNT : bit_vector := X"1f";
|
388 |
|
|
SIM_VERSION : string := "1.0";
|
389 |
|
|
SSL_MESSAGE_AUTO : string := "FALSE";
|
390 |
|
|
TECRC_EP_INV : string := "FALSE";
|
391 |
|
|
UR_CFG1 : string := "TRUE";
|
392 |
|
|
USE_RID_PINS : string := "FALSE";
|
393 |
|
|
|
394 |
|
|
-- New Parameters
|
395 |
|
|
DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED : string := "FALSE";
|
396 |
|
|
DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED : string := "FALSE";
|
397 |
|
|
DEV_CAP2_LTR_MECHANISM_SUPPORTED : string := "FALSE";
|
398 |
|
|
DEV_CAP2_MAX_ENDEND_TLP_PREFIXES : bit_vector := X"0";
|
399 |
|
|
DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING : string := "FALSE";
|
400 |
|
|
|
401 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : string := "FALSE";
|
402 |
|
|
|
403 |
|
|
AER_CAP_ID : bit_vector := X"0001";
|
404 |
|
|
AER_CAP_VERSION : bit_vector := X"1";
|
405 |
|
|
|
406 |
|
|
RBAR_CAP_ID : bit_vector := X"0015";
|
407 |
|
|
RBAR_CAP_NEXTPTR : bit_vector := X"000";
|
408 |
|
|
RBAR_CAP_VERSION : bit_vector := X"1";
|
409 |
|
|
PCIE_USE_MODE : string := "1.0";
|
410 |
|
|
PCIE_GT_DEVICE : string := "GTP";
|
411 |
|
|
PCIE_CHAN_BOND : integer := 1;
|
412 |
|
|
PCIE_PLL_SEL : string := "CPLL";
|
413 |
|
|
PCIE_ASYNC_EN : string := "FALSE";
|
414 |
|
|
PCIE_TXBUF_EN : string := "FALSE"
|
415 |
|
|
);
|
416 |
|
|
port (
|
417 |
|
|
|
418 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
419 |
|
|
-- 1. PCI Express (pci_exp) Interface --
|
420 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
421 |
|
|
pci_exp_txp : out std_logic_vector(3 downto 0);
|
422 |
|
|
pci_exp_txn : out std_logic_vector(3 downto 0);
|
423 |
|
|
pci_exp_rxp : in std_logic_vector(3 downto 0);
|
424 |
|
|
pci_exp_rxn : in std_logic_vector(3 downto 0);
|
425 |
|
|
|
426 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
427 |
|
|
-- 2. Clocking Interface --
|
428 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
429 |
|
|
PIPE_PCLK_IN : in std_logic;
|
430 |
|
|
PIPE_RXUSRCLK_IN : in std_logic;
|
431 |
|
|
PIPE_RXOUTCLK_IN : in std_logic_vector(3 downto 0);
|
432 |
|
|
PIPE_DCLK_IN : in std_logic;
|
433 |
|
|
PIPE_USERCLK1_IN : in std_logic;
|
434 |
|
|
PIPE_USERCLK2_IN : in std_logic;
|
435 |
|
|
PIPE_OOBCLK_IN : in std_logic;
|
436 |
|
|
PIPE_MMCM_LOCK_IN : in std_logic;
|
437 |
|
|
|
438 |
|
|
PIPE_TXOUTCLK_OUT : out std_logic;
|
439 |
|
|
PIPE_RXOUTCLK_OUT : out std_logic_vector(3 downto 0);
|
440 |
|
|
PIPE_PCLK_SEL_OUT : out std_logic_vector(3 downto 0);
|
441 |
|
|
PIPE_GEN3_OUT : out std_logic;
|
442 |
|
|
|
443 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
444 |
|
|
-- 3. AXI-S Interface --
|
445 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
446 |
|
|
-- Common
|
447 |
|
|
user_clk_out : out std_logic;
|
448 |
|
|
user_reset_out : out std_logic;
|
449 |
|
|
user_lnk_up : out std_logic;
|
450 |
|
|
|
451 |
|
|
-- TX
|
452 |
|
|
tx_buf_av : out std_logic_vector(5 downto 0);
|
453 |
|
|
tx_cfg_req : out std_logic;
|
454 |
|
|
tx_err_drop : out std_logic;
|
455 |
|
|
s_axis_tx_tready : out std_logic;
|
456 |
|
|
s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
|
457 |
|
|
s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
|
458 |
|
|
s_axis_tx_tlast : in std_logic;
|
459 |
|
|
s_axis_tx_tvalid : in std_logic;
|
460 |
|
|
s_axis_tx_tuser : in std_logic_vector(3 downto 0);
|
461 |
|
|
tx_cfg_gnt : in std_logic;
|
462 |
|
|
|
463 |
|
|
-- RX
|
464 |
|
|
m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
|
465 |
|
|
m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
|
466 |
|
|
m_axis_rx_tlast : out std_logic;
|
467 |
|
|
m_axis_rx_tvalid : out std_logic;
|
468 |
|
|
m_axis_rx_tready : in std_logic;
|
469 |
|
|
m_axis_rx_tuser : out std_logic_vector(21 downto 0);
|
470 |
|
|
rx_np_ok : in std_logic;
|
471 |
|
|
rx_np_req : in std_logic;
|
472 |
|
|
|
473 |
|
|
-- Flow Control
|
474 |
|
|
fc_cpld : out std_logic_vector(11 downto 0);
|
475 |
|
|
fc_cplh : out std_logic_vector(7 downto 0);
|
476 |
|
|
fc_npd : out std_logic_vector(11 downto 0);
|
477 |
|
|
fc_nph : out std_logic_vector(7 downto 0);
|
478 |
|
|
fc_pd : out std_logic_vector(11 downto 0);
|
479 |
|
|
fc_ph : out std_logic_vector(7 downto 0);
|
480 |
|
|
fc_sel : in std_logic_vector(2 downto 0);
|
481 |
|
|
|
482 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
483 |
|
|
-- 4. Configuration (CFG) Interface --
|
484 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
485 |
|
|
---------------------------------------------------------------------
|
486 |
|
|
-- EP and RP --
|
487 |
|
|
---------------------------------------------------------------------
|
488 |
|
|
cfg_mgmt_do : out std_logic_vector (31 downto 0);
|
489 |
|
|
cfg_mgmt_rd_wr_done : out std_logic;
|
490 |
|
|
|
491 |
|
|
cfg_status : out std_logic_vector(15 downto 0);
|
492 |
|
|
cfg_command : out std_logic_vector(15 downto 0);
|
493 |
|
|
cfg_dstatus : out std_logic_vector(15 downto 0);
|
494 |
|
|
cfg_dcommand : out std_logic_vector(15 downto 0);
|
495 |
|
|
cfg_lstatus : out std_logic_vector(15 downto 0);
|
496 |
|
|
cfg_lcommand : out std_logic_vector(15 downto 0);
|
497 |
|
|
cfg_dcommand2 : out std_logic_vector(15 downto 0);
|
498 |
|
|
cfg_pcie_link_state : out std_logic_vector(2 downto 0);
|
499 |
|
|
|
500 |
|
|
cfg_pmcsr_pme_en : out std_logic;
|
501 |
|
|
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
|
502 |
|
|
cfg_pmcsr_pme_status : out std_logic;
|
503 |
|
|
cfg_received_func_lvl_rst : out std_logic;
|
504 |
|
|
|
505 |
|
|
-- Management Interface
|
506 |
|
|
cfg_mgmt_di : in std_logic_vector (31 downto 0);
|
507 |
|
|
cfg_mgmt_byte_en : in std_logic_vector (3 downto 0);
|
508 |
|
|
cfg_mgmt_dwaddr : in std_logic_vector (9 downto 0);
|
509 |
|
|
cfg_mgmt_wr_en : in std_logic;
|
510 |
|
|
cfg_mgmt_rd_en : in std_logic;
|
511 |
|
|
cfg_mgmt_wr_readonly : in std_logic;
|
512 |
|
|
|
513 |
|
|
-- Error Reporting Interface
|
514 |
|
|
cfg_err_ecrc : in std_logic;
|
515 |
|
|
cfg_err_ur : in std_logic;
|
516 |
|
|
cfg_err_cpl_timeout : in std_logic;
|
517 |
|
|
cfg_err_cpl_unexpect : in std_logic;
|
518 |
|
|
cfg_err_cpl_abort : in std_logic;
|
519 |
|
|
cfg_err_posted : in std_logic;
|
520 |
|
|
cfg_err_cor : in std_logic;
|
521 |
|
|
cfg_err_atomic_egress_blocked : in std_logic;
|
522 |
|
|
cfg_err_internal_cor : in std_logic;
|
523 |
|
|
cfg_err_malformed : in std_logic;
|
524 |
|
|
cfg_err_mc_blocked : in std_logic;
|
525 |
|
|
cfg_err_poisoned : in std_logic;
|
526 |
|
|
cfg_err_norecovery : in std_logic;
|
527 |
|
|
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
|
528 |
|
|
cfg_err_cpl_rdy : out std_logic;
|
529 |
|
|
cfg_err_locked : in std_logic;
|
530 |
|
|
cfg_err_acs : in std_logic;
|
531 |
|
|
cfg_err_internal_uncor : in std_logic;
|
532 |
|
|
cfg_trn_pending : in std_logic;
|
533 |
|
|
cfg_pm_halt_aspm_l0s : in std_logic;
|
534 |
|
|
cfg_pm_halt_aspm_l1 : in std_logic;
|
535 |
|
|
cfg_pm_force_state_en : in std_logic;
|
536 |
|
|
cfg_pm_force_state : std_logic_vector(1 downto 0);
|
537 |
|
|
cfg_dsn : std_logic_vector(63 downto 0);
|
538 |
|
|
|
539 |
|
|
---------------------------------------------------------------------
|
540 |
|
|
-- EP Only --
|
541 |
|
|
---------------------------------------------------------------------
|
542 |
|
|
cfg_interrupt : in std_logic;
|
543 |
|
|
cfg_interrupt_rdy : out std_logic;
|
544 |
|
|
cfg_interrupt_assert : in std_logic;
|
545 |
|
|
cfg_interrupt_di : in std_logic_vector(7 downto 0);
|
546 |
|
|
cfg_interrupt_do : out std_logic_vector(7 downto 0);
|
547 |
|
|
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
|
548 |
|
|
cfg_interrupt_msienable : out std_logic;
|
549 |
|
|
cfg_interrupt_msixenable : out std_logic;
|
550 |
|
|
cfg_interrupt_msixfm : out std_logic;
|
551 |
|
|
cfg_interrupt_stat : in std_logic;
|
552 |
|
|
cfg_pciecap_interrupt_msgnum : in std_logic_vector(4 downto 0);
|
553 |
|
|
cfg_to_turnoff : out std_logic;
|
554 |
|
|
cfg_turnoff_ok : in std_logic;
|
555 |
|
|
cfg_bus_number : out std_logic_vector(7 downto 0);
|
556 |
|
|
cfg_device_number : out std_logic_vector(4 downto 0);
|
557 |
|
|
cfg_function_number : out std_logic_vector(2 downto 0);
|
558 |
|
|
cfg_pm_wake : in std_logic;
|
559 |
|
|
|
560 |
|
|
---------------------------------------------------------------------
|
561 |
|
|
-- RP Only --
|
562 |
|
|
---------------------------------------------------------------------
|
563 |
|
|
cfg_pm_send_pme_to : in std_logic;
|
564 |
|
|
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
|
565 |
|
|
cfg_ds_device_number : in std_logic_vector(4 downto 0);
|
566 |
|
|
cfg_ds_function_number : in std_logic_vector(2 downto 0);
|
567 |
|
|
|
568 |
|
|
cfg_mgmt_wr_rw1c_as_rw : in std_logic;
|
569 |
|
|
cfg_msg_received : out std_logic;
|
570 |
|
|
cfg_msg_data : out std_logic_vector(15 downto 0);
|
571 |
|
|
|
572 |
|
|
cfg_bridge_serr_en : out std_logic;
|
573 |
|
|
cfg_slot_control_electromech_il_ctl_pulse : out std_logic;
|
574 |
|
|
cfg_root_control_syserr_corr_err_en : out std_logic;
|
575 |
|
|
cfg_root_control_syserr_non_fatal_err_en : out std_logic;
|
576 |
|
|
cfg_root_control_syserr_fatal_err_en : out std_logic;
|
577 |
|
|
cfg_root_control_pme_int_en : out std_logic;
|
578 |
|
|
cfg_aer_rooterr_corr_err_reporting_en : out std_logic;
|
579 |
|
|
cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;
|
580 |
|
|
cfg_aer_rooterr_fatal_err_reporting_en : out std_logic;
|
581 |
|
|
cfg_aer_rooterr_corr_err_received : out std_logic;
|
582 |
|
|
cfg_aer_rooterr_non_fatal_err_received : out std_logic;
|
583 |
|
|
cfg_aer_rooterr_fatal_err_received : out std_logic;
|
584 |
|
|
|
585 |
|
|
cfg_msg_received_err_cor : out std_logic;
|
586 |
|
|
cfg_msg_received_err_non_fatal : out std_logic;
|
587 |
|
|
cfg_msg_received_err_fatal : out std_logic;
|
588 |
|
|
cfg_msg_received_pm_as_nak : out std_logic;
|
589 |
|
|
cfg_msg_received_pm_pme : out std_logic;
|
590 |
|
|
cfg_msg_received_pme_to_ack : out std_logic;
|
591 |
|
|
cfg_msg_received_assert_int_a : out std_logic;
|
592 |
|
|
cfg_msg_received_assert_int_b : out std_logic;
|
593 |
|
|
cfg_msg_received_assert_int_c : out std_logic;
|
594 |
|
|
cfg_msg_received_assert_int_d : out std_logic;
|
595 |
|
|
cfg_msg_received_deassert_int_a : out std_logic;
|
596 |
|
|
cfg_msg_received_deassert_int_b : out std_logic;
|
597 |
|
|
cfg_msg_received_deassert_int_c : out std_logic;
|
598 |
|
|
cfg_msg_received_deassert_int_d : out std_logic;
|
599 |
|
|
cfg_msg_received_setslotpowerlimit : out std_logic;
|
600 |
|
|
|
601 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
602 |
|
|
-- 5. Physical Layer Control and Status (PL) Interface --
|
603 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
604 |
|
|
pl_directed_link_change : in std_logic_vector(1 downto 0);
|
605 |
|
|
pl_directed_link_width : in std_logic_vector(1 downto 0);
|
606 |
|
|
pl_directed_link_speed : in std_logic;
|
607 |
|
|
pl_directed_link_auton : in std_logic;
|
608 |
|
|
pl_upstream_prefer_deemph : in std_logic;
|
609 |
|
|
|
610 |
|
|
pl_sel_lnk_rate : out std_logic;
|
611 |
|
|
pl_sel_lnk_width : out std_logic_vector(1 downto 0);
|
612 |
|
|
pl_ltssm_state : out std_logic_vector(5 downto 0);
|
613 |
|
|
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
|
614 |
|
|
|
615 |
|
|
pl_phy_lnk_up : out std_logic;
|
616 |
|
|
pl_tx_pm_state : out std_logic_vector(2 downto 0);
|
617 |
|
|
pl_rx_pm_state : out std_logic_vector(1 downto 0);
|
618 |
|
|
|
619 |
|
|
pl_link_upcfg_cap : out std_logic;
|
620 |
|
|
pl_link_gen2_cap : out std_logic;
|
621 |
|
|
pl_link_partner_gen2_supported : out std_logic;
|
622 |
|
|
pl_initial_link_width : out std_logic_vector(2 downto 0);
|
623 |
|
|
|
624 |
|
|
pl_directed_change_done : out std_logic;
|
625 |
|
|
|
626 |
|
|
---------------------------------------------------------------------
|
627 |
|
|
-- EP Only --
|
628 |
|
|
---------------------------------------------------------------------
|
629 |
|
|
pl_received_hot_rst : out std_logic;
|
630 |
|
|
---------------------------------------------------------------------
|
631 |
|
|
-- RP Only --
|
632 |
|
|
---------------------------------------------------------------------
|
633 |
|
|
pl_transmit_hot_rst : in std_logic;
|
634 |
|
|
pl_downstream_deemph_source : in std_logic;
|
635 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
636 |
|
|
-- 6. AER interface --
|
637 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
638 |
|
|
cfg_err_aer_headerlog : in std_logic_vector(127 downto 0);
|
639 |
|
|
cfg_aer_interrupt_msgnum : in std_logic_vector(4 downto 0);
|
640 |
|
|
cfg_err_aer_headerlog_set : out std_logic;
|
641 |
|
|
cfg_aer_ecrc_check_en : out std_logic;
|
642 |
|
|
cfg_aer_ecrc_gen_en : out std_logic;
|
643 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
644 |
|
|
-- 7. VC interface --
|
645 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
646 |
|
|
cfg_vc_tcvc_map : out std_logic_vector(6 downto 0);
|
647 |
|
|
|
648 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
649 |
|
|
-- 8. System(SYS) Interface --
|
650 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
651 |
|
|
PIPE_MMCM_RST_N : in std_logic; -- // Async | Async
|
652 |
|
|
sys_clk : in std_logic;
|
653 |
|
|
sys_rst_n : in std_logic
|
654 |
|
|
);
|
655 |
|
|
end cl_a7pcie_x4;
|
656 |
|
|
|
657 |
|
|
architecture pcie_7x of cl_a7pcie_x4 is
|
658 |
|
|
|
659 |
|
|
attribute CORE_GENERATION_INFO : string;
|
660 |
|
|
attribute CORE_GENERATION_INFO of pcie_7x : ARCHITECTURE is
|
661 |
49 |
dsmv |
"cl_a7pcie_x4,pcie_7x_v1_11,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=29,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=437,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_NPD=24,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=461,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=DISABLE_LANE_REVERSAL=FALSE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}";
|
662 |
46 |
dsmv |
component cl_a7pcie_x4_pcie_top is
|
663 |
|
|
generic (
|
664 |
|
|
C_DATA_WIDTH : INTEGER range 32 to 128 := 64;
|
665 |
|
|
C_REM_WIDTH : INTEGER range 0 to 128 := 1;
|
666 |
|
|
PIPE_PIPELINE_STAGES : INTEGER range 0 to 2 := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
|
667 |
|
|
-- PCIE_2_1 params
|
668 |
|
|
AER_BASE_PTR : bit_vector := X"140";
|
669 |
|
|
AER_CAP_ECRC_CHECK_CAPABLE : string := "FALSE";
|
670 |
|
|
AER_CAP_ECRC_GEN_CAPABLE : string := "FALSE";
|
671 |
|
|
AER_CAP_ID : bit_vector := X"0001";
|
672 |
|
|
AER_CAP_MULTIHEADER : string := "FALSE";
|
673 |
|
|
AER_CAP_NEXTPTR : bit_vector := X"178";
|
674 |
|
|
AER_CAP_ON : string := "FALSE";
|
675 |
|
|
AER_CAP_OPTIONAL_ERR_SUPPORT : bit_vector := X"000000";
|
676 |
|
|
AER_CAP_PERMIT_ROOTERR_UPDATE : string := "TRUE";
|
677 |
|
|
AER_CAP_VERSION : bit_vector := X"2";
|
678 |
|
|
ALLOW_X8_GEN2 : string := "FALSE";
|
679 |
|
|
BAR0 : bit_vector := X"FFFFFF00";
|
680 |
|
|
BAR1 : bit_vector := X"FFFF0000";
|
681 |
|
|
BAR2 : bit_vector := X"FFFF000C";
|
682 |
|
|
BAR3 : bit_vector := X"FFFFFFFF";
|
683 |
|
|
BAR4 : bit_vector := X"00000000";
|
684 |
|
|
BAR5 : bit_vector := X"00000000";
|
685 |
|
|
CAPABILITIES_PTR : bit_vector := X"40";
|
686 |
|
|
CARDBUS_CIS_POINTER : bit_vector := X"00000000";
|
687 |
|
|
CFG_ECRC_ERR_CPLSTAT : integer := 0;
|
688 |
|
|
CLASS_CODE : bit_vector := X"000000";
|
689 |
|
|
CMD_INTX_IMPLEMENTED : string := "TRUE";
|
690 |
|
|
CPL_TIMEOUT_DISABLE_SUPPORTED : string := "FALSE";
|
691 |
|
|
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";
|
692 |
|
|
CRM_MODULE_RSTS : bit_vector := X"00";
|
693 |
|
|
DEV_CAP2_ARI_FORWARDING_SUPPORTED : string := "FALSE";
|
694 |
|
|
DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED : string := "FALSE";
|
695 |
|
|
DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED : string := "FALSE";
|
696 |
|
|
DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED : string := "FALSE";
|
697 |
|
|
DEV_CAP2_CAS128_COMPLETER_SUPPORTED : string := "FALSE";
|
698 |
|
|
DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED : string := "FALSE";
|
699 |
|
|
DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED : string := "FALSE";
|
700 |
|
|
DEV_CAP2_LTR_MECHANISM_SUPPORTED : string := "FALSE";
|
701 |
|
|
DEV_CAP2_MAX_ENDEND_TLP_PREFIXES : bit_vector := X"0";
|
702 |
|
|
DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING : string := "FALSE";
|
703 |
|
|
DEV_CAP2_TPH_COMPLETER_SUPPORTED : bit_vector := X"0";
|
704 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : string := "TRUE";
|
705 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : string := "TRUE";
|
706 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
|
707 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;
|
708 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED : string := "TRUE";
|
709 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : string := "FALSE";
|
710 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
|
711 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
|
712 |
|
|
DEV_CAP_ROLE_BASED_ERROR : string := "TRUE";
|
713 |
|
|
DEV_CAP_RSVD_14_12 : integer := 0;
|
714 |
|
|
DEV_CAP_RSVD_17_16 : integer := 0;
|
715 |
|
|
DEV_CAP_RSVD_31_29 : integer := 0;
|
716 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED : string := "FALSE";
|
717 |
|
|
DEV_CONTROL_EXT_TAG_DEFAULT : string := "FALSE";
|
718 |
|
|
DISABLE_ASPM_L1_TIMER : string := "FALSE";
|
719 |
|
|
DISABLE_BAR_FILTERING : string := "FALSE";
|
720 |
|
|
DISABLE_ERR_MSG : string := "FALSE";
|
721 |
|
|
DISABLE_ID_CHECK : string := "FALSE";
|
722 |
|
|
DISABLE_LANE_REVERSAL : string := "FALSE";
|
723 |
|
|
DISABLE_LOCKED_FILTER : string := "FALSE";
|
724 |
|
|
DISABLE_PPM_FILTER : string := "FALSE";
|
725 |
|
|
DISABLE_RX_POISONED_RESP : string := "FALSE";
|
726 |
|
|
DISABLE_RX_TC_FILTER : string := "FALSE";
|
727 |
|
|
DISABLE_SCRAMBLING : string := "FALSE";
|
728 |
|
|
DNSTREAM_LINK_NUM : bit_vector := X"00";
|
729 |
|
|
DSN_BASE_PTR : bit_vector := X"100";
|
730 |
|
|
DSN_CAP_ID : bit_vector := X"0003";
|
731 |
|
|
DSN_CAP_NEXTPTR : bit_vector := X"10C";
|
732 |
|
|
DSN_CAP_ON : string := "TRUE";
|
733 |
|
|
DSN_CAP_VERSION : bit_vector := X"1";
|
734 |
|
|
ENABLE_MSG_ROUTE : bit_vector := X"000";
|
735 |
|
|
ENABLE_RX_TD_ECRC_TRIM : string := "FALSE";
|
736 |
|
|
ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED : string := "FALSE";
|
737 |
|
|
ENTER_RVRY_EI_L0 : string := "TRUE";
|
738 |
|
|
EXIT_LOOPBACK_ON_EI : string := "TRUE";
|
739 |
|
|
EXPANSION_ROM : bit_vector := X"FFFFF001";
|
740 |
|
|
EXT_CFG_CAP_PTR : bit_vector := X"3F";
|
741 |
|
|
EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
|
742 |
|
|
HEADER_TYPE : bit_vector := X"00";
|
743 |
|
|
INFER_EI : bit_vector := X"00";
|
744 |
|
|
INTERRUPT_PIN : bit_vector := X"01";
|
745 |
|
|
INTERRUPT_STAT_AUTO : string := "TRUE";
|
746 |
|
|
IS_SWITCH : string := "FALSE";
|
747 |
|
|
LAST_CONFIG_DWORD : bit_vector := X"3FF";
|
748 |
|
|
LINK_CAP_ASPM_OPTIONALITY : string := "TRUE";
|
749 |
|
|
LINK_CAP_ASPM_SUPPORT : integer := 1;
|
750 |
|
|
LINK_CAP_CLOCK_POWER_MANAGEMENT : string := "FALSE";
|
751 |
|
|
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : string := "FALSE";
|
752 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
|
753 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
|
754 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
|
755 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
|
756 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
|
757 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
|
758 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
|
759 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
|
760 |
|
|
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : string := "FALSE";
|
761 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
|
762 |
|
|
LINK_CAP_MAX_LINK_SPEED_int : integer := 1;
|
763 |
|
|
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
|
764 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
|
765 |
|
|
LINK_CAP_RSVD_23 : integer := 0;
|
766 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : string := "FALSE";
|
767 |
|
|
LINK_CONTROL_RCB : integer := 0;
|
768 |
|
|
LINK_CTRL2_DEEMPHASIS : string := "FALSE";
|
769 |
|
|
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : string := "FALSE";
|
770 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
|
771 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG : string := "TRUE";
|
772 |
|
|
LL_ACK_TIMEOUT : bit_vector := X"0000";
|
773 |
|
|
LL_ACK_TIMEOUT_EN : string := "FALSE";
|
774 |
|
|
LL_ACK_TIMEOUT_FUNC : integer := 0;
|
775 |
|
|
LL_REPLAY_TIMEOUT : bit_vector := X"0000";
|
776 |
|
|
LL_REPLAY_TIMEOUT_EN : string := "FALSE";
|
777 |
|
|
LL_REPLAY_TIMEOUT_FUNC : integer := 0;
|
778 |
|
|
LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";
|
779 |
|
|
MPS_FORCE : string := "FALSE";
|
780 |
|
|
MSIX_BASE_PTR : bit_vector := X"9C";
|
781 |
|
|
MSIX_CAP_ID : bit_vector := X"11";
|
782 |
|
|
MSIX_CAP_NEXTPTR : bit_vector := X"00";
|
783 |
|
|
MSIX_CAP_ON : string := "FALSE";
|
784 |
|
|
MSIX_CAP_PBA_BIR : integer := 0;
|
785 |
|
|
MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";
|
786 |
|
|
MSIX_CAP_TABLE_BIR : integer := 0;
|
787 |
|
|
MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";
|
788 |
|
|
MSIX_CAP_TABLE_SIZE : bit_vector := X"000";
|
789 |
|
|
MSI_BASE_PTR : bit_vector := X"48";
|
790 |
|
|
MSI_CAP_64_BIT_ADDR_CAPABLE : string := "TRUE";
|
791 |
|
|
MSI_CAP_ID : bit_vector := X"05";
|
792 |
|
|
MSI_CAP_MULTIMSGCAP : integer := 0;
|
793 |
|
|
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
|
794 |
|
|
MSI_CAP_NEXTPTR : bit_vector := X"60";
|
795 |
|
|
MSI_CAP_ON : string := "FALSE";
|
796 |
|
|
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : string := "TRUE";
|
797 |
|
|
N_FTS_COMCLK_GEN1 : integer := 255;
|
798 |
|
|
N_FTS_COMCLK_GEN2 : integer := 255;
|
799 |
|
|
N_FTS_GEN1 : integer := 255;
|
800 |
|
|
N_FTS_GEN2 : integer := 255;
|
801 |
|
|
PCIE_BASE_PTR : bit_vector := X"60";
|
802 |
|
|
PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
|
803 |
|
|
PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
|
804 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0";
|
805 |
|
|
PCIE_CAP_NEXTPTR : bit_vector := X"9C";
|
806 |
|
|
PCIE_CAP_ON : string := "TRUE";
|
807 |
|
|
PCIE_CAP_RSVD_15_14 : integer := 0;
|
808 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED : string := "FALSE";
|
809 |
|
|
PCIE_REVISION : integer := 2;
|
810 |
|
|
PL_AUTO_CONFIG : integer := 0;
|
811 |
|
|
PL_FAST_TRAIN : string := "FALSE";
|
812 |
|
|
PM_ASPML0S_TIMEOUT : bit_vector := X"0000";
|
813 |
|
|
PM_ASPML0S_TIMEOUT_EN : string := "FALSE";
|
814 |
|
|
PM_ASPML0S_TIMEOUT_FUNC : integer := 0;
|
815 |
|
|
PM_ASPM_FASTEXIT : string := "FALSE";
|
816 |
|
|
PM_BASE_PTR : bit_vector := X"40";
|
817 |
|
|
PM_CAP_AUXCURRENT : integer := 0;
|
818 |
|
|
PM_CAP_D1SUPPORT : string := "TRUE";
|
819 |
|
|
PM_CAP_D2SUPPORT : string := "TRUE";
|
820 |
|
|
PM_CAP_DSI : string := "FALSE";
|
821 |
|
|
PM_CAP_ID : bit_vector := X"01";
|
822 |
|
|
PM_CAP_NEXTPTR : bit_vector := X"48";
|
823 |
|
|
PM_CAP_ON : string := "TRUE";
|
824 |
|
|
PM_CAP_PMESUPPORT : bit_vector := X"0F";
|
825 |
|
|
PM_CAP_PME_CLOCK : string := "FALSE";
|
826 |
|
|
PM_CAP_RSVD_04 : integer := 0;
|
827 |
|
|
PM_CAP_VERSION : integer := 3;
|
828 |
|
|
PM_CSR_B2B3 : string := "FALSE";
|
829 |
|
|
PM_CSR_BPCCEN : string := "FALSE";
|
830 |
|
|
PM_CSR_NOSOFTRST : string := "TRUE";
|
831 |
|
|
PM_DATA0 : bit_vector := X"01";
|
832 |
|
|
PM_DATA1 : bit_vector := X"01";
|
833 |
|
|
PM_DATA2 : bit_vector := X"01";
|
834 |
|
|
PM_DATA3 : bit_vector := X"01";
|
835 |
|
|
PM_DATA4 : bit_vector := X"01";
|
836 |
|
|
PM_DATA5 : bit_vector := X"01";
|
837 |
|
|
PM_DATA6 : bit_vector := X"01";
|
838 |
|
|
PM_DATA7 : bit_vector := X"01";
|
839 |
|
|
PM_DATA_SCALE0 : bit_vector := X"1";
|
840 |
|
|
PM_DATA_SCALE1 : bit_vector := X"1";
|
841 |
|
|
PM_DATA_SCALE2 : bit_vector := X"1";
|
842 |
|
|
PM_DATA_SCALE3 : bit_vector := X"1";
|
843 |
|
|
PM_DATA_SCALE4 : bit_vector := X"1";
|
844 |
|
|
PM_DATA_SCALE5 : bit_vector := X"1";
|
845 |
|
|
PM_DATA_SCALE6 : bit_vector := X"1";
|
846 |
|
|
PM_DATA_SCALE7 : bit_vector := X"1";
|
847 |
|
|
PM_MF : string := "FALSE";
|
848 |
|
|
RBAR_BASE_PTR : bit_vector := X"178";
|
849 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR0 : bit_vector := X"00";
|
850 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR1 : bit_vector := X"00";
|
851 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR2 : bit_vector := X"00";
|
852 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR3 : bit_vector := X"00";
|
853 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR4 : bit_vector := X"00";
|
854 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR5 : bit_vector := X"00";
|
855 |
|
|
RBAR_CAP_ID : bit_vector := X"0015";
|
856 |
|
|
RBAR_CAP_INDEX0 : bit_vector := X"0";
|
857 |
|
|
RBAR_CAP_INDEX1 : bit_vector := X"0";
|
858 |
|
|
RBAR_CAP_INDEX2 : bit_vector := X"0";
|
859 |
|
|
RBAR_CAP_INDEX3 : bit_vector := X"0";
|
860 |
|
|
RBAR_CAP_INDEX4 : bit_vector := X"0";
|
861 |
|
|
RBAR_CAP_INDEX5 : bit_vector := X"0";
|
862 |
|
|
RBAR_CAP_NEXTPTR : bit_vector := X"000";
|
863 |
|
|
RBAR_CAP_ON : string := "FALSE";
|
864 |
|
|
RBAR_CAP_SUP0 : bit_vector := X"00000000";
|
865 |
|
|
RBAR_CAP_SUP1 : bit_vector := X"00000000";
|
866 |
|
|
RBAR_CAP_SUP2 : bit_vector := X"00000000";
|
867 |
|
|
RBAR_CAP_SUP3 : bit_vector := X"00000000";
|
868 |
|
|
RBAR_CAP_SUP4 : bit_vector := X"00000000";
|
869 |
|
|
RBAR_CAP_SUP5 : bit_vector := X"00000000";
|
870 |
|
|
RBAR_CAP_VERSION : bit_vector := X"1";
|
871 |
|
|
RBAR_NUM : bit_vector := X"1";
|
872 |
|
|
RECRC_CHK : integer := 0;
|
873 |
|
|
RECRC_CHK_TRIM : string := "FALSE";
|
874 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY : string := "FALSE";
|
875 |
|
|
RP_AUTO_SPD : bit_vector := X"1";
|
876 |
|
|
RP_AUTO_SPD_LOOPCNT : bit_vector := X"1F";
|
877 |
|
|
SELECT_DLL_IF : string := "FALSE";
|
878 |
|
|
SIM_VERSION : string := "1.0";
|
879 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT : string := "FALSE";
|
880 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT : string := "FALSE";
|
881 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT : string := "FALSE";
|
882 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE : string := "FALSE";
|
883 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE : string := "FALSE";
|
884 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT : string := "FALSE";
|
885 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : string := "FALSE";
|
886 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
|
887 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT : string := "FALSE";
|
888 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT : string := "FALSE";
|
889 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
|
890 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
|
891 |
|
|
SPARE_BIT0 : integer := 0;
|
892 |
|
|
SPARE_BIT1 : integer := 0;
|
893 |
|
|
SPARE_BIT2 : integer := 0;
|
894 |
|
|
SPARE_BIT3 : integer := 0;
|
895 |
|
|
SPARE_BIT4 : integer := 0;
|
896 |
|
|
SPARE_BIT5 : integer := 0;
|
897 |
|
|
SPARE_BIT6 : integer := 0;
|
898 |
|
|
SPARE_BIT7 : integer := 0;
|
899 |
|
|
SPARE_BIT8 : integer := 0;
|
900 |
|
|
SPARE_BYTE0 : bit_vector := X"00";
|
901 |
|
|
SPARE_BYTE1 : bit_vector := X"00";
|
902 |
|
|
SPARE_BYTE2 : bit_vector := X"00";
|
903 |
|
|
SPARE_BYTE3 : bit_vector := X"00";
|
904 |
|
|
SPARE_WORD0 : bit_vector := X"00000000";
|
905 |
|
|
SPARE_WORD1 : bit_vector := X"00000000";
|
906 |
|
|
SPARE_WORD2 : bit_vector := X"00000000";
|
907 |
|
|
SPARE_WORD3 : bit_vector := X"00000000";
|
908 |
|
|
SSL_MESSAGE_AUTO : string := "FALSE";
|
909 |
|
|
TECRC_EP_INV : string := "FALSE";
|
910 |
|
|
TL_RBYPASS : string := "FALSE";
|
911 |
|
|
TL_RX_RAM_RADDR_LATENCY : integer := 0;
|
912 |
|
|
TL_RX_RAM_RDATA_LATENCY : integer := 2;
|
913 |
|
|
TL_RX_RAM_WRITE_LATENCY : integer := 0;
|
914 |
|
|
TL_TFC_DISABLE : string := "FALSE";
|
915 |
|
|
TL_TX_CHECKS_DISABLE : string := "FALSE";
|
916 |
|
|
TL_TX_RAM_RADDR_LATENCY : integer := 0;
|
917 |
|
|
TL_TX_RAM_RDATA_LATENCY : integer := 2;
|
918 |
|
|
TL_TX_RAM_WRITE_LATENCY : integer := 0;
|
919 |
|
|
TRN_DW : string := "FALSE";
|
920 |
|
|
TRN_NP_FC : string := "FALSE";
|
921 |
|
|
UPCONFIG_CAPABLE : string := "TRUE";
|
922 |
|
|
UPSTREAM_FACING : string := "TRUE";
|
923 |
|
|
UR_ATOMIC : string := "TRUE";
|
924 |
|
|
UR_CFG1 : string := "TRUE";
|
925 |
|
|
UR_INV_REQ : string := "TRUE";
|
926 |
|
|
UR_PRS_RESPONSE : string := "TRUE";
|
927 |
|
|
USER_CLK2_DIV2 : string := "FALSE";
|
928 |
|
|
USER_CLK_FREQ : integer := 3;
|
929 |
|
|
USE_RID_PINS : string := "FALSE";
|
930 |
|
|
VC0_CPL_INFINITE : string := "TRUE";
|
931 |
|
|
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
|
932 |
|
|
VC0_TOTAL_CREDITS_CD : integer := 127;
|
933 |
|
|
VC0_TOTAL_CREDITS_CH : integer := 31;
|
934 |
|
|
VC0_TOTAL_CREDITS_NPD : integer := 24;
|
935 |
|
|
VC0_TOTAL_CREDITS_NPH : integer := 12;
|
936 |
|
|
VC0_TOTAL_CREDITS_PD : integer := 288;
|
937 |
|
|
VC0_TOTAL_CREDITS_PH : integer := 32;
|
938 |
|
|
VC0_TX_LASTPACKET : integer := 31;
|
939 |
|
|
VC_BASE_PTR : bit_vector := X"10C";
|
940 |
|
|
VC_CAP_ID : bit_vector := X"0002";
|
941 |
|
|
VC_CAP_NEXTPTR : bit_vector := X"000";
|
942 |
|
|
VC_CAP_ON : string := "FALSE";
|
943 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS : string := "FALSE";
|
944 |
|
|
VC_CAP_VERSION : bit_vector := X"1";
|
945 |
|
|
VSEC_BASE_PTR : bit_vector := X"128";
|
946 |
|
|
VSEC_CAP_HDR_ID : bit_vector := X"1234";
|
947 |
|
|
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
|
948 |
|
|
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
|
949 |
|
|
VSEC_CAP_ID : bit_vector := X"000B";
|
950 |
|
|
VSEC_CAP_IS_LINK_VISIBLE : string := "TRUE";
|
951 |
|
|
VSEC_CAP_NEXTPTR : bit_vector := X"140";
|
952 |
|
|
VSEC_CAP_ON : string := "FALSE";
|
953 |
|
|
VSEC_CAP_VERSION : bit_vector := X"1"
|
954 |
|
|
);
|
955 |
|
|
port (
|
956 |
|
|
-- Common
|
957 |
|
|
user_clk_out : out std_logic;
|
958 |
|
|
user_reset : in std_logic;
|
959 |
|
|
user_lnk_up : in std_logic;
|
960 |
|
|
|
961 |
|
|
trn_lnk_up : out std_logic;
|
962 |
|
|
user_rst_n : out std_logic;
|
963 |
|
|
|
964 |
|
|
-- Tx
|
965 |
|
|
tx_buf_av : out std_logic_vector(5 downto 0);
|
966 |
|
|
tx_cfg_req : out std_logic;
|
967 |
|
|
tx_err_drop : out std_logic;
|
968 |
|
|
s_axis_tx_tready : out std_logic;
|
969 |
|
|
s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
|
970 |
|
|
s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
|
971 |
|
|
s_axis_tx_tlast : in std_logic;
|
972 |
|
|
s_axis_tx_tvalid : in std_logic;
|
973 |
|
|
s_axis_tx_tuser : in std_logic_vector(3 downto 0);
|
974 |
|
|
tx_cfg_gnt : in std_logic;
|
975 |
|
|
|
976 |
|
|
-- Rx
|
977 |
|
|
m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
|
978 |
|
|
m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
|
979 |
|
|
m_axis_rx_tlast : out std_logic;
|
980 |
|
|
m_axis_rx_tvalid : out std_logic;
|
981 |
|
|
m_axis_rx_tready : in std_logic;
|
982 |
|
|
m_axis_rx_tuser : out std_logic_vector(21 downto 0);
|
983 |
|
|
rx_np_ok : in std_logic;
|
984 |
|
|
rx_np_req : in std_logic;
|
985 |
|
|
|
986 |
|
|
-- Flow Control
|
987 |
|
|
fc_cpld : out std_logic_vector(11 downto 0);
|
988 |
|
|
fc_cplh : out std_logic_vector(7 downto 0);
|
989 |
|
|
fc_npd : out std_logic_vector(11 downto 0);
|
990 |
|
|
fc_nph : out std_logic_vector(7 downto 0);
|
991 |
|
|
fc_pd : out std_logic_vector(11 downto 0);
|
992 |
|
|
fc_ph : out std_logic_vector(7 downto 0);
|
993 |
|
|
fc_sel : in std_logic_vector(2 downto 0);
|
994 |
|
|
|
995 |
|
|
pl_directed_link_change : in std_logic_vector(1 downto 0);
|
996 |
|
|
pl_directed_link_width : in std_logic_vector(1 downto 0);
|
997 |
|
|
pl_directed_link_speed : in std_logic;
|
998 |
|
|
pl_directed_link_auton : in std_logic;
|
999 |
|
|
pl_upstream_prefer_deemph : in std_logic;
|
1000 |
|
|
pl_downstream_deemph_source : in std_logic;
|
1001 |
|
|
pl_directed_ltssm_new_vld : in std_logic;
|
1002 |
|
|
pl_directed_ltssm_new : in std_logic_vector (5 downto 0);
|
1003 |
|
|
pl_directed_ltssm_stall : in std_logic;
|
1004 |
|
|
|
1005 |
|
|
cm_rst_n : in std_logic;
|
1006 |
|
|
func_lvl_rst_n : in std_logic;
|
1007 |
|
|
pl_transmit_hot_rst : in std_logic;
|
1008 |
|
|
cfg_mgmt_di : in std_logic_vector(31 downto 0);
|
1009 |
|
|
cfg_mgmt_byte_en_n : in std_logic_vector(3 downto 0);
|
1010 |
|
|
cfg_mgmt_dwaddr : in std_logic_vector(9 downto 0);
|
1011 |
|
|
cfg_mgmt_wr_rw1c_as_rw_n : in std_logic;
|
1012 |
|
|
cfg_mgmt_wr_readonly_n : in std_logic;
|
1013 |
|
|
cfg_mgmt_wr_en_n : in std_logic;
|
1014 |
|
|
cfg_mgmt_rd_en_n : in std_logic;
|
1015 |
|
|
cfg_err_malformed_n : in std_logic;
|
1016 |
|
|
cfg_err_cor_n : in std_logic;
|
1017 |
|
|
cfg_err_ur_n : in std_logic;
|
1018 |
|
|
cfg_err_ecrc_n : in std_logic;
|
1019 |
|
|
cfg_err_cpl_timeout_n : in std_logic;
|
1020 |
|
|
cfg_err_cpl_abort_n : in std_logic;
|
1021 |
|
|
cfg_err_cpl_unexpect_n : in std_logic;
|
1022 |
|
|
cfg_err_poisoned_n : in std_logic;
|
1023 |
|
|
cfg_err_acs_n : in std_logic;
|
1024 |
|
|
cfg_err_atomic_egress_blocked_n : in std_logic;
|
1025 |
|
|
cfg_err_mc_blocked_n : in std_logic;
|
1026 |
|
|
cfg_err_internal_uncor_n : in std_logic;
|
1027 |
|
|
cfg_err_internal_cor_n : in std_logic;
|
1028 |
|
|
cfg_err_posted_n : in std_logic;
|
1029 |
|
|
cfg_err_locked_n : in std_logic;
|
1030 |
|
|
cfg_err_norecovery_n : in std_logic;
|
1031 |
|
|
cfg_err_aer_headerlog : in std_logic_vector(127 downto 0);
|
1032 |
|
|
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
|
1033 |
|
|
cfg_interrupt_n : in std_logic;
|
1034 |
|
|
cfg_interrupt_di : in std_logic_vector(7 downto 0);
|
1035 |
|
|
cfg_interrupt_assert_n : in std_logic;
|
1036 |
|
|
cfg_interrupt_stat_n : in std_logic;
|
1037 |
|
|
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
|
1038 |
|
|
cfg_ds_device_number : in std_logic_vector(4 downto 0);
|
1039 |
|
|
cfg_ds_function_number : in std_logic_vector( 2 downto 0);
|
1040 |
|
|
cfg_port_number : in std_logic_vector(7 downto 0);
|
1041 |
|
|
cfg_pm_halt_aspm_l0s_n : in std_logic;
|
1042 |
|
|
cfg_pm_halt_aspm_l1_n : in std_logic;
|
1043 |
|
|
cfg_pm_force_state_en_n : in std_logic;
|
1044 |
|
|
cfg_pm_force_state : in std_logic_vector(1 downto 0);
|
1045 |
|
|
cfg_pm_wake_n : in std_logic;
|
1046 |
|
|
cfg_turnoff_ok : in std_logic;
|
1047 |
|
|
cfg_pm_send_pme_to_n : in std_logic;
|
1048 |
|
|
cfg_pciecap_interrupt_msgnum : in std_logic_vector(4 downto 0);
|
1049 |
|
|
cfg_trn_pending : in std_logic;
|
1050 |
|
|
cfg_force_mps : in std_logic_vector( 2 downto 0);
|
1051 |
|
|
cfg_force_common_clock_off : in std_logic;
|
1052 |
|
|
cfg_force_extended_sync_on : in std_logic;
|
1053 |
|
|
cfg_dsn : in std_logic_vector(63 downto 0);
|
1054 |
|
|
cfg_aer_interrupt_msgnum : in std_logic_vector(4 downto 0);
|
1055 |
|
|
|
1056 |
|
|
drp_clk : in std_logic;
|
1057 |
|
|
drp_en : in std_logic;
|
1058 |
|
|
drp_we : in std_logic;
|
1059 |
|
|
drp_addr : in std_logic_vector(8 downto 0);
|
1060 |
|
|
drp_di : in std_logic_vector(15 downto 0);
|
1061 |
|
|
drp_rdy : out std_logic;
|
1062 |
|
|
drp_do : out std_logic_vector(15 downto 0);
|
1063 |
|
|
|
1064 |
|
|
dbg_mode : in std_logic_vector(1 downto 0);
|
1065 |
|
|
dbg_sub_mode : in std_logic;
|
1066 |
|
|
pl_dbg_mode : in std_logic_vector(2 downto 0);
|
1067 |
|
|
|
1068 |
|
|
pl_sel_lnk_rate : out std_logic;
|
1069 |
|
|
pl_sel_lnk_width : out std_logic_vector(1 downto 0);
|
1070 |
|
|
pl_ltssm_state : out std_logic_vector(5 downto 0);
|
1071 |
|
|
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
|
1072 |
|
|
pl_phy_lnk_up : out std_logic;
|
1073 |
|
|
pl_tx_pm_state : out std_logic_vector(2 downto 0);
|
1074 |
|
|
pl_rx_pm_state : out std_logic_vector(1 downto 0);
|
1075 |
|
|
pl_link_upcfg_cap : out std_logic;
|
1076 |
|
|
pl_link_gen2_cap : out std_logic;
|
1077 |
|
|
pl_link_partner_gen2_supported : out std_logic;
|
1078 |
|
|
pl_initial_link_width : out std_logic_vector(2 downto 0);
|
1079 |
|
|
pl_directed_change_done : out std_logic;
|
1080 |
|
|
pl_received_hot_rst : out std_logic;
|
1081 |
|
|
lnk_clk_en : out std_logic;
|
1082 |
|
|
cfg_mgmt_do : out std_logic_vector(31 downto 0);
|
1083 |
|
|
cfg_mgmt_rd_wr_done : out std_logic;
|
1084 |
|
|
cfg_err_aer_headerlog_set : out std_logic;
|
1085 |
|
|
cfg_err_cpl_rdy : out std_logic;
|
1086 |
|
|
cfg_interrupt_rdy : out std_logic;
|
1087 |
|
|
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
|
1088 |
|
|
cfg_interrupt_msienable : out std_logic;
|
1089 |
|
|
cfg_interrupt_do : out std_logic_vector(7 downto 0);
|
1090 |
|
|
cfg_interrupt_msixenable : out std_logic;
|
1091 |
|
|
cfg_interrupt_msixfm : out std_logic;
|
1092 |
|
|
cfg_bus_number : out std_logic_vector(7 downto 0);
|
1093 |
|
|
cfg_device_number : out std_logic_vector(4 downto 0);
|
1094 |
|
|
cfg_function_number : out std_logic_vector(2 downto 0);
|
1095 |
|
|
cfg_status : out std_logic_vector(15 downto 0);
|
1096 |
|
|
cfg_command : out std_logic_vector(15 downto 0);
|
1097 |
|
|
cfg_dstatus : out std_logic_vector(15 downto 0);
|
1098 |
|
|
cfg_dcommand : out std_logic_vector(15 downto 0);
|
1099 |
|
|
cfg_lstatus : out std_logic_vector(15 downto 0);
|
1100 |
|
|
cfg_lcommand : out std_logic_vector(15 downto 0);
|
1101 |
|
|
cfg_dcommand2 : out std_logic_vector(15 downto 0);
|
1102 |
|
|
cfg_received_func_lvl_rst : out std_logic;
|
1103 |
|
|
cfg_msg_received : out std_logic;
|
1104 |
|
|
cfg_msg_data : out std_logic_vector(15 downto 0);
|
1105 |
|
|
cfg_msg_received_err_cor : out std_logic;
|
1106 |
|
|
cfg_msg_received_err_non_fatal : out std_logic;
|
1107 |
|
|
cfg_msg_received_err_fatal : out std_logic;
|
1108 |
|
|
cfg_msg_received_assert_int_a : out std_logic;
|
1109 |
|
|
cfg_msg_received_deassert_int_a : out std_logic;
|
1110 |
|
|
cfg_msg_received_assert_int_b : out std_logic;
|
1111 |
|
|
cfg_msg_received_deassert_int_b : out std_logic;
|
1112 |
|
|
cfg_msg_received_assert_int_c : out std_logic;
|
1113 |
|
|
cfg_msg_received_deassert_int_c : out std_logic;
|
1114 |
|
|
cfg_msg_received_assert_int_d : out std_logic;
|
1115 |
|
|
cfg_msg_received_deassert_int_d : out std_logic;
|
1116 |
|
|
cfg_msg_received_pm_pme : out std_logic;
|
1117 |
|
|
cfg_msg_received_pme_to_ack : out std_logic;
|
1118 |
|
|
cfg_msg_received_pme_to : out std_logic;
|
1119 |
|
|
cfg_msg_received_setslotpowerlimit : out std_logic;
|
1120 |
|
|
cfg_msg_received_unlock : out std_logic;
|
1121 |
|
|
cfg_msg_received_pm_as_nak : out std_logic;
|
1122 |
|
|
cfg_to_turnoff : out std_logic;
|
1123 |
|
|
cfg_pcie_link_state : out std_logic_vector(2 downto 0);
|
1124 |
|
|
cfg_pm_rcv_as_req_l1_n : out std_logic;
|
1125 |
|
|
cfg_pm_rcv_enter_l1_n : out std_logic;
|
1126 |
|
|
cfg_pm_rcv_enter_l23_n : out std_logic;
|
1127 |
|
|
cfg_pm_rcv_req_ack_n : out std_logic;
|
1128 |
|
|
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
|
1129 |
|
|
cfg_pmcsr_pme_en : out std_logic;
|
1130 |
|
|
cfg_pmcsr_pme_status : out std_logic;
|
1131 |
|
|
cfg_transaction : out std_logic;
|
1132 |
|
|
cfg_transaction_type : out std_logic;
|
1133 |
|
|
cfg_transaction_addr : out std_logic_vector(6 downto 0);
|
1134 |
|
|
cfg_command_io_enable : out std_logic;
|
1135 |
|
|
cfg_command_mem_enable : out std_logic;
|
1136 |
|
|
cfg_command_bus_master_enable : out std_logic;
|
1137 |
|
|
cfg_command_interrupt_disable : out std_logic;
|
1138 |
|
|
cfg_command_serr_en : out std_logic;
|
1139 |
|
|
cfg_bridge_serr_en : out std_logic;
|
1140 |
|
|
cfg_dev_status_corr_err_detected : out std_logic;
|
1141 |
|
|
cfg_dev_status_non_fatal_err_detected : out std_logic;
|
1142 |
|
|
cfg_dev_status_fatal_err_detected : out std_logic;
|
1143 |
|
|
cfg_dev_status_ur_detected : out std_logic;
|
1144 |
|
|
cfg_dev_control_corr_err_reporting_en : out std_logic;
|
1145 |
|
|
cfg_dev_control_non_fatal_reporting_en : out std_logic;
|
1146 |
|
|
cfg_dev_control_fatal_err_reporting_en : out std_logic;
|
1147 |
|
|
cfg_dev_control_ur_err_reporting_en : out std_logic;
|
1148 |
|
|
cfg_dev_control_enable_ro : out std_logic;
|
1149 |
|
|
cfg_dev_control_max_payload : out std_logic_vector(2 downto 0);
|
1150 |
|
|
cfg_dev_control_ext_tag_en : out std_logic;
|
1151 |
|
|
cfg_dev_control_phantom_en : out std_logic;
|
1152 |
|
|
cfg_dev_control_aux_power_en : out std_logic;
|
1153 |
|
|
cfg_dev_control_no_snoop_en : out std_logic;
|
1154 |
|
|
cfg_dev_control_max_read_req : out std_logic_vector(2 downto 0);
|
1155 |
|
|
cfg_dev_id : in std_logic_vector(15 downto 0);
|
1156 |
|
|
cfg_vend_id : in std_logic_vector(15 downto 0);
|
1157 |
|
|
cfg_rev_id : in std_logic_vector(7 downto 0);
|
1158 |
|
|
cfg_subsys_id : in std_logic_vector(15 downto 0);
|
1159 |
|
|
cfg_subsys_vend_id : in std_logic_vector(15 downto 0);
|
1160 |
|
|
cfg_link_status_current_speed : out std_logic_vector(1 downto 0);
|
1161 |
|
|
cfg_link_status_negotiated_width : out std_logic_vector(3 downto 0);
|
1162 |
|
|
cfg_link_status_link_training : out std_logic;
|
1163 |
|
|
cfg_link_status_dll_active : out std_logic;
|
1164 |
|
|
cfg_link_status_bandwidth_status : out std_logic;
|
1165 |
|
|
cfg_link_status_auto_bandwidth_status : out std_logic;
|
1166 |
|
|
cfg_link_control_aspm_control : out std_logic_vector(1 downto 0);
|
1167 |
|
|
cfg_link_control_rcb : out std_logic;
|
1168 |
|
|
cfg_link_control_link_disable : out std_logic;
|
1169 |
|
|
cfg_link_control_retrain_link : out std_logic;
|
1170 |
|
|
cfg_link_control_common_clock : out std_logic;
|
1171 |
|
|
cfg_link_control_extended_sync : out std_logic;
|
1172 |
|
|
cfg_link_control_clock_pm_en : out std_logic;
|
1173 |
|
|
cfg_link_control_hw_auto_width_dis : out std_logic;
|
1174 |
|
|
cfg_link_control_bandwidth_int_en : out std_logic;
|
1175 |
|
|
cfg_link_control_auto_bandwidth_int_en : out std_logic;
|
1176 |
|
|
cfg_dev_control2_cpl_timeout_val : out std_logic_vector(3 downto 0);
|
1177 |
|
|
cfg_dev_control2_cpl_timeout_dis : out std_logic;
|
1178 |
|
|
cfg_dev_control2_ari_forward_en : out std_logic;
|
1179 |
|
|
cfg_dev_control2_atomic_requester_en : out std_logic;
|
1180 |
|
|
cfg_dev_control2_atomic_egress_block : out std_logic;
|
1181 |
|
|
cfg_dev_control2_ido_req_en : out std_logic;
|
1182 |
|
|
cfg_dev_control2_ido_cpl_en : out std_logic;
|
1183 |
|
|
cfg_dev_control2_ltr_en : out std_logic;
|
1184 |
|
|
cfg_dev_control2_tlp_prefix_block : out std_logic;
|
1185 |
|
|
cfg_slot_control_electromech_il_ctl_pulse : out std_logic;
|
1186 |
|
|
cfg_root_control_syserr_corr_err_en : out std_logic;
|
1187 |
|
|
cfg_root_control_syserr_non_fatal_err_en : out std_logic;
|
1188 |
|
|
cfg_root_control_syserr_fatal_err_en : out std_logic;
|
1189 |
|
|
cfg_root_control_pme_int_en : out std_logic;
|
1190 |
|
|
cfg_aer_ecrc_check_en : out std_logic;
|
1191 |
|
|
cfg_aer_ecrc_gen_en : out std_logic;
|
1192 |
|
|
cfg_aer_rooterr_corr_err_reporting_en : out std_logic;
|
1193 |
|
|
cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;
|
1194 |
|
|
cfg_aer_rooterr_fatal_err_reporting_en : out std_logic;
|
1195 |
|
|
cfg_aer_rooterr_corr_err_received : out std_logic;
|
1196 |
|
|
cfg_aer_rooterr_non_fatal_err_received : out std_logic;
|
1197 |
|
|
cfg_aer_rooterr_fatal_err_received : out std_logic;
|
1198 |
|
|
cfg_vc_tcvc_map : out std_logic_vector(6 downto 0);
|
1199 |
|
|
dbg_vec_a : out std_logic_vector(63 downto 0);
|
1200 |
|
|
dbg_vec_b : out std_logic_vector(63 downto 0);
|
1201 |
|
|
dbg_vec_c : out std_logic_vector(11 downto 0);
|
1202 |
|
|
dbg_sclr_a : out std_logic;
|
1203 |
|
|
dbg_sclr_b : out std_logic;
|
1204 |
|
|
dbg_sclr_c : out std_logic;
|
1205 |
|
|
dbg_sclr_d : out std_logic;
|
1206 |
|
|
dbg_sclr_e : out std_logic;
|
1207 |
|
|
dbg_sclr_f : out std_logic;
|
1208 |
|
|
dbg_sclr_g : out std_logic;
|
1209 |
|
|
dbg_sclr_h : out std_logic;
|
1210 |
|
|
dbg_sclr_i : out std_logic;
|
1211 |
|
|
dbg_sclr_j : out std_logic;
|
1212 |
|
|
dbg_sclr_k : out std_logic;
|
1213 |
|
|
trn_rdllp_data : out std_logic_vector(63 downto 0);
|
1214 |
|
|
trn_rdllp_src_rdy : out std_logic_vector(1 downto 0);
|
1215 |
|
|
pl_dbg_vec : out std_logic_vector(11 downto 0);
|
1216 |
|
|
|
1217 |
|
|
phy_rdy_n : in std_logic;
|
1218 |
|
|
pipe_clk : in std_logic;
|
1219 |
|
|
user_clk : in std_logic;
|
1220 |
|
|
user_clk2 : in std_logic;
|
1221 |
|
|
pipe_rx0_polarity_gt : out std_logic;
|
1222 |
|
|
pipe_rx1_polarity_gt : out std_logic;
|
1223 |
|
|
pipe_rx2_polarity_gt : out std_logic;
|
1224 |
|
|
pipe_rx3_polarity_gt : out std_logic;
|
1225 |
|
|
pipe_rx4_polarity_gt : out std_logic;
|
1226 |
|
|
pipe_rx5_polarity_gt : out std_logic;
|
1227 |
|
|
pipe_rx6_polarity_gt : out std_logic;
|
1228 |
|
|
pipe_rx7_polarity_gt : out std_logic;
|
1229 |
|
|
pipe_tx_deemph_gt : out std_logic;
|
1230 |
|
|
pipe_tx_margin_gt : out std_logic_vector (2 downto 0);
|
1231 |
|
|
pipe_tx_rate_gt : out std_logic;
|
1232 |
|
|
pipe_tx_rcvr_det_gt : out std_logic;
|
1233 |
|
|
pipe_tx0_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1234 |
|
|
pipe_tx0_compliance_gt : out std_logic;
|
1235 |
|
|
pipe_tx0_data_gt : out std_logic_vector (15 downto 0);
|
1236 |
|
|
pipe_tx0_elec_idle_gt : out std_logic;
|
1237 |
|
|
pipe_tx0_powerdown_gt : out std_logic_vector (1 downto 0);
|
1238 |
|
|
pipe_tx1_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1239 |
|
|
pipe_tx1_compliance_gt : out std_logic;
|
1240 |
|
|
pipe_tx1_data_gt : out std_logic_vector (15 downto 0);
|
1241 |
|
|
pipe_tx1_elec_idle_gt : out std_logic;
|
1242 |
|
|
pipe_tx1_powerdown_gt : out std_logic_vector (1 downto 0);
|
1243 |
|
|
pipe_tx2_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1244 |
|
|
pipe_tx2_compliance_gt : out std_logic;
|
1245 |
|
|
pipe_tx2_data_gt : out std_logic_vector (15 downto 0);
|
1246 |
|
|
pipe_tx2_elec_idle_gt : out std_logic;
|
1247 |
|
|
pipe_tx2_powerdown_gt : out std_logic_vector (1 downto 0);
|
1248 |
|
|
pipe_tx3_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1249 |
|
|
pipe_tx3_compliance_gt : out std_logic;
|
1250 |
|
|
pipe_tx3_data_gt : out std_logic_vector (15 downto 0);
|
1251 |
|
|
pipe_tx3_elec_idle_gt : out std_logic;
|
1252 |
|
|
pipe_tx3_powerdown_gt : out std_logic_vector (1 downto 0);
|
1253 |
|
|
pipe_tx4_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1254 |
|
|
pipe_tx4_compliance_gt : out std_logic;
|
1255 |
|
|
pipe_tx4_data_gt : out std_logic_vector (15 downto 0);
|
1256 |
|
|
pipe_tx4_elec_idle_gt : out std_logic;
|
1257 |
|
|
pipe_tx4_powerdown_gt : out std_logic_vector (1 downto 0);
|
1258 |
|
|
pipe_tx5_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1259 |
|
|
pipe_tx5_compliance_gt : out std_logic;
|
1260 |
|
|
pipe_tx5_data_gt : out std_logic_vector (15 downto 0);
|
1261 |
|
|
pipe_tx5_elec_idle_gt : out std_logic;
|
1262 |
|
|
pipe_tx5_powerdown_gt : out std_logic_vector (1 downto 0);
|
1263 |
|
|
pipe_tx6_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1264 |
|
|
pipe_tx6_compliance_gt : out std_logic;
|
1265 |
|
|
pipe_tx6_data_gt : out std_logic_vector (15 downto 0);
|
1266 |
|
|
pipe_tx6_elec_idle_gt : out std_logic;
|
1267 |
|
|
pipe_tx6_powerdown_gt : out std_logic_vector (1 downto 0);
|
1268 |
|
|
pipe_tx7_char_is_k_gt : out std_logic_vector (1 downto 0);
|
1269 |
|
|
pipe_tx7_compliance_gt : out std_logic;
|
1270 |
|
|
pipe_tx7_data_gt : out std_logic_vector (15 downto 0);
|
1271 |
|
|
pipe_tx7_elec_idle_gt : out std_logic;
|
1272 |
|
|
pipe_tx7_powerdown_gt : out std_logic_vector (1 downto 0);
|
1273 |
|
|
|
1274 |
|
|
pipe_rx0_chanisaligned_gt : in std_logic;
|
1275 |
|
|
pipe_rx0_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1276 |
|
|
pipe_rx0_data_gt : in std_logic_vector (15 downto 0);
|
1277 |
|
|
pipe_rx0_elec_idle_gt : in std_logic;
|
1278 |
|
|
pipe_rx0_phy_status_gt : in std_logic;
|
1279 |
|
|
pipe_rx0_status_gt : in std_logic_vector (2 downto 0);
|
1280 |
|
|
pipe_rx0_valid_gt : in std_logic;
|
1281 |
|
|
pipe_rx1_chanisaligned_gt : in std_logic;
|
1282 |
|
|
pipe_rx1_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1283 |
|
|
pipe_rx1_data_gt : in std_logic_vector (15 downto 0);
|
1284 |
|
|
pipe_rx1_elec_idle_gt : in std_logic;
|
1285 |
|
|
pipe_rx1_phy_status_gt : in std_logic;
|
1286 |
|
|
pipe_rx1_status_gt : in std_logic_vector (2 downto 0);
|
1287 |
|
|
pipe_rx1_valid_gt : in std_logic;
|
1288 |
|
|
pipe_rx2_chanisaligned_gt : in std_logic;
|
1289 |
|
|
pipe_rx2_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1290 |
|
|
pipe_rx2_data_gt : in std_logic_vector (15 downto 0);
|
1291 |
|
|
pipe_rx2_elec_idle_gt : in std_logic;
|
1292 |
|
|
pipe_rx2_phy_status_gt : in std_logic;
|
1293 |
|
|
pipe_rx2_status_gt : in std_logic_vector (2 downto 0);
|
1294 |
|
|
pipe_rx2_valid_gt : in std_logic;
|
1295 |
|
|
pipe_rx3_chanisaligned_gt : in std_logic;
|
1296 |
|
|
pipe_rx3_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1297 |
|
|
pipe_rx3_data_gt : in std_logic_vector (15 downto 0);
|
1298 |
|
|
pipe_rx3_elec_idle_gt : in std_logic;
|
1299 |
|
|
pipe_rx3_phy_status_gt : in std_logic;
|
1300 |
|
|
pipe_rx3_status_gt : in std_logic_vector (2 downto 0);
|
1301 |
|
|
pipe_rx3_valid_gt : in std_logic;
|
1302 |
|
|
pipe_rx4_chanisaligned_gt : in std_logic;
|
1303 |
|
|
pipe_rx4_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1304 |
|
|
pipe_rx4_data_gt : in std_logic_vector (15 downto 0);
|
1305 |
|
|
pipe_rx4_elec_idle_gt : in std_logic;
|
1306 |
|
|
pipe_rx4_phy_status_gt : in std_logic;
|
1307 |
|
|
pipe_rx4_status_gt : in std_logic_vector (2 downto 0);
|
1308 |
|
|
pipe_rx4_valid_gt : in std_logic;
|
1309 |
|
|
pipe_rx5_chanisaligned_gt : in std_logic;
|
1310 |
|
|
pipe_rx5_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1311 |
|
|
pipe_rx5_data_gt : in std_logic_vector (15 downto 0);
|
1312 |
|
|
pipe_rx5_elec_idle_gt : in std_logic;
|
1313 |
|
|
pipe_rx5_phy_status_gt : in std_logic;
|
1314 |
|
|
pipe_rx5_status_gt : in std_logic_vector (2 downto 0);
|
1315 |
|
|
pipe_rx5_valid_gt : in std_logic;
|
1316 |
|
|
pipe_rx6_chanisaligned_gt : in std_logic;
|
1317 |
|
|
pipe_rx6_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1318 |
|
|
pipe_rx6_data_gt : in std_logic_vector (15 downto 0);
|
1319 |
|
|
pipe_rx6_elec_idle_gt : in std_logic;
|
1320 |
|
|
pipe_rx6_phy_status_gt : in std_logic;
|
1321 |
|
|
pipe_rx6_status_gt : in std_logic_vector (2 downto 0);
|
1322 |
|
|
pipe_rx6_valid_gt : in std_logic;
|
1323 |
|
|
pipe_rx7_chanisaligned_gt : in std_logic;
|
1324 |
|
|
pipe_rx7_char_is_k_gt : in std_logic_vector (1 downto 0);
|
1325 |
|
|
pipe_rx7_data_gt : in std_logic_vector (15 downto 0);
|
1326 |
|
|
pipe_rx7_elec_idle_gt : in std_logic;
|
1327 |
|
|
pipe_rx7_phy_status_gt : in std_logic;
|
1328 |
|
|
pipe_rx7_status_gt : in std_logic_vector (2 downto 0);
|
1329 |
|
|
pipe_rx7_valid_gt : in std_logic
|
1330 |
|
|
);
|
1331 |
|
|
end component;
|
1332 |
|
|
|
1333 |
|
|
component cl_a7pcie_x4_gt_top is
|
1334 |
|
|
generic (
|
1335 |
|
|
LINK_CAP_MAX_LINK_WIDTH_INT : integer := 1; -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
|
1336 |
|
|
REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
|
1337 |
|
|
USER_CLK2_DIV2 : string := "FALSE"; -- "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
|
1338 |
|
|
-- "FALSE" => user_clk2 = user_clk
|
1339 |
|
|
USER_CLK_FREQ : integer := 3; -- 0 - 31.25 MHz, 1 - 62.5 MHz, 2 - 125 MHz, 3 - 250 MHz, 4 - 500Mhz
|
1340 |
|
|
PL_FAST_TRAIN : string := "FALSE"; -- Simulation Speedup
|
1341 |
|
|
PCIE_EXT_CLK : string := "FALSE"; -- External Clock Enable
|
1342 |
|
|
PCIE_USE_MODE : string := "1.0"; -- 1.0 = K325T IES, 1.1 = vx485t IES, 3.0 = K325T GES
|
1343 |
|
|
PCIE_GT_DEVICE : string := "GTX"; -- Select the GT to use (GTP for Artix-7, GTX for K7/V7)
|
1344 |
|
|
PCIE_PLL_SEL : string := "CPLL"; -- Select the PLL (CPLL or QPLL)
|
1345 |
|
|
PCIE_ASYNC_EN : string := "FALSE"; -- Asynchronous Clocking Enable
|
1346 |
|
|
PCIE_TXBUF_EN : string := "FALSE"; -- Use the Tansmit Buffer
|
1347 |
|
|
PCIE_CHAN_BOND : integer := 0 -- PCIE Channel Bond Methodology Select
|
1348 |
|
|
|
1349 |
|
|
);
|
1350 |
|
|
port (
|
1351 |
|
|
-- pl ltssm
|
1352 |
|
|
pl_ltssm_state : in std_logic_vector(5 downto 0);
|
1353 |
|
|
|
1354 |
|
|
-- Pipe Per-Link Signals
|
1355 |
|
|
pipe_tx_rcvr_det : in std_logic;
|
1356 |
|
|
pipe_tx_reset : in std_logic;
|
1357 |
|
|
pipe_tx_rate : in std_logic;
|
1358 |
|
|
pipe_tx_deemph : in std_logic;
|
1359 |
|
|
pipe_tx_margin : in std_logic_vector (2 downto 0);
|
1360 |
|
|
pipe_tx_swing : in std_logic;
|
1361 |
|
|
|
1362 |
|
|
----------------------------------------------------------------------------------------------------
|
1363 |
|
|
-- External Clocking Interface --
|
1364 |
|
|
----------------------------------------------------------------------------------------------------
|
1365 |
|
|
|
1366 |
|
|
PIPE_PCLK_IN : in std_logic;
|
1367 |
|
|
PIPE_RXUSRCLK_IN : in std_logic;
|
1368 |
|
|
PIPE_RXOUTCLK_IN : in std_logic_vector(3 downto 0);
|
1369 |
|
|
PIPE_DCLK_IN : in std_logic;
|
1370 |
|
|
PIPE_USERCLK1_IN : in std_logic;
|
1371 |
|
|
PIPE_USERCLK2_IN : in std_logic;
|
1372 |
|
|
PIPE_OOBCLK_IN : in std_logic;
|
1373 |
|
|
PIPE_MMCM_LOCK_IN : in std_logic;
|
1374 |
|
|
|
1375 |
|
|
PIPE_TXOUTCLK_OUT : out std_logic;
|
1376 |
|
|
PIPE_RXOUTCLK_OUT : out std_logic_vector(3 downto 0);
|
1377 |
|
|
PIPE_PCLK_SEL_OUT : out std_logic_vector(3 downto 0);
|
1378 |
|
|
PIPE_GEN3_OUT : out std_logic;
|
1379 |
|
|
|
1380 |
|
|
-- Pipe Per-Lane Signals - Lane 0
|
1381 |
|
|
pipe_rx0_char_is_k : out std_logic_vector(1 downto 0);
|
1382 |
|
|
pipe_rx0_data : out std_logic_vector(15 downto 0);
|
1383 |
|
|
pipe_rx0_valid : out std_logic;
|
1384 |
|
|
pipe_rx0_chanisaligned : out std_logic;
|
1385 |
|
|
pipe_rx0_status : out std_logic_vector(2 downto 0);
|
1386 |
|
|
pipe_rx0_phy_status : out std_logic;
|
1387 |
|
|
pipe_rx0_elec_idle : out std_logic;
|
1388 |
|
|
pipe_rx0_polarity : in std_logic;
|
1389 |
|
|
pipe_tx0_compliance : in std_logic;
|
1390 |
|
|
pipe_tx0_char_is_k : in std_logic_vector(1 downto 0);
|
1391 |
|
|
pipe_tx0_data : in std_logic_vector(15 downto 0);
|
1392 |
|
|
pipe_tx0_elec_idle : in std_logic;
|
1393 |
|
|
pipe_tx0_powerdown : in std_logic_vector(1 downto 0);
|
1394 |
|
|
|
1395 |
|
|
-- Pipe Per-Lane Signals - Lane 1
|
1396 |
|
|
pipe_rx1_char_is_k : out std_logic_vector(1 downto 0);
|
1397 |
|
|
pipe_rx1_data : out std_logic_vector(15 downto 0);
|
1398 |
|
|
pipe_rx1_valid : out std_logic;
|
1399 |
|
|
pipe_rx1_chanisaligned : out std_logic;
|
1400 |
|
|
pipe_rx1_status : out std_logic_vector(2 downto 0);
|
1401 |
|
|
pipe_rx1_phy_status : out std_logic;
|
1402 |
|
|
pipe_rx1_elec_idle : out std_logic;
|
1403 |
|
|
pipe_rx1_polarity : in std_logic;
|
1404 |
|
|
pipe_tx1_compliance : in std_logic;
|
1405 |
|
|
pipe_tx1_char_is_k : in std_logic_vector(1 downto 0);
|
1406 |
|
|
pipe_tx1_data : in std_logic_vector(15 downto 0);
|
1407 |
|
|
pipe_tx1_elec_idle : in std_logic;
|
1408 |
|
|
pipe_tx1_powerdown : in std_logic_vector(1 downto 0);
|
1409 |
|
|
|
1410 |
|
|
-- Pipe Per-Lane Signals - Lane 2
|
1411 |
|
|
pipe_rx2_char_is_k : out std_logic_vector(1 downto 0);
|
1412 |
|
|
pipe_rx2_data : out std_logic_vector(15 downto 0);
|
1413 |
|
|
pipe_rx2_valid : out std_logic;
|
1414 |
|
|
pipe_rx2_chanisaligned : out std_logic;
|
1415 |
|
|
pipe_rx2_status : out std_logic_vector(2 downto 0);
|
1416 |
|
|
pipe_rx2_phy_status : out std_logic;
|
1417 |
|
|
pipe_rx2_elec_idle : out std_logic;
|
1418 |
|
|
pipe_rx2_polarity : in std_logic;
|
1419 |
|
|
pipe_tx2_compliance : in std_logic;
|
1420 |
|
|
pipe_tx2_char_is_k : in std_logic_vector(1 downto 0);
|
1421 |
|
|
pipe_tx2_data : in std_logic_vector(15 downto 0);
|
1422 |
|
|
pipe_tx2_elec_idle : in std_logic;
|
1423 |
|
|
pipe_tx2_powerdown : in std_logic_vector(1 downto 0);
|
1424 |
|
|
|
1425 |
|
|
-- Pipe Per-Lane Signals - Lane 3
|
1426 |
|
|
pipe_rx3_char_is_k : out std_logic_vector(1 downto 0);
|
1427 |
|
|
pipe_rx3_data : out std_logic_vector(15 downto 0);
|
1428 |
|
|
pipe_rx3_valid : out std_logic;
|
1429 |
|
|
pipe_rx3_chanisaligned : out std_logic;
|
1430 |
|
|
pipe_rx3_status : out std_logic_vector(2 downto 0);
|
1431 |
|
|
pipe_rx3_phy_status : out std_logic;
|
1432 |
|
|
pipe_rx3_elec_idle : out std_logic;
|
1433 |
|
|
pipe_rx3_polarity : in std_logic;
|
1434 |
|
|
pipe_tx3_compliance : in std_logic;
|
1435 |
|
|
pipe_tx3_char_is_k : in std_logic_vector(1 downto 0);
|
1436 |
|
|
pipe_tx3_data : in std_logic_vector(15 downto 0);
|
1437 |
|
|
pipe_tx3_elec_idle : in std_logic;
|
1438 |
|
|
pipe_tx3_powerdown : in std_logic_vector(1 downto 0);
|
1439 |
|
|
|
1440 |
|
|
-- Pipe Per-Lane Signals - Lane 4
|
1441 |
|
|
pipe_rx4_char_is_k : out std_logic_vector(1 downto 0);
|
1442 |
|
|
pipe_rx4_data : out std_logic_vector(15 downto 0);
|
1443 |
|
|
pipe_rx4_valid : out std_logic;
|
1444 |
|
|
pipe_rx4_chanisaligned : out std_logic;
|
1445 |
|
|
pipe_rx4_status : out std_logic_vector(2 downto 0);
|
1446 |
|
|
pipe_rx4_phy_status : out std_logic;
|
1447 |
|
|
pipe_rx4_elec_idle : out std_logic;
|
1448 |
|
|
pipe_rx4_polarity : in std_logic;
|
1449 |
|
|
pipe_tx4_compliance : in std_logic;
|
1450 |
|
|
pipe_tx4_char_is_k : in std_logic_vector(1 downto 0);
|
1451 |
|
|
pipe_tx4_data : in std_logic_vector(15 downto 0);
|
1452 |
|
|
pipe_tx4_elec_idle : in std_logic;
|
1453 |
|
|
pipe_tx4_powerdown : in std_logic_vector(1 downto 0);
|
1454 |
|
|
|
1455 |
|
|
-- Pipe Per-Lane Signals - Lane 5
|
1456 |
|
|
pipe_rx5_char_is_k : out std_logic_vector(1 downto 0);
|
1457 |
|
|
pipe_rx5_data : out std_logic_vector(15 downto 0);
|
1458 |
|
|
pipe_rx5_valid : out std_logic;
|
1459 |
|
|
pipe_rx5_chanisaligned : out std_logic;
|
1460 |
|
|
pipe_rx5_status : out std_logic_vector(2 downto 0);
|
1461 |
|
|
pipe_rx5_phy_status : out std_logic;
|
1462 |
|
|
pipe_rx5_elec_idle : out std_logic;
|
1463 |
|
|
pipe_rx5_polarity : in std_logic;
|
1464 |
|
|
pipe_tx5_compliance : in std_logic;
|
1465 |
|
|
pipe_tx5_char_is_k : in std_logic_vector(1 downto 0);
|
1466 |
|
|
pipe_tx5_data : in std_logic_vector(15 downto 0);
|
1467 |
|
|
pipe_tx5_elec_idle : in std_logic;
|
1468 |
|
|
pipe_tx5_powerdown : in std_logic_vector(1 downto 0);
|
1469 |
|
|
|
1470 |
|
|
-- Pipe Per-Lane Signals - Lane 6
|
1471 |
|
|
pipe_rx6_char_is_k : out std_logic_vector(1 downto 0);
|
1472 |
|
|
pipe_rx6_data : out std_logic_vector(15 downto 0);
|
1473 |
|
|
pipe_rx6_valid : out std_logic;
|
1474 |
|
|
pipe_rx6_chanisaligned : out std_logic;
|
1475 |
|
|
pipe_rx6_status : out std_logic_vector(2 downto 0);
|
1476 |
|
|
pipe_rx6_phy_status : out std_logic;
|
1477 |
|
|
pipe_rx6_elec_idle : out std_logic;
|
1478 |
|
|
pipe_rx6_polarity : in std_logic;
|
1479 |
|
|
pipe_tx6_compliance : in std_logic;
|
1480 |
|
|
pipe_tx6_char_is_k : in std_logic_vector(1 downto 0);
|
1481 |
|
|
pipe_tx6_data : in std_logic_vector(15 downto 0);
|
1482 |
|
|
pipe_tx6_elec_idle : in std_logic;
|
1483 |
|
|
pipe_tx6_powerdown : in std_logic_vector(1 downto 0);
|
1484 |
|
|
|
1485 |
|
|
-- Pipe Per-Lane Signals - Lane 7
|
1486 |
|
|
pipe_rx7_char_is_k : out std_logic_vector(1 downto 0);
|
1487 |
|
|
pipe_rx7_data : out std_logic_vector(15 downto 0);
|
1488 |
|
|
pipe_rx7_valid : out std_logic;
|
1489 |
|
|
pipe_rx7_chanisaligned : out std_logic;
|
1490 |
|
|
pipe_rx7_status : out std_logic_vector(2 downto 0);
|
1491 |
|
|
pipe_rx7_phy_status : out std_logic;
|
1492 |
|
|
pipe_rx7_elec_idle : out std_logic;
|
1493 |
|
|
pipe_rx7_polarity : in std_logic;
|
1494 |
|
|
pipe_tx7_compliance : in std_logic;
|
1495 |
|
|
pipe_tx7_char_is_k : in std_logic_vector(1 downto 0);
|
1496 |
|
|
pipe_tx7_data : in std_logic_vector(15 downto 0);
|
1497 |
|
|
pipe_tx7_elec_idle : in std_logic;
|
1498 |
|
|
pipe_tx7_powerdown : in std_logic_vector(1 downto 0);
|
1499 |
|
|
|
1500 |
|
|
-- PCI Express signals
|
1501 |
|
|
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_INT-1) downto 0);
|
1502 |
|
|
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_INT-1) downto 0);
|
1503 |
|
|
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_INT-1) downto 0);
|
1504 |
|
|
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_INT-1) downto 0);
|
1505 |
|
|
|
1506 |
|
|
-- Non PIPE signals
|
1507 |
|
|
sys_clk : in std_logic;
|
1508 |
|
|
PIPE_MMCM_RST_N : in std_logic; -- // Async | Async
|
1509 |
|
|
|
1510 |
|
|
pipe_clk : out std_logic;
|
1511 |
|
|
user_clk : out std_logic;
|
1512 |
|
|
user_clk2 : out std_logic;
|
1513 |
|
|
sys_rst_n : in std_logic;
|
1514 |
|
|
phy_rdy_n : out std_logic
|
1515 |
|
|
);
|
1516 |
|
|
end component;
|
1517 |
|
|
|
1518 |
|
|
signal user_clk : std_logic;
|
1519 |
|
|
signal user_clk2 : std_logic;
|
1520 |
|
|
signal pipe_clk : std_logic;
|
1521 |
|
|
|
1522 |
|
|
signal cfg_vend_id_wire : std_logic_vector(15 downto 0);--;= CFG_VEND_ID;
|
1523 |
|
|
signal cfg_dev_id_wire : std_logic_vector(15 downto 0);--;= CFG_DEV_ID;
|
1524 |
|
|
signal cfg_rev_id_wire : std_logic_vector(7 downto 0); --;= CFG_REV_ID;
|
1525 |
|
|
signal cfg_subsys_vend_id_wire : std_logic_vector(15 downto 0);--;= CFG_SUBSYS_VEND_ID;
|
1526 |
|
|
signal cfg_subsys_id_wire : std_logic_vector(15 downto 0);--;= CFG_SUBSYS_ID;
|
1527 |
|
|
|
1528 |
|
|
-- PIPE Interface Wires
|
1529 |
|
|
signal phy_rdy_n : std_logic;
|
1530 |
|
|
signal pipe_rx0_polarity_gt : std_logic;
|
1531 |
|
|
signal pipe_rx1_polarity_gt : std_logic;
|
1532 |
|
|
signal pipe_rx2_polarity_gt : std_logic;
|
1533 |
|
|
signal pipe_rx3_polarity_gt : std_logic;
|
1534 |
|
|
signal pipe_rx4_polarity_gt : std_logic;
|
1535 |
|
|
signal pipe_rx5_polarity_gt : std_logic;
|
1536 |
|
|
signal pipe_rx6_polarity_gt : std_logic;
|
1537 |
|
|
signal pipe_rx7_polarity_gt : std_logic;
|
1538 |
|
|
signal pipe_tx_deemph_gt : std_logic;
|
1539 |
|
|
signal pipe_tx_margin_gt : std_logic_vector(2 downto 0);
|
1540 |
|
|
signal pipe_tx_rate_gt : std_logic;
|
1541 |
|
|
signal pipe_tx_rcvr_det_gt : std_logic;
|
1542 |
|
|
signal pipe_tx0_char_is_k_gt : std_logic_vector(1 downto 0);
|
1543 |
|
|
signal pipe_tx0_compliance_gt : std_logic;
|
1544 |
|
|
signal pipe_tx0_data_gt : std_logic_vector(15 downto 0);
|
1545 |
|
|
signal pipe_tx0_elec_idle_gt : std_logic;
|
1546 |
|
|
signal pipe_tx0_powerdown_gt : std_logic_vector(1 downto 0);
|
1547 |
|
|
signal pipe_tx1_char_is_k_gt : std_logic_vector(1 downto 0);
|
1548 |
|
|
signal pipe_tx1_compliance_gt : std_logic;
|
1549 |
|
|
signal pipe_tx1_data_gt : std_logic_vector(15 downto 0);
|
1550 |
|
|
signal pipe_tx1_elec_idle_gt : std_logic;
|
1551 |
|
|
signal pipe_tx1_powerdown_gt : std_logic_vector(1 downto 0);
|
1552 |
|
|
signal pipe_tx2_char_is_k_gt : std_logic_vector(1 downto 0);
|
1553 |
|
|
signal pipe_tx2_compliance_gt : std_logic;
|
1554 |
|
|
signal pipe_tx2_data_gt : std_logic_vector(15 downto 0);
|
1555 |
|
|
signal pipe_tx2_elec_idle_gt : std_logic;
|
1556 |
|
|
signal pipe_tx2_powerdown_gt : std_logic_vector(1 downto 0);
|
1557 |
|
|
signal pipe_tx3_char_is_k_gt : std_logic_vector(1 downto 0);
|
1558 |
|
|
signal pipe_tx3_compliance_gt : std_logic;
|
1559 |
|
|
signal pipe_tx3_data_gt : std_logic_vector(15 downto 0);
|
1560 |
|
|
signal pipe_tx3_elec_idle_gt : std_logic;
|
1561 |
|
|
signal pipe_tx3_powerdown_gt : std_logic_vector(1 downto 0);
|
1562 |
|
|
signal pipe_tx4_char_is_k_gt : std_logic_vector(1 downto 0);
|
1563 |
|
|
signal pipe_tx4_compliance_gt : std_logic;
|
1564 |
|
|
signal pipe_tx4_data_gt : std_logic_vector(15 downto 0);
|
1565 |
|
|
signal pipe_tx4_elec_idle_gt : std_logic;
|
1566 |
|
|
signal pipe_tx4_powerdown_gt : std_logic_vector(1 downto 0);
|
1567 |
|
|
signal pipe_tx5_char_is_k_gt : std_logic_vector(1 downto 0);
|
1568 |
|
|
signal pipe_tx5_compliance_gt : std_logic;
|
1569 |
|
|
signal pipe_tx5_data_gt : std_logic_vector(15 downto 0);
|
1570 |
|
|
signal pipe_tx5_elec_idle_gt : std_logic;
|
1571 |
|
|
signal pipe_tx5_powerdown_gt : std_logic_vector(1 downto 0);
|
1572 |
|
|
signal pipe_tx6_char_is_k_gt : std_logic_vector(1 downto 0);
|
1573 |
|
|
signal pipe_tx6_compliance_gt : std_logic;
|
1574 |
|
|
signal pipe_tx6_data_gt : std_logic_vector(15 downto 0);
|
1575 |
|
|
signal pipe_tx6_elec_idle_gt : std_logic;
|
1576 |
|
|
signal pipe_tx6_powerdown_gt : std_logic_vector(1 downto 0);
|
1577 |
|
|
signal pipe_tx7_char_is_k_gt : std_logic_vector(1 downto 0);
|
1578 |
|
|
signal pipe_tx7_compliance_gt : std_logic;
|
1579 |
|
|
signal pipe_tx7_data_gt : std_logic_vector(15 downto 0);
|
1580 |
|
|
signal pipe_tx7_elec_idle_gt : std_logic;
|
1581 |
|
|
signal pipe_tx7_powerdown_gt : std_logic_vector(1 downto 0);
|
1582 |
|
|
|
1583 |
|
|
signal pipe_rx0_chanisaligned_gt : std_logic;
|
1584 |
|
|
signal pipe_rx0_char_is_k_gt : std_logic_vector(1 downto 0);
|
1585 |
|
|
signal pipe_rx0_data_gt : std_logic_vector(15 downto 0);
|
1586 |
|
|
signal pipe_rx0_elec_idle_gt : std_logic;
|
1587 |
|
|
signal pipe_rx0_phy_status_gt : std_logic;
|
1588 |
|
|
signal pipe_rx0_status_gt : std_logic_vector(2 downto 0);
|
1589 |
|
|
signal pipe_rx0_valid_gt : std_logic;
|
1590 |
|
|
signal pipe_rx1_chanisaligned_gt : std_logic;
|
1591 |
|
|
signal pipe_rx1_char_is_k_gt : std_logic_vector(1 downto 0);
|
1592 |
|
|
signal pipe_rx1_data_gt : std_logic_vector(15 downto 0);
|
1593 |
|
|
signal pipe_rx1_elec_idle_gt : std_logic;
|
1594 |
|
|
signal pipe_rx1_phy_status_gt : std_logic;
|
1595 |
|
|
signal pipe_rx1_status_gt : std_logic_vector(2 downto 0);
|
1596 |
|
|
signal pipe_rx1_valid_gt : std_logic;
|
1597 |
|
|
signal pipe_rx2_chanisaligned_gt : std_logic;
|
1598 |
|
|
signal pipe_rx2_char_is_k_gt : std_logic_vector(1 downto 0);
|
1599 |
|
|
signal pipe_rx2_data_gt : std_logic_vector(15 downto 0);
|
1600 |
|
|
signal pipe_rx2_elec_idle_gt : std_logic;
|
1601 |
|
|
signal pipe_rx2_phy_status_gt : std_logic;
|
1602 |
|
|
signal pipe_rx2_status_gt : std_logic_vector(2 downto 0);
|
1603 |
|
|
signal pipe_rx2_valid_gt : std_logic;
|
1604 |
|
|
signal pipe_rx3_chanisaligned_gt : std_logic;
|
1605 |
|
|
signal pipe_rx3_char_is_k_gt : std_logic_vector(1 downto 0);
|
1606 |
|
|
signal pipe_rx3_data_gt : std_logic_vector(15 downto 0);
|
1607 |
|
|
signal pipe_rx3_elec_idle_gt : std_logic;
|
1608 |
|
|
signal pipe_rx3_phy_status_gt : std_logic;
|
1609 |
|
|
signal pipe_rx3_status_gt : std_logic_vector(2 downto 0);
|
1610 |
|
|
signal pipe_rx3_valid_gt : std_logic;
|
1611 |
|
|
signal pipe_rx4_chanisaligned_gt : std_logic;
|
1612 |
|
|
signal pipe_rx4_char_is_k_gt : std_logic_vector(1 downto 0);
|
1613 |
|
|
signal pipe_rx4_data_gt : std_logic_vector(15 downto 0);
|
1614 |
|
|
signal pipe_rx4_elec_idle_gt : std_logic;
|
1615 |
|
|
signal pipe_rx4_phy_status_gt : std_logic;
|
1616 |
|
|
signal pipe_rx4_status_gt : std_logic_vector(2 downto 0);
|
1617 |
|
|
signal pipe_rx4_valid_gt : std_logic;
|
1618 |
|
|
signal pipe_rx5_chanisaligned_gt : std_logic;
|
1619 |
|
|
signal pipe_rx5_char_is_k_gt : std_logic_vector(1 downto 0);
|
1620 |
|
|
signal pipe_rx5_data_gt : std_logic_vector(15 downto 0);
|
1621 |
|
|
signal pipe_rx5_elec_idle_gt : std_logic;
|
1622 |
|
|
signal pipe_rx5_phy_status_gt : std_logic;
|
1623 |
|
|
signal pipe_rx5_status_gt : std_logic_vector(2 downto 0);
|
1624 |
|
|
signal pipe_rx5_valid_gt : std_logic;
|
1625 |
|
|
signal pipe_rx6_chanisaligned_gt : std_logic;
|
1626 |
|
|
signal pipe_rx6_char_is_k_gt : std_logic_vector(1 downto 0);
|
1627 |
|
|
signal pipe_rx6_data_gt : std_logic_vector(15 downto 0);
|
1628 |
|
|
signal pipe_rx6_elec_idle_gt : std_logic;
|
1629 |
|
|
signal pipe_rx6_phy_status_gt : std_logic;
|
1630 |
|
|
signal pipe_rx6_status_gt : std_logic_vector(2 downto 0);
|
1631 |
|
|
signal pipe_rx6_valid_gt : std_logic;
|
1632 |
|
|
signal pipe_rx7_chanisaligned_gt : std_logic;
|
1633 |
|
|
signal pipe_rx7_char_is_k_gt : std_logic_vector(1 downto 0);
|
1634 |
|
|
signal pipe_rx7_data_gt : std_logic_vector(15 downto 0);
|
1635 |
|
|
signal pipe_rx7_elec_idle_gt : std_logic;
|
1636 |
|
|
signal pipe_rx7_phy_status_gt : std_logic;
|
1637 |
|
|
signal pipe_rx7_status_gt : std_logic_vector(2 downto 0);
|
1638 |
|
|
signal pipe_rx7_valid_gt : std_logic;
|
1639 |
|
|
|
1640 |
|
|
signal user_lnk_up_d : std_logic;
|
1641 |
|
|
signal user_lnk_up_int : std_logic;
|
1642 |
|
|
signal user_reset_int : std_logic;
|
1643 |
|
|
signal user_rst_n : std_logic;
|
1644 |
|
|
signal sys_or_hot_rst : std_logic;
|
1645 |
|
|
-- signal sys_rst_n : std_logic;
|
1646 |
|
|
signal trn_lnk_up : std_logic;
|
1647 |
|
|
|
1648 |
|
|
-- Intermediate signals that need to be inverted
|
1649 |
|
|
signal cfg_mgmt_byte_en_int_n : std_logic_vector(3 downto 0);
|
1650 |
|
|
signal cfg_err_cor_int_n : std_logic;
|
1651 |
|
|
signal cfg_err_cpl_abort_int_n : std_logic;
|
1652 |
|
|
signal cfg_err_cpl_timeout_int_n : std_logic;
|
1653 |
|
|
signal cfg_err_cpl_unexpect_int_n : std_logic;
|
1654 |
|
|
signal cfg_err_ecrc_int_n : std_logic;
|
1655 |
|
|
signal cfg_err_locked_int_n : std_logic;
|
1656 |
|
|
signal cfg_err_posted_int_n : std_logic;
|
1657 |
|
|
signal cfg_err_ur_int_n : std_logic;
|
1658 |
|
|
signal cfg_err_malformed_int_n : std_logic;
|
1659 |
|
|
signal cfg_err_poisoned_int_n : std_logic;
|
1660 |
|
|
signal cfg_err_atomic_egress_blocked_int_n : std_logic;
|
1661 |
|
|
signal cfg_err_mc_blocked_int_n : std_logic;
|
1662 |
|
|
signal cfg_err_internal_uncor_int_n : std_logic;
|
1663 |
|
|
signal cfg_err_internal_cor_int_n : std_logic;
|
1664 |
|
|
signal cfg_err_norecovery_int_n : std_logic;
|
1665 |
|
|
signal cfg_interrupt_assert_int_n : std_logic;
|
1666 |
|
|
signal cfg_interrupt_int_n : std_logic;
|
1667 |
|
|
signal cfg_interrupt_stat_int_n : std_logic;
|
1668 |
|
|
signal cfg_pm_wake_int_n : std_logic;
|
1669 |
|
|
signal cfg_pm_halt_aspm_l0s_int_n : std_logic;
|
1670 |
|
|
signal cfg_pm_halt_aspm_l1_int_n : std_logic;
|
1671 |
|
|
signal cfg_pm_force_state_en_int_n : std_logic;
|
1672 |
|
|
signal cfg_mgmt_rd_en_int_n : std_logic;
|
1673 |
|
|
signal cfg_mgmt_wr_en_int_n : std_logic;
|
1674 |
|
|
signal cfg_mgmt_wr_readonly_int_n : std_logic;
|
1675 |
|
|
signal cfg_mgmt_wr_rw1c_as_rw_int_n : std_logic;
|
1676 |
|
|
signal pl_received_hot_rst_int : std_logic;
|
1677 |
|
|
signal pl_received_hot_rst_q : std_logic;
|
1678 |
|
|
signal user_clk_out_int : std_logic;
|
1679 |
|
|
signal pl_phy_lnk_up_int : std_logic;
|
1680 |
|
|
signal pl_phy_lnk_up_q : std_logic;
|
1681 |
|
|
signal bridge_reset_int : std_logic;
|
1682 |
|
|
signal bridge_reset_d : std_logic;
|
1683 |
|
|
|
1684 |
|
|
signal pl_ltssm_state_int : std_logic_vector(5 downto 0);
|
1685 |
|
|
|
1686 |
|
|
|
1687 |
|
|
|
1688 |
|
|
|
1689 |
|
|
|
1690 |
|
|
-- map the data bits
|
1691 |
|
|
function get_rem(
|
1692 |
|
|
constant dw : integer)
|
1693 |
|
|
return integer is
|
1694 |
|
|
begin -- get_rem
|
1695 |
|
|
if (dw = 128) then
|
1696 |
|
|
return 2;
|
1697 |
|
|
else
|
1698 |
|
|
return 1;
|
1699 |
|
|
end if;
|
1700 |
|
|
end get_rem;
|
1701 |
|
|
|
1702 |
|
|
function pad_gen (
|
1703 |
|
|
in_vec : bit_vector;
|
1704 |
|
|
op_len : integer)
|
1705 |
|
|
return bit_vector is
|
1706 |
|
|
variable ret : bit_vector(op_len-1 downto 0) := (others => '0');
|
1707 |
|
|
constant len : integer := in_vec'length; -- length of input vector
|
1708 |
|
|
begin -- pad_gen
|
1709 |
|
|
for i in 0 to op_len-1 loop
|
1710 |
|
|
if (i < len) then
|
1711 |
|
|
ret(i) := in_vec(len-i-1);
|
1712 |
|
|
else
|
1713 |
|
|
ret(i) := '0';
|
1714 |
|
|
end if;
|
1715 |
|
|
end loop; -- i
|
1716 |
|
|
return ret;
|
1717 |
|
|
end pad_gen;
|
1718 |
|
|
|
1719 |
|
|
constant C_REM_WIDTH : integer := get_rem(C_DATA_WIDTH);
|
1720 |
|
|
constant TCQ : integer := 1; -- clock to out delay model
|
1721 |
|
|
|
1722 |
|
|
begin
|
1723 |
|
|
-- sys_rst_n <= not sys_reset;
|
1724 |
|
|
cfg_mgmt_byte_en_int_n <= not cfg_mgmt_byte_en;
|
1725 |
|
|
cfg_err_cor_int_n <= not cfg_err_cor;
|
1726 |
|
|
cfg_err_cpl_abort_int_n <= not cfg_err_cpl_abort;
|
1727 |
|
|
cfg_err_cpl_timeout_int_n <= not cfg_err_cpl_timeout;
|
1728 |
|
|
cfg_err_cpl_unexpect_int_n <= not cfg_err_cpl_unexpect;
|
1729 |
|
|
cfg_err_ecrc_int_n <= not cfg_err_ecrc;
|
1730 |
|
|
cfg_err_locked_int_n <= not cfg_err_locked;
|
1731 |
|
|
cfg_err_posted_int_n <= not cfg_err_posted;
|
1732 |
|
|
cfg_err_ur_int_n <= not cfg_err_ur;
|
1733 |
|
|
cfg_err_malformed_int_n <= not cfg_err_malformed;
|
1734 |
|
|
cfg_err_poisoned_int_n <= not cfg_err_poisoned;
|
1735 |
|
|
cfg_err_atomic_egress_blocked_int_n <= not cfg_err_atomic_egress_blocked;
|
1736 |
|
|
cfg_err_mc_blocked_int_n <= not cfg_err_mc_blocked;
|
1737 |
|
|
cfg_err_internal_uncor_int_n <= not cfg_err_internal_uncor;
|
1738 |
|
|
cfg_err_internal_cor_int_n <= not cfg_err_internal_cor;
|
1739 |
|
|
cfg_err_norecovery_int_n <= not cfg_err_norecovery;
|
1740 |
|
|
cfg_interrupt_assert_int_n <= not cfg_interrupt_assert;
|
1741 |
|
|
cfg_interrupt_int_n <= not cfg_interrupt;
|
1742 |
|
|
cfg_interrupt_stat_int_n <= not cfg_interrupt_stat;
|
1743 |
|
|
cfg_pm_wake_int_n <= not cfg_pm_wake;
|
1744 |
|
|
cfg_pm_halt_aspm_l0s_int_n <= not cfg_pm_halt_aspm_l0s;
|
1745 |
|
|
cfg_pm_halt_aspm_l1_int_n <= not cfg_pm_halt_aspm_l1;
|
1746 |
|
|
cfg_pm_force_state_en_int_n <= not cfg_pm_force_state_en;
|
1747 |
|
|
cfg_mgmt_rd_en_int_n <= not cfg_mgmt_rd_en;
|
1748 |
|
|
cfg_mgmt_wr_en_int_n <= not cfg_mgmt_wr_en;
|
1749 |
|
|
cfg_mgmt_wr_readonly_int_n <= not cfg_mgmt_wr_readonly;
|
1750 |
|
|
cfg_mgmt_wr_rw1c_as_rw_int_n <= not cfg_mgmt_wr_rw1c_as_rw;
|
1751 |
|
|
cfg_vend_id_wire <= CFG_VEND_ID;
|
1752 |
|
|
cfg_dev_id_wire <= CFG_DEV_ID;
|
1753 |
|
|
cfg_rev_id_wire <= CFG_REV_ID;
|
1754 |
|
|
cfg_subsys_vend_id_wire <= CFG_SUBSYS_VEND_ID;
|
1755 |
|
|
cfg_subsys_id_wire <= CFG_SUBSYS_ID;
|
1756 |
|
|
sys_or_hot_rst <= (not sys_rst_n) or pl_received_hot_rst_q;
|
1757 |
|
|
pl_received_hot_rst <= pl_received_hot_rst_q;
|
1758 |
|
|
user_clk_out <= user_clk_out_int;
|
1759 |
|
|
pl_phy_lnk_up <= pl_phy_lnk_up_q;
|
1760 |
|
|
user_lnk_up <= user_lnk_up_int;
|
1761 |
|
|
|
1762 |
|
|
pl_ltssm_state <= pl_ltssm_state_int;
|
1763 |
|
|
|
1764 |
|
|
|
1765 |
|
|
-- Register Block Outputs to ease timing
|
1766 |
|
|
process (user_clk_out_int)
|
1767 |
|
|
begin
|
1768 |
|
|
if (user_clk_out_int'event and user_clk_out_int = '1') then
|
1769 |
|
|
|
1770 |
|
|
if (sys_rst_n = '0') then
|
1771 |
|
|
pl_phy_lnk_up_q <= '0' after (TCQ)*1 ps;
|
1772 |
|
|
pl_received_hot_rst_q <= '0' after (TCQ)*1 ps;
|
1773 |
|
|
else
|
1774 |
|
|
pl_phy_lnk_up_q <= pl_phy_lnk_up_int after (TCQ)*1 ps;
|
1775 |
|
|
pl_received_hot_rst_q <= pl_received_hot_rst_int after (TCQ)*1 ps;
|
1776 |
|
|
end if;
|
1777 |
|
|
end if;
|
1778 |
|
|
end process;
|
1779 |
|
|
|
1780 |
|
|
process (user_clk_out_int)
|
1781 |
|
|
begin
|
1782 |
|
|
if (user_clk_out_int'event and user_clk_out_int = '1') then
|
1783 |
|
|
|
1784 |
|
|
if (sys_rst_n = '0') then
|
1785 |
|
|
user_lnk_up_int <= '0' after (TCQ)*1 ps;
|
1786 |
|
|
else
|
1787 |
|
|
user_lnk_up_int <= user_lnk_up_d after (TCQ)*1 ps;
|
1788 |
|
|
end if;
|
1789 |
|
|
end if;
|
1790 |
|
|
end process;
|
1791 |
|
|
|
1792 |
|
|
process (user_clk_out_int)
|
1793 |
|
|
begin
|
1794 |
|
|
if (user_clk_out_int'event and user_clk_out_int = '1') then
|
1795 |
|
|
|
1796 |
|
|
if (sys_rst_n = '0') then
|
1797 |
|
|
user_lnk_up_d <= '0' after (TCQ)*1 ps;
|
1798 |
|
|
else
|
1799 |
|
|
user_lnk_up_d <= trn_lnk_up after (TCQ)*1 ps;
|
1800 |
|
|
end if;
|
1801 |
|
|
end if;
|
1802 |
|
|
end process;
|
1803 |
|
|
|
1804 |
|
|
|
1805 |
|
|
-- Generate user_reset_out
|
1806 |
|
|
-- Once user reset output of PCIE and Phy Layer is active, de-assert reset
|
1807 |
|
|
-- Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise
|
1808 |
|
|
|
1809 |
|
|
process (user_clk_out_int,sys_or_hot_rst)
|
1810 |
|
|
begin
|
1811 |
|
|
if (sys_or_hot_rst = '1') then
|
1812 |
|
|
user_reset_int <= '1' after (TCQ)*1 ps;
|
1813 |
|
|
elsif (user_clk_out_int'event and user_clk_out_int = '1') then
|
1814 |
|
|
if (user_rst_n='1' and pl_phy_lnk_up_q='1') then
|
1815 |
|
|
user_reset_int <= '0' after (TCQ)*1 ps;
|
1816 |
|
|
end if;
|
1817 |
|
|
end if;
|
1818 |
|
|
end process;
|
1819 |
|
|
|
1820 |
|
|
process (user_clk_out_int,sys_or_hot_rst)
|
1821 |
|
|
begin
|
1822 |
|
|
if (sys_or_hot_rst = '1') then
|
1823 |
|
|
user_reset_out <= '1' after (TCQ)*1 ps;
|
1824 |
|
|
elsif (user_clk_out_int'event and user_clk_out_int = '1') then
|
1825 |
|
|
user_reset_out <= user_reset_int after (TCQ)*1 ps;
|
1826 |
|
|
end if;
|
1827 |
|
|
end process;
|
1828 |
|
|
|
1829 |
|
|
process (user_clk_out_int,sys_or_hot_rst)
|
1830 |
|
|
begin
|
1831 |
|
|
if (sys_or_hot_rst = '1') then
|
1832 |
|
|
bridge_reset_int <= '1' after (TCQ)*1 ps;
|
1833 |
|
|
elsif (user_clk_out_int'event and user_clk_out_int = '1') then
|
1834 |
|
|
if (user_rst_n='1' and pl_phy_lnk_up_q='1') then
|
1835 |
|
|
bridge_reset_int <= '0' after (TCQ)*1 ps;
|
1836 |
|
|
end if;
|
1837 |
|
|
end if;
|
1838 |
|
|
end process;
|
1839 |
|
|
|
1840 |
|
|
process (user_clk_out_int,sys_or_hot_rst)
|
1841 |
|
|
begin
|
1842 |
|
|
if (sys_or_hot_rst = '1') then
|
1843 |
|
|
bridge_reset_d <= '1' after (TCQ)*1 ps;
|
1844 |
|
|
elsif (user_clk_out_int'event and user_clk_out_int = '1') then
|
1845 |
|
|
bridge_reset_d <= bridge_reset_int after (TCQ)*1 ps;
|
1846 |
|
|
end if;
|
1847 |
|
|
end process;
|
1848 |
|
|
|
1849 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
1850 |
|
|
-- **** PCI Express Core Wrapper **** --
|
1851 |
|
|
-- The PCI Express Core Wrapper includes the following: --
|
1852 |
|
|
-- 1) AXI Streaming Bridge --
|
1853 |
|
|
-- 2) PCIE 2_1 Hard Block --
|
1854 |
|
|
-- 3) PCIE PIPE Interface Pipeline --
|
1855 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
1856 |
|
|
pcie_top_i : cl_a7pcie_x4_pcie_top
|
1857 |
|
|
generic map (
|
1858 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES ,
|
1859 |
|
|
AER_BASE_PTR => AER_BASE_PTR ,
|
1860 |
|
|
AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE ,
|
1861 |
|
|
AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE ,
|
1862 |
|
|
AER_CAP_ID => AER_CAP_ID ,
|
1863 |
|
|
AER_CAP_MULTIHEADER => AER_CAP_MULTIHEADER ,
|
1864 |
|
|
AER_CAP_NEXTPTR => AER_CAP_NEXTPTR ,
|
1865 |
|
|
AER_CAP_ON => AER_CAP_ON ,
|
1866 |
|
|
AER_CAP_OPTIONAL_ERR_SUPPORT => AER_CAP_OPTIONAL_ERR_SUPPORT ,
|
1867 |
|
|
AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE ,
|
1868 |
|
|
AER_CAP_VERSION => AER_CAP_VERSION ,
|
1869 |
|
|
ALLOW_X8_GEN2 => ALLOW_X8_GEN2 ,
|
1870 |
|
|
BAR0 => BAR0 ,
|
1871 |
|
|
BAR1 => BAR1 ,
|
1872 |
|
|
BAR2 => BAR2 ,
|
1873 |
|
|
BAR3 => BAR3 ,
|
1874 |
|
|
BAR4 => BAR4 ,
|
1875 |
|
|
BAR5 => BAR5 ,
|
1876 |
|
|
C_DATA_WIDTH => C_DATA_WIDTH ,
|
1877 |
|
|
C_REM_WIDTH => C_REM_WIDTH,
|
1878 |
|
|
CAPABILITIES_PTR => CAPABILITIES_PTR ,
|
1879 |
|
|
CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER ,
|
1880 |
|
|
CFG_ECRC_ERR_CPLSTAT => CFG_ECRC_ERR_CPLSTAT ,
|
1881 |
|
|
CLASS_CODE => CLASS_CODE ,
|
1882 |
|
|
CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED ,
|
1883 |
|
|
CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED ,
|
1884 |
|
|
CPL_TIMEOUT_RANGES_SUPPORTED => CPL_TIMEOUT_RANGES_SUPPORTED ,
|
1885 |
|
|
CRM_MODULE_RSTS => CRM_MODULE_RSTS ,
|
1886 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ,
|
1887 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ,
|
1888 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY ,
|
1889 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY ,
|
1890 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED ,
|
1891 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ,
|
1892 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED ,
|
1893 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ,
|
1894 |
|
|
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR ,
|
1895 |
|
|
DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12 ,
|
1896 |
|
|
DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16 ,
|
1897 |
|
|
DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29 ,
|
1898 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED ,
|
1899 |
|
|
DEV_CONTROL_EXT_TAG_DEFAULT => DEV_CONTROL_EXT_TAG_DEFAULT ,
|
1900 |
|
|
DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER ,
|
1901 |
|
|
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING ,
|
1902 |
|
|
DISABLE_ID_CHECK => DISABLE_ID_CHECK ,
|
1903 |
|
|
DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL ,
|
1904 |
|
|
DISABLE_RX_POISONED_RESP => DISABLE_RX_POISONED_RESP ,
|
1905 |
|
|
DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER ,
|
1906 |
|
|
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING ,
|
1907 |
|
|
DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM ,
|
1908 |
|
|
DSN_BASE_PTR => DSN_BASE_PTR ,
|
1909 |
|
|
DSN_CAP_ID => DSN_CAP_ID ,
|
1910 |
|
|
DSN_CAP_NEXTPTR => DSN_CAP_NEXTPTR ,
|
1911 |
|
|
DSN_CAP_ON => DSN_CAP_ON ,
|
1912 |
|
|
DSN_CAP_VERSION => DSN_CAP_VERSION ,
|
1913 |
|
|
DEV_CAP2_ARI_FORWARDING_SUPPORTED => DEV_CAP2_ARI_FORWARDING_SUPPORTED ,
|
1914 |
|
|
DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED => DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ,
|
1915 |
|
|
DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED => DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ,
|
1916 |
|
|
DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED => DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ,
|
1917 |
|
|
DEV_CAP2_CAS128_COMPLETER_SUPPORTED => DEV_CAP2_CAS128_COMPLETER_SUPPORTED ,
|
1918 |
|
|
DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED => DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ,
|
1919 |
|
|
DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED => DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ,
|
1920 |
|
|
DEV_CAP2_LTR_MECHANISM_SUPPORTED => DEV_CAP2_LTR_MECHANISM_SUPPORTED ,
|
1921 |
|
|
DEV_CAP2_MAX_ENDEND_TLP_PREFIXES => DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ,
|
1922 |
|
|
DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING => DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ,
|
1923 |
|
|
DEV_CAP2_TPH_COMPLETER_SUPPORTED => DEV_CAP2_TPH_COMPLETER_SUPPORTED ,
|
1924 |
|
|
DISABLE_ERR_MSG => DISABLE_ERR_MSG ,
|
1925 |
|
|
DISABLE_LOCKED_FILTER => DISABLE_LOCKED_FILTER ,
|
1926 |
|
|
DISABLE_PPM_FILTER => DISABLE_PPM_FILTER ,
|
1927 |
|
|
ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED => ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ,
|
1928 |
|
|
ENABLE_MSG_ROUTE => ENABLE_MSG_ROUTE ,
|
1929 |
|
|
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM ,
|
1930 |
|
|
ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0 ,
|
1931 |
|
|
EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI ,
|
1932 |
|
|
EXPANSION_ROM => EXPANSION_ROM ,
|
1933 |
|
|
EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR ,
|
1934 |
|
|
EXT_CFG_XP_CAP_PTR => EXT_CFG_XP_CAP_PTR ,
|
1935 |
|
|
HEADER_TYPE => HEADER_TYPE ,
|
1936 |
|
|
INFER_EI => INFER_EI ,
|
1937 |
|
|
INTERRUPT_PIN => pad_gen(INTERRUPT_PIN, 8) ,
|
1938 |
|
|
INTERRUPT_STAT_AUTO => INTERRUPT_STAT_AUTO ,
|
1939 |
|
|
IS_SWITCH => IS_SWITCH ,
|
1940 |
|
|
LAST_CONFIG_DWORD => LAST_CONFIG_DWORD ,
|
1941 |
|
|
LINK_CAP_ASPM_OPTIONALITY => LINK_CAP_ASPM_OPTIONALITY ,
|
1942 |
|
|
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT ,
|
1943 |
|
|
LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT ,
|
1944 |
|
|
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ,
|
1945 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ,
|
1946 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ,
|
1947 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1 ,
|
1948 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2 ,
|
1949 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ,
|
1950 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ,
|
1951 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1 ,
|
1952 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2 ,
|
1953 |
|
|
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ,
|
1954 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED ,
|
1955 |
|
|
LINK_CAP_MAX_LINK_SPEED_int => LINK_CAP_MAX_LINK_SPEED_int ,
|
1956 |
|
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH ,
|
1957 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int ,
|
1958 |
|
|
LINK_CAP_RSVD_23 => LINK_CAP_RSVD_23 ,
|
1959 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ,
|
1960 |
|
|
LINK_CONTROL_RCB => LINK_CONTROL_RCB ,
|
1961 |
|
|
LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS ,
|
1962 |
|
|
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ,
|
1963 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED => LINK_CTRL2_TARGET_LINK_SPEED ,
|
1964 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG ,
|
1965 |
|
|
LL_ACK_TIMEOUT => LL_ACK_TIMEOUT ,
|
1966 |
|
|
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN ,
|
1967 |
|
|
LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC ,
|
1968 |
|
|
LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT ,
|
1969 |
|
|
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN ,
|
1970 |
|
|
LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC ,
|
1971 |
|
|
LTSSM_MAX_LINK_WIDTH => LTSSM_MAX_LINK_WIDTH ,
|
1972 |
|
|
MPS_FORCE => MPS_FORCE,
|
1973 |
|
|
MSI_BASE_PTR => MSI_BASE_PTR ,
|
1974 |
|
|
MSI_CAP_ID => MSI_CAP_ID ,
|
1975 |
|
|
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP ,
|
1976 |
|
|
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION ,
|
1977 |
|
|
MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR ,
|
1978 |
|
|
MSI_CAP_ON => MSI_CAP_ON ,
|
1979 |
|
|
MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE ,
|
1980 |
|
|
MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE ,
|
1981 |
|
|
MSIX_BASE_PTR => MSIX_BASE_PTR ,
|
1982 |
|
|
MSIX_CAP_ID => MSIX_CAP_ID ,
|
1983 |
|
|
MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR ,
|
1984 |
|
|
MSIX_CAP_ON => MSIX_CAP_ON ,
|
1985 |
|
|
MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR ,
|
1986 |
|
|
MSIX_CAP_PBA_OFFSET => pad_gen(MSIX_CAP_PBA_OFFSET, 29) ,
|
1987 |
|
|
MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR ,
|
1988 |
|
|
MSIX_CAP_TABLE_OFFSET => pad_gen(MSIX_CAP_TABLE_OFFSET, 29) ,
|
1989 |
|
|
MSIX_CAP_TABLE_SIZE => pad_gen(MSIX_CAP_TABLE_SIZE, 11) ,
|
1990 |
|
|
N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1 ,
|
1991 |
|
|
N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2 ,
|
1992 |
|
|
N_FTS_GEN1 => N_FTS_GEN1 ,
|
1993 |
|
|
N_FTS_GEN2 => N_FTS_GEN2 ,
|
1994 |
|
|
PCIE_BASE_PTR => PCIE_BASE_PTR ,
|
1995 |
|
|
PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID ,
|
1996 |
|
|
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION ,
|
1997 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE ,
|
1998 |
|
|
PCIE_CAP_NEXTPTR => PCIE_CAP_NEXTPTR ,
|
1999 |
|
|
PCIE_CAP_ON => PCIE_CAP_ON ,
|
2000 |
|
|
PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14 ,
|
2001 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED ,
|
2002 |
|
|
PCIE_REVISION => PCIE_REVISION ,
|
2003 |
|
|
PL_AUTO_CONFIG => PL_AUTO_CONFIG ,
|
2004 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN ,
|
2005 |
|
|
PM_ASPML0S_TIMEOUT => PM_ASPML0S_TIMEOUT ,
|
2006 |
|
|
PM_ASPML0S_TIMEOUT_EN => PM_ASPML0S_TIMEOUT_EN ,
|
2007 |
|
|
PM_ASPML0S_TIMEOUT_FUNC => PM_ASPML0S_TIMEOUT_FUNC ,
|
2008 |
|
|
PM_ASPM_FASTEXIT => PM_ASPM_FASTEXIT ,
|
2009 |
|
|
PM_BASE_PTR => PM_BASE_PTR ,
|
2010 |
|
|
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT ,
|
2011 |
|
|
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT ,
|
2012 |
|
|
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT ,
|
2013 |
|
|
PM_CAP_DSI => PM_CAP_DSI ,
|
2014 |
|
|
PM_CAP_ID => PM_CAP_ID ,
|
2015 |
|
|
PM_CAP_NEXTPTR => PM_CAP_NEXTPTR ,
|
2016 |
|
|
PM_CAP_ON => PM_CAP_ON ,
|
2017 |
|
|
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK ,
|
2018 |
|
|
PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT ,
|
2019 |
|
|
PM_CAP_RSVD_04 => PM_CAP_RSVD_04 ,
|
2020 |
|
|
PM_CAP_VERSION => PM_CAP_VERSION ,
|
2021 |
|
|
PM_CSR_B2B3 => PM_CSR_B2B3 ,
|
2022 |
|
|
PM_CSR_BPCCEN => PM_CSR_BPCCEN ,
|
2023 |
|
|
PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST ,
|
2024 |
|
|
PM_DATA0 => PM_DATA0 ,
|
2025 |
|
|
PM_DATA1 => PM_DATA1 ,
|
2026 |
|
|
PM_DATA2 => PM_DATA2 ,
|
2027 |
|
|
PM_DATA3 => PM_DATA3 ,
|
2028 |
|
|
PM_DATA4 => PM_DATA4 ,
|
2029 |
|
|
PM_DATA5 => PM_DATA5 ,
|
2030 |
|
|
PM_DATA6 => PM_DATA6 ,
|
2031 |
|
|
PM_DATA7 => PM_DATA7 ,
|
2032 |
|
|
PM_DATA_SCALE0 => PM_DATA_SCALE0 ,
|
2033 |
|
|
PM_DATA_SCALE1 => PM_DATA_SCALE1 ,
|
2034 |
|
|
PM_DATA_SCALE2 => PM_DATA_SCALE2 ,
|
2035 |
|
|
PM_DATA_SCALE3 => PM_DATA_SCALE3 ,
|
2036 |
|
|
PM_DATA_SCALE4 => PM_DATA_SCALE4 ,
|
2037 |
|
|
PM_DATA_SCALE5 => PM_DATA_SCALE5 ,
|
2038 |
|
|
PM_DATA_SCALE6 => PM_DATA_SCALE6 ,
|
2039 |
|
|
PM_DATA_SCALE7 => PM_DATA_SCALE7 ,
|
2040 |
|
|
PM_MF => PM_MF ,
|
2041 |
|
|
RBAR_BASE_PTR => RBAR_BASE_PTR ,
|
2042 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR0 => RBAR_CAP_CONTROL_ENCODEDBAR0 ,
|
2043 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR1 => RBAR_CAP_CONTROL_ENCODEDBAR1 ,
|
2044 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR2 => RBAR_CAP_CONTROL_ENCODEDBAR2 ,
|
2045 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR3 => RBAR_CAP_CONTROL_ENCODEDBAR3 ,
|
2046 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR4 => RBAR_CAP_CONTROL_ENCODEDBAR4 ,
|
2047 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR5 => RBAR_CAP_CONTROL_ENCODEDBAR5 ,
|
2048 |
|
|
RBAR_CAP_ID => RBAR_CAP_ID,
|
2049 |
|
|
RBAR_CAP_INDEX0 => RBAR_CAP_INDEX0 ,
|
2050 |
|
|
RBAR_CAP_INDEX1 => RBAR_CAP_INDEX1 ,
|
2051 |
|
|
RBAR_CAP_INDEX2 => RBAR_CAP_INDEX2 ,
|
2052 |
|
|
RBAR_CAP_INDEX3 => RBAR_CAP_INDEX3 ,
|
2053 |
|
|
RBAR_CAP_INDEX4 => RBAR_CAP_INDEX4 ,
|
2054 |
|
|
RBAR_CAP_INDEX5 => RBAR_CAP_INDEX5 ,
|
2055 |
|
|
RBAR_CAP_NEXTPTR => RBAR_CAP_NEXTPTR ,
|
2056 |
|
|
RBAR_CAP_ON => RBAR_CAP_ON ,
|
2057 |
|
|
RBAR_CAP_SUP0 => pad_gen(RBAR_CAP_SUP0, 32) ,
|
2058 |
|
|
RBAR_CAP_SUP1 => pad_gen(RBAR_CAP_SUP1, 32) ,
|
2059 |
|
|
RBAR_CAP_SUP2 => pad_gen(RBAR_CAP_SUP2, 32) ,
|
2060 |
|
|
RBAR_CAP_SUP3 => pad_gen(RBAR_CAP_SUP3, 32) ,
|
2061 |
|
|
RBAR_CAP_SUP4 => pad_gen(RBAR_CAP_SUP4, 32) ,
|
2062 |
|
|
RBAR_CAP_SUP5 => pad_gen(RBAR_CAP_SUP5, 32) ,
|
2063 |
|
|
RBAR_CAP_VERSION => RBAR_CAP_VERSION ,
|
2064 |
|
|
RBAR_NUM => RBAR_NUM ,
|
2065 |
|
|
RECRC_CHK => RECRC_CHK ,
|
2066 |
|
|
RECRC_CHK_TRIM => RECRC_CHK_TRIM ,
|
2067 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY ,
|
2068 |
|
|
RP_AUTO_SPD => RP_AUTO_SPD ,
|
2069 |
|
|
RP_AUTO_SPD_LOOPCNT => RP_AUTO_SPD_LOOPCNT ,
|
2070 |
|
|
SELECT_DLL_IF => SELECT_DLL_IF ,
|
2071 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT ,
|
2072 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT ,
|
2073 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT ,
|
2074 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE ,
|
2075 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE ,
|
2076 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT ,
|
2077 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ,
|
2078 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM ,
|
2079 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT ,
|
2080 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT ,
|
2081 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE ,
|
2082 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE ,
|
2083 |
|
|
SPARE_BIT0 => SPARE_BIT0 ,
|
2084 |
|
|
SPARE_BIT1 => SPARE_BIT1 ,
|
2085 |
|
|
SPARE_BIT2 => SPARE_BIT2 ,
|
2086 |
|
|
SPARE_BIT3 => SPARE_BIT3 ,
|
2087 |
|
|
SPARE_BIT4 => SPARE_BIT4 ,
|
2088 |
|
|
SPARE_BIT5 => SPARE_BIT5 ,
|
2089 |
|
|
SPARE_BIT6 => SPARE_BIT6 ,
|
2090 |
|
|
SPARE_BIT7 => SPARE_BIT7 ,
|
2091 |
|
|
SPARE_BIT8 => SPARE_BIT8 ,
|
2092 |
|
|
SPARE_BYTE0 => SPARE_BYTE0 ,
|
2093 |
|
|
SPARE_BYTE1 => SPARE_BYTE1 ,
|
2094 |
|
|
SPARE_BYTE2 => SPARE_BYTE2 ,
|
2095 |
|
|
SPARE_BYTE3 => SPARE_BYTE3 ,
|
2096 |
|
|
SPARE_WORD0 => SPARE_WORD0 ,
|
2097 |
|
|
SPARE_WORD1 => SPARE_WORD1 ,
|
2098 |
|
|
SPARE_WORD2 => SPARE_WORD2 ,
|
2099 |
|
|
SPARE_WORD3 => SPARE_WORD3 ,
|
2100 |
|
|
SSL_MESSAGE_AUTO => SSL_MESSAGE_AUTO ,
|
2101 |
|
|
TECRC_EP_INV => TECRC_EP_INV ,
|
2102 |
|
|
TL_RBYPASS => TL_RBYPASS ,
|
2103 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY ,
|
2104 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY ,
|
2105 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY ,
|
2106 |
|
|
TL_TFC_DISABLE => TL_TFC_DISABLE ,
|
2107 |
|
|
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE ,
|
2108 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY ,
|
2109 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY ,
|
2110 |
|
|
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY ,
|
2111 |
|
|
TRN_DW => TRN_DW ,
|
2112 |
|
|
TRN_NP_FC => TRN_NP_FC ,
|
2113 |
|
|
UPCONFIG_CAPABLE => UPCONFIG_CAPABLE ,
|
2114 |
|
|
UPSTREAM_FACING => UPSTREAM_FACING ,
|
2115 |
|
|
UR_ATOMIC => UR_ATOMIC ,
|
2116 |
|
|
UR_CFG1 => UR_CFG1 ,
|
2117 |
|
|
UR_INV_REQ => UR_INV_REQ ,
|
2118 |
|
|
UR_PRS_RESPONSE => UR_PRS_RESPONSE ,
|
2119 |
|
|
USER_CLK2_DIV2 => USER_CLK2_DIV2 ,
|
2120 |
|
|
USER_CLK_FREQ => USER_CLK_FREQ ,
|
2121 |
|
|
USE_RID_PINS => USE_RID_PINS ,
|
2122 |
|
|
VC0_CPL_INFINITE => VC0_CPL_INFINITE ,
|
2123 |
|
|
VC0_RX_RAM_LIMIT => pad_gen(VC0_RX_RAM_LIMIT, 13) ,
|
2124 |
|
|
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD ,
|
2125 |
|
|
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH ,
|
2126 |
|
|
VC0_TOTAL_CREDITS_NPD => VC0_TOTAL_CREDITS_NPD,
|
2127 |
|
|
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH ,
|
2128 |
|
|
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD ,
|
2129 |
|
|
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH ,
|
2130 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET ,
|
2131 |
|
|
VC_BASE_PTR => pad_gen(VC_BASE_PTR, 12) ,
|
2132 |
|
|
VC_CAP_ID => VC_CAP_ID ,
|
2133 |
|
|
VC_CAP_NEXTPTR => VC_CAP_NEXTPTR ,
|
2134 |
|
|
VC_CAP_ON => VC_CAP_ON ,
|
2135 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS ,
|
2136 |
|
|
VC_CAP_VERSION => VC_CAP_VERSION ,
|
2137 |
|
|
VSEC_BASE_PTR => pad_gen(VSEC_BASE_PTR, 12) ,
|
2138 |
|
|
VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID ,
|
2139 |
|
|
VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH ,
|
2140 |
|
|
VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION ,
|
2141 |
|
|
VSEC_CAP_ID => VSEC_CAP_ID ,
|
2142 |
|
|
VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE ,
|
2143 |
|
|
VSEC_CAP_NEXTPTR => VSEC_CAP_NEXTPTR ,
|
2144 |
|
|
VSEC_CAP_ON => VSEC_CAP_ON ,
|
2145 |
|
|
VSEC_CAP_VERSION => VSEC_CAP_VERSION
|
2146 |
|
|
-- I/O
|
2147 |
|
|
)
|
2148 |
|
|
port map (
|
2149 |
|
|
|
2150 |
|
|
-- AXI Interface
|
2151 |
|
|
user_clk_out => user_clk_out_int ,
|
2152 |
|
|
user_reset => bridge_reset_d ,
|
2153 |
|
|
user_lnk_up => user_lnk_up_int ,
|
2154 |
|
|
|
2155 |
|
|
user_rst_n => user_rst_n ,
|
2156 |
|
|
trn_lnk_up => trn_lnk_up ,
|
2157 |
|
|
|
2158 |
|
|
tx_buf_av => tx_buf_av ,
|
2159 |
|
|
tx_err_drop => tx_err_drop ,
|
2160 |
|
|
tx_cfg_req => tx_cfg_req ,
|
2161 |
|
|
s_axis_tx_tready => s_axis_tx_tready ,
|
2162 |
|
|
s_axis_tx_tdata => s_axis_tx_tdata ,
|
2163 |
|
|
s_axis_tx_tkeep => s_axis_tx_tkeep ,
|
2164 |
|
|
s_axis_tx_tuser => s_axis_tx_tuser ,
|
2165 |
|
|
s_axis_tx_tlast => s_axis_tx_tlast ,
|
2166 |
|
|
s_axis_tx_tvalid => s_axis_tx_tvalid ,
|
2167 |
|
|
tx_cfg_gnt => tx_cfg_gnt ,
|
2168 |
|
|
|
2169 |
|
|
m_axis_rx_tdata => m_axis_rx_tdata ,
|
2170 |
|
|
m_axis_rx_tkeep => m_axis_rx_tkeep ,
|
2171 |
|
|
m_axis_rx_tlast => m_axis_rx_tlast ,
|
2172 |
|
|
m_axis_rx_tvalid => m_axis_rx_tvalid ,
|
2173 |
|
|
m_axis_rx_tready => m_axis_rx_tready ,
|
2174 |
|
|
m_axis_rx_tuser => m_axis_rx_tuser ,
|
2175 |
|
|
rx_np_ok => rx_np_ok ,
|
2176 |
|
|
rx_np_req => rx_np_req ,
|
2177 |
|
|
|
2178 |
|
|
fc_cpld => fc_cpld ,
|
2179 |
|
|
fc_cplh => fc_cplh ,
|
2180 |
|
|
fc_npd => fc_npd ,
|
2181 |
|
|
fc_nph => fc_nph ,
|
2182 |
|
|
fc_pd => fc_pd ,
|
2183 |
|
|
fc_ph => fc_ph ,
|
2184 |
|
|
fc_sel => fc_sel ,
|
2185 |
|
|
cfg_turnoff_ok => cfg_turnoff_ok ,
|
2186 |
|
|
cfg_received_func_lvl_rst => cfg_received_func_lvl_rst ,
|
2187 |
|
|
|
2188 |
|
|
cm_rst_n => '1' ,
|
2189 |
|
|
func_lvl_rst_n => '1' ,
|
2190 |
|
|
|
2191 |
|
|
cfg_dev_id => cfg_dev_id_wire ,
|
2192 |
|
|
cfg_vend_id => cfg_vend_id_wire ,
|
2193 |
|
|
cfg_rev_id => cfg_rev_id_wire ,
|
2194 |
|
|
cfg_subsys_id => cfg_subsys_id_wire ,
|
2195 |
|
|
cfg_subsys_vend_id => cfg_subsys_vend_id_wire ,
|
2196 |
|
|
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum ,
|
2197 |
|
|
|
2198 |
|
|
cfg_bridge_serr_en => cfg_bridge_serr_en ,
|
2199 |
|
|
cfg_status => cfg_status ,
|
2200 |
|
|
cfg_command => cfg_command ,
|
2201 |
|
|
cfg_dstatus => cfg_dstatus ,
|
2202 |
|
|
cfg_dcommand => cfg_dcommand ,
|
2203 |
|
|
cfg_lstatus => cfg_lstatus ,
|
2204 |
|
|
cfg_lcommand => cfg_lcommand ,
|
2205 |
|
|
cfg_dcommand2 => cfg_dcommand2 ,
|
2206 |
|
|
|
2207 |
|
|
cfg_command_bus_master_enable => open ,
|
2208 |
|
|
cfg_command_interrupt_disable => open ,
|
2209 |
|
|
cfg_command_io_enable => open ,
|
2210 |
|
|
cfg_command_mem_enable => open ,
|
2211 |
|
|
cfg_command_serr_en => open ,
|
2212 |
|
|
cfg_dev_control_aux_power_en => open ,
|
2213 |
|
|
cfg_dev_control_corr_err_reporting_en => open ,
|
2214 |
|
|
cfg_dev_control_enable_ro => open ,
|
2215 |
|
|
cfg_dev_control_ext_tag_en => open ,
|
2216 |
|
|
cfg_dev_control_fatal_err_reporting_en => open ,
|
2217 |
|
|
cfg_dev_control_max_payload => open ,
|
2218 |
|
|
cfg_dev_control_max_read_req => open ,
|
2219 |
|
|
cfg_dev_control_non_fatal_reporting_en => open ,
|
2220 |
|
|
cfg_dev_control_no_snoop_en => open ,
|
2221 |
|
|
cfg_dev_control_phantom_en => open ,
|
2222 |
|
|
cfg_dev_control_ur_err_reporting_en => open ,
|
2223 |
|
|
cfg_dev_control2_cpl_timeout_dis => open ,
|
2224 |
|
|
cfg_dev_control2_cpl_timeout_val => open ,
|
2225 |
|
|
cfg_dev_control2_ari_forward_en => open ,
|
2226 |
|
|
cfg_dev_control2_atomic_requester_en => open ,
|
2227 |
|
|
cfg_dev_control2_atomic_egress_block => open ,
|
2228 |
|
|
cfg_dev_control2_ido_req_en => open ,
|
2229 |
|
|
cfg_dev_control2_ido_cpl_en => open ,
|
2230 |
|
|
cfg_dev_control2_ltr_en => open ,
|
2231 |
|
|
cfg_dev_control2_tlp_prefix_block => open ,
|
2232 |
|
|
cfg_dev_status_corr_err_detected => open ,
|
2233 |
|
|
cfg_dev_status_fatal_err_detected => open ,
|
2234 |
|
|
cfg_dev_status_non_fatal_err_detected => open ,
|
2235 |
|
|
cfg_dev_status_ur_detected => open ,
|
2236 |
|
|
|
2237 |
|
|
cfg_mgmt_do => cfg_mgmt_do ,
|
2238 |
|
|
cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set ,
|
2239 |
|
|
cfg_err_aer_headerlog => cfg_err_aer_headerlog ,
|
2240 |
|
|
cfg_err_cpl_rdy => cfg_err_cpl_rdy ,
|
2241 |
|
|
cfg_interrupt_do => cfg_interrupt_do ,
|
2242 |
|
|
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
|
2243 |
|
|
cfg_interrupt_msienable => cfg_interrupt_msienable ,
|
2244 |
|
|
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
|
2245 |
|
|
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
|
2246 |
|
|
cfg_interrupt_rdy => cfg_interrupt_rdy ,
|
2247 |
|
|
cfg_link_control_rcb => open ,
|
2248 |
|
|
cfg_link_control_aspm_control => open ,
|
2249 |
|
|
cfg_link_control_auto_bandwidth_int_en => open ,
|
2250 |
|
|
cfg_link_control_bandwidth_int_en => open ,
|
2251 |
|
|
cfg_link_control_clock_pm_en => open ,
|
2252 |
|
|
cfg_link_control_common_clock => open ,
|
2253 |
|
|
cfg_link_control_extended_sync => open ,
|
2254 |
|
|
cfg_link_control_hw_auto_width_dis => open ,
|
2255 |
|
|
cfg_link_control_link_disable => open ,
|
2256 |
|
|
cfg_link_control_retrain_link => open ,
|
2257 |
|
|
cfg_link_status_auto_bandwidth_status => open ,
|
2258 |
|
|
cfg_link_status_bandwidth_status => open ,
|
2259 |
|
|
cfg_link_status_current_speed => open ,
|
2260 |
|
|
cfg_link_status_dll_active => open ,
|
2261 |
|
|
cfg_link_status_link_training => open ,
|
2262 |
|
|
cfg_link_status_negotiated_width => open ,
|
2263 |
|
|
cfg_msg_data => cfg_msg_data ,
|
2264 |
|
|
cfg_msg_received => cfg_msg_received ,
|
2265 |
|
|
cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a ,
|
2266 |
|
|
cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b ,
|
2267 |
|
|
cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c ,
|
2268 |
|
|
cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d ,
|
2269 |
|
|
cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a ,
|
2270 |
|
|
cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b ,
|
2271 |
|
|
cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c ,
|
2272 |
|
|
cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d ,
|
2273 |
|
|
cfg_msg_received_err_cor => cfg_msg_received_err_cor ,
|
2274 |
|
|
cfg_msg_received_err_fatal => cfg_msg_received_err_fatal ,
|
2275 |
|
|
cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal ,
|
2276 |
|
|
cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak ,
|
2277 |
|
|
cfg_msg_received_pme_to => open ,
|
2278 |
|
|
cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack ,
|
2279 |
|
|
cfg_msg_received_pm_pme => cfg_msg_received_pm_pme ,
|
2280 |
|
|
cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit ,
|
2281 |
|
|
cfg_msg_received_unlock => open ,
|
2282 |
|
|
cfg_to_turnoff => cfg_to_turnoff ,
|
2283 |
|
|
cfg_pcie_link_state => cfg_pcie_link_state ,
|
2284 |
|
|
cfg_pmcsr_pme_en => cfg_pmcsr_pme_en ,
|
2285 |
|
|
cfg_pmcsr_powerstate => cfg_pmcsr_powerstate ,
|
2286 |
|
|
cfg_pmcsr_pme_status => cfg_pmcsr_pme_status ,
|
2287 |
|
|
cfg_pm_rcv_as_req_l1_n => open ,
|
2288 |
|
|
cfg_pm_rcv_enter_l1_n => open ,
|
2289 |
|
|
cfg_pm_rcv_enter_l23_n => open ,
|
2290 |
|
|
cfg_pm_rcv_req_ack_n => open ,
|
2291 |
|
|
cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done ,
|
2292 |
|
|
cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse ,
|
2293 |
|
|
cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en ,
|
2294 |
|
|
cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en ,
|
2295 |
|
|
cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en ,
|
2296 |
|
|
cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
|
2297 |
|
|
cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en ,
|
2298 |
|
|
cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en ,
|
2299 |
|
|
cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en ,
|
2300 |
|
|
cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en ,
|
2301 |
|
|
cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en ,
|
2302 |
|
|
cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received ,
|
2303 |
|
|
cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received ,
|
2304 |
|
|
cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received ,
|
2305 |
|
|
cfg_aer_interrupt_msgnum => cfg_aer_interrupt_msgnum ,
|
2306 |
|
|
cfg_transaction => open ,
|
2307 |
|
|
cfg_transaction_addr => open ,
|
2308 |
|
|
cfg_transaction_type => open ,
|
2309 |
|
|
cfg_vc_tcvc_map => cfg_vc_tcvc_map ,
|
2310 |
|
|
cfg_mgmt_byte_en_n => cfg_mgmt_byte_en_int_n ,
|
2311 |
|
|
cfg_mgmt_di => cfg_mgmt_di ,
|
2312 |
|
|
cfg_dsn => cfg_dsn ,
|
2313 |
|
|
cfg_mgmt_dwaddr => cfg_mgmt_dwaddr ,
|
2314 |
|
|
cfg_err_acs_n => '1' ,
|
2315 |
|
|
cfg_err_cor_n => cfg_err_cor_int_n ,
|
2316 |
|
|
cfg_err_cpl_abort_n => cfg_err_cpl_abort_int_n ,
|
2317 |
|
|
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_int_n ,
|
2318 |
|
|
cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_int_n ,
|
2319 |
|
|
cfg_err_ecrc_n => cfg_err_ecrc_int_n ,
|
2320 |
|
|
cfg_err_locked_n => cfg_err_locked_int_n ,
|
2321 |
|
|
cfg_err_posted_n => cfg_err_posted_int_n ,
|
2322 |
|
|
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header ,
|
2323 |
|
|
cfg_err_ur_n => cfg_err_ur_int_n ,
|
2324 |
|
|
cfg_err_malformed_n => cfg_err_malformed_int_n ,
|
2325 |
|
|
cfg_err_poisoned_n => cfg_err_poisoned_int_n ,
|
2326 |
|
|
cfg_err_atomic_egress_blocked_n => cfg_err_atomic_egress_blocked_int_n ,
|
2327 |
|
|
cfg_err_mc_blocked_n => cfg_err_mc_blocked_int_n ,
|
2328 |
|
|
cfg_err_internal_uncor_n => cfg_err_internal_uncor_int_n ,
|
2329 |
|
|
cfg_err_internal_cor_n => cfg_err_internal_cor_int_n ,
|
2330 |
|
|
cfg_err_norecovery_n => cfg_err_norecovery_int_n ,
|
2331 |
|
|
|
2332 |
|
|
cfg_interrupt_assert_n => cfg_interrupt_assert_int_n ,
|
2333 |
|
|
cfg_interrupt_di => cfg_interrupt_di ,
|
2334 |
|
|
cfg_interrupt_n => cfg_interrupt_int_n ,
|
2335 |
|
|
cfg_interrupt_stat_n => cfg_interrupt_stat_int_n ,
|
2336 |
|
|
cfg_bus_number => cfg_bus_number,
|
2337 |
|
|
cfg_device_number => cfg_device_number,
|
2338 |
|
|
cfg_function_number => cfg_function_number,
|
2339 |
|
|
cfg_ds_bus_number => cfg_ds_bus_number ,
|
2340 |
|
|
cfg_ds_device_number => cfg_ds_device_number ,
|
2341 |
|
|
cfg_ds_function_number => cfg_ds_function_number ,
|
2342 |
|
|
cfg_pm_send_pme_to_n => '1' ,
|
2343 |
|
|
cfg_pm_wake_n => cfg_pm_wake_int_n ,
|
2344 |
|
|
cfg_pm_halt_aspm_l0s_n => cfg_pm_halt_aspm_l0s_int_n ,
|
2345 |
|
|
cfg_pm_halt_aspm_l1_n => cfg_pm_halt_aspm_l1_int_n ,
|
2346 |
|
|
cfg_pm_force_state_en_n => cfg_pm_force_state_en_int_n ,
|
2347 |
|
|
cfg_pm_force_state => cfg_pm_force_state ,
|
2348 |
|
|
cfg_force_mps => "000" ,
|
2349 |
|
|
cfg_force_common_clock_off => '0' ,
|
2350 |
|
|
cfg_force_extended_sync_on => '0' ,
|
2351 |
|
|
cfg_port_number => x"00" ,
|
2352 |
|
|
cfg_mgmt_rd_en_n => cfg_mgmt_rd_en_int_n ,
|
2353 |
|
|
cfg_trn_pending => cfg_trn_pending ,
|
2354 |
|
|
cfg_mgmt_wr_en_n => cfg_mgmt_wr_en_int_n ,
|
2355 |
|
|
cfg_mgmt_wr_readonly_n => cfg_mgmt_wr_readonly_int_n ,
|
2356 |
|
|
cfg_mgmt_wr_rw1c_as_rw_n => cfg_mgmt_wr_rw1c_as_rw_int_n ,
|
2357 |
|
|
|
2358 |
|
|
pl_initial_link_width => pl_initial_link_width ,
|
2359 |
|
|
pl_lane_reversal_mode => pl_lane_reversal_mode ,
|
2360 |
|
|
pl_link_gen2_cap => pl_link_gen2_cap ,
|
2361 |
|
|
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
|
2362 |
|
|
pl_link_upcfg_cap => pl_link_upcfg_cap ,
|
2363 |
|
|
pl_ltssm_state => pl_ltssm_state_int ,
|
2364 |
|
|
pl_phy_lnk_up => pl_phy_lnk_up_int ,
|
2365 |
|
|
pl_received_hot_rst => pl_received_hot_rst_int ,
|
2366 |
|
|
pl_rx_pm_state => pl_rx_pm_state ,
|
2367 |
|
|
pl_sel_lnk_rate => pl_sel_lnk_rate ,
|
2368 |
|
|
pl_sel_lnk_width => pl_sel_lnk_width ,
|
2369 |
|
|
pl_tx_pm_state => pl_tx_pm_state ,
|
2370 |
|
|
pl_directed_link_auton => pl_directed_link_auton ,
|
2371 |
|
|
pl_directed_link_change => pl_directed_link_change ,
|
2372 |
|
|
pl_directed_link_speed => pl_directed_link_speed ,
|
2373 |
|
|
pl_directed_link_width => pl_directed_link_width ,
|
2374 |
|
|
pl_downstream_deemph_source => pl_downstream_deemph_source ,
|
2375 |
|
|
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
|
2376 |
|
|
pl_transmit_hot_rst => pl_transmit_hot_rst ,
|
2377 |
|
|
pl_directed_ltssm_new_vld => '0' ,
|
2378 |
|
|
pl_directed_ltssm_new => "000000" ,
|
2379 |
|
|
pl_directed_ltssm_stall => '0' ,
|
2380 |
|
|
pl_directed_change_done => pl_directed_change_done ,
|
2381 |
|
|
|
2382 |
|
|
phy_rdy_n => phy_rdy_n ,
|
2383 |
|
|
dbg_sclr_a => open ,
|
2384 |
|
|
dbg_sclr_b => open ,
|
2385 |
|
|
dbg_sclr_c => open ,
|
2386 |
|
|
dbg_sclr_d => open ,
|
2387 |
|
|
dbg_sclr_e => open ,
|
2388 |
|
|
dbg_sclr_f => open ,
|
2389 |
|
|
dbg_sclr_g => open ,
|
2390 |
|
|
dbg_sclr_h => open ,
|
2391 |
|
|
dbg_sclr_i => open ,
|
2392 |
|
|
dbg_sclr_j => open ,
|
2393 |
|
|
dbg_sclr_k => open ,
|
2394 |
|
|
|
2395 |
|
|
dbg_vec_a => open ,
|
2396 |
|
|
dbg_vec_b => open ,
|
2397 |
|
|
dbg_vec_c => open ,
|
2398 |
|
|
pl_dbg_vec => open ,
|
2399 |
|
|
trn_rdllp_data => open ,
|
2400 |
|
|
trn_rdllp_src_rdy => open ,
|
2401 |
|
|
dbg_mode => "00" ,
|
2402 |
|
|
dbg_sub_mode => '0' ,
|
2403 |
|
|
pl_dbg_mode => "000" ,
|
2404 |
|
|
|
2405 |
|
|
|
2406 |
|
|
drp_clk => '0',
|
2407 |
|
|
drp_en => '0',
|
2408 |
|
|
drp_we => '0',
|
2409 |
|
|
drp_addr => "000000000",
|
2410 |
|
|
drp_di => X"0000",
|
2411 |
|
|
drp_do => open,
|
2412 |
|
|
drp_rdy => open,
|
2413 |
|
|
-- Pipe Interface
|
2414 |
|
|
|
2415 |
|
|
pipe_clk => pipe_clk ,
|
2416 |
|
|
user_clk => user_clk ,
|
2417 |
|
|
user_clk2 => user_clk2 ,
|
2418 |
|
|
pipe_rx0_polarity_gt => pipe_rx0_polarity_gt ,
|
2419 |
|
|
pipe_rx1_polarity_gt => pipe_rx1_polarity_gt ,
|
2420 |
|
|
pipe_rx2_polarity_gt => pipe_rx2_polarity_gt ,
|
2421 |
|
|
pipe_rx3_polarity_gt => pipe_rx3_polarity_gt ,
|
2422 |
|
|
pipe_rx4_polarity_gt => pipe_rx4_polarity_gt ,
|
2423 |
|
|
pipe_rx5_polarity_gt => pipe_rx5_polarity_gt ,
|
2424 |
|
|
pipe_rx6_polarity_gt => pipe_rx6_polarity_gt ,
|
2425 |
|
|
pipe_rx7_polarity_gt => pipe_rx7_polarity_gt ,
|
2426 |
|
|
pipe_tx_deemph_gt => pipe_tx_deemph_gt ,
|
2427 |
|
|
pipe_tx_margin_gt => pipe_tx_margin_gt ,
|
2428 |
|
|
pipe_tx_rate_gt => pipe_tx_rate_gt ,
|
2429 |
|
|
pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt ,
|
2430 |
|
|
pipe_tx0_char_is_k_gt => pipe_tx0_char_is_k_gt ,
|
2431 |
|
|
pipe_tx0_compliance_gt => pipe_tx0_compliance_gt ,
|
2432 |
|
|
pipe_tx0_data_gt => pipe_tx0_data_gt ,
|
2433 |
|
|
pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt ,
|
2434 |
|
|
pipe_tx0_powerdown_gt => pipe_tx0_powerdown_gt ,
|
2435 |
|
|
pipe_tx1_char_is_k_gt => pipe_tx1_char_is_k_gt ,
|
2436 |
|
|
pipe_tx1_compliance_gt => pipe_tx1_compliance_gt ,
|
2437 |
|
|
pipe_tx1_data_gt => pipe_tx1_data_gt ,
|
2438 |
|
|
pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt ,
|
2439 |
|
|
pipe_tx1_powerdown_gt => pipe_tx1_powerdown_gt ,
|
2440 |
|
|
pipe_tx2_char_is_k_gt => pipe_tx2_char_is_k_gt ,
|
2441 |
|
|
pipe_tx2_compliance_gt => pipe_tx2_compliance_gt ,
|
2442 |
|
|
pipe_tx2_data_gt => pipe_tx2_data_gt ,
|
2443 |
|
|
pipe_tx2_elec_idle_gt => pipe_tx2_elec_idle_gt ,
|
2444 |
|
|
pipe_tx2_powerdown_gt => pipe_tx2_powerdown_gt ,
|
2445 |
|
|
pipe_tx3_char_is_k_gt => pipe_tx3_char_is_k_gt ,
|
2446 |
|
|
pipe_tx3_compliance_gt => pipe_tx3_compliance_gt ,
|
2447 |
|
|
pipe_tx3_data_gt => pipe_tx3_data_gt ,
|
2448 |
|
|
pipe_tx3_elec_idle_gt => pipe_tx3_elec_idle_gt ,
|
2449 |
|
|
pipe_tx3_powerdown_gt => pipe_tx3_powerdown_gt ,
|
2450 |
|
|
pipe_tx4_char_is_k_gt => pipe_tx4_char_is_k_gt ,
|
2451 |
|
|
pipe_tx4_compliance_gt => pipe_tx4_compliance_gt ,
|
2452 |
|
|
pipe_tx4_data_gt => pipe_tx4_data_gt ,
|
2453 |
|
|
pipe_tx4_elec_idle_gt => pipe_tx4_elec_idle_gt ,
|
2454 |
|
|
pipe_tx4_powerdown_gt => pipe_tx4_powerdown_gt ,
|
2455 |
|
|
pipe_tx5_char_is_k_gt => pipe_tx5_char_is_k_gt ,
|
2456 |
|
|
pipe_tx5_compliance_gt => pipe_tx5_compliance_gt ,
|
2457 |
|
|
pipe_tx5_data_gt => pipe_tx5_data_gt ,
|
2458 |
|
|
pipe_tx5_elec_idle_gt => pipe_tx5_elec_idle_gt ,
|
2459 |
|
|
pipe_tx5_powerdown_gt => pipe_tx5_powerdown_gt ,
|
2460 |
|
|
pipe_tx6_char_is_k_gt => pipe_tx6_char_is_k_gt ,
|
2461 |
|
|
pipe_tx6_compliance_gt => pipe_tx6_compliance_gt ,
|
2462 |
|
|
pipe_tx6_data_gt => pipe_tx6_data_gt ,
|
2463 |
|
|
pipe_tx6_elec_idle_gt => pipe_tx6_elec_idle_gt ,
|
2464 |
|
|
pipe_tx6_powerdown_gt => pipe_tx6_powerdown_gt ,
|
2465 |
|
|
pipe_tx7_char_is_k_gt => pipe_tx7_char_is_k_gt ,
|
2466 |
|
|
pipe_tx7_compliance_gt => pipe_tx7_compliance_gt ,
|
2467 |
|
|
pipe_tx7_data_gt => pipe_tx7_data_gt ,
|
2468 |
|
|
pipe_tx7_elec_idle_gt => pipe_tx7_elec_idle_gt ,
|
2469 |
|
|
pipe_tx7_powerdown_gt => pipe_tx7_powerdown_gt ,
|
2470 |
|
|
|
2471 |
|
|
pipe_rx0_chanisaligned_gt => pipe_rx0_chanisaligned_gt ,
|
2472 |
|
|
pipe_rx0_char_is_k_gt => pipe_rx0_char_is_k_gt ,
|
2473 |
|
|
pipe_rx0_data_gt => pipe_rx0_data_gt ,
|
2474 |
|
|
pipe_rx0_elec_idle_gt => pipe_rx0_elec_idle_gt ,
|
2475 |
|
|
pipe_rx0_phy_status_gt => pipe_rx0_phy_status_gt ,
|
2476 |
|
|
pipe_rx0_status_gt => pipe_rx0_status_gt ,
|
2477 |
|
|
pipe_rx0_valid_gt => pipe_rx0_valid_gt ,
|
2478 |
|
|
pipe_rx1_chanisaligned_gt => pipe_rx1_chanisaligned_gt ,
|
2479 |
|
|
pipe_rx1_char_is_k_gt => pipe_rx1_char_is_k_gt ,
|
2480 |
|
|
pipe_rx1_data_gt => pipe_rx1_data_gt ,
|
2481 |
|
|
pipe_rx1_elec_idle_gt => pipe_rx1_elec_idle_gt ,
|
2482 |
|
|
pipe_rx1_phy_status_gt => pipe_rx1_phy_status_gt ,
|
2483 |
|
|
pipe_rx1_status_gt => pipe_rx1_status_gt ,
|
2484 |
|
|
pipe_rx1_valid_gt => pipe_rx1_valid_gt ,
|
2485 |
|
|
pipe_rx2_chanisaligned_gt => pipe_rx2_chanisaligned_gt ,
|
2486 |
|
|
pipe_rx2_char_is_k_gt => pipe_rx2_char_is_k_gt ,
|
2487 |
|
|
pipe_rx2_data_gt => pipe_rx2_data_gt ,
|
2488 |
|
|
pipe_rx2_elec_idle_gt => pipe_rx2_elec_idle_gt ,
|
2489 |
|
|
pipe_rx2_phy_status_gt => pipe_rx2_phy_status_gt ,
|
2490 |
|
|
pipe_rx2_status_gt => pipe_rx2_status_gt ,
|
2491 |
|
|
pipe_rx2_valid_gt => pipe_rx2_valid_gt ,
|
2492 |
|
|
pipe_rx3_chanisaligned_gt => pipe_rx3_chanisaligned_gt ,
|
2493 |
|
|
pipe_rx3_char_is_k_gt => pipe_rx3_char_is_k_gt ,
|
2494 |
|
|
pipe_rx3_data_gt => pipe_rx3_data_gt ,
|
2495 |
|
|
pipe_rx3_elec_idle_gt => pipe_rx3_elec_idle_gt ,
|
2496 |
|
|
pipe_rx3_phy_status_gt => pipe_rx3_phy_status_gt ,
|
2497 |
|
|
pipe_rx3_status_gt => pipe_rx3_status_gt ,
|
2498 |
|
|
pipe_rx3_valid_gt => pipe_rx3_valid_gt ,
|
2499 |
|
|
pipe_rx4_chanisaligned_gt => pipe_rx4_chanisaligned_gt ,
|
2500 |
|
|
pipe_rx4_char_is_k_gt => pipe_rx4_char_is_k_gt ,
|
2501 |
|
|
pipe_rx4_data_gt => pipe_rx4_data_gt ,
|
2502 |
|
|
pipe_rx4_elec_idle_gt => pipe_rx4_elec_idle_gt ,
|
2503 |
|
|
pipe_rx4_phy_status_gt => pipe_rx4_phy_status_gt ,
|
2504 |
|
|
pipe_rx4_status_gt => pipe_rx4_status_gt ,
|
2505 |
|
|
pipe_rx4_valid_gt => pipe_rx4_valid_gt ,
|
2506 |
|
|
pipe_rx5_chanisaligned_gt => pipe_rx5_chanisaligned_gt ,
|
2507 |
|
|
pipe_rx5_char_is_k_gt => pipe_rx5_char_is_k_gt ,
|
2508 |
|
|
pipe_rx5_data_gt => pipe_rx5_data_gt ,
|
2509 |
|
|
pipe_rx5_elec_idle_gt => pipe_rx5_elec_idle_gt ,
|
2510 |
|
|
pipe_rx5_phy_status_gt => pipe_rx5_phy_status_gt ,
|
2511 |
|
|
pipe_rx5_status_gt => pipe_rx5_status_gt ,
|
2512 |
|
|
pipe_rx5_valid_gt => pipe_rx5_valid_gt ,
|
2513 |
|
|
pipe_rx6_chanisaligned_gt => pipe_rx6_chanisaligned_gt ,
|
2514 |
|
|
pipe_rx6_char_is_k_gt => pipe_rx6_char_is_k_gt ,
|
2515 |
|
|
pipe_rx6_data_gt => pipe_rx6_data_gt ,
|
2516 |
|
|
pipe_rx6_elec_idle_gt => pipe_rx6_elec_idle_gt ,
|
2517 |
|
|
pipe_rx6_phy_status_gt => pipe_rx6_phy_status_gt ,
|
2518 |
|
|
pipe_rx6_status_gt => pipe_rx6_status_gt ,
|
2519 |
|
|
pipe_rx6_valid_gt => pipe_rx6_valid_gt ,
|
2520 |
|
|
pipe_rx7_chanisaligned_gt => pipe_rx7_chanisaligned_gt ,
|
2521 |
|
|
pipe_rx7_char_is_k_gt => pipe_rx7_char_is_k_gt ,
|
2522 |
|
|
pipe_rx7_data_gt => pipe_rx7_data_gt ,
|
2523 |
|
|
pipe_rx7_elec_idle_gt => pipe_rx7_elec_idle_gt ,
|
2524 |
|
|
pipe_rx7_phy_status_gt => pipe_rx7_phy_status_gt ,
|
2525 |
|
|
pipe_rx7_status_gt => pipe_rx7_status_gt ,
|
2526 |
|
|
pipe_rx7_valid_gt => pipe_rx7_valid_gt
|
2527 |
|
|
|
2528 |
|
|
);
|
2529 |
|
|
|
2530 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
2531 |
|
|
-- **** V7/K7/A7 GTX Wrapper **** --
|
2532 |
|
|
-- The 7-Series GTX Wrapper includes the following: --
|
2533 |
|
|
-- 1) Virtex-7 GTX --
|
2534 |
|
|
-- 2) Kintex-7 GTX --
|
2535 |
|
|
-- 3) Artix-7 GTP --
|
2536 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
2537 |
|
|
gt_top_i : cl_a7pcie_x4_gt_top
|
2538 |
|
|
generic map (
|
2539 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int,
|
2540 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ,
|
2541 |
|
|
USER_CLK_FREQ => USER_CLK_FREQ,
|
2542 |
|
|
USER_CLK2_DIV2 => USER_CLK2_DIV2,
|
2543 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN,
|
2544 |
|
|
PCIE_EXT_CLK => PCIE_EXT_CLK,
|
2545 |
|
|
PCIE_USE_MODE => PCIE_USE_MODE,
|
2546 |
|
|
PCIE_GT_DEVICE => PCIE_GT_DEVICE,
|
2547 |
|
|
PCIE_PLL_SEL => PCIE_PLL_SEL,
|
2548 |
|
|
PCIE_ASYNC_EN => PCIE_ASYNC_EN,
|
2549 |
|
|
PCIE_TXBUF_EN => PCIE_TXBUF_EN,
|
2550 |
|
|
PCIE_CHAN_BOND => PCIE_CHAN_BOND
|
2551 |
|
|
)
|
2552 |
|
|
port map (
|
2553 |
|
|
-- pl ltssm
|
2554 |
|
|
pl_ltssm_state => pl_ltssm_state_int ,
|
2555 |
|
|
|
2556 |
|
|
-- Pipe Common Signals
|
2557 |
|
|
pipe_tx_rcvr_det => pipe_tx_rcvr_det_gt ,
|
2558 |
|
|
pipe_tx_reset => '0' ,
|
2559 |
|
|
pipe_tx_rate => pipe_tx_rate_gt ,
|
2560 |
|
|
pipe_tx_deemph => pipe_tx_deemph_gt ,
|
2561 |
|
|
pipe_tx_margin => pipe_tx_margin_gt ,
|
2562 |
|
|
pipe_tx_swing => '0' ,
|
2563 |
|
|
|
2564 |
|
|
PIPE_PCLK_IN => PIPE_PCLK_IN ,
|
2565 |
|
|
PIPE_RXUSRCLK_IN => PIPE_RXUSRCLK_IN ,
|
2566 |
|
|
PIPE_RXOUTCLK_IN => PIPE_RXOUTCLK_IN ,
|
2567 |
|
|
PIPE_DCLK_IN => PIPE_DCLK_IN ,
|
2568 |
|
|
PIPE_USERCLK1_IN => PIPE_USERCLK1_IN ,
|
2569 |
|
|
PIPE_USERCLK2_IN => PIPE_USERCLK2_IN ,
|
2570 |
|
|
PIPE_OOBCLK_IN => PIPE_OOBCLK_IN,
|
2571 |
|
|
PIPE_MMCM_LOCK_IN => PIPE_MMCM_LOCK_IN,
|
2572 |
|
|
|
2573 |
|
|
PIPE_TXOUTCLK_OUT => PIPE_TXOUTCLK_OUT,
|
2574 |
|
|
PIPE_RXOUTCLK_OUT => PIPE_RXOUTCLK_OUT,
|
2575 |
|
|
PIPE_PCLK_SEL_OUT => PIPE_PCLK_SEL_OUT,
|
2576 |
|
|
PIPE_GEN3_OUT => PIPE_GEN3_OUT ,
|
2577 |
|
|
|
2578 |
|
|
-- Pipe Per-Lane Signals - Lane 0
|
2579 |
|
|
pipe_rx0_char_is_k => pipe_rx0_char_is_k_gt ,
|
2580 |
|
|
pipe_rx0_data => pipe_rx0_data_gt ,
|
2581 |
|
|
pipe_rx0_valid => pipe_rx0_valid_gt ,
|
2582 |
|
|
pipe_rx0_chanisaligned => pipe_rx0_chanisaligned_gt ,
|
2583 |
|
|
pipe_rx0_status => pipe_rx0_status_gt ,
|
2584 |
|
|
pipe_rx0_phy_status => pipe_rx0_phy_status_gt ,
|
2585 |
|
|
pipe_rx0_elec_idle => pipe_rx0_elec_idle_gt ,
|
2586 |
|
|
pipe_rx0_polarity => pipe_rx0_polarity_gt ,
|
2587 |
|
|
pipe_tx0_compliance => pipe_tx0_compliance_gt ,
|
2588 |
|
|
pipe_tx0_char_is_k => pipe_tx0_char_is_k_gt ,
|
2589 |
|
|
pipe_tx0_data => pipe_tx0_data_gt ,
|
2590 |
|
|
pipe_tx0_elec_idle => pipe_tx0_elec_idle_gt ,
|
2591 |
|
|
pipe_tx0_powerdown => pipe_tx0_powerdown_gt ,
|
2592 |
|
|
|
2593 |
|
|
-- Pipe Per-Lane Signals - Lane 1
|
2594 |
|
|
|
2595 |
|
|
pipe_rx1_char_is_k => pipe_rx1_char_is_k_gt,
|
2596 |
|
|
pipe_rx1_data => pipe_rx1_data_gt ,
|
2597 |
|
|
pipe_rx1_valid => pipe_rx1_valid_gt ,
|
2598 |
|
|
pipe_rx1_chanisaligned => pipe_rx1_chanisaligned_gt ,
|
2599 |
|
|
pipe_rx1_status => pipe_rx1_status_gt ,
|
2600 |
|
|
pipe_rx1_phy_status => pipe_rx1_phy_status_gt ,
|
2601 |
|
|
pipe_rx1_elec_idle => pipe_rx1_elec_idle_gt ,
|
2602 |
|
|
pipe_rx1_polarity => pipe_rx1_polarity_gt ,
|
2603 |
|
|
pipe_tx1_compliance => pipe_tx1_compliance_gt ,
|
2604 |
|
|
pipe_tx1_char_is_k => pipe_tx1_char_is_k_gt ,
|
2605 |
|
|
pipe_tx1_data => pipe_tx1_data_gt ,
|
2606 |
|
|
pipe_tx1_elec_idle => pipe_tx1_elec_idle_gt ,
|
2607 |
|
|
pipe_tx1_powerdown => pipe_tx1_powerdown_gt ,
|
2608 |
|
|
|
2609 |
|
|
-- Pipe Per-Lane Signals - Lane 2
|
2610 |
|
|
|
2611 |
|
|
pipe_rx2_char_is_k => pipe_rx2_char_is_k_gt,
|
2612 |
|
|
pipe_rx2_data => pipe_rx2_data_gt ,
|
2613 |
|
|
pipe_rx2_valid => pipe_rx2_valid_gt ,
|
2614 |
|
|
pipe_rx2_chanisaligned => pipe_rx2_chanisaligned_gt ,
|
2615 |
|
|
pipe_rx2_status => pipe_rx2_status_gt ,
|
2616 |
|
|
pipe_rx2_phy_status => pipe_rx2_phy_status_gt ,
|
2617 |
|
|
pipe_rx2_elec_idle => pipe_rx2_elec_idle_gt ,
|
2618 |
|
|
pipe_rx2_polarity => pipe_rx2_polarity_gt ,
|
2619 |
|
|
pipe_tx2_compliance => pipe_tx2_compliance_gt ,
|
2620 |
|
|
pipe_tx2_char_is_k => pipe_tx2_char_is_k_gt ,
|
2621 |
|
|
pipe_tx2_data => pipe_tx2_data_gt ,
|
2622 |
|
|
pipe_tx2_elec_idle => pipe_tx2_elec_idle_gt ,
|
2623 |
|
|
pipe_tx2_powerdown => pipe_tx2_powerdown_gt ,
|
2624 |
|
|
|
2625 |
|
|
-- Pipe Per-Lane Signals - Lane 3
|
2626 |
|
|
|
2627 |
|
|
pipe_rx3_char_is_k => pipe_rx3_char_is_k_gt,
|
2628 |
|
|
pipe_rx3_data => pipe_rx3_data_gt ,
|
2629 |
|
|
pipe_rx3_valid => pipe_rx3_valid_gt ,
|
2630 |
|
|
pipe_rx3_chanisaligned => pipe_rx3_chanisaligned_gt ,
|
2631 |
|
|
pipe_rx3_status => pipe_rx3_status_gt ,
|
2632 |
|
|
pipe_rx3_phy_status => pipe_rx3_phy_status_gt ,
|
2633 |
|
|
pipe_rx3_elec_idle => pipe_rx3_elec_idle_gt ,
|
2634 |
|
|
pipe_rx3_polarity => pipe_rx3_polarity_gt ,
|
2635 |
|
|
pipe_tx3_compliance => pipe_tx3_compliance_gt ,
|
2636 |
|
|
pipe_tx3_char_is_k => pipe_tx3_char_is_k_gt ,
|
2637 |
|
|
pipe_tx3_data => pipe_tx3_data_gt ,
|
2638 |
|
|
pipe_tx3_elec_idle => pipe_tx3_elec_idle_gt ,
|
2639 |
|
|
pipe_tx3_powerdown => pipe_tx3_powerdown_gt ,
|
2640 |
|
|
|
2641 |
|
|
-- Pipe Per-Lane Signals - Lane 4
|
2642 |
|
|
|
2643 |
|
|
pipe_rx4_char_is_k => pipe_rx4_char_is_k_gt,
|
2644 |
|
|
pipe_rx4_data => pipe_rx4_data_gt ,
|
2645 |
|
|
pipe_rx4_valid => pipe_rx4_valid_gt ,
|
2646 |
|
|
pipe_rx4_chanisaligned => pipe_rx4_chanisaligned_gt ,
|
2647 |
|
|
pipe_rx4_status => pipe_rx4_status_gt ,
|
2648 |
|
|
pipe_rx4_phy_status => pipe_rx4_phy_status_gt ,
|
2649 |
|
|
pipe_rx4_elec_idle => pipe_rx4_elec_idle_gt ,
|
2650 |
|
|
pipe_rx4_polarity => pipe_rx4_polarity_gt ,
|
2651 |
|
|
pipe_tx4_compliance => pipe_tx4_compliance_gt ,
|
2652 |
|
|
pipe_tx4_char_is_k => pipe_tx4_char_is_k_gt ,
|
2653 |
|
|
pipe_tx4_data => pipe_tx4_data_gt ,
|
2654 |
|
|
pipe_tx4_elec_idle => pipe_tx4_elec_idle_gt ,
|
2655 |
|
|
pipe_tx4_powerdown => pipe_tx4_powerdown_gt ,
|
2656 |
|
|
|
2657 |
|
|
-- Pipe Per-Lane Signals - Lane 5
|
2658 |
|
|
|
2659 |
|
|
pipe_rx5_char_is_k => pipe_rx5_char_is_k_gt,
|
2660 |
|
|
pipe_rx5_data => pipe_rx5_data_gt ,
|
2661 |
|
|
pipe_rx5_valid => pipe_rx5_valid_gt ,
|
2662 |
|
|
pipe_rx5_chanisaligned => pipe_rx5_chanisaligned_gt ,
|
2663 |
|
|
pipe_rx5_status => pipe_rx5_status_gt ,
|
2664 |
|
|
pipe_rx5_phy_status => pipe_rx5_phy_status_gt ,
|
2665 |
|
|
pipe_rx5_elec_idle => pipe_rx5_elec_idle_gt ,
|
2666 |
|
|
pipe_rx5_polarity => pipe_rx5_polarity_gt ,
|
2667 |
|
|
pipe_tx5_compliance => pipe_tx5_compliance_gt ,
|
2668 |
|
|
pipe_tx5_char_is_k => pipe_tx5_char_is_k_gt ,
|
2669 |
|
|
pipe_tx5_data => pipe_tx5_data_gt ,
|
2670 |
|
|
pipe_tx5_elec_idle => pipe_tx5_elec_idle_gt ,
|
2671 |
|
|
pipe_tx5_powerdown => pipe_tx5_powerdown_gt ,
|
2672 |
|
|
|
2673 |
|
|
-- Pipe Per-Lane Signals - Lane 6
|
2674 |
|
|
|
2675 |
|
|
pipe_rx6_char_is_k => pipe_rx6_char_is_k_gt,
|
2676 |
|
|
pipe_rx6_data => pipe_rx6_data_gt ,
|
2677 |
|
|
pipe_rx6_valid => pipe_rx6_valid_gt ,
|
2678 |
|
|
pipe_rx6_chanisaligned => pipe_rx6_chanisaligned_gt ,
|
2679 |
|
|
pipe_rx6_status => pipe_rx6_status_gt ,
|
2680 |
|
|
pipe_rx6_phy_status => pipe_rx6_phy_status_gt ,
|
2681 |
|
|
pipe_rx6_elec_idle => pipe_rx6_elec_idle_gt ,
|
2682 |
|
|
pipe_rx6_polarity => pipe_rx6_polarity_gt ,
|
2683 |
|
|
pipe_tx6_compliance => pipe_tx6_compliance_gt ,
|
2684 |
|
|
pipe_tx6_char_is_k => pipe_tx6_char_is_k_gt ,
|
2685 |
|
|
pipe_tx6_data => pipe_tx6_data_gt ,
|
2686 |
|
|
pipe_tx6_elec_idle => pipe_tx6_elec_idle_gt ,
|
2687 |
|
|
pipe_tx6_powerdown => pipe_tx6_powerdown_gt ,
|
2688 |
|
|
|
2689 |
|
|
-- Pipe Per-Lane Signals - Lane 7
|
2690 |
|
|
|
2691 |
|
|
pipe_rx7_char_is_k => pipe_rx7_char_is_k_gt,
|
2692 |
|
|
pipe_rx7_data => pipe_rx7_data_gt ,
|
2693 |
|
|
pipe_rx7_valid => pipe_rx7_valid_gt ,
|
2694 |
|
|
pipe_rx7_chanisaligned => pipe_rx7_chanisaligned_gt ,
|
2695 |
|
|
pipe_rx7_status => pipe_rx7_status_gt ,
|
2696 |
|
|
pipe_rx7_phy_status => pipe_rx7_phy_status_gt ,
|
2697 |
|
|
pipe_rx7_elec_idle => pipe_rx7_elec_idle_gt ,
|
2698 |
|
|
pipe_rx7_polarity => pipe_rx7_polarity_gt ,
|
2699 |
|
|
pipe_tx7_compliance => pipe_tx7_compliance_gt ,
|
2700 |
|
|
pipe_tx7_char_is_k => pipe_tx7_char_is_k_gt ,
|
2701 |
|
|
pipe_tx7_data => pipe_tx7_data_gt ,
|
2702 |
|
|
pipe_tx7_elec_idle => pipe_tx7_elec_idle_gt ,
|
2703 |
|
|
pipe_tx7_powerdown => pipe_tx7_powerdown_gt ,
|
2704 |
|
|
|
2705 |
|
|
-- PCI Express Signals
|
2706 |
|
|
pci_exp_txn => pci_exp_txn ,
|
2707 |
|
|
pci_exp_txp => pci_exp_txp ,
|
2708 |
|
|
pci_exp_rxn => pci_exp_rxn ,
|
2709 |
|
|
pci_exp_rxp => pci_exp_rxp ,
|
2710 |
|
|
|
2711 |
|
|
-- Non PIPE Signals
|
2712 |
|
|
sys_clk => sys_clk ,
|
2713 |
|
|
sys_rst_n => sys_rst_n ,
|
2714 |
|
|
PIPE_MMCM_RST_N => PIPE_MMCM_RST_N , -- Async | Async
|
2715 |
|
|
pipe_clk => pipe_clk ,
|
2716 |
|
|
|
2717 |
|
|
user_clk => user_clk ,
|
2718 |
|
|
user_clk2 => user_clk2 ,
|
2719 |
|
|
phy_rdy_n => phy_rdy_n
|
2720 |
|
|
);
|
2721 |
|
|
|
2722 |
|
|
end pcie_7x;
|