| 1 |
46 |
dsmv |
//-----------------------------------------------------------------------------
|
| 2 |
|
|
//
|
| 3 |
|
|
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
|
| 4 |
|
|
//
|
| 5 |
|
|
// This file contains confidential and proprietary information
|
| 6 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
| 7 |
|
|
// international copyright and other intellectual property
|
| 8 |
|
|
// laws.
|
| 9 |
|
|
//
|
| 10 |
|
|
// DISCLAIMER
|
| 11 |
|
|
// This disclaimer is not a license and does not grant any
|
| 12 |
|
|
// rights to the materials distributed herewith. Except as
|
| 13 |
|
|
// otherwise provided in a valid license issued to you by
|
| 14 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
| 15 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
| 16 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
| 17 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
| 18 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
| 19 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
| 20 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
| 21 |
|
|
// including negligence, or under any other theory of
|
| 22 |
|
|
// liability) for any loss or damage of any kind or nature
|
| 23 |
|
|
// related to, arising under or in connection with these
|
| 24 |
|
|
// materials, including for any direct, or any indirect,
|
| 25 |
|
|
// special, incidental, or consequential loss or damage
|
| 26 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
| 27 |
|
|
// loss or damage suffered as a result of any action brought
|
| 28 |
|
|
// by a third party) even if such damage or loss was
|
| 29 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
| 30 |
|
|
// possibility of the same.
|
| 31 |
|
|
//
|
| 32 |
|
|
// CRITICAL APPLICATIONS
|
| 33 |
|
|
// Xilinx products are not designed or intended to be fail-
|
| 34 |
|
|
// safe, or for use in any application requiring fail-safe
|
| 35 |
|
|
// performance, such as life-support or safety devices or
|
| 36 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
| 37 |
|
|
// applications related to the deployment of airbags, or any
|
| 38 |
|
|
// other applications that could lead to death, personal
|
| 39 |
|
|
// injury, or severe property or environmental damage
|
| 40 |
|
|
// (individually and collectively, "Critical
|
| 41 |
|
|
// Applications"). Customer assumes the sole risk and
|
| 42 |
|
|
// liability of any use of Xilinx products in Critical
|
| 43 |
|
|
// Applications, subject only to applicable laws and
|
| 44 |
|
|
// regulations governing limitations on product liability.
|
| 45 |
|
|
//
|
| 46 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
| 47 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
| 48 |
|
|
//
|
| 49 |
|
|
//-----------------------------------------------------------------------------
|
| 50 |
|
|
// Project : Series-7 Integrated Block for PCI Express
|
| 51 |
|
|
// File : cl_a7pcie_x4_gt_wrapper.v
|
| 52 |
48 |
dsmv |
// Version : 1.10
|
| 53 |
46 |
dsmv |
//------------------------------------------------------------------------------
|
| 54 |
|
|
// Filename : gt_wrapper.v
|
| 55 |
|
|
// Description : GT Wrapper Module for 7 Series Transceiver
|
| 56 |
|
|
// Version : 19.0
|
| 57 |
|
|
//------------------------------------------------------------------------------
|
| 58 |
|
|
|
| 59 |
|
|
|
| 60 |
|
|
|
| 61 |
|
|
`timescale 1ns / 1ps
|
| 62 |
|
|
|
| 63 |
|
|
|
| 64 |
|
|
|
| 65 |
|
|
//---------- GT Wrapper --------------------------------------------------------
|
| 66 |
|
|
module cl_a7pcie_x4_gt_wrapper #
|
| 67 |
|
|
(
|
| 68 |
|
|
|
| 69 |
|
|
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
|
| 70 |
|
|
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
|
| 71 |
|
|
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
|
| 72 |
|
|
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
|
| 73 |
|
|
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
|
| 74 |
|
|
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2
|
| 75 |
|
|
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
|
| 76 |
|
|
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
|
| 77 |
|
|
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
|
| 78 |
|
|
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
|
| 79 |
|
|
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
|
| 80 |
|
|
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
|
| 81 |
|
|
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
|
| 82 |
|
|
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
|
| 83 |
|
|
parameter PCIE_LANE = 1, // PCIe number of lane
|
| 84 |
|
|
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
|
| 85 |
|
|
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
|
| 86 |
|
|
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
|
| 87 |
|
|
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
|
| 88 |
|
|
|
| 89 |
|
|
)
|
| 90 |
|
|
|
| 91 |
|
|
(
|
| 92 |
|
|
|
| 93 |
|
|
//---------- GT User Ports -----------------------------
|
| 94 |
|
|
input GT_MASTER,
|
| 95 |
|
|
input GT_GEN3,
|
| 96 |
|
|
input GT_RX_CONVERGE,
|
| 97 |
|
|
|
| 98 |
|
|
//---------- GT Clock Ports ----------------------------
|
| 99 |
|
|
input GT_GTREFCLK0,
|
| 100 |
|
|
input GT_QPLLCLK,
|
| 101 |
|
|
input GT_QPLLREFCLK,
|
| 102 |
|
|
input GT_TXUSRCLK,
|
| 103 |
|
|
input GT_RXUSRCLK,
|
| 104 |
|
|
input GT_TXUSRCLK2,
|
| 105 |
|
|
input GT_RXUSRCLK2,
|
| 106 |
|
|
input GT_OOBCLK,
|
| 107 |
|
|
input [ 1:0] GT_TXSYSCLKSEL,
|
| 108 |
|
|
input [ 1:0] GT_RXSYSCLKSEL,
|
| 109 |
|
|
|
| 110 |
|
|
output GT_TXOUTCLK,
|
| 111 |
|
|
output GT_RXOUTCLK,
|
| 112 |
|
|
output GT_CPLLLOCK,
|
| 113 |
|
|
output GT_RXCDRLOCK,
|
| 114 |
|
|
|
| 115 |
|
|
//---------- GT Reset Ports ----------------------------
|
| 116 |
|
|
input GT_CPLLPD,
|
| 117 |
|
|
input GT_CPLLRESET,
|
| 118 |
|
|
input GT_TXUSERRDY,
|
| 119 |
|
|
input GT_RXUSERRDY,
|
| 120 |
|
|
input GT_RESETOVRD,
|
| 121 |
|
|
input GT_GTTXRESET,
|
| 122 |
|
|
input GT_GTRXRESET,
|
| 123 |
|
|
input GT_TXPMARESET,
|
| 124 |
|
|
input GT_RXPMARESET,
|
| 125 |
|
|
input GT_RXCDRRESET,
|
| 126 |
|
|
input GT_RXCDRFREQRESET,
|
| 127 |
|
|
input GT_RXDFELPMRESET,
|
| 128 |
|
|
input GT_EYESCANRESET,
|
| 129 |
|
|
input GT_TXPCSRESET,
|
| 130 |
|
|
input GT_RXPCSRESET,
|
| 131 |
|
|
input GT_RXBUFRESET,
|
| 132 |
|
|
|
| 133 |
|
|
output GT_TXRESETDONE,
|
| 134 |
|
|
output GT_RXRESETDONE,
|
| 135 |
|
|
output GT_RXPMARESETDONE,
|
| 136 |
|
|
|
| 137 |
|
|
//---------- GT TX Data Ports --------------------------
|
| 138 |
|
|
input [31:0] GT_TXDATA,
|
| 139 |
|
|
input [ 3:0] GT_TXDATAK,
|
| 140 |
|
|
|
| 141 |
|
|
output GT_TXP,
|
| 142 |
|
|
output GT_TXN,
|
| 143 |
|
|
|
| 144 |
|
|
//---------- GT RX Data Ports --------------------------
|
| 145 |
|
|
input GT_RXN,
|
| 146 |
|
|
input GT_RXP,
|
| 147 |
|
|
|
| 148 |
|
|
output [31:0] GT_RXDATA,
|
| 149 |
|
|
output [ 3:0] GT_RXDATAK,
|
| 150 |
|
|
|
| 151 |
|
|
//---------- GT Command Ports --------------------------
|
| 152 |
|
|
input GT_TXDETECTRX,
|
| 153 |
|
|
input GT_TXELECIDLE,
|
| 154 |
|
|
input GT_TXCOMPLIANCE,
|
| 155 |
|
|
input GT_RXPOLARITY,
|
| 156 |
|
|
input [ 1:0] GT_TXPOWERDOWN,
|
| 157 |
|
|
input [ 1:0] GT_RXPOWERDOWN,
|
| 158 |
|
|
input [ 2:0] GT_TXRATE,
|
| 159 |
|
|
input [ 2:0] GT_RXRATE,
|
| 160 |
|
|
|
| 161 |
|
|
//---------- GT Electrical Command Ports ---------------
|
| 162 |
|
|
input [ 2:0] GT_TXMARGIN,
|
| 163 |
|
|
input GT_TXSWING,
|
| 164 |
|
|
input GT_TXDEEMPH,
|
| 165 |
|
|
input [ 4:0] GT_TXPRECURSOR,
|
| 166 |
|
|
input [ 6:0] GT_TXMAINCURSOR,
|
| 167 |
|
|
input [ 4:0] GT_TXPOSTCURSOR,
|
| 168 |
|
|
|
| 169 |
|
|
//---------- GT Status Ports ---------------------------
|
| 170 |
|
|
output GT_RXVALID,
|
| 171 |
|
|
output GT_PHYSTATUS,
|
| 172 |
|
|
output GT_RXELECIDLE,
|
| 173 |
|
|
output [ 2:0] GT_RXSTATUS,
|
| 174 |
|
|
output [ 2:0] GT_RXBUFSTATUS,
|
| 175 |
|
|
output GT_TXRATEDONE,
|
| 176 |
|
|
output GT_RXRATEDONE,
|
| 177 |
|
|
|
| 178 |
|
|
//---------- GT DRP Ports ------------------------------
|
| 179 |
|
|
input GT_DRPCLK,
|
| 180 |
|
|
input [ 8:0] GT_DRPADDR,
|
| 181 |
|
|
input GT_DRPEN,
|
| 182 |
|
|
input [15:0] GT_DRPDI,
|
| 183 |
|
|
input GT_DRPWE,
|
| 184 |
|
|
|
| 185 |
|
|
output [15:0] GT_DRPDO,
|
| 186 |
|
|
output GT_DRPRDY,
|
| 187 |
|
|
|
| 188 |
|
|
//---------- GT TX Sync Ports --------------------------
|
| 189 |
|
|
input GT_TXPHALIGN,
|
| 190 |
|
|
input GT_TXPHALIGNEN,
|
| 191 |
|
|
input GT_TXPHINIT,
|
| 192 |
|
|
input GT_TXDLYBYPASS,
|
| 193 |
|
|
input GT_TXDLYSRESET,
|
| 194 |
|
|
input GT_TXDLYEN,
|
| 195 |
|
|
|
| 196 |
|
|
output GT_TXDLYSRESETDONE,
|
| 197 |
|
|
output GT_TXPHINITDONE,
|
| 198 |
|
|
output GT_TXPHALIGNDONE,
|
| 199 |
|
|
|
| 200 |
|
|
input GT_TXPHDLYRESET,
|
| 201 |
|
|
input GT_TXSYNCMODE, // GTH
|
| 202 |
|
|
input GT_TXSYNCIN, // GTH
|
| 203 |
|
|
input GT_TXSYNCALLIN, // GTH
|
| 204 |
|
|
|
| 205 |
|
|
output GT_TXSYNCOUT, // GTH
|
| 206 |
|
|
output GT_TXSYNCDONE, // GTH
|
| 207 |
|
|
|
| 208 |
|
|
//---------- GT RX Sync Ports --------------------------
|
| 209 |
|
|
input GT_RXPHALIGN,
|
| 210 |
|
|
input GT_RXPHALIGNEN,
|
| 211 |
|
|
input GT_RXDLYBYPASS,
|
| 212 |
|
|
input GT_RXDLYSRESET,
|
| 213 |
|
|
input GT_RXDLYEN,
|
| 214 |
|
|
input GT_RXDDIEN,
|
| 215 |
|
|
|
| 216 |
|
|
output GT_RXDLYSRESETDONE,
|
| 217 |
|
|
output GT_RXPHALIGNDONE,
|
| 218 |
|
|
|
| 219 |
|
|
input GT_RXSYNCMODE, // GTH
|
| 220 |
|
|
input GT_RXSYNCIN, // GTH
|
| 221 |
|
|
input GT_RXSYNCALLIN, // GTH
|
| 222 |
|
|
|
| 223 |
|
|
output GT_RXSYNCOUT, // GTH
|
| 224 |
|
|
output GT_RXSYNCDONE, // GTH
|
| 225 |
|
|
|
| 226 |
|
|
//---------- GT Comma Alignment Ports ------------------
|
| 227 |
|
|
input GT_RXSLIDE,
|
| 228 |
|
|
|
| 229 |
|
|
output GT_RXCOMMADET,
|
| 230 |
|
|
output [ 3:0] GT_RXCHARISCOMMA,
|
| 231 |
|
|
output GT_RXBYTEISALIGNED,
|
| 232 |
|
|
output GT_RXBYTEREALIGN,
|
| 233 |
|
|
|
| 234 |
|
|
//---------- GT Channel Bonding Ports ------------------
|
| 235 |
|
|
input GT_RXCHBONDEN,
|
| 236 |
|
|
input [ 4:0] GT_RXCHBONDI,
|
| 237 |
|
|
input [ 2:0] GT_RXCHBONDLEVEL,
|
| 238 |
|
|
input GT_RXCHBONDMASTER,
|
| 239 |
|
|
input GT_RXCHBONDSLAVE,
|
| 240 |
|
|
|
| 241 |
|
|
output GT_RXCHANISALIGNED,
|
| 242 |
|
|
output [ 4:0] GT_RXCHBONDO,
|
| 243 |
|
|
|
| 244 |
|
|
//---------- GT PRBS/Loopback Ports --------------------
|
| 245 |
|
|
input [ 2:0] GT_TXPRBSSEL,
|
| 246 |
|
|
input [ 2:0] GT_RXPRBSSEL,
|
| 247 |
|
|
input GT_TXPRBSFORCEERR,
|
| 248 |
|
|
input GT_RXPRBSCNTRESET,
|
| 249 |
|
|
input [ 2:0] GT_LOOPBACK,
|
| 250 |
|
|
|
| 251 |
|
|
output GT_RXPRBSERR,
|
| 252 |
|
|
|
| 253 |
|
|
//---------- GT Debug Ports ----------------------------
|
| 254 |
|
|
output [14:0] GT_DMONITOROUT
|
| 255 |
|
|
|
| 256 |
|
|
);
|
| 257 |
|
|
|
| 258 |
|
|
//---------- Internal Signals --------------------------
|
| 259 |
|
|
wire [ 2:0] txoutclksel;
|
| 260 |
|
|
wire [ 2:0] rxoutclksel;
|
| 261 |
|
|
wire [63:0] rxdata;
|
| 262 |
|
|
wire [ 7:0] rxdatak;
|
| 263 |
|
|
wire [ 7:0] rxchariscomma;
|
| 264 |
|
|
wire rxlpmen;
|
| 265 |
|
|
wire [14:0] dmonitorout;
|
| 266 |
|
|
wire dmonitorclk;
|
| 267 |
|
|
|
| 268 |
|
|
//---------- Select CPLL and Clock Dividers ------------
|
| 269 |
|
|
localparam CPLL_REFCLK_DIV = 1;
|
| 270 |
|
|
localparam CPLL_FBDIV_45 = 5;
|
| 271 |
|
|
localparam CPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 2 :
|
| 272 |
|
|
(PCIE_REFCLK_FREQ == 1) ? 4 : 5;
|
| 273 |
|
|
localparam OUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 4 : 2;
|
| 274 |
|
|
localparam CLK25_DIV = (PCIE_REFCLK_FREQ == 2) ? 10 :
|
| 275 |
|
|
(PCIE_REFCLK_FREQ == 1) ? 5 : 4;
|
| 276 |
|
|
|
| 277 |
|
|
//---------- Select IES vs. GES ------------------------
|
| 278 |
|
|
localparam CLKMUX_PD = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 1'd0 : 1'd1;
|
| 279 |
|
|
|
| 280 |
|
|
//---------- Select GTP CPLL configuration -------------
|
| 281 |
|
|
// PLL0/1_CFG[ 5:2] = CP1 : [ 8, 4, 2, 1] units
|
| 282 |
|
|
// PLL0/1_CFG[10:6] = CP2 : [16, 8, 4, 2, 1] units
|
| 283 |
|
|
// CP2/CP1 = 2 to 3
|
| 284 |
|
|
// (8/4=2) = 27'h01F0210 = 0000_0001_1111_0000_0010_0001_0000
|
| 285 |
|
|
// (9/3=3) = 27'h01F024C = 0000_0001_1111_0000_0010_0100_1100
|
| 286 |
|
|
// (8/3=2.67) = 27'h01F020C = 0000_0001_1111_0000_0010_0000_1100
|
| 287 |
|
|
// (7/3=2.33) = 27'h01F01CC = 0000_0001_1111_0000_0001_1100_1100
|
| 288 |
|
|
// (6/3=2) = 27'h01F018C = 0000_0001_1111_0000_0001_1000_1100
|
| 289 |
|
|
// (5/3=1.67) = 27'h01F014C = 0000_0001_1111_0000_0001_0100_1100
|
| 290 |
|
|
// (6/2=3) = 27'h01F0188 = 0000_0001_1111_0000_0001_1000_1000
|
| 291 |
|
|
//---------- Select GTX CPLL configuration -------------
|
| 292 |
|
|
// CPLL_CFG[ 5: 2] = CP1 : [ 8, 4, 2, 1] units
|
| 293 |
|
|
// CPLL_CFG[22:18] = CP2 : [16, 8, 4, 2, 1] units
|
| 294 |
|
|
// CP2/CP1 = 2 to 3
|
| 295 |
|
|
// (9/3=3) = 1010_0100_0000_0111_1100_1100
|
| 296 |
|
|
//------------------------------------------------------
|
| 297 |
|
|
localparam CPLL_CFG = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 24'hB407CC : 24'hA407CC;
|
| 298 |
|
|
|
| 299 |
|
|
//---------- Select TX XCLK ----------------------------
|
| 300 |
|
|
// TXOUT for TX Buffer Use
|
| 301 |
|
|
// TXUSR for TX Buffer Bypass
|
| 302 |
|
|
//------------------------------------------------------
|
| 303 |
|
|
localparam TX_XCLK_SEL = (PCIE_TXBUF_EN == "TRUE") ? "TXOUT" : "TXUSR";
|
| 304 |
|
|
|
| 305 |
|
|
//---------- Select TX Receiver Detection Configuration
|
| 306 |
|
|
localparam TX_RXDETECT_CFG = (PCIE_REFCLK_FREQ == 2) ? 14'd250 :
|
| 307 |
|
|
(PCIE_REFCLK_FREQ == 1) ? 14'd125 : 14'd100;
|
| 308 |
|
|
localparam TX_RXDETECT_REF = (((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) && (PCIE_SIM_MODE == "FALSE")) ? 3'b000 : 3'b011;
|
| 309 |
|
|
|
| 310 |
|
|
//---------- Select PCS_RSVD_ATTR ----------------------
|
| 311 |
|
|
// [0]: 1 = enable latch when bypassing TX buffer, 0 = disable latch when using TX buffer
|
| 312 |
|
|
// [1]: 1 = enable manual TX sync, 0 = enable auto TX sync
|
| 313 |
|
|
// [2]: 1 = enable manual RX sync, 0 = enable auto RX sync
|
| 314 |
|
|
// [3]: 1 = select external clock for OOB 0 = select reference clock for OOB
|
| 315 |
|
|
// [6]: 1 = enable DMON 0 = disable DMON
|
| 316 |
|
|
// [7]: 1 = filter stale TX[P/N] data when exiting TX electrical idle
|
| 317 |
|
|
// [8]: 1 = power up OOB 0 = power down OOB
|
| 318 |
|
|
//------------------------------------------------------
|
| 319 |
|
|
localparam OOBCLK_SEL = (PCIE_OOBCLK_MODE == 0) ? 1'd0 : 1'd1; // GTX
|
| 320 |
|
|
localparam RXOOB_CLK_CFG = (PCIE_OOBCLK_MODE == 0) ? "PMA" : "FABRIC"; // GTH/GTP
|
| 321 |
|
|
|
| 322 |
|
|
localparam PCS_RSVD_ATTR = ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
|
| 323 |
|
|
((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} :
|
| 324 |
|
|
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd7} :
|
| 325 |
|
|
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd6} :
|
| 326 |
|
|
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd5} :
|
| 327 |
|
|
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd4} :
|
| 328 |
|
|
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd3} :
|
| 329 |
|
|
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd2} :
|
| 330 |
|
|
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
|
| 331 |
|
|
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : {44'h0000000001C, OOBCLK_SEL, 3'd7};
|
| 332 |
|
|
|
| 333 |
|
|
//---------- Select RXCDR_CFG --------------------------
|
| 334 |
|
|
|
| 335 |
|
|
//---------- GTX Note ----------------------------------
|
| 336 |
|
|
// For GTX PCIe Gen1/Gen2 with 8B/10B, the following CDR setting may provide more margin
|
| 337 |
|
|
// Async 72'h03_8000_23FF_1040_0020
|
| 338 |
|
|
// Sync: 72'h03_0000_23FF_1040_0020
|
| 339 |
|
|
//------------------------------------------------------
|
| 340 |
|
|
|
| 341 |
|
|
localparam RXCDR_CFG_GTX = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ?
|
| 342 |
|
|
((PCIE_ASYNC_EN == "TRUE") ? 72'b0000_0010_0000_0111_1111_1110_0010_0000_0110_0000_0010_0001_0001_0000_0000000000010000
|
| 343 |
|
|
: 72'h11_07FE_4060_0104_0000): // IES setting
|
| 344 |
|
|
((PCIE_ASYNC_EN == "TRUE") ? 72'h03_8000_23FF_1020_0020 //
|
| 345 |
|
|
: 72'h03_0000_23FF_1020_0020); // optimized for GES silicon
|
| 346 |
|
|
|
| 347 |
|
|
localparam RXCDR_CFG_GTH = (PCIE_USE_MODE == "2.0") ?
|
| 348 |
|
|
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0011_07FE_4060_2104_1010
|
| 349 |
|
|
: 83'h0_0011_07FE_4060_0104_1010): // Optimized for IES silicon
|
| 350 |
|
|
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0020_07FE_2000_C208_8018
|
| 351 |
|
|
: 83'h0_0020_07FE_2000_C208_0018); // Optimized for 1.2 silicon
|
| 352 |
|
|
|
| 353 |
|
|
localparam RXCDR_CFG_GTP = ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0001_07FE_4060_2104_1010
|
| 354 |
|
|
: 83'h0_0001_07FE_4060_0104_1010); // Optimized for IES silicon
|
| 355 |
|
|
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
//---------- Select TX and RX Sync Mode ----------------
|
| 360 |
|
|
localparam TXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
|
| 361 |
|
|
localparam RXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
|
| 362 |
|
|
|
| 363 |
|
|
localparam TXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
|
| 364 |
|
|
localparam RXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
|
| 365 |
|
|
|
| 366 |
|
|
//---------- Select Clock Correction Min and Max Latency
|
| 367 |
|
|
// CLK_COR_MIN_LAT = Larger of (2 * RXCHBONDLEVEL + 13) or (CHAN_BOND_MAX_SKEW + 11)
|
| 368 |
|
|
// = 13 when PCIE_LANE = 1
|
| 369 |
|
|
// CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + CLK_COR_SEQ_LEN + 1
|
| 370 |
|
|
// = CLK_COR_MIN_LAT + 2
|
| 371 |
|
|
//------------------------------------------------------
|
| 372 |
|
|
|
| 373 |
|
|
//---------- CLK_COR_MIN_LAT Look-up Table -------------
|
| 374 |
|
|
// Lane | One-Hop | Daisy-Chain | Binary-Tree
|
| 375 |
|
|
//------------------------------------------------------
|
| 376 |
|
|
// 0 | 13 | 13 | 13
|
| 377 |
|
|
// 1 | 15 to 18 | 15 to 18 | 15 to 18
|
| 378 |
|
|
// 2 | 15 to 18 | 17 to 18 | 15 to 18
|
| 379 |
|
|
// 3 | 15 to 18 | 19 | 17 to 18
|
| 380 |
|
|
// 4 | 15 to 18 | 21 | 17 to 18
|
| 381 |
|
|
// 5 | 15 to 18 | 23 | 19
|
| 382 |
|
|
// 6 | 15 to 18 | 25 | 19
|
| 383 |
|
|
// 7 | 15 to 18 | 27 | 21
|
| 384 |
|
|
//------------------------------------------------------
|
| 385 |
|
|
|
| 386 |
|
|
localparam CLK_COR_MIN_LAT = ((PCIE_LANE == 8) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 27 : 21) :
|
| 387 |
|
|
((PCIE_LANE == 7) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 25 : 19) :
|
| 388 |
|
|
((PCIE_LANE == 6) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 23 : 19) :
|
| 389 |
|
|
((PCIE_LANE == 5) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 21 : 18) :
|
| 390 |
|
|
((PCIE_LANE == 4) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 19 : 18) :
|
| 391 |
|
|
((PCIE_LANE == 3) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
|
| 392 |
|
|
((PCIE_LANE == 2) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
|
| 393 |
|
|
((PCIE_LANE == 1) || (PCIE_CHAN_BOND_EN == "FALSE")) ? 13 : 18;
|
| 394 |
|
|
|
| 395 |
|
|
localparam CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + 2;
|
| 396 |
|
|
|
| 397 |
|
|
//---------- Simulation Speedup ------------------------
|
| 398 |
|
|
//localparam CFOK_CFG_GTH = (PCIE_SIM_MODE == "TRUE") ? 42'h240_0004_0F80 : 42'h248_0004_0E80; // [8] : 1 = Skip CFOK
|
| 399 |
|
|
//localparam CFOK_CFG_GTP = (PCIE_SIM_MODE == "TRUE") ? 43'h000_0000_0000 : 43'h000_0000_0100; // [2] : 1 = Skip CFOK
|
| 400 |
|
|
|
| 401 |
|
|
//---------- Select [TX/RX]OUTCLK ----------------------
|
| 402 |
|
|
assign txoutclksel = GT_MASTER ? 3'd3 : 3'd0;
|
| 403 |
|
|
assign rxoutclksel = ((PCIE_DEBUG_MODE == 1) || ((PCIE_ASYNC_EN == "TRUE") && GT_MASTER)) ? 3'd2 : 3'd0;
|
| 404 |
|
|
|
| 405 |
|
|
//---------- Select DFE vs. LPM ------------------------
|
| 406 |
|
|
// Gen1/2 = Use LPM by default. Option to use DFE.
|
| 407 |
|
|
// Gen3 = Use DFE by default. Option to use LPM.
|
| 408 |
|
|
//------------------------------------------------------
|
| 409 |
|
|
assign rxlpmen = GT_GEN3 ? ((PCIE_LPM_DFE_GEN3 == "LPM") ? 1'd1 : 1'd0) : ((PCIE_LPM_DFE == "LPM") ? 1'd1 : 1'd0);
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
//---------- Generate DMONITOR Clock Buffer for Debug ------
|
| 414 |
|
|
generate if (PCIE_DEBUG_MODE == 1)
|
| 415 |
|
|
|
| 416 |
|
|
begin : dmonitorclk_i
|
| 417 |
|
|
//---------- DMONITOR CLK ------------------------------
|
| 418 |
|
|
BUFG dmonitorclk_i
|
| 419 |
|
|
(
|
| 420 |
|
|
//---------- Input ---------------------------------
|
| 421 |
|
|
.I (dmonitorout[7]),
|
| 422 |
|
|
//---------- Output --------------------------------
|
| 423 |
|
|
.O (dmonitorclk)
|
| 424 |
|
|
);
|
| 425 |
|
|
end
|
| 426 |
|
|
|
| 427 |
|
|
else
|
| 428 |
|
|
|
| 429 |
|
|
begin : dmonitorclk_i_disable
|
| 430 |
|
|
assign dmonitorclk = 1'd0;
|
| 431 |
|
|
end
|
| 432 |
|
|
|
| 433 |
|
|
endgenerate
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
//---------- Select GTX or GTH or GTP ------------------------------------------
|
| 438 |
|
|
// Notes : Attributes that are commented out always use the GT default settings
|
| 439 |
|
|
//------------------------------------------------------------------------------
|
| 440 |
|
|
generate if (PCIE_GT_DEVICE == "GTP")
|
| 441 |
|
|
|
| 442 |
|
|
begin : gtp_channel
|
| 443 |
|
|
|
| 444 |
|
|
//---------- GTP Channel Module --------------------------------------------
|
| 445 |
|
|
GTPE2_CHANNEL #
|
| 446 |
|
|
(
|
| 447 |
|
|
|
| 448 |
|
|
//---------- Simulation Attributes -------------------------------------
|
| 449 |
|
|
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
|
| 450 |
|
|
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
|
| 451 |
|
|
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
|
| 452 |
|
|
.SIM_VERSION (PCIE_USE_MODE), //
|
| 453 |
|
|
|
| 454 |
|
|
//---------- Clock Attributes ------------------------------------------
|
| 455 |
|
|
.TXOUT_DIV (OUT_DIV), //
|
| 456 |
|
|
.RXOUT_DIV (OUT_DIV), //
|
| 457 |
|
|
.TX_CLK25_DIV (CLK25_DIV), //
|
| 458 |
|
|
.RX_CLK25_DIV (CLK25_DIV), //
|
| 459 |
|
|
//.TX_CLKMUX_EN ( 1'b1), // GTP rename
|
| 460 |
|
|
//.RX_CLKMUX_EN ( 1'b1), // GTP rename
|
| 461 |
|
|
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
|
| 462 |
|
|
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
|
| 463 |
|
|
//.OUTREFCLK_SEL_INV ( 2'b11), //
|
| 464 |
|
|
|
| 465 |
|
|
//---------- Reset Attributes ------------------------------------------
|
| 466 |
|
|
.TXPCSRESET_TIME ( 5'b00001), //
|
| 467 |
|
|
.RXPCSRESET_TIME ( 5'b00001), //
|
| 468 |
|
|
.TXPMARESET_TIME ( 5'b00011), //
|
| 469 |
|
|
.RXPMARESET_TIME ( 5'b00011), // Optimized for sim
|
| 470 |
|
|
//.RXISCANRESET_TIME ( 5'b00001), //
|
| 471 |
|
|
|
| 472 |
|
|
//---------- TX Data Attributes ----------------------------------------
|
| 473 |
|
|
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
|
| 474 |
|
|
|
| 475 |
|
|
//---------- RX Data Attributes ----------------------------------------
|
| 476 |
|
|
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
|
| 477 |
|
|
|
| 478 |
|
|
//---------- Command Attributes ----------------------------------------
|
| 479 |
|
|
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
|
| 480 |
|
|
.TX_RXDETECT_REF ( 3'b011), //
|
| 481 |
|
|
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
|
| 482 |
|
|
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for IES
|
| 483 |
|
|
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim
|
| 484 |
|
|
.TX_EIDLE_DEASSERT_DELAY ( 3'b010), // Optimized for sim
|
| 485 |
|
|
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
|
| 486 |
|
|
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
|
| 487 |
|
|
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
|
| 488 |
|
|
//.TRANS_TIME_RATE ( 8'h0E), //
|
| 489 |
|
|
|
| 490 |
|
|
//---------- Electrical Command Attributes -----------------------------
|
| 491 |
|
|
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
|
| 492 |
|
|
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
|
| 493 |
|
|
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
|
| 494 |
|
|
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
|
| 495 |
|
|
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
|
| 496 |
|
|
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
|
| 497 |
|
|
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
|
| 498 |
|
|
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
|
| 499 |
|
|
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
|
| 500 |
|
|
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
|
| 501 |
|
|
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
|
| 502 |
|
|
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
|
| 503 |
|
|
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
|
| 504 |
|
|
.TX_MAINCURSOR_SEL ( 1'b0), //
|
| 505 |
|
|
.TX_PREDRIVER_MODE ( 1'b0), // GTP
|
| 506 |
|
|
|
| 507 |
|
|
//---------- Status Attributes -----------------------------------------
|
| 508 |
|
|
//.RX_SIG_VALID_DLY ( 4), // CHECK
|
| 509 |
|
|
|
| 510 |
|
|
//---------- DRP Attributes --------------------------------------------
|
| 511 |
|
|
|
| 512 |
|
|
//---------- PCS Attributes --------------------------------------------
|
| 513 |
|
|
.PCS_PCIE_EN ("TRUE"), // PCIe
|
| 514 |
|
|
.PCS_RSVD_ATTR (48'h0000_0000_0100), // [8] : 1 = OOB power-up
|
| 515 |
|
|
|
| 516 |
|
|
//---------- PMA Attributes -------------------------------------------
|
| 517 |
|
|
//.CLK_COMMON_SWING ( 1'b0), // GTP new
|
| 518 |
|
|
//.PMA_RSV (32'd0), //
|
| 519 |
|
|
.PMA_RSV2 (32'h00002040), // Optimized for GES
|
| 520 |
|
|
//.PMA_RSV3 ( 2'd0), //
|
| 521 |
|
|
//.PMA_RSV4 ( 4'd0), // Changed from 15 to 4-bits
|
| 522 |
|
|
//.PMA_RSV5 ( 1'd0), // Changed from 4 to 1-bit
|
| 523 |
|
|
//.PMA_RSV6 ( 1'd0), // GTP new
|
| 524 |
|
|
//.PMA_RSV7 ( 1'd0), // GTP new
|
| 525 |
|
|
.RX_BIAS_CFG (16'h0F33), // Optimized for IES
|
| 526 |
|
|
.TERM_RCAL_CFG (15'b100001000010000), // Optimized for IES
|
| 527 |
|
|
.TERM_RCAL_OVRD ( 3'b000), // Optimized for IES
|
| 528 |
|
|
|
| 529 |
|
|
//---------- TX PI ----------------------------------------------------
|
| 530 |
|
|
//.TXPI_CFG0 ( 2'd0), //
|
| 531 |
|
|
//.TXPI_CFG1 ( 2'd0), //
|
| 532 |
|
|
//.TXPI_CFG2 ( 2'd0), //
|
| 533 |
|
|
//.TXPI_CFG3 ( 1'd0), //
|
| 534 |
|
|
//.TXPI_CFG4 ( 1'd0), //
|
| 535 |
|
|
//.TXPI_CFG5 ( 3'd000), //
|
| 536 |
|
|
//.TXPI_GREY_SEL ( 1'd0), //
|
| 537 |
|
|
//.TXPI_INVSTROBE_SEL ( 1'd0), //
|
| 538 |
|
|
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), //
|
| 539 |
|
|
//.TXPI_PPM_CFG ( 8'd0), //
|
| 540 |
|
|
//.TXPI_SYNFREQ_PPM ( 3'd0), //
|
| 541 |
|
|
|
| 542 |
|
|
//---------- RX PI -----------------------------------------------------
|
| 543 |
|
|
.RXPI_CFG0 ( 3'd0), // Changed from 3 to 2-bits, Optimized for IES
|
| 544 |
|
|
.RXPI_CFG1 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
|
| 545 |
|
|
.RXPI_CFG2 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
|
| 546 |
|
|
|
| 547 |
|
|
//---------- CDR Attributes ---------------------------------------------
|
| 548 |
|
|
//.RXCDR_CFG (72'b0000_001000000_11111_11111_001000000_011_0000111_000_001000_010000_100000000000000), // CHECK
|
| 549 |
|
|
.RXCDR_CFG (RXCDR_CFG_GTP), // Optimized for IES
|
| 550 |
|
|
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) CHECK
|
| 551 |
|
|
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
|
| 552 |
|
|
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
|
| 553 |
|
|
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
|
| 554 |
|
|
//.RXCDRFREQRESET_TIME ( 5'b00001), //
|
| 555 |
|
|
//.RXCDRPHRESET_TIME ( 5'b00001), //
|
| 556 |
|
|
|
| 557 |
|
|
//---------- LPM Attributes --------------------------------------------
|
| 558 |
|
|
//.RXLPMRESET_TIME ( 7'b0001111), // GTP new
|
| 559 |
|
|
//.RXLPM_BIAS_STARTUP_DISABLE ( 1'b0), // GTP new
|
| 560 |
|
|
.RXLPM_CFG ( 4'b0110), // GTP new, optimized for IES
|
| 561 |
|
|
//.RXLPM_CFG1 ( 1'b0), // GTP new
|
| 562 |
|
|
//.RXLPM_CM_CFG ( 1'b0), // GTP new
|
| 563 |
|
|
.RXLPM_GC_CFG ( 9'b111100010), // GTP new, optimized for IES
|
| 564 |
|
|
.RXLPM_GC_CFG2 ( 3'b001), // GTP new, optimized for IES
|
| 565 |
|
|
//.RXLPM_HF_CFG (14'b00001111110000), //
|
| 566 |
|
|
.RXLPM_HF_CFG2 ( 5'b01010), // GTP new
|
| 567 |
|
|
//.RXLPM_HF_CFG3 ( 4'b0000), // GTP new
|
| 568 |
|
|
.RXLPM_HOLD_DURING_EIDLE ( 1'b1), // GTP new
|
| 569 |
|
|
.RXLPM_INCM_CFG ( 1'b1), // GTP new, optimized for IES
|
| 570 |
|
|
.RXLPM_IPCM_CFG ( 1'b0), // GTP new, optimized for IES
|
| 571 |
|
|
//.RXLPM_LF_CFG (18'b000000001111110000), //
|
| 572 |
|
|
.RXLPM_LF_CFG2 ( 5'b01010), // GTP new, optimized for IES
|
| 573 |
|
|
.RXLPM_OSINT_CFG ( 3'b100), // GTP new, optimized for IES
|
| 574 |
|
|
|
| 575 |
|
|
//---------- OS Attributes ---------------------------------------------
|
| 576 |
|
|
.RX_OS_CFG (13'h0080), // CHECK
|
| 577 |
|
|
.RXOSCALRESET_TIME (5'b00011), // Optimized for IES
|
| 578 |
|
|
.RXOSCALRESET_TIMEOUT (5'b00000), // Disable timeout, Optimized for IES
|
| 579 |
|
|
|
| 580 |
|
|
//---------- Eye Scan Attributes ---------------------------------------
|
| 581 |
|
|
//.ES_CLK_PHASE_SEL ( 1'b0), //
|
| 582 |
|
|
//.ES_CONTROL ( 6'd0), //
|
| 583 |
|
|
//.ES_ERRDET_EN ("FALSE"), //
|
| 584 |
|
|
.ES_EYE_SCAN_EN ("TRUE"), //
|
| 585 |
|
|
//.ES_HORZ_OFFSET (12'd0), //
|
| 586 |
|
|
//.ES_PMA_CFG (10'd0), //
|
| 587 |
|
|
//.ES_PRESCALE ( 5'd0), //
|
| 588 |
|
|
//.ES_QUAL_MASK (80'd0), //
|
| 589 |
|
|
//.ES_QUALIFIER (80'd0), //
|
| 590 |
|
|
//.ES_SDATA_MASK (80'd0), //
|
| 591 |
|
|
//.ES_VERT_OFFSET ( 9'd0), //
|
| 592 |
|
|
|
| 593 |
|
|
//---------- TX Buffer Attributes --------------------------------------
|
| 594 |
|
|
.TXBUF_EN (PCIE_TXBUF_EN), //
|
| 595 |
|
|
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
|
| 596 |
|
|
|
| 597 |
|
|
//---------- RX Buffer Attributes --------------------------------------
|
| 598 |
|
|
.RXBUF_EN ("TRUE"), //
|
| 599 |
|
|
//.RX_BUFFER_CFG ( 6'd0), //
|
| 600 |
|
|
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
|
| 601 |
|
|
.RXBUF_ADDR_MODE ("FULL"), //
|
| 602 |
|
|
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
|
| 603 |
|
|
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
|
| 604 |
|
|
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
|
| 605 |
|
|
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
|
| 606 |
|
|
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
|
| 607 |
|
|
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
|
| 608 |
|
|
.RXBUF_THRESH_OVRD ("FALSE"), //
|
| 609 |
|
|
.RXBUF_THRESH_OVFLW (61), //
|
| 610 |
|
|
.RXBUF_THRESH_UNDFLW ( 4), //
|
| 611 |
|
|
//.RXBUFRESET_TIME ( 5'b00001), //
|
| 612 |
|
|
|
| 613 |
|
|
//---------- TX Sync Attributes ----------------------------------------
|
| 614 |
|
|
.TXPH_CFG (16'h0780), //
|
| 615 |
|
|
.TXPH_MONITOR_SEL ( 5'd0), //
|
| 616 |
|
|
.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
|
| 617 |
|
|
.TXDLY_CFG (16'h001F), //
|
| 618 |
|
|
.TXDLY_LCFG ( 9'h030), //
|
| 619 |
|
|
.TXDLY_TAP_CFG (16'd0), //
|
| 620 |
|
|
|
| 621 |
|
|
.TXSYNC_OVRD (TXSYNC_OVRD), //
|
| 622 |
|
|
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), //
|
| 623 |
|
|
.TXSYNC_SKIP_DA (1'b0), //
|
| 624 |
|
|
|
| 625 |
|
|
//---------- RX Sync Attributes ----------------------------------------
|
| 626 |
|
|
.RXPH_CFG (24'd0), //
|
| 627 |
|
|
.RXPH_MONITOR_SEL ( 5'd0), //
|
| 628 |
|
|
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
|
| 629 |
|
|
.RXDLY_CFG (16'h001F), //
|
| 630 |
|
|
.RXDLY_LCFG ( 9'h030), //
|
| 631 |
|
|
.RXDLY_TAP_CFG (16'd0), //
|
| 632 |
|
|
.RX_DDI_SEL ( 6'd0), //
|
| 633 |
|
|
|
| 634 |
|
|
.RXSYNC_OVRD (RXSYNC_OVRD), //
|
| 635 |
|
|
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), //
|
| 636 |
|
|
.RXSYNC_SKIP_DA (1'b0), //
|
| 637 |
|
|
|
| 638 |
|
|
//---------- Comma Alignment Attributes --------------------------------
|
| 639 |
|
|
.ALIGN_COMMA_DOUBLE ("FALSE"), //
|
| 640 |
|
|
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
|
| 641 |
|
|
.ALIGN_COMMA_WORD ( 1), //
|
| 642 |
|
|
.ALIGN_MCOMMA_DET ("TRUE"), //
|
| 643 |
|
|
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
|
| 644 |
|
|
.ALIGN_PCOMMA_DET ("TRUE"), //
|
| 645 |
|
|
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
|
| 646 |
|
|
.DEC_MCOMMA_DETECT ("TRUE"), //
|
| 647 |
|
|
.DEC_PCOMMA_DETECT ("TRUE"), //
|
| 648 |
|
|
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
|
| 649 |
|
|
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
|
| 650 |
|
|
.RXSLIDE_AUTO_WAIT ( 7), //
|
| 651 |
|
|
.RXSLIDE_MODE ("PMA"), // PCIe
|
| 652 |
|
|
|
| 653 |
|
|
//---------- Channel Bonding Attributes --------------------------------
|
| 654 |
|
|
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
|
| 655 |
|
|
.CHAN_BOND_MAX_SKEW ( 7), //
|
| 656 |
|
|
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
|
| 657 |
|
|
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
|
| 658 |
|
|
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
|
| 659 |
|
|
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
|
| 660 |
|
|
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
|
| 661 |
|
|
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
|
| 662 |
|
|
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
|
| 663 |
|
|
.CHAN_BOND_SEQ_2_ENABLE (4'b1111), //
|
| 664 |
|
|
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
|
| 665 |
|
|
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
|
| 666 |
|
|
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
|
| 667 |
|
|
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
|
| 668 |
|
|
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
|
| 669 |
|
|
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
|
| 670 |
|
|
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
|
| 671 |
|
|
|
| 672 |
|
|
//---------- Clock Correction Attributes -------------------------------
|
| 673 |
|
|
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
|
| 674 |
|
|
.CLK_CORRECT_USE ("TRUE"), //
|
| 675 |
|
|
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
|
| 676 |
|
|
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
|
| 677 |
|
|
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
|
| 678 |
|
|
.CLK_COR_PRECEDENCE ("TRUE"), //
|
| 679 |
|
|
.CLK_COR_REPEAT_WAIT ( 0), //
|
| 680 |
|
|
.CLK_COR_SEQ_LEN ( 1), //
|
| 681 |
|
|
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
|
| 682 |
|
|
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
|
| 683 |
|
|
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
|
| 684 |
|
|
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
|
| 685 |
|
|
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
|
| 686 |
|
|
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
|
| 687 |
|
|
.CLK_COR_SEQ_2_USE ("FALSE"), //
|
| 688 |
|
|
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
|
| 689 |
|
|
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
|
| 690 |
|
|
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
|
| 691 |
|
|
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
|
| 692 |
|
|
|
| 693 |
|
|
//---------- 8b10b Attributes ------------------------------------------
|
| 694 |
|
|
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
|
| 695 |
|
|
|
| 696 |
|
|
//---------- 64b/66b & 64b/67b Attributes ------------------------------
|
| 697 |
|
|
.GEARBOX_MODE ( 3'd0), //
|
| 698 |
|
|
.TXGEARBOX_EN ("FALSE"), //
|
| 699 |
|
|
.RXGEARBOX_EN ("FALSE"), //
|
| 700 |
|
|
|
| 701 |
|
|
//---------- PRBS & Loopback Attributes ---------------------------------
|
| 702 |
|
|
.LOOPBACK_CFG ( 1'd0), // Enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
|
| 703 |
|
|
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
|
| 704 |
|
|
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
|
| 705 |
|
|
|
| 706 |
|
|
//---------- OOB & SATA Attributes --------------------------------------
|
| 707 |
|
|
.TXOOB_CFG ( 1'd1), // Filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
|
| 708 |
|
|
//.RXOOB_CFG ( 7'b0000110), //
|
| 709 |
|
|
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), //
|
| 710 |
|
|
//.SAS_MAX_COM (64), //
|
| 711 |
|
|
//.SAS_MIN_COM (36), //
|
| 712 |
|
|
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
|
| 713 |
|
|
//.SATA_BURST_VAL ( 3'b100), //
|
| 714 |
|
|
//.SATA_PLL_CFG ("VCO_3000MHZ"), //
|
| 715 |
|
|
//.SATA_EIDLE_VAL ( 3'b100), //
|
| 716 |
|
|
//.SATA_MAX_BURST ( 8), //
|
| 717 |
|
|
//.SATA_MAX_INIT (21), //
|
| 718 |
|
|
//.SATA_MAX_WAKE ( 7), //
|
| 719 |
|
|
//.SATA_MIN_BURST ( 4), //
|
| 720 |
|
|
//.SATA_MIN_INIT (12), //
|
| 721 |
|
|
//.SATA_MIN_WAKE ( 4), //
|
| 722 |
|
|
|
| 723 |
|
|
//---------- MISC ------------------------------------------------------
|
| 724 |
|
|
.DMONITOR_CFG (24'h000B01), //
|
| 725 |
|
|
.RX_DEBUG_CFG (14'h0000), // Optimized for IES
|
| 726 |
|
|
//.TST_RSV (32'd0), //
|
| 727 |
|
|
//.UCODEER_CLR ( 1'd0) //
|
| 728 |
|
|
|
| 729 |
|
|
//---------- GTP -------------------------------------------------------
|
| 730 |
|
|
//.ACJTAG_DEBUG_MODE (1'd0), //
|
| 731 |
|
|
//.ACJTAG_MODE (1'd0), //
|
| 732 |
|
|
//.ACJTAG_RESET (1'd0), //
|
| 733 |
|
|
//.ADAPT_CFG0 (20'd0), //
|
| 734 |
|
|
.CFOK_CFG (43'h490_0004_0E80), // Changed from 42 to 43-bits, Optimized for IES
|
| 735 |
|
|
.CFOK_CFG2 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
|
| 736 |
|
|
.CFOK_CFG3 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
|
| 737 |
|
|
.CFOK_CFG4 ( 1'd0), // GTP new, Optimized for IES
|
| 738 |
|
|
.CFOK_CFG5 ( 2'd0), // GTP new, Optimized for IES
|
| 739 |
|
|
.CFOK_CFG6 ( 4'd0) // GTP new, Optimized for IES
|
| 740 |
|
|
|
| 741 |
|
|
)
|
| 742 |
|
|
gtpe2_channel_i
|
| 743 |
|
|
(
|
| 744 |
|
|
|
| 745 |
|
|
//---------- Clock -----------------------------------------------------
|
| 746 |
|
|
.PLL0CLK (GT_QPLLCLK), //
|
| 747 |
|
|
.PLL1CLK (1'd0), //
|
| 748 |
|
|
.PLL0REFCLK (GT_QPLLREFCLK), //
|
| 749 |
|
|
.PLL1REFCLK (1'd0), //
|
| 750 |
|
|
.TXUSRCLK (GT_TXUSRCLK), //
|
| 751 |
|
|
.RXUSRCLK (GT_RXUSRCLK), //
|
| 752 |
|
|
.TXUSRCLK2 (GT_TXUSRCLK2), //
|
| 753 |
|
|
.RXUSRCLK2 (GT_RXUSRCLK2), //
|
| 754 |
|
|
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
|
| 755 |
|
|
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
|
| 756 |
|
|
.TXOUTCLKSEL (txoutclksel), //
|
| 757 |
|
|
.RXOUTCLKSEL (rxoutclksel), //
|
| 758 |
|
|
.CLKRSVD0 (1'd0), //
|
| 759 |
|
|
.CLKRSVD1 (1'd0), //
|
| 760 |
|
|
|
| 761 |
|
|
.TXOUTCLK (GT_TXOUTCLK), //
|
| 762 |
|
|
.RXOUTCLK (GT_RXOUTCLK), //
|
| 763 |
|
|
.TXOUTCLKFABRIC (), //
|
| 764 |
|
|
.RXOUTCLKFABRIC (), //
|
| 765 |
|
|
.TXOUTCLKPCS (), //
|
| 766 |
|
|
.RXOUTCLKPCS (), //
|
| 767 |
|
|
.RXCDRLOCK (GT_RXCDRLOCK), //
|
| 768 |
|
|
|
| 769 |
|
|
//---------- Reset -----------------------------------------------------
|
| 770 |
|
|
.TXUSERRDY (GT_TXUSERRDY), //
|
| 771 |
|
|
.RXUSERRDY (GT_RXUSERRDY), //
|
| 772 |
|
|
.CFGRESET (1'd0), //
|
| 773 |
|
|
.GTRESETSEL (1'd0), //
|
| 774 |
|
|
.RESETOVRD (GT_RESETOVRD), //
|
| 775 |
|
|
.GTTXRESET (GT_GTTXRESET), //
|
| 776 |
|
|
.GTRXRESET (GT_GTRXRESET), //
|
| 777 |
|
|
|
| 778 |
|
|
.TXRESETDONE (GT_TXRESETDONE), //
|
| 779 |
|
|
.RXRESETDONE (GT_RXRESETDONE), //
|
| 780 |
|
|
|
| 781 |
|
|
//---------- TX Data ---------------------------------------------------
|
| 782 |
|
|
.TXDATA (GT_TXDATA), //
|
| 783 |
|
|
.TXCHARISK (GT_TXDATAK), //
|
| 784 |
|
|
|
| 785 |
|
|
.GTPTXP (GT_TXP), // GTP
|
| 786 |
|
|
.GTPTXN (GT_TXN), // GTP
|
| 787 |
|
|
|
| 788 |
|
|
//---------- RX Data ---------------------------------------------------
|
| 789 |
|
|
.GTPRXP (GT_RXP), // GTP
|
| 790 |
|
|
.GTPRXN (GT_RXN), // GTP
|
| 791 |
|
|
|
| 792 |
|
|
.RXDATA (rxdata[31:0]), //
|
| 793 |
|
|
.RXCHARISK (rxdatak[3:0]), //
|
| 794 |
|
|
|
| 795 |
|
|
//---------- Command ---------------------------------------------------
|
| 796 |
|
|
.TXDETECTRX (GT_TXDETECTRX), //
|
| 797 |
|
|
.TXPDELECIDLEMODE ( 1'd0), //
|
| 798 |
|
|
.RXELECIDLEMODE ( 2'd0), //
|
| 799 |
|
|
.TXELECIDLE (GT_TXELECIDLE), //
|
| 800 |
|
|
.TXCHARDISPMODE ({3'd0, GT_TXCOMPLIANCE}), // Changed from 8 to 4-bits
|
| 801 |
|
|
.TXCHARDISPVAL ( 4'd0), // Changed from 8 to 4-bits
|
| 802 |
|
|
.TXPOLARITY ( 1'd0), //
|
| 803 |
|
|
.RXPOLARITY (GT_RXPOLARITY), //
|
| 804 |
|
|
.TXPD (GT_TXPOWERDOWN), //
|
| 805 |
|
|
.RXPD (GT_RXPOWERDOWN), //
|
| 806 |
|
|
.TXRATE (GT_TXRATE), //
|
| 807 |
|
|
.RXRATE (GT_RXRATE), //
|
| 808 |
|
|
.TXRATEMODE (1'b0), //
|
| 809 |
|
|
.RXRATEMODE (1'b0), //
|
| 810 |
|
|
|
| 811 |
|
|
//---------- Electrical Command ----------------------------------------
|
| 812 |
|
|
.TXMARGIN (GT_TXMARGIN), //
|
| 813 |
|
|
.TXSWING (GT_TXSWING), //
|
| 814 |
|
|
.TXDEEMPH (GT_TXDEEMPH), //
|
| 815 |
|
|
.TXINHIBIT (1'd0), //
|
| 816 |
|
|
.TXBUFDIFFCTRL (3'b100), //
|
| 817 |
|
|
.TXDIFFCTRL (4'b1100), // Select 850mV
|
| 818 |
|
|
.TXPRECURSOR (GT_TXPRECURSOR), //
|
| 819 |
|
|
.TXPRECURSORINV (1'd0), //
|
| 820 |
|
|
.TXMAINCURSOR (GT_TXMAINCURSOR), //
|
| 821 |
|
|
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
|
| 822 |
|
|
.TXPOSTCURSORINV (1'd0), //
|
| 823 |
|
|
|
| 824 |
|
|
//---------- Status ----------------------------------------------------
|
| 825 |
|
|
.RXVALID (GT_RXVALID), //
|
| 826 |
|
|
.PHYSTATUS (GT_PHYSTATUS), //
|
| 827 |
|
|
.RXELECIDLE (GT_RXELECIDLE), //
|
| 828 |
|
|
.RXSTATUS (GT_RXSTATUS), //
|
| 829 |
|
|
.TXRATEDONE (GT_TXRATEDONE), //
|
| 830 |
|
|
.RXRATEDONE (GT_RXRATEDONE), //
|
| 831 |
|
|
|
| 832 |
|
|
//---------- DRP -------------------------------------------------------
|
| 833 |
|
|
.DRPCLK (GT_DRPCLK), //
|
| 834 |
|
|
.DRPADDR (GT_DRPADDR), //
|
| 835 |
|
|
.DRPEN (GT_DRPEN), //
|
| 836 |
|
|
.DRPDI (GT_DRPDI), //
|
| 837 |
|
|
.DRPWE (GT_DRPWE), //
|
| 838 |
|
|
|
| 839 |
|
|
.DRPDO (GT_DRPDO), //
|
| 840 |
|
|
.DRPRDY (GT_DRPRDY), //
|
| 841 |
|
|
|
| 842 |
|
|
//---------- PMA -------------------------------------------------------
|
| 843 |
|
|
.TXPMARESET (GT_TXPMARESET), //
|
| 844 |
|
|
.RXPMARESET (GT_RXPMARESET), //
|
| 845 |
|
|
.RXLPMRESET ( 1'd0), // GTP new
|
| 846 |
|
|
.RXLPMOSINTNTRLEN ( 1'd0), // GTP new
|
| 847 |
|
|
.RXLPMHFHOLD ( 1'd0), //
|
| 848 |
|
|
.RXLPMHFOVRDEN ( 1'd0), //
|
| 849 |
|
|
.RXLPMLFHOLD ( 1'd0), //
|
| 850 |
|
|
.RXLPMLFOVRDEN ( 1'd0), //
|
| 851 |
|
|
.PMARSVDIN0 ( 1'd0), // GTP new
|
| 852 |
|
|
.PMARSVDIN1 ( 1'd0), // GTP new
|
| 853 |
|
|
.PMARSVDIN2 ( 1'd0), // GTP new
|
| 854 |
|
|
.PMARSVDIN3 ( 1'd0), // GTP new
|
| 855 |
|
|
.PMARSVDIN4 ( 1'd0), // GTP new
|
| 856 |
|
|
.GTRSVD (16'd0), //
|
| 857 |
|
|
|
| 858 |
|
|
.PMARSVDOUT0 (), // GTP new
|
| 859 |
|
|
.PMARSVDOUT1 (), // GTP new
|
| 860 |
|
|
.DMONITOROUT (dmonitorout), // GTP 15-bits
|
| 861 |
|
|
|
| 862 |
|
|
//---------- PCS -------------------------------------------------------
|
| 863 |
|
|
.TXPCSRESET (GT_TXPCSRESET), //
|
| 864 |
|
|
.RXPCSRESET (GT_RXPCSRESET), //
|
| 865 |
|
|
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
|
| 866 |
|
|
|
| 867 |
|
|
.PCSRSVDOUT (), //
|
| 868 |
|
|
|
| 869 |
|
|
//---------- CDR -------------------------------------------------------
|
| 870 |
|
|
.RXCDRRESET (GT_RXCDRRESET), //
|
| 871 |
|
|
.RXCDRRESETRSV (1'd0), //
|
| 872 |
|
|
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
|
| 873 |
|
|
.RXCDRHOLD (1'd0), //
|
| 874 |
|
|
.RXCDROVRDEN (1'd0), //
|
| 875 |
|
|
|
| 876 |
|
|
//---------- PI --------------------------------------------------------
|
| 877 |
|
|
.TXPIPPMEN (1'd0), //
|
| 878 |
|
|
.TXPIPPMOVRDEN (1'd0), //
|
| 879 |
|
|
.TXPIPPMPD (1'd0), //
|
| 880 |
|
|
.TXPIPPMSEL (1'd0), //
|
| 881 |
|
|
.TXPIPPMSTEPSIZE (5'd0), //
|
| 882 |
|
|
.TXPISOPD (1'd0), // GTP new
|
| 883 |
|
|
|
| 884 |
|
|
//---------- DFE -------------------------------------------------------
|
| 885 |
|
|
.RXDFEXYDEN (1'd0), //
|
| 886 |
|
|
|
| 887 |
|
|
//---------- OS --------------------------------------------------------
|
| 888 |
|
|
.RXOSHOLD (1'd0), // Optimized for IES
|
| 889 |
|
|
.RXOSOVRDEN (1'd0), // Optimized for IES
|
| 890 |
|
|
.RXOSINTEN (1'd1), // Optimized for IES
|
| 891 |
|
|
.RXOSINTHOLD (1'd0), // Optimized for IES
|
| 892 |
|
|
.RXOSINTNTRLEN (1'd0), // Optimized for IES
|
| 893 |
|
|
.RXOSINTOVRDEN (1'd0), // Optimized for IES
|
| 894 |
|
|
.RXOSINTPD (1'd0), // GTP new, Optimized for IES
|
| 895 |
|
|
.RXOSINTSTROBE (1'd0), // Optimized for IES
|
| 896 |
|
|
.RXOSINTTESTOVRDEN (1'd0), // Optimized for IES
|
| 897 |
|
|
.RXOSINTCFG (4'b0010), // Optimized for IES
|
| 898 |
|
|
.RXOSINTID0 (4'd0), // Optimized for IES
|
| 899 |
|
|
|
| 900 |
|
|
.RXOSINTDONE (), //
|
| 901 |
|
|
.RXOSINTSTARTED (), //
|
| 902 |
|
|
.RXOSINTSTROBEDONE (), //
|
| 903 |
|
|
.RXOSINTSTROBESTARTED (), //
|
| 904 |
|
|
|
| 905 |
|
|
//---------- Eye Scan --------------------------------------------------
|
| 906 |
|
|
.EYESCANRESET (GT_EYESCANRESET), //
|
| 907 |
|
|
.EYESCANMODE (1'd0), //
|
| 908 |
|
|
.EYESCANTRIGGER (1'd0), //
|
| 909 |
|
|
|
| 910 |
|
|
.EYESCANDATAERROR (), //
|
| 911 |
|
|
|
| 912 |
|
|
//---------- TX Buffer -------------------------------------------------
|
| 913 |
|
|
.TXBUFSTATUS (), //
|
| 914 |
|
|
|
| 915 |
|
|
//---------- RX Buffer -------------------------------------------------
|
| 916 |
|
|
.RXBUFRESET (GT_RXBUFRESET), //
|
| 917 |
|
|
|
| 918 |
|
|
.RXBUFSTATUS (GT_RXBUFSTATUS), //
|
| 919 |
|
|
|
| 920 |
|
|
//---------- TX Sync ---------------------------------------------------
|
| 921 |
|
|
.TXPHDLYRESET (GT_TXPHDLYRESET), //
|
| 922 |
|
|
.TXPHDLYTSTCLK (1'd0), //
|
| 923 |
|
|
.TXPHALIGN (GT_TXPHALIGN), //
|
| 924 |
|
|
.TXPHALIGNEN (GT_TXPHALIGNEN), //
|
| 925 |
|
|
.TXPHDLYPD (1'd0), //
|
| 926 |
|
|
.TXPHINIT (GT_TXPHINIT), //
|
| 927 |
|
|
.TXPHOVRDEN (1'd0), //
|
| 928 |
|
|
.TXDLYBYPASS (GT_TXDLYBYPASS), //
|
| 929 |
|
|
.TXDLYSRESET (GT_TXDLYSRESET), //
|
| 930 |
|
|
.TXDLYEN (GT_TXDLYEN), //
|
| 931 |
|
|
.TXDLYOVRDEN (1'd0), //
|
| 932 |
|
|
.TXDLYHOLD (1'd0), //
|
| 933 |
|
|
.TXDLYUPDOWN (1'd0), //
|
| 934 |
|
|
|
| 935 |
|
|
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
|
| 936 |
|
|
.TXPHINITDONE (GT_TXPHINITDONE), //
|
| 937 |
|
|
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
|
| 938 |
|
|
|
| 939 |
|
|
.TXSYNCMODE (GT_TXSYNCMODE), //
|
| 940 |
|
|
.TXSYNCIN (GT_TXSYNCIN), //
|
| 941 |
|
|
.TXSYNCALLIN (GT_TXSYNCALLIN), //
|
| 942 |
|
|
|
| 943 |
|
|
.TXSYNCDONE (GT_TXSYNCDONE), //
|
| 944 |
|
|
.TXSYNCOUT (GT_TXSYNCOUT), //
|
| 945 |
|
|
|
| 946 |
|
|
//---------- RX Sync ---------------------------------------------------
|
| 947 |
|
|
.RXPHDLYRESET (1'd0), //
|
| 948 |
|
|
.RXPHALIGN (GT_RXPHALIGN), //
|
| 949 |
|
|
.RXPHALIGNEN (GT_RXPHALIGNEN), //
|
| 950 |
|
|
.RXPHDLYPD (1'd0), //
|
| 951 |
|
|
.RXPHOVRDEN (1'd0), //
|
| 952 |
|
|
.RXDLYBYPASS (GT_RXDLYBYPASS), //
|
| 953 |
|
|
.RXDLYSRESET (GT_RXDLYSRESET), //
|
| 954 |
|
|
.RXDLYEN (GT_RXDLYEN), //
|
| 955 |
|
|
.RXDLYOVRDEN (1'd0), //
|
| 956 |
|
|
.RXDDIEN (GT_RXDDIEN), //
|
| 957 |
|
|
|
| 958 |
|
|
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
|
| 959 |
|
|
.RXPHMONITOR (), //
|
| 960 |
|
|
.RXPHSLIPMONITOR (), //
|
| 961 |
|
|
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
|
| 962 |
|
|
|
| 963 |
|
|
.RXSYNCMODE (GT_RXSYNCMODE), //
|
| 964 |
|
|
.RXSYNCIN (GT_RXSYNCIN), //
|
| 965 |
|
|
.RXSYNCALLIN (GT_RXSYNCALLIN), //
|
| 966 |
|
|
|
| 967 |
|
|
.RXSYNCDONE (GT_RXSYNCDONE), //
|
| 968 |
|
|
.RXSYNCOUT (GT_RXSYNCOUT), //
|
| 969 |
|
|
|
| 970 |
|
|
//---------- Comma Alignment -------------------------------------------
|
| 971 |
|
|
.RXCOMMADETEN (1'd1), //
|
| 972 |
|
|
.RXMCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
|
| 973 |
|
|
.RXPCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
|
| 974 |
|
|
.RXSLIDE (GT_RXSLIDE), //
|
| 975 |
|
|
.RXCOMMADET (GT_RXCOMMADET), //
|
| 976 |
|
|
.RXCHARISCOMMA (rxchariscomma[3:0]), //
|
| 977 |
|
|
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
|
| 978 |
|
|
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
|
| 979 |
|
|
|
| 980 |
|
|
//---------- Channel Bonding -------------------------------------------
|
| 981 |
|
|
.RXCHBONDEN (GT_RXCHBONDEN), //
|
| 982 |
|
|
.RXCHBONDI (GT_RXCHBONDI[3:0]), //
|
| 983 |
|
|
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
|
| 984 |
|
|
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
|
| 985 |
|
|
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
|
| 986 |
|
|
|
| 987 |
|
|
.RXCHANBONDSEQ (), //
|
| 988 |
|
|
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
|
| 989 |
|
|
.RXCHANREALIGN (), //
|
| 990 |
|
|
.RXCHBONDO (GT_RXCHBONDO[3:0]), //
|
| 991 |
|
|
|
| 992 |
|
|
//---------- Clock Correction -----------------------------------------
|
| 993 |
|
|
.RXCLKCORCNT (), //
|
| 994 |
|
|
|
| 995 |
|
|
//---------- 8b10b -----------------------------------------------------
|
| 996 |
|
|
.TX8B10BBYPASS (4'd0), //
|
| 997 |
|
|
.TX8B10BEN (1'b1), // No Gen3 support in GTP
|
| 998 |
|
|
.RX8B10BEN (1'b1), // No Gen3 support in GTP
|
| 999 |
|
|
|
| 1000 |
|
|
.RXDISPERR (), //
|
| 1001 |
|
|
.RXNOTINTABLE (), //
|
| 1002 |
|
|
|
| 1003 |
|
|
//---------- 64b/66b & 64b/67b -----------------------------------------
|
| 1004 |
|
|
.TXHEADER (3'd0), //
|
| 1005 |
|
|
.TXSEQUENCE (7'd0), //
|
| 1006 |
|
|
.TXSTARTSEQ (1'd0), //
|
| 1007 |
|
|
.RXGEARBOXSLIP (1'd0), //
|
| 1008 |
|
|
|
| 1009 |
|
|
.TXGEARBOXREADY (), //
|
| 1010 |
|
|
.RXDATAVALID (), //
|
| 1011 |
|
|
.RXHEADER (), //
|
| 1012 |
|
|
.RXHEADERVALID (), //
|
| 1013 |
|
|
.RXSTARTOFSEQ (), //
|
| 1014 |
|
|
|
| 1015 |
|
|
//---------- PRBS/Loopback ---------------------------------------------
|
| 1016 |
|
|
.TXPRBSSEL (GT_TXPRBSSEL), //
|
| 1017 |
|
|
.RXPRBSSEL (GT_RXPRBSSEL), //
|
| 1018 |
|
|
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
|
| 1019 |
|
|
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
|
| 1020 |
|
|
.LOOPBACK (GT_LOOPBACK), //
|
| 1021 |
|
|
|
| 1022 |
|
|
.RXPRBSERR (GT_RXPRBSERR), //
|
| 1023 |
|
|
|
| 1024 |
|
|
//---------- OOB -------------------------------------------------------
|
| 1025 |
|
|
.SIGVALIDCLK (GT_OOBCLK), // Optimized for debug
|
| 1026 |
|
|
.TXCOMINIT (1'd0), //
|
| 1027 |
|
|
.TXCOMSAS (1'd0), //
|
| 1028 |
|
|
.TXCOMWAKE (1'd0), //
|
| 1029 |
|
|
.RXOOBRESET (1'd0), //
|
| 1030 |
|
|
|
| 1031 |
|
|
.TXCOMFINISH (), //
|
| 1032 |
|
|
.RXCOMINITDET (), //
|
| 1033 |
|
|
.RXCOMSASDET (), //
|
| 1034 |
|
|
.RXCOMWAKEDET (), //
|
| 1035 |
|
|
|
| 1036 |
|
|
//---------- MISC ------------------------------------------------------
|
| 1037 |
|
|
.SETERRSTATUS ( 1'd0), //
|
| 1038 |
|
|
.TXDIFFPD ( 1'd0), //
|
| 1039 |
|
|
.TSTIN (20'hFFFFF), //
|
| 1040 |
|
|
|
| 1041 |
|
|
//---------- GTP -------------------------------------------------------
|
| 1042 |
|
|
.RXADAPTSELTEST (14'd0), //
|
| 1043 |
|
|
.DMONFIFORESET ( 1'd0), //
|
| 1044 |
|
|
.DMONITORCLK (dmonitorclk), //
|
| 1045 |
|
|
.RXOSCALRESET ( 1'd0), //
|
| 1046 |
|
|
|
| 1047 |
|
|
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTP
|
| 1048 |
|
|
.TXPMARESETDONE () //
|
| 1049 |
|
|
|
| 1050 |
|
|
);
|
| 1051 |
|
|
|
| 1052 |
|
|
assign GT_CPLLLOCK = 1'b0;
|
| 1053 |
|
|
|
| 1054 |
|
|
end
|
| 1055 |
|
|
|
| 1056 |
|
|
else if (PCIE_GT_DEVICE == "GTH")
|
| 1057 |
|
|
|
| 1058 |
|
|
begin : gth_channel
|
| 1059 |
|
|
|
| 1060 |
|
|
//---------- GTH Channel Module --------------------------------------------
|
| 1061 |
|
|
GTHE2_CHANNEL #
|
| 1062 |
|
|
(
|
| 1063 |
|
|
|
| 1064 |
|
|
//---------- Simulation Attributes -------------------------------------
|
| 1065 |
|
|
.SIM_CPLLREFCLK_SEL (3'b001), //
|
| 1066 |
|
|
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
|
| 1067 |
|
|
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
|
| 1068 |
|
|
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
|
| 1069 |
|
|
.SIM_VERSION ("2.0"), //
|
| 1070 |
|
|
|
| 1071 |
|
|
//---------- Clock Attributes ------------------------------------------
|
| 1072 |
|
|
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
|
| 1073 |
|
|
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
|
| 1074 |
|
|
.CPLL_FBDIV (CPLL_FBDIV), //
|
| 1075 |
|
|
.TXOUT_DIV (OUT_DIV), //
|
| 1076 |
|
|
.RXOUT_DIV (OUT_DIV), //
|
| 1077 |
|
|
.TX_CLK25_DIV (CLK25_DIV), //
|
| 1078 |
|
|
.RX_CLK25_DIV (CLK25_DIV), //
|
| 1079 |
|
|
.TX_CLKMUX_PD ( 1'b1), // GTH
|
| 1080 |
|
|
.RX_CLKMUX_PD ( 1'b1), // GTH
|
| 1081 |
|
|
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
|
| 1082 |
|
|
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
|
| 1083 |
|
|
.OUTREFCLK_SEL_INV ( 2'b11), //
|
| 1084 |
|
|
.CPLL_CFG (29'h00A407CC), // Changed from 24 to 29-bits, Optimized for PCIe PLL BW
|
| 1085 |
|
|
.CPLL_INIT_CFG (24'h00001E), // Optimized for IES
|
| 1086 |
|
|
.CPLL_LOCK_CFG (16'h01E8), // Optimized for IES
|
| 1087 |
|
|
//.USE_PCS_CLK_PHASE_SEL ( 1'd0) // GTH new
|
| 1088 |
|
|
|
| 1089 |
|
|
//---------- Reset Attributes ------------------------------------------
|
| 1090 |
|
|
.TXPCSRESET_TIME (5'b00001), //
|
| 1091 |
|
|
.RXPCSRESET_TIME (5'b00001), //
|
| 1092 |
|
|
.TXPMARESET_TIME (5'b00011), //
|
| 1093 |
|
|
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
|
| 1094 |
|
|
//.RXISCANRESET_TIME (5'b00001), //
|
| 1095 |
|
|
//.RESET_POWERSAVE_DISABLE ( 1'd0), // GTH new
|
| 1096 |
|
|
|
| 1097 |
|
|
//---------- TX Data Attributes ----------------------------------------
|
| 1098 |
|
|
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
|
| 1099 |
|
|
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
|
| 1100 |
|
|
|
| 1101 |
|
|
//---------- RX Data Attributes ----------------------------------------
|
| 1102 |
|
|
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
|
| 1103 |
|
|
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
|
| 1104 |
|
|
|
| 1105 |
|
|
//---------- Command Attributes ----------------------------------------
|
| 1106 |
|
|
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
|
| 1107 |
|
|
.TX_RXDETECT_PRECHARGE_TIME (17'h00001), // GTH new, Optimized for sim
|
| 1108 |
|
|
.TX_RXDETECT_REF ( 3'b011), //
|
| 1109 |
|
|
.RX_CM_SEL ( 2'b11), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable, optimized for silicon
|
| 1110 |
|
|
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for silicon
|
| 1111 |
|
|
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
|
| 1112 |
|
|
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
|
| 1113 |
|
|
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
|
| 1114 |
|
|
.PD_TRANS_TIME_NONE_P2 ( 8'h09), // Optimized for sim
|
| 1115 |
|
|
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
|
| 1116 |
|
|
//.TRANS_TIME_RATE ( 8'h0E), //
|
| 1117 |
|
|
|
| 1118 |
|
|
//---------- Electrical Command Attributes -----------------------------
|
| 1119 |
|
|
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
|
| 1120 |
|
|
.TX_DEEMPH0 ( 6'b010100), // 6.0 dB, optimized for compliance, changed from 5 to 6-bits
|
| 1121 |
|
|
.TX_DEEMPH1 ( 6'b001011), // 3.5 dB, optimized for compliance, changed from 5 to 6-bits
|
| 1122 |
|
|
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
|
| 1123 |
|
|
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
|
| 1124 |
|
|
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
|
| 1125 |
|
|
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
|
| 1126 |
|
|
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
|
| 1127 |
|
|
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
|
| 1128 |
|
|
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
|
| 1129 |
|
|
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
|
| 1130 |
|
|
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
|
| 1131 |
|
|
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
|
| 1132 |
|
|
.TX_MAINCURSOR_SEL ( 1'b0), //
|
| 1133 |
|
|
.TX_QPI_STATUS_EN ( 1'b0), //
|
| 1134 |
|
|
|
| 1135 |
|
|
//---------- Status Attributes -----------------------------------------
|
| 1136 |
|
|
.RX_SIG_VALID_DLY (4), // Optimized for sim
|
| 1137 |
|
|
|
| 1138 |
|
|
//---------- DRP Attributes --------------------------------------------
|
| 1139 |
|
|
|
| 1140 |
|
|
//---------- PCS Attributes --------------------------------------------
|
| 1141 |
|
|
.PCS_PCIE_EN ("TRUE"), // PCIe
|
| 1142 |
|
|
.PCS_RSVD_ATTR (48'h0000_0000_0140), // [8] : 1 = OOB power-up, [6] : 1 = DMON enable, Optimized for IES
|
| 1143 |
|
|
|
| 1144 |
|
|
//---------- PMA Attributes --------------------------------------------
|
| 1145 |
|
|
.PMA_RSV (32'h00000080), // Optimized for IES
|
| 1146 |
|
|
.PMA_RSV2 (32'h1C00000A), // Changed from 16 to 32-bits, Optimized for IES
|
| 1147 |
|
|
//.PMA_RSV3 ( 2'h0), //
|
| 1148 |
|
|
.PMA_RSV4 (15'h0008), // GTH new, Optimized for IES
|
| 1149 |
|
|
//.PMA_RSV5 ( 4'h00), // GTH new
|
| 1150 |
|
|
.RX_BIAS_CFG (24'h0C0010), // Changed from 12 to 24-bits, Optimized for IES
|
| 1151 |
|
|
.TERM_RCAL_CFG (15'b100001000010000), // Changed from 5 to 15-bits, Optimized for IES
|
| 1152 |
|
|
.TERM_RCAL_OVRD ( 3'b000), // Changed from 1 to 3-bits, Optimized for IES
|
| 1153 |
|
|
|
| 1154 |
|
|
//---------- TX PI -----------------------------------------------------
|
| 1155 |
|
|
//.TXPI_CFG0 ( 2'd0), // GTH new
|
| 1156 |
|
|
//.TXPI_CFG1 ( 2'd0), // GTH new
|
| 1157 |
|
|
//.TXPI_CFG2 ( 2'd0), // GTH new
|
| 1158 |
|
|
//.TXPI_CFG3 ( 1'd0), // GTH new
|
| 1159 |
|
|
//.TXPI_CFG4 ( 1'd0), // GTH new
|
| 1160 |
|
|
//.TXPI_CFG5 ( 3'b100), // GTH new
|
| 1161 |
|
|
//.TXPI_GREY_SEL ( 1'd0), // GTH new
|
| 1162 |
|
|
//.TXPI_INVSTROBE_SEL ( 1'd0), // GTH new
|
| 1163 |
|
|
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // GTH new
|
| 1164 |
|
|
//.TXPI_PPM_CFG ( 8'd0), // GTH new
|
| 1165 |
|
|
//.TXPI_SYNFREQ_PPM ( 3'd0), // GTH new
|
| 1166 |
|
|
|
| 1167 |
|
|
//---------- RX PI -----------------------------------------------------
|
| 1168 |
|
|
.RXPI_CFG0 (2'b00), // GTH new
|
| 1169 |
|
|
.RXPI_CFG1 (2'b11), // GTH new
|
| 1170 |
|
|
.RXPI_CFG2 (2'b11), // GTH new
|
| 1171 |
|
|
.RXPI_CFG3 (2'b11), // GTH new
|
| 1172 |
|
|
.RXPI_CFG4 (1'b0), // GTH new
|
| 1173 |
|
|
.RXPI_CFG5 (1'b0), // GTH new
|
| 1174 |
|
|
.RXPI_CFG6 (3'b100), // GTH new
|
| 1175 |
|
|
|
| 1176 |
|
|
//---------- CDR Attributes --------------------------------------------
|
| 1177 |
|
|
.RXCDR_CFG (RXCDR_CFG_GTH), //
|
| 1178 |
|
|
//.RXCDR_CFG (83'h0_0011_07FE_4060_0104_1010), // A. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, default, converted from GTX GES VnC,(2 Gen1)
|
| 1179 |
|
|
//.RXCDR_CFG (83'h0_0011_07FE_4060_2104_1010), // B. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, default, converted from GTX GES VnC,(2 Gen1)
|
| 1180 |
|
|
//.RXCDR_CFG (83'h0_0011_07FE_2060_0104_1010), // C. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, converted from GTX GES recommended, (3 Gen1)
|
| 1181 |
|
|
//.RXCDR_CFG (83'h0_0011_07FE_2060_2104_1010), // D. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, converted from GTX GES recommended, (3 Gen1)
|
| 1182 |
|
|
//.RXCDR_CFG (83'h0_0001_07FE_1060_0110_1010), // E. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, default, (3 Gen2)
|
| 1183 |
|
|
//.RXCDR_CFG (83'h0_0001_07FE_1060_2110_1010), // F. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, default, (3 Gen2)
|
| 1184 |
|
|
//.RXCDR_CFG (83'h0_0011_07FE_1060_0110_1010), // G. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, converted from GTX GES recommended, (3 Gen2)
|
| 1185 |
|
|
//.RXCDR_CFG (83'h0_0011_07FE_1060_2110_1010), // H. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, converted from GTX GES recommended, (2 Gen1)
|
| 1186 |
|
|
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
|
| 1187 |
|
|
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
|
| 1188 |
|
|
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
|
| 1189 |
|
|
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
|
| 1190 |
|
|
//.RXCDRFREQRESET_TIME ( 5'b00001), // optimized for IES
|
| 1191 |
|
|
//.RXCDRPHRESET_TIME ( 5'b00001), // optimized for IES
|
| 1192 |
|
|
|
| 1193 |
|
|
//---------- LPM Attributes --------------------------------------------
|
| 1194 |
|
|
.RXLPM_HF_CFG (14'h0200), // Optimized for IES
|
| 1195 |
|
|
.RXLPM_LF_CFG (18'h09000), // Changed from 14 to 18-bits, Optimized for IES
|
| 1196 |
|
|
|
| 1197 |
|
|
//---------- DFE Attributes --------------------------------------------
|
| 1198 |
|
|
.RXDFELPMRESET_TIME ( 7'h0F), // Optimized for IES
|
| 1199 |
|
|
.RX_DFE_AGC_CFG0 ( 2'h0), // GTH new, optimized for IES
|
| 1200 |
|
|
.RX_DFE_AGC_CFG1 ( 3'h4), // GTH new, optimized for IES, DFE
|
| 1201 |
|
|
.RX_DFE_AGC_CFG2 ( 4'h0), // GTH new, optimized for IES
|
| 1202 |
|
|
.RX_DFE_AGC_OVRDEN ( 1'h1), // GTH new, optimized for IES
|
| 1203 |
|
|
.RX_DFE_GAIN_CFG (23'h0020C0), // Optimized for IES
|
| 1204 |
|
|
.RX_DFE_H2_CFG (12'h000), // Optimized for IES
|
| 1205 |
|
|
.RX_DFE_H3_CFG (12'h040), // Optimized for IES
|
| 1206 |
|
|
.RX_DFE_H4_CFG (11'h0E0), // Optimized for IES
|
| 1207 |
|
|
.RX_DFE_H5_CFG (11'h0E0), // Optimized for IES
|
| 1208 |
|
|
.RX_DFE_H6_CFG (11'h020), // GTH new, optimized for IES
|
| 1209 |
|
|
.RX_DFE_H7_CFG (11'h020), // GTH new, optimized for IES
|
| 1210 |
|
|
.RX_DFE_KL_CFG (33'h000000310), // Changed from 13 to 33-bits, optimized for IES
|
| 1211 |
|
|
.RX_DFE_KL_LPM_KH_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
|
| 1212 |
|
|
.RX_DFE_KL_LPM_KH_CFG1 ( 3'h2), // GTH new, optimized for IES
|
| 1213 |
|
|
.RX_DFE_KL_LPM_KH_CFG2 ( 4'h2), // GTH new, optimized for IES
|
| 1214 |
|
|
.RX_DFE_KL_LPM_KH_OVRDEN ( 1'h1), // GTH new, optimized for IES
|
| 1215 |
|
|
.RX_DFE_KL_LPM_KL_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
|
| 1216 |
|
|
.RX_DFE_KL_LPM_KL_CFG1 ( 3'h2), // GTH new, optimized for IES
|
| 1217 |
|
|
.RX_DFE_KL_LPM_KL_CFG2 ( 4'h2), // GTH new, optimized for IES
|
| 1218 |
|
|
.RX_DFE_KL_LPM_KL_OVRDEN ( 1'b1), // GTH new, optimized for IES
|
| 1219 |
|
|
.RX_DFE_LPM_CFG (16'h0080), // Optimized for IES
|
| 1220 |
|
|
.RX_DFELPM_CFG0 ( 4'h6), // GTH new, optimized for IES
|
| 1221 |
|
|
.RX_DFELPM_CFG1 ( 4'h0), // GTH new, optimized for IES
|
| 1222 |
|
|
.RX_DFELPM_KLKH_AGC_STUP_EN ( 1'h1), // GTH new, optimized for IES
|
| 1223 |
|
|
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'h1), // PCIe use mode
|
| 1224 |
|
|
.RX_DFE_ST_CFG (54'h00_C100_000C_003F), // GTH new, optimized for IES
|
| 1225 |
|
|
.RX_DFE_UT_CFG (17'h03800), // Optimized for IES
|
| 1226 |
|
|
.RX_DFE_VP_CFG (17'h03AA3), // Optimized for IES
|
| 1227 |
|
|
|
| 1228 |
|
|
//---------- OS Attributes ---------------------------------------------
|
| 1229 |
|
|
.RX_OS_CFG (13'h0080), // Optimized for IES
|
| 1230 |
|
|
.A_RXOSCALRESET ( 1'd0), // GTH new, optimized for IES
|
| 1231 |
|
|
.RXOSCALRESET_TIME ( 5'b00011), // GTH new, optimized for IES
|
| 1232 |
|
|
.RXOSCALRESET_TIMEOUT ( 5'b00000), // GTH new, disable timeout, optimized for IES
|
| 1233 |
|
|
|
| 1234 |
|
|
//---------- Eye Scan Attributes ---------------------------------------
|
| 1235 |
|
|
//.ES_CLK_PHASE_SEL ( 1'd0), // GTH new
|
| 1236 |
|
|
//.ES_CONTROL ( 6'd0), //
|
| 1237 |
|
|
//.ES_ERRDET_EN ("FALSE"), //
|
| 1238 |
|
|
.ES_EYE_SCAN_EN ("TRUE"), // Optimized for IES
|
| 1239 |
|
|
.ES_HORZ_OFFSET (12'h000), // Optimized for IES
|
| 1240 |
|
|
//.ES_PMA_CFG (10'd0), //
|
| 1241 |
|
|
//.ES_PRESCALE ( 5'd0), //
|
| 1242 |
|
|
//.ES_QUAL_MASK (80'd0), //
|
| 1243 |
|
|
//.ES_QUALIFIER (80'd0), //
|
| 1244 |
|
|
//.ES_SDATA_MASK (80'd0), //
|
| 1245 |
|
|
//.ES_VERT_OFFSET ( 9'd0), //
|
| 1246 |
|
|
|
| 1247 |
|
|
//---------- TX Buffer Attributes --------------------------------------
|
| 1248 |
|
|
.TXBUF_EN (PCIE_TXBUF_EN), //
|
| 1249 |
|
|
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
|
| 1250 |
|
|
|
| 1251 |
|
|
//---------- RX Buffer Attributes --------------------------------------
|
| 1252 |
|
|
.RXBUF_EN ("TRUE"), //
|
| 1253 |
|
|
//.RX_BUFFER_CFG ( 6'd0), //
|
| 1254 |
|
|
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
|
| 1255 |
|
|
.RXBUF_ADDR_MODE ("FULL"), //
|
| 1256 |
|
|
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
|
| 1257 |
|
|
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
|
| 1258 |
|
|
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
|
| 1259 |
|
|
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
|
| 1260 |
|
|
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
|
| 1261 |
|
|
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
|
| 1262 |
|
|
.RXBUF_THRESH_OVRD ("FALSE"), //
|
| 1263 |
|
|
.RXBUF_THRESH_OVFLW (61), //
|
| 1264 |
|
|
.RXBUF_THRESH_UNDFLW ( 4), //
|
| 1265 |
|
|
//.RXBUFRESET_TIME ( 5'b00001), //
|
| 1266 |
|
|
|
| 1267 |
|
|
//---------- TX Sync Attributes ----------------------------------------
|
| 1268 |
|
|
//.TXPH_CFG (16'h0780), //
|
| 1269 |
|
|
.TXPH_MONITOR_SEL ( 5'd0), //
|
| 1270 |
|
|
//.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
|
| 1271 |
|
|
//.TXDLY_CFG (16'h001F), //
|
| 1272 |
|
|
//.TXDLY_LCFG ( 9'h030), //
|
| 1273 |
|
|
//.TXDLY_TAP_CFG (16'd0), //
|
| 1274 |
|
|
|
| 1275 |
|
|
.TXSYNC_OVRD (TXSYNC_OVRD), // GTH new
|
| 1276 |
|
|
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), // GTH new
|
| 1277 |
|
|
.TXSYNC_SKIP_DA (1'b0), // GTH new
|
| 1278 |
|
|
|
| 1279 |
|
|
//---------- RX Sync Attributes ----------------------------------------
|
| 1280 |
|
|
//.RXPH_CFG (24'd0), //
|
| 1281 |
|
|
.RXPH_MONITOR_SEL ( 5'd0), //
|
| 1282 |
|
|
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
|
| 1283 |
|
|
//.RXDLY_CFG (16'h001F), //
|
| 1284 |
|
|
//.RXDLY_LCFG ( 9'h030), //
|
| 1285 |
|
|
//.RXDLY_TAP_CFG (16'd0), //
|
| 1286 |
|
|
.RX_DDI_SEL ( 6'd0), //
|
| 1287 |
|
|
|
| 1288 |
|
|
.RXSYNC_OVRD (RXSYNC_OVRD), // GTH new
|
| 1289 |
|
|
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), // GTH new
|
| 1290 |
|
|
.RXSYNC_SKIP_DA (1'b0), // GTH new
|
| 1291 |
|
|
|
| 1292 |
|
|
//---------- Comma Alignment Attributes --------------------------------
|
| 1293 |
|
|
.ALIGN_COMMA_DOUBLE ("FALSE"), //
|
| 1294 |
|
|
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
|
| 1295 |
|
|
.ALIGN_COMMA_WORD ( 1), //
|
| 1296 |
|
|
.ALIGN_MCOMMA_DET ("TRUE"), //
|
| 1297 |
|
|
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
|
| 1298 |
|
|
.ALIGN_PCOMMA_DET ("TRUE"), //
|
| 1299 |
|
|
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
|
| 1300 |
|
|
.DEC_MCOMMA_DETECT ("TRUE"), //
|
| 1301 |
|
|
.DEC_PCOMMA_DETECT ("TRUE"), //
|
| 1302 |
|
|
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
|
| 1303 |
|
|
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
|
| 1304 |
|
|
.RXSLIDE_AUTO_WAIT ( 7), //
|
| 1305 |
|
|
.RXSLIDE_MODE ("PMA"), // PCIe
|
| 1306 |
|
|
|
| 1307 |
|
|
//---------- Channel Bonding Attributes --------------------------------
|
| 1308 |
|
|
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
|
| 1309 |
|
|
.CHAN_BOND_MAX_SKEW ( 7), //
|
| 1310 |
|
|
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
|
| 1311 |
|
|
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
|
| 1312 |
|
|
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
|
| 1313 |
|
|
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
|
| 1314 |
|
|
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
|
| 1315 |
|
|
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
|
| 1316 |
|
|
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
|
| 1317 |
|
|
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
|
| 1318 |
|
|
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
|
| 1319 |
|
|
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
|
| 1320 |
|
|
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
|
| 1321 |
|
|
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
|
| 1322 |
|
|
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
|
| 1323 |
|
|
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
|
| 1324 |
|
|
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
|
| 1325 |
|
|
|
| 1326 |
|
|
//---------- Clock Correction Attributes -------------------------------
|
| 1327 |
|
|
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
|
| 1328 |
|
|
.CLK_CORRECT_USE ("TRUE"), //
|
| 1329 |
|
|
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
|
| 1330 |
|
|
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
|
| 1331 |
|
|
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
|
| 1332 |
|
|
.CLK_COR_PRECEDENCE ("TRUE"), //
|
| 1333 |
|
|
.CLK_COR_REPEAT_WAIT ( 0), //
|
| 1334 |
|
|
.CLK_COR_SEQ_LEN ( 1), //
|
| 1335 |
|
|
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
|
| 1336 |
|
|
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
|
| 1337 |
|
|
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
|
| 1338 |
|
|
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
|
| 1339 |
|
|
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
|
| 1340 |
|
|
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
|
| 1341 |
|
|
.CLK_COR_SEQ_2_USE ("FALSE"), //
|
| 1342 |
|
|
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
|
| 1343 |
|
|
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
|
| 1344 |
|
|
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
|
| 1345 |
|
|
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
|
| 1346 |
|
|
|
| 1347 |
|
|
//---------- 8b10b Attributes ------------------------------------------
|
| 1348 |
|
|
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
|
| 1349 |
|
|
|
| 1350 |
|
|
//---------- 64b/66b & 64b/67b Attributes ------------------------------
|
| 1351 |
|
|
.GEARBOX_MODE (3'd0), //
|
| 1352 |
|
|
.TXGEARBOX_EN ("FALSE"), //
|
| 1353 |
|
|
.RXGEARBOX_EN ("FALSE"), //
|
| 1354 |
|
|
|
| 1355 |
|
|
//---------- PRBS & Loopback Attributes --------------------------------
|
| 1356 |
|
|
.LOOPBACK_CFG ( 1'd1), // GTH new, enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
|
| 1357 |
|
|
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
|
| 1358 |
|
|
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
|
| 1359 |
|
|
|
| 1360 |
|
|
//---------- OOB & SATA Attributes -------------------------------------
|
| 1361 |
|
|
.TXOOB_CFG ( 1'd1), // GTH new, filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
|
| 1362 |
|
|
//.RXOOB_CFG ( 7'b0000110), //
|
| 1363 |
|
|
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), // GTH new
|
| 1364 |
|
|
//.SAS_MAX_COM (64), //
|
| 1365 |
|
|
//.SAS_MIN_COM (36), //
|
| 1366 |
|
|
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
|
| 1367 |
|
|
//.SATA_BURST_VAL ( 3'b100), //
|
| 1368 |
|
|
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
|
| 1369 |
|
|
//.SATA_EIDLE_VAL ( 3'b100), //
|
| 1370 |
|
|
//.SATA_MAX_BURST ( 8), //
|
| 1371 |
|
|
//.SATA_MAX_INIT (21), //
|
| 1372 |
|
|
//.SATA_MAX_WAKE ( 7), //
|
| 1373 |
|
|
//.SATA_MIN_BURST ( 4), //
|
| 1374 |
|
|
//.SATA_MIN_INIT (12), //
|
| 1375 |
|
|
//.SATA_MIN_WAKE ( 4), //
|
| 1376 |
|
|
|
| 1377 |
|
|
//---------- MISC ------------------------------------------------------
|
| 1378 |
|
|
.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 1011 = AGC
|
| 1379 |
|
|
//.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 0000 = CDR FSM
|
| 1380 |
|
|
.RX_DEBUG_CFG (14'b00000011000000), // Changed from 12 to 14-bits, optimized for IES
|
| 1381 |
|
|
//.TST_RSV (32'd0), //
|
| 1382 |
|
|
//.UCODEER_CLR ( 1'd0), //
|
| 1383 |
|
|
|
| 1384 |
|
|
//---------- GTH -------------------------------------------------------
|
| 1385 |
|
|
//.ACJTAG_DEBUG_MODE ( 1'd0), // GTH new
|
| 1386 |
|
|
//.ACJTAG_MODE ( 1'd0), // GTH new
|
| 1387 |
|
|
//.ACJTAG_RESET ( 1'd0), // GTH new
|
| 1388 |
|
|
.ADAPT_CFG0 (20'h00C10), // GTH new, optimized for IES
|
| 1389 |
|
|
.CFOK_CFG (42'h248_0004_0E80), // GTH new, optimized for IES, [8] : 1 = Skip CFOK
|
| 1390 |
|
|
.CFOK_CFG2 ( 6'b100000), // GTH new, optimized for IES
|
| 1391 |
|
|
.CFOK_CFG3 ( 6'b100000) // GTH new, optimized for IES
|
| 1392 |
|
|
|
| 1393 |
|
|
)
|
| 1394 |
|
|
gthe2_channel_i
|
| 1395 |
|
|
(
|
| 1396 |
|
|
|
| 1397 |
|
|
//---------- Clock -----------------------------------------------------
|
| 1398 |
|
|
.GTGREFCLK (1'd0), //
|
| 1399 |
|
|
.GTREFCLK0 (GT_GTREFCLK0), //
|
| 1400 |
|
|
.GTREFCLK1 (1'd0), //
|
| 1401 |
|
|
.GTNORTHREFCLK0 (1'd0), //
|
| 1402 |
|
|
.GTNORTHREFCLK1 (1'd0), //
|
| 1403 |
|
|
.GTSOUTHREFCLK0 (1'd0), //
|
| 1404 |
|
|
.GTSOUTHREFCLK1 (1'd0), //
|
| 1405 |
|
|
.QPLLCLK (GT_QPLLCLK), //
|
| 1406 |
|
|
.QPLLREFCLK (GT_QPLLREFCLK), //
|
| 1407 |
|
|
.TXUSRCLK (GT_TXUSRCLK), //
|
| 1408 |
|
|
.RXUSRCLK (GT_RXUSRCLK), //
|
| 1409 |
|
|
.TXUSRCLK2 (GT_TXUSRCLK2), //
|
| 1410 |
|
|
.RXUSRCLK2 (GT_RXUSRCLK2), //
|
| 1411 |
|
|
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
|
| 1412 |
|
|
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
|
| 1413 |
|
|
.TXOUTCLKSEL (txoutclksel), //
|
| 1414 |
|
|
.RXOUTCLKSEL (rxoutclksel), //
|
| 1415 |
|
|
.CPLLREFCLKSEL (3'd1), //
|
| 1416 |
|
|
.CPLLLOCKDETCLK (1'd0), //
|
| 1417 |
|
|
.CPLLLOCKEN (1'd1), //
|
| 1418 |
|
|
.CLKRSVD0 (1'd0), // GTH
|
| 1419 |
|
|
.CLKRSVD1 (1'd0), // GTH
|
| 1420 |
|
|
|
| 1421 |
|
|
.TXOUTCLK (GT_TXOUTCLK), //
|
| 1422 |
|
|
.RXOUTCLK (GT_RXOUTCLK), //
|
| 1423 |
|
|
.TXOUTCLKFABRIC (), //
|
| 1424 |
|
|
.RXOUTCLKFABRIC (), //
|
| 1425 |
|
|
.TXOUTCLKPCS (), //
|
| 1426 |
|
|
.RXOUTCLKPCS (), //
|
| 1427 |
|
|
.CPLLLOCK (GT_CPLLLOCK), //
|
| 1428 |
|
|
.CPLLREFCLKLOST (), //
|
| 1429 |
|
|
.CPLLFBCLKLOST (), //
|
| 1430 |
|
|
.RXCDRLOCK (GT_RXCDRLOCK), //
|
| 1431 |
|
|
.GTREFCLKMONITOR (), //
|
| 1432 |
|
|
|
| 1433 |
|
|
//---------- Reset -----------------------------------------------------
|
| 1434 |
|
|
.CPLLPD (GT_CPLLPD), //
|
| 1435 |
|
|
.CPLLRESET (GT_CPLLRESET), //
|
| 1436 |
|
|
.TXUSERRDY (GT_TXUSERRDY), //
|
| 1437 |
|
|
.RXUSERRDY (GT_RXUSERRDY), //
|
| 1438 |
|
|
.CFGRESET (1'd0), //
|
| 1439 |
|
|
.GTRESETSEL (1'd0), //
|
| 1440 |
|
|
.RESETOVRD (GT_RESETOVRD), //
|
| 1441 |
|
|
.GTTXRESET (GT_GTTXRESET), //
|
| 1442 |
|
|
.GTRXRESET (GT_GTRXRESET), //
|
| 1443 |
|
|
|
| 1444 |
|
|
.TXRESETDONE (GT_TXRESETDONE), //
|
| 1445 |
|
|
.RXRESETDONE (GT_RXRESETDONE), //
|
| 1446 |
|
|
|
| 1447 |
|
|
//---------- TX Data ---------------------------------------------------
|
| 1448 |
|
|
.TXDATA ({32'd0, GT_TXDATA}), //
|
| 1449 |
|
|
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
|
| 1450 |
|
|
|
| 1451 |
|
|
.GTHTXP (GT_TXP), // GTH
|
| 1452 |
|
|
.GTHTXN (GT_TXN), // GTH
|
| 1453 |
|
|
|
| 1454 |
|
|
//---------- RX Data ---------------------------------------------------
|
| 1455 |
|
|
.GTHRXP (GT_RXP), // GTH
|
| 1456 |
|
|
.GTHRXN (GT_RXN), // GTH
|
| 1457 |
|
|
|
| 1458 |
|
|
.RXDATA (rxdata), //
|
| 1459 |
|
|
.RXCHARISK (rxdatak), //
|
| 1460 |
|
|
|
| 1461 |
|
|
//---------- Command ---------------------------------------------------
|
| 1462 |
|
|
.TXDETECTRX (GT_TXDETECTRX), //
|
| 1463 |
|
|
.TXPDELECIDLEMODE ( 1'd0), //
|
| 1464 |
|
|
.RXELECIDLEMODE ( 2'd0), //
|
| 1465 |
|
|
.TXELECIDLE (GT_TXELECIDLE), //
|
| 1466 |
|
|
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
|
| 1467 |
|
|
.TXCHARDISPVAL ( 8'd0), //
|
| 1468 |
|
|
.TXPOLARITY ( 1'd0), //
|
| 1469 |
|
|
.RXPOLARITY (GT_RXPOLARITY), //
|
| 1470 |
|
|
.TXPD (GT_TXPOWERDOWN), //
|
| 1471 |
|
|
.RXPD (GT_RXPOWERDOWN), //
|
| 1472 |
|
|
.TXRATE (GT_TXRATE), //
|
| 1473 |
|
|
.RXRATE (GT_RXRATE), //
|
| 1474 |
|
|
.TXRATEMODE (1'd0), // GTH
|
| 1475 |
|
|
.RXRATEMODE (1'd0), // GTH
|
| 1476 |
|
|
|
| 1477 |
|
|
//---------- Electrical Command ----------------------------------------
|
| 1478 |
|
|
.TXMARGIN (GT_TXMARGIN), //
|
| 1479 |
|
|
.TXSWING (GT_TXSWING), //
|
| 1480 |
|
|
.TXDEEMPH (GT_TXDEEMPH), //
|
| 1481 |
|
|
.TXINHIBIT (1'd0), //
|
| 1482 |
|
|
.TXBUFDIFFCTRL (3'b100), //
|
| 1483 |
|
|
.TXDIFFCTRL (4'b1111), // Select 850mV
|
| 1484 |
|
|
.TXPRECURSOR (GT_TXPRECURSOR), //
|
| 1485 |
|
|
.TXPRECURSORINV (1'd0), //
|
| 1486 |
|
|
.TXMAINCURSOR (GT_TXMAINCURSOR), //
|
| 1487 |
|
|
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
|
| 1488 |
|
|
.TXPOSTCURSORINV (1'd0), //
|
| 1489 |
|
|
|
| 1490 |
|
|
//---------- Status ----------------------------------------------------
|
| 1491 |
|
|
.RXVALID (GT_RXVALID), //
|
| 1492 |
|
|
.PHYSTATUS (GT_PHYSTATUS), //
|
| 1493 |
|
|
.RXELECIDLE (GT_RXELECIDLE), //
|
| 1494 |
|
|
.RXSTATUS (GT_RXSTATUS), //
|
| 1495 |
|
|
.TXRATEDONE (GT_TXRATEDONE), //
|
| 1496 |
|
|
.RXRATEDONE (GT_RXRATEDONE), //
|
| 1497 |
|
|
|
| 1498 |
|
|
//---------- DRP -------------------------------------------------------
|
| 1499 |
|
|
.DRPCLK (GT_DRPCLK), //
|
| 1500 |
|
|
.DRPADDR (GT_DRPADDR), //
|
| 1501 |
|
|
.DRPEN (GT_DRPEN), //
|
| 1502 |
|
|
.DRPDI (GT_DRPDI), //
|
| 1503 |
|
|
.DRPWE (GT_DRPWE), //
|
| 1504 |
|
|
|
| 1505 |
|
|
.DRPDO (GT_DRPDO), //
|
| 1506 |
|
|
.DRPRDY (GT_DRPRDY), //
|
| 1507 |
|
|
|
| 1508 |
|
|
//---------- PMA -------------------------------------------------------
|
| 1509 |
|
|
.TXPMARESET (GT_TXPMARESET), //
|
| 1510 |
|
|
.RXPMARESET (GT_RXPMARESET), //
|
| 1511 |
|
|
.RXLPMEN (rxlpmen), // ***
|
| 1512 |
|
|
.RXLPMHFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
|
| 1513 |
|
|
.RXLPMHFOVRDEN ( 1'd0), //
|
| 1514 |
|
|
.RXLPMLFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
|
| 1515 |
|
|
.RXLPMLFKLOVRDEN ( 1'd0), //
|
| 1516 |
|
|
.TXQPIBIASEN ( 1'd0), //
|
| 1517 |
|
|
.TXQPISTRONGPDOWN ( 1'd0), //
|
| 1518 |
|
|
.TXQPIWEAKPUP ( 1'd0), //
|
| 1519 |
|
|
.RXQPIEN ( 1'd0), // Optimized for IES
|
| 1520 |
|
|
.PMARSVDIN ( 5'd0), //
|
| 1521 |
|
|
.GTRSVD (16'd0), //
|
| 1522 |
|
|
|
| 1523 |
|
|
.TXQPISENP (), //
|
| 1524 |
|
|
.TXQPISENN (), //
|
| 1525 |
|
|
.RXQPISENP (), //
|
| 1526 |
|
|
.RXQPISENN (), //
|
| 1527 |
|
|
.DMONITOROUT (dmonitorout), // GTH 15-bits.
|
| 1528 |
|
|
|
| 1529 |
|
|
//---------- PCS -------------------------------------------------------
|
| 1530 |
|
|
.TXPCSRESET (GT_TXPCSRESET), //
|
| 1531 |
|
|
.RXPCSRESET (GT_RXPCSRESET), //
|
| 1532 |
|
|
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
|
| 1533 |
|
|
.PCSRSVDIN2 ( 5'd0), //
|
| 1534 |
|
|
|
| 1535 |
|
|
.PCSRSVDOUT (), //
|
| 1536 |
|
|
|
| 1537 |
|
|
//---------- CDR -------------------------------------------------------
|
| 1538 |
|
|
.RXCDRRESET (GT_RXCDRRESET), //
|
| 1539 |
|
|
.RXCDRRESETRSV (1'd0), //
|
| 1540 |
|
|
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
|
| 1541 |
|
|
.RXCDRHOLD (1'd0), //
|
| 1542 |
|
|
.RXCDROVRDEN (1'd0), //
|
| 1543 |
|
|
|
| 1544 |
|
|
//---------- PI --------------------------------------------------------
|
| 1545 |
|
|
.TXPIPPMEN (1'd0), // GTH new
|
| 1546 |
|
|
.TXPIPPMOVRDEN (1'd0), // GTH new
|
| 1547 |
|
|
.TXPIPPMPD (1'd0), // GTH new
|
| 1548 |
|
|
.TXPIPPMSEL (1'd0), // GTH new
|
| 1549 |
|
|
.TXPIPPMSTEPSIZE (5'd0), // GTH new
|
| 1550 |
|
|
|
| 1551 |
|
|
//---------- DFE -------------------------------------------------------
|
| 1552 |
|
|
.RXDFELPMRESET (GT_RXDFELPMRESET), //
|
| 1553 |
|
|
.RXDFEAGCTRL (5'b10000), // GTH new, optimized for IES
|
| 1554 |
|
|
.RXDFECM1EN (1'd0), //
|
| 1555 |
|
|
.RXDFEVSEN (1'd0), //
|
| 1556 |
|
|
.RXDFETAP2HOLD (1'd0), //
|
| 1557 |
|
|
.RXDFETAP2OVRDEN (1'd0), //
|
| 1558 |
|
|
.RXDFETAP3HOLD (1'd0), //
|
| 1559 |
|
|
.RXDFETAP3OVRDEN (1'd0), //
|
| 1560 |
|
|
.RXDFETAP4HOLD (1'd0), //
|
| 1561 |
|
|
.RXDFETAP4OVRDEN (1'd0), //
|
| 1562 |
|
|
.RXDFETAP5HOLD (1'd0), //
|
| 1563 |
|
|
.RXDFETAP5OVRDEN (1'd0), //
|
| 1564 |
|
|
.RXDFETAP6HOLD (1'd0), // GTH new
|
| 1565 |
|
|
.RXDFETAP6OVRDEN (1'd0), // GTH new
|
| 1566 |
|
|
.RXDFETAP7HOLD (1'd0), // GTH new
|
| 1567 |
|
|
.RXDFETAP7OVRDEN (1'd0), // GTH new
|
| 1568 |
|
|
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
|
| 1569 |
|
|
.RXDFEAGCOVRDEN (rxlpmen), //
|
| 1570 |
|
|
.RXDFELFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
|
| 1571 |
|
|
.RXDFELFOVRDEN (1'd0), //
|
| 1572 |
|
|
.RXDFEUTHOLD (1'd0), //
|
| 1573 |
|
|
.RXDFEUTOVRDEN (1'd0), //
|
| 1574 |
|
|
.RXDFEVPHOLD (1'd0), //
|
| 1575 |
|
|
.RXDFEVPOVRDEN (1'd0), //
|
| 1576 |
|
|
.RXDFEXYDEN (1'd1), // Optimized for IES
|
| 1577 |
|
|
.RXMONITORSEL (2'd0), //
|
| 1578 |
|
|
.RXDFESLIDETAP (5'd0), // GTH new
|
| 1579 |
|
|
.RXDFESLIDETAPID (6'd0), // GTH new
|
| 1580 |
|
|
.RXDFESLIDETAPHOLD (1'd0), // GTH new
|
| 1581 |
|
|
.RXDFESLIDETAPOVRDEN (1'd0), // GTH new
|
| 1582 |
|
|
.RXDFESLIDETAPADAPTEN (1'd0), // GTH new
|
| 1583 |
|
|
.RXDFESLIDETAPINITOVRDEN (1'd0), // GTH new
|
| 1584 |
|
|
.RXDFESLIDETAPONLYADAPTEN (1'd0), // GTH new
|
| 1585 |
|
|
.RXDFESLIDETAPSTROBE (1'd0), // GTH new
|
| 1586 |
|
|
|
| 1587 |
|
|
.RXMONITOROUT (), //
|
| 1588 |
|
|
.RXDFESLIDETAPSTARTED (), // GTH new
|
| 1589 |
|
|
.RXDFESLIDETAPSTROBEDONE (), // GTH new
|
| 1590 |
|
|
.RXDFESLIDETAPSTROBESTARTED (), // GTH new
|
| 1591 |
|
|
.RXDFESTADAPTDONE (), // GTH new
|
| 1592 |
|
|
|
| 1593 |
|
|
//---------- OS --------------------------------------------------------
|
| 1594 |
|
|
.RXOSHOLD (1'd0), // optimized for IES
|
| 1595 |
|
|
.RXOSOVRDEN (1'd0), // optimized for IES
|
| 1596 |
|
|
.RXOSINTEN (1'd1), // GTH new, optimized for IES
|
| 1597 |
|
|
.RXOSINTHOLD (1'd0), // GTH new, optimized for IES
|
| 1598 |
|
|
.RXOSINTNTRLEN (1'd0), // GTH new, optimized for IES
|
| 1599 |
|
|
.RXOSINTOVRDEN (1'd0), // GTH new, optimized for IES
|
| 1600 |
|
|
.RXOSINTSTROBE (1'd0), // GTH new, optimized for IES
|
| 1601 |
|
|
.RXOSINTTESTOVRDEN (1'd0), // GTH new, optimized for IES
|
| 1602 |
|
|
.RXOSINTCFG (4'b0110), // GTH new, optimized for IES
|
| 1603 |
|
|
.RXOSINTID0 (4'b0000), // GTH new, optimized for IES
|
| 1604 |
|
|
.RXOSCALRESET ( 1'd0), // GTH, optimized for IES
|
| 1605 |
|
|
|
| 1606 |
|
|
.RSOSINTDONE (), // GTH new
|
| 1607 |
|
|
.RXOSINTSTARTED (), // GTH new
|
| 1608 |
|
|
.RXOSINTSTROBEDONE (), // GTH new
|
| 1609 |
|
|
.RXOSINTSTROBESTARTED (), // GTH new
|
| 1610 |
|
|
|
| 1611 |
|
|
//---------- Eye Scan --------------------------------------------------
|
| 1612 |
|
|
.EYESCANRESET (GT_EYESCANRESET), //
|
| 1613 |
|
|
.EYESCANMODE (1'd0), //
|
| 1614 |
|
|
.EYESCANTRIGGER (1'd0), //
|
| 1615 |
|
|
|
| 1616 |
|
|
.EYESCANDATAERROR (), //
|
| 1617 |
|
|
|
| 1618 |
|
|
//---------- TX Buffer -------------------------------------------------
|
| 1619 |
|
|
.TXBUFSTATUS (), //
|
| 1620 |
|
|
|
| 1621 |
|
|
//---------- RX Buffer -------------------------------------------------
|
| 1622 |
|
|
.RXBUFRESET (GT_RXBUFRESET), //
|
| 1623 |
|
|
|
| 1624 |
|
|
.RXBUFSTATUS (GT_RXBUFSTATUS), //
|
| 1625 |
|
|
|
| 1626 |
|
|
//---------- TX Sync ---------------------------------------------------
|
| 1627 |
|
|
.TXPHDLYRESET (GT_TXPHDLYRESET), //
|
| 1628 |
|
|
.TXPHDLYTSTCLK (1'd0), //
|
| 1629 |
|
|
.TXPHALIGN (GT_TXPHALIGN), //
|
| 1630 |
|
|
.TXPHALIGNEN (GT_TXPHALIGNEN), //
|
| 1631 |
|
|
.TXPHDLYPD (1'd0), //
|
| 1632 |
|
|
.TXPHINIT (GT_TXPHINIT), //
|
| 1633 |
|
|
.TXPHOVRDEN (1'd0), //
|
| 1634 |
|
|
.TXDLYBYPASS (GT_TXDLYBYPASS), //
|
| 1635 |
|
|
.TXDLYSRESET (GT_TXDLYSRESET), //
|
| 1636 |
|
|
.TXDLYEN (GT_TXDLYEN), //
|
| 1637 |
|
|
.TXDLYOVRDEN (1'd0), //
|
| 1638 |
|
|
.TXDLYHOLD (1'd0), //
|
| 1639 |
|
|
.TXDLYUPDOWN (1'd0), //
|
| 1640 |
|
|
|
| 1641 |
|
|
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
|
| 1642 |
|
|
.TXPHINITDONE (GT_TXPHINITDONE), //
|
| 1643 |
|
|
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
|
| 1644 |
|
|
|
| 1645 |
|
|
.TXSYNCMODE (GT_TXSYNCMODE), // GTH
|
| 1646 |
|
|
.TXSYNCIN (GT_TXSYNCIN), // GTH
|
| 1647 |
|
|
.TXSYNCALLIN (GT_TXSYNCALLIN), // GTH
|
| 1648 |
|
|
|
| 1649 |
|
|
.TXSYNCDONE (GT_TXSYNCDONE), // GTH
|
| 1650 |
|
|
.TXSYNCOUT (GT_TXSYNCOUT), // GTH
|
| 1651 |
|
|
|
| 1652 |
|
|
//---------- RX Sync ---------------------------------------------------
|
| 1653 |
|
|
.RXPHDLYRESET (1'd0), //
|
| 1654 |
|
|
.RXPHALIGN (GT_RXPHALIGN), //
|
| 1655 |
|
|
.RXPHALIGNEN (GT_RXPHALIGNEN), //
|
| 1656 |
|
|
.RXPHDLYPD (1'd0), //
|
| 1657 |
|
|
.RXPHOVRDEN (1'd0), //
|
| 1658 |
|
|
.RXDLYBYPASS (GT_RXDLYBYPASS), //
|
| 1659 |
|
|
.RXDLYSRESET (GT_RXDLYSRESET), //
|
| 1660 |
|
|
.RXDLYEN (GT_RXDLYEN), //
|
| 1661 |
|
|
.RXDLYOVRDEN (1'd0), //
|
| 1662 |
|
|
.RXDDIEN (GT_RXDDIEN), //
|
| 1663 |
|
|
|
| 1664 |
|
|
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
|
| 1665 |
|
|
.RXPHMONITOR (), //
|
| 1666 |
|
|
.RXPHSLIPMONITOR (), //
|
| 1667 |
|
|
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
|
| 1668 |
|
|
|
| 1669 |
|
|
.RXSYNCMODE (GT_RXSYNCMODE), // GTH
|
| 1670 |
|
|
.RXSYNCIN (GT_RXSYNCIN), // GTH
|
| 1671 |
|
|
.RXSYNCALLIN (GT_RXSYNCALLIN), // GTH
|
| 1672 |
|
|
|
| 1673 |
|
|
.RXSYNCDONE (GT_RXSYNCDONE), // GTH
|
| 1674 |
|
|
.RXSYNCOUT (GT_RXSYNCOUT), // GTH
|
| 1675 |
|
|
|
| 1676 |
|
|
//---------- Comma Alignment -------------------------------------------
|
| 1677 |
|
|
.RXCOMMADETEN ( 1'd1), //
|
| 1678 |
|
|
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
|
| 1679 |
|
|
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
|
| 1680 |
|
|
.RXSLIDE ( GT_RXSLIDE), //
|
| 1681 |
|
|
|
| 1682 |
|
|
.RXCOMMADET (GT_RXCOMMADET), //
|
| 1683 |
|
|
.RXCHARISCOMMA (rxchariscomma), //
|
| 1684 |
|
|
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
|
| 1685 |
|
|
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
|
| 1686 |
|
|
|
| 1687 |
|
|
//---------- Channel Bonding -------------------------------------------
|
| 1688 |
|
|
.RXCHBONDEN (GT_RXCHBONDEN), //
|
| 1689 |
|
|
.RXCHBONDI (GT_RXCHBONDI), //
|
| 1690 |
|
|
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
|
| 1691 |
|
|
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
|
| 1692 |
|
|
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
|
| 1693 |
|
|
|
| 1694 |
|
|
.RXCHANBONDSEQ (), //
|
| 1695 |
|
|
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
|
| 1696 |
|
|
.RXCHANREALIGN (), //
|
| 1697 |
|
|
.RXCHBONDO (GT_RXCHBONDO), //
|
| 1698 |
|
|
|
| 1699 |
|
|
//---------- Clock Correction -----------------------------------------
|
| 1700 |
|
|
.RXCLKCORCNT (), //
|
| 1701 |
|
|
|
| 1702 |
|
|
//---------- 8b10b -----------------------------------------------------
|
| 1703 |
|
|
.TX8B10BBYPASS (8'd0), //
|
| 1704 |
|
|
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
|
| 1705 |
|
|
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
|
| 1706 |
|
|
|
| 1707 |
|
|
.RXDISPERR (), //
|
| 1708 |
|
|
.RXNOTINTABLE (), //
|
| 1709 |
|
|
|
| 1710 |
|
|
//---------- 64b/66b & 64b/67b -----------------------------------------
|
| 1711 |
|
|
.TXHEADER (3'd0), //
|
| 1712 |
|
|
.TXSEQUENCE (7'd0), //
|
| 1713 |
|
|
.TXSTARTSEQ (1'd0), //
|
| 1714 |
|
|
.RXGEARBOXSLIP (1'd0), //
|
| 1715 |
|
|
|
| 1716 |
|
|
.TXGEARBOXREADY (), //
|
| 1717 |
|
|
.RXDATAVALID (), //
|
| 1718 |
|
|
.RXHEADER (), //
|
| 1719 |
|
|
.RXHEADERVALID (), //
|
| 1720 |
|
|
.RXSTARTOFSEQ (), //
|
| 1721 |
|
|
|
| 1722 |
|
|
//---------- PRBS & Loopback -------------------------------------------
|
| 1723 |
|
|
.TXPRBSSEL (GT_TXPRBSSEL), //
|
| 1724 |
|
|
.RXPRBSSEL (GT_RXPRBSSEL), //
|
| 1725 |
|
|
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
|
| 1726 |
|
|
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
|
| 1727 |
|
|
.LOOPBACK (GT_LOOPBACK), //
|
| 1728 |
|
|
|
| 1729 |
|
|
.RXPRBSERR (GT_RXPRBSERR), //
|
| 1730 |
|
|
|
| 1731 |
|
|
//---------- OOB -------------------------------------------------------
|
| 1732 |
|
|
.SIGVALIDCLK (GT_OOBCLK), // GTH, optimized for debug
|
| 1733 |
|
|
.TXCOMINIT (1'd0), //
|
| 1734 |
|
|
.TXCOMSAS (1'd0), //
|
| 1735 |
|
|
.TXCOMWAKE (1'd0), //
|
| 1736 |
|
|
.RXOOBRESET (1'd0), //
|
| 1737 |
|
|
|
| 1738 |
|
|
.TXCOMFINISH (), //
|
| 1739 |
|
|
.RXCOMINITDET (), //
|
| 1740 |
|
|
.RXCOMSASDET (), //
|
| 1741 |
|
|
.RXCOMWAKEDET (), //
|
| 1742 |
|
|
|
| 1743 |
|
|
//---------- MISC ------------------------------------------------------
|
| 1744 |
|
|
.SETERRSTATUS ( 1'd0), //
|
| 1745 |
|
|
.TXDIFFPD ( 1'd0), //
|
| 1746 |
|
|
.TXPISOPD ( 1'd0), //
|
| 1747 |
|
|
.TSTIN (20'hFFFFF), //
|
| 1748 |
|
|
|
| 1749 |
|
|
//---------- GTH -------------------------------------------------------
|
| 1750 |
|
|
.RXADAPTSELTEST (14'd0), // GTH new
|
| 1751 |
|
|
.DMONFIFORESET ( 1'd0), // GTH
|
| 1752 |
|
|
.DMONITORCLK (dmonitorclk), // GTH, optimized for debug
|
| 1753 |
|
|
//.DMONITORCLK (GT_DRPCLK), // GTH, optimized for debug
|
| 1754 |
|
|
|
| 1755 |
|
|
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTH
|
| 1756 |
|
|
.TXPMARESETDONE () // GTH
|
| 1757 |
|
|
|
| 1758 |
|
|
);
|
| 1759 |
|
|
|
| 1760 |
|
|
end
|
| 1761 |
|
|
|
| 1762 |
|
|
else
|
| 1763 |
|
|
|
| 1764 |
|
|
begin : gtx_channel
|
| 1765 |
|
|
|
| 1766 |
|
|
//---------- GTX Channel Module --------------------------------------------
|
| 1767 |
|
|
GTXE2_CHANNEL #
|
| 1768 |
|
|
(
|
| 1769 |
|
|
|
| 1770 |
|
|
//---------- Simulation Attributes -------------------------------------
|
| 1771 |
|
|
.SIM_CPLLREFCLK_SEL (3'b001), //
|
| 1772 |
|
|
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
|
| 1773 |
|
|
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
|
| 1774 |
|
|
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
|
| 1775 |
|
|
.SIM_VERSION (PCIE_USE_MODE), //
|
| 1776 |
|
|
|
| 1777 |
|
|
//---------- Clock Attributes ------------------------------------------
|
| 1778 |
|
|
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
|
| 1779 |
|
|
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
|
| 1780 |
|
|
.CPLL_FBDIV (CPLL_FBDIV), //
|
| 1781 |
|
|
.TXOUT_DIV (OUT_DIV), //
|
| 1782 |
|
|
.RXOUT_DIV (OUT_DIV), //
|
| 1783 |
|
|
.TX_CLK25_DIV (CLK25_DIV), //
|
| 1784 |
|
|
.RX_CLK25_DIV (CLK25_DIV), //
|
| 1785 |
|
|
.TX_CLKMUX_PD (CLKMUX_PD), // GTX
|
| 1786 |
|
|
.RX_CLKMUX_PD (CLKMUX_PD), // GTX
|
| 1787 |
|
|
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
|
| 1788 |
|
|
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
|
| 1789 |
|
|
.OUTREFCLK_SEL_INV ( 2'b11), //
|
| 1790 |
|
|
.CPLL_CFG (CPLL_CFG), // Optimized for silicon
|
| 1791 |
|
|
//.CPLL_INIT_CFG (24'h00001E), //
|
| 1792 |
|
|
//.CPLL_LOCK_CFG (16'h01E8), //
|
| 1793 |
|
|
|
| 1794 |
|
|
//---------- Reset Attributes ------------------------------------------
|
| 1795 |
|
|
.TXPCSRESET_TIME (5'b00001), //
|
| 1796 |
|
|
.RXPCSRESET_TIME (5'b00001), //
|
| 1797 |
|
|
.TXPMARESET_TIME (5'b00011), //
|
| 1798 |
|
|
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
|
| 1799 |
|
|
//.RXISCANRESET_TIME (5'b00001), //
|
| 1800 |
|
|
|
| 1801 |
|
|
//---------- TX Data Attributes ----------------------------------------
|
| 1802 |
|
|
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
|
| 1803 |
|
|
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
|
| 1804 |
|
|
|
| 1805 |
|
|
//---------- RX Data Attributes ----------------------------------------
|
| 1806 |
|
|
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
|
| 1807 |
|
|
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
|
| 1808 |
|
|
|
| 1809 |
|
|
//---------- Command Attributes ----------------------------------------
|
| 1810 |
|
|
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
|
| 1811 |
|
|
.TX_RXDETECT_REF (TX_RXDETECT_REF), //
|
| 1812 |
|
|
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
|
| 1813 |
|
|
.RX_CM_TRIM ( 3'b010), // Select 800mV
|
| 1814 |
|
|
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
|
| 1815 |
|
|
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
|
| 1816 |
|
|
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
|
| 1817 |
|
|
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
|
| 1818 |
|
|
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
|
| 1819 |
|
|
//.TRANS_TIME_RATE ( 8'h0E), //
|
| 1820 |
|
|
|
| 1821 |
|
|
//---------- Electrical Command Attributes -----------------------------
|
| 1822 |
|
|
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
|
| 1823 |
|
|
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
|
| 1824 |
|
|
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
|
| 1825 |
|
|
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
|
| 1826 |
|
|
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
|
| 1827 |
|
|
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
|
| 1828 |
|
|
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
|
| 1829 |
|
|
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
|
| 1830 |
|
|
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
|
| 1831 |
|
|
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
|
| 1832 |
|
|
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
|
| 1833 |
|
|
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
|
| 1834 |
|
|
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
|
| 1835 |
|
|
.TX_MAINCURSOR_SEL ( 1'b0), //
|
| 1836 |
|
|
.TX_PREDRIVER_MODE ( 1'b0), // GTX
|
| 1837 |
|
|
.TX_QPI_STATUS_EN ( 1'b0), //
|
| 1838 |
|
|
|
| 1839 |
|
|
//---------- Status Attributes -----------------------------------------
|
| 1840 |
|
|
.RX_SIG_VALID_DLY (4), // Optimized for sim
|
| 1841 |
|
|
|
| 1842 |
|
|
//---------- DRP Attributes --------------------------------------------
|
| 1843 |
|
|
|
| 1844 |
|
|
//---------- PCS Attributes --------------------------------------------
|
| 1845 |
|
|
.PCS_PCIE_EN ("TRUE"), // PCIe
|
| 1846 |
|
|
.PCS_RSVD_ATTR (PCS_RSVD_ATTR), //
|
| 1847 |
|
|
|
| 1848 |
|
|
//---------- PMA Attributes --------------------------------------------
|
| 1849 |
|
|
.PMA_RSV (32'h00018480), // Optimized for GES Gen1/Gen2
|
| 1850 |
|
|
.PMA_RSV2 (16'h2070), // Optimized for silicon, [4] RX_CM_TRIM[4], [5] = 1 Enable Eye Scan
|
| 1851 |
|
|
//.PMA_RSV3 ( 2'd0), //
|
| 1852 |
|
|
//.PMA_RSV4 (32'd0), // GTX 3.0 new
|
| 1853 |
|
|
.RX_BIAS_CFG (12'b000000000100), // Optimized for GES
|
| 1854 |
|
|
//.TERM_RCAL_CFG ( 5'b10000), //
|
| 1855 |
|
|
//.TERM_RCAL_OVRD ( 1'd0), //
|
| 1856 |
|
|
|
| 1857 |
|
|
//---------- CDR Attributes --------------------------------------------
|
| 1858 |
|
|
.RXCDR_CFG (RXCDR_CFG_GTX), //
|
| 1859 |
|
|
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
|
| 1860 |
|
|
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
|
| 1861 |
|
|
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
|
| 1862 |
|
|
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
|
| 1863 |
|
|
//.RXCDRFREQRESET_TIME ( 5'b00001), //
|
| 1864 |
|
|
//.RXCDRPHRESET_TIME ( 5'b00001), //
|
| 1865 |
|
|
|
| 1866 |
|
|
//---------- LPM Attributes --------------------------------------------
|
| 1867 |
|
|
.RXLPM_HF_CFG (14'h00F0), // Optimized for silicon
|
| 1868 |
|
|
.RXLPM_LF_CFG (14'h00F0), // Optimized for silicon
|
| 1869 |
|
|
|
| 1870 |
|
|
//---------- DFE Attributes --------------------------------------------
|
| 1871 |
|
|
//.RXDFELPMRESET_TIME ( 7'b0001111), //
|
| 1872 |
|
|
.RX_DFE_GAIN_CFG (23'h020FEA), // Optimized for GES, IES = 23'h001F0A
|
| 1873 |
|
|
.RX_DFE_H2_CFG (12'b000000000000), // Optimized for GES
|
| 1874 |
|
|
.RX_DFE_H3_CFG (12'b000001000000), // Optimized for GES
|
| 1875 |
|
|
.RX_DFE_H4_CFG (11'b00011110000), // Optimized for GES
|
| 1876 |
|
|
.RX_DFE_H5_CFG (11'b00011100000), // Optimized for GES
|
| 1877 |
|
|
.RX_DFE_KL_CFG (13'b0000011111110), // Optimized for GES
|
| 1878 |
|
|
.RX_DFE_KL_CFG2 (32'h3290D86C), // Optimized for GES, GTX new, CTLE 3 3 5, default = 32'h3010D90C
|
| 1879 |
|
|
.RX_DFE_LPM_CFG (16'h0954), // Optimized for GES
|
| 1880 |
|
|
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'd1), // Optimized for PCIe
|
| 1881 |
|
|
.RX_DFE_UT_CFG (17'b10001111000000000), // Optimized for GES, IES = 17'h08F00
|
| 1882 |
|
|
.RX_DFE_VP_CFG (17'b00011111100000011), // Optimized for GES
|
| 1883 |
|
|
.RX_DFE_XYD_CFG (13'h0000), // Optimized for 4.0
|
| 1884 |
|
|
|
| 1885 |
|
|
//---------- OS Attributes ---------------------------------------------
|
| 1886 |
|
|
.RX_OS_CFG (13'b0000010000000), // Optimized for GES
|
| 1887 |
|
|
|
| 1888 |
|
|
//---------- Eye Scan Attributes ---------------------------------------
|
| 1889 |
|
|
//.ES_CONTROL ( 6'd0), //
|
| 1890 |
|
|
//.ES_ERRDET_EN ("FALSE"), //
|
| 1891 |
|
|
.ES_EYE_SCAN_EN ("TRUE"), //
|
| 1892 |
|
|
.ES_HORZ_OFFSET (12'd0), //
|
| 1893 |
|
|
//.ES_PMA_CFG (10'd0), //
|
| 1894 |
|
|
//.ES_PRESCALE ( 5'd0), //
|
| 1895 |
|
|
//.ES_QUAL_MASK (80'd0), //
|
| 1896 |
|
|
//.ES_QUALIFIER (80'd0), //
|
| 1897 |
|
|
//.ES_SDATA_MASK (80'd0), //
|
| 1898 |
|
|
//.ES_VERT_OFFSET ( 9'd0), //
|
| 1899 |
|
|
|
| 1900 |
|
|
//---------- TX Buffer Attributes --------------------------------------
|
| 1901 |
|
|
.TXBUF_EN (PCIE_TXBUF_EN), //
|
| 1902 |
|
|
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
|
| 1903 |
|
|
|
| 1904 |
|
|
//---------- RX Buffer Attributes --------------------------------------
|
| 1905 |
|
|
.RXBUF_EN ("TRUE"), //
|
| 1906 |
|
|
//.RX_BUFFER_CFG ( 6'd0), //
|
| 1907 |
|
|
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
|
| 1908 |
|
|
.RXBUF_ADDR_MODE ("FULL"), //
|
| 1909 |
|
|
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
|
| 1910 |
|
|
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
|
| 1911 |
|
|
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
|
| 1912 |
|
|
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
|
| 1913 |
|
|
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
|
| 1914 |
|
|
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
|
| 1915 |
|
|
.RXBUF_THRESH_OVRD ("FALSE"), //
|
| 1916 |
|
|
.RXBUF_THRESH_OVFLW (61), //
|
| 1917 |
|
|
.RXBUF_THRESH_UNDFLW ( 4), //
|
| 1918 |
|
|
//.RXBUFRESET_TIME ( 5'b00001), //
|
| 1919 |
|
|
|
| 1920 |
|
|
//---------- TX Sync Attributes ----------------------------------------
|
| 1921 |
|
|
//.TXPH_CFG (16'h0780), //
|
| 1922 |
|
|
.TXPH_MONITOR_SEL ( 5'd0), //
|
| 1923 |
|
|
//.TXPHDLY_CFG (24'h084020), //
|
| 1924 |
|
|
//.TXDLY_CFG (16'h001F), //
|
| 1925 |
|
|
//.TXDLY_LCFG ( 9'h030), //
|
| 1926 |
|
|
//.TXDLY_TAP_CFG (16'd0), //
|
| 1927 |
|
|
|
| 1928 |
|
|
//---------- RX Sync Attributes ----------------------------------------
|
| 1929 |
|
|
//.RXPH_CFG (24'd0), //
|
| 1930 |
|
|
.RXPH_MONITOR_SEL ( 5'd0), //
|
| 1931 |
|
|
.RXPHDLY_CFG (24'h004020), // Optimized for sim
|
| 1932 |
|
|
//.RXDLY_CFG (16'h001F), //
|
| 1933 |
|
|
//.RXDLY_LCFG ( 9'h030), //
|
| 1934 |
|
|
//.RXDLY_TAP_CFG (16'd0), //
|
| 1935 |
|
|
.RX_DDI_SEL ( 6'd0), //
|
| 1936 |
|
|
|
| 1937 |
|
|
//---------- Comma Alignment Attributes --------------------------------
|
| 1938 |
|
|
.ALIGN_COMMA_DOUBLE ("FALSE"), //
|
| 1939 |
|
|
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
|
| 1940 |
|
|
.ALIGN_COMMA_WORD ( 1), //
|
| 1941 |
|
|
.ALIGN_MCOMMA_DET ("TRUE"), //
|
| 1942 |
|
|
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
|
| 1943 |
|
|
.ALIGN_PCOMMA_DET ("TRUE"), //
|
| 1944 |
|
|
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
|
| 1945 |
|
|
.DEC_MCOMMA_DETECT ("TRUE"), //
|
| 1946 |
|
|
.DEC_PCOMMA_DETECT ("TRUE"), //
|
| 1947 |
|
|
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
|
| 1948 |
|
|
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
|
| 1949 |
|
|
.RXSLIDE_AUTO_WAIT ( 7), //
|
| 1950 |
|
|
.RXSLIDE_MODE ("PMA"), // PCIe
|
| 1951 |
|
|
|
| 1952 |
|
|
//---------- Channel Bonding Attributes --------------------------------
|
| 1953 |
|
|
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
|
| 1954 |
|
|
.CHAN_BOND_MAX_SKEW ( 7), //
|
| 1955 |
|
|
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
|
| 1956 |
|
|
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
|
| 1957 |
|
|
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
|
| 1958 |
|
|
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
|
| 1959 |
|
|
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
|
| 1960 |
|
|
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
|
| 1961 |
|
|
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
|
| 1962 |
|
|
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
|
| 1963 |
|
|
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
|
| 1964 |
|
|
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
|
| 1965 |
|
|
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
|
| 1966 |
|
|
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
|
| 1967 |
|
|
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
|
| 1968 |
|
|
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
|
| 1969 |
|
|
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
|
| 1970 |
|
|
|
| 1971 |
|
|
//---------- Clock Correction Attributes -------------------------------
|
| 1972 |
|
|
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
|
| 1973 |
|
|
.CLK_CORRECT_USE ("TRUE"), //
|
| 1974 |
|
|
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
|
| 1975 |
|
|
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
|
| 1976 |
|
|
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
|
| 1977 |
|
|
.CLK_COR_PRECEDENCE ("TRUE"), //
|
| 1978 |
|
|
.CLK_COR_REPEAT_WAIT ( 0), //
|
| 1979 |
|
|
.CLK_COR_SEQ_LEN ( 1), //
|
| 1980 |
|
|
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
|
| 1981 |
|
|
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
|
| 1982 |
|
|
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
|
| 1983 |
|
|
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
|
| 1984 |
|
|
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
|
| 1985 |
|
|
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
|
| 1986 |
|
|
.CLK_COR_SEQ_2_USE ("FALSE"), //
|
| 1987 |
|
|
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
|
| 1988 |
|
|
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
|
| 1989 |
|
|
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
|
| 1990 |
|
|
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
|
| 1991 |
|
|
|
| 1992 |
|
|
//---------- 8b10b Attributes ------------------------------------------
|
| 1993 |
|
|
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
|
| 1994 |
|
|
|
| 1995 |
|
|
//---------- 64b/66b & 64b/67b Attributes ------------------------------
|
| 1996 |
|
|
.GEARBOX_MODE (3'd0), //
|
| 1997 |
|
|
.TXGEARBOX_EN ("FALSE"), //
|
| 1998 |
|
|
.RXGEARBOX_EN ("FALSE"), //
|
| 1999 |
|
|
|
| 2000 |
|
|
//---------- PRBS & Loopback Attributes --------------------------------
|
| 2001 |
|
|
.RXPRBS_ERR_LOOPBACK (1'd0), //
|
| 2002 |
|
|
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
|
| 2003 |
|
|
|
| 2004 |
|
|
//---------- OOB & SATA Attributes -------------------------------------
|
| 2005 |
|
|
//.RXOOB_CFG ( 7'b0000110), //
|
| 2006 |
|
|
//.SAS_MAX_COM (64), //
|
| 2007 |
|
|
//.SAS_MIN_COM (36), //
|
| 2008 |
|
|
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
|
| 2009 |
|
|
//.SATA_BURST_VAL ( 3'b100), //
|
| 2010 |
|
|
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
|
| 2011 |
|
|
//.SATA_EIDLE_VAL ( 3'b100), //
|
| 2012 |
|
|
//.SATA_MAX_BURST ( 8), //
|
| 2013 |
|
|
//.SATA_MAX_INIT (21), //
|
| 2014 |
|
|
//.SATA_MAX_WAKE ( 7), //
|
| 2015 |
|
|
//.SATA_MIN_BURST ( 4), //
|
| 2016 |
|
|
//.SATA_MIN_INIT (12), //
|
| 2017 |
|
|
//.SATA_MIN_WAKE ( 4), //
|
| 2018 |
|
|
|
| 2019 |
|
|
//---------- MISC ------------------------------------------------------
|
| 2020 |
|
|
.DMONITOR_CFG (24'h000B01), // Optimized for debug
|
| 2021 |
|
|
.RX_DEBUG_CFG (12'd0) // Optimized for GES
|
| 2022 |
|
|
//.TST_RSV (32'd0), //
|
| 2023 |
|
|
//.UCODEER_CLR ( 1'd0) //
|
| 2024 |
|
|
|
| 2025 |
|
|
)
|
| 2026 |
|
|
gtxe2_channel_i
|
| 2027 |
|
|
(
|
| 2028 |
|
|
|
| 2029 |
|
|
//---------- Clock -----------------------------------------------------
|
| 2030 |
|
|
.GTGREFCLK (1'd0), //
|
| 2031 |
|
|
.GTREFCLK0 (GT_GTREFCLK0), //
|
| 2032 |
|
|
.GTREFCLK1 (1'd0), //
|
| 2033 |
|
|
.GTNORTHREFCLK0 (1'd0), //
|
| 2034 |
|
|
.GTNORTHREFCLK1 (1'd0), //
|
| 2035 |
|
|
.GTSOUTHREFCLK0 (1'd0), //
|
| 2036 |
|
|
.GTSOUTHREFCLK1 (1'd0), //
|
| 2037 |
|
|
.QPLLCLK (GT_QPLLCLK), //
|
| 2038 |
|
|
.QPLLREFCLK (GT_QPLLREFCLK), //
|
| 2039 |
|
|
.TXUSRCLK (GT_TXUSRCLK), //
|
| 2040 |
|
|
.RXUSRCLK (GT_RXUSRCLK), //
|
| 2041 |
|
|
.TXUSRCLK2 (GT_TXUSRCLK2), //
|
| 2042 |
|
|
.RXUSRCLK2 (GT_RXUSRCLK2), //
|
| 2043 |
|
|
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
|
| 2044 |
|
|
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
|
| 2045 |
|
|
.TXOUTCLKSEL (txoutclksel), //
|
| 2046 |
|
|
.RXOUTCLKSEL (rxoutclksel), //
|
| 2047 |
|
|
.CPLLREFCLKSEL (3'd1), //
|
| 2048 |
|
|
.CPLLLOCKDETCLK (1'd0), //
|
| 2049 |
|
|
.CPLLLOCKEN (1'd1), //
|
| 2050 |
|
|
.CLKRSVD ({2'd0, dmonitorclk, GT_OOBCLK}), // Optimized for debug
|
| 2051 |
|
|
|
| 2052 |
|
|
.TXOUTCLK (GT_TXOUTCLK), //
|
| 2053 |
|
|
.RXOUTCLK (GT_RXOUTCLK), //
|
| 2054 |
|
|
.TXOUTCLKFABRIC (), //
|
| 2055 |
|
|
.RXOUTCLKFABRIC (), //
|
| 2056 |
|
|
.TXOUTCLKPCS (), //
|
| 2057 |
|
|
.RXOUTCLKPCS (), //
|
| 2058 |
|
|
.CPLLLOCK (GT_CPLLLOCK), //
|
| 2059 |
|
|
.CPLLREFCLKLOST (), //
|
| 2060 |
|
|
.CPLLFBCLKLOST (), //
|
| 2061 |
|
|
.RXCDRLOCK (GT_RXCDRLOCK), //
|
| 2062 |
|
|
.GTREFCLKMONITOR (), //
|
| 2063 |
|
|
|
| 2064 |
|
|
//---------- Reset -----------------------------------------------------
|
| 2065 |
|
|
.CPLLPD (GT_CPLLPD), //
|
| 2066 |
|
|
.CPLLRESET (GT_CPLLRESET), //
|
| 2067 |
|
|
.TXUSERRDY (GT_TXUSERRDY), //
|
| 2068 |
|
|
.RXUSERRDY (GT_RXUSERRDY), //
|
| 2069 |
|
|
.CFGRESET (1'd0), //
|
| 2070 |
|
|
.GTRESETSEL (1'd0), //
|
| 2071 |
|
|
.RESETOVRD (GT_RESETOVRD), //
|
| 2072 |
|
|
.GTTXRESET (GT_GTTXRESET), //
|
| 2073 |
|
|
.GTRXRESET (GT_GTRXRESET), //
|
| 2074 |
|
|
|
| 2075 |
|
|
.TXRESETDONE (GT_TXRESETDONE), //
|
| 2076 |
|
|
.RXRESETDONE (GT_RXRESETDONE), //
|
| 2077 |
|
|
|
| 2078 |
|
|
//---------- TX Data ---------------------------------------------------
|
| 2079 |
|
|
.TXDATA ({32'd0, GT_TXDATA}), //
|
| 2080 |
|
|
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
|
| 2081 |
|
|
|
| 2082 |
|
|
.GTXTXP (GT_TXP), // GTX
|
| 2083 |
|
|
.GTXTXN (GT_TXN), // GTX
|
| 2084 |
|
|
|
| 2085 |
|
|
//---------- RX Data ---------------------------------------------------
|
| 2086 |
|
|
.GTXRXP (GT_RXP), // GTX
|
| 2087 |
|
|
.GTXRXN (GT_RXN), // GTX
|
| 2088 |
|
|
|
| 2089 |
|
|
.RXDATA (rxdata), //
|
| 2090 |
|
|
.RXCHARISK (rxdatak), //
|
| 2091 |
|
|
|
| 2092 |
|
|
//---------- Command ---------------------------------------------------
|
| 2093 |
|
|
.TXDETECTRX (GT_TXDETECTRX), //
|
| 2094 |
|
|
.TXPDELECIDLEMODE ( 1'd0), //
|
| 2095 |
|
|
.RXELECIDLEMODE ( 2'd0), //
|
| 2096 |
|
|
.TXELECIDLE (GT_TXELECIDLE), //
|
| 2097 |
|
|
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
|
| 2098 |
|
|
.TXCHARDISPVAL ( 8'd0), //
|
| 2099 |
|
|
.TXPOLARITY ( 1'd0), //
|
| 2100 |
|
|
.RXPOLARITY (GT_RXPOLARITY), //
|
| 2101 |
|
|
.TXPD (GT_TXPOWERDOWN), //
|
| 2102 |
|
|
.RXPD (GT_RXPOWERDOWN), //
|
| 2103 |
|
|
.TXRATE (GT_TXRATE), //
|
| 2104 |
|
|
.RXRATE (GT_RXRATE), //
|
| 2105 |
|
|
|
| 2106 |
|
|
//---------- Electrical Command ----------------------------------------
|
| 2107 |
|
|
.TXMARGIN (GT_TXMARGIN), //
|
| 2108 |
|
|
.TXSWING (GT_TXSWING), //
|
| 2109 |
|
|
.TXDEEMPH (GT_TXDEEMPH), //
|
| 2110 |
|
|
.TXINHIBIT (1'd0), //
|
| 2111 |
|
|
.TXBUFDIFFCTRL (3'b100), //
|
| 2112 |
|
|
.TXDIFFCTRL (4'b1100), //
|
| 2113 |
|
|
.TXPRECURSOR (GT_TXPRECURSOR), //
|
| 2114 |
|
|
.TXPRECURSORINV (1'd0), //
|
| 2115 |
|
|
.TXMAINCURSOR (GT_TXMAINCURSOR), //
|
| 2116 |
|
|
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
|
| 2117 |
|
|
.TXPOSTCURSORINV (1'd0), //
|
| 2118 |
|
|
|
| 2119 |
|
|
//---------- Status ----------------------------------------------------
|
| 2120 |
|
|
.RXVALID (GT_RXVALID), //
|
| 2121 |
|
|
.PHYSTATUS (GT_PHYSTATUS), //
|
| 2122 |
|
|
.RXELECIDLE (GT_RXELECIDLE), //
|
| 2123 |
|
|
.RXSTATUS (GT_RXSTATUS), //
|
| 2124 |
|
|
.TXRATEDONE (GT_TXRATEDONE), //
|
| 2125 |
|
|
.RXRATEDONE (GT_RXRATEDONE), //
|
| 2126 |
|
|
|
| 2127 |
|
|
//---------- DRP -------------------------------------------------------
|
| 2128 |
|
|
.DRPCLK (GT_DRPCLK), //
|
| 2129 |
|
|
.DRPADDR (GT_DRPADDR), //
|
| 2130 |
|
|
.DRPEN (GT_DRPEN), //
|
| 2131 |
|
|
.DRPDI (GT_DRPDI), //
|
| 2132 |
|
|
.DRPWE (GT_DRPWE), //
|
| 2133 |
|
|
|
| 2134 |
|
|
.DRPDO (GT_DRPDO), //
|
| 2135 |
|
|
.DRPRDY (GT_DRPRDY), //
|
| 2136 |
|
|
|
| 2137 |
|
|
//---------- PMA -------------------------------------------------------
|
| 2138 |
|
|
.TXPMARESET (GT_TXPMARESET), //
|
| 2139 |
|
|
.RXPMARESET (GT_RXPMARESET), //
|
| 2140 |
|
|
.RXLPMEN (rxlpmen), //
|
| 2141 |
|
|
.RXLPMHFHOLD ( 1'd0), //
|
| 2142 |
|
|
.RXLPMHFOVRDEN ( 1'd0), //
|
| 2143 |
|
|
.RXLPMLFHOLD ( 1'd0), //
|
| 2144 |
|
|
.RXLPMLFKLOVRDEN ( 1'd0), //
|
| 2145 |
|
|
.TXQPIBIASEN ( 1'd0), //
|
| 2146 |
|
|
.TXQPISTRONGPDOWN ( 1'd0), //
|
| 2147 |
|
|
.TXQPIWEAKPUP ( 1'd0), //
|
| 2148 |
|
|
.RXQPIEN ( 1'd0), //
|
| 2149 |
|
|
.PMARSVDIN ( 5'd0), //
|
| 2150 |
|
|
.PMARSVDIN2 ( 5'd0), // GTX
|
| 2151 |
|
|
.GTRSVD (16'd0), //
|
| 2152 |
|
|
|
| 2153 |
|
|
.TXQPISENP (), //
|
| 2154 |
|
|
.TXQPISENN (), //
|
| 2155 |
|
|
.RXQPISENP (), //
|
| 2156 |
|
|
.RXQPISENN (), //
|
| 2157 |
|
|
.DMONITOROUT (dmonitorout[7:0]), // GTX 8-bits
|
| 2158 |
|
|
|
| 2159 |
|
|
//---------- PCS -------------------------------------------------------
|
| 2160 |
|
|
.TXPCSRESET (GT_TXPCSRESET), //
|
| 2161 |
|
|
.RXPCSRESET (GT_RXPCSRESET), //
|
| 2162 |
|
|
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
|
| 2163 |
|
|
.PCSRSVDIN2 ( 5'd0), //
|
| 2164 |
|
|
|
| 2165 |
|
|
.PCSRSVDOUT (), //
|
| 2166 |
|
|
//---------- CDR -------------------------------------------------------
|
| 2167 |
|
|
.RXCDRRESET (GT_RXCDRRESET), //
|
| 2168 |
|
|
.RXCDRRESETRSV (1'd0), //
|
| 2169 |
|
|
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
|
| 2170 |
|
|
.RXCDRHOLD (1'd0), //
|
| 2171 |
|
|
.RXCDROVRDEN (1'd0), //
|
| 2172 |
|
|
|
| 2173 |
|
|
//---------- DFE -------------------------------------------------------
|
| 2174 |
|
|
.RXDFELPMRESET (GT_RXDFELPMRESET), //
|
| 2175 |
|
|
.RXDFECM1EN (1'd0), //
|
| 2176 |
|
|
.RXDFEVSEN (1'd0), //
|
| 2177 |
|
|
.RXDFETAP2HOLD (1'd0), //
|
| 2178 |
|
|
.RXDFETAP2OVRDEN (1'd0), //
|
| 2179 |
|
|
.RXDFETAP3HOLD (1'd0), //
|
| 2180 |
|
|
.RXDFETAP3OVRDEN (1'd0), //
|
| 2181 |
|
|
.RXDFETAP4HOLD (1'd0), //
|
| 2182 |
|
|
.RXDFETAP4OVRDEN (1'd0), //
|
| 2183 |
|
|
.RXDFETAP5HOLD (1'd0), //
|
| 2184 |
|
|
.RXDFETAP5OVRDEN (1'd0), //
|
| 2185 |
|
|
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Optimized for GES, Set to 1 after convergence
|
| 2186 |
|
|
.RXDFEAGCOVRDEN (1'd0), //
|
| 2187 |
|
|
.RXDFELFHOLD (1'd0), //
|
| 2188 |
|
|
.RXDFELFOVRDEN (1'd1), // Optimized for GES
|
| 2189 |
|
|
.RXDFEUTHOLD (1'd0), //
|
| 2190 |
|
|
.RXDFEUTOVRDEN (1'd0), //
|
| 2191 |
|
|
.RXDFEVPHOLD (1'd0), //
|
| 2192 |
|
|
.RXDFEVPOVRDEN (1'd0), //
|
| 2193 |
|
|
.RXDFEXYDEN (1'd0), //
|
| 2194 |
|
|
.RXDFEXYDHOLD (1'd0), // GTX
|
| 2195 |
|
|
.RXDFEXYDOVRDEN (1'd0), // GTX
|
| 2196 |
|
|
.RXMONITORSEL (2'd0), //
|
| 2197 |
|
|
|
| 2198 |
|
|
.RXMONITOROUT (), //
|
| 2199 |
|
|
|
| 2200 |
|
|
//---------- OS --------------------------------------------------------
|
| 2201 |
|
|
.RXOSHOLD (1'd0), //
|
| 2202 |
|
|
.RXOSOVRDEN (1'd0), //
|
| 2203 |
|
|
|
| 2204 |
|
|
//---------- Eye Scan --------------------------------------------------
|
| 2205 |
|
|
.EYESCANRESET (GT_EYESCANRESET), //
|
| 2206 |
|
|
.EYESCANMODE (1'd0), //
|
| 2207 |
|
|
.EYESCANTRIGGER (1'd0), //
|
| 2208 |
|
|
|
| 2209 |
|
|
.EYESCANDATAERROR (), //
|
| 2210 |
|
|
|
| 2211 |
|
|
//---------- TX Buffer -------------------------------------------------
|
| 2212 |
|
|
.TXBUFSTATUS (), //
|
| 2213 |
|
|
|
| 2214 |
|
|
//---------- RX Buffer -------------------------------------------------
|
| 2215 |
|
|
.RXBUFRESET (GT_RXBUFRESET), //
|
| 2216 |
|
|
|
| 2217 |
|
|
.RXBUFSTATUS (GT_RXBUFSTATUS), //
|
| 2218 |
|
|
|
| 2219 |
|
|
//---------- TX Sync ---------------------------------------------------
|
| 2220 |
|
|
.TXPHDLYRESET (1'd0), //
|
| 2221 |
|
|
.TXPHDLYTSTCLK (1'd0), //
|
| 2222 |
|
|
.TXPHALIGN (GT_TXPHALIGN), //
|
| 2223 |
|
|
.TXPHALIGNEN (GT_TXPHALIGNEN), //
|
| 2224 |
|
|
.TXPHDLYPD (1'd0), //
|
| 2225 |
|
|
.TXPHINIT (GT_TXPHINIT), //
|
| 2226 |
|
|
.TXPHOVRDEN (1'd0), //
|
| 2227 |
|
|
.TXDLYBYPASS (GT_TXDLYBYPASS), //
|
| 2228 |
|
|
.TXDLYSRESET (GT_TXDLYSRESET), //
|
| 2229 |
|
|
.TXDLYEN (GT_TXDLYEN), //
|
| 2230 |
|
|
.TXDLYOVRDEN (1'd0), //
|
| 2231 |
|
|
.TXDLYHOLD (1'd0), //
|
| 2232 |
|
|
.TXDLYUPDOWN (1'd0), //
|
| 2233 |
|
|
|
| 2234 |
|
|
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
|
| 2235 |
|
|
.TXPHINITDONE (GT_TXPHINITDONE), //
|
| 2236 |
|
|
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
|
| 2237 |
|
|
|
| 2238 |
|
|
//---------- RX Sync ---------------------------------------------------
|
| 2239 |
|
|
.RXPHDLYRESET (1'd0), //
|
| 2240 |
|
|
.RXPHALIGN (GT_RXPHALIGN), //
|
| 2241 |
|
|
.RXPHALIGNEN (GT_RXPHALIGNEN), //
|
| 2242 |
|
|
.RXPHDLYPD (1'd0), //
|
| 2243 |
|
|
.RXPHOVRDEN (1'd0), //
|
| 2244 |
|
|
.RXDLYBYPASS (GT_RXDLYBYPASS), //
|
| 2245 |
|
|
.RXDLYSRESET (GT_RXDLYSRESET), //
|
| 2246 |
|
|
.RXDLYEN (GT_RXDLYEN), //
|
| 2247 |
|
|
.RXDLYOVRDEN (1'd0), //
|
| 2248 |
|
|
.RXDDIEN (GT_RXDDIEN), //
|
| 2249 |
|
|
|
| 2250 |
|
|
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
|
| 2251 |
|
|
.RXPHMONITOR (), //
|
| 2252 |
|
|
.RXPHSLIPMONITOR (), //
|
| 2253 |
|
|
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
|
| 2254 |
|
|
|
| 2255 |
|
|
//---------- Comma Alignment -------------------------------------------
|
| 2256 |
|
|
.RXCOMMADETEN ( 1'd1), //
|
| 2257 |
|
|
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
|
| 2258 |
|
|
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
|
| 2259 |
|
|
.RXSLIDE ( GT_RXSLIDE), //
|
| 2260 |
|
|
|
| 2261 |
|
|
.RXCOMMADET (GT_RXCOMMADET), //
|
| 2262 |
|
|
.RXCHARISCOMMA (rxchariscomma), //
|
| 2263 |
|
|
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
|
| 2264 |
|
|
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
|
| 2265 |
|
|
|
| 2266 |
|
|
//---------- Channel Bonding -------------------------------------------
|
| 2267 |
|
|
.RXCHBONDEN (GT_RXCHBONDEN), //
|
| 2268 |
|
|
.RXCHBONDI (GT_RXCHBONDI), //
|
| 2269 |
|
|
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
|
| 2270 |
|
|
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
|
| 2271 |
|
|
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
|
| 2272 |
|
|
|
| 2273 |
|
|
.RXCHANBONDSEQ (), //
|
| 2274 |
|
|
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
|
| 2275 |
|
|
.RXCHANREALIGN (), //
|
| 2276 |
|
|
.RXCHBONDO (GT_RXCHBONDO), //
|
| 2277 |
|
|
|
| 2278 |
|
|
//---------- Clock Correction -----------------------------------------
|
| 2279 |
|
|
.RXCLKCORCNT (), //
|
| 2280 |
|
|
|
| 2281 |
|
|
//---------- 8b10b -----------------------------------------------------
|
| 2282 |
|
|
.TX8B10BBYPASS (8'd0), //
|
| 2283 |
|
|
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
|
| 2284 |
|
|
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
|
| 2285 |
|
|
|
| 2286 |
|
|
.RXDISPERR (), //
|
| 2287 |
|
|
.RXNOTINTABLE (), //
|
| 2288 |
|
|
|
| 2289 |
|
|
//---------- 64b/66b & 64b/67b -----------------------------------------
|
| 2290 |
|
|
.TXHEADER (3'd0), //
|
| 2291 |
|
|
.TXSEQUENCE (7'd0), //
|
| 2292 |
|
|
.TXSTARTSEQ (1'd0), //
|
| 2293 |
|
|
.RXGEARBOXSLIP (1'd0), //
|
| 2294 |
|
|
|
| 2295 |
|
|
.TXGEARBOXREADY (), //
|
| 2296 |
|
|
.RXDATAVALID (), //
|
| 2297 |
|
|
.RXHEADER (), //
|
| 2298 |
|
|
.RXHEADERVALID (), //
|
| 2299 |
|
|
.RXSTARTOFSEQ (), //
|
| 2300 |
|
|
|
| 2301 |
|
|
//---------- PRBS/Loopback ---------------------------------------------
|
| 2302 |
|
|
.TXPRBSSEL (GT_TXPRBSSEL), //
|
| 2303 |
|
|
.RXPRBSSEL (GT_RXPRBSSEL), //
|
| 2304 |
|
|
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
|
| 2305 |
|
|
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
|
| 2306 |
|
|
.LOOPBACK (GT_LOOPBACK), //
|
| 2307 |
|
|
|
| 2308 |
|
|
.RXPRBSERR (GT_RXPRBSERR), //
|
| 2309 |
|
|
|
| 2310 |
|
|
//---------- OOB -------------------------------------------------------
|
| 2311 |
|
|
.TXCOMINIT (1'd0), //
|
| 2312 |
|
|
.TXCOMSAS (1'd0), //
|
| 2313 |
|
|
.TXCOMWAKE (1'd0), //
|
| 2314 |
|
|
.RXOOBRESET (1'd0), //
|
| 2315 |
|
|
|
| 2316 |
|
|
.TXCOMFINISH (), //
|
| 2317 |
|
|
.RXCOMINITDET (), //
|
| 2318 |
|
|
.RXCOMSASDET (), //
|
| 2319 |
|
|
.RXCOMWAKEDET (), //
|
| 2320 |
|
|
|
| 2321 |
|
|
//---------- MISC ------------------------------------------------------
|
| 2322 |
|
|
.SETERRSTATUS ( 1'd0), //
|
| 2323 |
|
|
.TXDIFFPD ( 1'd0), //
|
| 2324 |
|
|
.TXPISOPD ( 1'd0), //
|
| 2325 |
|
|
.TSTIN (20'hFFFFF), //
|
| 2326 |
|
|
|
| 2327 |
|
|
.TSTOUT () // GTX
|
| 2328 |
|
|
|
| 2329 |
|
|
);
|
| 2330 |
|
|
|
| 2331 |
|
|
//---------- Default -------------------------------------------------------
|
| 2332 |
|
|
assign dmonitorout[14:8] = 7'd0; // GTH GTP
|
| 2333 |
|
|
assign GT_TXSYNCOUT = 1'd0; // GTH GTP
|
| 2334 |
|
|
assign GT_TXSYNCDONE = 1'd0; // GTH GTP
|
| 2335 |
|
|
assign GT_RXSYNCOUT = 1'd0; // GTH GTP
|
| 2336 |
|
|
assign GT_RXSYNCDONE = 1'd0; // GTH GTP
|
| 2337 |
|
|
assign GT_RXPMARESETDONE = 1'd0; // GTH GTP
|
| 2338 |
|
|
|
| 2339 |
|
|
end
|
| 2340 |
|
|
|
| 2341 |
|
|
endgenerate
|
| 2342 |
|
|
|
| 2343 |
|
|
|
| 2344 |
|
|
|
| 2345 |
|
|
//---------- GT Wrapper Outputs ------------------------------------------------
|
| 2346 |
|
|
assign GT_RXDATA = rxdata [31:0];
|
| 2347 |
|
|
assign GT_RXDATAK = rxdatak[ 3:0];
|
| 2348 |
|
|
assign GT_RXCHARISCOMMA = rxchariscomma[ 3:0];
|
| 2349 |
|
|
assign GT_DMONITOROUT = dmonitorout;
|
| 2350 |
|
|
|
| 2351 |
|
|
|
| 2352 |
|
|
|
| 2353 |
|
|
endmodule
|
