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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_gtp_pipe_rate.v
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dsmv |
// Version : 1.10
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dsmv |
//------------------------------------------------------------------------------
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// Filename : gtp_pipe_rate.v
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// Description : PIPE Rate Module for 7 Series Transceiver
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// Version : 19.0
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- PIPE Rate Module --------------------------------------------------
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module cl_a7pcie_x4_gtp_pipe_rate #
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(
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim mode
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parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
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)
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(
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//---------- Input -------------------------------------
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input RATE_CLK,
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input RATE_RST_N,
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input [ 1:0] RATE_RATE_IN,
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input RATE_DRP_DONE,
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input RATE_RXPMARESETDONE,
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input RATE_TXRATEDONE,
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input RATE_RXRATEDONE,
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input RATE_TXSYNC_DONE,
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input RATE_PHYSTATUS,
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//---------- Output ------------------------------------
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output RATE_PCLK_SEL,
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output RATE_DRP_START,
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output RATE_DRP_X16,
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output [ 2:0] RATE_RATE_OUT,
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output RATE_TXSYNC_START,
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output RATE_DONE,
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output RATE_IDLE,
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output [ 4:0] RATE_FSM
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);
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//---------- Input FF or Buffer ------------------------
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dsmv |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
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dsmv |
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//---------- Internal Signals --------------------------
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wire [ 2:0] rate;
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reg [ 3:0] txdata_wait_cnt = 4'd0;
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reg txratedone = 1'd0;
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reg rxratedone = 1'd0;
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reg phystatus = 1'd0;
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reg ratedone = 1'd0;
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//---------- Output FF or Buffer -----------------------
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reg pclk_sel = 1'd0;
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reg [ 2:0] rate_out = 3'd0;
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reg [ 3:0] fsm = 0;
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 0;
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localparam FSM_TXDATA_WAIT = 1;
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localparam FSM_PCLK_SEL = 2;
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localparam FSM_DRP_X16_START = 3;
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localparam FSM_DRP_X16_DONE = 4;
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localparam FSM_RATE_SEL = 5;
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localparam FSM_RXPMARESETDONE = 6;
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localparam FSM_DRP_X20_START = 7;
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localparam FSM_DRP_X20_DONE = 8;
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localparam FSM_RATE_DONE = 9;
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localparam FSM_TXSYNC_START = 10;
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localparam FSM_TXSYNC_DONE = 11;
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localparam FSM_DONE = 12; // Must sync value to pipe_user.v
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge RATE_CLK)
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begin
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if (!RATE_RST_N)
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begin
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//---------- 1st Stage FF --------------------------
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rate_in_reg1 <= 2'd0;
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drp_done_reg1 <= 1'd0;
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rxpmaresetdone_reg1 <= 1'd0;
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txratedone_reg1 <= 1'd0;
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rxratedone_reg1 <= 1'd0;
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phystatus_reg1 <= 1'd0;
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txsync_done_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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rate_in_reg2 <= 2'd0;
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drp_done_reg2 <= 1'd0;
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rxpmaresetdone_reg2 <= 1'd0;
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txratedone_reg2 <= 1'd0;
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rxratedone_reg2 <= 1'd0;
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phystatus_reg2 <= 1'd0;
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txsync_done_reg2 <= 1'd0;
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end
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else
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begin
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//---------- 1st Stage FF --------------------------
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rate_in_reg1 <= RATE_RATE_IN;
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drp_done_reg1 <= RATE_DRP_DONE;
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rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
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txratedone_reg1 <= RATE_TXRATEDONE;
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rxratedone_reg1 <= RATE_RXRATEDONE;
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phystatus_reg1 <= RATE_PHYSTATUS;
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txsync_done_reg1 <= RATE_TXSYNC_DONE;
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//---------- 2nd Stage FF --------------------------
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rate_in_reg2 <= rate_in_reg1;
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drp_done_reg2 <= drp_done_reg1;
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rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
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txratedone_reg2 <= txratedone_reg1;
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rxratedone_reg2 <= rxratedone_reg1;
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phystatus_reg2 <= phystatus_reg1;
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txsync_done_reg2 <= txsync_done_reg1;
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end
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end
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//---------- Select Rate -------------------------------------------------------
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// Gen1 : div 2 using [TX/RX]OUT_DIV = 2
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// Gen2 : div 1 using [TX/RX]RATE = 3'd1
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//------------------------------------------------------------------------------
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assign rate = (rate_in_reg2 == 2'd1) ? 3'd1 : 3'd0;
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//---------- TXDATA Wait Counter -----------------------------------------------
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always @ (posedge RATE_CLK)
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begin
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if (!RATE_RST_N)
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txdata_wait_cnt <= 4'd0;
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else
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//---------- Increment Wait Counter ----------------
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if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
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txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
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//---------- Hold Wait Counter ---------------------
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else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
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txdata_wait_cnt <= txdata_wait_cnt;
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//---------- Reset Wait Counter --------------------
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else
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txdata_wait_cnt <= 4'd0;
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end
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//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
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always @ (posedge RATE_CLK)
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begin
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if (!RATE_RST_N)
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begin
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txratedone <= 1'd0;
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rxratedone <= 1'd0;
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phystatus <= 1'd0;
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ratedone <= 1'd0;
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end
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else
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begin
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if ((fsm == FSM_RATE_DONE) || (fsm == FSM_RXPMARESETDONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE))
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begin
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//---------- Latch TXRATEDONE ------------------
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if (txratedone_reg2)
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txratedone <= 1'd1;
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else
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txratedone <= txratedone;
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//---------- Latch RXRATEDONE ------------------
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if (rxratedone_reg2)
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rxratedone <= 1'd1;
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else
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rxratedone <= rxratedone;
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//---------- Latch PHYSTATUS -------------------
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if (phystatus_reg2)
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phystatus <= 1'd1;
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else
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phystatus <= phystatus;
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//---------- Latch Rate Done -------------------
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if (rxratedone && txratedone && phystatus)
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ratedone <= 1'd1;
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else
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ratedone <= ratedone;
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end
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else
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begin
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txratedone <= 1'd0;
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rxratedone <= 1'd0;
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phystatus <= 1'd0;
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ratedone <= 1'd0;
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end
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end
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end
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281 |
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282 |
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//---------- PIPE Rate FSM -----------------------------------------------------
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283 |
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always @ (posedge RATE_CLK)
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begin
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285 |
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if (!RATE_RST_N)
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begin
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288 |
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fsm <= FSM_IDLE;
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pclk_sel <= 1'd0;
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rate_out <= 3'd0;
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end
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else
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begin
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case (fsm)
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297 |
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//---------- Idle State ----------------------------
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298 |
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FSM_IDLE :
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299 |
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300 |
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begin
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301 |
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//---------- Detect Rate Change ----------------
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302 |
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if (rate_in_reg2 != rate_in_reg1)
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begin
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304 |
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fsm <= FSM_TXDATA_WAIT;
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pclk_sel <= pclk_sel;
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rate_out <= rate_out;
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end
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else
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309 |
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begin
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310 |
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fsm <= FSM_IDLE;
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311 |
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pclk_sel <= pclk_sel;
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rate_out <= rate_out;
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end
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314 |
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end
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315 |
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316 |
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//---------- Wait for TXDATA to TX[P/N] Latency ----
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317 |
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FSM_TXDATA_WAIT :
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318 |
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319 |
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begin
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320 |
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fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
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pclk_sel <= pclk_sel;
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rate_out <= rate_out;
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end
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325 |
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//---------- Select PCLK Frequency -----------------
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326 |
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// Gen1 : PCLK = 125 MHz
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// Gen2 : PCLK = 250 MHz
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328 |
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//--------------------------------------------------
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329 |
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FSM_PCLK_SEL :
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331 |
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begin
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fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_SEL : FSM_DRP_X16_START;
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pclk_sel <= (rate_in_reg2 == 2'd1);
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rate_out <= rate_out;
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end
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337 |
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//---------- Start DRP x16 -------------------------
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338 |
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FSM_DRP_X16_START :
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339 |
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340 |
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begin
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341 |
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fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
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pclk_sel <= pclk_sel;
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rate_out <= rate_out;
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end
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345 |
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346 |
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//---------- Wait for DRP x16 Done -----------------
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347 |
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FSM_DRP_X16_DONE :
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348 |
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349 |
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begin
|
350 |
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fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
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351 |
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pclk_sel <= pclk_sel;
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352 |
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rate_out <= rate_out;
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353 |
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end
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354 |
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|
355 |
|
|
//---------- Select Rate ---------------------------
|
356 |
|
|
FSM_RATE_SEL :
|
357 |
|
|
|
358 |
|
|
begin
|
359 |
|
|
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_DONE : FSM_RXPMARESETDONE;
|
360 |
|
|
pclk_sel <= pclk_sel;
|
361 |
|
|
rate_out <= rate; // Update [TX/RX]RATE
|
362 |
|
|
end
|
363 |
|
|
|
364 |
|
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
365 |
|
|
FSM_RXPMARESETDONE :
|
366 |
|
|
|
367 |
|
|
begin
|
368 |
|
|
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
|
369 |
|
|
pclk_sel <= pclk_sel;
|
370 |
|
|
rate_out <= rate_out;
|
371 |
|
|
end
|
372 |
|
|
|
373 |
|
|
//---------- Start DRP x20 -------------------------
|
374 |
|
|
FSM_DRP_X20_START :
|
375 |
|
|
|
376 |
|
|
begin
|
377 |
|
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
378 |
|
|
pclk_sel <= pclk_sel;
|
379 |
|
|
rate_out <= rate_out;
|
380 |
|
|
end
|
381 |
|
|
|
382 |
|
|
//---------- Wait for DRP x20 Done -----------------
|
383 |
|
|
FSM_DRP_X20_DONE :
|
384 |
|
|
|
385 |
|
|
begin
|
386 |
|
|
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
|
387 |
|
|
pclk_sel <= pclk_sel;
|
388 |
|
|
rate_out <= rate_out;
|
389 |
|
|
end
|
390 |
|
|
|
391 |
|
|
//---------- Wait for Rate Change Done -------------
|
392 |
|
|
FSM_RATE_DONE :
|
393 |
|
|
|
394 |
|
|
begin
|
395 |
|
|
if (ratedone)
|
396 |
|
|
fsm <= FSM_TXSYNC_START;
|
397 |
|
|
else
|
398 |
|
|
fsm <= FSM_RATE_DONE;
|
399 |
|
|
|
400 |
|
|
pclk_sel <= pclk_sel;
|
401 |
|
|
rate_out <= rate_out;
|
402 |
|
|
end
|
403 |
|
|
|
404 |
|
|
//---------- Start TX Sync -------------------------
|
405 |
|
|
FSM_TXSYNC_START:
|
406 |
|
|
|
407 |
|
|
begin
|
408 |
|
|
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
409 |
|
|
pclk_sel <= pclk_sel;
|
410 |
|
|
rate_out <= rate_out;
|
411 |
|
|
end
|
412 |
|
|
|
413 |
|
|
//---------- Wait for TX Sync Done -----------------
|
414 |
|
|
FSM_TXSYNC_DONE:
|
415 |
|
|
|
416 |
|
|
begin
|
417 |
|
|
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
|
418 |
|
|
pclk_sel <= pclk_sel;
|
419 |
|
|
rate_out <= rate_out;
|
420 |
|
|
end
|
421 |
|
|
|
422 |
|
|
//---------- Rate Change Done ----------------------
|
423 |
|
|
FSM_DONE :
|
424 |
|
|
|
425 |
|
|
begin
|
426 |
|
|
fsm <= FSM_IDLE;
|
427 |
|
|
pclk_sel <= pclk_sel;
|
428 |
|
|
rate_out <= rate_out;
|
429 |
|
|
end
|
430 |
|
|
|
431 |
|
|
//---------- Default State -------------------------
|
432 |
|
|
default :
|
433 |
|
|
|
434 |
|
|
begin
|
435 |
|
|
fsm <= FSM_IDLE;
|
436 |
|
|
pclk_sel <= 1'd0;
|
437 |
|
|
rate_out <= 3'd0;
|
438 |
|
|
end
|
439 |
|
|
|
440 |
|
|
endcase
|
441 |
|
|
|
442 |
|
|
end
|
443 |
|
|
|
444 |
|
|
end
|
445 |
|
|
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
//---------- PIPE Rate Output --------------------------------------------------
|
449 |
|
|
assign RATE_PCLK_SEL = pclk_sel;
|
450 |
|
|
assign RATE_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
|
451 |
|
|
assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
|
452 |
|
|
assign RATE_RATE_OUT = rate_out;
|
453 |
|
|
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
|
454 |
|
|
assign RATE_DONE = (fsm == FSM_DONE);
|
455 |
|
|
assign RATE_IDLE = (fsm == FSM_IDLE);
|
456 |
|
|
assign RATE_FSM = {1'd0, fsm};
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
endmodule
|