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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_pcie_bram_7x.vhd
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-- Version : 1.11
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-- Description : single bram wrapper for the mb pcie block
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-- The bram A port is the write port
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-- the B port is the read port
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--
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--
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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library unimacro;
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use unimacro.vcomponents.all;
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entity cl_a7pcie_x4_pcie_bram_7x is
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generic(
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LINK_CAP_MAX_LINK_SPEED : INTEGER := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
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LINK_CAP_MAX_LINK_WIDTH : INTEGER := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
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IMPL_TARGET : STRING := "HARD"; -- the implementation target : HARD, SOFT
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DOB_REG : INTEGER := 0; -- 1 - use the output register;
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-- 0 - don't use the output register
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WIDTH : INTEGER := 0 -- supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
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-- 72 - uses RAMB36SDP
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);
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port (
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user_clk_i : in std_logic; -- user clock
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reset_i : in std_logic; -- bram reset
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wen_i : in std_logic; -- write enable
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waddr_i : in std_logic_vector(12 downto 0); -- write address
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wdata_i : in std_logic_vector(WIDTH - 1 downto 0); -- write data
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ren_i : in std_logic; -- read enable
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rce_i : in std_logic; -- output register clock enable
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raddr_i : in std_logic_vector(12 downto 0); -- read address
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rdata_o : out std_logic_vector(WIDTH - 1 downto 0) -- read data
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);
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end cl_a7pcie_x4_pcie_bram_7x;
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architecture v7_pcie of cl_a7pcie_x4_pcie_bram_7x is
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-- map the address bits
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function msb_addr (
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constant wdt : integer)
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return integer is
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variable addr_msb : integer := 8;
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begin -- msb_addr
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if (wdt = 4) then
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addr_msb := 12;
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elsif (wdt = 9) then
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addr_msb := 11;
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elsif (wdt = 18) then
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addr_msb := 10;
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elsif (wdt = 36) then
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addr_msb := 9;
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else
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addr_msb := 8;
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end if;
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return addr_msb;
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end msb_addr;
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constant ADDR_MSB : integer := msb_addr(WIDTH);
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-- set the width of the tied off low address bits
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function alb (
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constant wdt : integer)
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return integer is
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variable addr_lo_bit : integer := 8;
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begin -- alb
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if (wdt = 4) then
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addr_lo_bit := 2;
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elsif (wdt = 9) then
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addr_lo_bit := 3;
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elsif (wdt = 18) then
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addr_lo_bit := 4;
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elsif (wdt = 36) then
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addr_lo_bit := 5;
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else
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addr_lo_bit := 0; -- for WIDTH 72 use RAMB36SDP
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end if;
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return addr_lo_bit;
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end alb;
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constant ADDR_LO_BITS : integer := alb(WIDTH);
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-- map the data bits
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function msb_d (
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constant wdt : integer)
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return integer is
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variable dmsb : integer := 8;
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begin -- msb_d
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if (wdt = 4) then
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dmsb := 3;
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elsif (wdt = 9) then
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dmsb := 7;
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elsif (wdt = 18) then
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dmsb := 15;
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elsif (wdt = 36) then
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dmsb := 31;
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else
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dmsb := 63;
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end if;
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return dmsb;
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end msb_d;
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constant D_MSB : integer := msb_d(WIDTH);
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-- map the data parity bits
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constant DP_LSB : integer := D_MSB + 1;
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function msb_dp (
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constant wdt : integer)
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return integer is
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variable dpmsb : integer := 8;
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begin -- msb_dp
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if (wdt = 4) then
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dpmsb := 4;
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elsif (wdt = 9) then
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dpmsb := 8;
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elsif (wdt = 18) then
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dpmsb := 17;
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elsif (wdt = 36) then
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dpmsb := 35;
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else
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dpmsb := 71;
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end if;
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return dpmsb;
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end msb_dp;
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function pad_val (
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in_vec : std_logic_vector;
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range_hi : integer;
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range_lo : integer;
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pad : std_logic;
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op_len : integer)
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return std_logic_vector is
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variable ret : std_logic_vector(op_len-1 downto 0) := (others => '0');
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begin -- pad_val
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for i in 0 to op_len-1 loop
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if ((i >= range_lo) and (i <= range_hi)) then
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ret(i) := in_vec(i - range_lo);
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else
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ret(i) := pad;
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end if;
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end loop; -- i
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return ret;
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end pad_val;
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function device_val (
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impl_target : string)
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return string is
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begin -- dev
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if (impl_target = "HARD") then
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return "7SERIES";
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else
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return "VIRTEX6";
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end if;
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end device_val;
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function get_write_mode (
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link_width : integer;
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WIDTH : integer;
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link_speed : integer)
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return string is
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begin -- wr_mode
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if ((WIDTH = 72) and (not((link_width =8) and (link_speed = 2)))) then
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return "WRITE_FIRST";
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elsif ((link_width =8) and (link_speed = 2)) then
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return "WRITE_FIRST";
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else
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return "NO_CHANGE";
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end if;
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end get_write_mode;
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function get_we_width (
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DEVICE : string;
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WIDTH : integer)
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return integer is
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begin -- wr_mode
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if ((DEVICE = "VIRTEX5") or (DEVICE = "VIRTEX6") or (DEVICE = "7SERIES")) then
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if (WIDTH <= 9) then
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return 1;
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elsif (WIDTH > 9 and WIDTH <= 18) then
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return 2;
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elsif (WIDTH > 18 and WIDTH <= 36) then
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return 4;
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elsif (WIDTH > 36 and WIDTH <= 72) then
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return 8;
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else
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return 8;
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end if;
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else
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return 8;
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end if;
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end get_we_width;
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constant DP_MSB : integer := msb_dp(WIDTH);
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constant DPW : integer := DP_MSB - DP_LSB + 1;
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constant WRITE_MODE : string := get_write_mode(LINK_CAP_MAX_LINK_WIDTH,WIDTH,LINK_CAP_MAX_LINK_SPEED);
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constant BRAM_SIZE : string := "36Kb";
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constant DEVICE : string := device_val(IMPL_TARGET);
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constant WE_WIDTH : integer := get_we_width(DEVICE,WIDTH);
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signal DIB_dummy : std_logic_vector ((WIDTH-1) downto 0);
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signal WE_dummy_gnd : std_logic_vector ((WE_WIDTH-1) downto 0);
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signal WE_dummy_vcc : std_logic_vector ((WE_WIDTH-1) downto 0);
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signal rdata_o_dummy : std_logic_vector (WIDTH-1 downto 0);
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begin
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-- Tie off dummy vectors
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DIB_dummy <= (others => '0');
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WE_dummy_gnd <= (others => '0');
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WE_dummy_vcc <= (others => '1');
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--synthesis translate_off
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process
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begin
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--$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
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-- $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
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case WIDTH is
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when 4 | 9 | 18 | 36 | 72 =>
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when others => -- case (WIDTH)
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-- $display("[%t] %m Error WIDTH %0d not supported", now, to_stdlogic(WIDTH));
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-- $finish();
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end case;
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wait;
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end process;
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--synthesis translate_on
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use_sdp : if (((LINK_CAP_MAX_LINK_WIDTH = "001000") and (LINK_CAP_MAX_LINK_SPEED = "0010")) or ( WIDTH = 72)) generate
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-- v6pcie2 <= (others => wen_i);
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-- rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
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295 |
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-- use RAMB36SDP if the width is 72 or X8GEN2
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ramb36sdp : BRAM_SDP_MACRO
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298 |
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generic map (
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299 |
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DEVICE => DEVICE,
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BRAM_SIZE => BRAM_SIZE,
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DO_REG => DOB_REG,
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READ_WIDTH => WIDTH,
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WRITE_WIDTH => WIDTH,
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WRITE_MODE => WRITE_MODE
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)
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port map (
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DO => rdata_o(WIDTH-1 downto 0),
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DI => wdata_i(WIDTH-1 downto 0),
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RDADDR => raddr_i(ADDR_MSB downto 0),
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RDCLK => user_clk_i,
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311 |
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RDEN => ren_i,
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REGCE => rce_i,
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RST => reset_i,
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WE => WE_dummy_vcc,
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315 |
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WRADDR => waddr_i(ADDR_MSB downto 0),
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WRCLK => user_clk_i,
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WREN => wen_i
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);
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-- use RAMB36's if the width is 4, 9, 18, or 36
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321 |
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end generate;
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323 |
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use_tdp : if (( WIDTH <= 36) and (not((LINK_CAP_MAX_LINK_WIDTH = "001000") and (LINK_CAP_MAX_LINK_SPEED = "0010")))) generate
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324 |
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-- use RAMB36SDP if the width is 72 or X8GEN2
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325 |
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ramb36 : BRAM_TDP_MACRO
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326 |
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generic map (
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327 |
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DEVICE => DEVICE,
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BRAM_SIZE => BRAM_SIZE,
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329 |
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DOA_REG => 0,
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330 |
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DOB_REG => DOB_REG,
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READ_WIDTH_A => WIDTH,
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READ_WIDTH_B => WIDTH,
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333 |
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WRITE_WIDTH_A => WIDTH,
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334 |
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WRITE_WIDTH_B => WIDTH,
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WRITE_MODE_A => WRITE_MODE
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)
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337 |
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port map (
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338 |
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DOA => rdata_o_dummy(WIDTH-1 downto 0),
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339 |
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DOB => rdata_o(WIDTH-1 downto 0),
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340 |
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ADDRA => waddr_i(ADDR_MSB downto 0),
|
341 |
|
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ADDRB => raddr_i(ADDR_MSB downto 0),
|
342 |
|
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CLKA => user_clk_i,
|
343 |
|
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CLKB => user_clk_i,
|
344 |
|
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DIA => wdata_i(WIDTH-1 downto 0),
|
345 |
|
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DIB => DIB_dummy,
|
346 |
|
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ENA => wen_i,
|
347 |
|
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ENB => ren_i,
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348 |
|
|
REGCEA => '0',
|
349 |
|
|
REGCEB => rce_i,
|
350 |
|
|
RSTA => reset_i,
|
351 |
|
|
RSTB => reset_i,
|
352 |
|
|
WEA => WE_dummy_vcc,
|
353 |
|
|
WEB => WE_dummy_gnd
|
354 |
|
|
);
|
355 |
|
|
|
356 |
|
|
end generate;
|
357 |
|
|
end v7_pcie;
|
358 |
|
|
|