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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_pcie_brams_7x.vhd
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-- Version : 1.10
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-- Description : pcie bram wrapper
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-- arrange and connect brams
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-- implement address decoding, datapath muxing and pipeline stages
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--
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-- banks of brams are used for 1,2,4,8,18 brams
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-- brams are stacked for other values of NUM_BRAMS
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_unsigned.all;
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entity cl_a7pcie_x4_pcie_brams_7x is
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generic(
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LINK_CAP_MAX_LINK_SPEED : integer := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
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LINK_CAP_MAX_LINK_WIDTH : integer := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
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IMPL_TARGET : string := "HARD"; -- the implementation target : HARD, SOFT
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-- the number of BRAMs to use
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-- supported values are:
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-- 1,2,4,8,18
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NUM_BRAMS : integer := 0;
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-- BRAM read address latency
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--
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-- value meaning
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-- ==========================
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-- 0 BRAM read address port sample
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-- 1 BRAM read address port sample and a pipeline stage on the address port
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RAM_RADDR_LATENCY : integer := 1;
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-- BRAM read data latency
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--
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-- value meaning
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-- ==========================
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-- 1 no BRAM OREG
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-- 2 use BRAM OREG
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-- 3 use BRAM OREG and a pipeline stage on the data port
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RAM_RDATA_LATENCY :integer := 1;
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-- BRAM write latency
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-- The BRAM write port is synchronous
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--
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-- value meaning
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-- ==========================
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-- 0 BRAM write port sample
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-- 1 BRAM write port sample plus pipeline stage
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RAM_WRITE_LATENCY :integer := 1
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);
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port (
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user_clk_i : in std_logic; -- user clock
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reset_i : in std_logic; -- bram reset
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wen : in std_logic; -- write enable
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waddr : in std_logic_vector(12 downto 0); -- write address
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wdata : in std_logic_vector(71 downto 0); -- write data
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ren : in std_logic; -- read enable
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rce : in std_logic; -- output register clock enable
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raddr : in std_logic_vector(12 downto 0); -- read address
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rdata : out std_logic_vector(71 downto 0) -- read data
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);
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end cl_a7pcie_x4_pcie_brams_7x;
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architecture pcie_7x of cl_a7pcie_x4_pcie_brams_7x is
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component cl_a7pcie_x4_pcie_bram_7x is
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generic (
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LINK_CAP_MAX_LINK_SPEED : INTEGER := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
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LINK_CAP_MAX_LINK_WIDTH : INTEGER := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
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IMPL_TARGET : STRING := "HARD"; -- the implementation target : HARD, SOFT
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DOB_REG : INTEGER := 0; -- 1 - use the output register;
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-- 0 - don't use the output register
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WIDTH : INTEGER := 0 -- supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
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-- 72 - uses RAMB36SDP
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);
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port (
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user_clk_i : in std_logic; -- user clock
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reset_i : in std_logic; -- bram reset
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wen_i : in std_logic; -- write enable
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waddr_i : in std_logic_vector(12 downto 0); -- write address
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wdata_i : in std_logic_vector(WIDTH - 1 downto 0); -- write data
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ren_i : in std_logic; -- read enable
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rce_i : in std_logic; -- output register clock enable
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raddr_i : in std_logic_vector(12 downto 0); -- read address
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rdata_o : out std_logic_vector(WIDTH - 1 downto 0) -- read data
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);
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end component;
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function get_dob_reg (
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constant rdata_lat : integer)
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return integer is
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begin -- get_dob_reg
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if (rdata_lat > 1) then
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return 1;
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else
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return 0;
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end if;
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end get_dob_reg;
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function get_width (
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constant num_brams : integer)
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return integer is
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begin -- msb_d
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if (num_brams = 1) then
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return 72;
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elsif (num_brams = 2) then
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return 36;
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elsif (num_brams = 4) then
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return 18;
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elsif (num_brams = 8) then
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return 9;
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else
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return 4;
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end if;
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end get_width;
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constant DOB_REG : integer := get_dob_reg(RAM_RDATA_LATENCY);
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constant WIDTH : integer := get_width(NUM_BRAMS);
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constant TCQ : integer := 1;
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signal wen_int : std_logic;
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signal waddr_int : std_logic_vector(12 downto 0);
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signal wdata_int : std_logic_vector(71 downto 0);
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signal wen_q : std_logic := '0';
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signal waddr_q : std_logic_vector(12 downto 0) := (others => '0');
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signal wdata_q : std_logic_vector(71 downto 0) := (others => '0');
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signal ren_int : std_logic;
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signal raddr_int : std_logic_vector(12 downto 0);
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signal rdata_int : std_logic_vector(71 downto 0);
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signal ren_q : std_logic := '0';
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signal raddr_q : std_logic_vector(12 downto 0) := (others => '0');
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signal rdata_q : std_logic_vector(71 downto 0) := (others => '0');
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begin
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--synthesis translate_off
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process
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begin
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-- $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
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-- now, to_stdlogic(NUM_BRAMS), to_stdlogicvector(DOB_REG, 13),
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-- ("00000000000000000000000000000000000000000000000000000000000000000" & WIDTH), to_stdlogic(RAM_WRITE_LATENCY),
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-- to_stdlogic(RAM_RADDR_LATENCY), to_stdlogicvector(RAM_RDATA_LATENCY, 13));
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case NUM_BRAMS is
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when 1 | 2 | 4 | 8 | 18 =>
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when others =>
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-- $display("[%t] %m Error NUM_BRAMS %0d not supported", now, to_stdlogic(NUM_BRAMS));
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-- $finish();
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end case; -- case(NUM_BRAMS)
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case RAM_RADDR_LATENCY is
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when 0 | 1 =>
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when others =>
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-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RADDR_LATENCY));
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-- $finish();
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end case; -- case (RAM_RADDR_LATENCY)
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case RAM_RDATA_LATENCY is
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when 1 | 2 | 3 =>
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when others =>
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-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RDATA_LATENCY));
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-- $finish();
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end case; -- case (RAM_RDATA_LATENCY)
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case RAM_WRITE_LATENCY is
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when 0 | 1 =>
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when others =>
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-- $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", now, to_stdlogic(RAM_WRITE_LATENCY));
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-- $finish();
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end case; -- case(RAM_WRITE_LATENCY)
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wait;
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end process;
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--synthesis translate_on
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-- model the delays for ram write latency
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wr_lat_2 : if (RAM_WRITE_LATENCY = 1) generate
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process (user_clk_i)
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begin
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if (user_clk_i'event and user_clk_i = '1') then
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if (reset_i = '1') then
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wen_q <= '0' after (TCQ)*1 ps;
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waddr_q <= "0000000000000" after (TCQ)*1 ps;
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wdata_q <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
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else
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wen_q <= wen after (TCQ)*1 ps;
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waddr_q <= waddr after (TCQ)*1 ps;
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wdata_q <= wdata after (TCQ)*1 ps;
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end if;
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end if;
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end process;
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wen_int <= wen_q;
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waddr_int <= waddr_q;
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wdata_int <= wdata_q;
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end generate;
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wr_lat_1 : if (RAM_WRITE_LATENCY = 0) generate
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wen_int <= wen;
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waddr_int <= waddr;
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wdata_int <= wdata;
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end generate;
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raddr_lat_2 : if (RAM_RADDR_LATENCY = 1) generate
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process (user_clk_i)
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begin
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if (user_clk_i'event and user_clk_i = '1') then
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if (reset_i = '1') then
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ren_q <= '0' after (TCQ)*1 ps;
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raddr_q <= "0000000000000" after (TCQ)*1 ps;
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else
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ren_q <= ren after (TCQ)*1 ps;
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raddr_q <= raddr after (TCQ)*1 ps;
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end if; -- else: !if(reset_i)
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end if;
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end process;
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ren_int <= ren_q;
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raddr_int <= raddr_q;
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end generate; -- block: rd_lat_addr_2
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raddr_lat_1 : if (not(RAM_RADDR_LATENCY = 1)) generate
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ren_int <= ren;
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raddr_int <= raddr;
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end generate;
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rdata_lat_3 : if (RAM_RDATA_LATENCY = 3) generate
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process (user_clk_i)
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begin
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if (user_clk_i'event and user_clk_i = '1') then
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if (reset_i = '1') then
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rdata_q <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
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else
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rdata_q <= rdata_int after (TCQ)*1 ps;
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end if; -- else: !if(reset_i)
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end if;
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end process;
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rdata <= rdata_q;
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end generate; -- block: rd_lat_data_3
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rdata_lat_1_2 : if (not(RAM_RDATA_LATENCY = 3)) generate
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rdata <= rdata_int after (TCQ)*1 ps;
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end generate;
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-- instantiate the brams
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brams : for ii in 0 to NUM_BRAMS - 1 generate
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ram : cl_a7pcie_x4_pcie_bram_7x
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generic map (
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LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH,
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LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
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IMPL_TARGET => IMPL_TARGET,
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DOB_REG => DOB_REG,
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WIDTH => WIDTH
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)
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port map (
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user_clk_i => user_clk_i,
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reset_i => reset_i,
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wen_i => wen_int,
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waddr_i => waddr_int,
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wdata_i => wdata_int(((ii+1)*WIDTH-1) downto (ii * WIDTH)),
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ren_i => ren_int,
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raddr_i => raddr_int,
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rdata_o => rdata_int(((ii+1)*WIDTH-1) downto (ii * WIDTH)),
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rce_i => rce
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);
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end generate;
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-- pcie_brams_7x
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end pcie_7x;
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