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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_drp.v
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// Version : 1.11
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//------------------------------------------------------------------------------
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// Filename : pipe_drp.v
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// Description : PIPE DRP Module for 7 Series Transceiver
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// Version : 20.0
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- PIPE DRP Module ---------------------------------------------------
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module cl_a7pcie_x4_pipe_drp #
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(
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
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parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
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parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
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parameter LOAD_CNT_MAX = 2'd1, // Load max count
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parameter INDEX_MAX = 5'd21 // Index max count
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)
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(
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//---------- Input -------------------------------------
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input DRP_CLK,
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input DRP_RST_N,
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input DRP_GTXRESET,
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input [ 1:0] DRP_RATE,
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input DRP_X16X20_MODE,
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input DRP_X16,
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input DRP_START,
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input [15:0] DRP_DO,
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input DRP_RDY,
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//---------- Output ------------------------------------
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output [ 8:0] DRP_ADDR,
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output DRP_EN,
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output [15:0] DRP_DI,
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output DRP_WE,
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output DRP_DONE,
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output [ 2:0] DRP_FSM
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);
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//---------- Input Registers ---------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
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//---------- Internal Signals --------------------------
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 4:0] index = 5'd0;
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reg mode = 1'd0;
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reg [ 8:0] addr_reg = 9'd0;
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reg [15:0] di_reg = 16'd0;
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//---------- Output Registers --------------------------
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reg done = 1'd0;
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reg [ 2:0] fsm = 0;
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//---------- DRP Address -------------------------------
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// DRP access for *RXCDR_EIDLE includes
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// - [11] RXCDR_HOLD_DURING_EIDLE
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// - [12] RXCDR_FR_RESET_ON_EIDLE
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// - [13] RXCDR_PH_RESET_ON_EIDLE
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//------------------------------------------------------
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localparam ADDR_PCS_RSVD_ATTR = 9'h06F;
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localparam ADDR_TXOUT_DIV = 9'h088;
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localparam ADDR_RXOUT_DIV = 9'h088;
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localparam ADDR_TX_DATA_WIDTH = 9'h06B;
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localparam ADDR_TX_INT_DATAWIDTH = 9'h06B;
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localparam ADDR_RX_DATA_WIDTH = 9'h011;
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localparam ADDR_RX_INT_DATAWIDTH = 9'h011;
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localparam ADDR_TXBUF_EN = 9'h01C;
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localparam ADDR_RXBUF_EN = 9'h09D;
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localparam ADDR_TX_XCLK_SEL = 9'h059;
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localparam ADDR_RX_XCLK_SEL = 9'h059;
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localparam ADDR_CLK_CORRECT_USE = 9'h044;
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localparam ADDR_TX_DRIVE_MODE = 9'h019;
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localparam ADDR_RXCDR_EIDLE = 9'h0A7;
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localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E;
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localparam ADDR_PMA_RSV_A = 9'h099;
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localparam ADDR_PMA_RSV_B = 9'h09A;
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localparam ADDR_RXCDR_CFG_A = 9'h0A8;
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localparam ADDR_RXCDR_CFG_B = 9'h0A9;
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localparam ADDR_RXCDR_CFG_C = 9'h0AA;
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localparam ADDR_RXCDR_CFG_D = 9'h0AB;
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localparam ADDR_RXCDR_CFG_E = 9'h0AC;
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localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only
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//---------- DRP Mask ----------------------------------
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localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1]
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localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4]
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localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0]
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localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
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localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4]
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localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11]
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localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only
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localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14]
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localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14]
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localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1]
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localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7]
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localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6]
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localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14]
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localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0]
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localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11]
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localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14]
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localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0]
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localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0]
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localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0]
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localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0]
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localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0]
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localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0]
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localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0]
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localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0]
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localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ]
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localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
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//---------- DRP Data for PCIe Gen1 and Gen2 -----------
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localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2
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localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2
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localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width
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localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
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localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width
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localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
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localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
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localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer
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localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
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localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC
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localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction
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localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode
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localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle
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localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle
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localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480
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localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001
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localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
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localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
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//----------
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localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020
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localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020
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localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF
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localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
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localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
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localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003
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localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
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//----------
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localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
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localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
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localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208
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localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000
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localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE
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localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020
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localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000
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//---------- DRP Data for PCIe Gen3 --------------------
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localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1
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localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1
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localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width
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localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width
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localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width
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localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width
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localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer
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localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer
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localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR
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localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR
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localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction
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localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode
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localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle
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localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle
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localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080
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localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E
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localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
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localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
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//----------
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localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080
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localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010
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localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF
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localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
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localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
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localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B
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localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
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//----------
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//localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
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|
|
//localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
|
258 |
|
|
//localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848
|
259 |
|
|
//localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000
|
260 |
|
|
//localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
|
261 |
|
|
//localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
|
262 |
|
|
//localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010
|
263 |
|
|
//localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
|
264 |
|
|
//localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
|
265 |
|
|
//----------
|
266 |
|
|
localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
|
267 |
|
|
localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
|
268 |
|
|
localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848
|
269 |
|
|
localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000
|
270 |
|
|
localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
|
271 |
|
|
localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
|
272 |
|
|
localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010
|
273 |
|
|
localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
|
274 |
|
|
localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
|
275 |
|
|
|
276 |
|
|
//---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----
|
277 |
|
|
localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode
|
278 |
|
|
localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode
|
279 |
|
|
localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode
|
280 |
|
|
|
281 |
|
|
//---------- DRP Data for x16 --------------------------
|
282 |
|
|
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
|
283 |
|
|
|
284 |
|
|
//---------- DRP Data for x20 --------------------------
|
285 |
|
|
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
|
286 |
|
|
|
287 |
|
|
//---------- DRP Data ----------------------------------
|
288 |
|
|
wire [15:0] data_txout_div;
|
289 |
|
|
wire [15:0] data_rxout_div;
|
290 |
|
|
wire [15:0] data_tx_data_width;
|
291 |
|
|
wire [15:0] data_tx_int_datawidth;
|
292 |
|
|
wire [15:0] data_rx_data_width;
|
293 |
|
|
wire [15:0] data_rx_int_datawidth;
|
294 |
|
|
wire [15:0] data_txbuf_en;
|
295 |
|
|
wire [15:0] data_rxbuf_en;
|
296 |
|
|
wire [15:0] data_tx_xclk_sel;
|
297 |
|
|
wire [15:0] data_rx_xclk_sel;
|
298 |
|
|
wire [15:0] data_clk_correction_use;
|
299 |
|
|
wire [15:0] data_tx_drive_mode;
|
300 |
|
|
wire [15:0] data_rxcdr_eidle;
|
301 |
|
|
wire [15:0] data_rx_dfe_lpm_eidle;
|
302 |
|
|
wire [15:0] data_pma_rsv_a;
|
303 |
|
|
wire [15:0] data_pma_rsv_b;
|
304 |
|
|
|
305 |
|
|
wire [15:0] data_rxcdr_cfg_a;
|
306 |
|
|
wire [15:0] data_rxcdr_cfg_b;
|
307 |
|
|
wire [15:0] data_rxcdr_cfg_c;
|
308 |
|
|
wire [15:0] data_rxcdr_cfg_d;
|
309 |
|
|
wire [15:0] data_rxcdr_cfg_e;
|
310 |
|
|
wire [15:0] data_rxcdr_cfg_f;
|
311 |
|
|
|
312 |
|
|
wire [15:0] data_pcs_rsvd_attr_a;
|
313 |
|
|
wire [15:0] data_pcs_rsvd_attr_m_tx;
|
314 |
|
|
wire [15:0] data_pcs_rsvd_attr_m_rx;
|
315 |
|
|
wire [15:0] data_pcs_rsvd_attr_m;
|
316 |
|
|
|
317 |
|
|
wire [15:0] data_x16x20_rx_datawidth;
|
318 |
|
|
|
319 |
|
|
//---------- FSM ---------------------------------------
|
320 |
|
|
localparam FSM_IDLE = 0;
|
321 |
|
|
localparam FSM_LOAD = 1;
|
322 |
|
|
localparam FSM_READ = 2;
|
323 |
|
|
localparam FSM_RRDY = 3;
|
324 |
|
|
localparam FSM_WRITE = 4;
|
325 |
|
|
localparam FSM_WRDY = 5;
|
326 |
|
|
localparam FSM_DONE = 6;
|
327 |
|
|
|
328 |
|
|
|
329 |
|
|
|
330 |
|
|
//---------- Input FF ----------------------------------------------------------
|
331 |
|
|
always @ (posedge DRP_CLK)
|
332 |
|
|
begin
|
333 |
|
|
|
334 |
|
|
if (!DRP_RST_N)
|
335 |
|
|
begin
|
336 |
|
|
//---------- 1st Stage FF --------------------------
|
337 |
|
|
gtxreset_reg1 <= 1'd0;
|
338 |
|
|
rate_reg1 <= 2'd0;
|
339 |
|
|
x16x20_mode_reg1 <= 1'd0;
|
340 |
|
|
x16_reg1 <= 1'd0;
|
341 |
|
|
do_reg1 <= 16'd0;
|
342 |
|
|
rdy_reg1 <= 1'd0;
|
343 |
|
|
start_reg1 <= 1'd0;
|
344 |
|
|
//---------- 2nd Stage FF --------------------------
|
345 |
|
|
gtxreset_reg2 <= 1'd0;
|
346 |
|
|
rate_reg2 <= 2'd0;
|
347 |
|
|
x16x20_mode_reg2 <= 1'd0;
|
348 |
|
|
x16_reg2 <= 1'd0;
|
349 |
|
|
do_reg2 <= 16'd0;
|
350 |
|
|
rdy_reg2 <= 1'd0;
|
351 |
|
|
start_reg2 <= 1'd0;
|
352 |
|
|
end
|
353 |
|
|
|
354 |
|
|
else
|
355 |
|
|
begin
|
356 |
|
|
//---------- 1st Stage FF --------------------------
|
357 |
|
|
gtxreset_reg1 <= DRP_GTXRESET;
|
358 |
|
|
rate_reg1 <= DRP_RATE;
|
359 |
|
|
x16x20_mode_reg1 <= DRP_X16X20_MODE;
|
360 |
|
|
x16_reg1 <= DRP_X16;
|
361 |
|
|
do_reg1 <= DRP_DO;
|
362 |
|
|
rdy_reg1 <= DRP_RDY;
|
363 |
|
|
start_reg1 <= DRP_START;
|
364 |
|
|
//---------- 2nd Stage FF --------------------------
|
365 |
|
|
gtxreset_reg2 <= gtxreset_reg1;
|
366 |
|
|
rate_reg2 <= rate_reg1;
|
367 |
|
|
x16x20_mode_reg2 <= x16x20_mode_reg1;
|
368 |
|
|
x16_reg2 <= x16_reg1;
|
369 |
|
|
do_reg2 <= do_reg1;
|
370 |
|
|
rdy_reg2 <= rdy_reg1;
|
371 |
|
|
start_reg2 <= start_reg1;
|
372 |
|
|
end
|
373 |
|
|
|
374 |
|
|
end
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
|
378 |
|
|
//---------- Select DRP Data ---------------------------------------------------
|
379 |
|
|
assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV;
|
380 |
|
|
assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV;
|
381 |
|
|
assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH;
|
382 |
|
|
assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
|
383 |
|
|
assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH;
|
384 |
|
|
|
385 |
|
|
assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
|
386 |
|
|
|
387 |
|
|
assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN;
|
388 |
|
|
assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN;
|
389 |
|
|
assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL;
|
390 |
|
|
assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL;
|
391 |
|
|
assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE;
|
392 |
|
|
assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE;
|
393 |
|
|
assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE;
|
394 |
|
|
assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
|
395 |
|
|
assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) :
|
396 |
|
|
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
|
397 |
|
|
assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) :
|
398 |
|
|
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
|
399 |
|
|
|
400 |
|
|
assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) :
|
401 |
|
|
((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
|
402 |
|
|
|
403 |
|
|
assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) :
|
404 |
|
|
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
|
405 |
|
|
|
406 |
|
|
assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) :
|
407 |
|
|
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
|
408 |
|
|
|
409 |
|
|
assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
|
410 |
|
|
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
|
411 |
|
|
|
412 |
|
|
assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) :
|
413 |
|
|
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
|
414 |
|
|
|
415 |
|
|
assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
|
416 |
|
|
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
|
417 |
|
|
|
418 |
|
|
assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A;
|
419 |
|
|
assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
|
420 |
|
|
assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
|
421 |
|
|
assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
|
422 |
|
|
|
423 |
|
|
assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
//---------- Load Counter ------------------------------------------------------
|
427 |
|
|
always @ (posedge DRP_CLK)
|
428 |
|
|
begin
|
429 |
|
|
|
430 |
|
|
if (!DRP_RST_N)
|
431 |
|
|
load_cnt <= 2'd0;
|
432 |
|
|
else
|
433 |
|
|
|
434 |
|
|
//---------- Increment Load Counter ----------------
|
435 |
|
|
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
|
436 |
|
|
load_cnt <= load_cnt + 2'd1;
|
437 |
|
|
|
438 |
|
|
//---------- Hold Load Counter ---------------------
|
439 |
|
|
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
|
440 |
|
|
load_cnt <= load_cnt;
|
441 |
|
|
|
442 |
|
|
//---------- Reset Load Counter --------------------
|
443 |
|
|
else
|
444 |
|
|
load_cnt <= 2'd0;
|
445 |
|
|
|
446 |
|
|
end
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
|
450 |
|
|
//---------- Update DRP Address and Data ---------------------------------------
|
451 |
|
|
always @ (posedge DRP_CLK)
|
452 |
|
|
begin
|
453 |
|
|
|
454 |
|
|
if (!DRP_RST_N)
|
455 |
|
|
begin
|
456 |
|
|
addr_reg <= 9'd0;
|
457 |
|
|
di_reg <= 16'd0;
|
458 |
|
|
end
|
459 |
|
|
else
|
460 |
|
|
begin
|
461 |
|
|
|
462 |
|
|
case (index)
|
463 |
|
|
|
464 |
|
|
//--------------------------------------------------
|
465 |
|
|
5'd0:
|
466 |
|
|
begin
|
467 |
|
|
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR :
|
468 |
|
|
x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV;
|
469 |
|
|
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) :
|
470 |
|
|
x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) :
|
471 |
|
|
((do_reg2 & MASK_TXOUT_DIV) | data_txout_div);
|
472 |
|
|
end
|
473 |
|
|
|
474 |
|
|
//--------------------------------------------------
|
475 |
|
|
5'd1:
|
476 |
|
|
begin
|
477 |
|
|
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
|
478 |
|
|
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) :
|
479 |
|
|
((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div);
|
480 |
|
|
end
|
481 |
|
|
|
482 |
|
|
//--------------------------------------------------
|
483 |
|
|
5'd2 :
|
484 |
|
|
begin
|
485 |
|
|
addr_reg <= ADDR_TX_DATA_WIDTH;
|
486 |
|
|
di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
|
487 |
|
|
end
|
488 |
|
|
|
489 |
|
|
//--------------------------------------------------
|
490 |
|
|
5'd3 :
|
491 |
|
|
begin
|
492 |
|
|
addr_reg <= ADDR_TX_INT_DATAWIDTH;
|
493 |
|
|
di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
|
494 |
|
|
end
|
495 |
|
|
|
496 |
|
|
//--------------------------------------------------
|
497 |
|
|
5'd4 :
|
498 |
|
|
begin
|
499 |
|
|
addr_reg <= ADDR_RX_DATA_WIDTH;
|
500 |
|
|
di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
|
501 |
|
|
end
|
502 |
|
|
|
503 |
|
|
//--------------------------------------------------
|
504 |
|
|
5'd5 :
|
505 |
|
|
begin
|
506 |
|
|
addr_reg <= ADDR_RX_INT_DATAWIDTH;
|
507 |
|
|
di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
|
508 |
|
|
end
|
509 |
|
|
|
510 |
|
|
//--------------------------------------------------
|
511 |
|
|
5'd6 :
|
512 |
|
|
begin
|
513 |
|
|
addr_reg <= ADDR_TXBUF_EN;
|
514 |
|
|
di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
|
515 |
|
|
end
|
516 |
|
|
|
517 |
|
|
//--------------------------------------------------
|
518 |
|
|
5'd7 :
|
519 |
|
|
begin
|
520 |
|
|
addr_reg <= ADDR_RXBUF_EN;
|
521 |
|
|
di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
|
522 |
|
|
end
|
523 |
|
|
|
524 |
|
|
//--------------------------------------------------
|
525 |
|
|
5'd8 :
|
526 |
|
|
begin
|
527 |
|
|
addr_reg <= ADDR_TX_XCLK_SEL;
|
528 |
|
|
di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
|
529 |
|
|
end
|
530 |
|
|
|
531 |
|
|
//--------------------------------------------------
|
532 |
|
|
5'd9 :
|
533 |
|
|
begin
|
534 |
|
|
addr_reg <= ADDR_RX_XCLK_SEL;
|
535 |
|
|
di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
|
536 |
|
|
end
|
537 |
|
|
|
538 |
|
|
//--------------------------------------------------
|
539 |
|
|
5'd10 :
|
540 |
|
|
begin
|
541 |
|
|
addr_reg <= ADDR_CLK_CORRECT_USE;
|
542 |
|
|
di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
|
543 |
|
|
end
|
544 |
|
|
|
545 |
|
|
//--------------------------------------------------
|
546 |
|
|
5'd11 :
|
547 |
|
|
begin
|
548 |
|
|
addr_reg <= ADDR_TX_DRIVE_MODE;
|
549 |
|
|
di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
|
550 |
|
|
end
|
551 |
|
|
|
552 |
|
|
//--------------------------------------------------
|
553 |
|
|
5'd12 :
|
554 |
|
|
begin
|
555 |
|
|
addr_reg <= ADDR_RXCDR_EIDLE;
|
556 |
|
|
di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
|
557 |
|
|
end
|
558 |
|
|
|
559 |
|
|
//--------------------------------------------------
|
560 |
|
|
5'd13 :
|
561 |
|
|
begin
|
562 |
|
|
addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
|
563 |
|
|
di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
|
564 |
|
|
end
|
565 |
|
|
|
566 |
|
|
//--------------------------------------------------
|
567 |
|
|
5'd14 :
|
568 |
|
|
begin
|
569 |
|
|
addr_reg <= ADDR_PMA_RSV_A;
|
570 |
|
|
di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
|
571 |
|
|
end
|
572 |
|
|
|
573 |
|
|
//--------------------------------------------------
|
574 |
|
|
5'd15 :
|
575 |
|
|
begin
|
576 |
|
|
addr_reg <= ADDR_PMA_RSV_B;
|
577 |
|
|
di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
|
578 |
|
|
end
|
579 |
|
|
|
580 |
|
|
//--------------------------------------------------
|
581 |
|
|
5'd16 :
|
582 |
|
|
begin
|
583 |
|
|
addr_reg <= ADDR_RXCDR_CFG_A;
|
584 |
|
|
di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
|
585 |
|
|
end
|
586 |
|
|
|
587 |
|
|
//--------------------------------------------------
|
588 |
|
|
5'd17 :
|
589 |
|
|
begin
|
590 |
|
|
addr_reg <= ADDR_RXCDR_CFG_B;
|
591 |
|
|
di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
|
592 |
|
|
end
|
593 |
|
|
|
594 |
|
|
//--------------------------------------------------
|
595 |
|
|
5'd18 :
|
596 |
|
|
begin
|
597 |
|
|
addr_reg <= ADDR_RXCDR_CFG_C;
|
598 |
|
|
di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
|
599 |
|
|
end
|
600 |
|
|
|
601 |
|
|
//--------------------------------------------------
|
602 |
|
|
5'd19 :
|
603 |
|
|
begin
|
604 |
|
|
addr_reg <= ADDR_RXCDR_CFG_D;
|
605 |
|
|
di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
|
606 |
|
|
end
|
607 |
|
|
|
608 |
|
|
//--------------------------------------------------
|
609 |
|
|
5'd20 :
|
610 |
|
|
begin
|
611 |
|
|
addr_reg <= ADDR_RXCDR_CFG_E;
|
612 |
|
|
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
|
613 |
|
|
end
|
614 |
|
|
|
615 |
|
|
//--------------------------------------------------
|
616 |
|
|
5'd21 :
|
617 |
|
|
begin
|
618 |
|
|
addr_reg <= ADDR_RXCDR_CFG_F;
|
619 |
|
|
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
|
620 |
|
|
end
|
621 |
|
|
|
622 |
|
|
//--------------------------------------------------
|
623 |
|
|
default :
|
624 |
|
|
begin
|
625 |
|
|
addr_reg <= 9'd0;
|
626 |
|
|
di_reg <= 16'd0;
|
627 |
|
|
end
|
628 |
|
|
|
629 |
|
|
endcase
|
630 |
|
|
|
631 |
|
|
end
|
632 |
|
|
|
633 |
|
|
end
|
634 |
|
|
|
635 |
|
|
|
636 |
|
|
|
637 |
|
|
//---------- PIPE DRP FSM ------------------------------------------------------
|
638 |
|
|
always @ (posedge DRP_CLK)
|
639 |
|
|
begin
|
640 |
|
|
|
641 |
|
|
if (!DRP_RST_N)
|
642 |
|
|
begin
|
643 |
|
|
fsm <= FSM_IDLE;
|
644 |
|
|
index <= 5'd0;
|
645 |
|
|
mode <= 1'd0;
|
646 |
|
|
done <= 1'd0;
|
647 |
|
|
end
|
648 |
|
|
else
|
649 |
|
|
begin
|
650 |
|
|
|
651 |
|
|
case (fsm)
|
652 |
|
|
|
653 |
|
|
//---------- Idle State ----------------------------
|
654 |
|
|
FSM_IDLE :
|
655 |
|
|
|
656 |
|
|
begin
|
657 |
|
|
//---------- Reset or Rate Change --------------
|
658 |
|
|
if (start_reg2)
|
659 |
|
|
begin
|
660 |
|
|
fsm <= FSM_LOAD;
|
661 |
|
|
index <= 5'd0;
|
662 |
|
|
mode <= 1'd0;
|
663 |
|
|
done <= 1'd0;
|
664 |
|
|
end
|
665 |
|
|
//---------- GTXRESET --------------------------
|
666 |
|
|
else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
|
667 |
|
|
begin
|
668 |
|
|
fsm <= FSM_LOAD;
|
669 |
|
|
index <= 5'd0;
|
670 |
|
|
mode <= 1'd1;
|
671 |
|
|
done <= 1'd0;
|
672 |
|
|
end
|
673 |
|
|
//---------- Idle ------------------------------
|
674 |
|
|
else
|
675 |
|
|
begin
|
676 |
|
|
fsm <= FSM_IDLE;
|
677 |
|
|
index <= 5'd0;
|
678 |
|
|
mode <= 1'd0;
|
679 |
|
|
done <= 1'd1;
|
680 |
|
|
end
|
681 |
|
|
end
|
682 |
|
|
|
683 |
|
|
//---------- Load DRP Address ---------------------
|
684 |
|
|
FSM_LOAD :
|
685 |
|
|
|
686 |
|
|
begin
|
687 |
|
|
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
|
688 |
|
|
index <= index;
|
689 |
|
|
mode <= mode;
|
690 |
|
|
done <= 1'd0;
|
691 |
|
|
end
|
692 |
|
|
|
693 |
|
|
//---------- Read DRP ------------------------------
|
694 |
|
|
FSM_READ :
|
695 |
|
|
|
696 |
|
|
begin
|
697 |
|
|
fsm <= FSM_RRDY;
|
698 |
|
|
index <= index;
|
699 |
|
|
mode <= mode;
|
700 |
|
|
done <= 1'd0;
|
701 |
|
|
end
|
702 |
|
|
|
703 |
|
|
//---------- Read DRP Ready ------------------------
|
704 |
|
|
FSM_RRDY :
|
705 |
|
|
|
706 |
|
|
begin
|
707 |
|
|
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
|
708 |
|
|
index <= index;
|
709 |
|
|
mode <= mode;
|
710 |
|
|
done <= 1'd0;
|
711 |
|
|
end
|
712 |
|
|
|
713 |
|
|
|
714 |
|
|
//---------- Write DRP -----------------------------
|
715 |
|
|
FSM_WRITE :
|
716 |
|
|
|
717 |
|
|
begin
|
718 |
|
|
fsm <= FSM_WRDY;
|
719 |
|
|
index <= index;
|
720 |
|
|
mode <= mode;
|
721 |
|
|
done <= 1'd0;
|
722 |
|
|
end
|
723 |
|
|
|
724 |
|
|
//---------- Write DRP Ready -----------------------
|
725 |
|
|
FSM_WRDY :
|
726 |
|
|
|
727 |
|
|
begin
|
728 |
|
|
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
|
729 |
|
|
index <= index;
|
730 |
|
|
mode <= mode;
|
731 |
|
|
done <= 1'd0;
|
732 |
|
|
end
|
733 |
|
|
|
734 |
|
|
//---------- DRP Done ------------------------------
|
735 |
|
|
FSM_DONE :
|
736 |
|
|
|
737 |
|
|
begin
|
738 |
|
|
if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
|
739 |
|
|
begin
|
740 |
|
|
fsm <= FSM_IDLE;
|
741 |
|
|
index <= 5'd0;
|
742 |
|
|
mode <= 1'd0;
|
743 |
|
|
done <= 1'd0;
|
744 |
|
|
end
|
745 |
|
|
else
|
746 |
|
|
begin
|
747 |
|
|
fsm <= FSM_LOAD;
|
748 |
|
|
index <= index + 5'd1;
|
749 |
|
|
mode <= mode;
|
750 |
|
|
done <= 1'd0;
|
751 |
|
|
end
|
752 |
|
|
end
|
753 |
|
|
|
754 |
|
|
//---------- Default State -------------------------
|
755 |
|
|
default :
|
756 |
|
|
|
757 |
|
|
begin
|
758 |
|
|
fsm <= FSM_IDLE;
|
759 |
|
|
index <= 5'd0;
|
760 |
|
|
mode <= 1'd0;
|
761 |
|
|
done <= 1'd0;
|
762 |
|
|
end
|
763 |
|
|
|
764 |
|
|
endcase
|
765 |
|
|
|
766 |
|
|
end
|
767 |
|
|
|
768 |
|
|
end
|
769 |
|
|
|
770 |
|
|
|
771 |
|
|
|
772 |
|
|
//---------- PIPE DRP Output ---------------------------------------------------
|
773 |
|
|
assign DRP_ADDR = addr_reg;
|
774 |
|
|
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
|
775 |
|
|
assign DRP_DI = di_reg;
|
776 |
|
|
assign DRP_WE = (fsm == FSM_WRITE);
|
777 |
|
|
assign DRP_DONE = done;
|
778 |
|
|
assign DRP_FSM = fsm;
|
779 |
|
|
|
780 |
|
|
|
781 |
|
|
|
782 |
|
|
endmodule
|