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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_artix7/] [cl_a7pcie_x4_pipe_sync.v] - Blame information for rev 46

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//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project    : Series-7 Integrated Block for PCI Express
// File       : cl_a7pcie_x4_pipe_sync.v
// Version    : 1.9
//------------------------------------------------------------------------------
//  Filename     :  pipe_sync.v
//  Description  :  PIPE Sync Module for 7 Series Transceiver
//  Version      :  20.1
//------------------------------------------------------------------------------
//  PCIE_TXSYNC_MODE  : 0 = Manual TX sync (default).
//                    : 1 = Auto TX sync.
//  PCIE_RXSYNC_MODE  : 0 = Manual RX sync (default).
//                    : 1 = Auto RX sync.
//------------------------------------------------------------------------------
 
 
 
`timescale 1ns / 1ps
 
 
 
//---------- PIPE Sync Module --------------------------------------------------
module cl_a7pcie_x4_pipe_sync #
(
 
    parameter PCIE_GT_DEVICE       = "GTX",                 // PCIe GT device
    parameter PCIE_TXBUF_EN        = "FALSE",               // PCIe TX buffer enable for Gen1/Gen2 only
    parameter PCIE_RXBUF_EN        = "TRUE",                // PCIe TX buffer enable for Gen3      only
    parameter PCIE_TXSYNC_MODE     = 0,                     // PCIe TX sync mode
    parameter PCIE_RXSYNC_MODE     = 0,                     // PCIe RX sync mode
    parameter PCIE_LANE            = 1,                     // PCIe lane
    parameter PCIE_LINK_SPEED      = 3,                     // PCIe link speed
    parameter BYPASS_TXDELAY_ALIGN = 0,                     // Bypass TX delay align
    parameter BYPASS_RXDELAY_ALIGN = 0                      // Bypass RX delay align
 
)
 
(
 
    //---------- Input -------------------------------------
    input               SYNC_CLK,
    input               SYNC_RST_N,
    input               SYNC_SLAVE,
    input               SYNC_GEN3,
    input               SYNC_RATE_IDLE,
    input               SYNC_MMCM_LOCK,
    input               SYNC_RXELECIDLE,
    input               SYNC_RXCDRLOCK,
    input               SYNC_ACTIVE_LANE,
 
    input               SYNC_TXSYNC_START,
    input               SYNC_TXPHINITDONE,
    input               SYNC_TXDLYSRESETDONE,
    input               SYNC_TXPHALIGNDONE,
    input               SYNC_TXSYNCDONE,
 
    input               SYNC_RXSYNC_START,
    input               SYNC_RXDLYSRESETDONE,
    input               SYNC_RXPHALIGNDONE_M,
    input               SYNC_RXPHALIGNDONE_S,
    input               SYNC_RXSYNC_DONEM_IN,
    input               SYNC_RXSYNCDONE,
 
    //---------- Output ------------------------------------
    output              SYNC_TXPHDLYRESET,
    output              SYNC_TXPHALIGN,
    output              SYNC_TXPHALIGNEN,
    output              SYNC_TXPHINIT,
    output              SYNC_TXDLYBYPASS,
    output              SYNC_TXDLYSRESET,
    output              SYNC_TXDLYEN,
    output              SYNC_TXSYNC_DONE,
    output    [ 5:0]    SYNC_FSM_TX,
 
    output              SYNC_RXPHALIGN,
    output              SYNC_RXPHALIGNEN,
    output              SYNC_RXDLYBYPASS,
    output              SYNC_RXDLYSRESET,
    output              SYNC_RXDLYEN,
    output              SYNC_RXDDIEN,
    output              SYNC_RXSYNC_DONEM_OUT,
    output              SYNC_RXSYNC_DONE,
    output    [ 6:0]    SYNC_FSM_RX
 
);
 
    //---------- Input Register ----------------------------
    reg                 gen3_reg1;
    reg                 rate_idle_reg1;
    reg                             mmcm_lock_reg1;
    reg                 rxelecidle_reg1;
    reg                 rxcdrlock_reg1;
 
    reg                 gen3_reg2;
    reg                 rate_idle_reg2;
    reg                                   mmcm_lock_reg2;
    reg                 rxelecidle_reg2;
    reg                 rxcdrlock_reg2;
 
    reg                                         txsync_start_reg1;
    reg                 txphinitdone_reg1;
    reg                 txdlysresetdone_reg1;
    reg                 txphaligndone_reg1;
    reg                 txsyncdone_reg1;
 
    reg                 txsync_start_reg2;
    reg                 txphinitdone_reg2;
    reg                 txdlysresetdone_reg2;
    reg                 txphaligndone_reg2;
    reg                 txsyncdone_reg2;
 
    reg                                         rxsync_start_reg1;
    reg                 rxdlysresetdone_reg1;
    reg                 rxphaligndone_m_reg1;
    reg                 rxphaligndone_s_reg1;
    reg                 rxsync_donem_reg1;
    reg                 rxsyncdone_reg1;
 
    reg                                         rxsync_start_reg2;
    reg                 rxdlysresetdone_reg2;
    reg                 rxphaligndone_m_reg2;
    reg                 rxphaligndone_s_reg2;
    reg                 rxsync_donem_reg2;
    reg                 rxsyncdone_reg2;
 
    //---------- Output Register ---------------------------          
    reg                 txdlyen     = 1'd0;
    reg                 txsync_done = 1'd0;
    reg         [ 5:0]  fsm_tx      = 6'd0;
 
    reg                 rxdlyen     = 1'd0;
    reg                 rxsync_done = 1'd0;
    reg         [ 6:0]  fsm_rx      = 7'd0;
 
    //---------- FSM ---------------------------------------                                         
    localparam          FSM_TXSYNC_IDLE  = 6'b000001;
    localparam          FSM_MMCM_LOCK    = 6'b000010;
    localparam          FSM_TXSYNC_START = 6'b000100;
    localparam          FSM_TXPHINITDONE = 6'b001000;       // Manual TX sync only
    localparam          FSM_TXSYNC_DONE1 = 6'b010000;
    localparam          FSM_TXSYNC_DONE2 = 6'b100000;
 
    localparam          FSM_RXSYNC_IDLE  = 7'b0000001;
    localparam          FSM_RXCDRLOCK    = 7'b0000010;
    localparam          FSM_RXSYNC_START = 7'b0000100;
    localparam          FSM_RXSYNC_DONE1 = 7'b0001000;
    localparam          FSM_RXSYNC_DONE2 = 7'b0010000;
    localparam          FSM_RXSYNC_DONES = 7'b0100000;
    localparam          FSM_RXSYNC_DONEM = 7'b1000000;
 
 
 
//---------- Input FF ----------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
 
    if (!SYNC_RST_N)
        begin
        //---------- 1st Stage FF --------------------------  
        gen3_reg1            <= 1'd0;
        rate_idle_reg1       <= 1'd0;
        mmcm_lock_reg1       <= 1'd0;
        rxelecidle_reg1      <= 1'd0;
        rxcdrlock_reg1       <= 1'd0;
 
        txsync_start_reg1          <= 1'd0;
        txphinitdone_reg1    <= 1'd0;
        txdlysresetdone_reg1 <= 1'd0;
        txphaligndone_reg1   <= 1'd0;
        txsyncdone_reg1      <= 1'd0;
 
        rxsync_start_reg1          <= 1'd0;
        rxdlysresetdone_reg1 <= 1'd0;
        rxphaligndone_m_reg1 <= 1'd0;
        rxphaligndone_s_reg1 <= 1'd0;
        rxsync_donem_reg1    <= 1'd0;
        rxsyncdone_reg1      <= 1'd0;
        //---------- 2nd Stage FF --------------------------
        gen3_reg2            <= 1'd0;
        rate_idle_reg2       <= 1'd0;
        mmcm_lock_reg2       <= 1'd0;
        rxelecidle_reg2      <= 1'd0;
        rxcdrlock_reg2       <= 1'd0;
 
        txsync_start_reg2          <= 1'd0;
        txphinitdone_reg2    <= 1'd0;
        txdlysresetdone_reg2 <= 1'd0;
        txphaligndone_reg2   <= 1'd0;
        txsyncdone_reg2      <= 1'd0;
 
        rxsync_start_reg2          <= 1'd0;
        rxdlysresetdone_reg2 <= 1'd0;
        rxphaligndone_m_reg2 <= 1'd0;
        rxphaligndone_s_reg2 <= 1'd0;
        rxsync_donem_reg2    <= 1'd0;
        rxsyncdone_reg2      <= 1'd0;
        end
    else
        begin
        //---------- 1st Stage FF --------------------------
        gen3_reg1            <= SYNC_GEN3;
        rate_idle_reg1       <= SYNC_RATE_IDLE;
        mmcm_lock_reg1       <= SYNC_MMCM_LOCK;
        rxelecidle_reg1      <= SYNC_RXELECIDLE;
        rxcdrlock_reg1       <= SYNC_RXCDRLOCK;
 
        txsync_start_reg1    <= SYNC_TXSYNC_START;
        txphinitdone_reg1    <= SYNC_TXPHINITDONE;
        txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
        txphaligndone_reg1   <= SYNC_TXPHALIGNDONE;
        txsyncdone_reg1      <= SYNC_TXSYNCDONE;
 
        rxsync_start_reg1          <= SYNC_RXSYNC_START;
        rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
        rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
        rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
        rxsync_donem_reg1    <= SYNC_RXSYNC_DONEM_IN;
        rxsyncdone_reg1      <= SYNC_RXSYNCDONE;
        //---------- 2nd Stage FF --------------------------
        gen3_reg2            <= gen3_reg1;
        rate_idle_reg2       <= rate_idle_reg1;
        mmcm_lock_reg2       <= mmcm_lock_reg1;
        rxelecidle_reg2      <= rxelecidle_reg1;
        rxcdrlock_reg2       <= rxcdrlock_reg1;
 
        txsync_start_reg2    <= txsync_start_reg1;
        txphinitdone_reg2    <= txphinitdone_reg1;
        txdlysresetdone_reg2 <= txdlysresetdone_reg1;
        txphaligndone_reg2   <= txphaligndone_reg1;
        txsyncdone_reg2      <= txsyncdone_reg1;
 
        rxsync_start_reg2    <= rxsync_start_reg1;
        rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
        rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
        rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
        rxsync_donem_reg2    <= rxsync_donem_reg1;
        rxsyncdone_reg2      <= rxsyncdone_reg1;
        end
 
end
 
 
 
//---------- Generate TX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
 
    begin : txsync_fsm
 
    //---------- PIPE TX Sync FSM ----------------------------------------------
    always @ (posedge SYNC_CLK)
    begin
 
        if (!SYNC_RST_N)
            begin
            fsm_tx      <= FSM_TXSYNC_IDLE;
            txdlyen     <= 1'd0;
            txsync_done <= 1'd0;
            end
        else
            begin
 
            case (fsm_tx)
 
            //---------- Idle State ------------------------
            FSM_TXSYNC_IDLE :
 
                begin
                //---------- Exiting Reset or Rate Change --
                if (txsync_start_reg2)
                    begin
                    fsm_tx      <= FSM_MMCM_LOCK;
                    txdlyen     <= 1'd0;
                    txsync_done <= 1'd0;
                    end
                else
                    begin
                    fsm_tx      <= FSM_TXSYNC_IDLE;
                    txdlyen     <= txdlyen;
                    txsync_done <= txsync_done;
                    end
                end
 
            //---------- Check MMCM Lock -------------------
            FSM_MMCM_LOCK :
 
                begin
                fsm_tx      <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
                txdlyen     <= 1'd0;
                txsync_done <= 1'd0;
                end
 
            //---------- TX Delay Soft Reset --------------- 
            FSM_TXSYNC_START :
 
                begin
                fsm_tx      <= (((!txdlysresetdone_reg2 && txdlysresetdone_reg1) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
                txdlyen     <= 1'd0;
                txsync_done <= 1'd0;
                end
 
            //---------- Wait for TX Phase Init Done (Manual Mode Only)
            FSM_TXPHINITDONE :
 
                begin
                fsm_tx      <= (((!txphinitdone_reg2 && txphinitdone_reg1) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
                txdlyen     <= 1'd0;
                txsync_done <= 1'd0;
                end
 
            //---------- Wait for TX Phase Alignment Done --
            FSM_TXSYNC_DONE1 :
 
                begin
                if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
                   fsm_tx <= ((!txsyncdone_reg2 && txsyncdone_reg1)       || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
                else
                   fsm_tx <= ((!txphaligndone_reg2 && txphaligndone_reg1) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
 
                txdlyen     <= 1'd0;
                txsync_done <= 1'd0;
                end
 
            //---------- Wait for Master TX Delay Alignment Done 
            FSM_TXSYNC_DONE2 :
 
                begin
                if ((!txphaligndone_reg2 && txphaligndone_reg1) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
                    begin
                    fsm_tx      <= FSM_TXSYNC_IDLE;
                    txdlyen     <= !SYNC_SLAVE;
                    txsync_done <= 1'd1;
                    end
                else
                    begin
                    fsm_tx      <= FSM_TXSYNC_DONE2;
                    txdlyen     <= !SYNC_SLAVE;
                    txsync_done <= 1'd0;
                    end
                end
 
            //---------- Default State ---------------------
            default :
                begin
                fsm_tx      <= FSM_TXSYNC_IDLE;
                txdlyen     <= 1'd0;
                txsync_done <= 1'd0;
                end
 
            endcase
 
            end
 
    end
 
    end
 
//---------- TX Sync FSM Default------------------------------------------------
else
 
    begin : txsync_fsm_disable
 
    //---------- Default -------------------------------------------------------
    always @ (posedge SYNC_CLK)
    begin
        fsm_tx      <= FSM_TXSYNC_IDLE;
        txdlyen     <= 1'd0;
        txsync_done <= 1'd0;
    end
 
    end
 
endgenerate
 
 
 
//---------- Generate RX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
 
    begin : rxsync_fsm
 
    //---------- PIPE RX Sync FSM ----------------------------------------------
    always @ (posedge SYNC_CLK)
    begin
 
        if (!SYNC_RST_N)
            begin
            fsm_rx      <= FSM_RXSYNC_IDLE;
            rxdlyen     <= 1'd0;
            rxsync_done <= 1'd0;
            end
        else
            begin
 
            case (fsm_rx)
 
            //---------- Idle State ------------------------
            FSM_RXSYNC_IDLE :
 
                begin
                //---------- Exiting Rate Change -----------
                if (rxsync_start_reg2)
                    begin
                    fsm_rx      <= FSM_RXCDRLOCK;
                    rxdlyen     <= 1'd0;
                    rxsync_done <= 1'd0;
                    end
                //---------- Exiting Electrical Idle without Rate Change 
                else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
                    begin
                    fsm_rx      <= FSM_RXCDRLOCK;
                    rxdlyen     <= 1'd0;
                    rxsync_done <= 1'd0;
                    end
                //---------- Idle --------------------------
                else
                    begin
                    fsm_rx      <= FSM_RXSYNC_IDLE;
                    rxdlyen     <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
                    rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
                    end
                end
 
            //---------- Wait for RX Electrical Idle Exit and RX CDR Lock 
            FSM_RXCDRLOCK :
 
                begin
                fsm_rx      <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
                rxdlyen     <= 1'd0;
                rxsync_done <= 1'd0;
                end
 
            //---------- Start RX Sync with RX Delay Soft Reset
            FSM_RXSYNC_START :
 
                begin
                fsm_rx      <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
                rxdlyen     <= 1'd0;
                rxsync_done <= 1'd0;
                end
 
            //---------- Wait for RX Phase Alignment Done --
            FSM_RXSYNC_DONE1 :
 
                begin
                if (SYNC_SLAVE)
                    begin
                    fsm_rx      <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
                    rxdlyen     <= 1'd0;
                    rxsync_done <= 1'd0;
                    end
                else
                    begin
                    fsm_rx      <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
                    rxdlyen     <= 1'd0;
                    rxsync_done <= 1'd0;
                    end
                end
 
            //---------- Wait for Master RX Delay Alignment Done 
            FSM_RXSYNC_DONE2 :
 
                begin
                if (SYNC_SLAVE)
                    begin
                    fsm_rx      <= FSM_RXSYNC_IDLE;
                    rxdlyen     <= 1'd0;
                    rxsync_done <= 1'd1;
                    end
                else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
                    begin
                    fsm_rx      <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
                    rxdlyen     <=  (PCIE_LANE == 1);
                    rxsync_done <=  (PCIE_LANE == 1);
                    end
                else
                    begin
                    fsm_rx      <= FSM_RXSYNC_DONE2;
                    rxdlyen     <= 1'd1;
                    rxsync_done <= 1'd0;
                    end
                end
 
            //---------- Wait for Slave RX Phase Alignment Done 
            FSM_RXSYNC_DONES :
 
                begin
                if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
                    begin
                    fsm_rx      <= FSM_RXSYNC_DONEM;
                    rxdlyen     <= 1'd1;
                    rxsync_done <= 1'd0;
                    end
                else
                    begin
                    fsm_rx      <= FSM_RXSYNC_DONES;
                    rxdlyen     <= 1'd0;
                    rxsync_done <= 1'd0;
                    end
                end
 
            //---------- Wait for Master RX Delay Alignment Done 
            FSM_RXSYNC_DONEM :
 
                begin
                if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
                    begin
                    fsm_rx      <= FSM_RXSYNC_IDLE;
                    rxdlyen     <= 1'd1;
                    rxsync_done <= 1'd1;
                    end
                else
                    begin
                    fsm_rx      <= FSM_RXSYNC_DONEM;
                    rxdlyen     <= 1'd1;
                    rxsync_done <= 1'd0;
                    end
                end
 
            //---------- Default State ---------------------
            default :
                begin
                fsm_rx      <= FSM_RXSYNC_IDLE;
                rxdlyen     <= 1'd0;
                rxsync_done <= 1'd0;
                end
 
                   endcase
 
            end
 
    end
 
    end
 
//---------- RX Sync FSM Default -----------------------------------------------
else
 
    begin : rxsync_fsm_disable
 
    //---------- Default -------------------------------------------------------
    always @ (posedge SYNC_CLK)
    begin
        fsm_rx      <= FSM_RXSYNC_IDLE;
        rxdlyen     <= 1'd0;
        rxsync_done <= 1'd0;
    end
 
    end
 
endgenerate
 
 
 
//---------- PIPE Sync Output --------------------------------------------------            
assign SYNC_TXPHALIGNEN      = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
assign SYNC_TXDLYBYPASS      = 1'd0;
//assign SYNC_TXDLYSRESET    = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0; 
assign SYNC_TXDLYSRESET      = (fsm_tx == FSM_TXSYNC_START);
assign SYNC_TXPHDLYRESET     =  (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHINIT         = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
assign SYNC_TXPHALIGN        = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
assign SYNC_TXDLYEN          = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
assign SYNC_TXSYNC_DONE      = txsync_done;
assign SYNC_FSM_TX           = fsm_tx;
 
assign SYNC_RXPHALIGNEN      = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
assign SYNC_RXDLYBYPASS      = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
assign SYNC_RXDLYSRESET      = (fsm_rx == FSM_RXSYNC_START);
assign SYNC_RXPHALIGN        = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
assign SYNC_RXDLYEN          = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
assign SYNC_RXDDIEN          = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
assign SYNC_RXSYNC_DONE      = rxsync_done;
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
assign SYNC_FSM_RX               = fsm_rx;
 
 
 
endmodule

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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_artix7/] [cl_a7pcie_x4_pipe_sync.v] - Blame information for rev 46

Line No.	Rev	Author	Line
1	46	dsmv	`//-----------------------------------------------------------------------------`
2			`//`
3			`// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.`
4			`//`
5			`// This file contains confidential and proprietary information`
6			`// of Xilinx, Inc. and is protected under U.S. and`
7			`// international copyright and other intellectual property`
8			`// laws.`
9			`//`
10			`// DISCLAIMER`
11			`// This disclaimer is not a license and does not grant any`
12			`// rights to the materials distributed herewith. Except as`
13			`// otherwise provided in a valid license issued to you by`
14			`// Xilinx, and to the maximum extent permitted by applicable`
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48			`//`
49			`//-----------------------------------------------------------------------------`
50			`// Project : Series-7 Integrated Block for PCI Express`
51			`// File : cl_a7pcie_x4_pipe_sync.v`
52			`// Version : 1.9`
53			`//------------------------------------------------------------------------------`
54			`// Filename : pipe_sync.v`
55			`// Description : PIPE Sync Module for 7 Series Transceiver`
56			`// Version : 20.1`
57			`//------------------------------------------------------------------------------`
58			`// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).`
59			`// : 1 = Auto TX sync.`
60			`// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).`
61			`// : 1 = Auto RX sync.`
62			`//------------------------------------------------------------------------------`
63
64
65
66			`timescale 1ns / 1ps
67
68
69
70			`//---------- PIPE Sync Module --------------------------------------------------`
71			`module cl_a7pcie_x4_pipe_sync #`
72			`(`
73
74			`parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device`
75			`parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only`
76			`parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only`
77			`parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode`
78			`parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode`
79			`parameter PCIE_LANE = 1, // PCIe lane`
80			`parameter PCIE_LINK_SPEED = 3, // PCIe link speed`
81			`parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align`
82			`parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align`
83
84			`)`
85
86			`(`
87
88			`//---------- Input -------------------------------------`
89			`input SYNC_CLK,`
90			`input SYNC_RST_N,`
91			`input SYNC_SLAVE,`
92			`input SYNC_GEN3,`
93			`input SYNC_RATE_IDLE,`
94			`input SYNC_MMCM_LOCK,`
95			`input SYNC_RXELECIDLE,`
96			`input SYNC_RXCDRLOCK,`
97			`input SYNC_ACTIVE_LANE,`
98
99			`input SYNC_TXSYNC_START,`
100			`input SYNC_TXPHINITDONE,`
101			`input SYNC_TXDLYSRESETDONE,`
102			`input SYNC_TXPHALIGNDONE,`
103			`input SYNC_TXSYNCDONE,`
104
105			`input SYNC_RXSYNC_START,`
106			`input SYNC_RXDLYSRESETDONE,`
107			`input SYNC_RXPHALIGNDONE_M,`
108			`input SYNC_RXPHALIGNDONE_S,`
109			`input SYNC_RXSYNC_DONEM_IN,`
110			`input SYNC_RXSYNCDONE,`
111
112			`//---------- Output ------------------------------------`
113			`output SYNC_TXPHDLYRESET,`
114			`output SYNC_TXPHALIGN,`
115			`output SYNC_TXPHALIGNEN,`
116			`output SYNC_TXPHINIT,`
117			`output SYNC_TXDLYBYPASS,`
118			`output SYNC_TXDLYSRESET,`
119			`output SYNC_TXDLYEN,`
120			`output SYNC_TXSYNC_DONE,`
121			`output [ 5:0] SYNC_FSM_TX,`
122
123			`output SYNC_RXPHALIGN,`
124			`output SYNC_RXPHALIGNEN,`
125			`output SYNC_RXDLYBYPASS,`
126			`output SYNC_RXDLYSRESET,`
127			`output SYNC_RXDLYEN,`
128			`output SYNC_RXDDIEN,`
129			`output SYNC_RXSYNC_DONEM_OUT,`
130			`output SYNC_RXSYNC_DONE,`
131			`output [ 6:0] SYNC_FSM_RX`
132
133			`);`
134
135			`//---------- Input Register ----------------------------`
136			`reg gen3_reg1;`
137			`reg rate_idle_reg1;`
138			`reg mmcm_lock_reg1;`
139			`reg rxelecidle_reg1;`
140			`reg rxcdrlock_reg1;`
141
142			`reg gen3_reg2;`
143			`reg rate_idle_reg2;`
144			`reg mmcm_lock_reg2;`
145			`reg rxelecidle_reg2;`
146			`reg rxcdrlock_reg2;`
147
148			`reg txsync_start_reg1;`
149			`reg txphinitdone_reg1;`
150			`reg txdlysresetdone_reg1;`
151			`reg txphaligndone_reg1;`
152			`reg txsyncdone_reg1;`
153
154			`reg txsync_start_reg2;`
155			`reg txphinitdone_reg2;`
156			`reg txdlysresetdone_reg2;`
157			`reg txphaligndone_reg2;`
158			`reg txsyncdone_reg2;`
159
160			`reg rxsync_start_reg1;`
161			`reg rxdlysresetdone_reg1;`
162			`reg rxphaligndone_m_reg1;`
163			`reg rxphaligndone_s_reg1;`
164			`reg rxsync_donem_reg1;`
165			`reg rxsyncdone_reg1;`
166
167			`reg rxsync_start_reg2;`
168			`reg rxdlysresetdone_reg2;`
169			`reg rxphaligndone_m_reg2;`
170			`reg rxphaligndone_s_reg2;`
171			`reg rxsync_donem_reg2;`
172			`reg rxsyncdone_reg2;`
173
174			`//---------- Output Register ---------------------------`
175			`reg txdlyen = 1'd0;`
176			`reg txsync_done = 1'd0;`
177			`reg [ 5:0] fsm_tx = 6'd0;`
178
179			`reg rxdlyen = 1'd0;`
180			`reg rxsync_done = 1'd0;`
181			`reg [ 6:0] fsm_rx = 7'd0;`
182
183			`//---------- FSM ---------------------------------------`
184			`localparam FSM_TXSYNC_IDLE = 6'b000001;`
185			`localparam FSM_MMCM_LOCK = 6'b000010;`
186			`localparam FSM_TXSYNC_START = 6'b000100;`
187			`localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only`
188			`localparam FSM_TXSYNC_DONE1 = 6'b010000;`
189			`localparam FSM_TXSYNC_DONE2 = 6'b100000;`
190
191			`localparam FSM_RXSYNC_IDLE = 7'b0000001;`
192			`localparam FSM_RXCDRLOCK = 7'b0000010;`
193			`localparam FSM_RXSYNC_START = 7'b0000100;`
194			`localparam FSM_RXSYNC_DONE1 = 7'b0001000;`
195			`localparam FSM_RXSYNC_DONE2 = 7'b0010000;`
196			`localparam FSM_RXSYNC_DONES = 7'b0100000;`
197			`localparam FSM_RXSYNC_DONEM = 7'b1000000;`
198
199
200
201			`//---------- Input FF ----------------------------------------------------------`
202			`always @ (posedge SYNC_CLK)`
203			`begin`
204
205			`if (!SYNC_RST_N)`
206			`begin`
207			`//---------- 1st Stage FF --------------------------`
208			`gen3_reg1 <= 1'd0;`
209			`rate_idle_reg1 <= 1'd0;`
210			`mmcm_lock_reg1 <= 1'd0;`
211			`rxelecidle_reg1 <= 1'd0;`
212			`rxcdrlock_reg1 <= 1'd0;`
213
214			`txsync_start_reg1 <= 1'd0;`
215			`txphinitdone_reg1 <= 1'd0;`
216			`txdlysresetdone_reg1 <= 1'd0;`
217			`txphaligndone_reg1 <= 1'd0;`
218			`txsyncdone_reg1 <= 1'd0;`
219
220			`rxsync_start_reg1 <= 1'd0;`
221			`rxdlysresetdone_reg1 <= 1'd0;`
222			`rxphaligndone_m_reg1 <= 1'd0;`
223			`rxphaligndone_s_reg1 <= 1'd0;`
224			`rxsync_donem_reg1 <= 1'd0;`
225			`rxsyncdone_reg1 <= 1'd0;`
226			`//---------- 2nd Stage FF --------------------------`
227			`gen3_reg2 <= 1'd0;`
228			`rate_idle_reg2 <= 1'd0;`
229			`mmcm_lock_reg2 <= 1'd0;`
230			`rxelecidle_reg2 <= 1'd0;`
231			`rxcdrlock_reg2 <= 1'd0;`
232
233			`txsync_start_reg2 <= 1'd0;`
234			`txphinitdone_reg2 <= 1'd0;`
235			`txdlysresetdone_reg2 <= 1'd0;`
236			`txphaligndone_reg2 <= 1'd0;`
237			`txsyncdone_reg2 <= 1'd0;`
238
239			`rxsync_start_reg2 <= 1'd0;`
240			`rxdlysresetdone_reg2 <= 1'd0;`
241			`rxphaligndone_m_reg2 <= 1'd0;`
242			`rxphaligndone_s_reg2 <= 1'd0;`
243			`rxsync_donem_reg2 <= 1'd0;`
244			`rxsyncdone_reg2 <= 1'd0;`
245			`end`
246			`else`
247			`begin`
248			`//---------- 1st Stage FF --------------------------`
249			`gen3_reg1 <= SYNC_GEN3;`
250			`rate_idle_reg1 <= SYNC_RATE_IDLE;`
251			`mmcm_lock_reg1 <= SYNC_MMCM_LOCK;`
252			`rxelecidle_reg1 <= SYNC_RXELECIDLE;`
253			`rxcdrlock_reg1 <= SYNC_RXCDRLOCK;`
254
255			`txsync_start_reg1 <= SYNC_TXSYNC_START;`
256			`txphinitdone_reg1 <= SYNC_TXPHINITDONE;`
257			`txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;`
258			`txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;`
259			`txsyncdone_reg1 <= SYNC_TXSYNCDONE;`
260
261			`rxsync_start_reg1 <= SYNC_RXSYNC_START;`
262			`rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;`
263			`rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;`
264			`rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;`
265			`rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;`
266			`rxsyncdone_reg1 <= SYNC_RXSYNCDONE;`
267			`//---------- 2nd Stage FF --------------------------`
268			`gen3_reg2 <= gen3_reg1;`
269			`rate_idle_reg2 <= rate_idle_reg1;`
270			`mmcm_lock_reg2 <= mmcm_lock_reg1;`
271			`rxelecidle_reg2 <= rxelecidle_reg1;`
272			`rxcdrlock_reg2 <= rxcdrlock_reg1;`
273
274			`txsync_start_reg2 <= txsync_start_reg1;`
275			`txphinitdone_reg2 <= txphinitdone_reg1;`
276			`txdlysresetdone_reg2 <= txdlysresetdone_reg1;`
277			`txphaligndone_reg2 <= txphaligndone_reg1;`
278			`txsyncdone_reg2 <= txsyncdone_reg1;`
279
280			`rxsync_start_reg2 <= rxsync_start_reg1;`
281			`rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;`
282			`rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;`
283			`rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;`
284			`rxsync_donem_reg2 <= rxsync_donem_reg1;`
285			`rxsyncdone_reg2 <= rxsyncdone_reg1;`
286			`end`
287
288			`end`
289
290
291
292			`//---------- Generate TX Sync FSM ----------------------------------------------`
293			`generate if ((PCIE_LINK_SPEED == 3) \|\| (PCIE_TXBUF_EN == "FALSE"))`
294
295			`begin : txsync_fsm`
296
297			`//---------- PIPE TX Sync FSM ----------------------------------------------`
298			`always @ (posedge SYNC_CLK)`
299			`begin`
300
301			`if (!SYNC_RST_N)`
302			`begin`
303			`fsm_tx <= FSM_TXSYNC_IDLE;`
304			`txdlyen <= 1'd0;`
305			`txsync_done <= 1'd0;`
306			`end`
307			`else`
308			`begin`
309
310			`case (fsm_tx)`
311
312			`//---------- Idle State ------------------------`
313			`FSM_TXSYNC_IDLE :`
314
315			`begin`
316			`//---------- Exiting Reset or Rate Change --`
317			`if (txsync_start_reg2)`
318			`begin`
319			`fsm_tx <= FSM_MMCM_LOCK;`
320			`txdlyen <= 1'd0;`
321			`txsync_done <= 1'd0;`
322			`end`
323			`else`
324			`begin`
325			`fsm_tx <= FSM_TXSYNC_IDLE;`
326			`txdlyen <= txdlyen;`
327			`txsync_done <= txsync_done;`
328			`end`
329			`end`
330
331			`//---------- Check MMCM Lock -------------------`
332			`FSM_MMCM_LOCK :`
333
334			`begin`
335			`fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);`
336			`txdlyen <= 1'd0;`
337			`txsync_done <= 1'd0;`
338			`end`
339
340			`//---------- TX Delay Soft Reset ---------------`
341			`FSM_TXSYNC_START :`
342
343			`begin`
344			`fsm_tx <= (((!txdlysresetdone_reg2 && txdlysresetdone_reg1) \|\| (((PCIE_GT_DEVICE == "GTH") \|\| (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);`
345			`txdlyen <= 1'd0;`
346			`txsync_done <= 1'd0;`
347			`end`
348
349			`//---------- Wait for TX Phase Init Done (Manual Mode Only)`
350			`FSM_TXPHINITDONE :`
351
352			`begin`
353			`fsm_tx <= (((!txphinitdone_reg2 && txphinitdone_reg1) \|\| (PCIE_TXSYNC_MODE == 1) \|\| (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);`
354			`txdlyen <= 1'd0;`
355			`txsync_done <= 1'd0;`
356			`end`
357
358			`//---------- Wait for TX Phase Alignment Done --`
359			`FSM_TXSYNC_DONE1 :`
360
361			`begin`
362			`if (((PCIE_GT_DEVICE == "GTH") \|\| (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)`
363			`fsm_tx <= ((!txsyncdone_reg2 && txsyncdone_reg1) \|\| (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);`
364			`else`
365			`fsm_tx <= ((!txphaligndone_reg2 && txphaligndone_reg1) \|\| (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);`
366
367			`txdlyen <= 1'd0;`
368			`txsync_done <= 1'd0;`
369			`end`
370
371			`//---------- Wait for Master TX Delay Alignment Done`
372			`FSM_TXSYNC_DONE2 :`
373
374			`begin`
375			`if ((!txphaligndone_reg2 && txphaligndone_reg1) \|\| (!SYNC_ACTIVE_LANE) \|\| SYNC_SLAVE \|\| (((PCIE_GT_DEVICE == "GTH") \|\| (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) \|\| (BYPASS_TXDELAY_ALIGN == 1))`
376			`begin`
377			`fsm_tx <= FSM_TXSYNC_IDLE;`
378			`txdlyen <= !SYNC_SLAVE;`
379			`txsync_done <= 1'd1;`
380			`end`
381			`else`
382			`begin`
383			`fsm_tx <= FSM_TXSYNC_DONE2;`
384			`txdlyen <= !SYNC_SLAVE;`
385			`txsync_done <= 1'd0;`
386			`end`
387			`end`
388
389			`//---------- Default State ---------------------`
390			`default :`
391			`begin`
392			`fsm_tx <= FSM_TXSYNC_IDLE;`
393			`txdlyen <= 1'd0;`
394			`txsync_done <= 1'd0;`
395			`end`
396
397			`endcase`
398
399			`end`
400
401			`end`
402
403			`end`
404
405			`//---------- TX Sync FSM Default------------------------------------------------`
406			`else`
407
408			`begin : txsync_fsm_disable`
409
410			`//---------- Default -------------------------------------------------------`
411			`always @ (posedge SYNC_CLK)`
412			`begin`
413			`fsm_tx <= FSM_TXSYNC_IDLE;`
414			`txdlyen <= 1'd0;`
415			`txsync_done <= 1'd0;`
416			`end`
417
418			`end`
419
420			`endgenerate`
421
422
423
424			`//---------- Generate RX Sync FSM ----------------------------------------------`
425			`generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))`
426
427			`begin : rxsync_fsm`
428
429			`//---------- PIPE RX Sync FSM ----------------------------------------------`
430			`always @ (posedge SYNC_CLK)`
431			`begin`
432
433			`if (!SYNC_RST_N)`
434			`begin`
435			`fsm_rx <= FSM_RXSYNC_IDLE;`
436			`rxdlyen <= 1'd0;`
437			`rxsync_done <= 1'd0;`
438			`end`
439			`else`
440			`begin`
441
442			`case (fsm_rx)`
443
444			`//---------- Idle State ------------------------`
445			`FSM_RXSYNC_IDLE :`
446
447			`begin`
448			`//---------- Exiting Rate Change -----------`
449			`if (rxsync_start_reg2)`
450			`begin`
451			`fsm_rx <= FSM_RXCDRLOCK;`
452			`rxdlyen <= 1'd0;`
453			`rxsync_done <= 1'd0;`
454			`end`
455			`//---------- Exiting Electrical Idle without Rate Change`
456			`else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))`
457			`begin`
458			`fsm_rx <= FSM_RXCDRLOCK;`
459			`rxdlyen <= 1'd0;`
460			`rxsync_done <= 1'd0;`
461			`end`
462			`//---------- Idle --------------------------`
463			`else`
464			`begin`
465			`fsm_rx <= FSM_RXSYNC_IDLE;`
466			`rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;`
467			`rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;`
468			`end`
469			`end`
470
471			`//---------- Wait for RX Electrical Idle Exit and RX CDR Lock`
472			`FSM_RXCDRLOCK :`
473
474			`begin`
475			`fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);`
476			`rxdlyen <= 1'd0;`
477			`rxsync_done <= 1'd0;`
478			`end`
479
480			`//---------- Start RX Sync with RX Delay Soft Reset`
481			`FSM_RXSYNC_START :`
482
483			`begin`
484			`fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);`
485			`rxdlyen <= 1'd0;`
486			`rxsync_done <= 1'd0;`
487			`end`
488
489			`//---------- Wait for RX Phase Alignment Done --`
490			`FSM_RXSYNC_DONE1 :`
491
492			`begin`
493			`if (SYNC_SLAVE)`
494			`begin`
495			`fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);`
496			`rxdlyen <= 1'd0;`
497			`rxsync_done <= 1'd0;`
498			`end`
499			`else`
500			`begin`
501			`fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);`
502			`rxdlyen <= 1'd0;`
503			`rxsync_done <= 1'd0;`
504			`end`
505			`end`
506
507			`//---------- Wait for Master RX Delay Alignment Done`
508			`FSM_RXSYNC_DONE2 :`
509
510			`begin`
511			`if (SYNC_SLAVE)`
512			`begin`
513			`fsm_rx <= FSM_RXSYNC_IDLE;`
514			`rxdlyen <= 1'd0;`
515			`rxsync_done <= 1'd1;`
516			`end`
517			`else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) \|\| (BYPASS_RXDELAY_ALIGN == 1))`
518			`begin`
519			`fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);`
520			`rxdlyen <= (PCIE_LANE == 1);`
521			`rxsync_done <= (PCIE_LANE == 1);`
522			`end`
523			`else`
524			`begin`
525			`fsm_rx <= FSM_RXSYNC_DONE2;`
526			`rxdlyen <= 1'd1;`
527			`rxsync_done <= 1'd0;`
528			`end`
529			`end`
530
531			`//---------- Wait for Slave RX Phase Alignment Done`
532			`FSM_RXSYNC_DONES :`
533
534			`begin`
535			`if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)`
536			`begin`
537			`fsm_rx <= FSM_RXSYNC_DONEM;`
538			`rxdlyen <= 1'd1;`
539			`rxsync_done <= 1'd0;`
540			`end`
541			`else`
542			`begin`
543			`fsm_rx <= FSM_RXSYNC_DONES;`
544			`rxdlyen <= 1'd0;`
545			`rxsync_done <= 1'd0;`
546			`end`
547			`end`
548
549			`//---------- Wait for Master RX Delay Alignment Done`
550			`FSM_RXSYNC_DONEM :`
551
552			`begin`
553			`if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) \|\| (BYPASS_RXDELAY_ALIGN == 1))`
554			`begin`
555			`fsm_rx <= FSM_RXSYNC_IDLE;`
556			`rxdlyen <= 1'd1;`
557			`rxsync_done <= 1'd1;`
558			`end`
559			`else`
560			`begin`
561			`fsm_rx <= FSM_RXSYNC_DONEM;`
562			`rxdlyen <= 1'd1;`
563			`rxsync_done <= 1'd0;`
564			`end`
565			`end`
566
567			`//---------- Default State ---------------------`
568			`default :`
569			`begin`
570			`fsm_rx <= FSM_RXSYNC_IDLE;`
571			`rxdlyen <= 1'd0;`
572			`rxsync_done <= 1'd0;`
573			`end`
574
575			`endcase`
576
577			`end`
578
579			`end`
580
581			`end`
582
583			`//---------- RX Sync FSM Default -----------------------------------------------`
584			`else`
585
586			`begin : rxsync_fsm_disable`
587
588			`//---------- Default -------------------------------------------------------`
589			`always @ (posedge SYNC_CLK)`
590			`begin`
591			`fsm_rx <= FSM_RXSYNC_IDLE;`
592			`rxdlyen <= 1'd0;`
593			`rxsync_done <= 1'd0;`
594			`end`
595
596			`end`
597
598			`endgenerate`
599
600
601
602			`//---------- PIPE Sync Output --------------------------------------------------`
603			`assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) \|\| (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;`
604			`assign SYNC_TXDLYBYPASS = 1'd0;`
605			`//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") \|\| (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;`
606			`assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);`
607			`assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") \|\| (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;`
608			`assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);`
609			`assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);`
610			`assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;`
611			`assign SYNC_TXSYNC_DONE = txsync_done;`
612			`assign SYNC_FSM_TX = fsm_tx;`
613
614			`assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) \|\| (!gen3_reg2) \|\| (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;`
615			`assign SYNC_RXDLYBYPASS = !gen3_reg2 \|\| (PCIE_RXBUF_EN == "TRUE");`
616			`assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);`
617			`assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));`
618			`assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;`
619			`assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");`
620			`assign SYNC_RXSYNC_DONE = rxsync_done;`
621			`assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);`
622			`assign SYNC_FSM_RX = fsm_rx;`
623
624
625
626			`endmodule`