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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_user.v
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dsmv |
// Version : 1.10
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dsmv |
//------------------------------------------------------------------------------
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// Filename : pipe_user.v
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// Description : PIPE User Module for 7 Series Transceiver
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// Version : 15.3.3
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- PIPE User Module --------------------------------------------------
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module cl_a7pcie_x4_pipe_user #
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(
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_USE_MODE = "3.0", // PCIe sim version
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parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
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parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
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parameter RXVALID_MAX = 4'd15, // RXVALID max count
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parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
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)
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(
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//---------- Input -------------------------------------
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input USER_TXUSRCLK,
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input USER_RXUSRCLK,
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input USER_OOBCLK_IN,
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input USER_RST_N,
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input USER_RXUSRCLK_RST_N,
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input USER_PCLK_SEL,
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input USER_RESETOVRD_START,
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input USER_TXRESETDONE,
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input USER_RXRESETDONE,
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input USER_TXELECIDLE,
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input USER_TXCOMPLIANCE,
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input USER_RXCDRLOCK_IN,
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input USER_RXVALID_IN,
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input USER_RXSTATUS_IN,
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input USER_PHYSTATUS_IN,
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input USER_RATE_DONE,
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input USER_RST_IDLE,
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input USER_RATE_RXSYNC,
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input USER_RATE_IDLE,
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input USER_RATE_GEN3,
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input USER_RXEQ_ADAPT_DONE,
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//---------- Output ------------------------------------
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output USER_OOBCLK,
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output USER_RESETOVRD,
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output USER_TXPMARESET,
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output USER_RXPMARESET,
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output USER_RXCDRRESET,
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output USER_RXCDRFREQRESET,
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output USER_RXDFELPMRESET,
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output USER_EYESCANRESET,
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output USER_TXPCSRESET,
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output USER_RXPCSRESET,
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output USER_RXBUFRESET,
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output USER_RESETOVRD_DONE,
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output USER_RESETDONE,
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output USER_ACTIVE_LANE,
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output USER_RXCDRLOCK_OUT,
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output USER_RXVALID_OUT,
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output USER_PHYSTATUS_OUT,
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output USER_PHYSTATUS_RST,
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output USER_GEN3_RDY,
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output USER_RX_CONVERGE
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);
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//---------- Input Registers ---------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
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dsmv |
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//---------- Internal Signal ---------------------------
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reg [ 1:0] oobclk_cnt = 2'd0;
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reg [ 7:0] reset_cnt = 8'd127;
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reg [ 3:0] rxcdrlock_cnt = 4'd0;
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reg [ 3:0] rxvalid_cnt = 4'd0;
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reg [21:0] converge_cnt = 22'd0;
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reg converge_gen3 = 1'd0;
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//---------- Output Registers --------------------------
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reg oobclk = 1'd0;
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reg [ 7:0] reset = 8'h00;
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reg gen3_rdy = 1'd0;
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reg [ 1:0] fsm = 2'd0;
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 2'd0;
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localparam FSM_RESETOVRD = 2'd1;
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localparam FSM_RESET_INIT = 2'd2;
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localparam FSM_RESET = 2'd3;
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//---------- Simulation Speedup ------------------------
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localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge USER_TXUSRCLK)
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begin
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if (!USER_RST_N)
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begin
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//---------- 1st Stage FF --------------------------
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pclk_sel_reg1 <= 1'd0;
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resetovrd_start_reg1 <= 1'd0;
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txresetdone_reg1 <= 1'd0;
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rxresetdone_reg1 <= 1'd0;
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txelecidle_reg1 <= 1'd0;
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txcompliance_reg1 <= 1'd0;
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rxcdrlock_reg1 <= 1'd0;
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rxeq_adapt_done_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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pclk_sel_reg2 <= 1'd0;
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resetovrd_start_reg2 <= 1'd0;
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txresetdone_reg2 <= 1'd0;
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rxresetdone_reg2 <= 1'd0;
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txelecidle_reg2 <= 1'd0;
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txcompliance_reg2 <= 1'd0;
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rxcdrlock_reg2 <= 1'd0;
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rxeq_adapt_done_reg2 <= 1'd0;
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end
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else
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begin
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//---------- 1st Stage FF --------------------------
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pclk_sel_reg1 <= USER_PCLK_SEL;
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resetovrd_start_reg1 <= USER_RESETOVRD_START;
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txresetdone_reg1 <= USER_TXRESETDONE;
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rxresetdone_reg1 <= USER_RXRESETDONE;
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txelecidle_reg1 <= USER_TXELECIDLE;
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txcompliance_reg1 <= USER_TXCOMPLIANCE;
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rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
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rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
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//---------- 2nd Stage FF --------------------------
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pclk_sel_reg2 <= pclk_sel_reg1;
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resetovrd_start_reg2 <= resetovrd_start_reg1;
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txresetdone_reg2 <= txresetdone_reg1;
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rxresetdone_reg2 <= rxresetdone_reg1;
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txelecidle_reg2 <= txelecidle_reg1;
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txcompliance_reg2 <= txcompliance_reg1;
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rxcdrlock_reg2 <= rxcdrlock_reg1;
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rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
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end
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end
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge USER_RXUSRCLK)
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begin
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if (!USER_RXUSRCLK_RST_N)
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begin
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//---------- 1st Stage FF --------------------------
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rxvalid_reg1 <= 1'd0;
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rxstatus_reg1 <= 1'd0;
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rst_idle_reg1 <= 1'd0;
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rate_done_reg1 <= 1'd0;
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rate_rxsync_reg1 <= 1'd0;
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rate_idle_reg1 <= 1'd0;
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rate_gen3_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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rxvalid_reg2 <= 1'd0;
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rxstatus_reg2 <= 1'd0;
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rst_idle_reg2 <= 1'd0;
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rate_done_reg2 <= 1'd0;
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rate_rxsync_reg2 <= 1'd0;
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rate_idle_reg2 <= 1'd0;
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rate_gen3_reg2 <= 1'd0;
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end
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else
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begin
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//---------- 1st Stage FF --------------------------
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rxvalid_reg1 <= USER_RXVALID_IN;
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rxstatus_reg1 <= USER_RXSTATUS_IN;
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rst_idle_reg1 <= USER_RST_IDLE;
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rate_done_reg1 <= USER_RATE_DONE;
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rate_rxsync_reg1 <= USER_RATE_RXSYNC;
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rate_idle_reg1 <= USER_RATE_IDLE;
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rate_gen3_reg1 <= USER_RATE_GEN3;
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//---------- 2nd Stage FF --------------------------
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rxvalid_reg2 <= rxvalid_reg1;
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rxstatus_reg2 <= rxstatus_reg1;
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rst_idle_reg2 <= rst_idle_reg1;
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rate_done_reg2 <= rate_done_reg1;
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rate_rxsync_reg2 <= rate_rxsync_reg1;
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rate_idle_reg2 <= rate_idle_reg1;
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rate_gen3_reg2 <= rate_gen3_reg1;
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end
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278 |
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end
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280 |
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281 |
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282 |
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283 |
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//---------- Generate Reset Override -------------------------------------------
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284 |
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generate if (PCIE_USE_MODE == "1.0")
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285 |
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begin : resetovrd
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287 |
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288 |
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//---------- Reset Counter -------------------------------------------------
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289 |
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always @ (posedge USER_TXUSRCLK)
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begin
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if (!USER_RST_N)
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reset_cnt <= 8'd127;
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else
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295 |
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296 |
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//---------- Decrement Counter ---------------------
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if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
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reset_cnt <= reset_cnt - 8'd1;
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299 |
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//---------- Reset Counter -------------------------
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else
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case (reset)
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8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
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8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
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8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
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8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
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8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
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8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
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8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
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8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
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8'b10000000 : reset_cnt <= 8'd127;
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313 |
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default : reset_cnt <= 8'd127;
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314 |
|
|
endcase
|
315 |
|
|
|
316 |
|
|
end
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
//---------- Reset Shift Register ------------------------------------------
|
321 |
|
|
always @ (posedge USER_TXUSRCLK)
|
322 |
|
|
begin
|
323 |
|
|
|
324 |
|
|
if (!USER_RST_N)
|
325 |
|
|
reset <= 8'h00;
|
326 |
|
|
else
|
327 |
|
|
|
328 |
|
|
//---------- Initialize Reset Register ---------
|
329 |
|
|
if (fsm == FSM_RESET_INIT)
|
330 |
|
|
reset <= 8'hFF;
|
331 |
|
|
//---------- Shift Reset Register --------------
|
332 |
|
|
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
|
333 |
|
|
reset <= {reset[6:0], 1'd0};
|
334 |
|
|
//---------- Hold Reset Register ---------------
|
335 |
|
|
else
|
336 |
|
|
reset <= reset;
|
337 |
|
|
|
338 |
|
|
end
|
339 |
|
|
|
340 |
|
|
|
341 |
|
|
|
342 |
|
|
//---------- Reset Override FSM --------------------------------------------
|
343 |
|
|
always @ (posedge USER_TXUSRCLK)
|
344 |
|
|
begin
|
345 |
|
|
|
346 |
|
|
if (!USER_RST_N)
|
347 |
|
|
fsm <= FSM_IDLE;
|
348 |
|
|
|
349 |
|
|
else
|
350 |
|
|
|
351 |
|
|
begin
|
352 |
|
|
|
353 |
|
|
case (fsm)
|
354 |
|
|
//---------- Idle State ------------------------
|
355 |
|
|
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
|
356 |
|
|
//---------- Assert RESETOVRD ------------------
|
357 |
|
|
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
|
358 |
|
|
//---------- Initialize Reset ------------------
|
359 |
|
|
FSM_RESET_INIT : fsm <= FSM_RESET;
|
360 |
|
|
//---------- Shift Reset -----------------------
|
361 |
|
|
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
|
362 |
|
|
//---------- Default State ---------------------
|
363 |
|
|
default : fsm <= FSM_IDLE;
|
364 |
|
|
endcase
|
365 |
|
|
|
366 |
|
|
end
|
367 |
|
|
|
368 |
|
|
end
|
369 |
|
|
|
370 |
|
|
end
|
371 |
|
|
|
372 |
|
|
//---------- Disable Reset Override --------------------------------------------
|
373 |
|
|
else
|
374 |
|
|
|
375 |
|
|
begin : resetovrd_disble
|
376 |
|
|
|
377 |
|
|
//---------- Generate Default Signals --------------------------------------
|
378 |
|
|
always @ (posedge USER_TXUSRCLK)
|
379 |
|
|
begin
|
380 |
|
|
|
381 |
|
|
if (!USER_RST_N)
|
382 |
|
|
begin
|
383 |
|
|
reset_cnt <= 8'hFF;
|
384 |
|
|
reset <= 8'd0;
|
385 |
|
|
fsm <= 2'd0;
|
386 |
|
|
end
|
387 |
|
|
else
|
388 |
|
|
begin
|
389 |
|
|
reset_cnt <= 8'hFF;
|
390 |
|
|
reset <= 8'd0;
|
391 |
|
|
fsm <= 2'd0;
|
392 |
|
|
end
|
393 |
|
|
|
394 |
|
|
end
|
395 |
|
|
|
396 |
|
|
end
|
397 |
|
|
|
398 |
|
|
endgenerate
|
399 |
|
|
|
400 |
|
|
|
401 |
|
|
|
402 |
|
|
//---------- Generate OOB Clock Divider ------------------------
|
403 |
|
|
generate if (PCIE_OOBCLK_MODE == 1)
|
404 |
|
|
|
405 |
|
|
begin : oobclk_div
|
406 |
|
|
|
407 |
|
|
//---------- OOB Clock Divider -----------------------------
|
408 |
|
|
always @ (posedge USER_OOBCLK_IN)
|
409 |
|
|
begin
|
410 |
|
|
|
411 |
|
|
if (!USER_RST_N)
|
412 |
|
|
begin
|
413 |
|
|
oobclk_cnt <= 2'd0;
|
414 |
|
|
oobclk <= 1'd0;
|
415 |
|
|
end
|
416 |
|
|
else
|
417 |
|
|
begin
|
418 |
|
|
oobclk_cnt <= oobclk_cnt + 2'd1;
|
419 |
|
|
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
|
420 |
|
|
end
|
421 |
|
|
|
422 |
|
|
end
|
423 |
|
|
|
424 |
|
|
end
|
425 |
|
|
|
426 |
|
|
else
|
427 |
|
|
|
428 |
|
|
begin : oobclk_div_disable
|
429 |
|
|
|
430 |
|
|
//---------- OOB Clock Default -------------------------
|
431 |
|
|
always @ (posedge USER_OOBCLK_IN)
|
432 |
|
|
begin
|
433 |
|
|
|
434 |
|
|
if (!USER_RST_N)
|
435 |
|
|
begin
|
436 |
|
|
oobclk_cnt <= 2'd0;
|
437 |
|
|
oobclk <= 1'd0;
|
438 |
|
|
end
|
439 |
|
|
else
|
440 |
|
|
begin
|
441 |
|
|
oobclk_cnt <= 2'd0;
|
442 |
|
|
oobclk <= 1'd0;
|
443 |
|
|
end
|
444 |
|
|
|
445 |
|
|
end
|
446 |
|
|
|
447 |
|
|
end
|
448 |
|
|
|
449 |
|
|
endgenerate
|
450 |
|
|
|
451 |
|
|
//---------- RXCDRLOCK Filter --------------------------------------------------
|
452 |
|
|
always @ (posedge USER_TXUSRCLK)
|
453 |
|
|
begin
|
454 |
|
|
|
455 |
|
|
if (!USER_RST_N)
|
456 |
|
|
rxcdrlock_cnt <= 4'd0;
|
457 |
|
|
else
|
458 |
|
|
|
459 |
|
|
//---------- Increment RXCDRLOCK Counter -----------
|
460 |
|
|
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
|
461 |
|
|
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
|
462 |
|
|
|
463 |
|
|
//---------- Hold RXCDRLOCK Counter ----------------
|
464 |
|
|
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
|
465 |
|
|
rxcdrlock_cnt <= rxcdrlock_cnt;
|
466 |
|
|
|
467 |
|
|
//---------- Reset RXCDRLOCK Counter ---------------
|
468 |
|
|
else
|
469 |
|
|
rxcdrlock_cnt <= 4'd0;
|
470 |
|
|
|
471 |
|
|
end
|
472 |
|
|
|
473 |
|
|
|
474 |
|
|
|
475 |
|
|
//---------- RXVALID Filter ----------------------------------------------------
|
476 |
|
|
always @ (posedge USER_RXUSRCLK)
|
477 |
|
|
begin
|
478 |
|
|
|
479 |
|
|
if (!USER_RXUSRCLK_RST_N)
|
480 |
|
|
rxvalid_cnt <= 4'd0;
|
481 |
|
|
else
|
482 |
|
|
|
483 |
|
|
//---------- Increment RXVALID Counter -------------
|
484 |
|
|
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
|
485 |
|
|
rxvalid_cnt <= rxvalid_cnt + 4'd1;
|
486 |
|
|
|
487 |
|
|
//---------- Hold RXVALID Counter ------------------
|
488 |
|
|
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
|
489 |
|
|
rxvalid_cnt <= rxvalid_cnt;
|
490 |
|
|
|
491 |
|
|
//---------- Reset RXVALID Counter -----------------
|
492 |
|
|
else
|
493 |
|
|
rxvalid_cnt <= 4'd0;
|
494 |
|
|
|
495 |
|
|
end
|
496 |
|
|
|
497 |
|
|
|
498 |
|
|
|
499 |
|
|
//---------- Converge Counter --------------------------------------------------
|
500 |
|
|
always @ (posedge USER_TXUSRCLK)
|
501 |
|
|
begin
|
502 |
|
|
|
503 |
|
|
if (!USER_RST_N)
|
504 |
|
|
converge_cnt <= 22'd0;
|
505 |
|
|
else
|
506 |
|
|
|
507 |
|
|
//---------- Enter Gen1/Gen2 -----------------------
|
508 |
|
|
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
|
509 |
|
|
begin
|
510 |
|
|
|
511 |
|
|
//---------- Increment Converge Counter --------
|
512 |
|
|
if (converge_cnt < converge_max_cnt)
|
513 |
|
|
converge_cnt <= converge_cnt + 22'd1;
|
514 |
|
|
//---------- Hold Converge Counter -------------
|
515 |
|
|
else
|
516 |
|
|
converge_cnt <= converge_cnt;
|
517 |
|
|
|
518 |
|
|
end
|
519 |
|
|
|
520 |
|
|
//---------- Reset Converge Counter ----------------
|
521 |
|
|
else
|
522 |
|
|
converge_cnt <= 22'd0;
|
523 |
|
|
|
524 |
|
|
end
|
525 |
|
|
|
526 |
|
|
|
527 |
|
|
|
528 |
|
|
//---------- Converge ----------------------------------------------------------
|
529 |
|
|
always @ (posedge USER_TXUSRCLK)
|
530 |
|
|
begin
|
531 |
|
|
|
532 |
|
|
if (!USER_RST_N)
|
533 |
|
|
converge_gen3 <= 1'd0;
|
534 |
|
|
else
|
535 |
|
|
|
536 |
|
|
//---------- Enter Gen3 ----------------------------
|
537 |
|
|
if (rate_gen3_reg2)
|
538 |
|
|
|
539 |
|
|
//---------- Wait for RX equalization adapt done
|
540 |
|
|
if (rxeq_adapt_done_reg2)
|
541 |
|
|
converge_gen3 <= 1'd1;
|
542 |
|
|
else
|
543 |
|
|
converge_gen3 <= converge_gen3;
|
544 |
|
|
|
545 |
|
|
//-------- Exit Gen3 -------------------------------
|
546 |
|
|
else
|
547 |
|
|
|
548 |
|
|
converge_gen3 <= 1'd0;
|
549 |
|
|
|
550 |
|
|
|
551 |
|
|
end
|
552 |
|
|
|
553 |
|
|
|
554 |
|
|
|
555 |
|
|
//---------- GEN3_RDY Generator ------------------------------------------------
|
556 |
|
|
always @ (posedge USER_RXUSRCLK)
|
557 |
|
|
begin
|
558 |
|
|
|
559 |
|
|
if (!USER_RXUSRCLK_RST_N)
|
560 |
|
|
gen3_rdy <= 1'd0;
|
561 |
|
|
else
|
562 |
|
|
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
|
563 |
|
|
|
564 |
|
|
end
|
565 |
|
|
|
566 |
|
|
|
567 |
|
|
|
568 |
|
|
//---------- PIPE User Override Reset Output -----------------------------------
|
569 |
|
|
assign USER_RESETOVRD = (fsm != FSM_IDLE);
|
570 |
|
|
assign USER_TXPMARESET = 1'd0;
|
571 |
|
|
assign USER_RXPMARESET = reset[0];
|
572 |
|
|
assign USER_RXCDRRESET = reset[1];
|
573 |
|
|
assign USER_RXCDRFREQRESET = reset[2];
|
574 |
|
|
assign USER_RXDFELPMRESET = reset[3];
|
575 |
|
|
assign USER_EYESCANRESET = reset[4];
|
576 |
|
|
assign USER_TXPCSRESET = 1'd0;
|
577 |
|
|
assign USER_RXPCSRESET = reset[5];
|
578 |
|
|
assign USER_RXBUFRESET = reset[6];
|
579 |
|
|
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
|
580 |
|
|
|
581 |
|
|
//---------- PIPE User Output --------------------------------------------------
|
582 |
|
|
assign USER_OOBCLK = oobclk;
|
583 |
|
|
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
|
584 |
|
|
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
|
585 |
|
|
//----------------------------------------------------------
|
586 |
|
|
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
|
587 |
|
|
//----------------------------------------------------------
|
588 |
|
|
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
|
589 |
|
|
rst_idle_reg2 && // Force RXVALID = 0 during reset
|
590 |
|
|
rate_idle_reg2); // Force RXVALID = 0 during rate change
|
591 |
|
|
//----------------------------------------------------------
|
592 |
|
|
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
|
593 |
|
|
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
|
594 |
|
|
rate_done_reg2); // Gated PHYSTATUS for rate change
|
595 |
|
|
//----------------------------------------------------------
|
596 |
|
|
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
|
597 |
|
|
//----------------------------------------------------------
|
598 |
|
|
assign USER_GEN3_RDY = 0;//gen3_rdy;
|
599 |
|
|
//----------------------------------------------------------
|
600 |
|
|
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
|
601 |
|
|
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
endmodule
|