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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_wrapper.v
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// Version : 1.10
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//------------------------------------------------------------------------------
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// Filename : pipe_wrapper.v
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// Description : PIPE Wrapper for 7 Series Transceiver
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// Version : 20.2
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//------------------------------------------------------------------------------
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//---------- PIPE Wrapper Hierarchy --------------------------------------------
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// pipe_wrapper.v
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// pipe_clock.v
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// pipe_reset.v or gtp_pipe_reset.v
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// qpll_reset.v
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// * Generate GTXE2_CHANNEL for every lane.
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// pipe_user.v
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// pipe_rate.v or gtp_pipe_rate.v
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// pipe_sync.v
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// pipe_drp.v or gtp_pipe_drp.v
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// pipe_eq.v
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// rxeq_scan.v
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// gt_wrapper.v
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// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
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// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
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// * Generate GTXE2_COMMON for every quad.
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// qpll_drp.v
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// qpll_wrapper.v
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//------------------------------------------------------------------------------
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//---------- PIPE Wrapper Parameter Encoding -----------------------------------
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// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
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// : "TRUE" = Simulation only
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// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
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// PCIE_GT_DEVICE : "GTX" (default)
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// : "GTH"
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// : "GTP"
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// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
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// : "1.1" = GTX IES 485T use mode.
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// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
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// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
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// : "3.0" = GTX GES 325T or 485T use mode (default).
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// PCIE_PLL_SEL : "CPLL" (default)
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// : "QPLL"
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// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
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// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
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// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
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// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
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// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
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// : "LPM" for Gen3 only (default) (GTX, GTH)
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// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
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// : "TRUE" = Use external clock module
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// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
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// : "TRUE" = Enable PLL power saving (default)
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// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
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// : "TRUE" = Asynchronous mode.
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// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
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// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
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// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
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// : "TRUE" = RX buffer use for Gen3 only (default)
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// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
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// : 1 = Auto TX sync (GTH)
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// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
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// : 1 = Auto RX sync (GTH)
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// PCIE_CHAN_BOND : 0 = One-Hop (default)
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// : 1 = Daisy-Chain
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// : 2 = Binary-Tree
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// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
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// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
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// PCIE_LANE : 1 (default), 2, 4, or 8
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// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
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// : 2 = PCIe Gen1/Gen2 Mode (default)
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// : 3 = PCIe Gen1/Gen2/Gen3 Mode
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// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
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// : 1 = 125 MHz
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// : 2 = 250 MHz
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// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
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// : 1 = 31.25 MHz
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// : 2 = 62.50 MHz (default)
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// : 3 = 125.00 MHz
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// : 4 = 250.00 MHz
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// : 5 = 500.00 MHz
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// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
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// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
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// : 1 = Return TX preset #5
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// PCIE_OOBCLK_MODE : 0 = Reference clock
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// : 1 = 62.50 MHz (default)
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// : 2 = 50.00 MHz (requires 1 BUFG)
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// PCIE_JTAG_MODE : 0 = Normal operation (default)
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// : 1 = JTAG mode (for debug only)
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// PCIE_DEBUG_MODE : 0 = Normal operation (default)
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// : 1 = Debug mode (for debug only)
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//------------------------------------------------------------------------------
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//---------- Notes -------------------------------------------------------------
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// Notes within the PIPE Wrapper RTL files are for internal use only.
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// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
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// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
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// In Gen3 mode, all 32-bits are used.
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- PIPE Wrapper ------------------------------------------------------
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module cl_a7pcie_x4_pipe_wrapper #
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(
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
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parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
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parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
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parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
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parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
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parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
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parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
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parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
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parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
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parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
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parameter PCIE_CHAN_BOND = 1, // PCIe channel bonding mode
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parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
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parameter PCIE_LANE = 1, // PCIe number of lanes
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parameter PCIE_LINK_SPEED = 3, // PCIe link speed
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parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
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parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
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parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
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parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
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parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
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parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
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parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
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parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
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)
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//--------------------------------------
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( // Gen1/Gen2 | Gen3
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//--------------------------------------
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//---------- PIPE Clock & Reset Ports ------------------
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input PIPE_CLK, // Reference clock that drives MMCM
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input PIPE_RESET_N, // PCLK | PCLK
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output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
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// Drives TXUSRCLK in Gen3
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// Drives RXUSRCLK in Gen3 async mode only
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//---------- PIPE TX Data Ports ------------------------
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input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
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input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
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output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
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output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
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//---------- PIPE RX Data Ports ------------------------
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input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
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input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
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output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
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output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
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//---------- PIPE Command Ports ------------------------
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input PIPE_TXDETECTRX, // PCLK | PCLK
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input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
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input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
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input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
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input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
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input [ 1:0] PIPE_RATE, // PCLK | PCLK
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//---------- PIPE Electrical Command Ports -------------
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input [ 2:0] PIPE_TXMARGIN, // Async | Async
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input PIPE_TXSWING, // Async | Async
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input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
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input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
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input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
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input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
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input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
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input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
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input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
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input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
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input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
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input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
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input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
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input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
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output [ 5:0] PIPE_TXEQ_FS, // Async | Async
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output [ 5:0] PIPE_TXEQ_LF, // Async | Async
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output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
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output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
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output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
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output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
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output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
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output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
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// output [PCIE_LANE-1:0] PIPE_RXEQ_CONVERGE, // PCLK | PCLK
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//---------- PIPE Status Ports -------------------------
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output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
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output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
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output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
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output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
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output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
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output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
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//---------- PIPE User Ports ---------------------------
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input PIPE_MMCM_RST_N, // Async | Async
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input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
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output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
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output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
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output PIPE_PCLK_LOCK, // Async | Async
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output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
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output PIPE_USERCLK1, // Optional user clock
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output PIPE_USERCLK2, // Optional user clock
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output PIPE_RXUSRCLK, // RXUSRCLK
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// Equivalent to PCLK in Gen1/Gen2
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// Equivalent to RXOUTCLK[0] in Gen3
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output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
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output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
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output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
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output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
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output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
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276 |
|
|
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
|
277 |
|
|
|
278 |
|
|
//---------- External Clock Ports ----------------------
|
279 |
|
|
input PIPE_PCLK_IN, // PCLK | PCLK
|
280 |
|
|
input PIPE_RXUSRCLK_IN, // RXUSERCLK
|
281 |
|
|
// Equivalent to PCLK in Gen1/Gen2
|
282 |
|
|
// Equivalent to RXOUTCLK[0] in Gen3
|
283 |
|
|
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
|
284 |
|
|
input PIPE_DCLK_IN, // DCLK | DCLK
|
285 |
|
|
input PIPE_USERCLK1_IN, // Optional user clock
|
286 |
|
|
input PIPE_USERCLK2_IN, // Optional user clock
|
287 |
|
|
input PIPE_OOBCLK_IN, // OOB | OOB
|
288 |
|
|
input PIPE_MMCM_LOCK_IN, // Async | Async
|
289 |
|
|
|
290 |
|
|
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
|
291 |
|
|
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
|
292 |
|
|
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
|
293 |
|
|
output PIPE_GEN3_OUT, // PCLK | PCLK
|
294 |
|
|
|
295 |
|
|
//---------- PRBS/Loopback Ports -----------------------
|
296 |
|
|
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
|
297 |
|
|
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
|
298 |
|
|
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
|
299 |
|
|
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
|
300 |
|
|
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
|
301 |
|
|
|
302 |
|
|
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
|
303 |
|
|
|
304 |
|
|
//---------- FSM Ports ---------------------------------
|
305 |
|
|
output [10:0] PIPE_RST_FSM, // PCLK | PCLK
|
306 |
|
|
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
|
307 |
|
|
output [(PCIE_LANE*31)-1:0]PIPE_RATE_FSM, // PCLK | PCLK
|
308 |
|
|
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
|
309 |
|
|
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
|
310 |
|
|
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
|
311 |
|
|
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
|
312 |
|
|
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
|
313 |
|
|
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
|
314 |
|
|
|
315 |
|
|
output PIPE_RST_IDLE, // PCLK | PCLK
|
316 |
|
|
output PIPE_QRST_IDLE, // PCLK | PCLK
|
317 |
|
|
output PIPE_RATE_IDLE, // PCLK | PCLK
|
318 |
|
|
|
319 |
|
|
//---------- JTAG Ports --------------------------------
|
320 |
|
|
input PIPE_JTAG_EN, // DCLK | DCLK
|
321 |
|
|
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
|
322 |
|
|
|
323 |
|
|
//---------- Debug Ports -------------------------------
|
324 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
|
325 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
|
326 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
|
327 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
|
328 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
|
329 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
|
330 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
|
331 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
|
332 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
|
333 |
|
|
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
|
334 |
|
|
output [31:0] PIPE_DEBUG, // Async | Async
|
335 |
|
|
|
336 |
|
|
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
|
337 |
|
|
|
338 |
|
|
);
|
339 |
|
|
|
340 |
|
|
//---------- Input Registers ---------------------------
|
341 |
48 |
dsmv |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
|
342 |
|
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
|
343 |
46 |
dsmv |
|
344 |
|
|
//---------- PIPE Clock Module Output ------------------
|
345 |
|
|
wire clk_pclk;
|
346 |
|
|
wire clk_rxusrclk;
|
347 |
|
|
wire [PCIE_LANE-1:0] clk_rxoutclk;
|
348 |
|
|
wire clk_dclk;
|
349 |
|
|
wire clk_oobclk;
|
350 |
|
|
wire clk_mmcm_lock;
|
351 |
|
|
|
352 |
|
|
//---------- PIPE Reset Module Output ------------------
|
353 |
|
|
wire rst_cpllreset;
|
354 |
|
|
wire rst_cpllpd;
|
355 |
|
|
wire rst_rxusrclk_reset;
|
356 |
|
|
wire rst_dclk_reset;
|
357 |
|
|
wire rst_gtreset;
|
358 |
|
|
wire rst_drp_start;
|
359 |
|
|
wire rst_drp_x16x20_mode;
|
360 |
|
|
wire rst_drp_x16;
|
361 |
|
|
wire rst_userrdy;
|
362 |
|
|
wire rst_txsync_start;
|
363 |
|
|
wire rst_idle;
|
364 |
|
|
wire [ 4:0] rst_fsm;
|
365 |
|
|
|
366 |
|
|
//------------------------------------------------------
|
367 |
|
|
wire gtp_rst_qpllreset; // GTP
|
368 |
|
|
wire gtp_rst_qpllpd; // GTP
|
369 |
|
|
|
370 |
|
|
//------------------------------------------------------
|
371 |
|
|
wire [(PCIE_LANE-1)>>2:0]qpllreset;
|
372 |
|
|
wire qpllpd;
|
373 |
|
|
|
374 |
|
|
//---------- QPLL Reset Module Output ------------------
|
375 |
|
|
wire qrst_ovrd;
|
376 |
|
|
wire qrst_drp_start;
|
377 |
|
|
wire qrst_qpllreset;
|
378 |
|
|
wire qrst_qpllpd;
|
379 |
|
|
wire qrst_idle;
|
380 |
|
|
wire [ 3:0] qrst_fsm;
|
381 |
|
|
|
382 |
|
|
//---------- PIPE_JTAG Master Module Output ------------
|
383 |
|
|
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
|
384 |
|
|
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
|
385 |
|
|
|
386 |
|
|
//---------- PIPE User Module Output -------------------
|
387 |
|
|
wire [PCIE_LANE-1:0] user_oobclk;
|
388 |
|
|
wire [PCIE_LANE-1:0] user_resetovrd;
|
389 |
|
|
wire [PCIE_LANE-1:0] user_txpmareset;
|
390 |
|
|
wire [PCIE_LANE-1:0] user_rxpmareset;
|
391 |
|
|
wire [PCIE_LANE-1:0] user_rxcdrreset;
|
392 |
|
|
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
|
393 |
|
|
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
|
394 |
|
|
wire [PCIE_LANE-1:0] user_eyescanreset;
|
395 |
|
|
wire [PCIE_LANE-1:0] user_txpcsreset;
|
396 |
|
|
wire [PCIE_LANE-1:0] user_rxpcsreset;
|
397 |
|
|
wire [PCIE_LANE-1:0] user_rxbufreset;
|
398 |
|
|
wire [PCIE_LANE-1:0] user_resetovrd_done;
|
399 |
|
|
wire [PCIE_LANE-1:0] user_active_lane;
|
400 |
|
|
wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */;
|
401 |
|
|
wire [PCIE_LANE-1:0] user_rxcdrlock;
|
402 |
|
|
wire [PCIE_LANE-1:0] user_rx_converge;
|
403 |
|
|
|
404 |
|
|
//---------- PIPE Rate Module Output -------------------
|
405 |
|
|
wire [PCIE_LANE-1:0] rate_cpllpd;
|
406 |
|
|
wire [PCIE_LANE-1:0] rate_qpllpd;
|
407 |
|
|
wire [PCIE_LANE-1:0] rate_cpllreset;
|
408 |
|
|
wire [PCIE_LANE-1:0] rate_qpllreset;
|
409 |
|
|
wire [PCIE_LANE-1:0] rate_txpmareset;
|
410 |
|
|
wire [PCIE_LANE-1:0] rate_rxpmareset;
|
411 |
|
|
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
|
412 |
|
|
wire [PCIE_LANE-1:0] rate_pclk_sel;
|
413 |
|
|
wire [PCIE_LANE-1:0] rate_drp_start;
|
414 |
|
|
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
|
415 |
|
|
wire [PCIE_LANE-1:0] rate_drp_x16;
|
416 |
|
|
wire [PCIE_LANE-1:0] rate_gen3;
|
417 |
|
|
wire [(PCIE_LANE*3)-1:0] rate_rate;
|
418 |
|
|
wire [PCIE_LANE-1:0] rate_resetovrd_start;
|
419 |
|
|
wire [PCIE_LANE-1:0] rate_txsync_start;
|
420 |
|
|
wire [PCIE_LANE-1:0] rate_done;
|
421 |
|
|
wire [PCIE_LANE-1:0] rate_rxsync_start;
|
422 |
|
|
wire [PCIE_LANE-1:0] rate_rxsync;
|
423 |
|
|
wire [PCIE_LANE-1:0] rate_idle;
|
424 |
|
|
wire [(PCIE_LANE*5)-1:0]rate_fsm;
|
425 |
|
|
|
426 |
|
|
//---------- PIPE Sync Module Output -------------------
|
427 |
|
|
wire [PCIE_LANE-1:0] sync_txphdlyreset;
|
428 |
|
|
wire [PCIE_LANE-1:0] sync_txphalign;
|
429 |
|
|
wire [PCIE_LANE-1:0] sync_txphalignen;
|
430 |
|
|
wire [PCIE_LANE-1:0] sync_txphinit;
|
431 |
|
|
wire [PCIE_LANE-1:0] sync_txdlybypass;
|
432 |
|
|
wire [PCIE_LANE-1:0] sync_txdlysreset;
|
433 |
|
|
wire [PCIE_LANE-1:0] sync_txdlyen;
|
434 |
|
|
wire [PCIE_LANE-1:0] sync_txsync_done;
|
435 |
|
|
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
|
436 |
|
|
|
437 |
|
|
wire [PCIE_LANE-1:0] sync_rxphalign;
|
438 |
|
|
wire [PCIE_LANE-1:0] sync_rxphalignen;
|
439 |
|
|
wire [PCIE_LANE-1:0] sync_rxdlybypass;
|
440 |
|
|
wire [PCIE_LANE-1:0] sync_rxdlysreset;
|
441 |
|
|
wire [PCIE_LANE-1:0] sync_rxdlyen;
|
442 |
|
|
wire [PCIE_LANE-1:0] sync_rxddien;
|
443 |
|
|
wire [PCIE_LANE-1:0] sync_rxsync_done;
|
444 |
|
|
wire [PCIE_LANE-1:0] sync_rxsync_donem;
|
445 |
|
|
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
|
446 |
|
|
|
447 |
|
|
wire [PCIE_LANE-1:0] txdlysresetdone;
|
448 |
|
|
wire [PCIE_LANE-1:0] txphaligndone;
|
449 |
|
|
wire [PCIE_LANE-1:0] rxdlysresetdone;
|
450 |
|
|
wire [PCIE_LANE-1:0] rxphaligndone_s;
|
451 |
|
|
|
452 |
|
|
wire txsyncallin; // GTH
|
453 |
|
|
wire rxsyncallin; // GTH
|
454 |
|
|
|
455 |
|
|
//---------- PIPE DRP Module Output --------------------
|
456 |
|
|
wire [(PCIE_LANE*9)-1:0] drp_addr;
|
457 |
|
|
wire [PCIE_LANE-1:0] drp_en;
|
458 |
|
|
wire [(PCIE_LANE*16)-1:0]drp_di;
|
459 |
|
|
wire [PCIE_LANE-1:0] drp_we;
|
460 |
|
|
wire [PCIE_LANE-1:0] drp_done;
|
461 |
|
|
wire [(PCIE_LANE*3)-1:0] drp_fsm;
|
462 |
|
|
|
463 |
|
|
//---------- PIPE JTAG Slave Module Output--------------
|
464 |
|
|
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
|
465 |
|
|
wire [PCIE_LANE-1:0] jtag_sl_den;
|
466 |
|
|
wire [PCIE_LANE-1:0] jtag_sl_en;
|
467 |
|
|
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
|
468 |
|
|
wire [PCIE_LANE-1:0] jtag_sl_we;
|
469 |
|
|
|
470 |
|
|
//---------- PIPE DRP MUX Output -----------------------
|
471 |
|
|
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
|
472 |
|
|
wire [PCIE_LANE-1:0] drp_mux_en;
|
473 |
|
|
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
|
474 |
|
|
wire [PCIE_LANE-1:0] drp_mux_we;
|
475 |
|
|
|
476 |
|
|
//---------- PIPE EQ Module Output ---------------------
|
477 |
|
|
wire [PCIE_LANE-1:0] eq_txeq_deemph;
|
478 |
|
|
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
|
479 |
|
|
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
|
480 |
|
|
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
|
481 |
|
|
|
482 |
|
|
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
|
483 |
|
|
|
484 |
|
|
//---------- PIPE DRP Module Output --------------------
|
485 |
|
|
wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr;
|
486 |
|
|
wire [(PCIE_LANE-1)>>2:0] qdrp_en;
|
487 |
|
|
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di;
|
488 |
|
|
wire [(PCIE_LANE-1)>>2:0] qdrp_we;
|
489 |
|
|
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
|
490 |
|
|
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
|
491 |
|
|
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
|
492 |
|
|
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
|
493 |
|
|
|
494 |
|
|
//---------- QPLL Wrapper Output -----------------------
|
495 |
|
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
|
496 |
|
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
|
497 |
|
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
|
498 |
|
|
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do;
|
499 |
|
|
wire [(PCIE_LANE-1)>>2:0] qpll_rdy;
|
500 |
|
|
|
501 |
|
|
//---------- GTX Wrapper Output ------------------------
|
502 |
|
|
wire [PCIE_LANE-1:0] gt_txoutclk;
|
503 |
|
|
wire [PCIE_LANE-1:0] gt_rxoutclk;
|
504 |
|
|
wire [PCIE_LANE-1:0] gt_cplllock;
|
505 |
|
|
wire [PCIE_LANE-1:0] gt_rxcdrlock;
|
506 |
|
|
wire [PCIE_LANE-1:0] gt_txresetdone;
|
507 |
|
|
wire [PCIE_LANE-1:0] gt_rxresetdone;
|
508 |
|
|
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
|
509 |
|
|
wire [PCIE_LANE-1:0] gt_rxvalid;
|
510 |
|
|
wire [PCIE_LANE-1:0] gt_phystatus;
|
511 |
|
|
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
|
512 |
|
|
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
|
513 |
|
|
wire [PCIE_LANE-1:0] gt_rxelecidle;
|
514 |
|
|
wire [PCIE_LANE-1:0] gt_txratedone;
|
515 |
|
|
wire [PCIE_LANE-1:0] gt_rxratedone;
|
516 |
|
|
wire [(PCIE_LANE*16)-1:0]gt_do;
|
517 |
|
|
wire [PCIE_LANE-1:0] gt_rdy;
|
518 |
|
|
wire [PCIE_LANE-1:0] gt_txphinitdone;
|
519 |
|
|
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
|
520 |
|
|
wire [PCIE_LANE-1:0] gt_txphaligndone;
|
521 |
|
|
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
|
522 |
|
|
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
|
523 |
|
|
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
|
524 |
|
|
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
|
525 |
|
|
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
|
526 |
|
|
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
|
527 |
|
|
wire [PCIE_LANE-1:0] gt_rxcommadet;
|
528 |
|
|
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
|
529 |
|
|
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
|
530 |
|
|
wire [PCIE_LANE-1:0] gt_rxbyterealign;
|
531 |
|
|
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
|
532 |
|
|
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
|
533 |
|
|
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
|
534 |
|
|
|
535 |
|
|
wire [PCIE_LANE-1:0] rxchbonden;
|
536 |
|
|
wire [PCIE_LANE-1:0] rxchbondmaster;
|
537 |
|
|
wire [PCIE_LANE-1:0] rxchbondslave;
|
538 |
|
|
wire [PCIE_LANE-1:0] oobclk;
|
539 |
|
|
|
540 |
|
|
//---------- TX EQ -------------------------------------
|
541 |
|
|
localparam TXEQ_FS = 6'd40; // TX equalization full swing
|
542 |
|
|
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
|
543 |
|
|
|
544 |
|
|
//---------- Select JTAG Slave Type ----------------------------------------
|
545 |
|
|
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
|
546 |
|
|
|
547 |
|
|
//---------- Generate Per-Lane Signals -----------------
|
548 |
|
|
genvar i; // Index for per-lane signals
|
549 |
|
|
|
550 |
|
|
|
551 |
|
|
|
552 |
|
|
//---------- Assignments -------------------------------------------------------
|
553 |
|
|
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
|
554 |
|
|
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
|
555 |
|
|
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
|
556 |
|
|
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
|
557 |
|
|
|
558 |
|
|
//---------- Reset Synchronizer ------------------------------------------------
|
559 |
|
|
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
|
560 |
|
|
begin
|
561 |
|
|
|
562 |
|
|
if (!PIPE_RESET_N)
|
563 |
|
|
begin
|
564 |
|
|
reset_n_reg1 <= 1'd0;
|
565 |
|
|
reset_n_reg2 <= 1'd0;
|
566 |
|
|
end
|
567 |
|
|
else
|
568 |
|
|
begin
|
569 |
|
|
reset_n_reg1 <= 1'd1;
|
570 |
|
|
reset_n_reg2 <= reset_n_reg1;
|
571 |
|
|
end
|
572 |
|
|
|
573 |
|
|
end
|
574 |
|
|
|
575 |
|
|
|
576 |
|
|
|
577 |
|
|
//---------- PIPE Clock Module -------------------------------------------------
|
578 |
|
|
generate
|
579 |
|
|
|
580 |
|
|
if (PCIE_EXT_CLK == "FALSE")
|
581 |
|
|
|
582 |
|
|
begin : pipe_clock_int
|
583 |
|
|
|
584 |
|
|
cl_a7pcie_x4_pipe_clock #
|
585 |
|
|
(
|
586 |
|
|
|
587 |
|
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
588 |
|
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
589 |
|
|
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
|
590 |
|
|
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
|
591 |
|
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
|
592 |
|
|
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
|
593 |
|
|
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
|
594 |
|
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
|
595 |
|
|
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
|
596 |
|
|
|
597 |
|
|
)
|
598 |
|
|
pipe_clock_i
|
599 |
|
|
(
|
600 |
|
|
|
601 |
|
|
//---------- Input -------------------------------------
|
602 |
|
|
.CLK_CLK (PIPE_CLK),
|
603 |
|
|
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
|
604 |
|
|
.CLK_RXOUTCLK_IN (gt_rxoutclk),
|
605 |
|
|
//.CLK_RST_N (1'b1),
|
606 |
|
|
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
|
607 |
|
|
.CLK_PCLK_SEL (rate_pclk_sel),
|
608 |
|
|
.CLK_GEN3 (rate_gen3[0]),
|
609 |
|
|
|
610 |
|
|
//---------- Output ------------------------------------
|
611 |
|
|
.CLK_PCLK (clk_pclk),
|
612 |
|
|
.CLK_RXUSRCLK (clk_rxusrclk),
|
613 |
|
|
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
|
614 |
|
|
.CLK_DCLK (clk_dclk),
|
615 |
|
|
.CLK_USERCLK1 (PIPE_USERCLK1),
|
616 |
|
|
.CLK_USERCLK2 (PIPE_USERCLK2),
|
617 |
|
|
.CLK_OOBCLK (clk_oobclk),
|
618 |
|
|
.CLK_MMCM_LOCK (clk_mmcm_lock)
|
619 |
|
|
|
620 |
|
|
);
|
621 |
|
|
|
622 |
|
|
end
|
623 |
|
|
|
624 |
|
|
else
|
625 |
|
|
|
626 |
|
|
//---------- PIPE Clock External ---------------------------------------
|
627 |
|
|
begin : pipe_clock_int_disable
|
628 |
|
|
assign clk_pclk = PIPE_PCLK_IN;
|
629 |
|
|
assign clk_rxusrclk = PIPE_RXUSRCLK_IN;
|
630 |
|
|
assign clk_rxoutclk = PIPE_RXOUTCLK_IN;
|
631 |
|
|
assign clk_dclk = PIPE_DCLK_IN;
|
632 |
|
|
assign PIPE_USERCLK1 = PIPE_USERCLK1_IN;
|
633 |
|
|
assign PIPE_USERCLK2 = PIPE_USERCLK2_IN;
|
634 |
|
|
assign clk_oobclk = PIPE_OOBCLK_IN;
|
635 |
|
|
assign clk_mmcm_lock = PIPE_MMCM_LOCK_IN;
|
636 |
|
|
end
|
637 |
|
|
|
638 |
|
|
endgenerate
|
639 |
|
|
|
640 |
|
|
|
641 |
|
|
|
642 |
|
|
//---------- PIPE Reset Module -------------------------------------------------
|
643 |
|
|
generate
|
644 |
|
|
|
645 |
|
|
if (PCIE_GT_DEVICE == "GTP")
|
646 |
|
|
|
647 |
|
|
begin : gtp_pipe_reset
|
648 |
|
|
|
649 |
|
|
//---------- GTP PIPE Reset Module -------------------------------------
|
650 |
|
|
cl_a7pcie_x4_gtp_pipe_reset #
|
651 |
|
|
(
|
652 |
|
|
|
653 |
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
|
654 |
|
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
655 |
|
|
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
|
656 |
|
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
657 |
|
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
658 |
|
|
|
659 |
|
|
)
|
660 |
|
|
gtp_pipe_reset_i
|
661 |
|
|
(
|
662 |
|
|
|
663 |
|
|
//---------- Input -----------------------------
|
664 |
|
|
.RST_CLK (clk_pclk),
|
665 |
|
|
.RST_RXUSRCLK (clk_rxusrclk),
|
666 |
|
|
.RST_DCLK (clk_dclk),
|
667 |
|
|
.RST_RST_N (reset_n_reg2),
|
668 |
|
|
.RST_DRP_DONE (drp_done),
|
669 |
|
|
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
|
670 |
|
|
.RST_PLLLOCK (&qpll_qplllock),
|
671 |
|
|
//.RST_QPLL_IDLE (qrst_idle), // removed for GTP
|
672 |
|
|
.RST_RATE_IDLE (rate_idle),
|
673 |
|
|
.RST_RXCDRLOCK (user_rxcdrlock),
|
674 |
|
|
.RST_MMCM_LOCK (clk_mmcm_lock),
|
675 |
|
|
.RST_RESETDONE (user_resetdone),
|
676 |
|
|
.RST_PHYSTATUS (gt_phystatus),
|
677 |
|
|
.RST_TXSYNC_DONE (sync_txsync_done),
|
678 |
|
|
|
679 |
|
|
//---------- Output ----------------------------
|
680 |
|
|
.RST_CPLLRESET (rst_cpllreset),
|
681 |
|
|
.RST_CPLLPD (rst_cpllpd),
|
682 |
|
|
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
|
683 |
|
|
.RST_DCLK_RESET (rst_dclk_reset),
|
684 |
|
|
.RST_GTRESET (rst_gtreset),
|
685 |
|
|
.RST_DRP_START (rst_drp_start),
|
686 |
|
|
.RST_DRP_X16 (rst_drp_x16),
|
687 |
|
|
.RST_USERRDY (rst_userrdy),
|
688 |
|
|
.RST_TXSYNC_START (rst_txsync_start),
|
689 |
|
|
.RST_IDLE (rst_idle),
|
690 |
|
|
.RST_FSM (rst_fsm)
|
691 |
|
|
|
692 |
|
|
);
|
693 |
|
|
|
694 |
|
|
//---------- Default ---------------------------------------------------
|
695 |
|
|
assign gtp_rst_qpllreset = rst_cpllreset;
|
696 |
|
|
assign gtp_rst_qpllpd = rst_cpllpd;
|
697 |
|
|
|
698 |
|
|
end
|
699 |
|
|
|
700 |
|
|
else
|
701 |
|
|
|
702 |
|
|
begin : pipe_reset
|
703 |
|
|
|
704 |
|
|
//---------- PIPE Reset Module -----------------------------------------
|
705 |
|
|
cl_a7pcie_x4_pipe_reset #
|
706 |
|
|
(
|
707 |
|
|
|
708 |
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
|
709 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
|
710 |
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
711 |
|
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
|
712 |
|
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
713 |
|
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
714 |
|
|
|
715 |
|
|
)
|
716 |
|
|
pipe_reset_i
|
717 |
|
|
(
|
718 |
|
|
|
719 |
|
|
//---------- Input -----------------------------
|
720 |
|
|
.RST_CLK (clk_pclk),
|
721 |
|
|
.RST_RXUSRCLK (clk_rxusrclk),
|
722 |
|
|
.RST_DCLK (clk_dclk),
|
723 |
|
|
.RST_RST_N (reset_n_reg2),
|
724 |
|
|
.RST_DRP_DONE (drp_done),
|
725 |
|
|
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
|
726 |
|
|
.RST_CPLLLOCK (gt_cplllock),
|
727 |
|
|
.RST_QPLL_IDLE (qrst_idle),
|
728 |
|
|
.RST_RATE_IDLE (rate_idle),
|
729 |
|
|
.RST_RXCDRLOCK (user_rxcdrlock),
|
730 |
|
|
.RST_MMCM_LOCK (clk_mmcm_lock),
|
731 |
|
|
.RST_RESETDONE (user_resetdone),
|
732 |
|
|
.RST_PHYSTATUS (gt_phystatus),
|
733 |
|
|
.RST_TXSYNC_DONE (sync_txsync_done),
|
734 |
|
|
|
735 |
|
|
//---------- Output ----------------------------
|
736 |
|
|
.RST_CPLLRESET (rst_cpllreset),
|
737 |
|
|
.RST_CPLLPD (rst_cpllpd),
|
738 |
|
|
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
|
739 |
|
|
.RST_DCLK_RESET (rst_dclk_reset),
|
740 |
|
|
.RST_GTRESET (rst_gtreset),
|
741 |
|
|
.RST_DRP_START (rst_drp_start),
|
742 |
|
|
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
|
743 |
|
|
.RST_DRP_X16 (rst_drp_x16),
|
744 |
|
|
.RST_USERRDY (rst_userrdy),
|
745 |
|
|
.RST_TXSYNC_START (rst_txsync_start),
|
746 |
|
|
.RST_IDLE (rst_idle),
|
747 |
48 |
dsmv |
.RST_FSM (rst_fsm[4:0])
|
748 |
46 |
dsmv |
|
749 |
|
|
);
|
750 |
|
|
|
751 |
|
|
//---------- Default ---------------------------------------------------
|
752 |
|
|
assign gtp_rst_qpllreset = 1'd0;
|
753 |
|
|
assign gtp_rst_qpllpd = 1'd0;
|
754 |
|
|
|
755 |
|
|
end
|
756 |
|
|
|
757 |
|
|
endgenerate
|
758 |
|
|
|
759 |
|
|
|
760 |
|
|
|
761 |
|
|
//---------- QPLL Reset Module -------------------------------------------------
|
762 |
|
|
generate
|
763 |
|
|
|
764 |
|
|
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
|
765 |
|
|
|
766 |
|
|
begin : qpll_reset
|
767 |
|
|
|
768 |
|
|
cl_a7pcie_x4_qpll_reset #
|
769 |
|
|
(
|
770 |
|
|
|
771 |
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
772 |
|
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
|
773 |
|
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
774 |
|
|
|
775 |
|
|
)
|
776 |
|
|
qpll_reset_i
|
777 |
|
|
(
|
778 |
|
|
|
779 |
|
|
//---------- Input ---------------------------------
|
780 |
|
|
.QRST_CLK (clk_pclk),
|
781 |
|
|
.QRST_RST_N (reset_n_reg2),
|
782 |
|
|
.QRST_MMCM_LOCK (clk_mmcm_lock),
|
783 |
|
|
.QRST_CPLLLOCK (gt_cplllock),
|
784 |
|
|
.QRST_DRP_DONE (qdrp_done),
|
785 |
|
|
.QRST_QPLLLOCK (qpll_qplllock),
|
786 |
|
|
.QRST_RATE (PIPE_RATE),
|
787 |
|
|
.QRST_QPLLRESET_IN (rate_qpllreset),
|
788 |
|
|
.QRST_QPLLPD_IN (rate_qpllpd),
|
789 |
|
|
|
790 |
|
|
//---------- Output --------------------------------
|
791 |
|
|
.QRST_OVRD (qrst_ovrd),
|
792 |
|
|
.QRST_DRP_START (qrst_drp_start),
|
793 |
|
|
.QRST_QPLLRESET_OUT (qrst_qpllreset),
|
794 |
|
|
.QRST_QPLLPD_OUT (qrst_qpllpd),
|
795 |
|
|
.QRST_IDLE (qrst_idle),
|
796 |
|
|
.QRST_FSM (qrst_fsm)
|
797 |
|
|
|
798 |
|
|
);
|
799 |
|
|
|
800 |
|
|
end
|
801 |
|
|
|
802 |
|
|
else
|
803 |
|
|
|
804 |
|
|
//---------- QPLL Reset Defaults ---------------------------------------
|
805 |
|
|
begin : qpll_reset_disable
|
806 |
|
|
assign qrst_ovrd = 1'd0;
|
807 |
|
|
assign qrst_drp_start = 1'd0;
|
808 |
|
|
assign qrst_qpllreset = 1'd0;
|
809 |
|
|
assign qrst_qpllpd = 1'd0;
|
810 |
|
|
assign qrst_idle = 1'd0;
|
811 |
48 |
dsmv |
assign qrst_fsm = 4'd1;
|
812 |
46 |
dsmv |
end
|
813 |
|
|
|
814 |
|
|
endgenerate
|
815 |
|
|
|
816 |
|
|
|
817 |
|
|
|
818 |
|
|
//---------- Generate PIPE JTAG Master -----------------------------------------
|
819 |
|
|
generate
|
820 |
|
|
|
821 |
|
|
if (PCIE_JTAG_MODE == 1)
|
822 |
|
|
|
823 |
|
|
begin : pipe_jtag_m
|
824 |
|
|
|
825 |
|
|
//-------------PIPE JTAG Master Module ---------------------------------
|
826 |
|
|
pipe_jtag_m #
|
827 |
|
|
(
|
828 |
|
|
.PCIE_LANE (PCIE_LANE)
|
829 |
|
|
)
|
830 |
|
|
pipe_jtag_m_i
|
831 |
|
|
(
|
832 |
|
|
|
833 |
|
|
//---------- Connect to JTAG Slave -------------
|
834 |
|
|
.JTAG_SL_IPORT (jtag_sl_iport), //
|
835 |
|
|
.JTAG_SL_OPORT (jtag_sl_oport),
|
836 |
|
|
|
837 |
|
|
//---------- Input -----------------------------
|
838 |
|
|
.JTAG_M_CLK (clk_dclk)
|
839 |
|
|
|
840 |
|
|
);
|
841 |
|
|
|
842 |
|
|
end
|
843 |
|
|
|
844 |
|
|
else
|
845 |
|
|
|
846 |
|
|
begin : pipe_jtag_m_disable
|
847 |
|
|
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
|
848 |
|
|
end
|
849 |
|
|
|
850 |
|
|
endgenerate
|
851 |
|
|
|
852 |
|
|
|
853 |
|
|
|
854 |
|
|
//---------- Generate PIPE Lane ------------------------------------------------
|
855 |
|
|
generate for (i=0; i<PCIE_LANE; i=i+1)
|
856 |
|
|
|
857 |
|
|
begin : pipe_lane
|
858 |
|
|
|
859 |
|
|
//---------- PIPE User Module ----------------------------------------------
|
860 |
|
|
cl_a7pcie_x4_pipe_user #
|
861 |
|
|
(
|
862 |
|
|
|
863 |
|
|
.PCIE_USE_MODE (PCIE_USE_MODE),
|
864 |
|
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
|
865 |
|
|
|
866 |
|
|
)
|
867 |
|
|
pipe_user_i
|
868 |
|
|
(
|
869 |
|
|
|
870 |
|
|
//---------- Input ---------------------------------
|
871 |
|
|
.USER_TXUSRCLK (clk_pclk),
|
872 |
|
|
.USER_RXUSRCLK (clk_rxusrclk),
|
873 |
|
|
.USER_OOBCLK_IN (clk_oobclk),
|
874 |
|
|
.USER_RST_N (!rst_cpllreset),
|
875 |
|
|
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
|
876 |
|
|
.USER_PCLK_SEL (rate_pclk_sel[i]),
|
877 |
|
|
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
|
878 |
|
|
.USER_TXRESETDONE (gt_txresetdone[i]),
|
879 |
|
|
.USER_RXRESETDONE (gt_rxresetdone[i]),
|
880 |
|
|
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
|
881 |
|
|
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
|
882 |
|
|
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
|
883 |
|
|
.USER_RXVALID_IN (gt_rxvalid[i]),
|
884 |
|
|
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
|
885 |
|
|
.USER_PHYSTATUS_IN (gt_phystatus[i]),
|
886 |
|
|
.USER_RATE_DONE (rate_done[i]),
|
887 |
|
|
.USER_RST_IDLE (rst_idle),
|
888 |
|
|
.USER_RATE_RXSYNC (rate_rxsync[i]),
|
889 |
|
|
.USER_RATE_IDLE (rate_idle[i]),
|
890 |
|
|
.USER_RATE_GEN3 (rate_gen3[i]),
|
891 |
|
|
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
|
892 |
|
|
|
893 |
|
|
//---------- Output --------------------------------
|
894 |
|
|
.USER_OOBCLK (user_oobclk[i]),
|
895 |
|
|
.USER_RESETOVRD (user_resetovrd[i]),
|
896 |
|
|
.USER_TXPMARESET (user_txpmareset[i]),
|
897 |
|
|
.USER_RXPMARESET (user_rxpmareset[i]),
|
898 |
|
|
.USER_RXCDRRESET (user_rxcdrreset[i]),
|
899 |
|
|
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
|
900 |
|
|
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
|
901 |
|
|
.USER_EYESCANRESET (user_eyescanreset[i]),
|
902 |
|
|
.USER_TXPCSRESET (user_txpcsreset[i]),
|
903 |
|
|
.USER_RXPCSRESET (user_rxpcsreset[i]),
|
904 |
|
|
.USER_RXBUFRESET (user_rxbufreset[i]),
|
905 |
|
|
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
|
906 |
|
|
.USER_RESETDONE (user_resetdone[i]),
|
907 |
|
|
.USER_ACTIVE_LANE (user_active_lane[i]),
|
908 |
|
|
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
|
909 |
|
|
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
|
910 |
|
|
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
|
911 |
|
|
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
|
912 |
|
|
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
|
913 |
|
|
.USER_RX_CONVERGE (user_rx_converge[i])
|
914 |
|
|
|
915 |
|
|
);
|
916 |
|
|
|
917 |
|
|
|
918 |
|
|
|
919 |
|
|
//---------- GTP PIPE Rate Module ------------------------------------------
|
920 |
|
|
if (PCIE_GT_DEVICE == "GTP")
|
921 |
|
|
|
922 |
|
|
begin : gtp_pipe_rate
|
923 |
|
|
|
924 |
|
|
cl_a7pcie_x4_gtp_pipe_rate #
|
925 |
|
|
(
|
926 |
|
|
|
927 |
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP) // PCIe sim speedup
|
928 |
|
|
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
|
929 |
|
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
930 |
|
|
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
|
931 |
|
|
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
|
932 |
|
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
|
933 |
|
|
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // removed for GTP
|
934 |
|
|
|
935 |
|
|
)
|
936 |
|
|
gtp_pipe_rate_i
|
937 |
|
|
(
|
938 |
|
|
|
939 |
|
|
//---------- Input -----------------------------
|
940 |
|
|
.RATE_CLK (clk_pclk),
|
941 |
|
|
.RATE_RST_N (!rst_cpllreset),
|
942 |
|
|
//.RATE_RST_IDLE (rst_idle), // removed for GTP
|
943 |
|
|
//.RATE_ACTIVE_LANE (user_active_lane[i]), // removed for GTP
|
944 |
|
|
.RATE_RATE_IN (PIPE_RATE),
|
945 |
|
|
//.RATE_CPLLLOCK (gt_cplllock[i]), // removed for GTP
|
946 |
|
|
//.RATE_QPLLLOCK (qpll_qplllock[i>>2]) // removed for GTP
|
947 |
|
|
//.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP
|
948 |
|
|
.RATE_DRP_DONE (drp_done[i]),
|
949 |
|
|
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
950 |
|
|
//.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP
|
951 |
|
|
//.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP
|
952 |
|
|
.RATE_TXRATEDONE (gt_txratedone[i]),
|
953 |
|
|
.RATE_RXRATEDONE (gt_rxratedone[i]),
|
954 |
|
|
.RATE_PHYSTATUS (gt_phystatus[i]),
|
955 |
|
|
//.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP
|
956 |
|
|
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
|
957 |
|
|
//.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP
|
958 |
|
|
|
959 |
|
|
//---------- Output ----------------------------
|
960 |
|
|
//.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP
|
961 |
|
|
//.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP
|
962 |
|
|
//.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP
|
963 |
|
|
//.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP
|
964 |
|
|
//.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP
|
965 |
|
|
//.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP
|
966 |
|
|
//.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP
|
967 |
|
|
.RATE_DRP_START (rate_drp_start[i]),
|
968 |
|
|
.RATE_DRP_X16 (rate_drp_x16[i]),
|
969 |
|
|
.RATE_PCLK_SEL (rate_pclk_sel[i]),
|
970 |
|
|
//.RATE_GEN3 (rate_gen3[i]), // removed for GTP
|
971 |
|
|
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
|
972 |
|
|
//.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP
|
973 |
|
|
.RATE_TXSYNC_START (rate_txsync_start[i]),
|
974 |
|
|
.RATE_DONE (rate_done[i]),
|
975 |
|
|
//.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP
|
976 |
|
|
//.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP
|
977 |
|
|
.RATE_IDLE (rate_idle[i]),
|
978 |
|
|
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
|
979 |
|
|
);
|
980 |
|
|
|
981 |
|
|
//---------- Default for GTP -----------------------
|
982 |
|
|
assign rate_cpllpd[i] = 1'd0;
|
983 |
|
|
assign rate_qpllpd[i] = 1'd0;
|
984 |
|
|
assign rate_cpllreset[i] = 1'd0;
|
985 |
|
|
assign rate_qpllreset[i] = 1'd0;
|
986 |
|
|
assign rate_txpmareset[i] = 1'd0;
|
987 |
|
|
assign rate_rxpmareset[i] = 1'd0;
|
988 |
|
|
assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0;
|
989 |
|
|
assign rate_gen3[i] = 1'd0;
|
990 |
|
|
assign rate_resetovrd_start[i] = 1'd0;
|
991 |
|
|
assign rate_rxsync_start[i] = 1'd0;
|
992 |
|
|
assign rate_rxsync[i] = 1'd0;
|
993 |
|
|
|
994 |
|
|
end
|
995 |
|
|
|
996 |
|
|
else
|
997 |
|
|
|
998 |
|
|
begin : pipe_rate
|
999 |
|
|
|
1000 |
|
|
//---------- PIPE Rate Module ----------------------------------------------
|
1001 |
|
|
cl_a7pcie_x4_pipe_rate #
|
1002 |
|
|
(
|
1003 |
|
|
|
1004 |
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
|
1005 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
1006 |
|
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
1007 |
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
1008 |
|
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
|
1009 |
|
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
1010 |
|
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
1011 |
|
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
|
1012 |
|
|
|
1013 |
|
|
)
|
1014 |
|
|
pipe_rate_i
|
1015 |
|
|
(
|
1016 |
|
|
|
1017 |
|
|
//---------- Input ---------------------------------
|
1018 |
|
|
.RATE_CLK (clk_pclk),
|
1019 |
|
|
.RATE_RST_N (!rst_cpllreset),
|
1020 |
|
|
.RATE_RST_IDLE (rst_idle),
|
1021 |
|
|
.RATE_ACTIVE_LANE (user_active_lane[i]),
|
1022 |
|
|
.RATE_RATE_IN (PIPE_RATE),
|
1023 |
|
|
.RATE_CPLLLOCK (gt_cplllock[i]),
|
1024 |
|
|
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
|
1025 |
|
|
.RATE_MMCM_LOCK (clk_mmcm_lock),
|
1026 |
|
|
.RATE_DRP_DONE (drp_done[i]),
|
1027 |
|
|
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
1028 |
|
|
.RATE_TXRESETDONE (gt_txresetdone[i]),
|
1029 |
|
|
.RATE_RXRESETDONE (gt_rxresetdone[i]),
|
1030 |
|
|
.RATE_TXRATEDONE (gt_txratedone[i]),
|
1031 |
|
|
.RATE_RXRATEDONE (gt_rxratedone[i]),
|
1032 |
|
|
.RATE_PHYSTATUS (gt_phystatus[i]),
|
1033 |
|
|
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
|
1034 |
|
|
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
|
1035 |
|
|
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
|
1036 |
|
|
|
1037 |
|
|
//---------- Output --------------------------------
|
1038 |
|
|
.RATE_CPLLPD (rate_cpllpd[i]),
|
1039 |
|
|
.RATE_QPLLPD (rate_qpllpd[i]),
|
1040 |
|
|
.RATE_CPLLRESET (rate_cpllreset[i]),
|
1041 |
|
|
.RATE_QPLLRESET (rate_qpllreset[i]),
|
1042 |
|
|
.RATE_TXPMARESET (rate_txpmareset[i]),
|
1043 |
|
|
.RATE_RXPMARESET (rate_rxpmareset[i]),
|
1044 |
|
|
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
1045 |
|
|
.RATE_DRP_START (rate_drp_start[i]),
|
1046 |
|
|
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
|
1047 |
|
|
.RATE_DRP_X16 (rate_drp_x16[i]),
|
1048 |
|
|
.RATE_PCLK_SEL (rate_pclk_sel[i]),
|
1049 |
|
|
.RATE_GEN3 (rate_gen3[i]),
|
1050 |
|
|
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
|
1051 |
|
|
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
|
1052 |
|
|
.RATE_TXSYNC_START (rate_txsync_start[i]),
|
1053 |
|
|
.RATE_DONE (rate_done[i]),
|
1054 |
|
|
.RATE_RXSYNC_START (rate_rxsync_start[i]),
|
1055 |
|
|
.RATE_RXSYNC (rate_rxsync[i]),
|
1056 |
|
|
.RATE_IDLE (rate_idle[i]),
|
1057 |
|
|
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
|
1058 |
|
|
|
1059 |
|
|
);
|
1060 |
|
|
|
1061 |
|
|
end
|
1062 |
|
|
|
1063 |
|
|
|
1064 |
|
|
|
1065 |
|
|
//---------- PIPE Sync Module ----------------------------------------------
|
1066 |
|
|
cl_a7pcie_x4_pipe_sync #
|
1067 |
|
|
(
|
1068 |
|
|
|
1069 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
|
1070 |
|
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
1071 |
|
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
|
1072 |
|
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
1073 |
|
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
|
1074 |
|
|
.PCIE_LANE (PCIE_LANE), // PCIe lane
|
1075 |
|
|
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
|
1076 |
|
|
|
1077 |
|
|
)
|
1078 |
|
|
pipe_sync_i
|
1079 |
|
|
(
|
1080 |
|
|
|
1081 |
|
|
//---------- Input ---------------------------------
|
1082 |
|
|
.SYNC_CLK (clk_pclk),
|
1083 |
|
|
.SYNC_RST_N (!rst_cpllreset),
|
1084 |
|
|
.SYNC_SLAVE (i > 0),
|
1085 |
|
|
.SYNC_GEN3 (rate_gen3[i]),
|
1086 |
|
|
.SYNC_RATE_IDLE (rate_idle[i]),
|
1087 |
|
|
.SYNC_MMCM_LOCK (clk_mmcm_lock),
|
1088 |
|
|
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
|
1089 |
|
|
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
|
1090 |
|
|
.SYNC_ACTIVE_LANE (user_active_lane[i]),
|
1091 |
|
|
|
1092 |
|
|
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
|
1093 |
|
|
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
|
1094 |
|
|
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
|
1095 |
|
|
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
|
1096 |
|
|
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
|
1097 |
|
|
|
1098 |
|
|
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
|
1099 |
|
|
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
|
1100 |
|
|
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
|
1101 |
|
|
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
|
1102 |
|
|
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
|
1103 |
|
|
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
|
1104 |
|
|
|
1105 |
|
|
//---------- Output --------------------------------
|
1106 |
|
|
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
|
1107 |
|
|
.SYNC_TXPHALIGN (sync_txphalign[i]),
|
1108 |
|
|
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
|
1109 |
|
|
.SYNC_TXPHINIT (sync_txphinit[i]),
|
1110 |
|
|
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
|
1111 |
|
|
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
|
1112 |
|
|
.SYNC_TXDLYEN (sync_txdlyen[i]),
|
1113 |
|
|
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
|
1114 |
|
|
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
|
1115 |
|
|
|
1116 |
|
|
.SYNC_RXPHALIGN (sync_rxphalign[i]),
|
1117 |
|
|
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
|
1118 |
|
|
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
|
1119 |
|
|
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
|
1120 |
|
|
.SYNC_RXDLYEN (sync_rxdlyen[i]),
|
1121 |
|
|
.SYNC_RXDDIEN (sync_rxddien[i]),
|
1122 |
|
|
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
|
1123 |
|
|
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
|
1124 |
|
|
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
|
1125 |
|
|
|
1126 |
|
|
);
|
1127 |
|
|
|
1128 |
|
|
//---------- PIPE Sync Assignments -----------------------------------------
|
1129 |
|
|
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
|
1130 |
|
|
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
|
1131 |
|
|
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
|
1132 |
|
|
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
|
1133 |
|
|
|
1134 |
|
|
|
1135 |
|
|
//---------- GTP PIPE DRP Module -------------------------------------------
|
1136 |
|
|
if (PCIE_GT_DEVICE == "GTP")
|
1137 |
|
|
|
1138 |
|
|
begin : gtp_pipe_drp
|
1139 |
|
|
|
1140 |
|
|
//---------- GTP PIPE DRP Module ---------------------------------------
|
1141 |
|
|
cl_a7pcie_x4_gtp_pipe_drp
|
1142 |
|
|
//(
|
1143 |
|
|
|
1144 |
|
|
//.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // removed for GTP
|
1145 |
|
|
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
|
1146 |
|
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
1147 |
|
|
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
|
1148 |
|
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
|
1149 |
|
|
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // removed for GTP
|
1150 |
|
|
//.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // removed for GTP
|
1151 |
|
|
//.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // removed for GTP
|
1152 |
|
|
|
1153 |
|
|
//)
|
1154 |
|
|
gtp_pipe_drp_i
|
1155 |
|
|
(
|
1156 |
|
|
|
1157 |
|
|
//---------- Input ---------------------------------
|
1158 |
|
|
.DRP_CLK (clk_dclk),
|
1159 |
|
|
.DRP_RST_N (!rst_dclk_reset),
|
1160 |
|
|
//.DRP_GTXRESET (rst_gtreset), // removed for GTP
|
1161 |
|
|
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
|
1162 |
|
|
//.DRP_RATE (PIPE_RATE), // removed for GTP
|
1163 |
|
|
.DRP_START (rst_drp_start || rate_drp_start[i]),
|
1164 |
|
|
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
|
1165 |
|
|
.DRP_RDY (gt_rdy[i]),
|
1166 |
|
|
|
1167 |
|
|
//---------- Output --------------------------------
|
1168 |
|
|
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
|
1169 |
|
|
.DRP_EN (drp_en[i]),
|
1170 |
|
|
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
|
1171 |
|
|
.DRP_WE (drp_we[i]),
|
1172 |
|
|
.DRP_DONE (drp_done[i]),
|
1173 |
|
|
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
|
1174 |
|
|
|
1175 |
|
|
);
|
1176 |
|
|
|
1177 |
|
|
end
|
1178 |
|
|
|
1179 |
|
|
else
|
1180 |
|
|
|
1181 |
|
|
begin : pipe_drp
|
1182 |
|
|
|
1183 |
|
|
//---------- PIPE DRP Module -------------------------------------------
|
1184 |
|
|
cl_a7pcie_x4_pipe_drp #
|
1185 |
|
|
(
|
1186 |
|
|
|
1187 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
1188 |
|
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
1189 |
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
1190 |
|
|
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
|
1191 |
|
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
1192 |
|
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
1193 |
|
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
|
1194 |
|
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
1195 |
|
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
|
1196 |
|
|
|
1197 |
|
|
)
|
1198 |
|
|
pipe_drp_i
|
1199 |
|
|
(
|
1200 |
|
|
|
1201 |
|
|
//---------- Input ---------------------------------
|
1202 |
|
|
.DRP_CLK (clk_dclk),
|
1203 |
|
|
.DRP_RST_N (!rst_dclk_reset),
|
1204 |
|
|
.DRP_GTXRESET (rst_gtreset),
|
1205 |
|
|
.DRP_RATE (PIPE_RATE),
|
1206 |
|
|
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
|
1207 |
|
|
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
|
1208 |
|
|
.DRP_START (rst_drp_start || rate_drp_start[i]),
|
1209 |
|
|
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
|
1210 |
|
|
.DRP_RDY (gt_rdy[i]),
|
1211 |
|
|
|
1212 |
|
|
//---------- Output --------------------------------
|
1213 |
|
|
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
|
1214 |
|
|
.DRP_EN (drp_en[i]),
|
1215 |
|
|
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
|
1216 |
|
|
.DRP_WE (drp_we[i]),
|
1217 |
|
|
.DRP_DONE (drp_done[i]),
|
1218 |
|
|
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
|
1219 |
|
|
|
1220 |
|
|
);
|
1221 |
|
|
|
1222 |
|
|
end
|
1223 |
|
|
|
1224 |
|
|
|
1225 |
|
|
|
1226 |
|
|
//---------- Generate PIPE JTAG Slave --------------------------------------
|
1227 |
|
|
if (PCIE_JTAG_MODE == 1)
|
1228 |
|
|
|
1229 |
|
|
begin : pipe_jtag_s
|
1230 |
|
|
|
1231 |
|
|
//-------------PIPE JTAG Slave Module ----------------------------------
|
1232 |
|
|
pipe_jtag_s #
|
1233 |
|
|
(
|
1234 |
|
|
|
1235 |
|
|
.GC_XSDB_SLAVE_TYPE (GC_XSDB_SLAVE_TYPE)
|
1236 |
|
|
|
1237 |
|
|
)
|
1238 |
|
|
pipe_jtag_s_i
|
1239 |
|
|
(
|
1240 |
|
|
|
1241 |
|
|
//---------- Connect to JTAG Master ------------
|
1242 |
|
|
.JTAG_SL_I_PORT (jtag_sl_iport[((i+1)*37)-1 : (i*37)]),
|
1243 |
|
|
.JTAG_SL_O_PORT (jtag_sl_oport[((i+1)*17)-1 : (i*17)]),
|
1244 |
|
|
|
1245 |
|
|
//---------- Input -----------------------------
|
1246 |
|
|
.JTAG_SL_DRDY (gt_rdy[i]),
|
1247 |
|
|
.JTAG_SL_DO (gt_do[(16*i)+15:(16*i)]),
|
1248 |
|
|
|
1249 |
|
|
//---------- Output ----------------------------
|
1250 |
|
|
.JTAG_SL_DCLK (),
|
1251 |
|
|
.JTAG_SL_ADDR (jtag_sl_addr[(17*i)+16:(17*i)]),
|
1252 |
|
|
.JTAG_SL_DEN (jtag_sl_den[i]),
|
1253 |
|
|
.JTAG_SL_DI (jtag_sl_di[(16*i)+15:(16*i)]),
|
1254 |
|
|
.JTAG_SL_DWE (jtag_sl_we[i])
|
1255 |
|
|
|
1256 |
|
|
);
|
1257 |
|
|
|
1258 |
|
|
end
|
1259 |
|
|
|
1260 |
|
|
else
|
1261 |
|
|
|
1262 |
|
|
//---------- PIPE JTAG Slave Default ----------------------------------
|
1263 |
|
|
begin : pipe_jtag_s_disable
|
1264 |
|
|
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
|
1265 |
|
|
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
|
1266 |
|
|
assign jtag_sl_den[i] = 1'd0;
|
1267 |
|
|
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
|
1268 |
|
|
assign jtag_sl_we[i] = 1'd0;
|
1269 |
|
|
end
|
1270 |
|
|
|
1271 |
|
|
//---------- Generate DRP MUX ----------------------------------------------
|
1272 |
|
|
assign PIPE_JTAG_RDY[i] = drp_fsm[3*i];
|
1273 |
|
|
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
|
1274 |
|
|
|
1275 |
|
|
assign drp_mux_addr[(9*i)+8:(9*i)] = PIPE_JTAG_EN ? jtag_sl_addr[(17*i)+8:(17*i)] : drp_addr[(9*i)+8:(9*i)];
|
1276 |
|
|
assign drp_mux_en[i] = PIPE_JTAG_EN ? jtag_sl_en[i] : drp_en[i];
|
1277 |
|
|
assign drp_mux_di[(16*i)+15:(16*i)] = PIPE_JTAG_EN ? jtag_sl_di[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
|
1278 |
|
|
assign drp_mux_we[i] = PIPE_JTAG_EN ? jtag_sl_we[i] : drp_we[i];
|
1279 |
|
|
|
1280 |
|
|
|
1281 |
|
|
|
1282 |
|
|
//---------- Generate PIPE EQ ----------------------------------------------
|
1283 |
|
|
if (PCIE_LINK_SPEED == 3)
|
1284 |
|
|
|
1285 |
|
|
begin : pipe_eq
|
1286 |
|
|
|
1287 |
|
|
//---------- PIPE EQ Module --------------------------------------------
|
1288 |
|
|
cl_a7pcie_x4_pipe_eq #
|
1289 |
|
|
(
|
1290 |
|
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
1291 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
|
1292 |
|
|
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
|
1293 |
|
|
)
|
1294 |
|
|
pipe_eq_i
|
1295 |
|
|
(
|
1296 |
|
|
|
1297 |
|
|
//---------- Input -----------------------------
|
1298 |
|
|
.EQ_CLK (clk_pclk),
|
1299 |
|
|
.EQ_RST_N (!rst_cpllreset),
|
1300 |
|
|
.EQ_GEN3 (rate_gen3[i]),
|
1301 |
|
|
|
1302 |
|
|
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
|
1303 |
|
|
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
|
1304 |
|
|
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
|
1305 |
|
|
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
|
1306 |
|
|
|
1307 |
|
|
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
|
1308 |
|
|
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
|
1309 |
|
|
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
|
1310 |
|
|
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
|
1311 |
|
|
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
|
1312 |
|
|
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
|
1313 |
|
|
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
|
1314 |
|
|
|
1315 |
|
|
//---------- Output ----------------------------
|
1316 |
|
|
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
|
1317 |
|
|
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
|
1318 |
|
|
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
|
1319 |
|
|
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
|
1320 |
|
|
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
|
1321 |
|
|
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
|
1322 |
|
|
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
|
1323 |
|
|
|
1324 |
|
|
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
|
1325 |
|
|
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
|
1326 |
|
|
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
|
1327 |
|
|
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
|
1328 |
|
|
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
|
1329 |
|
|
|
1330 |
|
|
);
|
1331 |
|
|
|
1332 |
|
|
end
|
1333 |
|
|
|
1334 |
|
|
else
|
1335 |
|
|
|
1336 |
|
|
//---------- PIPE EQ Defaults ------------------------------------------
|
1337 |
|
|
begin : pipe_eq_disable
|
1338 |
|
|
assign eq_txeq_deemph[i] = 1'd0;
|
1339 |
|
|
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
|
1340 |
|
|
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
|
1341 |
|
|
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
|
1342 |
|
|
assign eq_rxeq_adapt_done[i] = 1'd0;
|
1343 |
|
|
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
|
1344 |
|
|
assign PIPE_TXEQ_DONE[i] = 1'd0;
|
1345 |
|
|
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
|
1346 |
|
|
|
1347 |
|
|
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
|
1348 |
|
|
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
|
1349 |
|
|
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
|
1350 |
|
|
assign PIPE_RXEQ_DONE[i] = 1'd0;
|
1351 |
|
|
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
|
1352 |
|
|
end
|
1353 |
|
|
|
1354 |
|
|
|
1355 |
|
|
|
1356 |
|
|
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
|
1357 |
|
|
if ((i%4)==0)
|
1358 |
|
|
|
1359 |
|
|
begin : pipe_quad
|
1360 |
|
|
|
1361 |
|
|
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
|
1362 |
|
|
|
1363 |
|
|
begin : pipe_common
|
1364 |
|
|
|
1365 |
|
|
//---------- QPLL DRP Module ---------------------------------------
|
1366 |
|
|
cl_a7pcie_x4_qpll_drp #
|
1367 |
|
|
(
|
1368 |
|
|
|
1369 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
1370 |
|
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
1371 |
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
1372 |
|
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
|
1373 |
|
|
|
1374 |
|
|
)
|
1375 |
|
|
qpll_drp_i
|
1376 |
|
|
(
|
1377 |
|
|
|
1378 |
|
|
//---------- Input -------------------------
|
1379 |
|
|
.DRP_CLK (clk_dclk),
|
1380 |
|
|
.DRP_RST_N (!rst_dclk_reset),
|
1381 |
|
|
.DRP_OVRD (qrst_ovrd),
|
1382 |
|
|
.DRP_GEN3 (&rate_gen3),
|
1383 |
|
|
.DRP_QPLLLOCK (qpll_qplllock[i>>2]),
|
1384 |
|
|
.DRP_START (qrst_drp_start),
|
1385 |
|
|
.DRP_DO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
|
1386 |
|
|
.DRP_RDY (qpll_rdy[i>>2]),
|
1387 |
|
|
|
1388 |
|
|
//---------- Output ------------------------
|
1389 |
|
|
.DRP_ADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
|
1390 |
|
|
.DRP_EN (qdrp_en[i>>2]),
|
1391 |
|
|
.DRP_DI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
|
1392 |
|
|
.DRP_WE (qdrp_we[i>>2]),
|
1393 |
|
|
.DRP_DONE (qdrp_done[i>>2]),
|
1394 |
|
|
.DRP_QPLLRESET (qdrp_qpllreset[i>>2]),
|
1395 |
|
|
.DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
|
1396 |
|
|
.DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))])
|
1397 |
|
|
|
1398 |
|
|
);
|
1399 |
|
|
|
1400 |
|
|
|
1401 |
|
|
|
1402 |
|
|
//---------- QPLL Wrapper ------------------------------------------
|
1403 |
|
|
cl_a7pcie_x4_qpll_wrapper #
|
1404 |
|
|
(
|
1405 |
|
|
|
1406 |
|
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
1407 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
1408 |
|
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
1409 |
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
1410 |
|
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
|
1411 |
|
|
|
1412 |
|
|
)
|
1413 |
|
|
qpll_wrapper_i
|
1414 |
|
|
(
|
1415 |
|
|
|
1416 |
|
|
//---------- QPLL Clock Ports --------------
|
1417 |
|
|
.QPLL_GTGREFCLK (PIPE_CLK),
|
1418 |
|
|
.QPLL_QPLLLOCKDETCLK (1'd0),
|
1419 |
|
|
|
1420 |
|
|
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
|
1421 |
|
|
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
|
1422 |
|
|
.QPLL_QPLLLOCK (qpll_qplllock[i>>2]),
|
1423 |
|
|
|
1424 |
|
|
//---------- QPLL Reset Ports --------------
|
1425 |
|
|
.QPLL_QPLLPD (qpllpd),
|
1426 |
|
|
.QPLL_QPLLRESET (qpllreset[i>>2]),
|
1427 |
|
|
|
1428 |
|
|
//---------- QPLL DRP Ports ----------------
|
1429 |
|
|
.QPLL_DRPCLK (clk_dclk),
|
1430 |
|
|
.QPLL_DRPADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
|
1431 |
|
|
.QPLL_DRPEN (qdrp_en[i>>2]),
|
1432 |
|
|
.QPLL_DRPDI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
|
1433 |
|
|
.QPLL_DRPWE (qdrp_we[i>>2]),
|
1434 |
|
|
|
1435 |
|
|
.QPLL_DRPDO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
|
1436 |
|
|
.QPLL_DRPRDY (qpll_rdy[i>>2])
|
1437 |
|
|
|
1438 |
|
|
);
|
1439 |
|
|
|
1440 |
|
|
end
|
1441 |
|
|
|
1442 |
|
|
else
|
1443 |
|
|
|
1444 |
|
|
//---------- PIPE Common Defaults ----------------------------------
|
1445 |
|
|
begin : pipe_common_disable
|
1446 |
|
|
assign qdrp_addr[(8*(i>>2))+7:(8*(i>>2))] = 8'd0;
|
1447 |
|
|
assign qdrp_en[i>>2] = 1'd0;
|
1448 |
|
|
assign qdrp_di[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
|
1449 |
|
|
assign qdrp_we[i>>2] = 1'd0;
|
1450 |
|
|
assign qdrp_done[i>>2] = 1'd0;
|
1451 |
|
|
assign qdrp_qpllreset[i>>2] = 1'd0;
|
1452 |
|
|
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
|
1453 |
|
|
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 7'd0;
|
1454 |
|
|
|
1455 |
|
|
assign qpll_qplloutclk[i>>2] = 1'd0;
|
1456 |
|
|
assign qpll_qplloutrefclk[i>>2] = 1'd0;
|
1457 |
|
|
assign qpll_qplllock[i>>2] = 1'd0;
|
1458 |
|
|
assign qpll_do[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
|
1459 |
|
|
assign qpll_rdy[i>>2] = 1'd0;
|
1460 |
|
|
end
|
1461 |
|
|
|
1462 |
|
|
|
1463 |
|
|
//---------- Generate QPLL Powerdown and Reset -------------------------
|
1464 |
|
|
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
|
1465 |
|
|
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
|
1466 |
|
|
|
1467 |
|
|
end
|
1468 |
|
|
|
1469 |
|
|
|
1470 |
|
|
|
1471 |
|
|
//---------- GT Wrapper ----------------------------------------------------
|
1472 |
|
|
cl_a7pcie_x4_gt_wrapper #
|
1473 |
|
|
(
|
1474 |
|
|
|
1475 |
|
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
1476 |
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
|
1477 |
|
|
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
|
1478 |
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
1479 |
|
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
1480 |
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
1481 |
|
|
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
|
1482 |
|
|
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
|
1483 |
|
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
1484 |
|
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
1485 |
|
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
1486 |
|
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
|
1487 |
|
|
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
|
1488 |
|
|
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
|
1489 |
|
|
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
|
1490 |
|
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
|
1491 |
|
|
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
|
1492 |
|
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
|
1493 |
|
|
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
|
1494 |
|
|
|
1495 |
|
|
)
|
1496 |
|
|
gt_wrapper_i
|
1497 |
|
|
(
|
1498 |
|
|
|
1499 |
|
|
//---------- GT User Ports -------------------------
|
1500 |
|
|
.GT_MASTER (i == 0),
|
1501 |
|
|
.GT_GEN3 (rate_gen3[i]),
|
1502 |
|
|
.GT_RX_CONVERGE (&user_rx_converge),
|
1503 |
|
|
|
1504 |
|
|
//---------- GT Clock Ports ------------------------
|
1505 |
|
|
.GT_GTREFCLK0 (PIPE_CLK),
|
1506 |
|
|
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
|
1507 |
|
|
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
|
1508 |
|
|
.GT_TXUSRCLK (clk_pclk),
|
1509 |
|
|
.GT_RXUSRCLK (clk_rxusrclk),
|
1510 |
|
|
.GT_TXUSRCLK2 (clk_pclk),
|
1511 |
|
|
.GT_RXUSRCLK2 (clk_rxusrclk),
|
1512 |
|
|
.GT_OOBCLK (oobclk[i]),
|
1513 |
|
|
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
1514 |
|
|
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
1515 |
|
|
|
1516 |
|
|
.GT_TXOUTCLK (gt_txoutclk[i]),
|
1517 |
|
|
.GT_RXOUTCLK (gt_rxoutclk[i]),
|
1518 |
|
|
.GT_CPLLLOCK (gt_cplllock[i]),
|
1519 |
|
|
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
|
1520 |
|
|
|
1521 |
|
|
//---------- GT Reset Ports ------------------------
|
1522 |
|
|
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
|
1523 |
|
|
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
|
1524 |
|
|
.GT_TXUSERRDY (rst_userrdy),
|
1525 |
|
|
.GT_RXUSERRDY (rst_userrdy),
|
1526 |
|
|
.GT_RESETOVRD (user_resetovrd[i]),
|
1527 |
|
|
.GT_GTTXRESET (rst_gtreset),
|
1528 |
|
|
.GT_GTRXRESET (rst_gtreset),
|
1529 |
|
|
.GT_TXPMARESET (user_txpmareset[i] || rate_txpmareset[i]),
|
1530 |
|
|
.GT_RXPMARESET (user_rxpmareset[i] || rate_rxpmareset[i]),
|
1531 |
|
|
.GT_RXCDRRESET (user_rxcdrreset[i]),
|
1532 |
|
|
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
|
1533 |
|
|
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
|
1534 |
|
|
.GT_EYESCANRESET (user_eyescanreset[i]),
|
1535 |
|
|
.GT_TXPCSRESET (user_txpcsreset[i]),
|
1536 |
|
|
.GT_RXPCSRESET (user_rxpcsreset[i]),
|
1537 |
|
|
.GT_RXBUFRESET (user_rxbufreset[i]),
|
1538 |
|
|
|
1539 |
|
|
.GT_TXRESETDONE (gt_txresetdone[i]),
|
1540 |
|
|
.GT_RXRESETDONE (gt_rxresetdone[i]),
|
1541 |
|
|
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
1542 |
|
|
|
1543 |
|
|
//---------- GT TX Data Ports ----------------------
|
1544 |
|
|
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
|
1545 |
|
|
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
|
1546 |
|
|
|
1547 |
|
|
.GT_TXP (PIPE_TXP[i]),
|
1548 |
|
|
.GT_TXN (PIPE_TXN[i]),
|
1549 |
|
|
|
1550 |
|
|
//---------- GT RX Data Ports ----------------------
|
1551 |
|
|
.GT_RXP (PIPE_RXP[i]),
|
1552 |
|
|
.GT_RXN (PIPE_RXN[i]),
|
1553 |
|
|
|
1554 |
|
|
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
|
1555 |
|
|
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
|
1556 |
|
|
|
1557 |
|
|
//---------- GT Command Ports ----------------------
|
1558 |
|
|
.GT_TXDETECTRX (PIPE_TXDETECTRX),
|
1559 |
|
|
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
|
1560 |
|
|
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
|
1561 |
|
|
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
|
1562 |
|
|
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
|
1563 |
|
|
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
|
1564 |
|
|
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
|
1565 |
|
|
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
|
1566 |
|
|
|
1567 |
|
|
//---------- GT Electrical Command Ports -----------
|
1568 |
|
|
.GT_TXMARGIN (PIPE_TXMARGIN),
|
1569 |
|
|
.GT_TXSWING (PIPE_TXSWING),
|
1570 |
|
|
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
|
1571 |
|
|
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
|
1572 |
|
|
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
|
1573 |
|
|
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
|
1574 |
|
|
|
1575 |
|
|
//---------- GT Status Ports -----------------------
|
1576 |
|
|
.GT_RXVALID (gt_rxvalid[i]),
|
1577 |
|
|
.GT_PHYSTATUS (gt_phystatus[i]),
|
1578 |
|
|
.GT_RXELECIDLE (gt_rxelecidle[i]),
|
1579 |
|
|
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
|
1580 |
|
|
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
|
1581 |
|
|
.GT_TXRATEDONE (gt_txratedone[i]),
|
1582 |
|
|
.GT_RXRATEDONE (gt_rxratedone[i]),
|
1583 |
|
|
|
1584 |
|
|
//---------- GT DRP Ports --------------------------
|
1585 |
|
|
.GT_DRPCLK (clk_dclk),
|
1586 |
|
|
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
|
1587 |
|
|
.GT_DRPEN (drp_mux_en[i]),
|
1588 |
|
|
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
|
1589 |
|
|
.GT_DRPWE (drp_mux_we[i]),
|
1590 |
|
|
|
1591 |
|
|
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
|
1592 |
|
|
.GT_DRPRDY (gt_rdy[i]),
|
1593 |
|
|
|
1594 |
|
|
//---------- GT TX Sync Ports ----------------------
|
1595 |
|
|
.GT_TXPHALIGN (sync_txphalign[i]),
|
1596 |
|
|
.GT_TXPHALIGNEN (sync_txphalignen[i]),
|
1597 |
|
|
.GT_TXPHINIT (sync_txphinit[i]),
|
1598 |
|
|
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
|
1599 |
|
|
.GT_TXDLYSRESET (sync_txdlysreset[i]),
|
1600 |
|
|
.GT_TXDLYEN (sync_txdlyen[i]),
|
1601 |
|
|
|
1602 |
|
|
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
|
1603 |
|
|
.GT_TXPHINITDONE (gt_txphinitdone[i]),
|
1604 |
|
|
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
|
1605 |
|
|
|
1606 |
|
|
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
|
1607 |
|
|
.GT_TXSYNCMODE (i == 0), // GTH, GTP
|
1608 |
|
|
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
|
1609 |
|
|
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
|
1610 |
|
|
|
1611 |
|
|
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
|
1612 |
|
|
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
|
1613 |
|
|
|
1614 |
|
|
//---------- GT RX Sync Ports ----------------------
|
1615 |
|
|
.GT_RXPHALIGN (sync_rxphalign[i]),
|
1616 |
|
|
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
|
1617 |
|
|
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
|
1618 |
|
|
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
|
1619 |
|
|
.GT_RXDLYEN (sync_rxdlyen[i]),
|
1620 |
|
|
.GT_RXDDIEN (sync_rxddien[i]),
|
1621 |
|
|
|
1622 |
|
|
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
|
1623 |
|
|
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
|
1624 |
|
|
|
1625 |
|
|
.GT_RXSYNCMODE (i == 0), // GTH
|
1626 |
|
|
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
|
1627 |
|
|
.GT_RXSYNCALLIN (rxsyncallin), // GTH
|
1628 |
|
|
|
1629 |
|
|
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
|
1630 |
|
|
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
|
1631 |
|
|
|
1632 |
|
|
//---------- GT Comma Alignment Ports --------------
|
1633 |
|
|
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
|
1634 |
|
|
|
1635 |
|
|
.GT_RXCOMMADET (gt_rxcommadet[i]),
|
1636 |
|
|
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
|
1637 |
|
|
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
|
1638 |
|
|
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
|
1639 |
|
|
|
1640 |
|
|
//---------- GT Channel Bonding Ports --------------
|
1641 |
|
|
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
|
1642 |
|
|
.GT_RXCHBONDEN (rxchbonden[i]),
|
1643 |
|
|
.GT_RXCHBONDI (gt_rxchbondi[i]),
|
1644 |
|
|
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
|
1645 |
|
|
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
|
1646 |
|
|
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
|
1647 |
|
|
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
|
1648 |
|
|
|
1649 |
|
|
//---------- GT PRBS/Loopback Ports ----------------
|
1650 |
|
|
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
|
1651 |
|
|
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
|
1652 |
|
|
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
|
1653 |
|
|
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
|
1654 |
|
|
.GT_LOOPBACK (PIPE_LOOPBACK),
|
1655 |
|
|
|
1656 |
|
|
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
|
1657 |
|
|
|
1658 |
|
|
//---------- GT Debug Port -------------------------
|
1659 |
|
|
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
|
1660 |
|
|
|
1661 |
|
|
);
|
1662 |
|
|
|
1663 |
|
|
|
1664 |
|
|
|
1665 |
|
|
//---------- GT Wrapper Assignments ----------------------------------------
|
1666 |
|
|
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
|
1667 |
|
|
|
1668 |
|
|
//---------- Channel Bonding Master Slave Enable ---------------------------
|
1669 |
|
|
if (PCIE_CHAN_BOND_EN == "FALSE")
|
1670 |
|
|
begin : channel_bonding_ms_disable
|
1671 |
|
|
assign rxchbonden[i] = 1'd0;
|
1672 |
|
|
assign rxchbondmaster[i] = 1'd0;
|
1673 |
|
|
assign rxchbondslave[i] = 1'd0;
|
1674 |
|
|
end
|
1675 |
|
|
else
|
1676 |
|
|
begin : channel_bonding_ms_enable
|
1677 |
|
|
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
|
1678 |
|
|
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
|
1679 |
|
|
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
|
1680 |
|
|
end
|
1681 |
|
|
|
1682 |
|
|
//---------- Channel Bonding Input Connection ------------------------------
|
1683 |
|
|
if (PCIE_CHAN_BOND_EN == "FALSE")
|
1684 |
|
|
begin : channel_bonding_in_disable
|
1685 |
|
|
assign gt_rxchbondi[i] = 5'd0;
|
1686 |
|
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
|
1687 |
|
|
end
|
1688 |
|
|
else
|
1689 |
|
|
begin : channel_bonding_in_enable
|
1690 |
|
|
|
1691 |
|
|
//---------- Channel Bonding (2: Binary-Tree) --------------------------
|
1692 |
|
|
if (PCIE_CHAN_BOND == 2)
|
1693 |
|
|
|
1694 |
|
|
begin : channel_bonding_a
|
1695 |
|
|
|
1696 |
|
|
case (i)
|
1697 |
|
|
|
1698 |
|
|
//---------- Lane 0 --------------------------------
|
1699 |
|
|
|
1700 |
|
|
begin
|
1701 |
|
|
assign gt_rxchbondi[0] = gt_rxchbondo[0];
|
1702 |
|
|
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
|
1703 |
|
|
(PCIE_LANE > 4'd5) ? 3'd3 :
|
1704 |
|
|
(PCIE_LANE > 4'd3) ? 3'd2 :
|
1705 |
|
|
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
|
1706 |
|
|
end
|
1707 |
|
|
//---------- Lane 1 --------------------------------
|
1708 |
|
|
1 :
|
1709 |
|
|
begin
|
1710 |
|
|
assign gt_rxchbondi[1] = gt_rxchbondo[1];
|
1711 |
|
|
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
|
1712 |
|
|
(PCIE_LANE > 4'd5) ? 3'd2 :
|
1713 |
|
|
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
|
1714 |
|
|
end
|
1715 |
|
|
//---------- Lane 2 --------------------------------
|
1716 |
|
|
2 :
|
1717 |
|
|
begin
|
1718 |
|
|
assign gt_rxchbondi[2] = gt_rxchbondo[1];
|
1719 |
|
|
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
|
1720 |
|
|
(PCIE_LANE > 4'd5) ? 3'd2 :
|
1721 |
|
|
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
|
1722 |
|
|
end
|
1723 |
|
|
//---------- Lane 3 --------------------------------
|
1724 |
|
|
3 :
|
1725 |
|
|
begin
|
1726 |
|
|
assign gt_rxchbondi[3] = gt_rxchbondo[3];
|
1727 |
|
|
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
|
1728 |
|
|
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
|
1729 |
|
|
end
|
1730 |
|
|
//---------- Lane 4 --------------------------------
|
1731 |
|
|
4 :
|
1732 |
|
|
begin
|
1733 |
|
|
assign gt_rxchbondi[4] = gt_rxchbondo[3];
|
1734 |
|
|
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
|
1735 |
|
|
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
|
1736 |
|
|
end
|
1737 |
|
|
//---------- Lane 5 --------------------------------
|
1738 |
|
|
5 :
|
1739 |
|
|
begin
|
1740 |
|
|
assign gt_rxchbondi[5] = gt_rxchbondo[5];
|
1741 |
|
|
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
|
1742 |
|
|
end
|
1743 |
|
|
//---------- Lane 6 --------------------------------
|
1744 |
|
|
6 :
|
1745 |
|
|
begin
|
1746 |
|
|
assign gt_rxchbondi[6] = gt_rxchbondo[5];
|
1747 |
|
|
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
|
1748 |
|
|
end
|
1749 |
|
|
//---------- Lane 7 --------------------------------
|
1750 |
|
|
7 :
|
1751 |
|
|
begin
|
1752 |
|
|
assign gt_rxchbondi[7] = gt_rxchbondo[7];
|
1753 |
|
|
assign gt_rxchbondlevel[23:21] = 3'd0;
|
1754 |
|
|
end
|
1755 |
|
|
//---------- Default -------------------------------
|
1756 |
|
|
default :
|
1757 |
|
|
begin
|
1758 |
|
|
assign gt_rxchbondi[i] = gt_rxchbondo[7];
|
1759 |
|
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
|
1760 |
|
|
end
|
1761 |
|
|
|
1762 |
|
|
endcase
|
1763 |
|
|
|
1764 |
|
|
end
|
1765 |
|
|
|
1766 |
|
|
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
|
1767 |
|
|
else
|
1768 |
|
|
|
1769 |
|
|
begin : channel_bonding_b
|
1770 |
|
|
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
|
1771 |
|
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
|
1772 |
|
|
end
|
1773 |
|
|
|
1774 |
|
|
end
|
1775 |
|
|
|
1776 |
|
|
end
|
1777 |
|
|
|
1778 |
|
|
endgenerate
|
1779 |
|
|
|
1780 |
|
|
|
1781 |
|
|
|
1782 |
|
|
//---------- PIPE Wrapper Output -----------------------------------------------
|
1783 |
|
|
assign PIPE_TXEQ_FS = 0;//TXEQ_FS;
|
1784 |
|
|
assign PIPE_TXEQ_LF = 0;//TXEQ_LF;
|
1785 |
|
|
assign PIPE_RXELECIDLE = gt_rxelecidle;
|
1786 |
|
|
assign PIPE_RXSTATUS = gt_rxstatus;
|
1787 |
|
|
assign PIPE_RXBUFSTATUS = 0;//gt_rxbufstatus;
|
1788 |
|
|
|
1789 |
|
|
assign PIPE_CPLL_LOCK = gt_cplllock;
|
1790 |
|
|
assign PIPE_QPLL_LOCK = 0;//qpll_qplllock;
|
1791 |
|
|
assign PIPE_PCLK = clk_pclk;
|
1792 |
|
|
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
|
1793 |
|
|
assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock;
|
1794 |
|
|
assign PIPE_RXUSRCLK = 0;//clk_rxusrclk;
|
1795 |
|
|
assign PIPE_RXOUTCLK = 0;//clk_rxoutclk;
|
1796 |
|
|
assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done;
|
1797 |
|
|
assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done;
|
1798 |
|
|
assign PIPE_ACTIVE_LANE = 0;//user_active_lane;
|
1799 |
|
|
|
1800 |
|
|
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
|
1801 |
|
|
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
|
1802 |
|
|
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
|
1803 |
|
|
assign PIPE_GEN3_OUT = rate_gen3[0];
|
1804 |
|
|
|
1805 |
|
|
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
|
1806 |
|
|
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
|
1807 |
|
|
|
1808 |
|
|
assign PIPE_RST_FSM = 0;//rst_fsm;
|
1809 |
|
|
assign PIPE_QRST_FSM = 0;//qrst_fsm;
|
1810 |
|
|
assign PIPE_RATE_FSM = 0;//rate_fsm;
|
1811 |
|
|
assign PIPE_SYNC_FSM_TX = 0;//sync_fsm_tx;
|
1812 |
|
|
assign PIPE_SYNC_FSM_RX = 0;//sync_fsm_rx;
|
1813 |
|
|
assign PIPE_DRP_FSM = 0;//drp_fsm;
|
1814 |
|
|
assign PIPE_QDRP_FSM = 0;//qdrp_fsm;
|
1815 |
|
|
|
1816 |
|
|
assign PIPE_RST_IDLE = 0;//&rst_idle;
|
1817 |
|
|
assign PIPE_QRST_IDLE = 0;//&qrst_idle;
|
1818 |
|
|
assign PIPE_RATE_IDLE = 0;//&rate_idle;
|
1819 |
|
|
|
1820 |
|
|
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
|
1821 |
|
|
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
|
1822 |
|
|
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
|
1823 |
|
|
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
|
1824 |
|
|
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
|
1825 |
|
|
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
|
1826 |
|
|
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
|
1827 |
|
|
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
|
1828 |
|
|
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
|
1829 |
|
|
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
|
1830 |
|
|
|
1831 |
|
|
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
|
1832 |
|
|
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
|
1833 |
|
|
assign PIPE_DEBUG[31:6] = 26'd0;
|
1834 |
|
|
|
1835 |
|
|
|
1836 |
|
|
|
1837 |
|
|
endmodule
|