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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_qpll_wrapper.v
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// Version : 1.10
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//------------------------------------------------------------------------------
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// Filename : qpll_wrapper.v
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// Description : QPLL Wrapper Module for 7 Series Transceiver
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// Version : 18.1
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- QPLL Wrapper ----------------------------------------------------
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module cl_a7pcie_x4_qpll_wrapper #
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(
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
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)
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(
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//---------- QPLL Clock Ports --------------------------
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input QPLL_GTGREFCLK,
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input QPLL_QPLLLOCKDETCLK,
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output QPLL_QPLLOUTCLK,
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output QPLL_QPLLOUTREFCLK,
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output QPLL_QPLLLOCK,
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//---------- QPLL Reset Ports --------------------------
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input QPLL_QPLLPD,
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input QPLL_QPLLRESET,
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//---------- QPLL DRP Ports ----------------------------
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input QPLL_DRPCLK,
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input [ 7:0] QPLL_DRPADDR,
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input QPLL_DRPEN,
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input [15:0] QPLL_DRPDI,
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input QPLL_DRPWE,
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output [15:0] QPLL_DRPDO,
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output QPLL_DRPRDY
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);
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//---------- Select QPLL Feedback Divider --------------
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// N = 100 for 100 MHz ref clk and 10Gb/s line rate
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// N = 80 for 125 MHz ref clk and 10Gb/s line rate
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// N = 40 for 250 MHz ref clk and 10Gb/s line rate
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//------------------------------------------------------
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// N = 80 for 100 MHz ref clk and 8Gb/s line rate
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// N = 64 for 125 MHz ref clk and 8Gb/s line rate
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// N = 32 for 250 MHz ref clk and 8Gb/s line rate
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//------------------------------------------------------
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localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 10'b0010000000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 10'b0100100000 :
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(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 10'b0101110000 :
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(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 10'b0001100000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 10'b0011100000 : 10'b0100100000;
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//---------- Select GTP QPLL Feedback Divider ----------
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localparam GTP_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 3'd2 :
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(PCIE_REFCLK_FREQ == 1) ? 3'd4 : 3'd5;
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//---------- Select BIAS_CFG ---------------------------
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localparam BIAS_CFG = ((PCIE_USE_MODE == "1.0") && (PCIE_PLL_SEL == "CPLL")) ? 64'h0000042000001000 : 64'h0000040000001000;
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//---------- Select GTX or GTH or GTP ------------------------------------------
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// Notes : Attributes that are commented out uses the GT default settings
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//------------------------------------------------------------------------------
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generate if (PCIE_GT_DEVICE == "GTP")
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//---------- GTP Common ----------------------------------------------------
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begin : gtp_common
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//---------- GTP Common Module ---------------------------------------------
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GTPE2_COMMON #
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(
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//---------- Simulation Attributes -------------------------------------
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.SIM_PLL0REFCLK_SEL (3'b001), //
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.SIM_PLL1REFCLK_SEL (3'b001), //
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.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
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.SIM_VERSION (PCIE_USE_MODE), //
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//---------- Clock Attributes ------------------------------------------
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.PLL0_CFG (27'h01F024C), // Optimized for IES
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.PLL1_CFG (27'h01F024C), // Optimized for IES
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.PLL_CLKOUT_CFG (8'd0), // Optimized for IES
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.PLL0_DMON_CFG (1'b0), // Optimized for IES
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.PLL1_DMON_CFG (1'b0), // Optimized for IES
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.PLL0_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES
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.PLL1_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES
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.PLL0_FBDIV_45 (5), // Optimized for IES
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.PLL1_FBDIV_45 (5), // Optimized for IES
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.PLL0_INIT_CFG (24'h00001E), // Optimized for IES
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.PLL1_INIT_CFG (24'h00001E), // Optimized for IES
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.PLL0_LOCK_CFG ( 9'h1E8), // Optimized for IES
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.PLL1_LOCK_CFG ( 9'h1E8), // Optimized for IES
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.PLL0_REFCLK_DIV (1), // Optimized for IES
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.PLL1_REFCLK_DIV (1), // Optimized for IES
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//---------- MISC ------------------------------------------------------
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.BIAS_CFG (64'h0000000000050001), // Optimized for GES
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//.COMMON_CFG (32'd0), //
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.RSVD_ATTR0 (16'd0), //
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.RSVD_ATTR1 (16'd0) //
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)
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gtpe2_common_i
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(
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//---------- Clock -----------------------------------------------------
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.GTGREFCLK0 ( 1'd0), //
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.GTGREFCLK1 ( 1'd0), //
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.GTREFCLK0 (QPLL_GTGREFCLK), //
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.GTREFCLK1 ( 1'd0), //
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.GTEASTREFCLK0 ( 1'd0), //
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.GTEASTREFCLK1 ( 1'd0), //
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.GTWESTREFCLK0 ( 1'd0), //
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.GTWESTREFCLK1 ( 1'd0), //
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.PLL0LOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
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.PLL1LOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
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.PLL0LOCKEN ( 1'd1), //
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.PLL1LOCKEN ( 1'd1), //
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.PLL0REFCLKSEL ( 3'd1), // Optimized for IES
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.PLL1REFCLKSEL ( 3'd1), // Optimized for IES
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.PLLRSVD1 (16'd0), // Optimized for IES
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.PLLRSVD2 ( 5'd0), // Optimized for IES
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.PLL0OUTCLK (QPLL_QPLLOUTCLK), //
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.PLL1OUTCLK (), //
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.PLL0OUTREFCLK (QPLL_QPLLOUTREFCLK), //
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.PLL1OUTREFCLK (), //
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.PLL0LOCK (QPLL_QPLLLOCK), //
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.PLL1LOCK (), //
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.PLL0FBCLKLOST (), //
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.PLL1FBCLKLOST (), //
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.PLL0REFCLKLOST (), //
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.PLL1REFCLKLOST (), //
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.DMONITOROUT (), //
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//---------- Reset -----------------------------------------------------
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.PLL0PD (QPLL_QPLLPD), //
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.PLL1PD ( 1'd1), //
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.PLL0RESET (QPLL_QPLLRESET), //
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.PLL1RESET ( 1'd1), //
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//---------- DRP -------------------------------------------------------
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.DRPCLK (QPLL_DRPCLK), //
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.DRPADDR (QPLL_DRPADDR), //
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.DRPEN (QPLL_DRPEN), //
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.DRPDI (QPLL_DRPDI), //
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.DRPWE (QPLL_DRPWE), //
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.DRPDO (QPLL_DRPDO), //
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.DRPRDY (QPLL_DRPRDY), //
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//---------- Band Gap --------------------------------------------------
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.BGBYPASSB ( 1'd1), // Optimized for IES
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.BGMONITORENB ( 1'd1), // Optimized for IES
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.BGPDB ( 1'd1), // Optimized for IES
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.BGRCALOVRD ( 5'd31), // Optimized for IES
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.BGRCALOVRDENB ( 1'd1), // Optimized for IES
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//---------- MISC ------------------------------------------------------
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.PMARSVD ( 8'd0), //
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.RCALENB ( 1'd1), // Optimized for IES
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.REFCLKOUTMONITOR0 (), //
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.REFCLKOUTMONITOR1 (), //
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.PMARSVDOUT () //
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);
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end
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else if (PCIE_GT_DEVICE == "GTH")
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//---------- GTH Common ----------------------------------------------------
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begin : gth_common
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//---------- GTX Common Module ---------------------------------------------
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GTHE2_COMMON #
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(
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//---------- Simulation Attributes -------------------------------------
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.SIM_QPLLREFCLK_SEL (3'b001), //
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.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
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.SIM_VERSION ("2.0"), //
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//---------- Clock Attributes ------------------------------------------
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.QPLL_CFG (27'h04801C7), // QPLL for Gen3, optimized for GES
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.QPLL_CLKOUT_CFG ( 4'b1111), // Optimized for GES
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.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
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.QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), //
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.QPLL_CP (10'h0FF), // * Optimized for IES and PCIe PLL BW
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.QPLL_CP_MONITOR_EN ( 1'd0), //
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.QPLL_DMONITOR_SEL ( 1'd0), //
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.QPLL_FBDIV (QPLL_FBDIV), //
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.QPLL_FBDIV_MONITOR_EN ( 1'd0), //
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.QPLL_FBDIV_RATIO ( 1'd1), // Optimized
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.QPLL_INIT_CFG (24'h000006), //
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.QPLL_LOCK_CFG (16'h05E8), // Optimized for IES
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.QPLL_LPF ( 4'hD), // Optimized for IES, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
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.QPLL_REFCLK_DIV ( 1), //
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.QPLL_RP_COMP ( 1'd0), // GTH new
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.QPLL_VTRL_RESET ( 2'd0), // GTH new
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//---------- MISC ------------------------------------------------------
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.BIAS_CFG (64'h0000040000001050), // Optimized for GES
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.COMMON_CFG (32'd0), //
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.RCAL_CFG ( 2'b00), // GTH new
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.RSVD_ATTR0 (16'd0), // GTH
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.RSVD_ATTR1 (16'd0) // GTH
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)
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gthe2_common_i
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(
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//---------- Clock -----------------------------------------------------
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.GTGREFCLK ( 1'd0), //
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.GTREFCLK0 (QPLL_GTGREFCLK), //
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.GTREFCLK1 ( 1'd0), //
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.GTNORTHREFCLK0 ( 1'd0), //
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.GTNORTHREFCLK1 ( 1'd0), //
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.GTSOUTHREFCLK0 ( 1'd0), //
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.GTSOUTHREFCLK1 ( 1'd0), //
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.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
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.QPLLLOCKEN ( 1'd1), //
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.QPLLREFCLKSEL ( 3'd1), //
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.QPLLRSVD1 (16'd0), //
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.QPLLRSVD2 ( 5'b11111), //
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.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
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.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
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.QPLLLOCK (QPLL_QPLLLOCK), //
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.QPLLFBCLKLOST (), //
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.QPLLREFCLKLOST (), //
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.QPLLDMONITOR (), //
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//---------- Reset -----------------------------------------------------
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.QPLLPD (QPLL_QPLLPD), //
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.QPLLRESET (QPLL_QPLLRESET), //
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.QPLLOUTRESET ( 1'd0), //
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| 307 |
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//---------- DRP -------------------------------------------------------
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.DRPCLK (QPLL_DRPCLK), //
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.DRPADDR (QPLL_DRPADDR), //
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.DRPEN (QPLL_DRPEN), //
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.DRPDI (QPLL_DRPDI), //
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.DRPWE (QPLL_DRPWE), //
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| 313 |
|
|
|
| 314 |
|
|
.DRPDO (QPLL_DRPDO), //
|
| 315 |
|
|
.DRPRDY (QPLL_DRPRDY), //
|
| 316 |
|
|
|
| 317 |
|
|
//---------- Band Gap --------------------------------------------------
|
| 318 |
|
|
.BGBYPASSB ( 1'd1), // Optimized for IES
|
| 319 |
|
|
.BGMONITORENB ( 1'd1), // Optimized for IES
|
| 320 |
|
|
.BGPDB ( 1'd1), // Optimized for IES
|
| 321 |
|
|
.BGRCALOVRD ( 5'd31), // Optimized for IES
|
| 322 |
|
|
.BGRCALOVRDENB ( 1'd1), // GTH, Optimized for IES
|
| 323 |
|
|
|
| 324 |
|
|
//---------- MISC ------------------------------------------------------
|
| 325 |
|
|
.PMARSVD ( 8'd0), //
|
| 326 |
|
|
.RCALENB ( 1'd1), // Optimized for IES
|
| 327 |
|
|
|
| 328 |
|
|
.REFCLKOUTMONITOR (), //
|
| 329 |
|
|
.PMARSVDOUT () // GTH
|
| 330 |
|
|
|
| 331 |
|
|
);
|
| 332 |
|
|
|
| 333 |
|
|
end
|
| 334 |
|
|
|
| 335 |
|
|
else
|
| 336 |
|
|
|
| 337 |
|
|
//---------- GTX Common ----------------------------------------------------
|
| 338 |
|
|
begin : gtx_common
|
| 339 |
|
|
|
| 340 |
|
|
//---------- GTX Common Module ---------------------------------------------
|
| 341 |
|
|
GTXE2_COMMON #
|
| 342 |
|
|
(
|
| 343 |
|
|
|
| 344 |
|
|
//---------- Simulation Attributes -------------------------------------
|
| 345 |
|
|
.SIM_QPLLREFCLK_SEL ( 3'b001), //
|
| 346 |
|
|
.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
|
| 347 |
|
|
.SIM_VERSION (PCIE_USE_MODE), //
|
| 348 |
|
|
|
| 349 |
|
|
//---------- Clock Attributes ------------------------------------------
|
| 350 |
|
|
.QPLL_CFG (27'h06801C1), // QPLL for Gen3, Optimized for silicon,
|
| 351 |
|
|
//.QPLL_CLKOUT_CFG ( 4'd0), //
|
| 352 |
|
|
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
|
| 353 |
|
|
.QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), //
|
| 354 |
|
|
.QPLL_CP (10'h01F), // Optimized for Gen3 compliance (Gen1/Gen2 = 10'h1FF)
|
| 355 |
|
|
.QPLL_CP_MONITOR_EN ( 1'd0), //
|
| 356 |
|
|
.QPLL_DMONITOR_SEL ( 1'd0), //
|
| 357 |
|
|
.QPLL_FBDIV (QPLL_FBDIV), //
|
| 358 |
|
|
.QPLL_FBDIV_MONITOR_EN ( 1'd0), //
|
| 359 |
|
|
.QPLL_FBDIV_RATIO ( 1'd1), // Optimized for silicon
|
| 360 |
|
|
//.QPLL_INIT_CFG (24'h000006), //
|
| 361 |
|
|
.QPLL_LOCK_CFG (16'h21E8), // Optimized for silicon, IES = 16'h01D0, GES 16'h21D0
|
| 362 |
|
|
.QPLL_LPF ( 4'hD), // Optimized for silicon, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
|
| 363 |
|
|
.QPLL_REFCLK_DIV (1), //
|
| 364 |
|
|
|
| 365 |
|
|
//---------- MISC ------------------------------------------------------
|
| 366 |
|
|
.BIAS_CFG (BIAS_CFG) // Optimized for silicon
|
| 367 |
|
|
//.COMMON_CFG (32'd0) //
|
| 368 |
|
|
|
| 369 |
|
|
)
|
| 370 |
|
|
gtxe2_common_i
|
| 371 |
|
|
(
|
| 372 |
|
|
|
| 373 |
|
|
//---------- Clock -----------------------------------------------------
|
| 374 |
|
|
.GTGREFCLK ( 1'd0), //
|
| 375 |
|
|
.GTREFCLK0 (QPLL_GTGREFCLK), //
|
| 376 |
|
|
.GTREFCLK1 ( 1'd0), //
|
| 377 |
|
|
.GTNORTHREFCLK0 ( 1'd0), //
|
| 378 |
|
|
.GTNORTHREFCLK1 ( 1'd0), //
|
| 379 |
|
|
.GTSOUTHREFCLK0 ( 1'd0), //
|
| 380 |
|
|
.GTSOUTHREFCLK1 ( 1'd0), //
|
| 381 |
|
|
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
|
| 382 |
|
|
.QPLLLOCKEN ( 1'd1), //
|
| 383 |
|
|
.QPLLREFCLKSEL ( 3'd1), //
|
| 384 |
|
|
.QPLLRSVD1 (16'd0), //
|
| 385 |
|
|
.QPLLRSVD2 ( 5'b11111), //
|
| 386 |
|
|
|
| 387 |
|
|
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
|
| 388 |
|
|
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
|
| 389 |
|
|
.QPLLLOCK (QPLL_QPLLLOCK), //
|
| 390 |
|
|
.QPLLFBCLKLOST (), //
|
| 391 |
|
|
.QPLLREFCLKLOST (), //
|
| 392 |
|
|
.QPLLDMONITOR (), //
|
| 393 |
|
|
|
| 394 |
|
|
//---------- Reset -----------------------------------------------------
|
| 395 |
|
|
.QPLLPD (QPLL_QPLLPD), //
|
| 396 |
|
|
.QPLLRESET (QPLL_QPLLRESET), //
|
| 397 |
|
|
.QPLLOUTRESET ( 1'd0), //
|
| 398 |
|
|
|
| 399 |
|
|
//---------- DRP -------------------------------------------------------
|
| 400 |
|
|
.DRPCLK (QPLL_DRPCLK), //
|
| 401 |
|
|
.DRPADDR (QPLL_DRPADDR), //
|
| 402 |
|
|
.DRPEN (QPLL_DRPEN), //
|
| 403 |
|
|
.DRPDI (QPLL_DRPDI), //
|
| 404 |
|
|
.DRPWE (QPLL_DRPWE), //
|
| 405 |
|
|
|
| 406 |
|
|
.DRPDO (QPLL_DRPDO), //
|
| 407 |
|
|
.DRPRDY (QPLL_DRPRDY), //
|
| 408 |
|
|
|
| 409 |
|
|
//---------- Band Gap --------------------------------------------------
|
| 410 |
|
|
.BGBYPASSB ( 1'd1), //
|
| 411 |
|
|
.BGMONITORENB ( 1'd1), //
|
| 412 |
|
|
.BGPDB ( 1'd1), //
|
| 413 |
|
|
.BGRCALOVRD ( 5'd31), //
|
| 414 |
|
|
|
| 415 |
|
|
//---------- MISC ------------------------------------------------------
|
| 416 |
|
|
.PMARSVD ( 8'd0), //
|
| 417 |
|
|
.RCALENB ( 1'd1), // Optimized for GES
|
| 418 |
|
|
|
| 419 |
|
|
.REFCLKOUTMONITOR () //
|
| 420 |
|
|
|
| 421 |
|
|
);
|
| 422 |
|
|
|
| 423 |
|
|
end
|
| 424 |
|
|
|
| 425 |
|
|
endgenerate
|
| 426 |
|
|
|
| 427 |
|
|
endmodule
|
