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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_rxeq_scan.v
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// Version : 1.10
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//------------------------------------------------------------------------------
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// Filename : rxeq_scan.v
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// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
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// Version : 18.0
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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//---------- RXEQ Eye Scan Module ----------------------------------------------
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module cl_a7pcie_x4_rxeq_scan #
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(
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
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parameter CONVERGE_MAX = 22'd3125000, // Convergence max count (12ms)
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parameter CONVERGE_MAX_BYPASS = 22'd2083333 // Convergence max count for phase2/3 bypass mode (8ms)
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)
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(
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//---------- Input -------------------------------------
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input RXEQSCAN_CLK,
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input RXEQSCAN_RST_N,
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input [ 1:0] RXEQSCAN_CONTROL,
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input [ 2:0] RXEQSCAN_PRESET,
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input RXEQSCAN_PRESET_VALID,
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input [ 3:0] RXEQSCAN_TXPRESET,
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input [17:0] RXEQSCAN_TXCOEFF,
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input RXEQSCAN_NEW_TXCOEFF_REQ,
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input [ 5:0] RXEQSCAN_FS,
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input [ 5:0] RXEQSCAN_LF,
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//---------- Output ------------------------------------
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output RXEQSCAN_PRESET_DONE,
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output [17:0] RXEQSCAN_NEW_TXCOEFF,
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output RXEQSCAN_NEW_TXCOEFF_DONE,
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output RXEQSCAN_LFFS_SEL,
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output RXEQSCAN_ADAPT_DONE
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);
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//---------- Input Register ----------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2;
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//---------- Internal Signals --------------------------
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reg adapt_done_cnt = 1'd0;
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//---------- Output Register ---------------------------
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reg preset_done = 1'd0;
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reg [21:0] converge_cnt = 22'd0;
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reg [17:0] new_txcoeff = 18'd0;
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reg new_txcoeff_done = 1'd0;
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reg lffs_sel = 1'd0;
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reg adapt_done = 1'd0;
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reg [ 3:0] fsm = 4'd0;
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 4'b0001;
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localparam FSM_PRESET = 4'b0010;
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localparam FSM_CONVERGE = 4'b0100;
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localparam FSM_NEW_TXCOEFF_REQ = 4'b1000;
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//---------- Simulation Speedup ------------------------
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// Gen3: 32 bits / PCLK : 1 million bits / X PCLK
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// X =
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//------------------------------------------------------
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localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
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localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX_BYPASS;
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge RXEQSCAN_CLK)
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begin
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if (!RXEQSCAN_RST_N)
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begin
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//---------- 1st Stage FF --------------------------
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preset_reg1 <= 3'd0;
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preset_valid_reg1 <= 1'd0;
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txpreset_reg1 <= 4'd0;
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txcoeff_reg1 <= 18'd0;
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new_txcoeff_req_reg1 <= 1'd0;
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fs_reg1 <= 6'd0;
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lf_reg1 <= 6'd0;
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//---------- 2nd Stage FF --------------------------
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preset_reg2 <= 3'd0;
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preset_valid_reg2 <= 1'd0;
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txpreset_reg2 <= 4'd0;
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txcoeff_reg2 <= 18'd0;
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new_txcoeff_req_reg2 <= 1'd0;
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fs_reg2 <= 6'd0;
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lf_reg2 <= 6'd0;
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end
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else
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begin
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//---------- 1st Stage FF --------------------------
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preset_reg1 <= RXEQSCAN_PRESET;
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preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
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txpreset_reg1 <= RXEQSCAN_TXPRESET;
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txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
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new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
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fs_reg1 <= RXEQSCAN_FS;
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lf_reg1 <= RXEQSCAN_LF;
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//---------- 2nd Stage FF --------------------------
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preset_reg2 <= preset_reg1;
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preset_valid_reg2 <= preset_valid_reg1;
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txpreset_reg2 <= txpreset_reg1;
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txcoeff_reg2 <= txcoeff_reg1;
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new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
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fs_reg2 <= fs_reg1;
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lf_reg2 <= lf_reg1;
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end
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end
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//---------- Eye Scan ----------------------------------------------------------
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always @ (posedge RXEQSCAN_CLK)
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begin
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if (!RXEQSCAN_RST_N)
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begin
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fsm <= FSM_IDLE;
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preset_done <= 1'd0;
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converge_cnt <= 22'd0;
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new_txcoeff <= 18'd0;
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new_txcoeff_done <= 1'd0;
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lffs_sel <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done_cnt <= 1'd0;
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end
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else
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begin
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case (fsm)
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//---------- Idle State ----------------------------
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FSM_IDLE :
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begin
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//---------- Process RXEQ Preset ---------------
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if (preset_valid_reg2)
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begin
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fsm <= FSM_PRESET;
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preset_done <= 1'd1;
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converge_cnt <= 22'd0;
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new_txcoeff <= new_txcoeff;
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new_txcoeff_done <= 1'd0;
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lffs_sel <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
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end
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//---------- Request New TX Coefficient --------
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else if (new_txcoeff_req_reg2)
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begin
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fsm <= FSM_CONVERGE;
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preset_done <= 1'd0;
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converge_cnt <= 22'd0;
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//new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4; // Default
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new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : (PCIE_GT_DEVICE == "GTX") ? 18'd5 : 18'd4; // Optimized for Gen3 RX JTOL
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new_txcoeff_done <= 1'd0;
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lffs_sel <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1;
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adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
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end
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//---------- Default ---------------------------
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else
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begin
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fsm <= FSM_IDLE;
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preset_done <= 1'd0;
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converge_cnt <= 22'd0;
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new_txcoeff <= new_txcoeff;
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new_txcoeff_done <= 1'd0;
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lffs_sel <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
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end
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end
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//---------- Process RXEQ Preset -------------------
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FSM_PRESET :
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begin
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fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
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preset_done <= 1'd1;
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converge_cnt <= 22'd0;
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new_txcoeff <= new_txcoeff;
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new_txcoeff_done <= 1'd0;
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266 |
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lffs_sel <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
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end
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270 |
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271 |
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//---------- Wait for Convergence ------------------
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272 |
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FSM_CONVERGE :
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273 |
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274 |
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begin
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275 |
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if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2))
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276 |
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begin
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277 |
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fsm <= FSM_NEW_TXCOEFF_REQ;
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preset_done <= 1'd0;
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279 |
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converge_cnt <= 22'd0;
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280 |
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new_txcoeff <= new_txcoeff;
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281 |
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new_txcoeff_done <= 1'd0;
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282 |
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lffs_sel <= lffs_sel;
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283 |
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adapt_done <= 1'd0;
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284 |
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adapt_done_cnt <= adapt_done_cnt;
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285 |
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end
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286 |
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else
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287 |
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begin
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288 |
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289 |
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//---------- Phase2/3 ----------------------
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290 |
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if (RXEQSCAN_CONTROL == 2'd2)
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291 |
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fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
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292 |
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//---------- Phase2/3 Bypass ---------------
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293 |
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else
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294 |
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fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
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295 |
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296 |
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preset_done <= 1'd0;
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297 |
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converge_cnt <= converge_cnt + 1'd1;
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298 |
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new_txcoeff <= new_txcoeff;
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299 |
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new_txcoeff_done <= 1'd0;
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lffs_sel <= lffs_sel;
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adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
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end
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end
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305 |
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//---------- Request New TX Coefficient ------------
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307 |
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FSM_NEW_TXCOEFF_REQ :
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308 |
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309 |
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begin
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310 |
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if (!new_txcoeff_req_reg2)
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311 |
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begin
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312 |
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fsm <= FSM_IDLE;
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preset_done <= 1'd0;
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converge_cnt <= 22'd0;
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new_txcoeff <= new_txcoeff;
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new_txcoeff_done <= 1'd0;
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317 |
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lffs_sel <= lffs_sel;
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318 |
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adapt_done <= 1'd0;
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adapt_done_cnt <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1;
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end
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321 |
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else
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322 |
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begin
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323 |
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fsm <= FSM_NEW_TXCOEFF_REQ;
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preset_done <= 1'd0;
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converge_cnt <= 22'd0;
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new_txcoeff <= new_txcoeff;
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new_txcoeff_done <= 1'd1;
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328 |
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lffs_sel <= lffs_sel;
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329 |
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adapt_done <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3);
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330 |
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adapt_done_cnt <= adapt_done_cnt;
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331 |
|
|
end
|
332 |
|
|
end
|
333 |
|
|
|
334 |
|
|
//---------- Default State -------------------------
|
335 |
|
|
default :
|
336 |
|
|
|
337 |
|
|
begin
|
338 |
|
|
fsm <= FSM_IDLE;
|
339 |
|
|
preset_done <= 1'd0;
|
340 |
|
|
converge_cnt <= 22'd0;
|
341 |
|
|
new_txcoeff <= 18'd0;
|
342 |
|
|
new_txcoeff_done <= 1'd0;
|
343 |
|
|
lffs_sel <= 1'd0;
|
344 |
|
|
adapt_done <= 1'd0;
|
345 |
|
|
adapt_done_cnt <= 1'd0;
|
346 |
|
|
end
|
347 |
|
|
|
348 |
|
|
endcase
|
349 |
|
|
|
350 |
|
|
end
|
351 |
|
|
|
352 |
|
|
end
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
//---------- RXEQ Eye Scan Output ----------------------------------------------
|
357 |
|
|
assign RXEQSCAN_PRESET_DONE = preset_done;
|
358 |
|
|
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
|
359 |
|
|
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
|
360 |
|
|
assign RXEQSCAN_LFFS_SEL = lffs_sel;
|
361 |
|
|
assign RXEQSCAN_ADAPT_DONE = adapt_done;
|
362 |
|
|
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
endmodule
|