OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_wishbone/] [src/] [testbench/] [test_pkg.vhd] - Blame information for rev 40

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dsmv 
---------------------------------------------------------------------------------------------------
2 
--
3 
-- Title       : test_pkg.vhd
4 
-- Author      : Dmitry Smekhov
5 
-- Company     : Instrumental System
6 
--
7 
-- Version     : 1.0
8 
--
9 
---------------------------------------------------------------------------------------------------
10 
--
11 
-- Description : Ïàêåò äëÿ òåñòèðîâàíèÿ ambpex5.
12 
--
13 
---------------------------------------------------------------------------------------------------
14 
--
15 
--  Version 1.1 (25.10.2011) Kuzmi4
16 
--      Description: add couple of simple tests for test WB stuff, let "test_num_1" unchanged.
17 
--
18 
---------------------------------------------------------------------------------------------------
19 
library ieee;
20 
use ieee.std_logic_1164.all;
21 
use ieee.std_logic_arith.all;
22 
use ieee.std_logic_unsigned.all;
23 
use ieee.std_logic_textio.all;
24 
use std.textio.all;
25 
 
26 
library work;
27 
use work.cmd_sim_pkg.all;
28 
use work.block_pkg.all;
29 
use work.wb_block_pkg.all;
30 
 
31 
package test_pkg is
32 
 
33 10 dsmv 
--! Initialising
34 2 dsmv 
procedure test_init(
35 38 dsmv 
                fname: in string        --! file name for report
36 2 dsmv 
        );
37 
 
38 10 dsmv 
--! Finished
39 2 dsmv 
procedure test_close;
40 
 
41 38 dsmv 
 
42 
--! Read registers
43 
procedure test_read_reg (
44 
                signal  cmd:    out bh_cmd; --! command
45 
                signal  ret:    in  bh_ret  --! answer
46 
                );
47 2 dsmv 
 
48 10 dsmv 
--! Start DMA with incorrect descriptor
49 2 dsmv 
procedure test_dsc_incorrect (
50 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
51 
                signal  ret:    in  bh_ret  --! answer
52 2 dsmv 
                );
53 
 
54 10 dsmv 
--! Start DMA for one block 4 kB
55 2 dsmv 
procedure test_read_4kb (
56 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
57 
                signal  ret:    in  bh_ret  --! answer
58 2 dsmv 
                );
59 
 
60 
 
61 10 dsmv 
--! Read block_test_check 8 kB
62 2 dsmv 
procedure test_adm_read_8kb (
63 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
64 
                signal  ret:    in  bh_ret  --! answer
65 2 dsmv 
                );
66 
 
67 
----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
68 
--procedure test_block_main (
69 38 dsmv 
--              signal  cmd:    out bh_cmd; --! command
70 
--              signal  ret:    in  bh_ret  --! answer
71 2 dsmv 
--              );
72 
--
73 
----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
74 
--procedure test_adm_read_16kb (
75 38 dsmv 
--              signal  cmd:    out bh_cmd; --! command
76 
--              signal  ret:    in  bh_ret  --! answer
77 2 dsmv 
--              );
78 
--
79 
--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
80 
procedure test_adm_write_16kb (
81 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
82 
                signal  ret:    in  bh_ret  --! answer
83 2 dsmv 
                );
84 
---------------------------------------------------------------------------------------------------
85 
--
86 
--
87 
--
88 
procedure test_num_1(
89 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
90 
                            signal  ret:    in  bh_ret  --! answer
91 2 dsmv 
                    );
92 
procedure test_num_2(
93 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
94 
                            signal  ret:    in  bh_ret  --! answer
95 2 dsmv 
                    );
96 
-- ==> TEST_CHECK.WB_CFG_SLAVE
97 
procedure test_wb_1(
98 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
99 
                            signal  ret:    in  bh_ret  --! answer
100 2 dsmv 
                    );
101 
-- ==> TEST_GEN.WB_CFG_SLAVE
102 
procedure test_wb_2(
103 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
104 
                            signal  ret:    in  bh_ret  --! answer
105 2 dsmv 
                    );
106 
end package     test_pkg;
107 
---------------------------------------------------------------------------------------------------
108 
package body test_pkg is
109 
 
110 
        FILE   log: text;
111 
 
112 
        shared variable cnt_ok, cnt_error: integer;
113 
 
114 10 dsmv 
        -- Initialising
115 2 dsmv 
        procedure test_init(
116 10 dsmv 
                fname: in string
117 2 dsmv 
                ) is
118 
        begin
119 
 
120 
                file_open( log, fname, WRITE_MODE );
121 
                cnt_ok:=0;
122 
                cnt_error:=0;
123 
 
124 
        end test_init;
125 
 
126 10 dsmv 
        --! Finished
127 2 dsmv 
        procedure test_close is
128 
                variable str : LINE;            -- pointer to string
129 
        begin
130 
 
131 
                std.textio.write( str, string'(" " ));
132 
                writeline( log, str );
133 
                writeline( log, str );
134 
 
135 10 dsmv 
                write( str, string'("check completed" ));
136 2 dsmv 
                writeline( log, str );
137 10 dsmv 
                write( str, string'("the number of successful tests:  " ));
138 2 dsmv 
                write( str, cnt_ok );
139 
                writeline( log, str );
140 10 dsmv 
                write( str, string'("the number of false test: " ));
141 2 dsmv 
                write( str, cnt_error );
142 
                writeline( log, str );
143 
 
144 
 
145 
                file_close( log );
146 
 
147 10 dsmv 
                if( cnt_ok>0 and cnt_error=0 ) then
148 
                        write( str, string'("TEST finished successfully") );
149 
                        writeline( output, str );
150 
                else
151 
                        write( str, string'("TEST finished with ERR") );
152 
                        writeline( output, str );
153 
 
154 
                end if;
155 
 
156 2 dsmv 
        end test_close;
157 
 
158 
 
159 38 dsmv 
--! Read registers
160 
procedure test_read_reg (
161 
                signal  cmd:    out bh_cmd; --! command
162 
                signal  ret:    in  bh_ret  --! answer
163 
                )
164 
is
165 
 
166 
variable        adr             : std_logic_vector( 31 downto 0 );
167 
variable        data1   : std_logic_vector( 31 downto 0 );
168 
variable        data2   : std_logic_vector( 31 downto 0 );
169 40 dsmv 
variable        str             : line;
170 
variable        error   : integer:=0;
171 38 dsmv 
begin
172 
 
173 
        write( str, string'("TEST_READ_REG" ));
174 
        writeline( log, str );
175 2 dsmv 
 
176 38 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
177 
        wait for 100 ns;
178 
 
179 
 
180 
        --block_read( cmd, ret, 4, 23, x"0000A400" );   -- LOCAL_ADR
181 
        wb_block_gen_read( cmd, ret,    REG_BLOCK_ID, data1 ); -- read block id
182 
        wb_block_check_read( cmd, ret,  REG_BLOCK_ID, data2 ); -- read block id
183 
 
184 
        write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
185 
        writeline( log, str );
186 
 
187 
        write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
188 
        writeline( log, str );
189 
 
190 40 dsmv 
--      wb_read( cmd, ret, 16#1000#, data1 );
191 
--
192 
--      wb_read( cmd, ret, 16#3000#, data1 );
193 
--
194 
--      write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) );
195 
--      writeline( log, str );
196 
--
197 
--      write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) );
198 
--      writeline( log, str );
199 38 dsmv 
 
200 
        block_write( cmd, ret, 0, 8, x"00000000" );              -- BRD_MODE
201 
        wait for 100 ns;
202 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE
203 
        wait for 100 ns;
204 
 
205 
        wb_block_gen_read( cmd, ret,    REG_BLOCK_ID, data1 ); -- read block id
206 
        wb_block_check_read( cmd, ret,  REG_BLOCK_ID, data2 ); -- read block id
207 
 
208 
        write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) );
209 40 dsmv 
 
210 
        if( data1( 15 downto 0 )=x"001B" ) then
211 
                write( str, string'(" - Ok" ));
212 
        else
213 
                write( str, string'(" - Error" ));
214 
                error := error + 1;
215 
        end if;
216 
 
217 38 dsmv 
        writeline( log, str );
218 
 
219 
        write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) );
220 40 dsmv 
 
221 
        if( data2( 15 downto 0 )=x"001A" ) then
222 
                write( str, string'(" - Ok" ));
223 
        else
224 
                write( str, string'(" - Error" ));
225 
                error := error + 1;
226 
        end if;
227 38 dsmv 
        writeline( log, str );
228 
 
229 40 dsmv 
        if( error=0 ) then
230 
                write( str, string'("Test read_reg - Ok" ));
231 
                cnt_ok := cnt_ok + 1;
232 
        else
233 
                write( str, string'("Test read_reg - Error" ));
234 
                cnt_error := cnt_error + 1;
235 
        end if;
236 
 
237 38 dsmv 
end test_read_reg;
238 
 
239 
 
240 
 
241 
 
242 
 
243 10 dsmv 
--! Start DMA with incorrect descriptor
244 2 dsmv 
procedure test_dsc_incorrect (
245 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
246 
                signal  ret:    in  bh_ret  --! answer
247 2 dsmv 
                )
248 
is
249 
 
250 
variable        adr             : std_logic_vector( 31 downto 0 );
251 
variable        data    : std_logic_vector( 31 downto 0 );
252 
variable        str             : line;
253 
begin
254 
 
255 
        write( str, string'("TEST_DSC_INCORRECT" ));
256 
        writeline( log, str );
257 
 
258 38 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
259 
        wait for 100 ns;
260 
 
261 10 dsmv 
        ---- Init block of descriptor ---
262 2 dsmv 
        for ii in 0 to 127 loop
263 
                adr:= x"00100000";
264 
                adr:=adr + ii*4;
265 
                int_mem_write( cmd, ret, adr,  x"00000000" );
266 
        end loop;
267 
 
268 
        int_mem_write( cmd, ret, x"00100000",  x"03020100" );
269 
        int_mem_write( cmd, ret, x"001001FC",  x"FF00AA00" );
270 
 
271 10 dsmv 
        ---- DMA program ----
272 2 dsmv 
        block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
273 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
274 
 
275 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
276 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
277 
        block_write( cmd, ret, 4, 23, x"0000A400" );    -- LOCAL_ADR
278 
 
279 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
280 
 
281 10 dsmv 
        wait for 20 us;
282 2 dsmv 
 
283 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
284 
 
285 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
286 
        if( data( 15 downto 0 )=x"A021" ) then
287 
                write( str, string'(" - Ok" ));
288 
                cnt_ok := cnt_ok + 1;
289 
        else
290 
                write( str, string'(" - Error" ));
291 
                cnt_error := cnt_error + 1;
292 
        end if;
293 
 
294 
        writeline( log, str );
295 
 
296 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
297 
 
298 
end test_dsc_incorrect;
299 
 
300 
 
301 10 dsmv 
--! Start DMA for one block 4 kB
302 2 dsmv 
procedure test_read_4kb (
303 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
304 
                signal  ret:    in  bh_ret  --! answer
305 2 dsmv 
                )
306 
is
307 
 
308 
variable        adr                             : std_logic_vector( 31 downto 0 );
309 
variable        data                    : std_logic_vector( 31 downto 0 );
310 
variable        str                             : line;
311 
 
312 
variable        error                   : integer:=0;
313 
variable        dma_complete    : integer;
314 
 
315 
begin
316 
 
317 
        write( str, string'("TEST_READ_4KB" ));
318 
        writeline( log, str );
319 
 
320 38 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
321 
        wait for 100 ns;
322 
 
323 
 
324 10 dsmv 
        ---- Init block of descriptor ---
325 2 dsmv 
        for ii in 0 to 127 loop
326 
                adr:= x"00100000";
327 
                adr:=adr + ii*4;
328 
                int_mem_write( cmd, ret, adr,  x"00000000" );
329 
        end loop;
330 
 
331 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
332 
        int_mem_write( cmd, ret, x"00100004",  x"00000100" );
333 
 
334 
 
335 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
336 
        int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );
337 
 
338 10 dsmv 
        --wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
339 2 dsmv 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
340 10 dsmv 
        wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
341 2 dsmv 
        write( str, string'("BLOCK TEST_GEN  ID: " ));
342 
        hwrite( str, data );
343 
        writeline( log, str );
344 
 
345 10 dsmv 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
346 2 dsmv 
 
347 
 
348 10 dsmv 
        ---- DMA program ----
349 
        block_write( cmd, ret, 4, 8, x"00000025" );             -- DMA_MODE - without request
350 2 dsmv 
        block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
351 
 
352 
        block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
353 
        block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
354 
        block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE );        -- LOCAL_ADR
355 
 
356 10 dsmv 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
357 2 dsmv 
 
358 
        wait for 1 us;
359 
 
360 
        block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
361 
 
362 
 
363 
        --wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A2" );
364 
 
365 
        wait for 20 us;
366 
 
367 
        block_read( cmd, ret, 4, 16, data );                    -- STATUS
368 
 
369 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
370 
        if( data( 8 )='1' ) then
371 10 dsmv 
                write( str, string'(" - descriptor is correct" ));
372 2 dsmv 
        else
373 10 dsmv 
                write( str, string'(" - descriptor is incorrect" ));
374 2 dsmv 
                error := error + 1;
375 
        end if;
376 
 
377 
        writeline( log, str );
378 
 
379 
        if( error=0 ) then
380 
 
381 10 dsmv 
                ---- Wait for DMA finished ----
382 2 dsmv 
                dma_complete := 0;
383 
                for ii in 0 to 100 loop
384 
 
385 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
386 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
387 
                        if( data(5)='1' ) then
388 10 dsmv 
                                write( str, string'(" - DMA finished " ));
389 2 dsmv 
                                dma_complete := 1;
390 
                        end if;
391 
                        writeline( log, str );
392 
 
393 
                        if( dma_complete=1 ) then
394 
                                exit;
395 
                        end if;
396 
 
397 
                        wait for 1 us;
398 
 
399 
                end loop;
400 
 
401 
                writeline( log, str );
402 
 
403 
                if( dma_complete=0 ) then
404 10 dsmv 
                        write( str, string'("Error - DMA not finished" ));
405 2 dsmv 
                        writeline( log, str );
406 
                        error:=error+1;
407 
                end if;
408 
 
409 
        end if;
410 
 
411 
        for ii in 0 to 3 loop
412 
 
413 
                block_read( cmd, ret, 4, 16, data );                    -- STATUS
414 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
415 
                writeline( log, str );
416 
                wait for 500 ns;
417 
 
418 
        end loop;
419 
 
420 
 
421 
        block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
422 
 
423 10 dsmv 
        write( str, string'(" Read: " ));
424 2 dsmv 
        writeline( log, str );
425 
 
426 
        for ii in 0 to 15 loop
427 
 
428 
                adr:= x"00800000";
429 
                adr:=adr + ii*4;
430 
                int_mem_read( cmd, ret, adr,  data );
431 
 
432 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
433 
                writeline( log, str );
434 
 
435 
        end loop;
436 
 
437 
 
438 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
439 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
440 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
441 
 
442 
 
443 
        writeline( log, str );
444 
        if( error=0 ) then
445 10 dsmv 
                write( str, string'("Test is correct" ));
446 2 dsmv 
                cnt_ok := cnt_ok + 1;
447 
        else
448 10 dsmv 
                write( str, string'("Test have ERRORS" ));
449 2 dsmv 
                cnt_error := cnt_error + 1;
450 
        end if;
451 
        writeline( log, str );
452 
        writeline( log, str );
453 
 
454 
end test_read_4kb;
455 
 
456 
 
457 10 dsmv 
--! Read block_test_check 8 kB
458 2 dsmv 
procedure test_adm_read_8kb (
459 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
460 
                signal  ret:    in  bh_ret  --! answer
461 2 dsmv 
                )
462 
is
463 
 
464 
variable        adr                             : std_logic_vector( 31 downto 0 );
465 
variable        data                    : std_logic_vector( 31 downto 0 );
466 
variable        str                             : line;
467 
 
468 
variable        error                   : integer:=0;
469 38 dsmv 
variable        dma_complete    : integer;
470 2 dsmv 
 
471 38 dsmv 
variable        status                  : std_logic_vector( 31 downto 0 );
472 
variable        reg_block_wr    : std_logic_vector( 31 downto 0 );
473 
 
474 2 dsmv 
begin
475 
 
476 
        write( str, string'("TEST_ADM_READ_8KB" ));
477 
        writeline( log, str );
478 
 
479 38 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
480 
        wait for 100 ns;
481 
 
482 10 dsmv 
        ---- Init block of descriptor ---
483 2 dsmv 
        for ii in 0 to 127 loop
484 
                adr:= x"00100000";
485 
                adr:=adr + ii*4;
486 
                int_mem_write( cmd, ret, adr,  x"00000000" );
487 
        end loop;
488 
 
489 10 dsmv 
        --- Desctriptor 0 ---
490 2 dsmv 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
491 10 dsmv 
        int_mem_write( cmd, ret, x"00100004",  x"00000111" );   -- jump to next descriptor
492 2 dsmv 
 
493 10 dsmv 
        --- Desctriptor 1 ---
494 2 dsmv 
        int_mem_write( cmd, ret, x"00100008",  x"00008010" );
495 10 dsmv 
        int_mem_write( cmd, ret, x"0010000C",  x"00000110" );   -- stop
496 2 dsmv 
 
497 
 
498 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
499 
        int_mem_write( cmd, ret, x"001001FC",  x"D6644953" );
500 
 
501 
 
502 
        ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
503 38 dsmv 
        block_write( cmd, ret, 5, 8, x"00000027" );             -- DMA_MODE
504 
        block_write( cmd, ret, 5, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
505 2 dsmv 
 
506 38 dsmv 
        block_write( cmd, ret, 5, 20, x"00100000" );    -- PCI_ADRL
507 
        block_write( cmd, ret, 5, 21, x"00100000" );    -- PCI_ADRH
508 
        block_write( cmd, ret, 5, 23, TEST_GEN_WB_BURST_SLAVE );        -- LOCAL_ADR
509 2 dsmv 
 
510 
 
511 10 dsmv 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
512 2 dsmv 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
513 10 dsmv 
        wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
514 2 dsmv 
        write( str, string'("BLOCK TEST_GEN  ID: " ));
515 
        hwrite( str, data );
516 
        writeline( log, str );
517 
 
518 10 dsmv 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
519 2 dsmv 
 
520 38 dsmv 
        block_write( cmd, ret, 5, 9, x"00000001" );             -- DMA_CTRL - START
521 2 dsmv 
 
522 38 dsmv 
        wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status );             -- read status
523 
        write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
524 
        wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR,  reg_block_wr );       -- read block_wr
525 
        write( str, string'("WB_GEN_BL_WR:  " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
526 
 
527 
 
528 10 dsmv 
        wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
529 2 dsmv 
 
530 
        wait for 20 us;
531 
 
532 38 dsmv 
        block_read( cmd, ret, 5, 16, data );                    -- STATUS
533 2 dsmv 
 
534 
        write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
535 
        if( data( 8 )='1' ) then
536 10 dsmv 
                write( str, string'(" - descriptor is correct" ));
537 2 dsmv 
        else
538 10 dsmv 
                write( str, string'(" - descriptor is incorrect" ));
539 2 dsmv 
                error := error + 1;
540 
        end if;
541 
 
542 
        writeline( log, str );
543 
 
544 
        if( error=0 ) then
545 
 
546 
                ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
547 
                dma_complete := 0;
548 
                for ii in 0 to 100 loop
549 
 
550 38 dsmv 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
551 2 dsmv 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
552 
                        if( data(5)='1' ) then
553 10 dsmv 
                                write( str, string'(" - DMA finished " ));
554 2 dsmv 
                                dma_complete := 1;
555 
 
556 38 dsmv 
                                block_write( cmd, ret, 5, 16#11#, x"00000010" );                -- FLAG_CLR - reset EOT
557 2 dsmv 
 
558 
                        end if;
559 
                        writeline( log, str );
560 
 
561 
                        if( dma_complete=1 ) then
562 
                                exit;
563 
                        end if;
564 
 
565 
                        wait for 1 us;
566 
 
567 
                end loop;
568 
 
569 
                writeline( log, str );
570 
 
571 
                if( dma_complete=0 ) then
572 10 dsmv 
                        write( str, string'("Error - DMA not finished " ));
573 2 dsmv 
                        writeline( log, str );
574 
                        error:=error+1;
575 
                end if;
576 
 
577 38 dsmv 
        end if;
578 2 dsmv 
 
579 38 dsmv 
        wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status );             -- read status
580 
        write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
581 
        wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR,  reg_block_wr );       -- read block_wr
582 
        write( str, string'("WB_GEN_BL_WR:  " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
583 
 
584 
 
585 2 dsmv 
        for ii in 0 to 3 loop
586 
 
587 38 dsmv 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
588 2 dsmv 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
589 
                writeline( log, str );
590 
                wait for 500 ns;
591 
 
592 
        end loop;
593 
 
594 
 
595 38 dsmv 
        block_write( cmd, ret, 5, 9, x"00000000" );             -- DMA_CTRL - STOP
596 2 dsmv 
 
597 10 dsmv 
        write( str, string'(" Block 0 - read: " ));
598 2 dsmv 
        writeline( log, str );
599 
 
600 
        for ii in 0 to 15 loop
601 
 
602 
                adr:= x"00800000";
603 
                adr:=adr + ii*4;
604 
                int_mem_read( cmd, ret, adr,  data );
605 
 
606 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
607 
                writeline( log, str );
608 
 
609 
        end loop;
610 
 
611 
        writeline( log, str );
612 
 
613 10 dsmv 
        write( str, string'(" Block 1 - read: " ));
614 2 dsmv 
        writeline( log, str );
615 
 
616 
        for ii in 0 to 15 loop
617 
 
618 
                adr:= x"00801000";
619 
                adr:=adr + ii*4;
620 
                int_mem_read( cmd, ret, adr,  data );
621 
 
622 
                write( str, ii ); write( str, string'("   " )); hwrite( str, data );
623 
                writeline( log, str );
624 
 
625 
        end loop;
626 
 
627 
 
628 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
629 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
630 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
631 
 
632 
 
633 
        writeline( log, str );
634 
        if( error=0 ) then
635 10 dsmv 
                write( str, string'(" Test is correct " ));
636 2 dsmv 
                cnt_ok := cnt_ok + 1;
637 
        else
638 10 dsmv 
                write( str, string'(" Test have ERRORS " ));
639 2 dsmv 
                cnt_error := cnt_error + 1;
640 
        end if;
641 
        writeline( log, str );
642 
        writeline( log, str );
643 
 
644 
end test_adm_read_8kb;
645 
--
646 
--
647 
----! Ïðîâåðêà îáðàùåíèé ê áëîêó MAIN
648 
--procedure test_block_main (
649 38 dsmv 
--              signal  cmd:    out bh_cmd; --! command
650 
--              signal  ret:    in  bh_ret  --! answer
651 2 dsmv 
--              )
652 
--is
653 
--
654 
--variable      adr                             : std_logic_vector( 31 downto 0 );
655 
--variable      data                    : std_logic_vector( 31 downto 0 );
656 
--variable      str                             : line;
657 
--
658 
--variable      error                   : integer:=0;
659 
--variable      dma_complete    : integer;
660 
--
661 
--begin
662 
--
663 
--      write( str, string'("TEST_BLOCK_MAIN" ));
664 
--      writeline( log, str );
665 
--
666 
--      block_read( cmd, ret, 4, 16#00#, data );
667 
--      write( str,  string'("ÁËÎÊ 4: " )); hwrite( str, data ); writeline( log, str );
668 
--
669 
--      wait for 10 us;
670 
--
671 
----    write( str, "Êîíñòàíòû:" );
672 
----    writeline( log, str );
673 
----    for ii in 0 to 5 loop
674 
----            write( str, "Áëîê " );
675 
----            write( str, ii );
676 
----            for jj in 0 to 7 loop
677 
----                    block_read( cmd, ret, ii, jj, data );
678 
----                    write( str, "   " );
679 
----                    hwrite( str, data );
680 
----            end loop;
681 
----            writeline( log, str );
682 
----    end loop;
683 
----
684 
----
685 
----    writeline( log, str );
686 
----
687 
----    block_read( cmd, ret, 0, 16#10#, data );
688 
----    write( str,  "STATUS: " ); hwrite( str, data ); writeline( log, str );
689 
----
690 
----    block_write( cmd, ret, 80, 16#08#, x"00000100" );
691 
----
692 
----    block_read( cmd, ret, 0, 16#10#, data );
693 
----    write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
694 
----
695 
----    block_write( cmd, ret, 80, 16#08#, x"00000200" );
696 
----
697 
----    block_read( cmd, ret, 0, 16#10#, data );
698 
----    write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
699 
----
700 
----
701 
----    writeline( log, str );
702 
----    if( error=0 ) then
703 
----            write( str, " Òåñò çàâåðø¸í óñïåøíî " );
704 
----            cnt_ok := cnt_ok + 1;
705 
----    else
706 
----            write( str, " Òåñò íå âûïîëíåí " );
707 
----            cnt_error := cnt_error + 1;
708 
----    end if;
709 
--
710 
--      for ii in 0 to 127 loop
711 
--
712 
--              block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
713 
--              block_read( cmd, ret, 4, 8, data );
714 
--              write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
715 
--              if( data/=x"0000AA55" ) then
716 
--                      error:=error+1;
717 
--              end if;
718 
--
719 
--      end loop;
720 
--
721 
--
722 
--
723 
--
724 
--      writeline( log, str );
725 
--      writeline( log, str );
726 
--
727 
--end test_block_main;
728 
--
729 
--
730 
--
731 
--
732 
----! ×òåíèå 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
733 
--procedure test_adm_read_16kb (
734 38 dsmv 
--              signal  cmd:    out bh_cmd; --! command
735 
--              signal  ret:    in  bh_ret  --! answer
736 2 dsmv 
--              )
737 
--is
738 
--
739 
--variable      adr                             : std_logic_vector( 31 downto 0 );
740 
--variable      data                    : std_logic_vector( 31 downto 0 );
741 
--variable      str                             : line;
742 
--
743 
--variable      error                   : integer:=0;
744 
--variable      dma_complete    : integer;
745 
--variable      kk                              : integer;
746 
--variable      status                  : std_logic_vector( 15 downto 0 );
747 
--
748 
--begin
749 
--
750 
--      write( str, string'("TEST_ADM_READ_16KB" ));
751 
--      writeline( log, str );
752 
--
753 
--      ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
754 
--      for ii in 0 to 256 loop
755 
--              adr:= x"00100000";
756 
--              adr:=adr + ii*4;
757 
--              int_mem_write( cmd, ret, adr,  x"00000000" );
758 
--      end loop;
759 
--
760 
--      --- Áëîê 0 ---
761 
--
762 
--      --- Äåñêðèïòîð 0 ---
763 
--      int_mem_write( cmd, ret, x"00100000",  x"00008000" );
764 
--      int_mem_write( cmd, ret, x"00100004",  x"00000111" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
765 
--
766 
--      --- Äåñêðèïòîð 1 ---
767 
--      int_mem_write( cmd, ret, x"00100008",  x"00008010" );
768 
--      int_mem_write( cmd, ret, x"0010000C",  x"00000112" );   -- ïåðåõîä ê ñëåäóþùåìó áëîêó
769 
--
770 
--      --- Äåñêðèïòîð 2 ---
771 
--      int_mem_write( cmd, ret, x"00100010",  x"00001002" );   -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
772 
--      int_mem_write( cmd, ret, x"00100014",  x"00000000" );
773 
--
774 
--
775 
--      int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
776 
--      int_mem_write( cmd, ret, x"001001FC",  x"14644953" );
777 
--
778 
--
779 
--      --- Áëîê 1 ---
780 
--
781 
--      --- Äåñêðèïòîð 0 ---
782 
--      int_mem_write( cmd, ret, x"00100200",  x"00008020" );
783 
--      int_mem_write( cmd, ret, x"00100204",  x"00000111" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
784 
--
785 
--      --- Äåñêðèïòîð 1 ---
786 
--      int_mem_write( cmd, ret, x"00100208",  x"00008030" );
787 
--      int_mem_write( cmd, ret, x"0010020C",  x"00000110" );   -- îñòàíîâêà
788 
--
789 
--
790 
--      int_mem_write( cmd, ret, x"001003F8",  x"00000000" );
791 
--      int_mem_write( cmd, ret, x"001003FC",  x"D67C4953" );
792 
--
793 
--
794 
--
795 
--      ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
796 
--      block_write( cmd, ret, 4, 8, x"00000027" );             -- DMA_MODE
797 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
798 
--
799 
--      block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
800 
--      block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
801 
--      block_write( cmd, ret, 4, 23, x"00019000" );    -- LOCAL_ADR
802 
--
803 
--
804 
--      ---- Ïîäãîòîâêà òåòðàäû ----
805 
--      trd_test_mode( cmd, ret, 0 );   -- ïåðåõîä â ðàáî÷èé ðåæèì --
806 
--      trd_wait_cmd( cmd, ret, 0, 16, x"1600" );               -- DMAR0 - îò òåòðàäû 6 --
807 
--
808 
--      trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" );   -- Ðàçìåð áëîêà = 4 êÁ --
809 
--
810 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
811 
--
812 
--      trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" );   -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
813 
--
814 
--      trd_wait_cmd( cmd, ret, 6,      0, x"2038" );           -- çàïóñê òåòðàäû DIO_IN
815 
--
816 
--      trd_wait_cmd( cmd, ret, 1, 16#1E#, x"0020" );   -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
817 
--
818 
--      wait for 20 us;
819 
--
820 
--      block_read( cmd, ret, 4, 16, data );                    -- STATUS
821 
--
822 
--      write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
823 
--      if( data( 8 )='1' ) then
824 
--              write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
825 
--      else
826 
--              write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
827 
--              error := error + 1;
828 
--      end if;
829 
--
830 
--      writeline( log, str );
831 
--
832 
--      if( error=0 ) then
833 
--
834 
--              kk:=0;
835 
--              loop
836 
--
837 
--              trd_status( cmd, ret, 6, status );
838 
--              write( str, string'("TRD_STATUS: " )); hwrite( str, status );
839 
--
840 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
841 
--              write( str, string'("    STATUS: " )); hwrite( str, data( 15 downto 0 ) );
842 
--
843 
--                      if( data(4)='1' ) then
844 
--                              write( str, string'(" - çàâåðøåíî ÷òåíèå áëîêà " ));
845 
--                              block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
846 
--                              kk:=kk+1;
847 
--                              if( kk=4 ) then
848 
--                                      exit;
849 
--                              end if;
850 
--                      end if;
851 
--                      writeline( log, str );
852 
--
853 
--                      wait for 500 ns;
854 
--
855 
--
856 
--              end loop;
857 
--
858 
--              ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
859 
--              dma_complete := 0;
860 
--              for ii in 0 to 100 loop
861 
--
862 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
863 
--              write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
864 
--                      if( data(5)='1' ) then
865 
--                              write( str, string'(" - DMA çàâåðø¸í " ));
866 
--                              dma_complete := 1;
867 
--
868 
--                              block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
869 
--
870 
--                      end if;
871 
--                      writeline( log, str );
872 
--
873 
--                      if( dma_complete=1 ) then
874 
--                              exit;
875 
--                      end if;
876 
--
877 
--                      wait for 1 us;
878 
--
879 
--              end loop;
880 
--
881 
--              writeline( log, str );
882 
--
883 
--              if( dma_complete=0 ) then
884 
--                      write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
885 
--                      writeline( log, str );
886 
--                      error:=error+1;
887 
--              end if;
888 
--
889 
--      end if;
890 
--
891 
--      for ii in 0 to 3 loop
892 
--
893 
--              block_read( cmd, ret, 4, 16, data );                    -- STATUS
894 
--              write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
895 
--              writeline( log, str );
896 
--              wait for 500 ns;
897 
--
898 
--      end loop;
899 
--
900 
--
901 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL - STOP
902 
--
903 
--      write( str, string'(" Áëîê 0 - ïðî÷èòàíî: " ));
904 
--      writeline( log, str );
905 
--
906 
--      for ii in 0 to 15 loop
907 
--
908 
--              adr:= x"00800000";
909 
--              adr:=adr + ii*4;
910 
--              int_mem_read( cmd, ret, adr,  data );
911 
--
912 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
913 
--              writeline( log, str );
914 
--
915 
--      end loop;
916 
--
917 
--      writeline( log, str );
918 
--
919 
--      write( str, string'(" Áëîê 1 - ïðî÷èòàíî: " ));
920 
--      writeline( log, str );
921 
--
922 
--      for ii in 0 to 15 loop
923 
--
924 
--              adr:= x"00801000";
925 
--              adr:=adr + ii*4;
926 
--              int_mem_read( cmd, ret, adr,  data );
927 
--
928 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
929 
--              writeline( log, str );
930 
--
931 
--      end loop;
932 
--
933 
--      write( str, string'(" Áëîê 2 - ïðî÷èòàíî: " ));
934 
--      writeline( log, str );
935 
--
936 
--      for ii in 0 to 15 loop
937 
--
938 
--              adr:= x"00802000";
939 
--              adr:=adr + ii*4;
940 
--              int_mem_read( cmd, ret, adr,  data );
941 
--
942 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
943 
--              writeline( log, str );
944 
--
945 
--      end loop;
946 
--
947 
--
948 
--      write( str, string'(" Áëîê 3 - ïðî÷èòàíî: " ));
949 
--      writeline( log, str );
950 
--
951 
--      for ii in 0 to 15 loop
952 
--
953 
--              adr:= x"00803000";
954 
--              adr:=adr + ii*4;
955 
--              int_mem_read( cmd, ret, adr,  data );
956 
--
957 
--              write( str, ii ); write( str, string'("   " )); hwrite( str, data );
958 
--              writeline( log, str );
959 
--
960 
--      end loop;
961 
--
962 
----    block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
963 
----    block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
964 
----    block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
965 
--
966 
--
967 
--      writeline( log, str );
968 
--      if( error=0 ) then
969 
--              write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
970 
--              cnt_ok := cnt_ok + 1;
971 
--      else
972 
--              write( str, string'(" Òåñò íå âûïîëíåí " ));
973 
--              cnt_error := cnt_error + 1;
974 
--      end if;
975 
--      writeline( log, str );
976 
--      writeline( log, str );
977 
--
978 
--end test_adm_read_16kb;
979 
--
980 
--
981 
--
982 
--
983 
--! Çàïèñü 16 êÁ ñ èñïîëüçîâàíèåì äâóõ áëîêîâ äåñêðèïòîðîâ
984 
procedure test_adm_write_16kb (
985 38 dsmv 
                signal  cmd:    out bh_cmd; --! command
986 
                signal  ret:    in  bh_ret  --! answer
987 2 dsmv 
                )
988 
is
989 
 
990 
variable        adr                             : std_logic_vector( 31 downto 0 );
991 
variable        data                    : std_logic_vector( 31 downto 0 );
992 
variable        str                             : line;
993 
 
994 
variable        error                   : integer:=0;
995 
variable        dma_complete    : integer;
996 
variable        kk                              : integer;
997 
variable        status                  : std_logic_vector( 15 downto 0 );
998 
 
999 
variable        data64                  : std_logic_vector( 63 downto 0 );
1000 
variable        data64n                 : std_logic_vector( 63 downto 0 );
1001 
 
1002 
begin
1003 
 
1004 
        write( str, string'("TEST_ADM_WRITE_16KB" ));
1005 
        writeline( log, str );
1006 
 
1007 38 dsmv 
        block_write( cmd, ret, 0, 8, x"0000000F" );              -- BRD_MODE, reset off
1008 
        wait for 100 ns;
1009 
 
1010 2 dsmv 
        ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
1011 
        for ii in 0 to 256 loop
1012 
                adr:= x"00100000";
1013 
                adr:=adr + ii*4;
1014 
                int_mem_write( cmd, ret, adr,  x"00000000" );
1015 
        end loop;
1016 
 
1017 
 
1018 
        data64 :=x"0000000000000000";
1019 
        data64n := not data64;
1020 
 
1021 
        ---- Çàïîëíåíèå áëîêà 0 ----
1022 
        adr:= x"00800000";
1023 
    data:=x"A5A50123";
1024 
        int_mem_write( cmd, ret, adr,  data );
1025 
        adr:=adr + 4;
1026 
 
1027 
        data:=x"00000000";
1028 
        int_mem_write( cmd, ret, adr,  data );
1029 
        adr:=adr + 4;
1030 
 
1031 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1032 
        adr:=adr + 4;
1033 
 
1034 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1035 
        adr:=adr + 4;
1036 
 
1037 
        data64:=data64 + 1;
1038 
        data64n := not data64;
1039 
 
1040 
        for ii in 0 to 254 loop
1041 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1042 
                adr:=adr + 4;
1043 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1044 
                adr:=adr + 4;
1045 
 
1046 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1047 
                adr:=adr + 4;
1048 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1049 
                adr:=adr + 4;
1050 
 
1051 
                data64:=data64 + 1;
1052 
                data64n := not data64;
1053 
 
1054 
        end loop;
1055 
 
1056 
        ---- Çàïîëíåíèå áëîêà 1 ----
1057 
        adr:= x"00801000";
1058 
    data:=x"A5A50123";
1059 
        int_mem_write( cmd, ret, adr,  data );
1060 
        adr:=adr + 4;
1061 
 
1062 
        data:=x"00000001";
1063 
        int_mem_write( cmd, ret, adr,  data );
1064 
        adr:=adr + 4;
1065 
 
1066 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1067 
        adr:=adr + 4;
1068 
 
1069 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1070 
        adr:=adr + 4;
1071 
 
1072 
        data64:=data64 + 1;
1073 
        data64n := not data64;
1074 
 
1075 
        for ii in 0 to 254 loop
1076 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1077 
                adr:=adr + 4;
1078 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1079 
                adr:=adr + 4;
1080 
 
1081 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1082 
                adr:=adr + 4;
1083 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1084 
                adr:=adr + 4;
1085 
 
1086 
                data64:=data64 + 1;
1087 
                data64n := not data64;
1088 
 
1089 
        end loop;
1090 
 
1091 
        ---- Çàïîëíåíèå áëîêà 2 ----
1092 
        adr:= x"00802000";
1093 
    data:=x"A5A50123";
1094 
        int_mem_write( cmd, ret, adr,  data );
1095 
        adr:=adr + 4;
1096 
 
1097 
        data:=x"00000002";
1098 
        int_mem_write( cmd, ret, adr,  data );
1099 
        adr:=adr + 4;
1100 
 
1101 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1102 
        adr:=adr + 4;
1103 
 
1104 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1105 
        adr:=adr + 4;
1106 
 
1107 
        data64:=data64 + 1;
1108 
        data64n := not data64;
1109 
 
1110 
        for ii in 0 to 254 loop
1111 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1112 
                adr:=adr + 4;
1113 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1114 
                adr:=adr + 4;
1115 
 
1116 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1117 
                adr:=adr + 4;
1118 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1119 
                adr:=adr + 4;
1120 
 
1121 
                data64:=data64 + 1;
1122 
                data64n := not data64;
1123 
 
1124 
        end loop;
1125 
 
1126 
        ---- Çàïîëíåíèå áëîêà 3 ----
1127 
        adr:= x"00803000";
1128 
    data:=x"A5A50123";
1129 
        int_mem_write( cmd, ret, adr,  data );
1130 
        adr:=adr + 4;
1131 
 
1132 
        data:=x"00000003";
1133 
        int_mem_write( cmd, ret, adr,  data );
1134 
        adr:=adr + 4;
1135 
 
1136 
        int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1137 
        adr:=adr + 4;
1138 
 
1139 
        int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1140 
        adr:=adr + 4;
1141 
 
1142 
        data64:=data64 + 1;
1143 
        data64n := not data64;
1144 
 
1145 
        for ii in 0 to 254 loop
1146 
                int_mem_write( cmd, ret, adr,  data64( 31 downto 0 ) );
1147 
                adr:=adr + 4;
1148 
                int_mem_write( cmd, ret, adr,  data64( 63 downto 32 ) );
1149 
                adr:=adr + 4;
1150 
 
1151 
                int_mem_write( cmd, ret, adr,  data64n( 31 downto 0 ) );
1152 
                adr:=adr + 4;
1153 
                int_mem_write( cmd, ret, adr,  data64n( 63 downto 32 ) );
1154 
                adr:=adr + 4;
1155 
 
1156 
                data64:=data64 + 1;
1157 
                data64n := not data64;
1158 
 
1159 
        end loop;
1160 
--      for ii in 0 to 256 loop
1161 
--              adr:= x"00802000";
1162 
--              adr:=adr + ii*4;
1163 
--              data:=x"00A20000";
1164 
--              data:=data + ii;
1165 
--              int_mem_write( cmd, ret, adr,  data );
1166 
--      end loop;
1167 
--
1168 
--      for ii in 0 to 256 loop
1169 
--              adr:= x"00803000";
1170 
--              adr:=adr + ii*4;
1171 
--              data:=x"00A30000";
1172 
--              data:=data + ii;
1173 
--              int_mem_write( cmd, ret, adr,  data );
1174 
--      end loop;
1175 
 
1176 
        --- Áëîê 0 ---
1177 
 
1178 
        --- Äåñêðèïòîð 0 ---
1179 
        int_mem_write( cmd, ret, x"00100000",  x"00008000" );
1180 
        int_mem_write( cmd, ret, x"00100004",  x"00000011" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
1181 
 
1182 
        --- Äåñêðèïòîð 1 ---
1183 
        int_mem_write( cmd, ret, x"00100008",  x"00008010" );
1184 
        int_mem_write( cmd, ret, x"0010000C",  x"00000012" );   -- ïåðåõîä ê ñëåäóþùåìó áëîêó
1185 
 
1186 
        --- Äåñêðèïòîð 2 ---
1187 
        int_mem_write( cmd, ret, x"00100010",  x"00001002" );   -- àäðåñ ñëåäóþùåãî äåñêðèïòîðà
1188 
        int_mem_write( cmd, ret, x"00100014",  x"00000000" );
1189 
 
1190 
 
1191 
        int_mem_write( cmd, ret, x"001001F8",  x"00000000" );
1192 
        int_mem_write( cmd, ret, x"001001FC",  x"14A44953" );
1193 
 
1194 
 
1195 
        --- Áëîê 1 ---
1196 
 
1197 
        --- Äåñêðèïòîð 0 ---
1198 
        int_mem_write( cmd, ret, x"00100200",  x"00008020" );
1199 
        int_mem_write( cmd, ret, x"00100204",  x"00000011" );   -- ïåðåõîä ê ñëåäóþùåìó äåñêðèïòîðó
1200 
 
1201 
        --- Äåñêðèïòîð 1 ---
1202 
        int_mem_write( cmd, ret, x"00100208",  x"00008030" );
1203 
        int_mem_write( cmd, ret, x"0010020C",  x"00000010" );   -- îñòàíîâêà
1204 
 
1205 
 
1206 
        int_mem_write( cmd, ret, x"001003F8",  x"00000000" );
1207 
        int_mem_write( cmd, ret, x"001003FC",  x"D6BC4953" );
1208 
 
1209 
 
1210 
 
1211 
        ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ----
1212 
        block_write( cmd, ret, 5, 8, x"00000023" );             -- DMA_MODE  - ñ çàïðîñàìè
1213 
        --block_write( cmd, ret, 5, 8, x"00000021" );           -- DMA_MODE - áåç çàïðîñîâ
1214 
        block_write( cmd, ret, 5, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
1215 
 
1216 
        block_write( cmd, ret, 5, 20, x"00100000" );    -- PCI_ADRL
1217 
        block_write( cmd, ret, 5, 21, x"00100000" );    -- PCI_ADRH
1218 
        block_write( cmd, ret, 5, 23, x"00001000" );    -- LOCAL_ADR
1219 
 
1220 
 
1221 
        ---- Ïîäãîòîâêà òåòðàäû ----
1222 
--      trd_test_mode( cmd, ret, 0 );   -- ïåðåõîä â ðàáî÷èé ðåæèì --
1223 
--      trd_wait_cmd( cmd, ret, 0, 16, x"1700" );               -- DMAR0 - îò òåòðàäû 7 --
1224 
--
1225 
--      trd_wait_cmd( cmd, ret, 1, 16#1D#, x"0001" );   -- Ðàçìåð áëîêà = 4 êÁ --
1226 
 
1227 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000001" ); -- ñáðîñ
1228 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000000" );
1229 
        wb_block_check_read( cmd, ret, REG_BLOCK_ID, data ); -- ÷òåíèå èäåíòèôèêàòîðà áëîêà
1230 
        write( str, string'("BLOCK TEST_CHECK  ID: " ));
1231 
        hwrite( str, data );
1232 
        writeline( log, str );
1233 
 
1234 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_SIZE, x"00000001" ); -- ðàçìåð áëîêà - 1 êèëîáàéò
1235 
 
1236 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"000006A0" ); -- çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè
1237 
        --
1238 
        --
1239 
        --
1240 
        data:=wb_block_check_burst_ctrl_build('1', 40, 473);
1241 
        wb_block_check_write( cmd, ret, REG_TEST_CHECK_WBS_BURST_CTRL, data);
1242 
        --
1243 
        --
1244 
        --
1245 
        block_write( cmd, ret, 5, 9, x"00000001" );             -- DMA_CTRL - START
1246 
 
1247 
--      trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" );   -- Ïîäêëþ÷åíèå âûõîäà ãåíåðàòîðà ê DIO_IN --
1248 
--
1249 
--      trd_wait_cmd( cmd, ret, 7,      0, x"2038" );           -- çàïóñê òåòðàäû DIO_OUT
1250 
--
1251 
--      trd_wait_cmd( cmd, ret, 1, 16#1C#, x"0020" );   -- Çàïóñê òåñòîâîé ïîñëåäîâàòåëüíîñòè --
1252 
 
1253 
        wait for 20 us;
1254 
 
1255 
 
1256 
        for ii in 0 to 20 loop
1257 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1258 
 
1259 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1260 
                if( data( 8 )='1' ) then
1261 
                        write( str, string'(" - Äåñêðèïòîð ïðàâèëüíûé" ));
1262 
                        error := 0;
1263 
                        exit;
1264 
                else
1265 
                        write( str, string'(" - Îøèáêà ÷òåíèÿ äåñêðèïòîðà" ));
1266 
                        error := error + 1;
1267 
                        wait for 10 us;
1268 
                end if;
1269 
 
1270 
                writeline( log, str );
1271 
        end loop;
1272 
 
1273 
 
1274 
        if( error=0 ) then
1275 
 
1276 
                kk:=0;
1277 
                loop
1278 
 
1279 
--              trd_status( cmd, ret, 6, status );
1280 
--              write( str, string'("TRD_STATUS: " )); hwrite( str, status );
1281 
 
1282 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1283 
                write( str, string'("    STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1284 
 
1285 
                        if( data(4)='1' ) then
1286 
                                write( str, string'(" - çàâåðøåíà ïåðåäà÷à áëîêà " ));
1287 
                                block_write( cmd, ret, 4, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
1288 
                                kk:=kk+1;
1289 
                                if( kk=4 ) then
1290 
                                        exit;
1291 
                                end if;
1292 
                        end if;
1293 
                        writeline( log, str );
1294 
 
1295 
                        wait for 500 ns;
1296 
 
1297 
 
1298 
                end loop;
1299 
 
1300 
                ---- Îæèäàíèå çàâåðøåíèÿ DMA ----
1301 
                dma_complete := 0;
1302 
                for ii in 0 to 100 loop
1303 
 
1304 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1305 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1306 
 
1307 
                        if( data(4)='1' ) then
1308 
                                write( str, string'(" - çàâåðø¸íà ïåðåäà÷à áëîêà " ));
1309 
 
1310 
                                block_write( cmd, ret, 5, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
1311 
 
1312 
                        end if;
1313 
                        writeline( log, str );
1314 
 
1315 
 
1316 
                        if( data(5)='1' ) then
1317 
                                write( str, string'(" - DMA çàâåðø¸í " ));
1318 
                                dma_complete := 1;
1319 
 
1320 
                                block_write( cmd, ret, 5, 16#11#, x"00000010" );                -- FLAG_CLR - ñáðîñ EOT
1321 
 
1322 
                        end if;
1323 
                        writeline( log, str );
1324 
 
1325 
                        if( dma_complete=1 ) then
1326 
                                exit;
1327 
                        end if;
1328 
 
1329 
                        wait for 1 us;
1330 
 
1331 
                end loop;
1332 
 
1333 
                writeline( log, str );
1334 
 
1335 
                if( dma_complete=0 ) then
1336 
                        write( str, string'("Îøèáêà - DMA íå çàâåðø¸í " ));
1337 
                        writeline( log, str );
1338 
                        error:=error+1;
1339 
                end if;
1340 
 
1341 
        end if;
1342 
 
1343 
        for ii in 0 to 3 loop
1344 
 
1345 
                block_read( cmd, ret, 5, 16, data );                    -- STATUS
1346 
                write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1347 
                writeline( log, str );
1348 
                wait for 500 ns;
1349 
 
1350 
        end loop;
1351 
 
1352 
        wait for 10 us;
1353 
 
1354 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_RD, data );
1355 
        write( str, string'( "Ïðèíÿòî áëîêîâ: " ) );
1356 
        hwrite( str, data );
1357 
        kk := conv_integer( data );
1358 
        if( 4/=kk ) then
1359 
                write( str, string'( " - Îøèáêà" ) );
1360 
                error := error + 1;
1361 
        else
1362 
                write( str, string'( " - Ok" ) );
1363 
        end if;
1364 
        writeline( log, str );
1365 
 
1366 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_OK, data );
1367 
        write( str, string'( "TEST_CHECK_BL_OK: " ) );
1368 
        hwrite( str, data );
1369 
        kk := conv_integer( data );
1370 
        if( 3/=kk ) then
1371 
                write( str, string'( " - Îøèáêà" ) );
1372 
                error := error + 1;
1373 
        else
1374 
                write( str, string'( " - Ok" ) );
1375 
        end if;
1376 
        writeline( log, str );
1377 
 
1378 
        wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_ERROR, data );
1379 
        write( str, string'( "TEST_CHECK_BL_ERROR: " ) );
1380 
        hwrite( str, data );
1381 
        kk := conv_integer( data );
1382 
        if( 0/=kk ) then
1383 
                write( str, string'( " - Îøèáêà" ) );
1384 
                error := error + 1;
1385 
        else
1386 
                write( str, string'( " - Ok" ) );
1387 
        end if;
1388 
        writeline( log, str );
1389 
 
1390 
 
1391 
 
1392 
        block_write( cmd, ret, 5, 9, x"00000000" );             -- DMA_CTRL - STOP
1393 
 
1394 
 
1395 
--      block_write( cmd, ret, 4, 9, x"00000010" );             -- DMA_CTRL - RESET FIFO
1396 
--      block_write( cmd, ret, 4, 9, x"00000000" );             -- DMA_CTRL
1397 
--      block_write( cmd, ret, 4, 9, x"00000001" );             -- DMA_CTRL - START
1398 
 
1399 
 
1400 
        writeline( log, str );
1401 
        if( error=0 ) then
1402 
                write( str, string'(" Òåñò çàâåðø¸í óñïåøíî " ));
1403 
                cnt_ok := cnt_ok + 1;
1404 
        else
1405 
                write( str, string'(" Òåñò íå âûïîëíåí " ));
1406 
                cnt_error := cnt_error + 1;
1407 
        end if;
1408 
        writeline( log, str );
1409 
        writeline( log, str );
1410 
 
1411 
end test_adm_write_16kb;
1412 
---------------------------------------------------------------------------------------------------
1413 
--
1414 
-- My procedure for test Updated Design (test_read_4kb like refenernce)
1415 
--
1416 
procedure test_num_1 (
1417 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1418 
                            signal  ret:    in  bh_ret  --! answer
1419 2 dsmv 
                        ) is
1420 
 
1421 
    variable    adr             : std_logic_vector( 31 downto 0 );
1422 
    variable    data            : std_logic_vector( 31 downto 0 );
1423 
    variable    str             : line;
1424 
 
1425 
    variable    error           : integer:=0;
1426 
    variable    dma_complete    : integer:=0;
1427 
 
1428 
begin
1429 
    -- Init Header
1430 
    write( str, string'("TEST#1: simple test of WB CORSS logic - read from empty place" ));
1431 
    writeline( log, str );
1432 
    --
1433 
    ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
1434 
    for ii in 0 to 127 loop
1435 
        adr:= x"00100000";
1436 
        adr:=adr + ii*4;
1437 
        int_mem_write( cmd, ret, adr,  x"00000000" );
1438 
    end loop;
1439 
    -- HOST MEM Writes:
1440 
    int_mem_write( cmd, ret, x"00100000",  x"00008000" );   --
1441 
    int_mem_write( cmd, ret, x"00100004",  x"00000100" );   --
1442 
 
1443 
    int_mem_write( cmd, ret, x"001001F8",  x"00000000" );   --
1444 
    int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );   --
1445 
    --
1446 
    ---- Ïðîãðàììèðîâàíèå êàíàëà DMA ---- PE_EXT_FIFO module: have bug in PE_EXT_FIFO, for check WB we will make a trick:
1447 
    block_write( cmd, ret, 4, 8, x"00000027" );     -- DMA_MODE - DEMAND_MODE==ON
1448 
    block_write( cmd, ret, 4, 9, x"00000010" );     -- DMA_CTRL - RESET FIFO
1449 
 
1450 
    block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
1451 
    block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
1452 
    block_write( cmd, ret, 4, 23, x"0000A400" );    -- LOCAL_ADR : xA400 addr - check WB CROSS logic, rx value must be EQU to p_TEST_DATA_64BIT in current design
1453 
 
1454 
    block_write( cmd, ret, 4, 9, x"00000001" );     -- DMA_CTRL - START
1455 
    --
1456 
    -- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
1457 
    wait for 1 us;
1458 
    block_write( cmd, ret, 4, 8, x"00000025" );     -- DMA_MODE - DEMAND_MODE==OFF
1459 
    --
1460 
    -- Delay for design
1461 
    wait for 20 us;
1462 
    --
1463 
    -- Read STATUS
1464 
    block_read( cmd, ret, 4, 16, data );
1465 
    -- Construct LOG MSG in accordance to STATUS value and update ERR counter
1466 
    write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1467 
    if( data( 8 )='1' ) then
1468 
        write( str, string'(" - Descriptor==OK" ));
1469 
    else
1470 
        write( str, string'(" - Descriptor RD ERR" ));
1471 
        error := error + 1;
1472 
    end if;
1473 
    writeline( log, str );  -- upd LOGFILE
1474 
    --
1475 
    -- Deal with STATUS Results:
1476 
    if( error=0 ) then  -- w8ing for DMA final
1477 
        dma_complete := 0;
1478 
        for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
1479 
            -- Read STATUS
1480 
            block_read( cmd, ret, 4, 16, data );
1481 
            -- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
1482 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1483 
            if( data(5)='1' ) then
1484 
                write( str, string'(" - DMA finished" ));
1485 
                dma_complete := 1;
1486 
            end if;
1487 
            writeline( log, str );
1488 
            -- Check "dma_complete"
1489 
            if( dma_complete=1 ) then
1490 
                exit;           -- EXIT Loop on FINAL
1491 
            else
1492 
                wait for 1 us;  -- DELAY in other case
1493 
            end if;
1494 
        end loop;
1495 
        writeline( log, str );  -- upd LOGFILE
1496 
 
1497 
        if( dma_complete=0 ) then   -- check "dma_complete" after all
1498 
            write( str, string'("ERR - DMA not finished " ));
1499 
            writeline( log, str );
1500 
            error:=error+1;
1501 
        end if;
1502 
 
1503 
    end if;
1504 
    --
1505 
    -- Print STATUS now
1506 
    for ii in 0 to 3 loop   -- print STATUS value 4 times with 0.5us delay after
1507 
        -- Read STATUS
1508 
        block_read( cmd, ret, 4, 16, data );
1509 
        -- Construct LOG MSG in accordance to STATUS value
1510 
        write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1511 
        -- upd LOGFILE
1512 
        writeline( log, str );
1513 
        wait for 500 ns;
1514 
    end loop;
1515 
    --
1516 
    -- Now STOP Design
1517 
    block_write( cmd, ret, 4, 9, x"00000000" );     -- DMA_CTRL - STOP
1518 
    --
1519 
    -- Now print RX values:
1520 
    --
1521 
    -- Construct Header:
1522 
    writeline( log, str );
1523 
    write( str, string'("PRINT 1st 15 RX values: " ));
1524 
    writeline( log, str );
1525 
    -- Get first 15 DATA values and print it:
1526 
    for ii in 0 to 15 loop
1527 
        adr:= x"00800000";                      -- init ADDR value
1528 
        adr:=adr + ii*4;                        -- upd addr to curr idx
1529 
        int_mem_read( cmd, ret, adr,  data );   -- HOST MEM Read
1530 
        -- Construct LOG MSG in accordance to HOST MEM Read value
1531 
        --write( str, ii ); write( str, string'("   " )); hwrite( str, data );
1532 
        hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
1533 
        writeline( log, str );  -- upd LOGFILE
1534 
    end loop;
1535 
    writeline( log, str );      -- upd LOGFILE
1536 
    --
1537 
    -- Final CHECK errors:
1538 
    if( error=0 ) then
1539 
        write( str, string'("SUCCSESSFULL FINAL " ));
1540 
        cnt_ok := cnt_ok + 1;
1541 
    else
1542 
        write( str, string'("FAILED FINAL " ));
1543 
        cnt_error := cnt_error + 1;
1544 
    end if;
1545 
    writeline( log, str );  -- upd LOGFILE
1546 
    writeline( log, str );  -- upd LOGFILE
1547 
    --
1548 
    -- END
1549 
end test_num_1;
1550 
--
1551 
--
1552 
--
1553 
procedure test_num_2 (
1554 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1555 
                            signal  ret:    in  bh_ret  --! answer
1556 2 dsmv 
                        ) is
1557 
 
1558 
    variable    adr             : std_logic_vector( 31 downto 0 );
1559 
    variable    data            : std_logic_vector( 31 downto 0 );
1560 
    variable    data64          : std_logic_vector( 63 downto 0 );
1561 
    variable    str             : line;
1562 
 
1563 
    variable    error           : integer:=0;
1564 
    variable    dma_complete    : integer:=0;
1565 
 
1566 
begin
1567 
    -- Init Header
1568 
    write( str, string'("TEST#2: Get data from TEST_GEN.WB_BURST_SLAVE" ));
1569 
    writeline( log, str );
1570 
    --
1571 
    ---- Ôîðìèðîâàíèå áëîêà äåñêðèïòîðîâ ---
1572 
    for ii in 0 to 127 loop
1573 
        adr:= x"00100000";
1574 
        adr:=adr + ii*4;
1575 
        int_mem_write( cmd, ret, adr,  x"00000000" );
1576 
    end loop;
1577 
    -- HOST MEM Writes:
1578 
    int_mem_write( cmd, ret, x"00100000",  x"00008000" );   --
1579 
    int_mem_write( cmd, ret, x"00100004",  x"00000100" );   --
1580 
 
1581 
    int_mem_write( cmd, ret, x"001001F8",  x"00000000" );   --
1582 
    int_mem_write( cmd, ret, x"001001FC",  x"762C4953" );   --
1583 
    --
1584 
    -- TEST_GEN.WB_CFG_SLAVE: config TEST_GEN
1585 
    adr     :=x"20002048";              --  TEST_GEN.WB_CFG_SLAVE.TEST_GEN_SIZE
1586 
    data64  :=x"0000000000000001";      --  TEST_GEN_SIZE=x01
1587 
    data_write64(cmd, ret, adr, data64);--  PCIE WR
1588 
 
1589 
    adr     :=x"20002040";              --  TEST_GEN.WB_CFG_SLAVE.TEST_GEN_CTRL
1590 
    data64  :=x"0000000000000022";      --  TEST_GEN_CTRL=x22 (START=1, TEST_GEN.di_start=1)
1591 
    data_write64(cmd, ret, adr, data64);--  PCIE WR
1592 
 
1593 
    -- PE_EXT_FIFO module config: --> have a bug in PE_EXT_FIFO, for check WB we will make a trick:
1594 
    block_write( cmd, ret, 4, 8, x"00000027" );     -- DMA_MODE - DEMAND_MODE==ON
1595 
    block_write( cmd, ret, 4, 9, x"00000010" );     -- DMA_CTRL - RESET FIFO
1596 
 
1597 
    block_write( cmd, ret, 4, 20, x"00100000" );    -- PCI_ADRL
1598 
    block_write( cmd, ret, 4, 21, x"00100000" );    -- PCI_ADRH
1599 
    block_write( cmd, ret, 4, 23, x"00003000" );    -- LOCAL_ADR: TEST_GEN.WB_BURST_SLAVE
1600 
 
1601 
    block_write( cmd, ret, 4, 9, x"00000001" );     -- DMA_CTRL - START
1602 
    --
1603 
    -- Delay for design: trick for afoid bug in PE_EXT_FIFO --> Îøèáêà #24
1604 
    wait for 1 us;
1605 
    block_write( cmd, ret, 4, 8, x"00000025" );     -- DMA_MODE - DEMAND_MODE==OFF
1606 
    --
1607 
    -- Delay for design
1608 
    wait for 20 us;
1609 
    --
1610 
    -- Read STATUS (check RD DESCR status):
1611 
    block_read( cmd, ret, 4, 16, data );
1612 
    -- Construct LOG MSG in accordance to STATUS value and update ERR counter
1613 
    write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1614 
    if( data( 8 )='1' ) then
1615 
        write( str, string'(" - Descriptor==OK" ));
1616 
    else
1617 
        write( str, string'(" - Descriptor RD ERR" ));
1618 
        error := error + 1;
1619 
    end if;
1620 
    writeline( log, str );  -- upd LOGFILE
1621 
    --
1622 
    -- W8ing for DMA finish:
1623 
    if( error=0 ) then  -- w8ing for DMA final
1624 
        dma_complete := 0;
1625 
        for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
1626 
            -- Read STATUS
1627 
            block_read( cmd, ret, 4, 16, data );
1628 
            -- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
1629 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1630 
            if( data(5)='1' ) then
1631 
                write( str, string'(" - DMA finished" ));
1632 
                dma_complete := 1;
1633 
            end if;
1634 
            writeline( log, str );
1635 
            -- Check "dma_complete"
1636 
            if( dma_complete=1 ) then
1637 
                exit;           -- EXIT Loop on FINAL
1638 
            else
1639 
                wait for 1 us;  -- DELAY in other case
1640 
            end if;
1641 
        end loop;
1642 
        writeline( log, str );  -- upd LOGFILE
1643 
 
1644 
        if( dma_complete=0 ) then   -- check "dma_complete" after all
1645 
            write( str, string'("ERR - DMA not finished " ));
1646 
            writeline( log, str );
1647 
            error:=error+1;
1648 
        end if;
1649 
 
1650 
    end if;
1651 
    --
1652 
    -- Print STATUS in ERR
1653 
    if (error /= 0 ) then
1654 
        for ii in 0 to 3 loop   -- print STATUS value 4 times with 0.5us delay after
1655 
            -- Read STATUS
1656 
            block_read( cmd, ret, 4, 16, data );
1657 
            -- Construct LOG MSG in accordance to STATUS value
1658 
            write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
1659 
            -- upd LOGFILE
1660 
            writeline( log, str );
1661 
            wait for 500 ns;
1662 
        end loop;
1663 
    end if;
1664 
    --
1665 
    -- Now STOP Design
1666 
    block_write( cmd, ret, 4, 9, x"00000000" );     -- DMA_CTRL - STOP
1667 
    --
1668 
    -- Now print RX values:
1669 
    --
1670 
    -- Construct Header:
1671 
    writeline( log, str );
1672 
    write( str, string'("PRINT 1st 15 RX values: " ));
1673 
    writeline( log, str );
1674 
    -- Get first 15 DATA values and print it:
1675 
    for ii in 0 to 15 loop
1676 
        adr:= x"00800000";                      -- init ADDR value
1677 
        adr:=adr + ii*4;                        -- upd addr to curr idx
1678 
        int_mem_read( cmd, ret, adr,  data );   -- HOST MEM Read
1679 
        -- Construct LOG MSG in accordance to HOST MEM Read value
1680 
        --write( str, ii ); write( str, string'("   " )); hwrite( str, data );
1681 
        hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
1682 
        writeline( log, str );  -- upd LOGFILE
1683 
    end loop;
1684 
    writeline( log, str );      -- upd LOGFILE
1685 
    --
1686 
    -- Final CHECK errors:
1687 
    if( error=0 ) then
1688 
        write( str, string'(" stb SUCCSESSFULL FINAL " ));
1689 
        cnt_ok := cnt_ok + 1;
1690 
    else
1691 
        write( str, string'(" stb FAILED FINAL " ));
1692 
        cnt_error := cnt_error + 1;
1693 
    end if;
1694 
    writeline( log, str );  -- upd LOGFILE
1695 
    writeline( log, str );  -- upd LOGFILE
1696 
    --
1697 
    -- END
1698 
end test_num_2;
1699 
---------------------------------------------------------------------------------------------------
1700 
--
1701 
-- My procedure for test WB stuff in Design:
1702 
--  ==> TEST_CHECK.WB_CFG_SLAVE
1703 
--
1704 
procedure test_wb_1 (
1705 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1706 
                            signal  ret:    in  bh_ret  --! answer
1707 2 dsmv 
                    ) is
1708 
 
1709 
    variable    adr             : std_logic_vector( 31 downto 0 );
1710 
    variable    data32          : std_logic_vector( 31 downto 0 );
1711 
    variable    data64          : std_logic_vector( 63 downto 0 );
1712 
    variable    str             : line;
1713 
 
1714 
    variable    error           : integer:=0;
1715 
    variable    dma_complete    : integer:=0;
1716 
 
1717 
    --
1718 
    --
1719 
    type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
1720 
    type wb_cfg_slave_data is record
1721 
        const   :   wb_cfg_slave_value(7 downto 0);
1722 
        cmd     :   wb_cfg_slave_value(7 downto 0);
1723 
        sts     :   wb_cfg_slave_value(7 downto 0);
1724 
    end record;
1725 
    --
1726 
    --
1727 
    variable    st_wb_cfg_slave_data_0  :   wb_cfg_slave_data;
1728 
    variable    st_wb_cfg_slave_data_1  :   wb_cfg_slave_data;
1729 
    variable    st_wb_cfg_slave_data_2  :   wb_cfg_slave_data;
1730 
 
1731 
 
1732 
begin
1733 
    -- Init Header
1734 
    write( str, string'("START TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE"));
1735 
    writeline( log, str );
1736 
    --
1737 
    -- Read "TEST_CHECK.WB_CFG_SLAVE"
1738 
    write( str, string'("1) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
1739 
    writeline( log, str );
1740 
    adr     := x"20000000";
1741 
 
1742 
    TEST_CHECK_WB_CFG_SLAVE_RD_00   :   for i in 0 to 2 loop
1743 
        TEST_CHECK_WB_CFG_SLAVE_RD_01   :   for j in 0 to 7 loop
1744 
            -- PCIE RD
1745 
            data_read64(cmd, ret, adr, data64);
1746 
            -- Put RD_Value to apropriate holder
1747 
            if (i=0) then       -- const
1748 
                st_wb_cfg_slave_data_0.const(j) := data64;
1749 
            elsif (i=1) then    -- cmd
1750 
                st_wb_cfg_slave_data_0.cmd(j)   := data64;
1751 
            else                -- sts
1752 
                st_wb_cfg_slave_data_0.sts(j)   := data64;
1753 
            end if;
1754 
            -- Incr ADDR
1755 
            adr := adr + x"00000008";
1756 
            -- Print RD_Value
1757 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1758 
            writeline( log, str );
1759 
 
1760 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
1761 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
1762 
 
1763 
    --
1764 
    -- Write
1765 
    write( str, string'("2) Write 'TEST_CHECK.WB_CFG_SLAVE'"));
1766 
    writeline( log, str );
1767 
    adr     := x"20000000";
1768 
 
1769 
    TEST_CHECK_WB_CFG_SLAVE_WR_00   :   for i in 0 to 2 loop
1770 
        TEST_CHECK_WB_CFG_SLAVE_WR_01   :   for j in 0 to 7 loop
1771 
            -- Prepare WR_Value
1772 
            data64 := conv_std_logic_vector(i*100+j*10+5, 64);
1773 
            -- PCIE WR
1774 
            data_write64(cmd, ret, adr, data64);
1775 
            -- Put WR_Value to apropriate holder
1776 
            if (i=0) then       -- const
1777 
                st_wb_cfg_slave_data_1.const(j) := data64;
1778 
            elsif (i=1) then    -- cmd
1779 
                st_wb_cfg_slave_data_1.cmd(j)   := data64;
1780 
            else                -- sts
1781 
                st_wb_cfg_slave_data_1.sts(j)   := data64;
1782 
            end if;
1783 
            -- Incr ADDR
1784 
            adr := adr + x"00000008";
1785 
            -- Print WR_Value
1786 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1787 
            writeline( log, str );
1788 
 
1789 
        end loop TEST_CHECK_WB_CFG_SLAVE_WR_01;
1790 
    end loop TEST_CHECK_WB_CFG_SLAVE_WR_00;
1791 
 
1792 
    --
1793 
    -- Read
1794 
    write( str, string'("3) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
1795 
    writeline( log, str );
1796 
    adr     := x"20000000";
1797 
 
1798 
    TEST_CHECK_WB_CFG_SLAVE_RD_10   :   for i in 0 to 2 loop
1799 
        TEST_CHECK_WB_CFG_SLAVE_RD_11   :   for j in 0 to 7 loop
1800 
            -- PCIE RD
1801 
            data_read64(cmd, ret, adr, data64);
1802 
            -- Put RD_Value to apropriate holder
1803 
            if (i=0) then       -- const
1804 
                st_wb_cfg_slave_data_2.const(j) := data64;
1805 
            elsif (i=1) then    -- cmd
1806 
                st_wb_cfg_slave_data_2.cmd(j)   := data64;
1807 
            else                -- sts
1808 
                st_wb_cfg_slave_data_2.sts(j)   := data64;
1809 
            end if;
1810 
            -- Incr ADDR
1811 
            adr := adr + x"00000008";
1812 
            -- Print RD_Value
1813 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1814 
            writeline( log, str );
1815 
 
1816 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_11;
1817 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_10;
1818 
 
1819 
    --
1820 
    -- Compare results
1821 
    write( str, string'("4) Process Results:"));
1822 
    writeline( log, str );
1823 
    --  cmp#0 - constants
1824 
    CMP_CONST   :   for i in 0 to 7 loop
1825 
        if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then   -- before WR and afetr WR must be EQU (RO)
1826 
            write( str, string'("   ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1827 
            writeline( log, str );
1828 
            error := error + 1;
1829 
        end if;
1830 
    end loop CMP_CONST;
1831 
    --  cmp#1 - commands
1832 
    CMP_CMD     :   for i in 0 to 7 loop
1833 
        if  ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then     -- WR value and RD value must be EQU (RW)
1834 
            write( str, string'("   ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1835 
            writeline( log, str );
1836 
            error := error + 1;
1837 
        end if;
1838 
    end loop CMP_CMD;
1839 
    --  cmp#2 - status
1840 
    CMP_STATUS  :   for i in 0 to 7 loop
1841 
        if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then       -- before WR and afetr WR must be EQU (RO)
1842 
            write( str, string'("   ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1843 
            writeline( log, str );
1844 
            error := error + 1;
1845 
        end if;
1846 
    end loop CMP_STATUS;
1847 
    --  print OK
1848 
    if (error = 0) then
1849 
        write( str, string'("   Results==OK"));
1850 
        writeline( log, str );
1851 
        cnt_ok := cnt_ok + 1;
1852 
    else
1853 
        cnt_error := cnt_error + 1;
1854 
    end if;
1855 
 
1856 
    -- Final Header
1857 
    write( str, string'("STOP TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE" ));
1858 
    writeline( log, str );  -- upd LOGFILE
1859 
    --
1860 
    -- END
1861 
end test_wb_1;
1862 
---------------------------------------------------------------------------------------------------
1863 
--
1864 
-- My procedure for test WB stuff in Design:
1865 
--  ==> TEST_GEN.WB_CFG_SLAVE
1866 
--
1867 
procedure test_wb_2 (
1868 38 dsmv 
                            signal  cmd:    out bh_cmd; --! command
1869 
                            signal  ret:    in  bh_ret  --! answer
1870 2 dsmv 
                    ) is
1871 
 
1872 
    variable    adr             : std_logic_vector( 31 downto 0 );
1873 
    variable    data32          : std_logic_vector( 31 downto 0 );
1874 
    variable    data64          : std_logic_vector( 63 downto 0 );
1875 
    variable    str             : line;
1876 
 
1877 
    variable    error           : integer:=0;
1878 
    variable    dma_complete    : integer:=0;
1879 
 
1880 
    --
1881 
    --
1882 
    type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
1883 
    type wb_cfg_slave_data is record
1884 
        const   :   wb_cfg_slave_value(7 downto 0);
1885 
        cmd     :   wb_cfg_slave_value(7 downto 0);
1886 
        sts     :   wb_cfg_slave_value(7 downto 0);
1887 
    end record;
1888 
    --
1889 
    --
1890 
    variable    st_wb_cfg_slave_data_0  :   wb_cfg_slave_data;
1891 
    variable    st_wb_cfg_slave_data_1  :   wb_cfg_slave_data;
1892 
    variable    st_wb_cfg_slave_data_2  :   wb_cfg_slave_data;
1893 
 
1894 
 
1895 
begin
1896 
    -- Init Header
1897 
    write( str, string'("START TEST_WB#2: TEST_GEN.WB_CFG_SLAVE"));
1898 
    writeline( log, str );
1899 
    --
1900 
    -- Read "TEST_CHECK.WB_CFG_SLAVE"
1901 
    write( str, string'("1) Read 'TEST_GEN.WB_CFG_SLAVE'"));
1902 
    writeline( log, str );
1903 
    adr     := x"20002000";
1904 
 
1905 
    TEST_CHECK_WB_CFG_SLAVE_RD_00   :   for i in 0 to 2 loop
1906 
        TEST_CHECK_WB_CFG_SLAVE_RD_01   :   for j in 0 to 7 loop
1907 
            -- PCIE RD
1908 
            data_read64(cmd, ret, adr, data64);
1909 
            -- Put RD_Value to apropriate holder
1910 
            if (i=0) then       -- const
1911 
                st_wb_cfg_slave_data_0.const(j) := data64;
1912 
            elsif (i=1) then    -- cmd
1913 
                st_wb_cfg_slave_data_0.cmd(j)   := data64;
1914 
            else                -- sts
1915 
                st_wb_cfg_slave_data_0.sts(j)   := data64;
1916 
            end if;
1917 
            -- Incr ADDR
1918 
            adr := adr + x"00000008";
1919 
            -- Print RD_Value
1920 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1921 
            writeline( log, str );
1922 
 
1923 
        end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
1924 
    end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
1925 
 
1926 
    --
1927 
    -- Write
1928 
    write( str, string'("2) Write 'TEST_GEN.WB_CFG_SLAVE'"));
1929 
    writeline( log, str );
1930 
    adr     := x"20002000";
1931 
 
1932 
    TEST_GEN_WB_CFG_SLAVE_WR_00   :   for i in 0 to 2 loop
1933 
        TEST_GEN_WB_CFG_SLAVE_WR_01   :   for j in 0 to 7 loop
1934 
            -- Prepare WR_Value
1935 
            data64 := conv_std_logic_vector(i*100+j*10+5, 64);
1936 
            -- PCIE WR
1937 
            data_write64(cmd, ret, adr, data64);
1938 
            -- Put WR_Value to apropriate holder
1939 
            if (i=0) then       -- const
1940 
                st_wb_cfg_slave_data_1.const(j) := data64;
1941 
            elsif (i=1) then    -- cmd
1942 
                st_wb_cfg_slave_data_1.cmd(j)   := data64;
1943 
            else                -- sts
1944 
                st_wb_cfg_slave_data_1.sts(j)   := data64;
1945 
            end if;
1946 
            -- Incr ADDR
1947 
            adr := adr + x"00000008";
1948 
            -- Print WR_Value
1949 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1950 
            writeline( log, str );
1951 
 
1952 
        end loop TEST_GEN_WB_CFG_SLAVE_WR_01;
1953 
    end loop TEST_GEN_WB_CFG_SLAVE_WR_00;
1954 
 
1955 
    --
1956 
    -- Read
1957 
    write( str, string'("3) Read 'TEST_GEN.WB_CFG_SLAVE'"));
1958 
    writeline( log, str );
1959 
    adr     := x"20002000";
1960 
 
1961 
    TEST_GEN_WB_CFG_SLAVE_RD_10   :   for i in 0 to 2 loop
1962 
        TEST_GEN_WB_CFG_SLAVE_RD_11   :   for j in 0 to 7 loop
1963 
            -- PCIE RD
1964 
            data_read64(cmd, ret, adr, data64);
1965 
            -- Put RD_Value to apropriate holder
1966 
            if (i=0) then       -- const
1967 
                st_wb_cfg_slave_data_2.const(j) := data64;
1968 
            elsif (i=1) then    -- cmd
1969 
                st_wb_cfg_slave_data_2.cmd(j)   := data64;
1970 
            else                -- sts
1971 
                st_wb_cfg_slave_data_2.sts(j)   := data64;
1972 
            end if;
1973 
            -- Incr ADDR
1974 
            adr := adr + x"00000008";
1975 
            -- Print RD_Value
1976 
            hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
1977 
            writeline( log, str );
1978 
 
1979 
        end loop TEST_GEN_WB_CFG_SLAVE_RD_11;
1980 
    end loop TEST_GEN_WB_CFG_SLAVE_RD_10;
1981 
 
1982 
    --
1983 
    -- Compare results
1984 
    write( str, string'("4) Process Results:"));
1985 
    writeline( log, str );
1986 
    --  cmp#0 - constants
1987 
    CMP_CONST   :   for i in 0 to 7 loop
1988 
        if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then   -- before WR and afetr WR must be EQU (RO)
1989 
            write( str, string'("   ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1990 
            writeline( log, str );
1991 
            error := error + 1;
1992 
        end if;
1993 
    end loop CMP_CONST;
1994 
    --  cmp#1 - commands
1995 
    CMP_CMD     :   for i in 0 to 7 loop
1996 
        if  ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then     -- WR value and RD value must be EQU (RW)
1997 
            write( str, string'("   ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
1998 
            writeline( log, str );
1999 
            error := error + 1;
2000 
        end if;
2001 
    end loop CMP_CMD;
2002 
    --  cmp#2 - status
2003 
    CMP_STATUS  :   for i in 0 to 7 loop
2004 
        if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then       -- before WR and afetr WR must be EQU (RO)
2005 
            write( str, string'("   ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
2006 
            writeline( log, str );
2007 
            error := error + 1;
2008 
        end if;
2009 
    end loop CMP_STATUS;
2010 
    --  print OK
2011 
    if (error = 0) then
2012 
        write( str, string'("   Results==OK"));
2013 
        writeline( log, str );
2014 
        cnt_ok := cnt_ok + 1;
2015 
    else
2016 
        cnt_error := cnt_error + 1;
2017 
    end if;
2018 
 
2019 
    -- Final Header
2020 
    write( str, string'("STOP TEST_WB#2: TEST_GEN.WB_CFG_SLAVE" ));
2021 
    writeline( log, str );  -- upd LOGFILE
2022 
    --
2023 
    -- END
2024 
end test_wb_2;
2025 
---------------------------------------------------------------------------------------------------
2026 
end package     body test_pkg;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.