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-- Project name: pcie_mini_axi4s_wb, device top level file, EXAMPLE DESIGN
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-- This is an example device top level file, where the pcie_mini_axi4s_wb is instantiated.
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-- Functions: PCIe endpoint, a register block, 2 LED outputs.
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--
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-- YOU don't need this file in your own custom design !!! This file is only demonstration.
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--
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-- Engineer: Istvan Nagy, buenoshun@gmail.com
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--
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-- Create Date: 10/10/2019
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-- Modify date: 10/10/2019
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-- Design Name: example_device_top encapsulating pcie_mini_axi4s_wb
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-- Version: 1.0
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-- Tool versions: Vivado 2019.1
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--
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-- Target Devices: Xilinx usc+ FPGAs.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--entity header ----------------------------------------------------------------
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entity example_device_top is
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Port (
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pci_exp_txp : out std_logic;
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pci_exp_txn : out std_logic;
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pci_exp_rxp : in std_logic;
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pci_exp_rxn : in std_logic;
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sys_clk_n : in std_logic;
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sys_clk_p : in std_logic;
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sys_reset_n : in std_logic;
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debug_pins : out std_logic_vector(31 downto 0);
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scan_pins : in std_logic_vector(31 downto 0);
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led_out_1 : out std_logic;
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led_out_2 : out std_logic
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);
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end example_device_top;
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--architecture start ------------------------------------------------------------
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architecture Behavioral of example_device_top is
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-- INTERNAL SIGNALS -------------------------------------------------------------
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SIGNAL dummy0: std_logic;
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SIGNAL dummy1: std_logic_VECTOR(6 DOWNTO 0);
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SIGNAL pcie_bar0_wb_data_o : std_logic_vector(31 downto 0);
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SIGNAL pcie_bar0_wb_data_i : std_logic_vector(31 downto 0);
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SIGNAL pcie_bar0_wb_addr_o : std_logic_vector(27 downto 0);
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SIGNAL pcie_bar0_wb_cyc_o : std_logic;
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SIGNAL pcie_bar0_wb_stb_o : std_logic;
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SIGNAL pcie_bar0_wb_wr_o : std_logic;
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SIGNAL pcie_bar0_wb_ack_i : std_logic;
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SIGNAL pcie_bar0_wb_clk_o : std_logic; --62.5MHz
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SIGNAL pcie_bar0_wb_sel_o : std_logic_vector(3 downto 0);
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SIGNAL pcie_irq : std_logic;
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SIGNAL pcie_msi_enabled : std_logic;
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SIGNAL pcie_resetout : std_logic;
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SIGNAL register_one : std_logic_vector(31 downto 0);
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SIGNAL register_two : std_logic_vector(31 downto 0);
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SIGNAL register_three : std_logic_vector(31 downto 0);
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SIGNAL register_four : std_logic_vector(31 downto 0);
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SIGNAL regxx_scratchpad : std_logic_vector(31 downto 0);
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SIGNAL scan_pins_latched1 : std_logic_vector(31 downto 0);
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SIGNAL scan_pins_latched2 : std_logic_vector(31 downto 0);
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SIGNAL wb_config_state : std_logic_vector(7 downto 0);
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SIGNAL ACK_copy : std_logic;
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--------- COMPONENT DECLARATIONS (introducing the IPs) --------------------------
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COMPONENT pcie_mini_axi4s_wb
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PORT ( --FPGA PINS(EXTERNAL):
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pci_exp_txp : out std_logic;
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pci_exp_txn : out std_logic;
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pci_exp_rxp : in std_logic;
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pci_exp_rxn : in std_logic;
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sys_clk_n : in std_logic;
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sys_clk_p : in std_logic;
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sys_reset_n : in std_logic;
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--ON CHIP PORTS:
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--DATA BUS for BAR0 (wishbone):
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pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0);
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pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
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pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
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pcie_bar0_wb_cyc_o : out std_logic;
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pcie_bar0_wb_stb_o : out std_logic;
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pcie_bar0_wb_wr_o : out std_logic;
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pcie_bar0_wb_ack_i : in std_logic;
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pcie_bar0_wb_clk_o : out std_logic; --62.5MHz
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pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
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--OTHER:
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pcie_irq : in std_logic;
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pcie_msi_enabled : out std_logic; -- added to monitor if MSI interrupt is enabled
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pcie_resetout : out std_logic --active high
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);
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END COMPONENT;
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--architecture body start -------------------------------------------------------
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begin
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--------- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------
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Inst_pcieaxiwbtop: pcie_mini_axi4s_wb
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PORT MAP (
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pci_exp_txp => pci_exp_txp,
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pci_exp_txn => pci_exp_txn,
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pci_exp_rxp => pci_exp_rxp,
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pci_exp_rxn => pci_exp_rxn,
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sys_clk_n => sys_clk_n,
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sys_clk_p => sys_clk_p,
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sys_reset_n => sys_reset_n,
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pcie_bar0_wb_data_o => pcie_bar0_wb_data_o,
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pcie_bar0_wb_data_i => pcie_bar0_wb_data_i,
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pcie_bar0_wb_addr_o => pcie_bar0_wb_addr_o,
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pcie_bar0_wb_cyc_o => pcie_bar0_wb_cyc_o,
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pcie_bar0_wb_stb_o => pcie_bar0_wb_stb_o,
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pcie_bar0_wb_wr_o => pcie_bar0_wb_wr_o,
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pcie_bar0_wb_ack_i => pcie_bar0_wb_ack_i,
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pcie_bar0_wb_clk_o => pcie_bar0_wb_clk_o,
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pcie_bar0_wb_sel_o => pcie_bar0_wb_sel_o,
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pcie_irq => pcie_irq,
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pcie_msi_enabled => pcie_msi_enabled,
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pcie_resetout => pcie_resetout
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);
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-- local Logic ------------------------------------------------------------------
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debug_pins <= register_one; --check register content with TopJtag_Probe.
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led_out_1 <= register_one(1);
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led_out_2 <= register_one(2);
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-- WISHB/SMB REGISTER SET
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wishbone: process (pcie_resetout , pcie_bar0_wb_clk_o) is
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begin
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if (pcie_resetout ='0') then
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--DAT_R(7 downto 0) <= (others => '0');
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register_one <= (OTHERS => '0');
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register_two <= (OTHERS => '0');
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register_three <= (OTHERS => '0');
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register_four <= (OTHERS => '0');
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wb_config_state <= (OTHERS => '0');
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regxx_scratchpad <= (OTHERS => '0');
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scan_pins_latched1 <= (OTHERS => '0');
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scan_pins_latched2 <= (OTHERS => '0');
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pcie_bar0_wb_data_i <= (OTHERS => '0');
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else
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if (pcie_bar0_wb_clk_o'event and pcie_bar0_wb_clk_o = '1') then
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scan_pins_latched1 <= scan_pins;
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scan_pins_latched2 <= scan_pins_latched1;
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case ( wb_config_state ) is
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--********** IDLE STATE **********
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when "00000000" => --state 0
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--WAIT FOR WISHBONE TRANSACTION:
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pcie_bar0_wb_ack_i <= '0';
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ACK_copy <= '0';
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--writes:
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if (pcie_bar0_wb_cyc_o = '1' and pcie_bar0_wb_wr_o = '1' and ACK_copy='0') then
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wb_config_state <= "00001001";
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--reads:
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elsif (pcie_bar0_wb_cyc_o = '1' and pcie_bar0_wb_wr_o = '0' and ACK_copy='0') then --read
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wb_config_state <= "00001010";
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end if;
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--********** write STATE **********
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when "00001001" => --state 1
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wb_config_state <= "00000000"; --no wait states, go back to idle
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pcie_bar0_wb_ack_i <= '1';
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ACK_copy <= '1';
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case (pcie_bar0_wb_addr_o(7 downto 0)) is
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when X"00" => register_one <= pcie_bar0_wb_data_o(31 downto 0);
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when X"01" => register_two <= pcie_bar0_wb_data_o(31 downto 0);
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when X"02" => register_three <= pcie_bar0_wb_data_o(31 downto 0);
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when X"03" => register_four <= pcie_bar0_wb_data_o(31 downto 0);
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when others => regxx_scratchpad <= pcie_bar0_wb_data_o(31 downto 0);
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end case;
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--********** read STATE **********
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when "00001010" => --state 2: registers read-out
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wb_config_state <= "00000000"; --no wait states, go back to idle
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pcie_bar0_wb_ack_i <= '1';
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ACK_copy <= '1';
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case (pcie_bar0_wb_addr_o(7 downto 0)) is
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when X"00" => pcie_bar0_wb_data_i(31 downto 0) <= register_one ;
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when X"01" => pcie_bar0_wb_data_i(31 downto 0) <= register_two ;
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when X"02" => pcie_bar0_wb_data_i(31 downto 0) <= register_three ;
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when X"03" => pcie_bar0_wb_data_i(31 downto 0) <= register_four ;
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when X"04" => pcie_bar0_wb_data_i(31 downto 0) <= scan_pins_latched2 ;
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when others => pcie_bar0_wb_data_i(31 downto 0) <= regxx_scratchpad ;
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end case;
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when others => --error state
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wb_config_state <= "00000000"; --go to state 0
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end case;
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end if;
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end if;
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end process wishbone;
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--end file ----------------------------------------------------------------------
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end Behavioral;
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