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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [synth_model/] [inout_logic.results] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
Release 12.3 - xst M.70d (nt)
2 
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
3 
-->
4 
Reading constraint file inout_logic_cw.xcf.
5 
XCF parsing done.
6 
 
7 
TABLE OF CONTENTS
8 
  1) Synthesis Options Summary
9 
  2) HDL Parsing
10 
  3) HDL Elaboration
11 
  4) HDL Synthesis
12 
       4.1) HDL Synthesis Report
13 
  5) Advanced HDL Synthesis
14 
       5.1) Advanced HDL Synthesis Report
15 
  6) Low Level Synthesis
16 
  7) Partition Report
17 
  8) Design Summary
18 
       8.1) Primitive and Black Box Usage
19 
       8.2) Device utilization summary
20 
       8.3) Partition Resource Summary
21 
       8.4) Timing Report
22 
            8.4.1) Clock Information
23 
            8.4.2) Asynchronous Control Signals Information
24 
            8.4.3) Timing Summary
25 
            8.4.4) Timing Details
26 
            8.4.5) Cross Clock Domains Report
27 
 
28 
 
29 
=========================================================================
30 
*                      Synthesis Options Summary                        *
31 
=========================================================================
32 
---- Source Parameters
33 
Input File Name                    : "xst_inout_logic.prj"
34 
Input Format                       : mixed
35 
Synthesis Constraint File          : inout_logic_cw.xcf
36 
 
37 
---- Target Parameters
38 
Output File Name                   : "inout_logic_cw.ngc"
39 
Output Format                      : NGC
40 
Target Device                      : xc6vlx240t-3ff784
41 
 
42 
---- Source Options
43 
Entity Name                        : inout_logic_cw
44 
Top Module Name                    : inout_logic_cw
45 
Automatic Register Balancing       : no
46 
 
47 
---- Target Options
48 
Add IO Buffers                     : NO
49 
Pack IO Registers into IOBs        : Auto
50 
 
51 
---- General Options
52 
Keep Hierarchy                     : NO
53 
Bus Delimiter                      : ()
54 
Hierarchy Separator                : /
55 
Write Timing Constraints           : yes
56 
 
57 
---- Other Options
58 
report_timing_constraint_problems  : warning
59 
 
60 
=========================================================================
61 
 
62 
WARNING:Xst:29 - Optimization Effort not specified
63 
The following parameters have been added:
64 
Optimization Goal                  : SPEED
65 
 
66 
=========================================================================
67 
 
68 
=========================================================================
69 
*                          HDL Parsing                                  *
70 
=========================================================================
71 
Parsing VHDL file "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic.vhd" into library work
72 
Parsing package .
73 
Parsing package body .
74 
Parsing entity .
75 
Parsing architecture  of entity .
76 
Parsing entity .
77 
Parsing architecture  of entity .
78 
Parsing entity .
79 
Parsing architecture  of entity .
80 
Parsing entity .
81 
Parsing architecture  of entity .
82 
Parsing entity .
83 
Parsing architecture  of entity .
84 
Parsing entity .
85 
Parsing architecture  of entity .
86 
Parsing entity .
87 
Parsing architecture  of entity .
88 
Parsing VHDL file "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" into library work
89 
Parsing entity .
90 
Parsing architecture  of entity .
91 
Parsing entity .
92 
Parsing architecture  of entity .
93 
Parsing entity .
94 
Parsing architecture  of entity .
95 
 
96 
=========================================================================
97 
*                            HDL Elaboration                            *
98 
=========================================================================
99 
 
100 
Elaborating entity  (architecture ) from library .
101 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 986: Assignment to to_register10_dout_net ignored, since the identifier is never used
102 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 987: Assignment to to_register11_dout_net ignored, since the identifier is never used
103 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 988: Assignment to to_register12_dout_net ignored, since the identifier is never used
104 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 989: Assignment to to_register13_dout_net ignored, since the identifier is never used
105 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 990: Assignment to to_register14_dout_net ignored, since the identifier is never used
106 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 991: Assignment to to_register15_dout_net ignored, since the identifier is never used
107 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 992: Assignment to to_register16_dout_net ignored, since the identifier is never used
108 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 993: Assignment to to_register17_dout_net ignored, since the identifier is never used
109 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 994: Assignment to to_register18_dout_net ignored, since the identifier is never used
110 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 995: Assignment to to_register19_dout_net ignored, since the identifier is never used
111 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 996: Assignment to to_register1_dout_net ignored, since the identifier is never used
112 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 997: Assignment to to_register20_dout_net ignored, since the identifier is never used
113 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 998: Assignment to to_register21_dout_net ignored, since the identifier is never used
114 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 999: Assignment to to_register22_dout_net ignored, since the identifier is never used
115 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1000: Assignment to to_register23_dout_net ignored, since the identifier is never used
116 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1001: Assignment to to_register24_dout_net ignored, since the identifier is never used
117 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1002: Assignment to to_register25_dout_net ignored, since the identifier is never used
118 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1003: Assignment to to_register26_dout_net ignored, since the identifier is never used
119 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1004: Assignment to to_register27_dout_net ignored, since the identifier is never used
120 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1005: Assignment to to_register28_dout_net ignored, since the identifier is never used
121 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1006: Assignment to to_register29_dout_net ignored, since the identifier is never used
122 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1007: Assignment to to_register2_dout_net ignored, since the identifier is never used
123 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1008: Assignment to to_register30_dout_net ignored, since the identifier is never used
124 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1009: Assignment to to_register31_dout_net ignored, since the identifier is never used
125 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1010: Assignment to to_register32_dout_net ignored, since the identifier is never used
126 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1011: Assignment to to_register33_dout_net ignored, since the identifier is never used
127 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1012: Assignment to to_register34_dout_net ignored, since the identifier is never used
128 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1013: Assignment to to_register3_dout_net ignored, since the identifier is never used
129 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1014: Assignment to to_register4_dout_net ignored, since the identifier is never used
130 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1015: Assignment to to_register5_dout_net ignored, since the identifier is never used
131 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1016: Assignment to to_register6_dout_net ignored, since the identifier is never used
132 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1017: Assignment to to_register7_dout_net ignored, since the identifier is never used
133 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1018: Assignment to to_register8_dout_net ignored, since the identifier is never used
134 
WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1019: Assignment to to_register9_dout_net ignored, since the identifier is never used
135 
 
136 
Elaborating entity  (architecture ) from library .
137 
 
138 
Elaborating entity  (architecture ) with generics from library .
139 
 
140 
Elaborating entity  (architecture ) with generics from library .
141 
 
142 
Elaborating entity  (architecture ) with generics from library .
143 
WARNING:HDLCompiler:89 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic.vhd" Line 1653:  remains a black-box since it has no binding entity.
144 
 
145 
Elaborating entity  (architecture ) from library .
146 
 
147 
Elaborating entity  (architecture ) from library .
148 
 
149 
=========================================================================
150 
*                           HDL Synthesis                               *
151 
=========================================================================
152 
 
153 
Synthesizing Unit .
154 
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd".
155 
    Set property "syn_black_box = true" for instance .
156 
    Set property "syn_noprune = true" for instance .
157 
    Set property "optimize_primitives = false" for instance .
158 
    Set property "dont_touch = true" for instance .
159 
    Set property "MAX_FANOUT = REDUCE" for signal .
160 
    Set property "syn_keep = true" for signal .
161 
    Set property "KEEP = TRUE" for signal .
162 
WARNING:Xst:37 - Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored.
163 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
164 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
165 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
166 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
167 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
168 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
169 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
170 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
171 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
172 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
173 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
174 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
175 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
176 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
177 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
178 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
179 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
180 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
181 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
182 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
183 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
184 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
185 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
186 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
187 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
188 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
189 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
190 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
191 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
192 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
193 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
194 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
195 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
196 
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
197 
WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
198 
    Summary:
199 
        no macro.
200 
Unit  synthesized.
201 
 
202 
Synthesizing Unit .
203 
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd".
204 
    Set property "syn_noprune = true".
205 
    Set property "optimize_primitives = false".
206 
    Set property "dont_touch = true".
207 
INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 378: Output port  of the instance  is unconnected or connected to loadless signal.
208 
INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 378: Output port  of the instance  is unconnected or connected to loadless signal.
209 
    Summary:
210 
        no macro.
211 
Unit  synthesized.
212 
 
213 
Synthesizing Unit .
214 
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd".
215 
        period = 1
216 
        log_2_period = 1
217 
        pipeline_regs = 5
218 
        use_bufg = 0
219 
    Set property "MAX_FANOUT = REDUCE" for signal .
220 
    Set property "MAX_FANOUT = REDUCE" for signal .
221 
INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 254: Output port  of the instance  is unconnected or connected to loadless signal.
222 
    Summary:
223 
        no macro.
224 
Unit  synthesized.
225 
 
226 
Synthesizing Unit .
227 
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
228 
        width = 1
229 
        init_index = 0
230 
        init_value = "0000"
231 
        latency = 1
232 
    Summary:
233 
        no macro.
234 
Unit  synthesized.
235 
 
236 
Synthesizing Unit .
237 
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
238 
        width = 1
239 
        init_index = 0
240 
        init_value = "0000"
241 
    Set property "syn_black_box = true" for instance .
242 
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
243 
    Summary:
244 
        no macro.
245 
Unit  synthesized.
246 
 
247 
Synthesizing Unit .
248 
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
249 
    Summary:
250 
        no macro.
251 
Unit  synthesized.
252 
 
253 
Synthesizing Unit .
254 
    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
255 
WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
256 
WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
257 
WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
258 
    Summary:
259 
        no macro.
260 
Unit  synthesized.
261 
 
262 
=========================================================================
263 
HDL Synthesis Report
264 
 
265 
Found no macro
266 
=========================================================================
267 
 
268 
=========================================================================
269 
*                       Advanced HDL Synthesis                          *
270 
=========================================================================
271 
 
272 
Reading core .
273 
Loading core  for timing and area information for instance .
274 
 
275 
=========================================================================
276 
Advanced HDL Synthesis Report
277 
 
278 
Macro Statistics
279 
# Registers                                            : 1
280 
 Flip-Flops                                            : 1
281 
 
282 
=========================================================================
283 
 
284 
=========================================================================
285 
*                         Low Level Synthesis                           *
286 
=========================================================================
287 
WARNING:Xst:1989 - Unit : instances ,  of unit  are equivalent, second instance is removed
288 
 
289 
Optimizing unit  ...
290 
 
291 
Mapping all equations...
292 
Annotating constraints using XCF file 'inout_logic_cw.xcf'
293 
XCF parsing done.
294 
Building and optimizing final netlist ...
295 
Found area constraint ratio of 100 (+ 0) on block inout_logic_cw, actual ratio is 0.
296 
 
297 
Final Macro Processing ...
298 
 
299 
=========================================================================
300 
Final Register Report
301 
 
302 
Macro Statistics
303 
# Registers                                            : 1
304 
 Flip-Flops                                            : 1
305 
 
306 
=========================================================================
307 
 
308 
=========================================================================
309 
*                           Partition Report                            *
310 
=========================================================================
311 
 
312 
Partition Implementation Status
313 
-------------------------------
314 
 
315 
  No Partitions were found in this design.
316 
 
317 
-------------------------------
318 
 
319 
=========================================================================
320 
*                            Design Summary                             *
321 
=========================================================================
322 
 
323 
Top Level Output File Name         : inout_logic_cw.ngc
324 
 
325 
Primitive and Black Box Usage:
326 
------------------------------
327 
# BELS                             : 2
328 
#      GND                         : 1
329 
#      VCC                         : 1
330 
# FlipFlops/Latches                : 2
331 
#      FD                          : 1
332 
#      FDRE                        : 1
333 
# Others                           : 1
334 
#      TIMESPEC                    : 1
335 
 
336 
Device utilization summary:
337 
---------------------------
338 
 
339 
Selected Device : 6vlx240tff784-3
340 
 
341 
 
342 
Slice Logic Utilization:
343 
 Number of Slice Registers:               2  out of  301440     0%
344 
 
345 
Slice Logic Distribution:
346 
 Number of LUT Flip Flop pairs used:      2
347 
   Number with an unused Flip Flop:       0  out of      2     0%
348 
   Number with an unused LUT:             2  out of      2   100%
349 
   Number of fully used LUT-FF pairs:     0  out of      2     0%
350 
   Number of unique control sets:         2
351 
 
352 
IO Utilization:
353 
 Number of IOs:                        2838
354 
 Number of bonded IOBs:                   0  out of    400     0%
355 
 
356 
Specific Feature Utilization:
357 
 
358 
---------------------------
359 
Partition Resource Summary:
360 
---------------------------
361 
 
362 
  No Partitions were found in this design.
363 
 
364 
---------------------------
365 
 
366 
 
367 
=========================================================================
368 
Timing Report
369 
 
370 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
371 
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
372 
      GENERATED AFTER PLACE-and-ROUTE.
373 
 
374 
Clock Information:
375 
------------------
376 
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
377 
Clock Signal                       | Clock buffer(FF name)                                                                                                      | Load  |
378 
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
379 
to_register9_clk                   | NONE(default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp)| 2     |
380 
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
381 
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
382 
 
383 
Asynchronous Control Signals Information:
384 
----------------------------------------
385 
No asynchronous control signals found in this design
386 
 
387 
Timing Summary:
388 
---------------
389 
Speed Grade: -3
390 
 
391 
   Minimum period: 0.559ns (Maximum Frequency: 1787.949MHz)
392 
   Minimum input arrival time before clock: No path found
393 
   Maximum output required time after clock: No path found
394 
   Maximum combinational path delay: 0.000ns
395 
 
396 
=========================================================================
397 
Timing constraint: TS_clk_54e96cfd = PERIOD TIMEGRP "clk_54e96cfd" 5 nS HIGH 2.500 nS
398 
  Clock period: 0.559ns (frequency: 1787.949MHz)
399 
  Total number of paths / destination ports: 1 / 1
400 
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
401 
-------------------------------------------------------------------------
402 
Slack:                  4.441ns
403 
  Source:               persistentdff_inst/q (FF)
404 
  Destination:          persistentdff_inst/q (FF)
405 
  Data Path Delay:      0.559ns (Levels of Logic = 1)
406 
  Source Clock:         to_register9_clk rising at 0.000ns
407 
  Destination Clock:    to_register9_clk rising at 5.000ns
408 
 
409 
  Data Path: persistentdff_inst/q (FF) to persistentdff_inst/q (FF)
410 
                                Gate     Net
411 
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
412 
    ----------------------------------------  ------------
413 
     FD:C->Q               1   0.280   0.279  q (q)
414 
     end scope: 'persistentdff_inst'
415 
     begin scope: 'persistentdff_inst'
416 
     FD:D                     -0.012          q
417 
    ----------------------------------------
418 
    Total                      0.559ns (0.280ns logic, 0.279ns route)
419 
                                       (50.1% logic, 49.9% route)
420 
 
421 
=========================================================================
422 
 
423 
Cross Clock Domains Report:
424 
--------------------------
425 
 
426 
Clock to Setup on destination clock to_register9_clk
427 
----------------+---------+---------+---------+---------+
428 
                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
429 
Source Clock    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
430 
----------------+---------+---------+---------+---------+
431 
to_register9_clk|    0.559|         |         |         |
432 
----------------+---------+---------+---------+---------+
433 
 
434 
=========================================================================
435 
 
436 
 
437 
Total REAL time to Xst completion: 4.00 secs
438 
Total CPU time to Xst completion: 3.95 secs
439 
 
440 
-->
441 
 
442 
Total memory usage is 152756 kilobytes
443 
 
444 
Number of errors   :    0 (   0 filtered)
445 
Number of warnings :   77 (   0 filtered)
446 
Number of infos    :    4 (   0 filtered)
447 
 

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