OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [synth_model/] [synopsis] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0,
4 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
5 
    'Impl_file' => 'ISE Defaults',
6 
    'Impl_file_sgadvanced' => '',
7 
    'Synth_file' => 'XST Defaults',
8 
    'Synth_file_sgadvanced' => '',
9 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
10 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
11 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
12 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
13 
    'base_system_period_hardware' => 5,
14 
    'base_system_period_simulink' => '8e-009',
15 
    'block_icon_display' => 'Default',
16 
    'block_type' => 'sysgen',
17 
    'block_version' => '',
18 
    'ce_clr' => 0,
19 
    'clkWrapper' => 'inout_logic_cw',
20 
    'clkWrapperFile' => 'inout_logic_cw.vhd',
21 
    'clock_loc' => '',
22 
    'clock_wrapper' => 'Clock Enables',
23 
    'clock_wrapper_sgadvanced' => '',
24 
    'compilation' => 'NGC Netlist',
25 
    'compilation_lut' => {
26 
      'keys' => [
27 
        'HDL Netlist',
28 
        'Bitstream',
29 
        'NGC Netlist',
30 
      ],
31 
      'values' => [
32 
        'target1',
33 
        'target2',
34 
        'target3',
35 
      ],
36 
    },
37 
    'compilation_target' => 'NGC Netlist',
38 
    'core_generation' => 1,
39 
    'core_generation_sgadvanced' => '',
40 
    'core_is_deployed' => 0,
41 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c00613f6911dfdaa6',
42 
    'coregen_part_family' => 'virtex6',
43 
    'createTestbench' => 0,
44 
    'create_interface_document' => 'off',
45 
    'dbl_ovrd' => -1,
46 
    'dbl_ovrd_sgadvanced' => '',
47 
    'dcm_info' => {
48 
    },
49 
    'dcm_input_clock_period' => 5,
50 
    'deprecated_control' => 'off',
51 
    'deprecated_control_sgadvanced' => '',
52 
    'design' => 'inout_logic',
53 
    'designFile' => 'inout_logic.vhd',
54 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\pcie-v6-ml605_ISE12_OpenCores\\MySysGen\\PCIe_UserLogic_00.mdl',
55 
    'device' => 'xc6vlx240t-3ff784',
56 
    'device_speed' => -3,
57 
    'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
58 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
59 
    'entityNamingInstrs' => {
60 
      'nameMap' => undef,
61 
      'namesAlreadyUsed' => {
62 
        'default_clock_driver' => 1,
63 
        'inout_logic_cw' => 1,
64 
      },
65 
    },
66 
    'eval_field' => 0,
67 
    'fileAttributes' => {
68 
      'nonleaf_results.vhd' => {
69 
        'producer' => 'nonleafNetlister',
70 
      },
71 
    },
72 
    'files' => [
73 
      'xlpersistentdff.ngc',
74 
      'synopsis',
75 
      'inout_logic.vhd',
76 
      'xlpersistentdff.ngc',
77 
      'inout_logic_cw.vhd',
78 
      'inout_logic_cw.ucf',
79 
      'inout_logic_cw.xcf',
80 
      'inout_logic_cw.sdc',
81 
      'xst_inout_logic.prj',
82 
      'xst_inout_logic.scr',
83 
      'vcom.do',
84 
      'isim_inout_logic.prj',
85 
      'globals',
86 
      'hdlFiles',
87 
      'inout_logic_cw.xise',
88 
      'inout_logic_cw.gise',
89 
      'inout_logic_cw.sgp',
90 
    ],
91 
    'fxdptinstalled' => 1,
92 
    'generateUsing71FrontEnd' => 1,
93 
    'generating_island_subsystem_handle' => 4.0009765625,
94 
    'generating_subsystem_handle' => 4.0009765625,
95 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
96 
    'has_advanced_control' => 0,
97 
    'hdlDir' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl',
98 
    'hdlKind' => 'vhdl',
99 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
100 
    'impl_file' => 'ISE Defaults*',
101 
    'incr_netlist' => 'off',
102 
    'incr_netlist_sgadvanced' => '',
103 
    'infoedit' => ' System Generator',
104 
    'isCombinatorial' => 1,
105 
    'isdeployed' => 0,
106 
    'ise_version' => '12.3i',
107 
    'master_sysgen_token_handle' => 5.0009765625,
108 
    'matlab' => 'C:/Programmi/MATLAB/R2010a',
109 
    'matlab_fixedpoint' => 1,
110 
    'mdlHandle' => 3.0009765625,
111 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
112 
    'modelDiagnostics' => [
113 
      {
114 
        'count' => 339,
115 
        'isMask' => 0,
116 
        'type' => 'PCIe_UserLogic_00 Total blocks',
117 
      },
118 
      {
119 
        'count' => 4,
120 
        'isMask' => 0,
121 
        'type' => 'DiscretePulseGenerator',
122 
      },
123 
      {
124 
        'count' => 327,
125 
        'isMask' => 0,
126 
        'type' => 'S-Function',
127 
      },
128 
      {
129 
        'count' => 4,
130 
        'isMask' => 0,
131 
        'type' => 'SubSystem',
132 
      },
133 
      {
134 
        'count' => 4,
135 
        'isMask' => 0,
136 
        'type' => 'Terminator',
137 
      },
138 
      {
139 
        'count' => 23,
140 
        'isMask' => 1,
141 
        'type' => 'Xilinx Constant Block Block',
142 
      },
143 
      {
144 
        'count' => 1,
145 
        'isMask' => 1,
146 
        'type' => 'Xilinx Counter Block',
147 
      },
148 
      {
149 
        'count' => 44,
150 
        'isMask' => 1,
151 
        'type' => 'Xilinx Gateway In Block',
152 
      },
153 
      {
154 
        'count' => 39,
155 
        'isMask' => 1,
156 
        'type' => 'Xilinx Gateway Out Block',
157 
      },
158 
      {
159 
        'count' => 2,
160 
        'isMask' => 1,
161 
        'type' => 'Xilinx Inverter Block',
162 
      },
163 
      {
164 
        'count' => 1,
165 
        'isMask' => 1,
166 
        'type' => 'Xilinx Logical Block Block',
167 
      },
168 
      {
169 
        'count' => 78,
170 
        'isMask' => 1,
171 
        'type' => 'Xilinx Register Block',
172 
      },
173 
      {
174 
        'count' => 62,
175 
        'isMask' => 1,
176 
        'type' => 'Xilinx Shared Memory Based From Register Block',
177 
      },
178 
      {
179 
        'count' => 62,
180 
        'isMask' => 1,
181 
        'type' => 'Xilinx Shared Memory Based To Register Block',
182 
      },
183 
      {
184 
        'count' => 1,
185 
        'isMask' => 1,
186 
        'type' => 'Xilinx Subsystem Generator Block',
187 
      },
188 
      {
189 
        'count' => 2,
190 
        'isMask' => 1,
191 
        'type' => 'Xilinx System Generator Block',
192 
      },
193 
      {
194 
        'count' => 14,
195 
        'isMask' => 1,
196 
        'type' => 'Xilinx Type Converter Block',
197 
      },
198 
    ],
199 
    'model_globals_initialized' => 1,
200 
    'model_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
201 
    'myxilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
202 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
203 
    'ngc_config' => {
204 
      'include_cf' => 1,
205 
      'include_clockwrapper' => 1,
206 
    },
207 
    'ngc_files' => [
208 
      'xlpersistentdff.ngc',
209 
    ],
210 
    'num_sim_cycles' => 1250000000,
211 
    'package' => 'ff784',
212 
    'part' => 'xc6vlx240t',
213 
    'partFamily' => 'virtex6',
214 
    'port_data_types_enabled' => 1,
215 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
216 
    'preserve_hierarchy' => 0,
217 
    'proj_type' => 'Project Navigator',
218 
    'proj_type_sgadvanced' => '',
219 
    'run_coregen' => 'off',
220 
    'run_coregen_sgadvanced' => '',
221 
    'sample_time_colors_enabled' => 1,
222 
    'sampletimecolors' => 1,
223 
    'sdcFile' => 'inout_logic_cw.sdc',
224 
    'settings_fcn' => 'xlngcsettings',
225 
    'sg_blockgui_xml' => '',
226 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
227 
    'sg_list_contents' => '',
228 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
229 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
230 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
231 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
232 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
233 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
234 
fprintf(\'\',\'COMMENT: end icon graphics\');
235 
fprintf(\'\',\'COMMENT: begin icon text\');
236 
fprintf(\'\',\'COMMENT: end icon text\');',
237 
    'sg_version' => '',
238 
    'sggui_pos' => '-1,-1,-1,-1',
239 
    'simulation_island_subsystem_handle' => 4.0009765625,
240 
    'simulinkName' => 'parking_lot',
241 
    'simulink_accelerator_running' => 0,
242 
    'simulink_debugger_running' => 0,
243 
    'simulink_period' => '8e-009',
244 
    'speed' => -3,
245 
    'synth_file' => 'XST Defaults*',
246 
    'synthesisTool' => 'XST',
247 
    'synthesis_language' => 'vhdl',
248 
    'synthesis_tool' => 'XST',
249 
    'synthesis_tool_sgadvanced' => '',
250 
    'sysclk_period' => 5,
251 
    'sysgen' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
252 
    'sysgenRoot' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
253 
    'sysgenTokenSettings' => {
254 
      'Impl_file' => 'ISE Defaults',
255 
      'Impl_file_sgadvanced' => '',
256 
      'Synth_file' => 'XST Defaults',
257 
      'Synth_file_sgadvanced' => '',
258 
      'base_system_period_hardware' => 5,
259 
      'base_system_period_simulink' => '8e-009',
260 
      'block_icon_display' => 'Default',
261 
      'block_type' => 'sysgen',
262 
      'block_version' => '',
263 
      'ce_clr' => 0,
264 
      'clock_loc' => '',
265 
      'clock_wrapper' => 'Clock Enables',
266 
      'clock_wrapper_sgadvanced' => '',
267 
      'compilation' => 'NGC Netlist',
268 
      'compilation_lut' => {
269 
        'keys' => [
270 
          'HDL Netlist',
271 
          'Bitstream',
272 
          'NGC Netlist',
273 
        ],
274 
        'values' => [
275 
          'target1',
276 
          'target2',
277 
          'target3',
278 
        ],
279 
      },
280 
      'core_generation' => 1,
281 
      'core_generation_sgadvanced' => '',
282 
      'coregen_part_family' => 'virtex6',
283 
      'create_interface_document' => 'off',
284 
      'dbl_ovrd' => -1,
285 
      'dbl_ovrd_sgadvanced' => '',
286 
      'dcm_input_clock_period' => 5,
287 
      'deprecated_control' => 'off',
288 
      'deprecated_control_sgadvanced' => '',
289 
      'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
290 
      'eval_field' => 0,
291 
      'has_advanced_control' => 0,
292 
      'impl_file' => 'ISE Defaults*',
293 
      'incr_netlist' => 'off',
294 
      'incr_netlist_sgadvanced' => '',
295 
      'infoedit' => ' System Generator',
296 
      'master_sysgen_token_handle' => 5.0009765625,
297 
      'ngc_config' => {
298 
        'include_cf' => 1,
299 
        'include_clockwrapper' => 1,
300 
      },
301 
      'package' => 'ff784',
302 
      'part' => 'xc6vlx240t',
303 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
304 
      'preserve_hierarchy' => 0,
305 
      'proj_type' => 'Project Navigator',
306 
      'proj_type_sgadvanced' => '',
307 
      'run_coregen' => 'off',
308 
      'run_coregen_sgadvanced' => '',
309 
      'settings_fcn' => 'xlngcsettings',
310 
      'sg_blockgui_xml' => '',
311 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
312 
      'sg_list_contents' => '',
313 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
314 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
315 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
316 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
317 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
318 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
319 
fprintf(\'\',\'COMMENT: end icon graphics\');
320 
fprintf(\'\',\'COMMENT: begin icon text\');
321 
fprintf(\'\',\'COMMENT: end icon text\');',
322 
      'sggui_pos' => '-1,-1,-1,-1',
323 
      'simulation_island_subsystem_handle' => 4.0009765625,
324 
      'simulink_period' => '8e-009',
325 
      'speed' => -3,
326 
      'synth_file' => 'XST Defaults*',
327 
      'synthesis_language' => 'vhdl',
328 
      'synthesis_tool' => 'XST',
329 
      'synthesis_tool_sgadvanced' => '',
330 
      'sysclk_period' => 5,
331 
      'testbench' => 0,
332 
      'testbench_sgadvanced' => '',
333 
      'trim_vbits' => 1,
334 
      'trim_vbits_sgadvanced' => '',
335 
      'xilinx_device' => 'xc6vlx240t-3ff784',
336 
      'xilinxfamily' => 'virtex6',
337 
    },
338 
    'sysgen_Root' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
339 
    'systemClockPeriod' => 5,
340 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
341 
    'testbench' => 0,
342 
    'testbench_sgadvanced' => '',
343 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/sysgen',
344 
    'trim_vbits' => 1,
345 
    'trim_vbits_sgadvanced' => '',
346 
    'ucfFile' => 'inout_logic_cw.ucf',
347 
    'use_ce_syn_keep' => 1,
348 
    'use_strict_names' => 1,
349 
    'user_tips_enabled' => 0,
350 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
351 
    'using71Netlister' => 1,
352 
    'verilog_files' => [
353 
      'conv_pkg.v',
354 
      'synth_reg.v',
355 
      'synth_reg_w_init.v',
356 
      'convert_type.v',
357 
    ],
358 
    'version' => '',
359 
    'vhdl_files' => [
360 
      'conv_pkg.vhd',
361 
      'synth_reg.vhd',
362 
      'synth_reg_w_init.vhd',
363 
    ],
364 
    'vsimtime' => '6875000275.000000 ns',
365 
    'xcfFile' => 'inout_logic_cw.xcf',
366 
    'xilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
367 
    'xilinx_device' => 'xc6vlx240t-3ff784',
368 
    'xilinx_family' => 'virtex6',
369 
    'xilinx_package' => 'ff784',
370 
    'xilinx_part' => 'xc6vlx240t',
371 
    'xilinxdevice' => 'xc6vlx240t-3ff784',
372 
    'xilinxfamily' => 'virtex6',
373 
    'xilinxpart' => 'xc6vlx240t',
374 
  },
375 
  'entityName' => '',
376 
  'nets' => {
377 
    '.clk' => {
378 
      'hdlType' => 'std_logic',
379 
      'width' => 1,
380 
    },
381 
    '.debug_in_1i' => {
382 
      'hdlType' => 'std_logic_vector(31 downto 0)',
383 
      'width' => 32,
384 
    },
385 
    '.debug_in_2i' => {
386 
      'hdlType' => 'std_logic_vector(31 downto 0)',
387 
      'width' => 32,
388 
    },
389 
    '.debug_in_3i' => {
390 
      'hdlType' => 'std_logic_vector(31 downto 0)',
391 
      'width' => 32,
392 
    },
393 
    '.debug_in_4i' => {
394 
      'hdlType' => 'std_logic_vector(31 downto 0)',
395 
      'width' => 32,
396 
    },
397 
    '.dma_host2board_busy' => {
398 
      'hdlType' => 'std_logic',
399 
      'width' => 1,
400 
    },
401 
    '.dma_host2board_done' => {
402 
      'hdlType' => 'std_logic',
403 
      'width' => 1,
404 
    },
405 
    '.reg01_td' => {
406 
      'hdlType' => 'std_logic_vector(31 downto 0)',
407 
      'width' => 32,
408 
    },
409 
    '.reg01_tv' => {
410 
      'hdlType' => 'std_logic',
411 
      'width' => 1,
412 
    },
413 
    '.reg02_td' => {
414 
      'hdlType' => 'std_logic_vector(31 downto 0)',
415 
      'width' => 32,
416 
    },
417 
    '.reg02_tv' => {
418 
      'hdlType' => 'std_logic',
419 
      'width' => 1,
420 
    },
421 
    '.reg03_td' => {
422 
      'hdlType' => 'std_logic_vector(31 downto 0)',
423 
      'width' => 32,
424 
    },
425 
    '.reg03_tv' => {
426 
      'hdlType' => 'std_logic',
427 
      'width' => 1,
428 
    },
429 
    '.reg04_td' => {
430 
      'hdlType' => 'std_logic_vector(31 downto 0)',
431 
      'width' => 32,
432 
    },
433 
    '.reg04_tv' => {
434 
      'hdlType' => 'std_logic',
435 
      'width' => 1,
436 
    },
437 
    '.reg05_td' => {
438 
      'hdlType' => 'std_logic_vector(31 downto 0)',
439 
      'width' => 32,
440 
    },
441 
    '.reg05_tv' => {
442 
      'hdlType' => 'std_logic',
443 
      'width' => 1,
444 
    },
445 
    '.reg06_td' => {
446 
      'hdlType' => 'std_logic_vector(31 downto 0)',
447 
      'width' => 32,
448 
    },
449 
    '.reg06_tv' => {
450 
      'hdlType' => 'std_logic',
451 
      'width' => 1,
452 
    },
453 
    '.reg07_td' => {
454 
      'hdlType' => 'std_logic_vector(31 downto 0)',
455 
      'width' => 32,
456 
    },
457 
    '.reg07_tv' => {
458 
      'hdlType' => 'std_logic',
459 
      'width' => 1,
460 
    },
461 
    '.reg08_td' => {
462 
      'hdlType' => 'std_logic_vector(31 downto 0)',
463 
      'width' => 32,
464 
    },
465 
    '.reg08_tv' => {
466 
      'hdlType' => 'std_logic',
467 
      'width' => 1,
468 
    },
469 
    '.reg09_td' => {
470 
      'hdlType' => 'std_logic_vector(31 downto 0)',
471 
      'width' => 32,
472 
    },
473 
    '.reg09_tv' => {
474 
      'hdlType' => 'std_logic',
475 
      'width' => 1,
476 
    },
477 
    '.reg10_td' => {
478 
      'hdlType' => 'std_logic_vector(31 downto 0)',
479 
      'width' => 32,
480 
    },
481 
    '.reg10_tv' => {
482 
      'hdlType' => 'std_logic',
483 
      'width' => 1,
484 
    },
485 
    '.reg11_td' => {
486 
      'hdlType' => 'std_logic_vector(31 downto 0)',
487 
      'width' => 32,
488 
    },
489 
    '.reg11_tv' => {
490 
      'hdlType' => 'std_logic',
491 
      'width' => 1,
492 
    },
493 
    '.reg12_td' => {
494 
      'hdlType' => 'std_logic_vector(31 downto 0)',
495 
      'width' => 32,
496 
    },
497 
    '.reg12_tv' => {
498 
      'hdlType' => 'std_logic',
499 
      'width' => 1,
500 
    },
501 
    '.reg13_td' => {
502 
      'hdlType' => 'std_logic_vector(31 downto 0)',
503 
      'width' => 32,
504 
    },
505 
    '.reg13_tv' => {
506 
      'hdlType' => 'std_logic',
507 
      'width' => 1,
508 
    },
509 
    '.reg14_td' => {
510 
      'hdlType' => 'std_logic_vector(31 downto 0)',
511 
      'width' => 32,
512 
    },
513 
    '.reg14_tv' => {
514 
      'hdlType' => 'std_logic',
515 
      'width' => 1,
516 
    },
517 
    'from_register1.data_out' => {
518 
      'hdlType' => 'std_logic',
519 
      'width' => 1,
520 
    },
521 
    'from_register10.data_out' => {
522 
      'hdlType' => 'std_logic_vector(31 downto 0)',
523 
      'width' => 32,
524 
    },
525 
    'from_register11.data_out' => {
526 
      'hdlType' => 'std_logic_vector(31 downto 0)',
527 
      'width' => 32,
528 
    },
529 
    'from_register12.data_out' => {
530 
      'hdlType' => 'std_logic',
531 
      'width' => 1,
532 
    },
533 
    'from_register13.data_out' => {
534 
      'hdlType' => 'std_logic_vector(31 downto 0)',
535 
      'width' => 32,
536 
    },
537 
    'from_register14.data_out' => {
538 
      'hdlType' => 'std_logic',
539 
      'width' => 1,
540 
    },
541 
    'from_register15.data_out' => {
542 
      'hdlType' => 'std_logic_vector(31 downto 0)',
543 
      'width' => 32,
544 
    },
545 
    'from_register16.data_out' => {
546 
      'hdlType' => 'std_logic',
547 
      'width' => 1,
548 
    },
549 
    'from_register17.data_out' => {
550 
      'hdlType' => 'std_logic_vector(31 downto 0)',
551 
      'width' => 32,
552 
    },
553 
    'from_register18.data_out' => {
554 
      'hdlType' => 'std_logic',
555 
      'width' => 1,
556 
    },
557 
    'from_register19.data_out' => {
558 
      'hdlType' => 'std_logic_vector(31 downto 0)',
559 
      'width' => 32,
560 
    },
561 
    'from_register2.data_out' => {
562 
      'hdlType' => 'std_logic',
563 
      'width' => 1,
564 
    },
565 
    'from_register20.data_out' => {
566 
      'hdlType' => 'std_logic',
567 
      'width' => 1,
568 
    },
569 
    'from_register21.data_out' => {
570 
      'hdlType' => 'std_logic_vector(31 downto 0)',
571 
      'width' => 32,
572 
    },
573 
    'from_register22.data_out' => {
574 
      'hdlType' => 'std_logic',
575 
      'width' => 1,
576 
    },
577 
    'from_register23.data_out' => {
578 
      'hdlType' => 'std_logic_vector(31 downto 0)',
579 
      'width' => 32,
580 
    },
581 
    'from_register24.data_out' => {
582 
      'hdlType' => 'std_logic',
583 
      'width' => 1,
584 
    },
585 
    'from_register25.data_out' => {
586 
      'hdlType' => 'std_logic_vector(31 downto 0)',
587 
      'width' => 32,
588 
    },
589 
    'from_register26.data_out' => {
590 
      'hdlType' => 'std_logic',
591 
      'width' => 1,
592 
    },
593 
    'from_register27.data_out' => {
594 
      'hdlType' => 'std_logic_vector(31 downto 0)',
595 
      'width' => 32,
596 
    },
597 
    'from_register28.data_out' => {
598 
      'hdlType' => 'std_logic',
599 
      'width' => 1,
600 
    },
601 
    'from_register3.data_out' => {
602 
      'hdlType' => 'std_logic_vector(31 downto 0)',
603 
      'width' => 32,
604 
    },
605 
    'from_register4.data_out' => {
606 
      'hdlType' => 'std_logic',
607 
      'width' => 1,
608 
    },
609 
    'from_register5.data_out' => {
610 
      'hdlType' => 'std_logic_vector(31 downto 0)',
611 
      'width' => 32,
612 
    },
613 
    'from_register6.data_out' => {
614 
      'hdlType' => 'std_logic',
615 
      'width' => 1,
616 
    },
617 
    'from_register7.data_out' => {
618 
      'hdlType' => 'std_logic_vector(31 downto 0)',
619 
      'width' => 32,
620 
    },
621 
    'from_register8.data_out' => {
622 
      'hdlType' => 'std_logic_vector(31 downto 0)',
623 
      'width' => 32,
624 
    },
625 
    'from_register9.data_out' => {
626 
      'hdlType' => 'std_logic',
627 
      'width' => 1,
628 
    },
629 
    'sysgen_dut.reg01_rd' => {
630 
      'hdlType' => 'std_logic_vector(31 downto 0)',
631 
      'width' => 32,
632 
    },
633 
    'sysgen_dut.reg01_rv' => {
634 
      'hdlType' => 'std_logic',
635 
      'width' => 1,
636 
    },
637 
    'sysgen_dut.reg02_rd' => {
638 
      'hdlType' => 'std_logic_vector(31 downto 0)',
639 
      'width' => 32,
640 
    },
641 
    'sysgen_dut.reg02_rv' => {
642 
      'hdlType' => 'std_logic',
643 
      'width' => 1,
644 
    },
645 
    'sysgen_dut.reg03_rd' => {
646 
      'hdlType' => 'std_logic_vector(31 downto 0)',
647 
      'width' => 32,
648 
    },
649 
    'sysgen_dut.reg03_rv' => {
650 
      'hdlType' => 'std_logic',
651 
      'width' => 1,
652 
    },
653 
    'sysgen_dut.reg04_rd' => {
654 
      'hdlType' => 'std_logic_vector(31 downto 0)',
655 
      'width' => 32,
656 
    },
657 
    'sysgen_dut.reg04_rv' => {
658 
      'hdlType' => 'std_logic',
659 
      'width' => 1,
660 
    },
661 
    'sysgen_dut.reg05_rd' => {
662 
      'hdlType' => 'std_logic_vector(31 downto 0)',
663 
      'width' => 32,
664 
    },
665 
    'sysgen_dut.reg05_rv' => {
666 
      'hdlType' => 'std_logic',
667 
      'width' => 1,
668 
    },
669 
    'sysgen_dut.reg06_rd' => {
670 
      'hdlType' => 'std_logic_vector(31 downto 0)',
671 
      'width' => 32,
672 
    },
673 
    'sysgen_dut.reg06_rv' => {
674 
      'hdlType' => 'std_logic',
675 
      'width' => 1,
676 
    },
677 
    'sysgen_dut.reg07_rd' => {
678 
      'hdlType' => 'std_logic_vector(31 downto 0)',
679 
      'width' => 32,
680 
    },
681 
    'sysgen_dut.reg07_rv' => {
682 
      'hdlType' => 'std_logic',
683 
      'width' => 1,
684 
    },
685 
    'sysgen_dut.reg08_rd' => {
686 
      'hdlType' => 'std_logic_vector(31 downto 0)',
687 
      'width' => 32,
688 
    },
689 
    'sysgen_dut.reg08_rv' => {
690 
      'hdlType' => 'std_logic',
691 
      'width' => 1,
692 
    },
693 
    'sysgen_dut.reg09_rd' => {
694 
      'hdlType' => 'std_logic_vector(31 downto 0)',
695 
      'width' => 32,
696 
    },
697 
    'sysgen_dut.reg09_rv' => {
698 
      'hdlType' => 'std_logic',
699 
      'width' => 1,
700 
    },
701 
    'sysgen_dut.reg10_rd' => {
702 
      'hdlType' => 'std_logic_vector(31 downto 0)',
703 
      'width' => 32,
704 
    },
705 
    'sysgen_dut.reg10_rv' => {
706 
      'hdlType' => 'std_logic',
707 
      'width' => 1,
708 
    },
709 
    'sysgen_dut.reg11_rd' => {
710 
      'hdlType' => 'std_logic_vector(31 downto 0)',
711 
      'width' => 32,
712 
    },
713 
    'sysgen_dut.reg11_rv' => {
714 
      'hdlType' => 'std_logic',
715 
      'width' => 1,
716 
    },
717 
    'sysgen_dut.reg12_rd' => {
718 
      'hdlType' => 'std_logic_vector(31 downto 0)',
719 
      'width' => 32,
720 
    },
721 
    'sysgen_dut.reg12_rv' => {
722 
      'hdlType' => 'std_logic',
723 
      'width' => 1,
724 
    },
725 
    'sysgen_dut.reg13_rd' => {
726 
      'hdlType' => 'std_logic_vector(31 downto 0)',
727 
      'width' => 32,
728 
    },
729 
    'sysgen_dut.reg13_rv' => {
730 
      'hdlType' => 'std_logic',
731 
      'width' => 1,
732 
    },
733 
    'sysgen_dut.reg14_rd' => {
734 
      'hdlType' => 'std_logic_vector(31 downto 0)',
735 
      'width' => 32,
736 
    },
737 
    'sysgen_dut.reg14_rv' => {
738 
      'hdlType' => 'std_logic',
739 
      'width' => 1,
740 
    },
741 
    'sysgen_dut.to_register10_ce' => {
742 
      'hdlType' => 'std_logic',
743 
      'width' => 1,
744 
    },
745 
    'sysgen_dut.to_register10_clk' => {
746 
      'hdlType' => 'std_logic',
747 
      'width' => 1,
748 
    },
749 
    'sysgen_dut.to_register10_clr' => {
750 
      'hdlType' => 'std_logic',
751 
      'width' => 1,
752 
    },
753 
    'sysgen_dut.to_register10_data_in' => {
754 
      'hdlType' => 'std_logic',
755 
      'width' => 1,
756 
    },
757 
    'sysgen_dut.to_register10_en' => {
758 
      'hdlType' => 'std_logic',
759 
      'width' => 1,
760 
    },
761 
    'sysgen_dut.to_register11_ce' => {
762 
      'hdlType' => 'std_logic',
763 
      'width' => 1,
764 
    },
765 
    'sysgen_dut.to_register11_clk' => {
766 
      'hdlType' => 'std_logic',
767 
      'width' => 1,
768 
    },
769 
    'sysgen_dut.to_register11_clr' => {
770 
      'hdlType' => 'std_logic',
771 
      'width' => 1,
772 
    },
773 
    'sysgen_dut.to_register11_data_in' => {
774 
      'hdlType' => 'std_logic_vector(31 downto 0)',
775 
      'width' => 32,
776 
    },
777 
    'sysgen_dut.to_register11_en' => {
778 
      'hdlType' => 'std_logic',
779 
      'width' => 1,
780 
    },
781 
    'sysgen_dut.to_register12_ce' => {
782 
      'hdlType' => 'std_logic',
783 
      'width' => 1,
784 
    },
785 
    'sysgen_dut.to_register12_clk' => {
786 
      'hdlType' => 'std_logic',
787 
      'width' => 1,
788 
    },
789 
    'sysgen_dut.to_register12_clr' => {
790 
      'hdlType' => 'std_logic',
791 
      'width' => 1,
792 
    },
793 
    'sysgen_dut.to_register12_data_in' => {
794 
      'hdlType' => 'std_logic',
795 
      'width' => 1,
796 
    },
797 
    'sysgen_dut.to_register12_en' => {
798 
      'hdlType' => 'std_logic',
799 
      'width' => 1,
800 
    },
801 
    'sysgen_dut.to_register13_ce' => {
802 
      'hdlType' => 'std_logic',
803 
      'width' => 1,
804 
    },
805 
    'sysgen_dut.to_register13_clk' => {
806 
      'hdlType' => 'std_logic',
807 
      'width' => 1,
808 
    },
809 
    'sysgen_dut.to_register13_clr' => {
810 
      'hdlType' => 'std_logic',
811 
      'width' => 1,
812 
    },
813 
    'sysgen_dut.to_register13_data_in' => {
814 
      'hdlType' => 'std_logic_vector(31 downto 0)',
815 
      'width' => 32,
816 
    },
817 
    'sysgen_dut.to_register13_en' => {
818 
      'hdlType' => 'std_logic',
819 
      'width' => 1,
820 
    },
821 
    'sysgen_dut.to_register14_ce' => {
822 
      'hdlType' => 'std_logic',
823 
      'width' => 1,
824 
    },
825 
    'sysgen_dut.to_register14_clk' => {
826 
      'hdlType' => 'std_logic',
827 
      'width' => 1,
828 
    },
829 
    'sysgen_dut.to_register14_clr' => {
830 
      'hdlType' => 'std_logic',
831 
      'width' => 1,
832 
    },
833 
    'sysgen_dut.to_register14_data_in' => {
834 
      'hdlType' => 'std_logic',
835 
      'width' => 1,
836 
    },
837 
    'sysgen_dut.to_register14_en' => {
838 
      'hdlType' => 'std_logic',
839 
      'width' => 1,
840 
    },
841 
    'sysgen_dut.to_register15_ce' => {
842 
      'hdlType' => 'std_logic',
843 
      'width' => 1,
844 
    },
845 
    'sysgen_dut.to_register15_clk' => {
846 
      'hdlType' => 'std_logic',
847 
      'width' => 1,
848 
    },
849 
    'sysgen_dut.to_register15_clr' => {
850 
      'hdlType' => 'std_logic',
851 
      'width' => 1,
852 
    },
853 
    'sysgen_dut.to_register15_data_in' => {
854 
      'hdlType' => 'std_logic_vector(31 downto 0)',
855 
      'width' => 32,
856 
    },
857 
    'sysgen_dut.to_register15_en' => {
858 
      'hdlType' => 'std_logic',
859 
      'width' => 1,
860 
    },
861 
    'sysgen_dut.to_register16_ce' => {
862 
      'hdlType' => 'std_logic',
863 
      'width' => 1,
864 
    },
865 
    'sysgen_dut.to_register16_clk' => {
866 
      'hdlType' => 'std_logic',
867 
      'width' => 1,
868 
    },
869 
    'sysgen_dut.to_register16_clr' => {
870 
      'hdlType' => 'std_logic',
871 
      'width' => 1,
872 
    },
873 
    'sysgen_dut.to_register16_data_in' => {
874 
      'hdlType' => 'std_logic',
875 
      'width' => 1,
876 
    },
877 
    'sysgen_dut.to_register16_en' => {
878 
      'hdlType' => 'std_logic',
879 
      'width' => 1,
880 
    },
881 
    'sysgen_dut.to_register17_ce' => {
882 
      'hdlType' => 'std_logic',
883 
      'width' => 1,
884 
    },
885 
    'sysgen_dut.to_register17_clk' => {
886 
      'hdlType' => 'std_logic',
887 
      'width' => 1,
888 
    },
889 
    'sysgen_dut.to_register17_clr' => {
890 
      'hdlType' => 'std_logic',
891 
      'width' => 1,
892 
    },
893 
    'sysgen_dut.to_register17_data_in' => {
894 
      'hdlType' => 'std_logic_vector(31 downto 0)',
895 
      'width' => 32,
896 
    },
897 
    'sysgen_dut.to_register17_en' => {
898 
      'hdlType' => 'std_logic',
899 
      'width' => 1,
900 
    },
901 
    'sysgen_dut.to_register18_ce' => {
902 
      'hdlType' => 'std_logic',
903 
      'width' => 1,
904 
    },
905 
    'sysgen_dut.to_register18_clk' => {
906 
      'hdlType' => 'std_logic',
907 
      'width' => 1,
908 
    },
909 
    'sysgen_dut.to_register18_clr' => {
910 
      'hdlType' => 'std_logic',
911 
      'width' => 1,
912 
    },
913 
    'sysgen_dut.to_register18_data_in' => {
914 
      'hdlType' => 'std_logic',
915 
      'width' => 1,
916 
    },
917 
    'sysgen_dut.to_register18_en' => {
918 
      'hdlType' => 'std_logic',
919 
      'width' => 1,
920 
    },
921 
    'sysgen_dut.to_register19_ce' => {
922 
      'hdlType' => 'std_logic',
923 
      'width' => 1,
924 
    },
925 
    'sysgen_dut.to_register19_clk' => {
926 
      'hdlType' => 'std_logic',
927 
      'width' => 1,
928 
    },
929 
    'sysgen_dut.to_register19_clr' => {
930 
      'hdlType' => 'std_logic',
931 
      'width' => 1,
932 
    },
933 
    'sysgen_dut.to_register19_data_in' => {
934 
      'hdlType' => 'std_logic',
935 
      'width' => 1,
936 
    },
937 
    'sysgen_dut.to_register19_en' => {
938 
      'hdlType' => 'std_logic',
939 
      'width' => 1,
940 
    },
941 
    'sysgen_dut.to_register1_ce' => {
942 
      'hdlType' => 'std_logic',
943 
      'width' => 1,
944 
    },
945 
    'sysgen_dut.to_register1_clk' => {
946 
      'hdlType' => 'std_logic',
947 
      'width' => 1,
948 
    },
949 
    'sysgen_dut.to_register1_clr' => {
950 
      'hdlType' => 'std_logic',
951 
      'width' => 1,
952 
    },
953 
    'sysgen_dut.to_register1_data_in' => {
954 
      'hdlType' => 'std_logic_vector(31 downto 0)',
955 
      'width' => 32,
956 
    },
957 
    'sysgen_dut.to_register1_en' => {
958 
      'hdlType' => 'std_logic',
959 
      'width' => 1,
960 
    },
961 
    'sysgen_dut.to_register20_ce' => {
962 
      'hdlType' => 'std_logic',
963 
      'width' => 1,
964 
    },
965 
    'sysgen_dut.to_register20_clk' => {
966 
      'hdlType' => 'std_logic',
967 
      'width' => 1,
968 
    },
969 
    'sysgen_dut.to_register20_clr' => {
970 
      'hdlType' => 'std_logic',
971 
      'width' => 1,
972 
    },
973 
    'sysgen_dut.to_register20_data_in' => {
974 
      'hdlType' => 'std_logic_vector(31 downto 0)',
975 
      'width' => 32,
976 
    },
977 
    'sysgen_dut.to_register20_en' => {
978 
      'hdlType' => 'std_logic',
979 
      'width' => 1,
980 
    },
981 
    'sysgen_dut.to_register21_ce' => {
982 
      'hdlType' => 'std_logic',
983 
      'width' => 1,
984 
    },
985 
    'sysgen_dut.to_register21_clk' => {
986 
      'hdlType' => 'std_logic',
987 
      'width' => 1,
988 
    },
989 
    'sysgen_dut.to_register21_clr' => {
990 
      'hdlType' => 'std_logic',
991 
      'width' => 1,
992 
    },
993 
    'sysgen_dut.to_register21_data_in' => {
994 
      'hdlType' => 'std_logic',
995 
      'width' => 1,
996 
    },
997 
    'sysgen_dut.to_register21_en' => {
998 
      'hdlType' => 'std_logic',
999 
      'width' => 1,
1000 
    },
1001 
    'sysgen_dut.to_register22_ce' => {
1002 
      'hdlType' => 'std_logic',
1003 
      'width' => 1,
1004 
    },
1005 
    'sysgen_dut.to_register22_clk' => {
1006 
      'hdlType' => 'std_logic',
1007 
      'width' => 1,
1008 
    },
1009 
    'sysgen_dut.to_register22_clr' => {
1010 
      'hdlType' => 'std_logic',
1011 
      'width' => 1,
1012 
    },
1013 
    'sysgen_dut.to_register22_data_in' => {
1014 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1015 
      'width' => 32,
1016 
    },
1017 
    'sysgen_dut.to_register22_en' => {
1018 
      'hdlType' => 'std_logic',
1019 
      'width' => 1,
1020 
    },
1021 
    'sysgen_dut.to_register23_ce' => {
1022 
      'hdlType' => 'std_logic',
1023 
      'width' => 1,
1024 
    },
1025 
    'sysgen_dut.to_register23_clk' => {
1026 
      'hdlType' => 'std_logic',
1027 
      'width' => 1,
1028 
    },
1029 
    'sysgen_dut.to_register23_clr' => {
1030 
      'hdlType' => 'std_logic',
1031 
      'width' => 1,
1032 
    },
1033 
    'sysgen_dut.to_register23_data_in' => {
1034 
      'hdlType' => 'std_logic',
1035 
      'width' => 1,
1036 
    },
1037 
    'sysgen_dut.to_register23_en' => {
1038 
      'hdlType' => 'std_logic',
1039 
      'width' => 1,
1040 
    },
1041 
    'sysgen_dut.to_register24_ce' => {
1042 
      'hdlType' => 'std_logic',
1043 
      'width' => 1,
1044 
    },
1045 
    'sysgen_dut.to_register24_clk' => {
1046 
      'hdlType' => 'std_logic',
1047 
      'width' => 1,
1048 
    },
1049 
    'sysgen_dut.to_register24_clr' => {
1050 
      'hdlType' => 'std_logic',
1051 
      'width' => 1,
1052 
    },
1053 
    'sysgen_dut.to_register24_data_in' => {
1054 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1055 
      'width' => 32,
1056 
    },
1057 
    'sysgen_dut.to_register24_en' => {
1058 
      'hdlType' => 'std_logic',
1059 
      'width' => 1,
1060 
    },
1061 
    'sysgen_dut.to_register25_ce' => {
1062 
      'hdlType' => 'std_logic',
1063 
      'width' => 1,
1064 
    },
1065 
    'sysgen_dut.to_register25_clk' => {
1066 
      'hdlType' => 'std_logic',
1067 
      'width' => 1,
1068 
    },
1069 
    'sysgen_dut.to_register25_clr' => {
1070 
      'hdlType' => 'std_logic',
1071 
      'width' => 1,
1072 
    },
1073 
    'sysgen_dut.to_register25_data_in' => {
1074 
      'hdlType' => 'std_logic',
1075 
      'width' => 1,
1076 
    },
1077 
    'sysgen_dut.to_register25_en' => {
1078 
      'hdlType' => 'std_logic',
1079 
      'width' => 1,
1080 
    },
1081 
    'sysgen_dut.to_register26_ce' => {
1082 
      'hdlType' => 'std_logic',
1083 
      'width' => 1,
1084 
    },
1085 
    'sysgen_dut.to_register26_clk' => {
1086 
      'hdlType' => 'std_logic',
1087 
      'width' => 1,
1088 
    },
1089 
    'sysgen_dut.to_register26_clr' => {
1090 
      'hdlType' => 'std_logic',
1091 
      'width' => 1,
1092 
    },
1093 
    'sysgen_dut.to_register26_data_in' => {
1094 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1095 
      'width' => 32,
1096 
    },
1097 
    'sysgen_dut.to_register26_en' => {
1098 
      'hdlType' => 'std_logic',
1099 
      'width' => 1,
1100 
    },
1101 
    'sysgen_dut.to_register27_ce' => {
1102 
      'hdlType' => 'std_logic',
1103 
      'width' => 1,
1104 
    },
1105 
    'sysgen_dut.to_register27_clk' => {
1106 
      'hdlType' => 'std_logic',
1107 
      'width' => 1,
1108 
    },
1109 
    'sysgen_dut.to_register27_clr' => {
1110 
      'hdlType' => 'std_logic',
1111 
      'width' => 1,
1112 
    },
1113 
    'sysgen_dut.to_register27_data_in' => {
1114 
      'hdlType' => 'std_logic',
1115 
      'width' => 1,
1116 
    },
1117 
    'sysgen_dut.to_register27_en' => {
1118 
      'hdlType' => 'std_logic',
1119 
      'width' => 1,
1120 
    },
1121 
    'sysgen_dut.to_register28_ce' => {
1122 
      'hdlType' => 'std_logic',
1123 
      'width' => 1,
1124 
    },
1125 
    'sysgen_dut.to_register28_clk' => {
1126 
      'hdlType' => 'std_logic',
1127 
      'width' => 1,
1128 
    },
1129 
    'sysgen_dut.to_register28_clr' => {
1130 
      'hdlType' => 'std_logic',
1131 
      'width' => 1,
1132 
    },
1133 
    'sysgen_dut.to_register28_data_in' => {
1134 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1135 
      'width' => 32,
1136 
    },
1137 
    'sysgen_dut.to_register28_en' => {
1138 
      'hdlType' => 'std_logic',
1139 
      'width' => 1,
1140 
    },
1141 
    'sysgen_dut.to_register29_ce' => {
1142 
      'hdlType' => 'std_logic',
1143 
      'width' => 1,
1144 
    },
1145 
    'sysgen_dut.to_register29_clk' => {
1146 
      'hdlType' => 'std_logic',
1147 
      'width' => 1,
1148 
    },
1149 
    'sysgen_dut.to_register29_clr' => {
1150 
      'hdlType' => 'std_logic',
1151 
      'width' => 1,
1152 
    },
1153 
    'sysgen_dut.to_register29_data_in' => {
1154 
      'hdlType' => 'std_logic',
1155 
      'width' => 1,
1156 
    },
1157 
    'sysgen_dut.to_register29_en' => {
1158 
      'hdlType' => 'std_logic',
1159 
      'width' => 1,
1160 
    },
1161 
    'sysgen_dut.to_register2_ce' => {
1162 
      'hdlType' => 'std_logic',
1163 
      'width' => 1,
1164 
    },
1165 
    'sysgen_dut.to_register2_clk' => {
1166 
      'hdlType' => 'std_logic',
1167 
      'width' => 1,
1168 
    },
1169 
    'sysgen_dut.to_register2_clr' => {
1170 
      'hdlType' => 'std_logic',
1171 
      'width' => 1,
1172 
    },
1173 
    'sysgen_dut.to_register2_data_in' => {
1174 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1175 
      'width' => 32,
1176 
    },
1177 
    'sysgen_dut.to_register2_en' => {
1178 
      'hdlType' => 'std_logic',
1179 
      'width' => 1,
1180 
    },
1181 
    'sysgen_dut.to_register30_ce' => {
1182 
      'hdlType' => 'std_logic',
1183 
      'width' => 1,
1184 
    },
1185 
    'sysgen_dut.to_register30_clk' => {
1186 
      'hdlType' => 'std_logic',
1187 
      'width' => 1,
1188 
    },
1189 
    'sysgen_dut.to_register30_clr' => {
1190 
      'hdlType' => 'std_logic',
1191 
      'width' => 1,
1192 
    },
1193 
    'sysgen_dut.to_register30_data_in' => {
1194 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1195 
      'width' => 32,
1196 
    },
1197 
    'sysgen_dut.to_register30_en' => {
1198 
      'hdlType' => 'std_logic',
1199 
      'width' => 1,
1200 
    },
1201 
    'sysgen_dut.to_register31_ce' => {
1202 
      'hdlType' => 'std_logic',
1203 
      'width' => 1,
1204 
    },
1205 
    'sysgen_dut.to_register31_clk' => {
1206 
      'hdlType' => 'std_logic',
1207 
      'width' => 1,
1208 
    },
1209 
    'sysgen_dut.to_register31_clr' => {
1210 
      'hdlType' => 'std_logic',
1211 
      'width' => 1,
1212 
    },
1213 
    'sysgen_dut.to_register31_data_in' => {
1214 
      'hdlType' => 'std_logic',
1215 
      'width' => 1,
1216 
    },
1217 
    'sysgen_dut.to_register31_en' => {
1218 
      'hdlType' => 'std_logic',
1219 
      'width' => 1,
1220 
    },
1221 
    'sysgen_dut.to_register32_ce' => {
1222 
      'hdlType' => 'std_logic',
1223 
      'width' => 1,
1224 
    },
1225 
    'sysgen_dut.to_register32_clk' => {
1226 
      'hdlType' => 'std_logic',
1227 
      'width' => 1,
1228 
    },
1229 
    'sysgen_dut.to_register32_clr' => {
1230 
      'hdlType' => 'std_logic',
1231 
      'width' => 1,
1232 
    },
1233 
    'sysgen_dut.to_register32_data_in' => {
1234 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1235 
      'width' => 32,
1236 
    },
1237 
    'sysgen_dut.to_register32_en' => {
1238 
      'hdlType' => 'std_logic',
1239 
      'width' => 1,
1240 
    },
1241 
    'sysgen_dut.to_register33_ce' => {
1242 
      'hdlType' => 'std_logic',
1243 
      'width' => 1,
1244 
    },
1245 
    'sysgen_dut.to_register33_clk' => {
1246 
      'hdlType' => 'std_logic',
1247 
      'width' => 1,
1248 
    },
1249 
    'sysgen_dut.to_register33_clr' => {
1250 
      'hdlType' => 'std_logic',
1251 
      'width' => 1,
1252 
    },
1253 
    'sysgen_dut.to_register33_data_in' => {
1254 
      'hdlType' => 'std_logic',
1255 
      'width' => 1,
1256 
    },
1257 
    'sysgen_dut.to_register33_en' => {
1258 
      'hdlType' => 'std_logic',
1259 
      'width' => 1,
1260 
    },
1261 
    'sysgen_dut.to_register34_ce' => {
1262 
      'hdlType' => 'std_logic',
1263 
      'width' => 1,
1264 
    },
1265 
    'sysgen_dut.to_register34_clk' => {
1266 
      'hdlType' => 'std_logic',
1267 
      'width' => 1,
1268 
    },
1269 
    'sysgen_dut.to_register34_clr' => {
1270 
      'hdlType' => 'std_logic',
1271 
      'width' => 1,
1272 
    },
1273 
    'sysgen_dut.to_register34_data_in' => {
1274 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1275 
      'width' => 32,
1276 
    },
1277 
    'sysgen_dut.to_register34_en' => {
1278 
      'hdlType' => 'std_logic',
1279 
      'width' => 1,
1280 
    },
1281 
    'sysgen_dut.to_register3_ce' => {
1282 
      'hdlType' => 'std_logic',
1283 
      'width' => 1,
1284 
    },
1285 
    'sysgen_dut.to_register3_clk' => {
1286 
      'hdlType' => 'std_logic',
1287 
      'width' => 1,
1288 
    },
1289 
    'sysgen_dut.to_register3_clr' => {
1290 
      'hdlType' => 'std_logic',
1291 
      'width' => 1,
1292 
    },
1293 
    'sysgen_dut.to_register3_data_in' => {
1294 
      'hdlType' => 'std_logic',
1295 
      'width' => 1,
1296 
    },
1297 
    'sysgen_dut.to_register3_en' => {
1298 
      'hdlType' => 'std_logic',
1299 
      'width' => 1,
1300 
    },
1301 
    'sysgen_dut.to_register4_ce' => {
1302 
      'hdlType' => 'std_logic',
1303 
      'width' => 1,
1304 
    },
1305 
    'sysgen_dut.to_register4_clk' => {
1306 
      'hdlType' => 'std_logic',
1307 
      'width' => 1,
1308 
    },
1309 
    'sysgen_dut.to_register4_clr' => {
1310 
      'hdlType' => 'std_logic',
1311 
      'width' => 1,
1312 
    },
1313 
    'sysgen_dut.to_register4_data_in' => {
1314 
      'hdlType' => 'std_logic',
1315 
      'width' => 1,
1316 
    },
1317 
    'sysgen_dut.to_register4_en' => {
1318 
      'hdlType' => 'std_logic',
1319 
      'width' => 1,
1320 
    },
1321 
    'sysgen_dut.to_register5_ce' => {
1322 
      'hdlType' => 'std_logic',
1323 
      'width' => 1,
1324 
    },
1325 
    'sysgen_dut.to_register5_clk' => {
1326 
      'hdlType' => 'std_logic',
1327 
      'width' => 1,
1328 
    },
1329 
    'sysgen_dut.to_register5_clr' => {
1330 
      'hdlType' => 'std_logic',
1331 
      'width' => 1,
1332 
    },
1333 
    'sysgen_dut.to_register5_data_in' => {
1334 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1335 
      'width' => 32,
1336 
    },
1337 
    'sysgen_dut.to_register5_en' => {
1338 
      'hdlType' => 'std_logic',
1339 
      'width' => 1,
1340 
    },
1341 
    'sysgen_dut.to_register6_ce' => {
1342 
      'hdlType' => 'std_logic',
1343 
      'width' => 1,
1344 
    },
1345 
    'sysgen_dut.to_register6_clk' => {
1346 
      'hdlType' => 'std_logic',
1347 
      'width' => 1,
1348 
    },
1349 
    'sysgen_dut.to_register6_clr' => {
1350 
      'hdlType' => 'std_logic',
1351 
      'width' => 1,
1352 
    },
1353 
    'sysgen_dut.to_register6_data_in' => {
1354 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1355 
      'width' => 32,
1356 
    },
1357 
    'sysgen_dut.to_register6_en' => {
1358 
      'hdlType' => 'std_logic',
1359 
      'width' => 1,
1360 
    },
1361 
    'sysgen_dut.to_register7_ce' => {
1362 
      'hdlType' => 'std_logic',
1363 
      'width' => 1,
1364 
    },
1365 
    'sysgen_dut.to_register7_clk' => {
1366 
      'hdlType' => 'std_logic',
1367 
      'width' => 1,
1368 
    },
1369 
    'sysgen_dut.to_register7_clr' => {
1370 
      'hdlType' => 'std_logic',
1371 
      'width' => 1,
1372 
    },
1373 
    'sysgen_dut.to_register7_data_in' => {
1374 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1375 
      'width' => 32,
1376 
    },
1377 
    'sysgen_dut.to_register7_en' => {
1378 
      'hdlType' => 'std_logic',
1379 
      'width' => 1,
1380 
    },
1381 
    'sysgen_dut.to_register8_ce' => {
1382 
      'hdlType' => 'std_logic',
1383 
      'width' => 1,
1384 
    },
1385 
    'sysgen_dut.to_register8_clk' => {
1386 
      'hdlType' => 'std_logic',
1387 
      'width' => 1,
1388 
    },
1389 
    'sysgen_dut.to_register8_clr' => {
1390 
      'hdlType' => 'std_logic',
1391 
      'width' => 1,
1392 
    },
1393 
    'sysgen_dut.to_register8_data_in' => {
1394 
      'hdlType' => 'std_logic',
1395 
      'width' => 1,
1396 
    },
1397 
    'sysgen_dut.to_register8_en' => {
1398 
      'hdlType' => 'std_logic',
1399 
      'width' => 1,
1400 
    },
1401 
    'sysgen_dut.to_register9_ce' => {
1402 
      'hdlType' => 'std_logic',
1403 
      'width' => 1,
1404 
    },
1405 
    'sysgen_dut.to_register9_clk' => {
1406 
      'hdlType' => 'std_logic',
1407 
      'width' => 1,
1408 
    },
1409 
    'sysgen_dut.to_register9_clr' => {
1410 
      'hdlType' => 'std_logic',
1411 
      'width' => 1,
1412 
    },
1413 
    'sysgen_dut.to_register9_data_in' => {
1414 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1415 
      'width' => 32,
1416 
    },
1417 
    'sysgen_dut.to_register9_en' => {
1418 
      'hdlType' => 'std_logic',
1419 
      'width' => 1,
1420 
    },
1421 
    'to_register1.dout' => {
1422 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1423 
      'width' => 32,
1424 
    },
1425 
    'to_register10.dout' => {
1426 
      'hdlType' => 'std_logic',
1427 
      'width' => 1,
1428 
    },
1429 
    'to_register11.dout' => {
1430 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1431 
      'width' => 32,
1432 
    },
1433 
    'to_register12.dout' => {
1434 
      'hdlType' => 'std_logic',
1435 
      'width' => 1,
1436 
    },
1437 
    'to_register13.dout' => {
1438 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1439 
      'width' => 32,
1440 
    },
1441 
    'to_register14.dout' => {
1442 
      'hdlType' => 'std_logic',
1443 
      'width' => 1,
1444 
    },
1445 
    'to_register15.dout' => {
1446 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1447 
      'width' => 32,
1448 
    },
1449 
    'to_register16.dout' => {
1450 
      'hdlType' => 'std_logic',
1451 
      'width' => 1,
1452 
    },
1453 
    'to_register17.dout' => {
1454 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1455 
      'width' => 32,
1456 
    },
1457 
    'to_register18.dout' => {
1458 
      'hdlType' => 'std_logic',
1459 
      'width' => 1,
1460 
    },
1461 
    'to_register19.dout' => {
1462 
      'hdlType' => 'std_logic',
1463 
      'width' => 1,
1464 
    },
1465 
    'to_register2.dout' => {
1466 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1467 
      'width' => 32,
1468 
    },
1469 
    'to_register20.dout' => {
1470 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1471 
      'width' => 32,
1472 
    },
1473 
    'to_register21.dout' => {
1474 
      'hdlType' => 'std_logic',
1475 
      'width' => 1,
1476 
    },
1477 
    'to_register22.dout' => {
1478 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1479 
      'width' => 32,
1480 
    },
1481 
    'to_register23.dout' => {
1482 
      'hdlType' => 'std_logic',
1483 
      'width' => 1,
1484 
    },
1485 
    'to_register24.dout' => {
1486 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1487 
      'width' => 32,
1488 
    },
1489 
    'to_register25.dout' => {
1490 
      'hdlType' => 'std_logic',
1491 
      'width' => 1,
1492 
    },
1493 
    'to_register26.dout' => {
1494 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1495 
      'width' => 32,
1496 
    },
1497 
    'to_register27.dout' => {
1498 
      'hdlType' => 'std_logic',
1499 
      'width' => 1,
1500 
    },
1501 
    'to_register28.dout' => {
1502 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1503 
      'width' => 32,
1504 
    },
1505 
    'to_register29.dout' => {
1506 
      'hdlType' => 'std_logic',
1507 
      'width' => 1,
1508 
    },
1509 
    'to_register3.dout' => {
1510 
      'hdlType' => 'std_logic',
1511 
      'width' => 1,
1512 
    },
1513 
    'to_register30.dout' => {
1514 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1515 
      'width' => 32,
1516 
    },
1517 
    'to_register31.dout' => {
1518 
      'hdlType' => 'std_logic',
1519 
      'width' => 1,
1520 
    },
1521 
    'to_register32.dout' => {
1522 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1523 
      'width' => 32,
1524 
    },
1525 
    'to_register33.dout' => {
1526 
      'hdlType' => 'std_logic',
1527 
      'width' => 1,
1528 
    },
1529 
    'to_register34.dout' => {
1530 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1531 
      'width' => 32,
1532 
    },
1533 
    'to_register4.dout' => {
1534 
      'hdlType' => 'std_logic',
1535 
      'width' => 1,
1536 
    },
1537 
    'to_register5.dout' => {
1538 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1539 
      'width' => 32,
1540 
    },
1541 
    'to_register6.dout' => {
1542 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1543 
      'width' => 32,
1544 
    },
1545 
    'to_register7.dout' => {
1546 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1547 
      'width' => 32,
1548 
    },
1549 
    'to_register8.dout' => {
1550 
      'hdlType' => 'std_logic',
1551 
      'width' => 1,
1552 
    },
1553 
    'to_register9.dout' => {
1554 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1555 
      'width' => 32,
1556 
    },
1557 
  },
1558 
  'subblocks' => {
1559 
    'debug_in_1i' => {
1560 
      'connections' => {
1561 
        'debug_in_1i' => '.debug_in_1i',
1562 
      },
1563 
      'entity' => {
1564 
        'attributes' => {
1565 
          'entityAlreadyNetlisted' => 1,
1566 
          'isGateway' => 1,
1567 
          'is_floating_block' => 1,
1568 
        },
1569 
        'entityName' => 'debug_in_1i',
1570 
        'ports' => {
1571 
          'debug_in_1i' => {
1572 
            'attributes' => {
1573 
              'bin_pt' => 0,
1574 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
1575 
              'is_floating_block' => 1,
1576 
              'is_gateway_port' => 1,
1577 
              'must_be_hdl_vector' => 1,
1578 
              'period' => 1,
1579 
              'port_id' => 0,
1580 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
1581 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
1582 
              'timingConstraint' => 'none',
1583 
              'type' => 'UFix_32_0',
1584 
            },
1585 
            'direction' => 'out',
1586 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1587 
            'width' => 32,
1588 
          },
1589 
        },
1590 
      },
1591 
      'entityName' => 'debug_in_1i',
1592 
    },
1593 
    'debug_in_2i' => {
1594 
      'connections' => {
1595 
        'debug_in_2i' => '.debug_in_2i',
1596 
      },
1597 
      'entity' => {
1598 
        'attributes' => {
1599 
          'entityAlreadyNetlisted' => 1,
1600 
          'isGateway' => 1,
1601 
          'is_floating_block' => 1,
1602 
        },
1603 
        'entityName' => 'debug_in_2i',
1604 
        'ports' => {
1605 
          'debug_in_2i' => {
1606 
            'attributes' => {
1607 
              'bin_pt' => 0,
1608 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
1609 
              'is_floating_block' => 1,
1610 
              'is_gateway_port' => 1,
1611 
              'must_be_hdl_vector' => 1,
1612 
              'period' => 1,
1613 
              'port_id' => 0,
1614 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
1615 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
1616 
              'timingConstraint' => 'none',
1617 
              'type' => 'UFix_32_0',
1618 
            },
1619 
            'direction' => 'out',
1620 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1621 
            'width' => 32,
1622 
          },
1623 
        },
1624 
      },
1625 
      'entityName' => 'debug_in_2i',
1626 
    },
1627 
    'debug_in_3i' => {
1628 
      'connections' => {
1629 
        'debug_in_3i' => '.debug_in_3i',
1630 
      },
1631 
      'entity' => {
1632 
        'attributes' => {
1633 
          'entityAlreadyNetlisted' => 1,
1634 
          'isGateway' => 1,
1635 
          'is_floating_block' => 1,
1636 
        },
1637 
        'entityName' => 'debug_in_3i',
1638 
        'ports' => {
1639 
          'debug_in_3i' => {
1640 
            'attributes' => {
1641 
              'bin_pt' => 0,
1642 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
1643 
              'is_floating_block' => 1,
1644 
              'is_gateway_port' => 1,
1645 
              'must_be_hdl_vector' => 1,
1646 
              'period' => 1,
1647 
              'port_id' => 0,
1648 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
1649 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
1650 
              'timingConstraint' => 'none',
1651 
              'type' => 'UFix_32_0',
1652 
            },
1653 
            'direction' => 'out',
1654 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1655 
            'width' => 32,
1656 
          },
1657 
        },
1658 
      },
1659 
      'entityName' => 'debug_in_3i',
1660 
    },
1661 
    'debug_in_4i' => {
1662 
      'connections' => {
1663 
        'debug_in_4i' => '.debug_in_4i',
1664 
      },
1665 
      'entity' => {
1666 
        'attributes' => {
1667 
          'entityAlreadyNetlisted' => 1,
1668 
          'isGateway' => 1,
1669 
          'is_floating_block' => 1,
1670 
        },
1671 
        'entityName' => 'debug_in_4i',
1672 
        'ports' => {
1673 
          'debug_in_4i' => {
1674 
            'attributes' => {
1675 
              'bin_pt' => 0,
1676 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
1677 
              'is_floating_block' => 1,
1678 
              'is_gateway_port' => 1,
1679 
              'must_be_hdl_vector' => 1,
1680 
              'period' => 1,
1681 
              'port_id' => 0,
1682 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
1683 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
1684 
              'timingConstraint' => 'none',
1685 
              'type' => 'UFix_32_0',
1686 
            },
1687 
            'direction' => 'out',
1688 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1689 
            'width' => 32,
1690 
          },
1691 
        },
1692 
      },
1693 
      'entityName' => 'debug_in_4i',
1694 
    },
1695 
    'dma_host2board_busy' => {
1696 
      'connections' => {
1697 
        'dma_host2board_busy' => '.dma_host2board_busy',
1698 
      },
1699 
      'entity' => {
1700 
        'attributes' => {
1701 
          'entityAlreadyNetlisted' => 1,
1702 
          'isGateway' => 1,
1703 
          'is_floating_block' => 1,
1704 
        },
1705 
        'entityName' => 'dma_host2board_busy',
1706 
        'ports' => {
1707 
          'dma_host2board_busy' => {
1708 
            'attributes' => {
1709 
              'bin_pt' => 0,
1710 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
1711 
              'is_floating_block' => 1,
1712 
              'is_gateway_port' => 1,
1713 
              'must_be_hdl_vector' => 1,
1714 
              'period' => 1,
1715 
              'port_id' => 0,
1716 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
1717 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
1718 
              'timingConstraint' => 'none',
1719 
              'type' => 'UFix_1_0',
1720 
            },
1721 
            'direction' => 'out',
1722 
            'hdlType' => 'std_logic',
1723 
            'width' => 1,
1724 
          },
1725 
        },
1726 
      },
1727 
      'entityName' => 'dma_host2board_busy',
1728 
    },
1729 
    'dma_host2board_done' => {
1730 
      'connections' => {
1731 
        'dma_host2board_done' => '.dma_host2board_done',
1732 
      },
1733 
      'entity' => {
1734 
        'attributes' => {
1735 
          'entityAlreadyNetlisted' => 1,
1736 
          'isGateway' => 1,
1737 
          'is_floating_block' => 1,
1738 
        },
1739 
        'entityName' => 'dma_host2board_done',
1740 
        'ports' => {
1741 
          'dma_host2board_done' => {
1742 
            'attributes' => {
1743 
              'bin_pt' => 0,
1744 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
1745 
              'is_floating_block' => 1,
1746 
              'is_gateway_port' => 1,
1747 
              'must_be_hdl_vector' => 1,
1748 
              'period' => 1,
1749 
              'port_id' => 0,
1750 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
1751 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
1752 
              'timingConstraint' => 'none',
1753 
              'type' => 'UFix_1_0',
1754 
            },
1755 
            'direction' => 'out',
1756 
            'hdlType' => 'std_logic',
1757 
            'width' => 1,
1758 
          },
1759 
        },
1760 
      },
1761 
      'entityName' => 'dma_host2board_done',
1762 
    },
1763 
    'from_register1' => {
1764 
      'connections' => {
1765 
        'data_out' => 'from_register1.data_out',
1766 
      },
1767 
      'entity' => {
1768 
        'attributes' => {
1769 
          'entityAlreadyNetlisted' => 1,
1770 
          'generics' => [
1771 
          ],
1772 
          'is_floating_block' => 1,
1773 
          'mask' => {
1774 
            'Block_Handle' => 10.0009765625,
1775 
            'Block_handle' => 10.0009765625,
1776 
            'MDL_Handle' => 3.0009765625,
1777 
            'MDL_handle' => 3.0009765625,
1778 
            'arith_type' => 2,
1779 
            'bin_pt' => 0,
1780 
            'block_config' => 'sysgen_blockset:fromreg_config',
1781 
            'block_handle' => 10.0009765625,
1782 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1783 
            'block_type' => 'fromreg',
1784 
            'dbl_ovrd' => 0,
1785 
            'init' => 0,
1786 
            'init_bit_vector' => '0b',
1787 
            'mdl_handle' => 3.0009765625,
1788 
            'model_handle' => 3.0009765625,
1789 
            'n_bits' => 1,
1790 
            'ownership' => 2,
1791 
            'period' => '8e-009',
1792 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1793 
            'shared_memory_name' => 'register01rv',
1794 
          },
1795 
          'needs_vhdl_wrapper' => 0,
1796 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1797 
        },
1798 
        'entityName' => 'x_x61',
1799 
        'ports' => {
1800 
          'data_out' => {
1801 
            'attributes' => {
1802 
              'bin_pt' => 0,
1803 
              'is_floating_block' => 1,
1804 
              'must_be_hdl_vector' => 1,
1805 
              'period' => 1,
1806 
              'port_id' => 0,
1807 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
1808 
              'type' => 'UFix_1_0',
1809 
            },
1810 
            'direction' => 'out',
1811 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1812 
            'width' => 1,
1813 
          },
1814 
        },
1815 
      },
1816 
      'entityName' => 'x_x61',
1817 
    },
1818 
    'from_register10' => {
1819 
      'connections' => {
1820 
        'data_out' => 'from_register10.data_out',
1821 
      },
1822 
      'entity' => {
1823 
        'attributes' => {
1824 
          'entityAlreadyNetlisted' => 1,
1825 
          'generics' => [
1826 
          ],
1827 
          'is_floating_block' => 1,
1828 
          'mask' => {
1829 
            'Block_Handle' => 11.0009765625,
1830 
            'Block_handle' => 11.0009765625,
1831 
            'MDL_Handle' => 3.0009765625,
1832 
            'MDL_handle' => 3.0009765625,
1833 
            'arith_type' => 2,
1834 
            'bin_pt' => 0,
1835 
            'block_config' => 'sysgen_blockset:fromreg_config',
1836 
            'block_handle' => 11.0009765625,
1837 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1838 
            'block_type' => 'fromreg',
1839 
            'dbl_ovrd' => 0,
1840 
            'init' => 0,
1841 
            'init_bit_vector' => '00000000000000000000000000000000b',
1842 
            'mdl_handle' => 3.0009765625,
1843 
            'model_handle' => 3.0009765625,
1844 
            'n_bits' => 32,
1845 
            'ownership' => 2,
1846 
            'period' => '8e-009',
1847 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1848 
            'shared_memory_name' => 'register05rd',
1849 
          },
1850 
          'needs_vhdl_wrapper' => 0,
1851 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1852 
        },
1853 
        'entityName' => 'x_x62',
1854 
        'ports' => {
1855 
          'data_out' => {
1856 
            'attributes' => {
1857 
              'bin_pt' => 0,
1858 
              'is_floating_block' => 1,
1859 
              'must_be_hdl_vector' => 1,
1860 
              'period' => 1,
1861 
              'port_id' => 0,
1862 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
1863 
              'type' => 'UFix_32_0',
1864 
            },
1865 
            'direction' => 'out',
1866 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1867 
            'width' => 32,
1868 
          },
1869 
        },
1870 
      },
1871 
      'entityName' => 'x_x62',
1872 
    },
1873 
    'from_register11' => {
1874 
      'connections' => {
1875 
        'data_out' => 'from_register11.data_out',
1876 
      },
1877 
      'entity' => {
1878 
        'attributes' => {
1879 
          'entityAlreadyNetlisted' => 1,
1880 
          'generics' => [
1881 
          ],
1882 
          'is_floating_block' => 1,
1883 
          'mask' => {
1884 
            'Block_Handle' => 12.0009765625,
1885 
            'Block_handle' => 12.0009765625,
1886 
            'MDL_Handle' => 3.0009765625,
1887 
            'MDL_handle' => 3.0009765625,
1888 
            'arith_type' => 2,
1889 
            'bin_pt' => 0,
1890 
            'block_config' => 'sysgen_blockset:fromreg_config',
1891 
            'block_handle' => 12.0009765625,
1892 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1893 
            'block_type' => 'fromreg',
1894 
            'dbl_ovrd' => 0,
1895 
            'init' => 0,
1896 
            'init_bit_vector' => '00000000000000000000000000000000b',
1897 
            'mdl_handle' => 3.0009765625,
1898 
            'model_handle' => 3.0009765625,
1899 
            'n_bits' => 32,
1900 
            'ownership' => 2,
1901 
            'period' => '8e-009',
1902 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1903 
            'shared_memory_name' => 'register06rd',
1904 
          },
1905 
          'needs_vhdl_wrapper' => 0,
1906 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1907 
        },
1908 
        'entityName' => 'x_x63',
1909 
        'ports' => {
1910 
          'data_out' => {
1911 
            'attributes' => {
1912 
              'bin_pt' => 0,
1913 
              'is_floating_block' => 1,
1914 
              'must_be_hdl_vector' => 1,
1915 
              'period' => 1,
1916 
              'port_id' => 0,
1917 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
1918 
              'type' => 'UFix_32_0',
1919 
            },
1920 
            'direction' => 'out',
1921 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1922 
            'width' => 32,
1923 
          },
1924 
        },
1925 
      },
1926 
      'entityName' => 'x_x63',
1927 
    },
1928 
    'from_register12' => {
1929 
      'connections' => {
1930 
        'data_out' => 'from_register12.data_out',
1931 
      },
1932 
      'entity' => {
1933 
        'attributes' => {
1934 
          'entityAlreadyNetlisted' => 1,
1935 
          'generics' => [
1936 
          ],
1937 
          'is_floating_block' => 1,
1938 
          'mask' => {
1939 
            'Block_Handle' => 13.0009765625,
1940 
            'Block_handle' => 13.0009765625,
1941 
            'MDL_Handle' => 3.0009765625,
1942 
            'MDL_handle' => 3.0009765625,
1943 
            'arith_type' => 2,
1944 
            'bin_pt' => 0,
1945 
            'block_config' => 'sysgen_blockset:fromreg_config',
1946 
            'block_handle' => 13.0009765625,
1947 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1948 
            'block_type' => 'fromreg',
1949 
            'dbl_ovrd' => 0,
1950 
            'init' => 0,
1951 
            'init_bit_vector' => '0b',
1952 
            'mdl_handle' => 3.0009765625,
1953 
            'model_handle' => 3.0009765625,
1954 
            'n_bits' => 1,
1955 
            'ownership' => 2,
1956 
            'period' => '8e-009',
1957 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1958 
            'shared_memory_name' => 'register06rv',
1959 
          },
1960 
          'needs_vhdl_wrapper' => 0,
1961 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1962 
        },
1963 
        'entityName' => 'x_x64',
1964 
        'ports' => {
1965 
          'data_out' => {
1966 
            'attributes' => {
1967 
              'bin_pt' => 0,
1968 
              'is_floating_block' => 1,
1969 
              'must_be_hdl_vector' => 1,
1970 
              'period' => 1,
1971 
              'port_id' => 0,
1972 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
1973 
              'type' => 'UFix_1_0',
1974 
            },
1975 
            'direction' => 'out',
1976 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1977 
            'width' => 1,
1978 
          },
1979 
        },
1980 
      },
1981 
      'entityName' => 'x_x64',
1982 
    },
1983 
    'from_register13' => {
1984 
      'connections' => {
1985 
        'data_out' => 'from_register13.data_out',
1986 
      },
1987 
      'entity' => {
1988 
        'attributes' => {
1989 
          'entityAlreadyNetlisted' => 1,
1990 
          'generics' => [
1991 
          ],
1992 
          'is_floating_block' => 1,
1993 
          'mask' => {
1994 
            'Block_Handle' => 14.0009765625,
1995 
            'Block_handle' => 14.0009765625,
1996 
            'MDL_Handle' => 3.0009765625,
1997 
            'MDL_handle' => 3.0009765625,
1998 
            'arith_type' => 2,
1999 
            'bin_pt' => 0,
2000 
            'block_config' => 'sysgen_blockset:fromreg_config',
2001 
            'block_handle' => 14.0009765625,
2002 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
2003 
            'block_type' => 'fromreg',
2004 
            'dbl_ovrd' => 0,
2005 
            'init' => 0,
2006 
            'init_bit_vector' => '00000000000000000000000000000000b',
2007 
            'mdl_handle' => 3.0009765625,
2008 
            'model_handle' => 3.0009765625,
2009 
            'n_bits' => 32,
2010 
            'ownership' => 2,
2011 
            'period' => '8e-009',
2012 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2013 
            'shared_memory_name' => 'register07rd',
2014 
          },
2015 
          'needs_vhdl_wrapper' => 0,
2016 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
2017 
        },
2018 
        'entityName' => 'x_x65',
2019 
        'ports' => {
2020 
          'data_out' => {
2021 
            'attributes' => {
2022 
              'bin_pt' => 0,
2023 
              'is_floating_block' => 1,
2024 
              'must_be_hdl_vector' => 1,
2025 
              'period' => 1,
2026 
              'port_id' => 0,
2027 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
2028 
              'type' => 'UFix_32_0',
2029 
            },
2030 
            'direction' => 'out',
2031 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2032 
            'width' => 32,
2033 
          },
2034 
        },
2035 
      },
2036 
      'entityName' => 'x_x65',
2037 
    },
2038 
    'from_register14' => {
2039 
      'connections' => {
2040 
        'data_out' => 'from_register14.data_out',
2041 
      },
2042 
      'entity' => {
2043 
        'attributes' => {
2044 
          'entityAlreadyNetlisted' => 1,
2045 
          'generics' => [
2046 
          ],
2047 
          'is_floating_block' => 1,
2048 
          'mask' => {
2049 
            'Block_Handle' => 15.0009765625,
2050 
            'Block_handle' => 15.0009765625,
2051 
            'MDL_Handle' => 3.0009765625,
2052 
            'MDL_handle' => 3.0009765625,
2053 
            'arith_type' => 2,
2054 
            'bin_pt' => 0,
2055 
            'block_config' => 'sysgen_blockset:fromreg_config',
2056 
            'block_handle' => 15.0009765625,
2057 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2058 
            'block_type' => 'fromreg',
2059 
            'dbl_ovrd' => 0,
2060 
            'init' => 0,
2061 
            'init_bit_vector' => '0b',
2062 
            'mdl_handle' => 3.0009765625,
2063 
            'model_handle' => 3.0009765625,
2064 
            'n_bits' => 1,
2065 
            'ownership' => 2,
2066 
            'period' => '8e-009',
2067 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2068 
            'shared_memory_name' => 'register07rv',
2069 
          },
2070 
          'needs_vhdl_wrapper' => 0,
2071 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2072 
        },
2073 
        'entityName' => 'x_x66',
2074 
        'ports' => {
2075 
          'data_out' => {
2076 
            'attributes' => {
2077 
              'bin_pt' => 0,
2078 
              'is_floating_block' => 1,
2079 
              'must_be_hdl_vector' => 1,
2080 
              'period' => 1,
2081 
              'port_id' => 0,
2082 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
2083 
              'type' => 'UFix_1_0',
2084 
            },
2085 
            'direction' => 'out',
2086 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2087 
            'width' => 1,
2088 
          },
2089 
        },
2090 
      },
2091 
      'entityName' => 'x_x66',
2092 
    },
2093 
    'from_register15' => {
2094 
      'connections' => {
2095 
        'data_out' => 'from_register15.data_out',
2096 
      },
2097 
      'entity' => {
2098 
        'attributes' => {
2099 
          'entityAlreadyNetlisted' => 1,
2100 
          'generics' => [
2101 
          ],
2102 
          'is_floating_block' => 1,
2103 
          'mask' => {
2104 
            'Block_Handle' => 16.0009765625,
2105 
            'Block_handle' => 16.0009765625,
2106 
            'MDL_Handle' => 3.0009765625,
2107 
            'MDL_handle' => 3.0009765625,
2108 
            'arith_type' => 2,
2109 
            'bin_pt' => 0,
2110 
            'block_config' => 'sysgen_blockset:fromreg_config',
2111 
            'block_handle' => 16.0009765625,
2112 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2113 
            'block_type' => 'fromreg',
2114 
            'dbl_ovrd' => 0,
2115 
            'init' => 0,
2116 
            'init_bit_vector' => '00000000000000000000000000000000b',
2117 
            'mdl_handle' => 3.0009765625,
2118 
            'model_handle' => 3.0009765625,
2119 
            'n_bits' => 32,
2120 
            'ownership' => 2,
2121 
            'period' => '8e-009',
2122 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2123 
            'shared_memory_name' => 'register08rd',
2124 
          },
2125 
          'needs_vhdl_wrapper' => 0,
2126 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2127 
        },
2128 
        'entityName' => 'x_x67',
2129 
        'ports' => {
2130 
          'data_out' => {
2131 
            'attributes' => {
2132 
              'bin_pt' => 0,
2133 
              'is_floating_block' => 1,
2134 
              'must_be_hdl_vector' => 1,
2135 
              'period' => 1,
2136 
              'port_id' => 0,
2137 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
2138 
              'type' => 'UFix_32_0',
2139 
            },
2140 
            'direction' => 'out',
2141 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2142 
            'width' => 32,
2143 
          },
2144 
        },
2145 
      },
2146 
      'entityName' => 'x_x67',
2147 
    },
2148 
    'from_register16' => {
2149 
      'connections' => {
2150 
        'data_out' => 'from_register16.data_out',
2151 
      },
2152 
      'entity' => {
2153 
        'attributes' => {
2154 
          'entityAlreadyNetlisted' => 1,
2155 
          'generics' => [
2156 
          ],
2157 
          'is_floating_block' => 1,
2158 
          'mask' => {
2159 
            'Block_Handle' => 17.0009765625,
2160 
            'Block_handle' => 17.0009765625,
2161 
            'MDL_Handle' => 3.0009765625,
2162 
            'MDL_handle' => 3.0009765625,
2163 
            'arith_type' => 2,
2164 
            'bin_pt' => 0,
2165 
            'block_config' => 'sysgen_blockset:fromreg_config',
2166 
            'block_handle' => 17.0009765625,
2167 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2168 
            'block_type' => 'fromreg',
2169 
            'dbl_ovrd' => 0,
2170 
            'init' => 0,
2171 
            'init_bit_vector' => '0b',
2172 
            'mdl_handle' => 3.0009765625,
2173 
            'model_handle' => 3.0009765625,
2174 
            'n_bits' => 1,
2175 
            'ownership' => 2,
2176 
            'period' => '8e-009',
2177 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2178 
            'shared_memory_name' => 'register08rv',
2179 
          },
2180 
          'needs_vhdl_wrapper' => 0,
2181 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2182 
        },
2183 
        'entityName' => 'x_x68',
2184 
        'ports' => {
2185 
          'data_out' => {
2186 
            'attributes' => {
2187 
              'bin_pt' => 0,
2188 
              'is_floating_block' => 1,
2189 
              'must_be_hdl_vector' => 1,
2190 
              'period' => 1,
2191 
              'port_id' => 0,
2192 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
2193 
              'type' => 'UFix_1_0',
2194 
            },
2195 
            'direction' => 'out',
2196 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2197 
            'width' => 1,
2198 
          },
2199 
        },
2200 
      },
2201 
      'entityName' => 'x_x68',
2202 
    },
2203 
    'from_register17' => {
2204 
      'connections' => {
2205 
        'data_out' => 'from_register17.data_out',
2206 
      },
2207 
      'entity' => {
2208 
        'attributes' => {
2209 
          'entityAlreadyNetlisted' => 1,
2210 
          'generics' => [
2211 
          ],
2212 
          'is_floating_block' => 1,
2213 
          'mask' => {
2214 
            'Block_Handle' => 18.0009765625,
2215 
            'Block_handle' => 18.0009765625,
2216 
            'MDL_Handle' => 3.0009765625,
2217 
            'MDL_handle' => 3.0009765625,
2218 
            'arith_type' => 2,
2219 
            'bin_pt' => 0,
2220 
            'block_config' => 'sysgen_blockset:fromreg_config',
2221 
            'block_handle' => 18.0009765625,
2222 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2223 
            'block_type' => 'fromreg',
2224 
            'dbl_ovrd' => 0,
2225 
            'init' => 0,
2226 
            'init_bit_vector' => '00000000000000000000000000000000b',
2227 
            'mdl_handle' => 3.0009765625,
2228 
            'model_handle' => 3.0009765625,
2229 
            'n_bits' => 32,
2230 
            'ownership' => 2,
2231 
            'period' => '8e-009',
2232 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2233 
            'shared_memory_name' => 'register09rd',
2234 
          },
2235 
          'needs_vhdl_wrapper' => 0,
2236 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2237 
        },
2238 
        'entityName' => 'x_x69',
2239 
        'ports' => {
2240 
          'data_out' => {
2241 
            'attributes' => {
2242 
              'bin_pt' => 0,
2243 
              'is_floating_block' => 1,
2244 
              'must_be_hdl_vector' => 1,
2245 
              'period' => 1,
2246 
              'port_id' => 0,
2247 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
2248 
              'type' => 'UFix_32_0',
2249 
            },
2250 
            'direction' => 'out',
2251 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2252 
            'width' => 32,
2253 
          },
2254 
        },
2255 
      },
2256 
      'entityName' => 'x_x69',
2257 
    },
2258 
    'from_register18' => {
2259 
      'connections' => {
2260 
        'data_out' => 'from_register18.data_out',
2261 
      },
2262 
      'entity' => {
2263 
        'attributes' => {
2264 
          'entityAlreadyNetlisted' => 1,
2265 
          'generics' => [
2266 
          ],
2267 
          'is_floating_block' => 1,
2268 
          'mask' => {
2269 
            'Block_Handle' => 19.0009765625,
2270 
            'Block_handle' => 19.0009765625,
2271 
            'MDL_Handle' => 3.0009765625,
2272 
            'MDL_handle' => 3.0009765625,
2273 
            'arith_type' => 2,
2274 
            'bin_pt' => 0,
2275 
            'block_config' => 'sysgen_blockset:fromreg_config',
2276 
            'block_handle' => 19.0009765625,
2277 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2278 
            'block_type' => 'fromreg',
2279 
            'dbl_ovrd' => 0,
2280 
            'init' => 0,
2281 
            'init_bit_vector' => '0b',
2282 
            'mdl_handle' => 3.0009765625,
2283 
            'model_handle' => 3.0009765625,
2284 
            'n_bits' => 1,
2285 
            'ownership' => 2,
2286 
            'period' => '8e-009',
2287 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2288 
            'shared_memory_name' => 'register09rv',
2289 
          },
2290 
          'needs_vhdl_wrapper' => 0,
2291 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2292 
        },
2293 
        'entityName' => 'x_x70',
2294 
        'ports' => {
2295 
          'data_out' => {
2296 
            'attributes' => {
2297 
              'bin_pt' => 0,
2298 
              'is_floating_block' => 1,
2299 
              'must_be_hdl_vector' => 1,
2300 
              'period' => 1,
2301 
              'port_id' => 0,
2302 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
2303 
              'type' => 'UFix_1_0',
2304 
            },
2305 
            'direction' => 'out',
2306 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2307 
            'width' => 1,
2308 
          },
2309 
        },
2310 
      },
2311 
      'entityName' => 'x_x70',
2312 
    },
2313 
    'from_register19' => {
2314 
      'connections' => {
2315 
        'data_out' => 'from_register19.data_out',
2316 
      },
2317 
      'entity' => {
2318 
        'attributes' => {
2319 
          'entityAlreadyNetlisted' => 1,
2320 
          'generics' => [
2321 
          ],
2322 
          'is_floating_block' => 1,
2323 
          'mask' => {
2324 
            'Block_Handle' => 20.0009765625,
2325 
            'Block_handle' => 20.0009765625,
2326 
            'MDL_Handle' => 3.0009765625,
2327 
            'MDL_handle' => 3.0009765625,
2328 
            'arith_type' => 2,
2329 
            'bin_pt' => 0,
2330 
            'block_config' => 'sysgen_blockset:fromreg_config',
2331 
            'block_handle' => 20.0009765625,
2332 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2333 
            'block_type' => 'fromreg',
2334 
            'dbl_ovrd' => 0,
2335 
            'init' => 0,
2336 
            'init_bit_vector' => '00000000000000000000000000000000b',
2337 
            'mdl_handle' => 3.0009765625,
2338 
            'model_handle' => 3.0009765625,
2339 
            'n_bits' => 32,
2340 
            'ownership' => 2,
2341 
            'period' => '8e-009',
2342 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2343 
            'shared_memory_name' => 'register10rd',
2344 
          },
2345 
          'needs_vhdl_wrapper' => 0,
2346 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2347 
        },
2348 
        'entityName' => 'x_x71',
2349 
        'ports' => {
2350 
          'data_out' => {
2351 
            'attributes' => {
2352 
              'bin_pt' => 0,
2353 
              'is_floating_block' => 1,
2354 
              'must_be_hdl_vector' => 1,
2355 
              'period' => 1,
2356 
              'port_id' => 0,
2357 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
2358 
              'type' => 'UFix_32_0',
2359 
            },
2360 
            'direction' => 'out',
2361 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2362 
            'width' => 32,
2363 
          },
2364 
        },
2365 
      },
2366 
      'entityName' => 'x_x71',
2367 
    },
2368 
    'from_register2' => {
2369 
      'connections' => {
2370 
        'data_out' => 'from_register2.data_out',
2371 
      },
2372 
      'entity' => {
2373 
        'attributes' => {
2374 
          'entityAlreadyNetlisted' => 1,
2375 
          'generics' => [
2376 
          ],
2377 
          'is_floating_block' => 1,
2378 
          'mask' => {
2379 
            'Block_Handle' => 21.0009765625,
2380 
            'Block_handle' => 21.0009765625,
2381 
            'MDL_Handle' => 3.0009765625,
2382 
            'MDL_handle' => 3.0009765625,
2383 
            'arith_type' => 2,
2384 
            'bin_pt' => 0,
2385 
            'block_config' => 'sysgen_blockset:fromreg_config',
2386 
            'block_handle' => 21.0009765625,
2387 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2388 
            'block_type' => 'fromreg',
2389 
            'dbl_ovrd' => 0,
2390 
            'init' => 0,
2391 
            'init_bit_vector' => '0b',
2392 
            'mdl_handle' => 3.0009765625,
2393 
            'model_handle' => 3.0009765625,
2394 
            'n_bits' => 1,
2395 
            'ownership' => 2,
2396 
            'period' => '8e-009',
2397 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2398 
            'shared_memory_name' => 'register02rv',
2399 
          },
2400 
          'needs_vhdl_wrapper' => 0,
2401 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2402 
        },
2403 
        'entityName' => 'x_x72',
2404 
        'ports' => {
2405 
          'data_out' => {
2406 
            'attributes' => {
2407 
              'bin_pt' => 0,
2408 
              'is_floating_block' => 1,
2409 
              'must_be_hdl_vector' => 1,
2410 
              'period' => 1,
2411 
              'port_id' => 0,
2412 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
2413 
              'type' => 'UFix_1_0',
2414 
            },
2415 
            'direction' => 'out',
2416 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2417 
            'width' => 1,
2418 
          },
2419 
        },
2420 
      },
2421 
      'entityName' => 'x_x72',
2422 
    },
2423 
    'from_register20' => {
2424 
      'connections' => {
2425 
        'data_out' => 'from_register20.data_out',
2426 
      },
2427 
      'entity' => {
2428 
        'attributes' => {
2429 
          'entityAlreadyNetlisted' => 1,
2430 
          'generics' => [
2431 
          ],
2432 
          'is_floating_block' => 1,
2433 
          'mask' => {
2434 
            'Block_Handle' => 22.0009765625,
2435 
            'Block_handle' => 22.0009765625,
2436 
            'MDL_Handle' => 3.0009765625,
2437 
            'MDL_handle' => 3.0009765625,
2438 
            'arith_type' => 2,
2439 
            'bin_pt' => 0,
2440 
            'block_config' => 'sysgen_blockset:fromreg_config',
2441 
            'block_handle' => 22.0009765625,
2442 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2443 
            'block_type' => 'fromreg',
2444 
            'dbl_ovrd' => 0,
2445 
            'init' => 0,
2446 
            'init_bit_vector' => '0b',
2447 
            'mdl_handle' => 3.0009765625,
2448 
            'model_handle' => 3.0009765625,
2449 
            'n_bits' => 1,
2450 
            'ownership' => 2,
2451 
            'period' => '8e-009',
2452 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2453 
            'shared_memory_name' => 'register10rv',
2454 
          },
2455 
          'needs_vhdl_wrapper' => 0,
2456 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2457 
        },
2458 
        'entityName' => 'x_x73',
2459 
        'ports' => {
2460 
          'data_out' => {
2461 
            'attributes' => {
2462 
              'bin_pt' => 0,
2463 
              'is_floating_block' => 1,
2464 
              'must_be_hdl_vector' => 1,
2465 
              'period' => 1,
2466 
              'port_id' => 0,
2467 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
2468 
              'type' => 'UFix_1_0',
2469 
            },
2470 
            'direction' => 'out',
2471 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2472 
            'width' => 1,
2473 
          },
2474 
        },
2475 
      },
2476 
      'entityName' => 'x_x73',
2477 
    },
2478 
    'from_register21' => {
2479 
      'connections' => {
2480 
        'data_out' => 'from_register21.data_out',
2481 
      },
2482 
      'entity' => {
2483 
        'attributes' => {
2484 
          'entityAlreadyNetlisted' => 1,
2485 
          'generics' => [
2486 
          ],
2487 
          'is_floating_block' => 1,
2488 
          'mask' => {
2489 
            'Block_Handle' => 23.0009765625,
2490 
            'Block_handle' => 23.0009765625,
2491 
            'MDL_Handle' => 3.0009765625,
2492 
            'MDL_handle' => 3.0009765625,
2493 
            'arith_type' => 2,
2494 
            'bin_pt' => 0,
2495 
            'block_config' => 'sysgen_blockset:fromreg_config',
2496 
            'block_handle' => 23.0009765625,
2497 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2498 
            'block_type' => 'fromreg',
2499 
            'dbl_ovrd' => 0,
2500 
            'init' => 0,
2501 
            'init_bit_vector' => '00000000000000000000000000000000b',
2502 
            'mdl_handle' => 3.0009765625,
2503 
            'model_handle' => 3.0009765625,
2504 
            'n_bits' => 32,
2505 
            'ownership' => 2,
2506 
            'period' => '8e-009',
2507 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2508 
            'shared_memory_name' => 'register11rd',
2509 
          },
2510 
          'needs_vhdl_wrapper' => 0,
2511 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2512 
        },
2513 
        'entityName' => 'x_x74',
2514 
        'ports' => {
2515 
          'data_out' => {
2516 
            'attributes' => {
2517 
              'bin_pt' => 0,
2518 
              'is_floating_block' => 1,
2519 
              'must_be_hdl_vector' => 1,
2520 
              'period' => 1,
2521 
              'port_id' => 0,
2522 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
2523 
              'type' => 'UFix_32_0',
2524 
            },
2525 
            'direction' => 'out',
2526 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2527 
            'width' => 32,
2528 
          },
2529 
        },
2530 
      },
2531 
      'entityName' => 'x_x74',
2532 
    },
2533 
    'from_register22' => {
2534 
      'connections' => {
2535 
        'data_out' => 'from_register22.data_out',
2536 
      },
2537 
      'entity' => {
2538 
        'attributes' => {
2539 
          'entityAlreadyNetlisted' => 1,
2540 
          'generics' => [
2541 
          ],
2542 
          'is_floating_block' => 1,
2543 
          'mask' => {
2544 
            'Block_Handle' => 24.0009765625,
2545 
            'Block_handle' => 24.0009765625,
2546 
            'MDL_Handle' => 3.0009765625,
2547 
            'MDL_handle' => 3.0009765625,
2548 
            'arith_type' => 2,
2549 
            'bin_pt' => 0,
2550 
            'block_config' => 'sysgen_blockset:fromreg_config',
2551 
            'block_handle' => 24.0009765625,
2552 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2553 
            'block_type' => 'fromreg',
2554 
            'dbl_ovrd' => 0,
2555 
            'init' => 0,
2556 
            'init_bit_vector' => '0b',
2557 
            'mdl_handle' => 3.0009765625,
2558 
            'model_handle' => 3.0009765625,
2559 
            'n_bits' => 1,
2560 
            'ownership' => 2,
2561 
            'period' => '8e-009',
2562 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2563 
            'shared_memory_name' => 'register11rv',
2564 
          },
2565 
          'needs_vhdl_wrapper' => 0,
2566 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2567 
        },
2568 
        'entityName' => 'x_x75',
2569 
        'ports' => {
2570 
          'data_out' => {
2571 
            'attributes' => {
2572 
              'bin_pt' => 0,
2573 
              'is_floating_block' => 1,
2574 
              'must_be_hdl_vector' => 1,
2575 
              'period' => 1,
2576 
              'port_id' => 0,
2577 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
2578 
              'type' => 'UFix_1_0',
2579 
            },
2580 
            'direction' => 'out',
2581 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2582 
            'width' => 1,
2583 
          },
2584 
        },
2585 
      },
2586 
      'entityName' => 'x_x75',
2587 
    },
2588 
    'from_register23' => {
2589 
      'connections' => {
2590 
        'data_out' => 'from_register23.data_out',
2591 
      },
2592 
      'entity' => {
2593 
        'attributes' => {
2594 
          'entityAlreadyNetlisted' => 1,
2595 
          'generics' => [
2596 
          ],
2597 
          'is_floating_block' => 1,
2598 
          'mask' => {
2599 
            'Block_Handle' => 25.0009765625,
2600 
            'Block_handle' => 25.0009765625,
2601 
            'MDL_Handle' => 3.0009765625,
2602 
            'MDL_handle' => 3.0009765625,
2603 
            'arith_type' => 2,
2604 
            'bin_pt' => 0,
2605 
            'block_config' => 'sysgen_blockset:fromreg_config',
2606 
            'block_handle' => 25.0009765625,
2607 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2608 
            'block_type' => 'fromreg',
2609 
            'dbl_ovrd' => 0,
2610 
            'init' => 0,
2611 
            'init_bit_vector' => '00000000000000000000000000000000b',
2612 
            'mdl_handle' => 3.0009765625,
2613 
            'model_handle' => 3.0009765625,
2614 
            'n_bits' => 32,
2615 
            'ownership' => 2,
2616 
            'period' => '8e-009',
2617 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2618 
            'shared_memory_name' => 'register12rd',
2619 
          },
2620 
          'needs_vhdl_wrapper' => 0,
2621 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2622 
        },
2623 
        'entityName' => 'x_x76',
2624 
        'ports' => {
2625 
          'data_out' => {
2626 
            'attributes' => {
2627 
              'bin_pt' => 0,
2628 
              'is_floating_block' => 1,
2629 
              'must_be_hdl_vector' => 1,
2630 
              'period' => 1,
2631 
              'port_id' => 0,
2632 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
2633 
              'type' => 'UFix_32_0',
2634 
            },
2635 
            'direction' => 'out',
2636 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2637 
            'width' => 32,
2638 
          },
2639 
        },
2640 
      },
2641 
      'entityName' => 'x_x76',
2642 
    },
2643 
    'from_register24' => {
2644 
      'connections' => {
2645 
        'data_out' => 'from_register24.data_out',
2646 
      },
2647 
      'entity' => {
2648 
        'attributes' => {
2649 
          'entityAlreadyNetlisted' => 1,
2650 
          'generics' => [
2651 
          ],
2652 
          'is_floating_block' => 1,
2653 
          'mask' => {
2654 
            'Block_Handle' => 26.0009765625,
2655 
            'Block_handle' => 26.0009765625,
2656 
            'MDL_Handle' => 3.0009765625,
2657 
            'MDL_handle' => 3.0009765625,
2658 
            'arith_type' => 2,
2659 
            'bin_pt' => 0,
2660 
            'block_config' => 'sysgen_blockset:fromreg_config',
2661 
            'block_handle' => 26.0009765625,
2662 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2663 
            'block_type' => 'fromreg',
2664 
            'dbl_ovrd' => 0,
2665 
            'init' => 0,
2666 
            'init_bit_vector' => '0b',
2667 
            'mdl_handle' => 3.0009765625,
2668 
            'model_handle' => 3.0009765625,
2669 
            'n_bits' => 1,
2670 
            'ownership' => 2,
2671 
            'period' => '8e-009',
2672 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2673 
            'shared_memory_name' => 'register12rv',
2674 
          },
2675 
          'needs_vhdl_wrapper' => 0,
2676 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2677 
        },
2678 
        'entityName' => 'x_x77',
2679 
        'ports' => {
2680 
          'data_out' => {
2681 
            'attributes' => {
2682 
              'bin_pt' => 0,
2683 
              'is_floating_block' => 1,
2684 
              'must_be_hdl_vector' => 1,
2685 
              'period' => 1,
2686 
              'port_id' => 0,
2687 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
2688 
              'type' => 'UFix_1_0',
2689 
            },
2690 
            'direction' => 'out',
2691 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2692 
            'width' => 1,
2693 
          },
2694 
        },
2695 
      },
2696 
      'entityName' => 'x_x77',
2697 
    },
2698 
    'from_register25' => {
2699 
      'connections' => {
2700 
        'data_out' => 'from_register25.data_out',
2701 
      },
2702 
      'entity' => {
2703 
        'attributes' => {
2704 
          'entityAlreadyNetlisted' => 1,
2705 
          'generics' => [
2706 
          ],
2707 
          'is_floating_block' => 1,
2708 
          'mask' => {
2709 
            'Block_Handle' => 27.0009765625,
2710 
            'Block_handle' => 27.0009765625,
2711 
            'MDL_Handle' => 3.0009765625,
2712 
            'MDL_handle' => 3.0009765625,
2713 
            'arith_type' => 2,
2714 
            'bin_pt' => 0,
2715 
            'block_config' => 'sysgen_blockset:fromreg_config',
2716 
            'block_handle' => 27.0009765625,
2717 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2718 
            'block_type' => 'fromreg',
2719 
            'dbl_ovrd' => 0,
2720 
            'init' => 0,
2721 
            'init_bit_vector' => '00000000000000000000000000000000b',
2722 
            'mdl_handle' => 3.0009765625,
2723 
            'model_handle' => 3.0009765625,
2724 
            'n_bits' => 32,
2725 
            'ownership' => 2,
2726 
            'period' => '8e-009',
2727 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2728 
            'shared_memory_name' => 'register13rd',
2729 
          },
2730 
          'needs_vhdl_wrapper' => 0,
2731 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2732 
        },
2733 
        'entityName' => 'x_x78',
2734 
        'ports' => {
2735 
          'data_out' => {
2736 
            'attributes' => {
2737 
              'bin_pt' => 0,
2738 
              'is_floating_block' => 1,
2739 
              'must_be_hdl_vector' => 1,
2740 
              'period' => 1,
2741 
              'port_id' => 0,
2742 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
2743 
              'type' => 'UFix_32_0',
2744 
            },
2745 
            'direction' => 'out',
2746 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2747 
            'width' => 32,
2748 
          },
2749 
        },
2750 
      },
2751 
      'entityName' => 'x_x78',
2752 
    },
2753 
    'from_register26' => {
2754 
      'connections' => {
2755 
        'data_out' => 'from_register26.data_out',
2756 
      },
2757 
      'entity' => {
2758 
        'attributes' => {
2759 
          'entityAlreadyNetlisted' => 1,
2760 
          'generics' => [
2761 
          ],
2762 
          'is_floating_block' => 1,
2763 
          'mask' => {
2764 
            'Block_Handle' => 28.0009765625,
2765 
            'Block_handle' => 28.0009765625,
2766 
            'MDL_Handle' => 3.0009765625,
2767 
            'MDL_handle' => 3.0009765625,
2768 
            'arith_type' => 2,
2769 
            'bin_pt' => 0,
2770 
            'block_config' => 'sysgen_blockset:fromreg_config',
2771 
            'block_handle' => 28.0009765625,
2772 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2773 
            'block_type' => 'fromreg',
2774 
            'dbl_ovrd' => 0,
2775 
            'init' => 0,
2776 
            'init_bit_vector' => '0b',
2777 
            'mdl_handle' => 3.0009765625,
2778 
            'model_handle' => 3.0009765625,
2779 
            'n_bits' => 1,
2780 
            'ownership' => 2,
2781 
            'period' => '8e-009',
2782 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2783 
            'shared_memory_name' => 'register13rv',
2784 
          },
2785 
          'needs_vhdl_wrapper' => 0,
2786 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2787 
        },
2788 
        'entityName' => 'x_x79',
2789 
        'ports' => {
2790 
          'data_out' => {
2791 
            'attributes' => {
2792 
              'bin_pt' => 0,
2793 
              'is_floating_block' => 1,
2794 
              'must_be_hdl_vector' => 1,
2795 
              'period' => 1,
2796 
              'port_id' => 0,
2797 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
2798 
              'type' => 'UFix_1_0',
2799 
            },
2800 
            'direction' => 'out',
2801 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2802 
            'width' => 1,
2803 
          },
2804 
        },
2805 
      },
2806 
      'entityName' => 'x_x79',
2807 
    },
2808 
    'from_register27' => {
2809 
      'connections' => {
2810 
        'data_out' => 'from_register27.data_out',
2811 
      },
2812 
      'entity' => {
2813 
        'attributes' => {
2814 
          'entityAlreadyNetlisted' => 1,
2815 
          'generics' => [
2816 
          ],
2817 
          'is_floating_block' => 1,
2818 
          'mask' => {
2819 
            'Block_Handle' => 29.0009765625,
2820 
            'Block_handle' => 29.0009765625,
2821 
            'MDL_Handle' => 3.0009765625,
2822 
            'MDL_handle' => 3.0009765625,
2823 
            'arith_type' => 2,
2824 
            'bin_pt' => 0,
2825 
            'block_config' => 'sysgen_blockset:fromreg_config',
2826 
            'block_handle' => 29.0009765625,
2827 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2828 
            'block_type' => 'fromreg',
2829 
            'dbl_ovrd' => 0,
2830 
            'init' => 0,
2831 
            'init_bit_vector' => '00000000000000000000000000000000b',
2832 
            'mdl_handle' => 3.0009765625,
2833 
            'model_handle' => 3.0009765625,
2834 
            'n_bits' => 32,
2835 
            'ownership' => 2,
2836 
            'period' => '8e-009',
2837 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2838 
            'shared_memory_name' => 'register14rd',
2839 
          },
2840 
          'needs_vhdl_wrapper' => 0,
2841 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2842 
        },
2843 
        'entityName' => 'x_x80',
2844 
        'ports' => {
2845 
          'data_out' => {
2846 
            'attributes' => {
2847 
              'bin_pt' => 0,
2848 
              'is_floating_block' => 1,
2849 
              'must_be_hdl_vector' => 1,
2850 
              'period' => 1,
2851 
              'port_id' => 0,
2852 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
2853 
              'type' => 'UFix_32_0',
2854 
            },
2855 
            'direction' => 'out',
2856 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2857 
            'width' => 32,
2858 
          },
2859 
        },
2860 
      },
2861 
      'entityName' => 'x_x80',
2862 
    },
2863 
    'from_register28' => {
2864 
      'connections' => {
2865 
        'data_out' => 'from_register28.data_out',
2866 
      },
2867 
      'entity' => {
2868 
        'attributes' => {
2869 
          'entityAlreadyNetlisted' => 1,
2870 
          'generics' => [
2871 
          ],
2872 
          'is_floating_block' => 1,
2873 
          'mask' => {
2874 
            'Block_Handle' => 30.0009765625,
2875 
            'Block_handle' => 30.0009765625,
2876 
            'MDL_Handle' => 3.0009765625,
2877 
            'MDL_handle' => 3.0009765625,
2878 
            'arith_type' => 2,
2879 
            'bin_pt' => 0,
2880 
            'block_config' => 'sysgen_blockset:fromreg_config',
2881 
            'block_handle' => 30.0009765625,
2882 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2883 
            'block_type' => 'fromreg',
2884 
            'dbl_ovrd' => 0,
2885 
            'init' => 0,
2886 
            'init_bit_vector' => '0b',
2887 
            'mdl_handle' => 3.0009765625,
2888 
            'model_handle' => 3.0009765625,
2889 
            'n_bits' => 1,
2890 
            'ownership' => 2,
2891 
            'period' => '8e-009',
2892 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2893 
            'shared_memory_name' => 'register14rv',
2894 
          },
2895 
          'needs_vhdl_wrapper' => 0,
2896 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2897 
        },
2898 
        'entityName' => 'x_x81',
2899 
        'ports' => {
2900 
          'data_out' => {
2901 
            'attributes' => {
2902 
              'bin_pt' => 0,
2903 
              'is_floating_block' => 1,
2904 
              'must_be_hdl_vector' => 1,
2905 
              'period' => 1,
2906 
              'port_id' => 0,
2907 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
2908 
              'type' => 'UFix_1_0',
2909 
            },
2910 
            'direction' => 'out',
2911 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2912 
            'width' => 1,
2913 
          },
2914 
        },
2915 
      },
2916 
      'entityName' => 'x_x81',
2917 
    },
2918 
    'from_register3' => {
2919 
      'connections' => {
2920 
        'data_out' => 'from_register3.data_out',
2921 
      },
2922 
      'entity' => {
2923 
        'attributes' => {
2924 
          'entityAlreadyNetlisted' => 1,
2925 
          'generics' => [
2926 
          ],
2927 
          'is_floating_block' => 1,
2928 
          'mask' => {
2929 
            'Block_Handle' => 31.0009765625,
2930 
            'Block_handle' => 31.0009765625,
2931 
            'MDL_Handle' => 3.0009765625,
2932 
            'MDL_handle' => 3.0009765625,
2933 
            'arith_type' => 2,
2934 
            'bin_pt' => 0,
2935 
            'block_config' => 'sysgen_blockset:fromreg_config',
2936 
            'block_handle' => 31.0009765625,
2937 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2938 
            'block_type' => 'fromreg',
2939 
            'dbl_ovrd' => 0,
2940 
            'init' => 0,
2941 
            'init_bit_vector' => '00000000000000000000000000000000b',
2942 
            'mdl_handle' => 3.0009765625,
2943 
            'model_handle' => 3.0009765625,
2944 
            'n_bits' => 32,
2945 
            'ownership' => 2,
2946 
            'period' => '8e-009',
2947 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2948 
            'shared_memory_name' => 'register01rd',
2949 
          },
2950 
          'needs_vhdl_wrapper' => 0,
2951 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2952 
        },
2953 
        'entityName' => 'x_x82',
2954 
        'ports' => {
2955 
          'data_out' => {
2956 
            'attributes' => {
2957 
              'bin_pt' => 0,
2958 
              'is_floating_block' => 1,
2959 
              'must_be_hdl_vector' => 1,
2960 
              'period' => 1,
2961 
              'port_id' => 0,
2962 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
2963 
              'type' => 'UFix_32_0',
2964 
            },
2965 
            'direction' => 'out',
2966 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2967 
            'width' => 32,
2968 
          },
2969 
        },
2970 
      },
2971 
      'entityName' => 'x_x82',
2972 
    },
2973 
    'from_register4' => {
2974 
      'connections' => {
2975 
        'data_out' => 'from_register4.data_out',
2976 
      },
2977 
      'entity' => {
2978 
        'attributes' => {
2979 
          'entityAlreadyNetlisted' => 1,
2980 
          'generics' => [
2981 
          ],
2982 
          'is_floating_block' => 1,
2983 
          'mask' => {
2984 
            'Block_Handle' => 32.0009765625,
2985 
            'Block_handle' => 32.0009765625,
2986 
            'MDL_Handle' => 3.0009765625,
2987 
            'MDL_handle' => 3.0009765625,
2988 
            'arith_type' => 2,
2989 
            'bin_pt' => 0,
2990 
            'block_config' => 'sysgen_blockset:fromreg_config',
2991 
            'block_handle' => 32.0009765625,
2992 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
2993 
            'block_type' => 'fromreg',
2994 
            'dbl_ovrd' => 0,
2995 
            'init' => 0,
2996 
            'init_bit_vector' => '0b',
2997 
            'mdl_handle' => 3.0009765625,
2998 
            'model_handle' => 3.0009765625,
2999 
            'n_bits' => 1,
3000 
            'ownership' => 2,
3001 
            'period' => '8e-009',
3002 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3003 
            'shared_memory_name' => 'register04rv',
3004 
          },
3005 
          'needs_vhdl_wrapper' => 0,
3006 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
3007 
        },
3008 
        'entityName' => 'x_x83',
3009 
        'ports' => {
3010 
          'data_out' => {
3011 
            'attributes' => {
3012 
              'bin_pt' => 0,
3013 
              'is_floating_block' => 1,
3014 
              'must_be_hdl_vector' => 1,
3015 
              'period' => 1,
3016 
              'port_id' => 0,
3017 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
3018 
              'type' => 'UFix_1_0',
3019 
            },
3020 
            'direction' => 'out',
3021 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3022 
            'width' => 1,
3023 
          },
3024 
        },
3025 
      },
3026 
      'entityName' => 'x_x83',
3027 
    },
3028 
    'from_register5' => {
3029 
      'connections' => {
3030 
        'data_out' => 'from_register5.data_out',
3031 
      },
3032 
      'entity' => {
3033 
        'attributes' => {
3034 
          'entityAlreadyNetlisted' => 1,
3035 
          'generics' => [
3036 
          ],
3037 
          'is_floating_block' => 1,
3038 
          'mask' => {
3039 
            'Block_Handle' => 33.0009765625,
3040 
            'Block_handle' => 33.0009765625,
3041 
            'MDL_Handle' => 3.0009765625,
3042 
            'MDL_handle' => 3.0009765625,
3043 
            'arith_type' => 2,
3044 
            'bin_pt' => 0,
3045 
            'block_config' => 'sysgen_blockset:fromreg_config',
3046 
            'block_handle' => 33.0009765625,
3047 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
3048 
            'block_type' => 'fromreg',
3049 
            'dbl_ovrd' => 0,
3050 
            'init' => 0,
3051 
            'init_bit_vector' => '00000000000000000000000000000000b',
3052 
            'mdl_handle' => 3.0009765625,
3053 
            'model_handle' => 3.0009765625,
3054 
            'n_bits' => 32,
3055 
            'ownership' => 2,
3056 
            'period' => '8e-009',
3057 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3058 
            'shared_memory_name' => 'register02rd',
3059 
          },
3060 
          'needs_vhdl_wrapper' => 0,
3061 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
3062 
        },
3063 
        'entityName' => 'x_x84',
3064 
        'ports' => {
3065 
          'data_out' => {
3066 
            'attributes' => {
3067 
              'bin_pt' => 0,
3068 
              'is_floating_block' => 1,
3069 
              'must_be_hdl_vector' => 1,
3070 
              'period' => 1,
3071 
              'port_id' => 0,
3072 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
3073 
              'type' => 'UFix_32_0',
3074 
            },
3075 
            'direction' => 'out',
3076 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3077 
            'width' => 32,
3078 
          },
3079 
        },
3080 
      },
3081 
      'entityName' => 'x_x84',
3082 
    },
3083 
    'from_register6' => {
3084 
      'connections' => {
3085 
        'data_out' => 'from_register6.data_out',
3086 
      },
3087 
      'entity' => {
3088 
        'attributes' => {
3089 
          'entityAlreadyNetlisted' => 1,
3090 
          'generics' => [
3091 
          ],
3092 
          'is_floating_block' => 1,
3093 
          'mask' => {
3094 
            'Block_Handle' => 34.0009765625,
3095 
            'Block_handle' => 34.0009765625,
3096 
            'MDL_Handle' => 3.0009765625,
3097 
            'MDL_handle' => 3.0009765625,
3098 
            'arith_type' => 2,
3099 
            'bin_pt' => 0,
3100 
            'block_config' => 'sysgen_blockset:fromreg_config',
3101 
            'block_handle' => 34.0009765625,
3102 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3103 
            'block_type' => 'fromreg',
3104 
            'dbl_ovrd' => 0,
3105 
            'init' => 0,
3106 
            'init_bit_vector' => '0b',
3107 
            'mdl_handle' => 3.0009765625,
3108 
            'model_handle' => 3.0009765625,
3109 
            'n_bits' => 1,
3110 
            'ownership' => 2,
3111 
            'period' => '8e-009',
3112 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3113 
            'shared_memory_name' => 'register03rv',
3114 
          },
3115 
          'needs_vhdl_wrapper' => 0,
3116 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3117 
        },
3118 
        'entityName' => 'x_x85',
3119 
        'ports' => {
3120 
          'data_out' => {
3121 
            'attributes' => {
3122 
              'bin_pt' => 0,
3123 
              'is_floating_block' => 1,
3124 
              'must_be_hdl_vector' => 1,
3125 
              'period' => 1,
3126 
              'port_id' => 0,
3127 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
3128 
              'type' => 'UFix_1_0',
3129 
            },
3130 
            'direction' => 'out',
3131 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3132 
            'width' => 1,
3133 
          },
3134 
        },
3135 
      },
3136 
      'entityName' => 'x_x85',
3137 
    },
3138 
    'from_register7' => {
3139 
      'connections' => {
3140 
        'data_out' => 'from_register7.data_out',
3141 
      },
3142 
      'entity' => {
3143 
        'attributes' => {
3144 
          'entityAlreadyNetlisted' => 1,
3145 
          'generics' => [
3146 
          ],
3147 
          'is_floating_block' => 1,
3148 
          'mask' => {
3149 
            'Block_Handle' => 35.0009765625,
3150 
            'Block_handle' => 35.0009765625,
3151 
            'MDL_Handle' => 3.0009765625,
3152 
            'MDL_handle' => 3.0009765625,
3153 
            'arith_type' => 2,
3154 
            'bin_pt' => 0,
3155 
            'block_config' => 'sysgen_blockset:fromreg_config',
3156 
            'block_handle' => 35.0009765625,
3157 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3158 
            'block_type' => 'fromreg',
3159 
            'dbl_ovrd' => 0,
3160 
            'init' => 0,
3161 
            'init_bit_vector' => '00000000000000000000000000000000b',
3162 
            'mdl_handle' => 3.0009765625,
3163 
            'model_handle' => 3.0009765625,
3164 
            'n_bits' => 32,
3165 
            'ownership' => 2,
3166 
            'period' => '8e-009',
3167 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3168 
            'shared_memory_name' => 'register03rd',
3169 
          },
3170 
          'needs_vhdl_wrapper' => 0,
3171 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3172 
        },
3173 
        'entityName' => 'x_x86',
3174 
        'ports' => {
3175 
          'data_out' => {
3176 
            'attributes' => {
3177 
              'bin_pt' => 0,
3178 
              'is_floating_block' => 1,
3179 
              'must_be_hdl_vector' => 1,
3180 
              'period' => 1,
3181 
              'port_id' => 0,
3182 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
3183 
              'type' => 'UFix_32_0',
3184 
            },
3185 
            'direction' => 'out',
3186 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3187 
            'width' => 32,
3188 
          },
3189 
        },
3190 
      },
3191 
      'entityName' => 'x_x86',
3192 
    },
3193 
    'from_register8' => {
3194 
      'connections' => {
3195 
        'data_out' => 'from_register8.data_out',
3196 
      },
3197 
      'entity' => {
3198 
        'attributes' => {
3199 
          'entityAlreadyNetlisted' => 1,
3200 
          'generics' => [
3201 
          ],
3202 
          'is_floating_block' => 1,
3203 
          'mask' => {
3204 
            'Block_Handle' => 36.0009765625,
3205 
            'Block_handle' => 36.0009765625,
3206 
            'MDL_Handle' => 3.0009765625,
3207 
            'MDL_handle' => 3.0009765625,
3208 
            'arith_type' => 2,
3209 
            'bin_pt' => 0,
3210 
            'block_config' => 'sysgen_blockset:fromreg_config',
3211 
            'block_handle' => 36.0009765625,
3212 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3213 
            'block_type' => 'fromreg',
3214 
            'dbl_ovrd' => 0,
3215 
            'init' => 0,
3216 
            'init_bit_vector' => '00000000000000000000000000000000b',
3217 
            'mdl_handle' => 3.0009765625,
3218 
            'model_handle' => 3.0009765625,
3219 
            'n_bits' => 32,
3220 
            'ownership' => 2,
3221 
            'period' => '8e-009',
3222 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3223 
            'shared_memory_name' => 'register04rd',
3224 
          },
3225 
          'needs_vhdl_wrapper' => 0,
3226 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3227 
        },
3228 
        'entityName' => 'x_x87',
3229 
        'ports' => {
3230 
          'data_out' => {
3231 
            'attributes' => {
3232 
              'bin_pt' => 0,
3233 
              'is_floating_block' => 1,
3234 
              'must_be_hdl_vector' => 1,
3235 
              'period' => 1,
3236 
              'port_id' => 0,
3237 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
3238 
              'type' => 'UFix_32_0',
3239 
            },
3240 
            'direction' => 'out',
3241 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3242 
            'width' => 32,
3243 
          },
3244 
        },
3245 
      },
3246 
      'entityName' => 'x_x87',
3247 
    },
3248 
    'from_register9' => {
3249 
      'connections' => {
3250 
        'data_out' => 'from_register9.data_out',
3251 
      },
3252 
      'entity' => {
3253 
        'attributes' => {
3254 
          'entityAlreadyNetlisted' => 1,
3255 
          'generics' => [
3256 
          ],
3257 
          'is_floating_block' => 1,
3258 
          'mask' => {
3259 
            'Block_Handle' => 37.0009765625,
3260 
            'Block_handle' => 37.0009765625,
3261 
            'MDL_Handle' => 3.0009765625,
3262 
            'MDL_handle' => 3.0009765625,
3263 
            'arith_type' => 2,
3264 
            'bin_pt' => 0,
3265 
            'block_config' => 'sysgen_blockset:fromreg_config',
3266 
            'block_handle' => 37.0009765625,
3267 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3268 
            'block_type' => 'fromreg',
3269 
            'dbl_ovrd' => 0,
3270 
            'init' => 0,
3271 
            'init_bit_vector' => '0b',
3272 
            'mdl_handle' => 3.0009765625,
3273 
            'model_handle' => 3.0009765625,
3274 
            'n_bits' => 1,
3275 
            'ownership' => 2,
3276 
            'period' => '8e-009',
3277 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3278 
            'shared_memory_name' => 'register05rv',
3279 
          },
3280 
          'needs_vhdl_wrapper' => 0,
3281 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3282 
        },
3283 
        'entityName' => 'x_x88',
3284 
        'ports' => {
3285 
          'data_out' => {
3286 
            'attributes' => {
3287 
              'bin_pt' => 0,
3288 
              'is_floating_block' => 1,
3289 
              'must_be_hdl_vector' => 1,
3290 
              'period' => 1,
3291 
              'port_id' => 0,
3292 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
3293 
              'type' => 'UFix_1_0',
3294 
            },
3295 
            'direction' => 'out',
3296 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3297 
            'width' => 1,
3298 
          },
3299 
        },
3300 
      },
3301 
      'entityName' => 'x_x88',
3302 
    },
3303 
    'reg01_rd' => {
3304 
      'connections' => {
3305 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
3306 
      },
3307 
      'entity' => {
3308 
        'attributes' => {
3309 
          'entityAlreadyNetlisted' => 1,
3310 
          'isGateway' => 1,
3311 
          'is_floating_block' => 1,
3312 
        },
3313 
        'entityName' => 'reg01_rd',
3314 
        'ports' => {
3315 
          'reg01_rd' => {
3316 
            'attributes' => {
3317 
              'bin_pt' => 0,
3318 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
3319 
              'is_floating_block' => 1,
3320 
              'is_gateway_port' => 1,
3321 
              'must_be_hdl_vector' => 1,
3322 
              'period' => 1,
3323 
              'port_id' => 0,
3324 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
3325 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
3326 
              'timingConstraint' => 'none',
3327 
              'type' => 'UFix_32_0',
3328 
            },
3329 
            'direction' => 'in',
3330 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3331 
            'width' => 32,
3332 
          },
3333 
        },
3334 
      },
3335 
      'entityName' => 'reg01_rd',
3336 
    },
3337 
    'reg01_rv' => {
3338 
      'connections' => {
3339 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
3340 
      },
3341 
      'entity' => {
3342 
        'attributes' => {
3343 
          'entityAlreadyNetlisted' => 1,
3344 
          'isGateway' => 1,
3345 
          'is_floating_block' => 1,
3346 
        },
3347 
        'entityName' => 'reg01_rv',
3348 
        'ports' => {
3349 
          'reg01_rv' => {
3350 
            'attributes' => {
3351 
              'bin_pt' => 0,
3352 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
3353 
              'is_floating_block' => 1,
3354 
              'is_gateway_port' => 1,
3355 
              'must_be_hdl_vector' => 1,
3356 
              'period' => 1,
3357 
              'port_id' => 0,
3358 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
3359 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
3360 
              'timingConstraint' => 'none',
3361 
              'type' => 'UFix_1_0',
3362 
            },
3363 
            'direction' => 'in',
3364 
            'hdlType' => 'std_logic',
3365 
            'width' => 1,
3366 
          },
3367 
        },
3368 
      },
3369 
      'entityName' => 'reg01_rv',
3370 
    },
3371 
    'reg01_td' => {
3372 
      'connections' => {
3373 
        'reg01_td' => '.reg01_td',
3374 
      },
3375 
      'entity' => {
3376 
        'attributes' => {
3377 
          'entityAlreadyNetlisted' => 1,
3378 
          'isGateway' => 1,
3379 
          'is_floating_block' => 1,
3380 
        },
3381 
        'entityName' => 'reg01_td',
3382 
        'ports' => {
3383 
          'reg01_td' => {
3384 
            'attributes' => {
3385 
              'bin_pt' => 0,
3386 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
3387 
              'is_floating_block' => 1,
3388 
              'is_gateway_port' => 1,
3389 
              'must_be_hdl_vector' => 1,
3390 
              'period' => 1,
3391 
              'port_id' => 0,
3392 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
3393 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
3394 
              'timingConstraint' => 'none',
3395 
              'type' => 'UFix_32_0',
3396 
            },
3397 
            'direction' => 'out',
3398 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3399 
            'width' => 32,
3400 
          },
3401 
        },
3402 
      },
3403 
      'entityName' => 'reg01_td',
3404 
    },
3405 
    'reg01_tv' => {
3406 
      'connections' => {
3407 
        'reg01_tv' => '.reg01_tv',
3408 
      },
3409 
      'entity' => {
3410 
        'attributes' => {
3411 
          'entityAlreadyNetlisted' => 1,
3412 
          'isGateway' => 1,
3413 
          'is_floating_block' => 1,
3414 
        },
3415 
        'entityName' => 'reg01_tv',
3416 
        'ports' => {
3417 
          'reg01_tv' => {
3418 
            'attributes' => {
3419 
              'bin_pt' => 0,
3420 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
3421 
              'is_floating_block' => 1,
3422 
              'is_gateway_port' => 1,
3423 
              'must_be_hdl_vector' => 1,
3424 
              'period' => 1,
3425 
              'port_id' => 0,
3426 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
3427 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
3428 
              'timingConstraint' => 'none',
3429 
              'type' => 'Bool',
3430 
            },
3431 
            'direction' => 'out',
3432 
            'hdlType' => 'std_logic',
3433 
            'width' => 1,
3434 
          },
3435 
        },
3436 
      },
3437 
      'entityName' => 'reg01_tv',
3438 
    },
3439 
    'reg02_rd' => {
3440 
      'connections' => {
3441 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
3442 
      },
3443 
      'entity' => {
3444 
        'attributes' => {
3445 
          'entityAlreadyNetlisted' => 1,
3446 
          'isGateway' => 1,
3447 
          'is_floating_block' => 1,
3448 
        },
3449 
        'entityName' => 'reg02_rd',
3450 
        'ports' => {
3451 
          'reg02_rd' => {
3452 
            'attributes' => {
3453 
              'bin_pt' => 0,
3454 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
3455 
              'is_floating_block' => 1,
3456 
              'is_gateway_port' => 1,
3457 
              'must_be_hdl_vector' => 1,
3458 
              'period' => 1,
3459 
              'port_id' => 0,
3460 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
3461 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
3462 
              'timingConstraint' => 'none',
3463 
              'type' => 'UFix_32_0',
3464 
            },
3465 
            'direction' => 'in',
3466 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3467 
            'width' => 32,
3468 
          },
3469 
        },
3470 
      },
3471 
      'entityName' => 'reg02_rd',
3472 
    },
3473 
    'reg02_rv' => {
3474 
      'connections' => {
3475 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
3476 
      },
3477 
      'entity' => {
3478 
        'attributes' => {
3479 
          'entityAlreadyNetlisted' => 1,
3480 
          'isGateway' => 1,
3481 
          'is_floating_block' => 1,
3482 
        },
3483 
        'entityName' => 'reg02_rv',
3484 
        'ports' => {
3485 
          'reg02_rv' => {
3486 
            'attributes' => {
3487 
              'bin_pt' => 0,
3488 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
3489 
              'is_floating_block' => 1,
3490 
              'is_gateway_port' => 1,
3491 
              'must_be_hdl_vector' => 1,
3492 
              'period' => 1,
3493 
              'port_id' => 0,
3494 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
3495 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
3496 
              'timingConstraint' => 'none',
3497 
              'type' => 'UFix_1_0',
3498 
            },
3499 
            'direction' => 'in',
3500 
            'hdlType' => 'std_logic',
3501 
            'width' => 1,
3502 
          },
3503 
        },
3504 
      },
3505 
      'entityName' => 'reg02_rv',
3506 
    },
3507 
    'reg02_td' => {
3508 
      'connections' => {
3509 
        'reg02_td' => '.reg02_td',
3510 
      },
3511 
      'entity' => {
3512 
        'attributes' => {
3513 
          'entityAlreadyNetlisted' => 1,
3514 
          'isGateway' => 1,
3515 
          'is_floating_block' => 1,
3516 
        },
3517 
        'entityName' => 'reg02_td',
3518 
        'ports' => {
3519 
          'reg02_td' => {
3520 
            'attributes' => {
3521 
              'bin_pt' => 0,
3522 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
3523 
              'is_floating_block' => 1,
3524 
              'is_gateway_port' => 1,
3525 
              'must_be_hdl_vector' => 1,
3526 
              'period' => 1,
3527 
              'port_id' => 0,
3528 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
3529 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
3530 
              'timingConstraint' => 'none',
3531 
              'type' => 'UFix_32_0',
3532 
            },
3533 
            'direction' => 'out',
3534 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3535 
            'width' => 32,
3536 
          },
3537 
        },
3538 
      },
3539 
      'entityName' => 'reg02_td',
3540 
    },
3541 
    'reg02_tv' => {
3542 
      'connections' => {
3543 
        'reg02_tv' => '.reg02_tv',
3544 
      },
3545 
      'entity' => {
3546 
        'attributes' => {
3547 
          'entityAlreadyNetlisted' => 1,
3548 
          'isGateway' => 1,
3549 
          'is_floating_block' => 1,
3550 
        },
3551 
        'entityName' => 'reg02_tv',
3552 
        'ports' => {
3553 
          'reg02_tv' => {
3554 
            'attributes' => {
3555 
              'bin_pt' => 0,
3556 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
3557 
              'is_floating_block' => 1,
3558 
              'is_gateway_port' => 1,
3559 
              'must_be_hdl_vector' => 1,
3560 
              'period' => 1,
3561 
              'port_id' => 0,
3562 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
3563 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
3564 
              'timingConstraint' => 'none',
3565 
              'type' => 'Bool',
3566 
            },
3567 
            'direction' => 'out',
3568 
            'hdlType' => 'std_logic',
3569 
            'width' => 1,
3570 
          },
3571 
        },
3572 
      },
3573 
      'entityName' => 'reg02_tv',
3574 
    },
3575 
    'reg03_rd' => {
3576 
      'connections' => {
3577 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
3578 
      },
3579 
      'entity' => {
3580 
        'attributes' => {
3581 
          'entityAlreadyNetlisted' => 1,
3582 
          'isGateway' => 1,
3583 
          'is_floating_block' => 1,
3584 
        },
3585 
        'entityName' => 'reg03_rd',
3586 
        'ports' => {
3587 
          'reg03_rd' => {
3588 
            'attributes' => {
3589 
              'bin_pt' => 0,
3590 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
3591 
              'is_floating_block' => 1,
3592 
              'is_gateway_port' => 1,
3593 
              'must_be_hdl_vector' => 1,
3594 
              'period' => 1,
3595 
              'port_id' => 0,
3596 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
3597 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
3598 
              'timingConstraint' => 'none',
3599 
              'type' => 'UFix_32_0',
3600 
            },
3601 
            'direction' => 'in',
3602 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3603 
            'width' => 32,
3604 
          },
3605 
        },
3606 
      },
3607 
      'entityName' => 'reg03_rd',
3608 
    },
3609 
    'reg03_rv' => {
3610 
      'connections' => {
3611 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
3612 
      },
3613 
      'entity' => {
3614 
        'attributes' => {
3615 
          'entityAlreadyNetlisted' => 1,
3616 
          'isGateway' => 1,
3617 
          'is_floating_block' => 1,
3618 
        },
3619 
        'entityName' => 'reg03_rv',
3620 
        'ports' => {
3621 
          'reg03_rv' => {
3622 
            'attributes' => {
3623 
              'bin_pt' => 0,
3624 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
3625 
              'is_floating_block' => 1,
3626 
              'is_gateway_port' => 1,
3627 
              'must_be_hdl_vector' => 1,
3628 
              'period' => 1,
3629 
              'port_id' => 0,
3630 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
3631 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
3632 
              'timingConstraint' => 'none',
3633 
              'type' => 'UFix_1_0',
3634 
            },
3635 
            'direction' => 'in',
3636 
            'hdlType' => 'std_logic',
3637 
            'width' => 1,
3638 
          },
3639 
        },
3640 
      },
3641 
      'entityName' => 'reg03_rv',
3642 
    },
3643 
    'reg03_td' => {
3644 
      'connections' => {
3645 
        'reg03_td' => '.reg03_td',
3646 
      },
3647 
      'entity' => {
3648 
        'attributes' => {
3649 
          'entityAlreadyNetlisted' => 1,
3650 
          'isGateway' => 1,
3651 
          'is_floating_block' => 1,
3652 
        },
3653 
        'entityName' => 'reg03_td',
3654 
        'ports' => {
3655 
          'reg03_td' => {
3656 
            'attributes' => {
3657 
              'bin_pt' => 0,
3658 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
3659 
              'is_floating_block' => 1,
3660 
              'is_gateway_port' => 1,
3661 
              'must_be_hdl_vector' => 1,
3662 
              'period' => 1,
3663 
              'port_id' => 0,
3664 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
3665 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
3666 
              'timingConstraint' => 'none',
3667 
              'type' => 'UFix_32_0',
3668 
            },
3669 
            'direction' => 'out',
3670 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3671 
            'width' => 32,
3672 
          },
3673 
        },
3674 
      },
3675 
      'entityName' => 'reg03_td',
3676 
    },
3677 
    'reg03_tv' => {
3678 
      'connections' => {
3679 
        'reg03_tv' => '.reg03_tv',
3680 
      },
3681 
      'entity' => {
3682 
        'attributes' => {
3683 
          'entityAlreadyNetlisted' => 1,
3684 
          'isGateway' => 1,
3685 
          'is_floating_block' => 1,
3686 
        },
3687 
        'entityName' => 'reg03_tv',
3688 
        'ports' => {
3689 
          'reg03_tv' => {
3690 
            'attributes' => {
3691 
              'bin_pt' => 0,
3692 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
3693 
              'is_floating_block' => 1,
3694 
              'is_gateway_port' => 1,
3695 
              'must_be_hdl_vector' => 1,
3696 
              'period' => 1,
3697 
              'port_id' => 0,
3698 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
3699 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
3700 
              'timingConstraint' => 'none',
3701 
              'type' => 'Bool',
3702 
            },
3703 
            'direction' => 'out',
3704 
            'hdlType' => 'std_logic',
3705 
            'width' => 1,
3706 
          },
3707 
        },
3708 
      },
3709 
      'entityName' => 'reg03_tv',
3710 
    },
3711 
    'reg04_rd' => {
3712 
      'connections' => {
3713 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
3714 
      },
3715 
      'entity' => {
3716 
        'attributes' => {
3717 
          'entityAlreadyNetlisted' => 1,
3718 
          'isGateway' => 1,
3719 
          'is_floating_block' => 1,
3720 
        },
3721 
        'entityName' => 'reg04_rd',
3722 
        'ports' => {
3723 
          'reg04_rd' => {
3724 
            'attributes' => {
3725 
              'bin_pt' => 0,
3726 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
3727 
              'is_floating_block' => 1,
3728 
              'is_gateway_port' => 1,
3729 
              'must_be_hdl_vector' => 1,
3730 
              'period' => 1,
3731 
              'port_id' => 0,
3732 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
3733 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
3734 
              'timingConstraint' => 'none',
3735 
              'type' => 'UFix_32_0',
3736 
            },
3737 
            'direction' => 'in',
3738 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3739 
            'width' => 32,
3740 
          },
3741 
        },
3742 
      },
3743 
      'entityName' => 'reg04_rd',
3744 
    },
3745 
    'reg04_rv' => {
3746 
      'connections' => {
3747 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
3748 
      },
3749 
      'entity' => {
3750 
        'attributes' => {
3751 
          'entityAlreadyNetlisted' => 1,
3752 
          'isGateway' => 1,
3753 
          'is_floating_block' => 1,
3754 
        },
3755 
        'entityName' => 'reg04_rv',
3756 
        'ports' => {
3757 
          'reg04_rv' => {
3758 
            'attributes' => {
3759 
              'bin_pt' => 0,
3760 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
3761 
              'is_floating_block' => 1,
3762 
              'is_gateway_port' => 1,
3763 
              'must_be_hdl_vector' => 1,
3764 
              'period' => 1,
3765 
              'port_id' => 0,
3766 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
3767 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
3768 
              'timingConstraint' => 'none',
3769 
              'type' => 'UFix_1_0',
3770 
            },
3771 
            'direction' => 'in',
3772 
            'hdlType' => 'std_logic',
3773 
            'width' => 1,
3774 
          },
3775 
        },
3776 
      },
3777 
      'entityName' => 'reg04_rv',
3778 
    },
3779 
    'reg04_td' => {
3780 
      'connections' => {
3781 
        'reg04_td' => '.reg04_td',
3782 
      },
3783 
      'entity' => {
3784 
        'attributes' => {
3785 
          'entityAlreadyNetlisted' => 1,
3786 
          'isGateway' => 1,
3787 
          'is_floating_block' => 1,
3788 
        },
3789 
        'entityName' => 'reg04_td',
3790 
        'ports' => {
3791 
          'reg04_td' => {
3792 
            'attributes' => {
3793 
              'bin_pt' => 0,
3794 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
3795 
              'is_floating_block' => 1,
3796 
              'is_gateway_port' => 1,
3797 
              'must_be_hdl_vector' => 1,
3798 
              'period' => 1,
3799 
              'port_id' => 0,
3800 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
3801 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
3802 
              'timingConstraint' => 'none',
3803 
              'type' => 'UFix_32_0',
3804 
            },
3805 
            'direction' => 'out',
3806 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3807 
            'width' => 32,
3808 
          },
3809 
        },
3810 
      },
3811 
      'entityName' => 'reg04_td',
3812 
    },
3813 
    'reg04_tv' => {
3814 
      'connections' => {
3815 
        'reg04_tv' => '.reg04_tv',
3816 
      },
3817 
      'entity' => {
3818 
        'attributes' => {
3819 
          'entityAlreadyNetlisted' => 1,
3820 
          'isGateway' => 1,
3821 
          'is_floating_block' => 1,
3822 
        },
3823 
        'entityName' => 'reg04_tv',
3824 
        'ports' => {
3825 
          'reg04_tv' => {
3826 
            'attributes' => {
3827 
              'bin_pt' => 0,
3828 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
3829 
              'is_floating_block' => 1,
3830 
              'is_gateway_port' => 1,
3831 
              'must_be_hdl_vector' => 1,
3832 
              'period' => 1,
3833 
              'port_id' => 0,
3834 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
3835 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
3836 
              'timingConstraint' => 'none',
3837 
              'type' => 'Bool',
3838 
            },
3839 
            'direction' => 'out',
3840 
            'hdlType' => 'std_logic',
3841 
            'width' => 1,
3842 
          },
3843 
        },
3844 
      },
3845 
      'entityName' => 'reg04_tv',
3846 
    },
3847 
    'reg05_rd' => {
3848 
      'connections' => {
3849 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
3850 
      },
3851 
      'entity' => {
3852 
        'attributes' => {
3853 
          'entityAlreadyNetlisted' => 1,
3854 
          'isGateway' => 1,
3855 
          'is_floating_block' => 1,
3856 
        },
3857 
        'entityName' => 'reg05_rd',
3858 
        'ports' => {
3859 
          'reg05_rd' => {
3860 
            'attributes' => {
3861 
              'bin_pt' => 0,
3862 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
3863 
              'is_floating_block' => 1,
3864 
              'is_gateway_port' => 1,
3865 
              'must_be_hdl_vector' => 1,
3866 
              'period' => 1,
3867 
              'port_id' => 0,
3868 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
3869 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
3870 
              'timingConstraint' => 'none',
3871 
              'type' => 'UFix_32_0',
3872 
            },
3873 
            'direction' => 'in',
3874 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3875 
            'width' => 32,
3876 
          },
3877 
        },
3878 
      },
3879 
      'entityName' => 'reg05_rd',
3880 
    },
3881 
    'reg05_rv' => {
3882 
      'connections' => {
3883 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
3884 
      },
3885 
      'entity' => {
3886 
        'attributes' => {
3887 
          'entityAlreadyNetlisted' => 1,
3888 
          'isGateway' => 1,
3889 
          'is_floating_block' => 1,
3890 
        },
3891 
        'entityName' => 'reg05_rv',
3892 
        'ports' => {
3893 
          'reg05_rv' => {
3894 
            'attributes' => {
3895 
              'bin_pt' => 0,
3896 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
3897 
              'is_floating_block' => 1,
3898 
              'is_gateway_port' => 1,
3899 
              'must_be_hdl_vector' => 1,
3900 
              'period' => 1,
3901 
              'port_id' => 0,
3902 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
3903 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
3904 
              'timingConstraint' => 'none',
3905 
              'type' => 'UFix_1_0',
3906 
            },
3907 
            'direction' => 'in',
3908 
            'hdlType' => 'std_logic',
3909 
            'width' => 1,
3910 
          },
3911 
        },
3912 
      },
3913 
      'entityName' => 'reg05_rv',
3914 
    },
3915 
    'reg05_td' => {
3916 
      'connections' => {
3917 
        'reg05_td' => '.reg05_td',
3918 
      },
3919 
      'entity' => {
3920 
        'attributes' => {
3921 
          'entityAlreadyNetlisted' => 1,
3922 
          'isGateway' => 1,
3923 
          'is_floating_block' => 1,
3924 
        },
3925 
        'entityName' => 'reg05_td',
3926 
        'ports' => {
3927 
          'reg05_td' => {
3928 
            'attributes' => {
3929 
              'bin_pt' => 0,
3930 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
3931 
              'is_floating_block' => 1,
3932 
              'is_gateway_port' => 1,
3933 
              'must_be_hdl_vector' => 1,
3934 
              'period' => 1,
3935 
              'port_id' => 0,
3936 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
3937 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
3938 
              'timingConstraint' => 'none',
3939 
              'type' => 'UFix_32_0',
3940 
            },
3941 
            'direction' => 'out',
3942 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3943 
            'width' => 32,
3944 
          },
3945 
        },
3946 
      },
3947 
      'entityName' => 'reg05_td',
3948 
    },
3949 
    'reg05_tv' => {
3950 
      'connections' => {
3951 
        'reg05_tv' => '.reg05_tv',
3952 
      },
3953 
      'entity' => {
3954 
        'attributes' => {
3955 
          'entityAlreadyNetlisted' => 1,
3956 
          'isGateway' => 1,
3957 
          'is_floating_block' => 1,
3958 
        },
3959 
        'entityName' => 'reg05_tv',
3960 
        'ports' => {
3961 
          'reg05_tv' => {
3962 
            'attributes' => {
3963 
              'bin_pt' => 0,
3964 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
3965 
              'is_floating_block' => 1,
3966 
              'is_gateway_port' => 1,
3967 
              'must_be_hdl_vector' => 1,
3968 
              'period' => 1,
3969 
              'port_id' => 0,
3970 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
3971 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
3972 
              'timingConstraint' => 'none',
3973 
              'type' => 'Bool',
3974 
            },
3975 
            'direction' => 'out',
3976 
            'hdlType' => 'std_logic',
3977 
            'width' => 1,
3978 
          },
3979 
        },
3980 
      },
3981 
      'entityName' => 'reg05_tv',
3982 
    },
3983 
    'reg06_rd' => {
3984 
      'connections' => {
3985 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
3986 
      },
3987 
      'entity' => {
3988 
        'attributes' => {
3989 
          'entityAlreadyNetlisted' => 1,
3990 
          'isGateway' => 1,
3991 
          'is_floating_block' => 1,
3992 
        },
3993 
        'entityName' => 'reg06_rd',
3994 
        'ports' => {
3995 
          'reg06_rd' => {
3996 
            'attributes' => {
3997 
              'bin_pt' => 0,
3998 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
3999 
              'is_floating_block' => 1,
4000 
              'is_gateway_port' => 1,
4001 
              'must_be_hdl_vector' => 1,
4002 
              'period' => 1,
4003 
              'port_id' => 0,
4004 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
4005 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
4006 
              'timingConstraint' => 'none',
4007 
              'type' => 'UFix_32_0',
4008 
            },
4009 
            'direction' => 'in',
4010 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4011 
            'width' => 32,
4012 
          },
4013 
        },
4014 
      },
4015 
      'entityName' => 'reg06_rd',
4016 
    },
4017 
    'reg06_rv' => {
4018 
      'connections' => {
4019 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
4020 
      },
4021 
      'entity' => {
4022 
        'attributes' => {
4023 
          'entityAlreadyNetlisted' => 1,
4024 
          'isGateway' => 1,
4025 
          'is_floating_block' => 1,
4026 
        },
4027 
        'entityName' => 'reg06_rv',
4028 
        'ports' => {
4029 
          'reg06_rv' => {
4030 
            'attributes' => {
4031 
              'bin_pt' => 0,
4032 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
4033 
              'is_floating_block' => 1,
4034 
              'is_gateway_port' => 1,
4035 
              'must_be_hdl_vector' => 1,
4036 
              'period' => 1,
4037 
              'port_id' => 0,
4038 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
4039 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
4040 
              'timingConstraint' => 'none',
4041 
              'type' => 'UFix_1_0',
4042 
            },
4043 
            'direction' => 'in',
4044 
            'hdlType' => 'std_logic',
4045 
            'width' => 1,
4046 
          },
4047 
        },
4048 
      },
4049 
      'entityName' => 'reg06_rv',
4050 
    },
4051 
    'reg06_td' => {
4052 
      'connections' => {
4053 
        'reg06_td' => '.reg06_td',
4054 
      },
4055 
      'entity' => {
4056 
        'attributes' => {
4057 
          'entityAlreadyNetlisted' => 1,
4058 
          'isGateway' => 1,
4059 
          'is_floating_block' => 1,
4060 
        },
4061 
        'entityName' => 'reg06_td',
4062 
        'ports' => {
4063 
          'reg06_td' => {
4064 
            'attributes' => {
4065 
              'bin_pt' => 0,
4066 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
4067 
              'is_floating_block' => 1,
4068 
              'is_gateway_port' => 1,
4069 
              'must_be_hdl_vector' => 1,
4070 
              'period' => 1,
4071 
              'port_id' => 0,
4072 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
4073 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
4074 
              'timingConstraint' => 'none',
4075 
              'type' => 'UFix_32_0',
4076 
            },
4077 
            'direction' => 'out',
4078 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4079 
            'width' => 32,
4080 
          },
4081 
        },
4082 
      },
4083 
      'entityName' => 'reg06_td',
4084 
    },
4085 
    'reg06_tv' => {
4086 
      'connections' => {
4087 
        'reg06_tv' => '.reg06_tv',
4088 
      },
4089 
      'entity' => {
4090 
        'attributes' => {
4091 
          'entityAlreadyNetlisted' => 1,
4092 
          'isGateway' => 1,
4093 
          'is_floating_block' => 1,
4094 
        },
4095 
        'entityName' => 'reg06_tv',
4096 
        'ports' => {
4097 
          'reg06_tv' => {
4098 
            'attributes' => {
4099 
              'bin_pt' => 0,
4100 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
4101 
              'is_floating_block' => 1,
4102 
              'is_gateway_port' => 1,
4103 
              'must_be_hdl_vector' => 1,
4104 
              'period' => 1,
4105 
              'port_id' => 0,
4106 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
4107 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
4108 
              'timingConstraint' => 'none',
4109 
              'type' => 'Bool',
4110 
            },
4111 
            'direction' => 'out',
4112 
            'hdlType' => 'std_logic',
4113 
            'width' => 1,
4114 
          },
4115 
        },
4116 
      },
4117 
      'entityName' => 'reg06_tv',
4118 
    },
4119 
    'reg07_rd' => {
4120 
      'connections' => {
4121 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
4122 
      },
4123 
      'entity' => {
4124 
        'attributes' => {
4125 
          'entityAlreadyNetlisted' => 1,
4126 
          'isGateway' => 1,
4127 
          'is_floating_block' => 1,
4128 
        },
4129 
        'entityName' => 'reg07_rd',
4130 
        'ports' => {
4131 
          'reg07_rd' => {
4132 
            'attributes' => {
4133 
              'bin_pt' => 0,
4134 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
4135 
              'is_floating_block' => 1,
4136 
              'is_gateway_port' => 1,
4137 
              'must_be_hdl_vector' => 1,
4138 
              'period' => 1,
4139 
              'port_id' => 0,
4140 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
4141 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
4142 
              'timingConstraint' => 'none',
4143 
              'type' => 'UFix_32_0',
4144 
            },
4145 
            'direction' => 'in',
4146 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4147 
            'width' => 32,
4148 
          },
4149 
        },
4150 
      },
4151 
      'entityName' => 'reg07_rd',
4152 
    },
4153 
    'reg07_rv' => {
4154 
      'connections' => {
4155 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
4156 
      },
4157 
      'entity' => {
4158 
        'attributes' => {
4159 
          'entityAlreadyNetlisted' => 1,
4160 
          'isGateway' => 1,
4161 
          'is_floating_block' => 1,
4162 
        },
4163 
        'entityName' => 'reg07_rv',
4164 
        'ports' => {
4165 
          'reg07_rv' => {
4166 
            'attributes' => {
4167 
              'bin_pt' => 0,
4168 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
4169 
              'is_floating_block' => 1,
4170 
              'is_gateway_port' => 1,
4171 
              'must_be_hdl_vector' => 1,
4172 
              'period' => 1,
4173 
              'port_id' => 0,
4174 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
4175 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
4176 
              'timingConstraint' => 'none',
4177 
              'type' => 'UFix_1_0',
4178 
            },
4179 
            'direction' => 'in',
4180 
            'hdlType' => 'std_logic',
4181 
            'width' => 1,
4182 
          },
4183 
        },
4184 
      },
4185 
      'entityName' => 'reg07_rv',
4186 
    },
4187 
    'reg07_td' => {
4188 
      'connections' => {
4189 
        'reg07_td' => '.reg07_td',
4190 
      },
4191 
      'entity' => {
4192 
        'attributes' => {
4193 
          'entityAlreadyNetlisted' => 1,
4194 
          'isGateway' => 1,
4195 
          'is_floating_block' => 1,
4196 
        },
4197 
        'entityName' => 'reg07_td',
4198 
        'ports' => {
4199 
          'reg07_td' => {
4200 
            'attributes' => {
4201 
              'bin_pt' => 0,
4202 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
4203 
              'is_floating_block' => 1,
4204 
              'is_gateway_port' => 1,
4205 
              'must_be_hdl_vector' => 1,
4206 
              'period' => 1,
4207 
              'port_id' => 0,
4208 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
4209 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
4210 
              'timingConstraint' => 'none',
4211 
              'type' => 'UFix_32_0',
4212 
            },
4213 
            'direction' => 'out',
4214 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4215 
            'width' => 32,
4216 
          },
4217 
        },
4218 
      },
4219 
      'entityName' => 'reg07_td',
4220 
    },
4221 
    'reg07_tv' => {
4222 
      'connections' => {
4223 
        'reg07_tv' => '.reg07_tv',
4224 
      },
4225 
      'entity' => {
4226 
        'attributes' => {
4227 
          'entityAlreadyNetlisted' => 1,
4228 
          'isGateway' => 1,
4229 
          'is_floating_block' => 1,
4230 
        },
4231 
        'entityName' => 'reg07_tv',
4232 
        'ports' => {
4233 
          'reg07_tv' => {
4234 
            'attributes' => {
4235 
              'bin_pt' => 0,
4236 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
4237 
              'is_floating_block' => 1,
4238 
              'is_gateway_port' => 1,
4239 
              'must_be_hdl_vector' => 1,
4240 
              'period' => 1,
4241 
              'port_id' => 0,
4242 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
4243 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
4244 
              'timingConstraint' => 'none',
4245 
              'type' => 'Bool',
4246 
            },
4247 
            'direction' => 'out',
4248 
            'hdlType' => 'std_logic',
4249 
            'width' => 1,
4250 
          },
4251 
        },
4252 
      },
4253 
      'entityName' => 'reg07_tv',
4254 
    },
4255 
    'reg08_rd' => {
4256 
      'connections' => {
4257 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
4258 
      },
4259 
      'entity' => {
4260 
        'attributes' => {
4261 
          'entityAlreadyNetlisted' => 1,
4262 
          'isGateway' => 1,
4263 
          'is_floating_block' => 1,
4264 
        },
4265 
        'entityName' => 'reg08_rd',
4266 
        'ports' => {
4267 
          'reg08_rd' => {
4268 
            'attributes' => {
4269 
              'bin_pt' => 0,
4270 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
4271 
              'is_floating_block' => 1,
4272 
              'is_gateway_port' => 1,
4273 
              'must_be_hdl_vector' => 1,
4274 
              'period' => 1,
4275 
              'port_id' => 0,
4276 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
4277 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
4278 
              'timingConstraint' => 'none',
4279 
              'type' => 'UFix_32_0',
4280 
            },
4281 
            'direction' => 'in',
4282 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4283 
            'width' => 32,
4284 
          },
4285 
        },
4286 
      },
4287 
      'entityName' => 'reg08_rd',
4288 
    },
4289 
    'reg08_rv' => {
4290 
      'connections' => {
4291 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
4292 
      },
4293 
      'entity' => {
4294 
        'attributes' => {
4295 
          'entityAlreadyNetlisted' => 1,
4296 
          'isGateway' => 1,
4297 
          'is_floating_block' => 1,
4298 
        },
4299 
        'entityName' => 'reg08_rv',
4300 
        'ports' => {
4301 
          'reg08_rv' => {
4302 
            'attributes' => {
4303 
              'bin_pt' => 0,
4304 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
4305 
              'is_floating_block' => 1,
4306 
              'is_gateway_port' => 1,
4307 
              'must_be_hdl_vector' => 1,
4308 
              'period' => 1,
4309 
              'port_id' => 0,
4310 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
4311 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
4312 
              'timingConstraint' => 'none',
4313 
              'type' => 'UFix_1_0',
4314 
            },
4315 
            'direction' => 'in',
4316 
            'hdlType' => 'std_logic',
4317 
            'width' => 1,
4318 
          },
4319 
        },
4320 
      },
4321 
      'entityName' => 'reg08_rv',
4322 
    },
4323 
    'reg08_td' => {
4324 
      'connections' => {
4325 
        'reg08_td' => '.reg08_td',
4326 
      },
4327 
      'entity' => {
4328 
        'attributes' => {
4329 
          'entityAlreadyNetlisted' => 1,
4330 
          'isGateway' => 1,
4331 
          'is_floating_block' => 1,
4332 
        },
4333 
        'entityName' => 'reg08_td',
4334 
        'ports' => {
4335 
          'reg08_td' => {
4336 
            'attributes' => {
4337 
              'bin_pt' => 0,
4338 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
4339 
              'is_floating_block' => 1,
4340 
              'is_gateway_port' => 1,
4341 
              'must_be_hdl_vector' => 1,
4342 
              'period' => 1,
4343 
              'port_id' => 0,
4344 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
4345 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
4346 
              'timingConstraint' => 'none',
4347 
              'type' => 'UFix_32_0',
4348 
            },
4349 
            'direction' => 'out',
4350 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4351 
            'width' => 32,
4352 
          },
4353 
        },
4354 
      },
4355 
      'entityName' => 'reg08_td',
4356 
    },
4357 
    'reg08_tv' => {
4358 
      'connections' => {
4359 
        'reg08_tv' => '.reg08_tv',
4360 
      },
4361 
      'entity' => {
4362 
        'attributes' => {
4363 
          'entityAlreadyNetlisted' => 1,
4364 
          'isGateway' => 1,
4365 
          'is_floating_block' => 1,
4366 
        },
4367 
        'entityName' => 'reg08_tv',
4368 
        'ports' => {
4369 
          'reg08_tv' => {
4370 
            'attributes' => {
4371 
              'bin_pt' => 0,
4372 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
4373 
              'is_floating_block' => 1,
4374 
              'is_gateway_port' => 1,
4375 
              'must_be_hdl_vector' => 1,
4376 
              'period' => 1,
4377 
              'port_id' => 0,
4378 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
4379 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
4380 
              'timingConstraint' => 'none',
4381 
              'type' => 'Bool',
4382 
            },
4383 
            'direction' => 'out',
4384 
            'hdlType' => 'std_logic',
4385 
            'width' => 1,
4386 
          },
4387 
        },
4388 
      },
4389 
      'entityName' => 'reg08_tv',
4390 
    },
4391 
    'reg09_rd' => {
4392 
      'connections' => {
4393 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
4394 
      },
4395 
      'entity' => {
4396 
        'attributes' => {
4397 
          'entityAlreadyNetlisted' => 1,
4398 
          'isGateway' => 1,
4399 
          'is_floating_block' => 1,
4400 
        },
4401 
        'entityName' => 'reg09_rd',
4402 
        'ports' => {
4403 
          'reg09_rd' => {
4404 
            'attributes' => {
4405 
              'bin_pt' => 0,
4406 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
4407 
              'is_floating_block' => 1,
4408 
              'is_gateway_port' => 1,
4409 
              'must_be_hdl_vector' => 1,
4410 
              'period' => 1,
4411 
              'port_id' => 0,
4412 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
4413 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
4414 
              'timingConstraint' => 'none',
4415 
              'type' => 'UFix_32_0',
4416 
            },
4417 
            'direction' => 'in',
4418 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4419 
            'width' => 32,
4420 
          },
4421 
        },
4422 
      },
4423 
      'entityName' => 'reg09_rd',
4424 
    },
4425 
    'reg09_rv' => {
4426 
      'connections' => {
4427 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
4428 
      },
4429 
      'entity' => {
4430 
        'attributes' => {
4431 
          'entityAlreadyNetlisted' => 1,
4432 
          'isGateway' => 1,
4433 
          'is_floating_block' => 1,
4434 
        },
4435 
        'entityName' => 'reg09_rv',
4436 
        'ports' => {
4437 
          'reg09_rv' => {
4438 
            'attributes' => {
4439 
              'bin_pt' => 0,
4440 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
4441 
              'is_floating_block' => 1,
4442 
              'is_gateway_port' => 1,
4443 
              'must_be_hdl_vector' => 1,
4444 
              'period' => 1,
4445 
              'port_id' => 0,
4446 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
4447 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
4448 
              'timingConstraint' => 'none',
4449 
              'type' => 'UFix_1_0',
4450 
            },
4451 
            'direction' => 'in',
4452 
            'hdlType' => 'std_logic',
4453 
            'width' => 1,
4454 
          },
4455 
        },
4456 
      },
4457 
      'entityName' => 'reg09_rv',
4458 
    },
4459 
    'reg09_td' => {
4460 
      'connections' => {
4461 
        'reg09_td' => '.reg09_td',
4462 
      },
4463 
      'entity' => {
4464 
        'attributes' => {
4465 
          'entityAlreadyNetlisted' => 1,
4466 
          'isGateway' => 1,
4467 
          'is_floating_block' => 1,
4468 
        },
4469 
        'entityName' => 'reg09_td',
4470 
        'ports' => {
4471 
          'reg09_td' => {
4472 
            'attributes' => {
4473 
              'bin_pt' => 0,
4474 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
4475 
              'is_floating_block' => 1,
4476 
              'is_gateway_port' => 1,
4477 
              'must_be_hdl_vector' => 1,
4478 
              'period' => 1,
4479 
              'port_id' => 0,
4480 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
4481 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
4482 
              'timingConstraint' => 'none',
4483 
              'type' => 'UFix_32_0',
4484 
            },
4485 
            'direction' => 'out',
4486 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4487 
            'width' => 32,
4488 
          },
4489 
        },
4490 
      },
4491 
      'entityName' => 'reg09_td',
4492 
    },
4493 
    'reg09_tv' => {
4494 
      'connections' => {
4495 
        'reg09_tv' => '.reg09_tv',
4496 
      },
4497 
      'entity' => {
4498 
        'attributes' => {
4499 
          'entityAlreadyNetlisted' => 1,
4500 
          'isGateway' => 1,
4501 
          'is_floating_block' => 1,
4502 
        },
4503 
        'entityName' => 'reg09_tv',
4504 
        'ports' => {
4505 
          'reg09_tv' => {
4506 
            'attributes' => {
4507 
              'bin_pt' => 0,
4508 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
4509 
              'is_floating_block' => 1,
4510 
              'is_gateway_port' => 1,
4511 
              'must_be_hdl_vector' => 1,
4512 
              'period' => 1,
4513 
              'port_id' => 0,
4514 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
4515 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
4516 
              'timingConstraint' => 'none',
4517 
              'type' => 'Bool',
4518 
            },
4519 
            'direction' => 'out',
4520 
            'hdlType' => 'std_logic',
4521 
            'width' => 1,
4522 
          },
4523 
        },
4524 
      },
4525 
      'entityName' => 'reg09_tv',
4526 
    },
4527 
    'reg10_rd' => {
4528 
      'connections' => {
4529 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
4530 
      },
4531 
      'entity' => {
4532 
        'attributes' => {
4533 
          'entityAlreadyNetlisted' => 1,
4534 
          'isGateway' => 1,
4535 
          'is_floating_block' => 1,
4536 
        },
4537 
        'entityName' => 'reg10_rd',
4538 
        'ports' => {
4539 
          'reg10_rd' => {
4540 
            'attributes' => {
4541 
              'bin_pt' => 0,
4542 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
4543 
              'is_floating_block' => 1,
4544 
              'is_gateway_port' => 1,
4545 
              'must_be_hdl_vector' => 1,
4546 
              'period' => 1,
4547 
              'port_id' => 0,
4548 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
4549 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
4550 
              'timingConstraint' => 'none',
4551 
              'type' => 'UFix_32_0',
4552 
            },
4553 
            'direction' => 'in',
4554 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4555 
            'width' => 32,
4556 
          },
4557 
        },
4558 
      },
4559 
      'entityName' => 'reg10_rd',
4560 
    },
4561 
    'reg10_rv' => {
4562 
      'connections' => {
4563 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
4564 
      },
4565 
      'entity' => {
4566 
        'attributes' => {
4567 
          'entityAlreadyNetlisted' => 1,
4568 
          'isGateway' => 1,
4569 
          'is_floating_block' => 1,
4570 
        },
4571 
        'entityName' => 'reg10_rv',
4572 
        'ports' => {
4573 
          'reg10_rv' => {
4574 
            'attributes' => {
4575 
              'bin_pt' => 0,
4576 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
4577 
              'is_floating_block' => 1,
4578 
              'is_gateway_port' => 1,
4579 
              'must_be_hdl_vector' => 1,
4580 
              'period' => 1,
4581 
              'port_id' => 0,
4582 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
4583 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
4584 
              'timingConstraint' => 'none',
4585 
              'type' => 'UFix_1_0',
4586 
            },
4587 
            'direction' => 'in',
4588 
            'hdlType' => 'std_logic',
4589 
            'width' => 1,
4590 
          },
4591 
        },
4592 
      },
4593 
      'entityName' => 'reg10_rv',
4594 
    },
4595 
    'reg10_td' => {
4596 
      'connections' => {
4597 
        'reg10_td' => '.reg10_td',
4598 
      },
4599 
      'entity' => {
4600 
        'attributes' => {
4601 
          'entityAlreadyNetlisted' => 1,
4602 
          'isGateway' => 1,
4603 
          'is_floating_block' => 1,
4604 
        },
4605 
        'entityName' => 'reg10_td',
4606 
        'ports' => {
4607 
          'reg10_td' => {
4608 
            'attributes' => {
4609 
              'bin_pt' => 0,
4610 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
4611 
              'is_floating_block' => 1,
4612 
              'is_gateway_port' => 1,
4613 
              'must_be_hdl_vector' => 1,
4614 
              'period' => 1,
4615 
              'port_id' => 0,
4616 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
4617 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
4618 
              'timingConstraint' => 'none',
4619 
              'type' => 'UFix_32_0',
4620 
            },
4621 
            'direction' => 'out',
4622 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4623 
            'width' => 32,
4624 
          },
4625 
        },
4626 
      },
4627 
      'entityName' => 'reg10_td',
4628 
    },
4629 
    'reg10_tv' => {
4630 
      'connections' => {
4631 
        'reg10_tv' => '.reg10_tv',
4632 
      },
4633 
      'entity' => {
4634 
        'attributes' => {
4635 
          'entityAlreadyNetlisted' => 1,
4636 
          'isGateway' => 1,
4637 
          'is_floating_block' => 1,
4638 
        },
4639 
        'entityName' => 'reg10_tv',
4640 
        'ports' => {
4641 
          'reg10_tv' => {
4642 
            'attributes' => {
4643 
              'bin_pt' => 0,
4644 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
4645 
              'is_floating_block' => 1,
4646 
              'is_gateway_port' => 1,
4647 
              'must_be_hdl_vector' => 1,
4648 
              'period' => 1,
4649 
              'port_id' => 0,
4650 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
4651 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
4652 
              'timingConstraint' => 'none',
4653 
              'type' => 'Bool',
4654 
            },
4655 
            'direction' => 'out',
4656 
            'hdlType' => 'std_logic',
4657 
            'width' => 1,
4658 
          },
4659 
        },
4660 
      },
4661 
      'entityName' => 'reg10_tv',
4662 
    },
4663 
    'reg11_rd' => {
4664 
      'connections' => {
4665 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
4666 
      },
4667 
      'entity' => {
4668 
        'attributes' => {
4669 
          'entityAlreadyNetlisted' => 1,
4670 
          'isGateway' => 1,
4671 
          'is_floating_block' => 1,
4672 
        },
4673 
        'entityName' => 'reg11_rd',
4674 
        'ports' => {
4675 
          'reg11_rd' => {
4676 
            'attributes' => {
4677 
              'bin_pt' => 0,
4678 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
4679 
              'is_floating_block' => 1,
4680 
              'is_gateway_port' => 1,
4681 
              'must_be_hdl_vector' => 1,
4682 
              'period' => 1,
4683 
              'port_id' => 0,
4684 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
4685 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
4686 
              'timingConstraint' => 'none',
4687 
              'type' => 'UFix_32_0',
4688 
            },
4689 
            'direction' => 'in',
4690 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4691 
            'width' => 32,
4692 
          },
4693 
        },
4694 
      },
4695 
      'entityName' => 'reg11_rd',
4696 
    },
4697 
    'reg11_rv' => {
4698 
      'connections' => {
4699 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
4700 
      },
4701 
      'entity' => {
4702 
        'attributes' => {
4703 
          'entityAlreadyNetlisted' => 1,
4704 
          'isGateway' => 1,
4705 
          'is_floating_block' => 1,
4706 
        },
4707 
        'entityName' => 'reg11_rv',
4708 
        'ports' => {
4709 
          'reg11_rv' => {
4710 
            'attributes' => {
4711 
              'bin_pt' => 0,
4712 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
4713 
              'is_floating_block' => 1,
4714 
              'is_gateway_port' => 1,
4715 
              'must_be_hdl_vector' => 1,
4716 
              'period' => 1,
4717 
              'port_id' => 0,
4718 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
4719 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
4720 
              'timingConstraint' => 'none',
4721 
              'type' => 'UFix_1_0',
4722 
            },
4723 
            'direction' => 'in',
4724 
            'hdlType' => 'std_logic',
4725 
            'width' => 1,
4726 
          },
4727 
        },
4728 
      },
4729 
      'entityName' => 'reg11_rv',
4730 
    },
4731 
    'reg11_td' => {
4732 
      'connections' => {
4733 
        'reg11_td' => '.reg11_td',
4734 
      },
4735 
      'entity' => {
4736 
        'attributes' => {
4737 
          'entityAlreadyNetlisted' => 1,
4738 
          'isGateway' => 1,
4739 
          'is_floating_block' => 1,
4740 
        },
4741 
        'entityName' => 'reg11_td',
4742 
        'ports' => {
4743 
          'reg11_td' => {
4744 
            'attributes' => {
4745 
              'bin_pt' => 0,
4746 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
4747 
              'is_floating_block' => 1,
4748 
              'is_gateway_port' => 1,
4749 
              'must_be_hdl_vector' => 1,
4750 
              'period' => 1,
4751 
              'port_id' => 0,
4752 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
4753 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
4754 
              'timingConstraint' => 'none',
4755 
              'type' => 'UFix_32_0',
4756 
            },
4757 
            'direction' => 'out',
4758 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4759 
            'width' => 32,
4760 
          },
4761 
        },
4762 
      },
4763 
      'entityName' => 'reg11_td',
4764 
    },
4765 
    'reg11_tv' => {
4766 
      'connections' => {
4767 
        'reg11_tv' => '.reg11_tv',
4768 
      },
4769 
      'entity' => {
4770 
        'attributes' => {
4771 
          'entityAlreadyNetlisted' => 1,
4772 
          'isGateway' => 1,
4773 
          'is_floating_block' => 1,
4774 
        },
4775 
        'entityName' => 'reg11_tv',
4776 
        'ports' => {
4777 
          'reg11_tv' => {
4778 
            'attributes' => {
4779 
              'bin_pt' => 0,
4780 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
4781 
              'is_floating_block' => 1,
4782 
              'is_gateway_port' => 1,
4783 
              'must_be_hdl_vector' => 1,
4784 
              'period' => 1,
4785 
              'port_id' => 0,
4786 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
4787 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
4788 
              'timingConstraint' => 'none',
4789 
              'type' => 'Bool',
4790 
            },
4791 
            'direction' => 'out',
4792 
            'hdlType' => 'std_logic',
4793 
            'width' => 1,
4794 
          },
4795 
        },
4796 
      },
4797 
      'entityName' => 'reg11_tv',
4798 
    },
4799 
    'reg12_rd' => {
4800 
      'connections' => {
4801 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
4802 
      },
4803 
      'entity' => {
4804 
        'attributes' => {
4805 
          'entityAlreadyNetlisted' => 1,
4806 
          'isGateway' => 1,
4807 
          'is_floating_block' => 1,
4808 
        },
4809 
        'entityName' => 'reg12_rd',
4810 
        'ports' => {
4811 
          'reg12_rd' => {
4812 
            'attributes' => {
4813 
              'bin_pt' => 0,
4814 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
4815 
              'is_floating_block' => 1,
4816 
              'is_gateway_port' => 1,
4817 
              'must_be_hdl_vector' => 1,
4818 
              'period' => 1,
4819 
              'port_id' => 0,
4820 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
4821 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
4822 
              'timingConstraint' => 'none',
4823 
              'type' => 'UFix_32_0',
4824 
            },
4825 
            'direction' => 'in',
4826 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4827 
            'width' => 32,
4828 
          },
4829 
        },
4830 
      },
4831 
      'entityName' => 'reg12_rd',
4832 
    },
4833 
    'reg12_rv' => {
4834 
      'connections' => {
4835 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
4836 
      },
4837 
      'entity' => {
4838 
        'attributes' => {
4839 
          'entityAlreadyNetlisted' => 1,
4840 
          'isGateway' => 1,
4841 
          'is_floating_block' => 1,
4842 
        },
4843 
        'entityName' => 'reg12_rv',
4844 
        'ports' => {
4845 
          'reg12_rv' => {
4846 
            'attributes' => {
4847 
              'bin_pt' => 0,
4848 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
4849 
              'is_floating_block' => 1,
4850 
              'is_gateway_port' => 1,
4851 
              'must_be_hdl_vector' => 1,
4852 
              'period' => 1,
4853 
              'port_id' => 0,
4854 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
4855 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
4856 
              'timingConstraint' => 'none',
4857 
              'type' => 'UFix_1_0',
4858 
            },
4859 
            'direction' => 'in',
4860 
            'hdlType' => 'std_logic',
4861 
            'width' => 1,
4862 
          },
4863 
        },
4864 
      },
4865 
      'entityName' => 'reg12_rv',
4866 
    },
4867 
    'reg12_td' => {
4868 
      'connections' => {
4869 
        'reg12_td' => '.reg12_td',
4870 
      },
4871 
      'entity' => {
4872 
        'attributes' => {
4873 
          'entityAlreadyNetlisted' => 1,
4874 
          'isGateway' => 1,
4875 
          'is_floating_block' => 1,
4876 
        },
4877 
        'entityName' => 'reg12_td',
4878 
        'ports' => {
4879 
          'reg12_td' => {
4880 
            'attributes' => {
4881 
              'bin_pt' => 0,
4882 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
4883 
              'is_floating_block' => 1,
4884 
              'is_gateway_port' => 1,
4885 
              'must_be_hdl_vector' => 1,
4886 
              'period' => 1,
4887 
              'port_id' => 0,
4888 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
4889 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
4890 
              'timingConstraint' => 'none',
4891 
              'type' => 'UFix_32_0',
4892 
            },
4893 
            'direction' => 'out',
4894 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4895 
            'width' => 32,
4896 
          },
4897 
        },
4898 
      },
4899 
      'entityName' => 'reg12_td',
4900 
    },
4901 
    'reg12_tv' => {
4902 
      'connections' => {
4903 
        'reg12_tv' => '.reg12_tv',
4904 
      },
4905 
      'entity' => {
4906 
        'attributes' => {
4907 
          'entityAlreadyNetlisted' => 1,
4908 
          'isGateway' => 1,
4909 
          'is_floating_block' => 1,
4910 
        },
4911 
        'entityName' => 'reg12_tv',
4912 
        'ports' => {
4913 
          'reg12_tv' => {
4914 
            'attributes' => {
4915 
              'bin_pt' => 0,
4916 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
4917 
              'is_floating_block' => 1,
4918 
              'is_gateway_port' => 1,
4919 
              'must_be_hdl_vector' => 1,
4920 
              'period' => 1,
4921 
              'port_id' => 0,
4922 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
4923 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
4924 
              'timingConstraint' => 'none',
4925 
              'type' => 'Bool',
4926 
            },
4927 
            'direction' => 'out',
4928 
            'hdlType' => 'std_logic',
4929 
            'width' => 1,
4930 
          },
4931 
        },
4932 
      },
4933 
      'entityName' => 'reg12_tv',
4934 
    },
4935 
    'reg13_rd' => {
4936 
      'connections' => {
4937 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
4938 
      },
4939 
      'entity' => {
4940 
        'attributes' => {
4941 
          'entityAlreadyNetlisted' => 1,
4942 
          'isGateway' => 1,
4943 
          'is_floating_block' => 1,
4944 
        },
4945 
        'entityName' => 'reg13_rd',
4946 
        'ports' => {
4947 
          'reg13_rd' => {
4948 
            'attributes' => {
4949 
              'bin_pt' => 0,
4950 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
4951 
              'is_floating_block' => 1,
4952 
              'is_gateway_port' => 1,
4953 
              'must_be_hdl_vector' => 1,
4954 
              'period' => 1,
4955 
              'port_id' => 0,
4956 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
4957 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
4958 
              'timingConstraint' => 'none',
4959 
              'type' => 'UFix_32_0',
4960 
            },
4961 
            'direction' => 'in',
4962 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4963 
            'width' => 32,
4964 
          },
4965 
        },
4966 
      },
4967 
      'entityName' => 'reg13_rd',
4968 
    },
4969 
    'reg13_rv' => {
4970 
      'connections' => {
4971 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
4972 
      },
4973 
      'entity' => {
4974 
        'attributes' => {
4975 
          'entityAlreadyNetlisted' => 1,
4976 
          'isGateway' => 1,
4977 
          'is_floating_block' => 1,
4978 
        },
4979 
        'entityName' => 'reg13_rv',
4980 
        'ports' => {
4981 
          'reg13_rv' => {
4982 
            'attributes' => {
4983 
              'bin_pt' => 0,
4984 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
4985 
              'is_floating_block' => 1,
4986 
              'is_gateway_port' => 1,
4987 
              'must_be_hdl_vector' => 1,
4988 
              'period' => 1,
4989 
              'port_id' => 0,
4990 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
4991 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
4992 
              'timingConstraint' => 'none',
4993 
              'type' => 'UFix_1_0',
4994 
            },
4995 
            'direction' => 'in',
4996 
            'hdlType' => 'std_logic',
4997 
            'width' => 1,
4998 
          },
4999 
        },
5000 
      },
5001 
      'entityName' => 'reg13_rv',
5002 
    },
5003 
    'reg13_td' => {
5004 
      'connections' => {
5005 
        'reg13_td' => '.reg13_td',
5006 
      },
5007 
      'entity' => {
5008 
        'attributes' => {
5009 
          'entityAlreadyNetlisted' => 1,
5010 
          'isGateway' => 1,
5011 
          'is_floating_block' => 1,
5012 
        },
5013 
        'entityName' => 'reg13_td',
5014 
        'ports' => {
5015 
          'reg13_td' => {
5016 
            'attributes' => {
5017 
              'bin_pt' => 0,
5018 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
5019 
              'is_floating_block' => 1,
5020 
              'is_gateway_port' => 1,
5021 
              'must_be_hdl_vector' => 1,
5022 
              'period' => 1,
5023 
              'port_id' => 0,
5024 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
5025 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
5026 
              'timingConstraint' => 'none',
5027 
              'type' => 'UFix_32_0',
5028 
            },
5029 
            'direction' => 'out',
5030 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5031 
            'width' => 32,
5032 
          },
5033 
        },
5034 
      },
5035 
      'entityName' => 'reg13_td',
5036 
    },
5037 
    'reg13_tv' => {
5038 
      'connections' => {
5039 
        'reg13_tv' => '.reg13_tv',
5040 
      },
5041 
      'entity' => {
5042 
        'attributes' => {
5043 
          'entityAlreadyNetlisted' => 1,
5044 
          'isGateway' => 1,
5045 
          'is_floating_block' => 1,
5046 
        },
5047 
        'entityName' => 'reg13_tv',
5048 
        'ports' => {
5049 
          'reg13_tv' => {
5050 
            'attributes' => {
5051 
              'bin_pt' => 0,
5052 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
5053 
              'is_floating_block' => 1,
5054 
              'is_gateway_port' => 1,
5055 
              'must_be_hdl_vector' => 1,
5056 
              'period' => 1,
5057 
              'port_id' => 0,
5058 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
5059 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
5060 
              'timingConstraint' => 'none',
5061 
              'type' => 'Bool',
5062 
            },
5063 
            'direction' => 'out',
5064 
            'hdlType' => 'std_logic',
5065 
            'width' => 1,
5066 
          },
5067 
        },
5068 
      },
5069 
      'entityName' => 'reg13_tv',
5070 
    },
5071 
    'reg14_rd' => {
5072 
      'connections' => {
5073 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5074 
      },
5075 
      'entity' => {
5076 
        'attributes' => {
5077 
          'entityAlreadyNetlisted' => 1,
5078 
          'isGateway' => 1,
5079 
          'is_floating_block' => 1,
5080 
        },
5081 
        'entityName' => 'reg14_rd',
5082 
        'ports' => {
5083 
          'reg14_rd' => {
5084 
            'attributes' => {
5085 
              'bin_pt' => 0,
5086 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
5087 
              'is_floating_block' => 1,
5088 
              'is_gateway_port' => 1,
5089 
              'must_be_hdl_vector' => 1,
5090 
              'period' => 1,
5091 
              'port_id' => 0,
5092 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
5093 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
5094 
              'timingConstraint' => 'none',
5095 
              'type' => 'UFix_32_0',
5096 
            },
5097 
            'direction' => 'in',
5098 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5099 
            'width' => 32,
5100 
          },
5101 
        },
5102 
      },
5103 
      'entityName' => 'reg14_rd',
5104 
    },
5105 
    'reg14_rv' => {
5106 
      'connections' => {
5107 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5108 
      },
5109 
      'entity' => {
5110 
        'attributes' => {
5111 
          'entityAlreadyNetlisted' => 1,
5112 
          'isGateway' => 1,
5113 
          'is_floating_block' => 1,
5114 
        },
5115 
        'entityName' => 'reg14_rv',
5116 
        'ports' => {
5117 
          'reg14_rv' => {
5118 
            'attributes' => {
5119 
              'bin_pt' => 0,
5120 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
5121 
              'is_floating_block' => 1,
5122 
              'is_gateway_port' => 1,
5123 
              'must_be_hdl_vector' => 1,
5124 
              'period' => 1,
5125 
              'port_id' => 0,
5126 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
5127 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
5128 
              'timingConstraint' => 'none',
5129 
              'type' => 'UFix_1_0',
5130 
            },
5131 
            'direction' => 'in',
5132 
            'hdlType' => 'std_logic',
5133 
            'width' => 1,
5134 
          },
5135 
        },
5136 
      },
5137 
      'entityName' => 'reg14_rv',
5138 
    },
5139 
    'reg14_td' => {
5140 
      'connections' => {
5141 
        'reg14_td' => '.reg14_td',
5142 
      },
5143 
      'entity' => {
5144 
        'attributes' => {
5145 
          'entityAlreadyNetlisted' => 1,
5146 
          'isGateway' => 1,
5147 
          'is_floating_block' => 1,
5148 
        },
5149 
        'entityName' => 'reg14_td',
5150 
        'ports' => {
5151 
          'reg14_td' => {
5152 
            'attributes' => {
5153 
              'bin_pt' => 0,
5154 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
5155 
              'is_floating_block' => 1,
5156 
              'is_gateway_port' => 1,
5157 
              'must_be_hdl_vector' => 1,
5158 
              'period' => 1,
5159 
              'port_id' => 0,
5160 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
5161 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
5162 
              'timingConstraint' => 'none',
5163 
              'type' => 'UFix_32_0',
5164 
            },
5165 
            'direction' => 'out',
5166 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5167 
            'width' => 32,
5168 
          },
5169 
        },
5170 
      },
5171 
      'entityName' => 'reg14_td',
5172 
    },
5173 
    'reg14_tv' => {
5174 
      'connections' => {
5175 
        'reg14_tv' => '.reg14_tv',
5176 
      },
5177 
      'entity' => {
5178 
        'attributes' => {
5179 
          'entityAlreadyNetlisted' => 1,
5180 
          'isGateway' => 1,
5181 
          'is_floating_block' => 1,
5182 
        },
5183 
        'entityName' => 'reg14_tv',
5184 
        'ports' => {
5185 
          'reg14_tv' => {
5186 
            'attributes' => {
5187 
              'bin_pt' => 0,
5188 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
5189 
              'is_floating_block' => 1,
5190 
              'is_gateway_port' => 1,
5191 
              'must_be_hdl_vector' => 1,
5192 
              'period' => 1,
5193 
              'port_id' => 0,
5194 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
5195 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
5196 
              'timingConstraint' => 'none',
5197 
              'type' => 'Bool',
5198 
            },
5199 
            'direction' => 'out',
5200 
            'hdlType' => 'std_logic',
5201 
            'width' => 1,
5202 
          },
5203 
        },
5204 
      },
5205 
      'entityName' => 'reg14_tv',
5206 
    },
5207 
    'sysgen_dut' => {
5208 
      'connections' => {
5209 
        'clk' => '.clk',
5210 
        'debug_in_1i' => '.debug_in_1i',
5211 
        'debug_in_2i' => '.debug_in_2i',
5212 
        'debug_in_3i' => '.debug_in_3i',
5213 
        'debug_in_4i' => '.debug_in_4i',
5214 
        'dma_host2board_busy' => '.dma_host2board_busy',
5215 
        'dma_host2board_done' => '.dma_host2board_done',
5216 
        'from_register10_data_out' => 'from_register10.data_out',
5217 
        'from_register11_data_out' => 'from_register11.data_out',
5218 
        'from_register12_data_out' => 'from_register12.data_out',
5219 
        'from_register13_data_out' => 'from_register13.data_out',
5220 
        'from_register14_data_out' => 'from_register14.data_out',
5221 
        'from_register15_data_out' => 'from_register15.data_out',
5222 
        'from_register16_data_out' => 'from_register16.data_out',
5223 
        'from_register17_data_out' => 'from_register17.data_out',
5224 
        'from_register18_data_out' => 'from_register18.data_out',
5225 
        'from_register19_data_out' => 'from_register19.data_out',
5226 
        'from_register1_data_out' => 'from_register1.data_out',
5227 
        'from_register20_data_out' => 'from_register20.data_out',
5228 
        'from_register21_data_out' => 'from_register21.data_out',
5229 
        'from_register22_data_out' => 'from_register22.data_out',
5230 
        'from_register23_data_out' => 'from_register23.data_out',
5231 
        'from_register24_data_out' => 'from_register24.data_out',
5232 
        'from_register25_data_out' => 'from_register25.data_out',
5233 
        'from_register26_data_out' => 'from_register26.data_out',
5234 
        'from_register27_data_out' => 'from_register27.data_out',
5235 
        'from_register28_data_out' => 'from_register28.data_out',
5236 
        'from_register2_data_out' => 'from_register2.data_out',
5237 
        'from_register3_data_out' => 'from_register3.data_out',
5238 
        'from_register4_data_out' => 'from_register4.data_out',
5239 
        'from_register5_data_out' => 'from_register5.data_out',
5240 
        'from_register6_data_out' => 'from_register6.data_out',
5241 
        'from_register7_data_out' => 'from_register7.data_out',
5242 
        'from_register8_data_out' => 'from_register8.data_out',
5243 
        'from_register9_data_out' => 'from_register9.data_out',
5244 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5245 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5246 
        'reg01_td' => '.reg01_td',
5247 
        'reg01_tv' => '.reg01_tv',
5248 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5249 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5250 
        'reg02_td' => '.reg02_td',
5251 
        'reg02_tv' => '.reg02_tv',
5252 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5253 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5254 
        'reg03_td' => '.reg03_td',
5255 
        'reg03_tv' => '.reg03_tv',
5256 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5257 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5258 
        'reg04_td' => '.reg04_td',
5259 
        'reg04_tv' => '.reg04_tv',
5260 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5261 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5262 
        'reg05_td' => '.reg05_td',
5263 
        'reg05_tv' => '.reg05_tv',
5264 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5265 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5266 
        'reg06_td' => '.reg06_td',
5267 
        'reg06_tv' => '.reg06_tv',
5268 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5269 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5270 
        'reg07_td' => '.reg07_td',
5271 
        'reg07_tv' => '.reg07_tv',
5272 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5273 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5274 
        'reg08_td' => '.reg08_td',
5275 
        'reg08_tv' => '.reg08_tv',
5276 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5277 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5278 
        'reg09_td' => '.reg09_td',
5279 
        'reg09_tv' => '.reg09_tv',
5280 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5281 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5282 
        'reg10_td' => '.reg10_td',
5283 
        'reg10_tv' => '.reg10_tv',
5284 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5285 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5286 
        'reg11_td' => '.reg11_td',
5287 
        'reg11_tv' => '.reg11_tv',
5288 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5289 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5290 
        'reg12_td' => '.reg12_td',
5291 
        'reg12_tv' => '.reg12_tv',
5292 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5293 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5294 
        'reg13_td' => '.reg13_td',
5295 
        'reg13_tv' => '.reg13_tv',
5296 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5297 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5298 
        'reg14_td' => '.reg14_td',
5299 
        'reg14_tv' => '.reg14_tv',
5300 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5301 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5302 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5303 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5304 
        'to_register10_dout' => 'to_register10.dout',
5305 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5306 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5307 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5308 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5309 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5310 
        'to_register11_dout' => 'to_register11.dout',
5311 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5312 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5313 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5314 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5315 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5316 
        'to_register12_dout' => 'to_register12.dout',
5317 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5318 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5319 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5320 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5321 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5322 
        'to_register13_dout' => 'to_register13.dout',
5323 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5324 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5325 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5326 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5327 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5328 
        'to_register14_dout' => 'to_register14.dout',
5329 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5330 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5331 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5332 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5333 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5334 
        'to_register15_dout' => 'to_register15.dout',
5335 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5336 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5337 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5338 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5339 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5340 
        'to_register16_dout' => 'to_register16.dout',
5341 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5342 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5343 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5344 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5345 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5346 
        'to_register17_dout' => 'to_register17.dout',
5347 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5348 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5349 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5350 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5351 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5352 
        'to_register18_dout' => 'to_register18.dout',
5353 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5354 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5355 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5356 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5357 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5358 
        'to_register19_dout' => 'to_register19.dout',
5359 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5360 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5361 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5362 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5363 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5364 
        'to_register1_dout' => 'to_register1.dout',
5365 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5366 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5367 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5368 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5369 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5370 
        'to_register20_dout' => 'to_register20.dout',
5371 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5372 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5373 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5374 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5375 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5376 
        'to_register21_dout' => 'to_register21.dout',
5377 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5378 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5379 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5380 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5381 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5382 
        'to_register22_dout' => 'to_register22.dout',
5383 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5384 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5385 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5386 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5387 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5388 
        'to_register23_dout' => 'to_register23.dout',
5389 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5390 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5391 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5392 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5393 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5394 
        'to_register24_dout' => 'to_register24.dout',
5395 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5396 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5397 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5398 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5399 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5400 
        'to_register25_dout' => 'to_register25.dout',
5401 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5402 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5403 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5404 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5405 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5406 
        'to_register26_dout' => 'to_register26.dout',
5407 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5408 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5409 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5410 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5411 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5412 
        'to_register27_dout' => 'to_register27.dout',
5413 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5414 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5415 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5416 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5417 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5418 
        'to_register28_dout' => 'to_register28.dout',
5419 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5420 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5421 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5422 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5423 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5424 
        'to_register29_dout' => 'to_register29.dout',
5425 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5426 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5427 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5428 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5429 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5430 
        'to_register2_dout' => 'to_register2.dout',
5431 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5432 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5433 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5434 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5435 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5436 
        'to_register30_dout' => 'to_register30.dout',
5437 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5438 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5439 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5440 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5441 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5442 
        'to_register31_dout' => 'to_register31.dout',
5443 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5444 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5445 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5446 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5447 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5448 
        'to_register32_dout' => 'to_register32.dout',
5449 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5450 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5451 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5452 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5453 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5454 
        'to_register33_dout' => 'to_register33.dout',
5455 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5456 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5457 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5458 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5459 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5460 
        'to_register34_dout' => 'to_register34.dout',
5461 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5462 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5463 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5464 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5465 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5466 
        'to_register3_dout' => 'to_register3.dout',
5467 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5468 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5469 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5470 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5471 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5472 
        'to_register4_dout' => 'to_register4.dout',
5473 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5474 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5475 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5476 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5477 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5478 
        'to_register5_dout' => 'to_register5.dout',
5479 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5480 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5481 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5482 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5483 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5484 
        'to_register6_dout' => 'to_register6.dout',
5485 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5486 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5487 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5488 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5489 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5490 
        'to_register7_dout' => 'to_register7.dout',
5491 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5492 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5493 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5494 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5495 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5496 
        'to_register8_dout' => 'to_register8.dout',
5497 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5498 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5499 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5500 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5501 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5502 
        'to_register9_dout' => 'to_register9.dout',
5503 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5504 
      },
5505 
      'entity' => {
5506 
        'attributes' => {
5507 
          'entityAlreadyNetlisted' => 1,
5508 
          'hdlArchAttributes' => [
5509 
          ],
5510 
          'hdlEntityAttributes' => [
5511 
          ],
5512 
          'isClkWrapper' => 1,
5513 
        },
5514 
        'connections' => {
5515 
          'clk' => 'clkNet',
5516 
          'debug_in_1i' => 'debug_in_1i_net',
5517 
          'debug_in_2i' => 'debug_in_2i_net',
5518 
          'debug_in_3i' => 'debug_in_3i_net',
5519 
          'debug_in_4i' => 'debug_in_4i_net',
5520 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5521 
          'dma_host2board_done' => 'dma_host2board_done_net',
5522 
          'from_register10_data_out' => 'from_register10_data_out_net',
5523 
          'from_register11_data_out' => 'from_register11_data_out_net',
5524 
          'from_register12_data_out' => 'from_register12_data_out_net',
5525 
          'from_register13_data_out' => 'from_register13_data_out_net',
5526 
          'from_register14_data_out' => 'from_register14_data_out_net',
5527 
          'from_register15_data_out' => 'from_register15_data_out_net',
5528 
          'from_register16_data_out' => 'from_register16_data_out_net',
5529 
          'from_register17_data_out' => 'from_register17_data_out_net',
5530 
          'from_register18_data_out' => 'from_register18_data_out_net',
5531 
          'from_register19_data_out' => 'from_register19_data_out_net',
5532 
          'from_register1_data_out' => 'from_register1_data_out_net',
5533 
          'from_register20_data_out' => 'from_register20_data_out_net',
5534 
          'from_register21_data_out' => 'from_register21_data_out_net',
5535 
          'from_register22_data_out' => 'from_register22_data_out_net',
5536 
          'from_register23_data_out' => 'from_register23_data_out_net',
5537 
          'from_register24_data_out' => 'from_register24_data_out_net',
5538 
          'from_register25_data_out' => 'from_register25_data_out_net',
5539 
          'from_register26_data_out' => 'from_register26_data_out_net',
5540 
          'from_register27_data_out' => 'from_register27_data_out_net',
5541 
          'from_register28_data_out' => 'from_register28_data_out_net',
5542 
          'from_register2_data_out' => 'from_register2_data_out_net',
5543 
          'from_register3_data_out' => 'from_register3_data_out_net',
5544 
          'from_register4_data_out' => 'from_register4_data_out_net',
5545 
          'from_register5_data_out' => 'from_register5_data_out_net',
5546 
          'from_register6_data_out' => 'from_register6_data_out_net',
5547 
          'from_register7_data_out' => 'from_register7_data_out_net',
5548 
          'from_register8_data_out' => 'from_register8_data_out_net',
5549 
          'from_register9_data_out' => 'from_register9_data_out_net',
5550 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5551 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5552 
          'reg01_td' => 'reg01_td_net',
5553 
          'reg01_tv' => 'reg01_tv_net',
5554 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5555 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5556 
          'reg02_td' => 'reg02_td_net',
5557 
          'reg02_tv' => 'reg02_tv_net',
5558 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5559 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5560 
          'reg03_td' => 'reg03_td_net',
5561 
          'reg03_tv' => 'reg03_tv_net',
5562 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5563 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5564 
          'reg04_td' => 'reg04_td_net',
5565 
          'reg04_tv' => 'reg04_tv_net',
5566 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5567 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5568 
          'reg05_td' => 'reg05_td_net',
5569 
          'reg05_tv' => 'reg05_tv_net',
5570 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5571 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5572 
          'reg06_td' => 'reg06_td_net',
5573 
          'reg06_tv' => 'reg06_tv_net',
5574 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5575 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5576 
          'reg07_td' => 'reg07_td_net',
5577 
          'reg07_tv' => 'reg07_tv_net',
5578 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5579 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5580 
          'reg08_td' => 'reg08_td_net',
5581 
          'reg08_tv' => 'reg08_tv_net',
5582 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5583 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5584 
          'reg09_td' => 'reg09_td_net',
5585 
          'reg09_tv' => 'reg09_tv_net',
5586 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5587 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5588 
          'reg10_td' => 'reg10_td_net',
5589 
          'reg10_tv' => 'reg10_tv_net',
5590 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5591 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5592 
          'reg11_td' => 'reg11_td_net',
5593 
          'reg11_tv' => 'reg11_tv_net',
5594 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5595 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5596 
          'reg12_td' => 'reg12_td_net',
5597 
          'reg12_tv' => 'reg12_tv_net',
5598 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5599 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5600 
          'reg13_td' => 'reg13_td_net',
5601 
          'reg13_tv' => 'reg13_tv_net',
5602 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5603 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5604 
          'reg14_td' => 'reg14_td_net',
5605 
          'reg14_tv' => 'reg14_tv_net',
5606 
          'to_register10_ce' => 'ce_1_sg',
5607 
          'to_register10_clk' => 'clk_1_sg',
5608 
          'to_register10_clr' => [
5609 
            'constant',
5610 
            '\'0\'',
5611 
          ],
5612 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5613 
          'to_register10_dout' => 'to_register10_dout_net',
5614 
          'to_register10_en' => 'constant5_op_net_x1',
5615 
          'to_register11_ce' => 'ce_1_sg',
5616 
          'to_register11_clk' => 'clk_1_sg',
5617 
          'to_register11_clr' => [
5618 
            'constant',
5619 
            '\'0\'',
5620 
          ],
5621 
          'to_register11_data_in' => 'reg04_td_net_x0',
5622 
          'to_register11_dout' => 'to_register11_dout_net',
5623 
          'to_register11_en' => 'constant5_op_net_x2',
5624 
          'to_register12_ce' => 'ce_1_sg',
5625 
          'to_register12_clk' => 'clk_1_sg',
5626 
          'to_register12_clr' => [
5627 
            'constant',
5628 
            '\'0\'',
5629 
          ],
5630 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5631 
          'to_register12_dout' => 'to_register12_dout_net',
5632 
          'to_register12_en' => 'constant5_op_net_x3',
5633 
          'to_register13_ce' => 'ce_1_sg',
5634 
          'to_register13_clk' => 'clk_1_sg',
5635 
          'to_register13_clr' => [
5636 
            'constant',
5637 
            '\'0\'',
5638 
          ],
5639 
          'to_register13_data_in' => 'reg05_td_net_x0',
5640 
          'to_register13_dout' => 'to_register13_dout_net',
5641 
          'to_register13_en' => 'constant5_op_net_x4',
5642 
          'to_register14_ce' => 'ce_1_sg',
5643 
          'to_register14_clk' => 'clk_1_sg',
5644 
          'to_register14_clr' => [
5645 
            'constant',
5646 
            '\'0\'',
5647 
          ],
5648 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5649 
          'to_register14_dout' => 'to_register14_dout_net',
5650 
          'to_register14_en' => 'constant5_op_net_x5',
5651 
          'to_register15_ce' => 'ce_1_sg',
5652 
          'to_register15_clk' => 'clk_1_sg',
5653 
          'to_register15_clr' => [
5654 
            'constant',
5655 
            '\'0\'',
5656 
          ],
5657 
          'to_register15_data_in' => 'reg06_td_net_x0',
5658 
          'to_register15_dout' => 'to_register15_dout_net',
5659 
          'to_register15_en' => 'constant5_op_net_x6',
5660 
          'to_register16_ce' => 'ce_1_sg',
5661 
          'to_register16_clk' => 'clk_1_sg',
5662 
          'to_register16_clr' => [
5663 
            'constant',
5664 
            '\'0\'',
5665 
          ],
5666 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5667 
          'to_register16_dout' => 'to_register16_dout_net',
5668 
          'to_register16_en' => 'constant5_op_net_x7',
5669 
          'to_register17_ce' => 'ce_1_sg',
5670 
          'to_register17_clk' => 'clk_1_sg',
5671 
          'to_register17_clr' => [
5672 
            'constant',
5673 
            '\'0\'',
5674 
          ],
5675 
          'to_register17_data_in' => 'reg07_td_net_x0',
5676 
          'to_register17_dout' => 'to_register17_dout_net',
5677 
          'to_register17_en' => 'constant5_op_net_x8',
5678 
          'to_register18_ce' => 'ce_1_sg',
5679 
          'to_register18_clk' => 'clk_1_sg',
5680 
          'to_register18_clr' => [
5681 
            'constant',
5682 
            '\'0\'',
5683 
          ],
5684 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5685 
          'to_register18_dout' => 'to_register18_dout_net',
5686 
          'to_register18_en' => 'constant5_op_net_x9',
5687 
          'to_register19_ce' => 'ce_1_sg',
5688 
          'to_register19_clk' => 'clk_1_sg',
5689 
          'to_register19_clr' => [
5690 
            'constant',
5691 
            '\'0\'',
5692 
          ],
5693 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5694 
          'to_register19_dout' => 'to_register19_dout_net',
5695 
          'to_register19_en' => 'constant5_op_net_x10',
5696 
          'to_register1_ce' => 'ce_1_sg',
5697 
          'to_register1_clk' => 'clk_1_sg',
5698 
          'to_register1_clr' => [
5699 
            'constant',
5700 
            '\'0\'',
5701 
          ],
5702 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5703 
          'to_register1_dout' => 'to_register1_dout_net',
5704 
          'to_register1_en' => 'constant5_op_net_x0',
5705 
          'to_register20_ce' => 'ce_1_sg',
5706 
          'to_register20_clk' => 'clk_1_sg',
5707 
          'to_register20_clr' => [
5708 
            'constant',
5709 
            '\'0\'',
5710 
          ],
5711 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5712 
          'to_register20_dout' => 'to_register20_dout_net',
5713 
          'to_register20_en' => 'constant5_op_net_x12',
5714 
          'to_register21_ce' => 'ce_1_sg',
5715 
          'to_register21_clk' => 'clk_1_sg',
5716 
          'to_register21_clr' => [
5717 
            'constant',
5718 
            '\'0\'',
5719 
          ],
5720 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5721 
          'to_register21_dout' => 'to_register21_dout_net',
5722 
          'to_register21_en' => 'constant1_op_net_x0',
5723 
          'to_register22_ce' => 'ce_1_sg',
5724 
          'to_register22_clk' => 'clk_1_sg',
5725 
          'to_register22_clr' => [
5726 
            'constant',
5727 
            '\'0\'',
5728 
          ],
5729 
          'to_register22_data_in' => 'reg09_td_net_x0',
5730 
          'to_register22_dout' => 'to_register22_dout_net',
5731 
          'to_register22_en' => 'constant1_op_net_x1',
5732 
          'to_register23_ce' => 'ce_1_sg',
5733 
          'to_register23_clk' => 'clk_1_sg',
5734 
          'to_register23_clr' => [
5735 
            'constant',
5736 
            '\'0\'',
5737 
          ],
5738 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5739 
          'to_register23_dout' => 'to_register23_dout_net',
5740 
          'to_register23_en' => 'constant1_op_net_x2',
5741 
          'to_register24_ce' => 'ce_1_sg',
5742 
          'to_register24_clk' => 'clk_1_sg',
5743 
          'to_register24_clr' => [
5744 
            'constant',
5745 
            '\'0\'',
5746 
          ],
5747 
          'to_register24_data_in' => 'reg10_td_net_x0',
5748 
          'to_register24_dout' => 'to_register24_dout_net',
5749 
          'to_register24_en' => 'constant1_op_net_x3',
5750 
          'to_register25_ce' => 'ce_1_sg',
5751 
          'to_register25_clk' => 'clk_1_sg',
5752 
          'to_register25_clr' => [
5753 
            'constant',
5754 
            '\'0\'',
5755 
          ],
5756 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5757 
          'to_register25_dout' => 'to_register25_dout_net',
5758 
          'to_register25_en' => 'constant1_op_net_x4',
5759 
          'to_register26_ce' => 'ce_1_sg',
5760 
          'to_register26_clk' => 'clk_1_sg',
5761 
          'to_register26_clr' => [
5762 
            'constant',
5763 
            '\'0\'',
5764 
          ],
5765 
          'to_register26_data_in' => 'reg08_td_net_x0',
5766 
          'to_register26_dout' => 'to_register26_dout_net',
5767 
          'to_register26_en' => 'constant1_op_net_x5',
5768 
          'to_register27_ce' => 'ce_1_sg',
5769 
          'to_register27_clk' => 'clk_1_sg',
5770 
          'to_register27_clr' => [
5771 
            'constant',
5772 
            '\'0\'',
5773 
          ],
5774 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5775 
          'to_register27_dout' => 'to_register27_dout_net',
5776 
          'to_register27_en' => 'constant1_op_net_x6',
5777 
          'to_register28_ce' => 'ce_1_sg',
5778 
          'to_register28_clk' => 'clk_1_sg',
5779 
          'to_register28_clr' => [
5780 
            'constant',
5781 
            '\'0\'',
5782 
          ],
5783 
          'to_register28_data_in' => 'reg11_td_net_x0',
5784 
          'to_register28_dout' => 'to_register28_dout_net',
5785 
          'to_register28_en' => 'constant1_op_net_x7',
5786 
          'to_register29_ce' => 'ce_1_sg',
5787 
          'to_register29_clk' => 'clk_1_sg',
5788 
          'to_register29_clr' => [
5789 
            'constant',
5790 
            '\'0\'',
5791 
          ],
5792 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5793 
          'to_register29_dout' => 'to_register29_dout_net',
5794 
          'to_register29_en' => 'constant1_op_net_x8',
5795 
          'to_register2_ce' => 'ce_1_sg',
5796 
          'to_register2_clk' => 'clk_1_sg',
5797 
          'to_register2_clr' => [
5798 
            'constant',
5799 
            '\'0\'',
5800 
          ],
5801 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5802 
          'to_register2_dout' => 'to_register2_dout_net',
5803 
          'to_register2_en' => 'constant5_op_net_x11',
5804 
          'to_register30_ce' => 'ce_1_sg',
5805 
          'to_register30_clk' => 'clk_1_sg',
5806 
          'to_register30_clr' => [
5807 
            'constant',
5808 
            '\'0\'',
5809 
          ],
5810 
          'to_register30_data_in' => 'reg12_td_net_x0',
5811 
          'to_register30_dout' => 'to_register30_dout_net',
5812 
          'to_register30_en' => 'constant1_op_net_x9',
5813 
          'to_register31_ce' => 'ce_1_sg',
5814 
          'to_register31_clk' => 'clk_1_sg',
5815 
          'to_register31_clr' => [
5816 
            'constant',
5817 
            '\'0\'',
5818 
          ],
5819 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5820 
          'to_register31_dout' => 'to_register31_dout_net',
5821 
          'to_register31_en' => 'constant1_op_net_x10',
5822 
          'to_register32_ce' => 'ce_1_sg',
5823 
          'to_register32_clk' => 'clk_1_sg',
5824 
          'to_register32_clr' => [
5825 
            'constant',
5826 
            '\'0\'',
5827 
          ],
5828 
          'to_register32_data_in' => 'reg13_td_net_x0',
5829 
          'to_register32_dout' => 'to_register32_dout_net',
5830 
          'to_register32_en' => 'constant1_op_net_x11',
5831 
          'to_register33_ce' => 'ce_1_sg',
5832 
          'to_register33_clk' => 'clk_1_sg',
5833 
          'to_register33_clr' => [
5834 
            'constant',
5835 
            '\'0\'',
5836 
          ],
5837 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5838 
          'to_register33_dout' => 'to_register33_dout_net',
5839 
          'to_register33_en' => 'constant1_op_net_x12',
5840 
          'to_register34_ce' => 'ce_1_sg',
5841 
          'to_register34_clk' => 'clk_1_sg',
5842 
          'to_register34_clr' => [
5843 
            'constant',
5844 
            '\'0\'',
5845 
          ],
5846 
          'to_register34_data_in' => 'reg14_td_net_x0',
5847 
          'to_register34_dout' => 'to_register34_dout_net',
5848 
          'to_register34_en' => 'constant1_op_net_x13',
5849 
          'to_register3_ce' => 'ce_1_sg',
5850 
          'to_register3_clk' => 'clk_1_sg',
5851 
          'to_register3_clr' => [
5852 
            'constant',
5853 
            '\'0\'',
5854 
          ],
5855 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5856 
          'to_register3_dout' => 'to_register3_dout_net',
5857 
          'to_register3_en' => 'constant5_op_net_x13',
5858 
          'to_register4_ce' => 'ce_1_sg',
5859 
          'to_register4_clk' => 'clk_1_sg',
5860 
          'to_register4_clr' => [
5861 
            'constant',
5862 
            '\'0\'',
5863 
          ],
5864 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5865 
          'to_register4_dout' => 'to_register4_dout_net',
5866 
          'to_register4_en' => 'constant5_op_net_x14',
5867 
          'to_register5_ce' => 'ce_1_sg',
5868 
          'to_register5_clk' => 'clk_1_sg',
5869 
          'to_register5_clr' => [
5870 
            'constant',
5871 
            '\'0\'',
5872 
          ],
5873 
          'to_register5_data_in' => 'reg02_td_net_x0',
5874 
          'to_register5_dout' => 'to_register5_dout_net',
5875 
          'to_register5_en' => 'constant5_op_net_x15',
5876 
          'to_register6_ce' => 'ce_1_sg',
5877 
          'to_register6_clk' => 'clk_1_sg',
5878 
          'to_register6_clr' => [
5879 
            'constant',
5880 
            '\'0\'',
5881 
          ],
5882 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5883 
          'to_register6_dout' => 'to_register6_dout_net',
5884 
          'to_register6_en' => 'constant5_op_net_x16',
5885 
          'to_register7_ce' => 'ce_1_sg',
5886 
          'to_register7_clk' => 'clk_1_sg',
5887 
          'to_register7_clr' => [
5888 
            'constant',
5889 
            '\'0\'',
5890 
          ],
5891 
          'to_register7_data_in' => 'reg01_td_net_x0',
5892 
          'to_register7_dout' => 'to_register7_dout_net',
5893 
          'to_register7_en' => 'constant5_op_net_x17',
5894 
          'to_register8_ce' => 'ce_1_sg',
5895 
          'to_register8_clk' => 'clk_1_sg',
5896 
          'to_register8_clr' => [
5897 
            'constant',
5898 
            '\'0\'',
5899 
          ],
5900 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5901 
          'to_register8_dout' => 'to_register8_dout_net',
5902 
          'to_register8_en' => 'constant5_op_net_x18',
5903 
          'to_register9_ce' => 'ce_1_sg',
5904 
          'to_register9_clk' => 'clk_1_sg',
5905 
          'to_register9_clr' => [
5906 
            'constant',
5907 
            '\'0\'',
5908 
          ],
5909 
          'to_register9_data_in' => 'reg03_td_net_x0',
5910 
          'to_register9_dout' => 'to_register9_dout_net',
5911 
          'to_register9_en' => 'constant5_op_net_x19',
5912 
        },
5913 
        'entityName' => 'inout_logic_cw',
5914 
        'nets' => {
5915 
          'ce_1_sg' => {
5916 
            'attributes' => {
5917 
              'hdlNetAttributes' => [
5918 
                [
5919 
                  'MAX_FANOUT',
5920 
                  'string',
5921 
                  '"REDUCE"',
5922 
                ],
5923 
              ],
5924 
            },
5925 
            'hdlType' => 'std_logic',
5926 
            'width' => 1,
5927 
          },
5928 
          'clkNet' => {
5929 
            'attributes' => {
5930 
              'hdlNetAttributes' => [
5931 
              ],
5932 
            },
5933 
            'hdlType' => 'std_logic',
5934 
            'width' => 1,
5935 
          },
5936 
          'clk_1_sg' => {
5937 
            'attributes' => {
5938 
              'hdlNetAttributes' => [
5939 
              ],
5940 
            },
5941 
            'hdlType' => 'std_logic',
5942 
            'width' => 1,
5943 
          },
5944 
          'constant1_op_net_x0' => {
5945 
            'attributes' => {
5946 
              'hdlNetAttributes' => [
5947 
              ],
5948 
            },
5949 
            'hdlType' => 'std_logic',
5950 
            'width' => 1,
5951 
          },
5952 
          'constant1_op_net_x1' => {
5953 
            'attributes' => {
5954 
              'hdlNetAttributes' => [
5955 
              ],
5956 
            },
5957 
            'hdlType' => 'std_logic',
5958 
            'width' => 1,
5959 
          },
5960 
          'constant1_op_net_x10' => {
5961 
            'attributes' => {
5962 
              'hdlNetAttributes' => [
5963 
              ],
5964 
            },
5965 
            'hdlType' => 'std_logic',
5966 
            'width' => 1,
5967 
          },
5968 
          'constant1_op_net_x11' => {
5969 
            'attributes' => {
5970 
              'hdlNetAttributes' => [
5971 
              ],
5972 
            },
5973 
            'hdlType' => 'std_logic',
5974 
            'width' => 1,
5975 
          },
5976 
          'constant1_op_net_x12' => {
5977 
            'attributes' => {
5978 
              'hdlNetAttributes' => [
5979 
              ],
5980 
            },
5981 
            'hdlType' => 'std_logic',
5982 
            'width' => 1,
5983 
          },
5984 
          'constant1_op_net_x13' => {
5985 
            'attributes' => {
5986 
              'hdlNetAttributes' => [
5987 
              ],
5988 
            },
5989 
            'hdlType' => 'std_logic',
5990 
            'width' => 1,
5991 
          },
5992 
          'constant1_op_net_x2' => {
5993 
            'attributes' => {
5994 
              'hdlNetAttributes' => [
5995 
              ],
5996 
            },
5997 
            'hdlType' => 'std_logic',
5998 
            'width' => 1,
5999 
          },
6000 
          'constant1_op_net_x3' => {
6001 
            'attributes' => {
6002 
              'hdlNetAttributes' => [
6003 
              ],
6004 
            },
6005 
            'hdlType' => 'std_logic',
6006 
            'width' => 1,
6007 
          },
6008 
          'constant1_op_net_x4' => {
6009 
            'attributes' => {
6010 
              'hdlNetAttributes' => [
6011 
              ],
6012 
            },
6013 
            'hdlType' => 'std_logic',
6014 
            'width' => 1,
6015 
          },
6016 
          'constant1_op_net_x5' => {
6017 
            'attributes' => {
6018 
              'hdlNetAttributes' => [
6019 
              ],
6020 
            },
6021 
            'hdlType' => 'std_logic',
6022 
            'width' => 1,
6023 
          },
6024 
          'constant1_op_net_x6' => {
6025 
            'attributes' => {
6026 
              'hdlNetAttributes' => [
6027 
              ],
6028 
            },
6029 
            'hdlType' => 'std_logic',
6030 
            'width' => 1,
6031 
          },
6032 
          'constant1_op_net_x7' => {
6033 
            'attributes' => {
6034 
              'hdlNetAttributes' => [
6035 
              ],
6036 
            },
6037 
            'hdlType' => 'std_logic',
6038 
            'width' => 1,
6039 
          },
6040 
          'constant1_op_net_x8' => {
6041 
            'attributes' => {
6042 
              'hdlNetAttributes' => [
6043 
              ],
6044 
            },
6045 
            'hdlType' => 'std_logic',
6046 
            'width' => 1,
6047 
          },
6048 
          'constant1_op_net_x9' => {
6049 
            'attributes' => {
6050 
              'hdlNetAttributes' => [
6051 
              ],
6052 
            },
6053 
            'hdlType' => 'std_logic',
6054 
            'width' => 1,
6055 
          },
6056 
          'constant5_op_net_x0' => {
6057 
            'attributes' => {
6058 
              'hdlNetAttributes' => [
6059 
              ],
6060 
            },
6061 
            'hdlType' => 'std_logic',
6062 
            'width' => 1,
6063 
          },
6064 
          'constant5_op_net_x1' => {
6065 
            'attributes' => {
6066 
              'hdlNetAttributes' => [
6067 
              ],
6068 
            },
6069 
            'hdlType' => 'std_logic',
6070 
            'width' => 1,
6071 
          },
6072 
          'constant5_op_net_x10' => {
6073 
            'attributes' => {
6074 
              'hdlNetAttributes' => [
6075 
              ],
6076 
            },
6077 
            'hdlType' => 'std_logic',
6078 
            'width' => 1,
6079 
          },
6080 
          'constant5_op_net_x11' => {
6081 
            'attributes' => {
6082 
              'hdlNetAttributes' => [
6083 
              ],
6084 
            },
6085 
            'hdlType' => 'std_logic',
6086 
            'width' => 1,
6087 
          },
6088 
          'constant5_op_net_x12' => {
6089 
            'attributes' => {
6090 
              'hdlNetAttributes' => [
6091 
              ],
6092 
            },
6093 
            'hdlType' => 'std_logic',
6094 
            'width' => 1,
6095 
          },
6096 
          'constant5_op_net_x13' => {
6097 
            'attributes' => {
6098 
              'hdlNetAttributes' => [
6099 
              ],
6100 
            },
6101 
            'hdlType' => 'std_logic',
6102 
            'width' => 1,
6103 
          },
6104 
          'constant5_op_net_x14' => {
6105 
            'attributes' => {
6106 
              'hdlNetAttributes' => [
6107 
              ],
6108 
            },
6109 
            'hdlType' => 'std_logic',
6110 
            'width' => 1,
6111 
          },
6112 
          'constant5_op_net_x15' => {
6113 
            'attributes' => {
6114 
              'hdlNetAttributes' => [
6115 
              ],
6116 
            },
6117 
            'hdlType' => 'std_logic',
6118 
            'width' => 1,
6119 
          },
6120 
          'constant5_op_net_x16' => {
6121 
            'attributes' => {
6122 
              'hdlNetAttributes' => [
6123 
              ],
6124 
            },
6125 
            'hdlType' => 'std_logic',
6126 
            'width' => 1,
6127 
          },
6128 
          'constant5_op_net_x17' => {
6129 
            'attributes' => {
6130 
              'hdlNetAttributes' => [
6131 
              ],
6132 
            },
6133 
            'hdlType' => 'std_logic',
6134 
            'width' => 1,
6135 
          },
6136 
          'constant5_op_net_x18' => {
6137 
            'attributes' => {
6138 
              'hdlNetAttributes' => [
6139 
              ],
6140 
            },
6141 
            'hdlType' => 'std_logic',
6142 
            'width' => 1,
6143 
          },
6144 
          'constant5_op_net_x19' => {
6145 
            'attributes' => {
6146 
              'hdlNetAttributes' => [
6147 
              ],
6148 
            },
6149 
            'hdlType' => 'std_logic',
6150 
            'width' => 1,
6151 
          },
6152 
          'constant5_op_net_x2' => {
6153 
            'attributes' => {
6154 
              'hdlNetAttributes' => [
6155 
              ],
6156 
            },
6157 
            'hdlType' => 'std_logic',
6158 
            'width' => 1,
6159 
          },
6160 
          'constant5_op_net_x3' => {
6161 
            'attributes' => {
6162 
              'hdlNetAttributes' => [
6163 
              ],
6164 
            },
6165 
            'hdlType' => 'std_logic',
6166 
            'width' => 1,
6167 
          },
6168 
          'constant5_op_net_x4' => {
6169 
            'attributes' => {
6170 
              'hdlNetAttributes' => [
6171 
              ],
6172 
            },
6173 
            'hdlType' => 'std_logic',
6174 
            'width' => 1,
6175 
          },
6176 
          'constant5_op_net_x5' => {
6177 
            'attributes' => {
6178 
              'hdlNetAttributes' => [
6179 
              ],
6180 
            },
6181 
            'hdlType' => 'std_logic',
6182 
            'width' => 1,
6183 
          },
6184 
          'constant5_op_net_x6' => {
6185 
            'attributes' => {
6186 
              'hdlNetAttributes' => [
6187 
              ],
6188 
            },
6189 
            'hdlType' => 'std_logic',
6190 
            'width' => 1,
6191 
          },
6192 
          'constant5_op_net_x7' => {
6193 
            'attributes' => {
6194 
              'hdlNetAttributes' => [
6195 
              ],
6196 
            },
6197 
            'hdlType' => 'std_logic',
6198 
            'width' => 1,
6199 
          },
6200 
          'constant5_op_net_x8' => {
6201 
            'attributes' => {
6202 
              'hdlNetAttributes' => [
6203 
              ],
6204 
            },
6205 
            'hdlType' => 'std_logic',
6206 
            'width' => 1,
6207 
          },
6208 
          'constant5_op_net_x9' => {
6209 
            'attributes' => {
6210 
              'hdlNetAttributes' => [
6211 
              ],
6212 
            },
6213 
            'hdlType' => 'std_logic',
6214 
            'width' => 1,
6215 
          },
6216 
          'debug_in_1i_net' => {
6217 
            'attributes' => {
6218 
              'hdlNetAttributes' => [
6219 
              ],
6220 
            },
6221 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6222 
            'width' => 32,
6223 
          },
6224 
          'debug_in_1i_net_x0' => {
6225 
            'attributes' => {
6226 
              'hdlNetAttributes' => [
6227 
              ],
6228 
            },
6229 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6230 
            'width' => 32,
6231 
          },
6232 
          'debug_in_2i_net' => {
6233 
            'attributes' => {
6234 
              'hdlNetAttributes' => [
6235 
              ],
6236 
            },
6237 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6238 
            'width' => 32,
6239 
          },
6240 
          'debug_in_2i_net_x0' => {
6241 
            'attributes' => {
6242 
              'hdlNetAttributes' => [
6243 
              ],
6244 
            },
6245 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6246 
            'width' => 32,
6247 
          },
6248 
          'debug_in_3i_net' => {
6249 
            'attributes' => {
6250 
              'hdlNetAttributes' => [
6251 
              ],
6252 
            },
6253 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6254 
            'width' => 32,
6255 
          },
6256 
          'debug_in_3i_net_x0' => {
6257 
            'attributes' => {
6258 
              'hdlNetAttributes' => [
6259 
              ],
6260 
            },
6261 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6262 
            'width' => 32,
6263 
          },
6264 
          'debug_in_4i_net' => {
6265 
            'attributes' => {
6266 
              'hdlNetAttributes' => [
6267 
              ],
6268 
            },
6269 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6270 
            'width' => 32,
6271 
          },
6272 
          'debug_in_4i_net_x0' => {
6273 
            'attributes' => {
6274 
              'hdlNetAttributes' => [
6275 
              ],
6276 
            },
6277 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6278 
            'width' => 32,
6279 
          },
6280 
          'dma_host2board_busy_net' => {
6281 
            'attributes' => {
6282 
              'hdlNetAttributes' => [
6283 
              ],
6284 
            },
6285 
            'hdlType' => 'std_logic',
6286 
            'width' => 1,
6287 
          },
6288 
          'dma_host2board_busy_net_x0' => {
6289 
            'attributes' => {
6290 
              'hdlNetAttributes' => [
6291 
              ],
6292 
            },
6293 
            'hdlType' => 'std_logic',
6294 
            'width' => 1,
6295 
          },
6296 
          'dma_host2board_done_net' => {
6297 
            'attributes' => {
6298 
              'hdlNetAttributes' => [
6299 
              ],
6300 
            },
6301 
            'hdlType' => 'std_logic',
6302 
            'width' => 1,
6303 
          },
6304 
          'dma_host2board_done_net_x0' => {
6305 
            'attributes' => {
6306 
              'hdlNetAttributes' => [
6307 
              ],
6308 
            },
6309 
            'hdlType' => 'std_logic',
6310 
            'width' => 1,
6311 
          },
6312 
          'from_register10_data_out_net' => {
6313 
            'attributes' => {
6314 
              'hdlNetAttributes' => [
6315 
              ],
6316 
            },
6317 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6318 
            'width' => 32,
6319 
          },
6320 
          'from_register10_data_out_net_x0' => {
6321 
            'attributes' => {
6322 
              'hdlNetAttributes' => [
6323 
              ],
6324 
            },
6325 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6326 
            'width' => 32,
6327 
          },
6328 
          'from_register11_data_out_net' => {
6329 
            'attributes' => {
6330 
              'hdlNetAttributes' => [
6331 
              ],
6332 
            },
6333 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6334 
            'width' => 32,
6335 
          },
6336 
          'from_register11_data_out_net_x0' => {
6337 
            'attributes' => {
6338 
              'hdlNetAttributes' => [
6339 
              ],
6340 
            },
6341 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6342 
            'width' => 32,
6343 
          },
6344 
          'from_register12_data_out_net' => {
6345 
            'attributes' => {
6346 
              'hdlNetAttributes' => [
6347 
              ],
6348 
            },
6349 
            'hdlType' => 'std_logic',
6350 
            'width' => 1,
6351 
          },
6352 
          'from_register12_data_out_net_x0' => {
6353 
            'attributes' => {
6354 
              'hdlNetAttributes' => [
6355 
              ],
6356 
            },
6357 
            'hdlType' => 'std_logic',
6358 
            'width' => 1,
6359 
          },
6360 
          'from_register13_data_out_net' => {
6361 
            'attributes' => {
6362 
              'hdlNetAttributes' => [
6363 
              ],
6364 
            },
6365 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6366 
            'width' => 32,
6367 
          },
6368 
          'from_register13_data_out_net_x0' => {
6369 
            'attributes' => {
6370 
              'hdlNetAttributes' => [
6371 
              ],
6372 
            },
6373 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6374 
            'width' => 32,
6375 
          },
6376 
          'from_register14_data_out_net' => {
6377 
            'attributes' => {
6378 
              'hdlNetAttributes' => [
6379 
              ],
6380 
            },
6381 
            'hdlType' => 'std_logic',
6382 
            'width' => 1,
6383 
          },
6384 
          'from_register14_data_out_net_x0' => {
6385 
            'attributes' => {
6386 
              'hdlNetAttributes' => [
6387 
              ],
6388 
            },
6389 
            'hdlType' => 'std_logic',
6390 
            'width' => 1,
6391 
          },
6392 
          'from_register15_data_out_net' => {
6393 
            'attributes' => {
6394 
              'hdlNetAttributes' => [
6395 
              ],
6396 
            },
6397 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6398 
            'width' => 32,
6399 
          },
6400 
          'from_register15_data_out_net_x0' => {
6401 
            'attributes' => {
6402 
              'hdlNetAttributes' => [
6403 
              ],
6404 
            },
6405 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6406 
            'width' => 32,
6407 
          },
6408 
          'from_register16_data_out_net' => {
6409 
            'attributes' => {
6410 
              'hdlNetAttributes' => [
6411 
              ],
6412 
            },
6413 
            'hdlType' => 'std_logic',
6414 
            'width' => 1,
6415 
          },
6416 
          'from_register16_data_out_net_x0' => {
6417 
            'attributes' => {
6418 
              'hdlNetAttributes' => [
6419 
              ],
6420 
            },
6421 
            'hdlType' => 'std_logic',
6422 
            'width' => 1,
6423 
          },
6424 
          'from_register17_data_out_net' => {
6425 
            'attributes' => {
6426 
              'hdlNetAttributes' => [
6427 
              ],
6428 
            },
6429 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6430 
            'width' => 32,
6431 
          },
6432 
          'from_register17_data_out_net_x0' => {
6433 
            'attributes' => {
6434 
              'hdlNetAttributes' => [
6435 
              ],
6436 
            },
6437 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6438 
            'width' => 32,
6439 
          },
6440 
          'from_register18_data_out_net' => {
6441 
            'attributes' => {
6442 
              'hdlNetAttributes' => [
6443 
              ],
6444 
            },
6445 
            'hdlType' => 'std_logic',
6446 
            'width' => 1,
6447 
          },
6448 
          'from_register18_data_out_net_x0' => {
6449 
            'attributes' => {
6450 
              'hdlNetAttributes' => [
6451 
              ],
6452 
            },
6453 
            'hdlType' => 'std_logic',
6454 
            'width' => 1,
6455 
          },
6456 
          'from_register19_data_out_net' => {
6457 
            'attributes' => {
6458 
              'hdlNetAttributes' => [
6459 
              ],
6460 
            },
6461 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6462 
            'width' => 32,
6463 
          },
6464 
          'from_register19_data_out_net_x0' => {
6465 
            'attributes' => {
6466 
              'hdlNetAttributes' => [
6467 
              ],
6468 
            },
6469 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6470 
            'width' => 32,
6471 
          },
6472 
          'from_register1_data_out_net' => {
6473 
            'attributes' => {
6474 
              'hdlNetAttributes' => [
6475 
              ],
6476 
            },
6477 
            'hdlType' => 'std_logic',
6478 
            'width' => 1,
6479 
          },
6480 
          'from_register1_data_out_net_x0' => {
6481 
            'attributes' => {
6482 
              'hdlNetAttributes' => [
6483 
              ],
6484 
            },
6485 
            'hdlType' => 'std_logic',
6486 
            'width' => 1,
6487 
          },
6488 
          'from_register20_data_out_net' => {
6489 
            'attributes' => {
6490 
              'hdlNetAttributes' => [
6491 
              ],
6492 
            },
6493 
            'hdlType' => 'std_logic',
6494 
            'width' => 1,
6495 
          },
6496 
          'from_register20_data_out_net_x0' => {
6497 
            'attributes' => {
6498 
              'hdlNetAttributes' => [
6499 
              ],
6500 
            },
6501 
            'hdlType' => 'std_logic',
6502 
            'width' => 1,
6503 
          },
6504 
          'from_register21_data_out_net' => {
6505 
            'attributes' => {
6506 
              'hdlNetAttributes' => [
6507 
              ],
6508 
            },
6509 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6510 
            'width' => 32,
6511 
          },
6512 
          'from_register21_data_out_net_x0' => {
6513 
            'attributes' => {
6514 
              'hdlNetAttributes' => [
6515 
              ],
6516 
            },
6517 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6518 
            'width' => 32,
6519 
          },
6520 
          'from_register22_data_out_net' => {
6521 
            'attributes' => {
6522 
              'hdlNetAttributes' => [
6523 
              ],
6524 
            },
6525 
            'hdlType' => 'std_logic',
6526 
            'width' => 1,
6527 
          },
6528 
          'from_register22_data_out_net_x0' => {
6529 
            'attributes' => {
6530 
              'hdlNetAttributes' => [
6531 
              ],
6532 
            },
6533 
            'hdlType' => 'std_logic',
6534 
            'width' => 1,
6535 
          },
6536 
          'from_register23_data_out_net' => {
6537 
            'attributes' => {
6538 
              'hdlNetAttributes' => [
6539 
              ],
6540 
            },
6541 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6542 
            'width' => 32,
6543 
          },
6544 
          'from_register23_data_out_net_x0' => {
6545 
            'attributes' => {
6546 
              'hdlNetAttributes' => [
6547 
              ],
6548 
            },
6549 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6550 
            'width' => 32,
6551 
          },
6552 
          'from_register24_data_out_net' => {
6553 
            'attributes' => {
6554 
              'hdlNetAttributes' => [
6555 
              ],
6556 
            },
6557 
            'hdlType' => 'std_logic',
6558 
            'width' => 1,
6559 
          },
6560 
          'from_register24_data_out_net_x0' => {
6561 
            'attributes' => {
6562 
              'hdlNetAttributes' => [
6563 
              ],
6564 
            },
6565 
            'hdlType' => 'std_logic',
6566 
            'width' => 1,
6567 
          },
6568 
          'from_register25_data_out_net' => {
6569 
            'attributes' => {
6570 
              'hdlNetAttributes' => [
6571 
              ],
6572 
            },
6573 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6574 
            'width' => 32,
6575 
          },
6576 
          'from_register25_data_out_net_x0' => {
6577 
            'attributes' => {
6578 
              'hdlNetAttributes' => [
6579 
              ],
6580 
            },
6581 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6582 
            'width' => 32,
6583 
          },
6584 
          'from_register26_data_out_net' => {
6585 
            'attributes' => {
6586 
              'hdlNetAttributes' => [
6587 
              ],
6588 
            },
6589 
            'hdlType' => 'std_logic',
6590 
            'width' => 1,
6591 
          },
6592 
          'from_register26_data_out_net_x0' => {
6593 
            'attributes' => {
6594 
              'hdlNetAttributes' => [
6595 
              ],
6596 
            },
6597 
            'hdlType' => 'std_logic',
6598 
            'width' => 1,
6599 
          },
6600 
          'from_register27_data_out_net' => {
6601 
            'attributes' => {
6602 
              'hdlNetAttributes' => [
6603 
              ],
6604 
            },
6605 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6606 
            'width' => 32,
6607 
          },
6608 
          'from_register27_data_out_net_x0' => {
6609 
            'attributes' => {
6610 
              'hdlNetAttributes' => [
6611 
              ],
6612 
            },
6613 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6614 
            'width' => 32,
6615 
          },
6616 
          'from_register28_data_out_net' => {
6617 
            'attributes' => {
6618 
              'hdlNetAttributes' => [
6619 
              ],
6620 
            },
6621 
            'hdlType' => 'std_logic',
6622 
            'width' => 1,
6623 
          },
6624 
          'from_register28_data_out_net_x0' => {
6625 
            'attributes' => {
6626 
              'hdlNetAttributes' => [
6627 
              ],
6628 
            },
6629 
            'hdlType' => 'std_logic',
6630 
            'width' => 1,
6631 
          },
6632 
          'from_register2_data_out_net' => {
6633 
            'attributes' => {
6634 
              'hdlNetAttributes' => [
6635 
              ],
6636 
            },
6637 
            'hdlType' => 'std_logic',
6638 
            'width' => 1,
6639 
          },
6640 
          'from_register2_data_out_net_x0' => {
6641 
            'attributes' => {
6642 
              'hdlNetAttributes' => [
6643 
              ],
6644 
            },
6645 
            'hdlType' => 'std_logic',
6646 
            'width' => 1,
6647 
          },
6648 
          'from_register3_data_out_net' => {
6649 
            'attributes' => {
6650 
              'hdlNetAttributes' => [
6651 
              ],
6652 
            },
6653 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6654 
            'width' => 32,
6655 
          },
6656 
          'from_register3_data_out_net_x0' => {
6657 
            'attributes' => {
6658 
              'hdlNetAttributes' => [
6659 
              ],
6660 
            },
6661 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6662 
            'width' => 32,
6663 
          },
6664 
          'from_register4_data_out_net' => {
6665 
            'attributes' => {
6666 
              'hdlNetAttributes' => [
6667 
              ],
6668 
            },
6669 
            'hdlType' => 'std_logic',
6670 
            'width' => 1,
6671 
          },
6672 
          'from_register4_data_out_net_x0' => {
6673 
            'attributes' => {
6674 
              'hdlNetAttributes' => [
6675 
              ],
6676 
            },
6677 
            'hdlType' => 'std_logic',
6678 
            'width' => 1,
6679 
          },
6680 
          'from_register5_data_out_net' => {
6681 
            'attributes' => {
6682 
              'hdlNetAttributes' => [
6683 
              ],
6684 
            },
6685 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6686 
            'width' => 32,
6687 
          },
6688 
          'from_register5_data_out_net_x0' => {
6689 
            'attributes' => {
6690 
              'hdlNetAttributes' => [
6691 
              ],
6692 
            },
6693 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6694 
            'width' => 32,
6695 
          },
6696 
          'from_register6_data_out_net' => {
6697 
            'attributes' => {
6698 
              'hdlNetAttributes' => [
6699 
              ],
6700 
            },
6701 
            'hdlType' => 'std_logic',
6702 
            'width' => 1,
6703 
          },
6704 
          'from_register6_data_out_net_x0' => {
6705 
            'attributes' => {
6706 
              'hdlNetAttributes' => [
6707 
              ],
6708 
            },
6709 
            'hdlType' => 'std_logic',
6710 
            'width' => 1,
6711 
          },
6712 
          'from_register7_data_out_net' => {
6713 
            'attributes' => {
6714 
              'hdlNetAttributes' => [
6715 
              ],
6716 
            },
6717 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6718 
            'width' => 32,
6719 
          },
6720 
          'from_register7_data_out_net_x0' => {
6721 
            'attributes' => {
6722 
              'hdlNetAttributes' => [
6723 
              ],
6724 
            },
6725 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6726 
            'width' => 32,
6727 
          },
6728 
          'from_register8_data_out_net' => {
6729 
            'attributes' => {
6730 
              'hdlNetAttributes' => [
6731 
              ],
6732 
            },
6733 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6734 
            'width' => 32,
6735 
          },
6736 
          'from_register8_data_out_net_x0' => {
6737 
            'attributes' => {
6738 
              'hdlNetAttributes' => [
6739 
              ],
6740 
            },
6741 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6742 
            'width' => 32,
6743 
          },
6744 
          'from_register9_data_out_net' => {
6745 
            'attributes' => {
6746 
              'hdlNetAttributes' => [
6747 
              ],
6748 
            },
6749 
            'hdlType' => 'std_logic',
6750 
            'width' => 1,
6751 
          },
6752 
          'from_register9_data_out_net_x0' => {
6753 
            'attributes' => {
6754 
              'hdlNetAttributes' => [
6755 
              ],
6756 
            },
6757 
            'hdlType' => 'std_logic',
6758 
            'width' => 1,
6759 
          },
6760 
          'persistentdff_inst_q' => {
6761 
            'attributes' => {
6762 
              'hdlNetAttributes' => [
6763 
                [
6764 
                  'syn_keep',
6765 
                  'boolean',
6766 
                  'true',
6767 
                ],
6768 
                [
6769 
                  'keep',
6770 
                  'boolean',
6771 
                  'true',
6772 
                ],
6773 
                [
6774 
                  'preserve_signal',
6775 
                  'boolean',
6776 
                  'true',
6777 
                ],
6778 
              ],
6779 
            },
6780 
            'hdlType' => 'std_logic',
6781 
            'width' => 1,
6782 
          },
6783 
          'reg01_td_net' => {
6784 
            'attributes' => {
6785 
              'hdlNetAttributes' => [
6786 
              ],
6787 
            },
6788 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6789 
            'width' => 32,
6790 
          },
6791 
          'reg01_td_net_x0' => {
6792 
            'attributes' => {
6793 
              'hdlNetAttributes' => [
6794 
              ],
6795 
            },
6796 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6797 
            'width' => 32,
6798 
          },
6799 
          'reg01_tv_net' => {
6800 
            'attributes' => {
6801 
              'hdlNetAttributes' => [
6802 
              ],
6803 
            },
6804 
            'hdlType' => 'std_logic',
6805 
            'width' => 1,
6806 
          },
6807 
          'reg01_tv_net_x0' => {
6808 
            'attributes' => {
6809 
              'hdlNetAttributes' => [
6810 
              ],
6811 
            },
6812 
            'hdlType' => 'std_logic',
6813 
            'width' => 1,
6814 
          },
6815 
          'reg02_td_net' => {
6816 
            'attributes' => {
6817 
              'hdlNetAttributes' => [
6818 
              ],
6819 
            },
6820 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6821 
            'width' => 32,
6822 
          },
6823 
          'reg02_td_net_x0' => {
6824 
            'attributes' => {
6825 
              'hdlNetAttributes' => [
6826 
              ],
6827 
            },
6828 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6829 
            'width' => 32,
6830 
          },
6831 
          'reg02_tv_net' => {
6832 
            'attributes' => {
6833 
              'hdlNetAttributes' => [
6834 
              ],
6835 
            },
6836 
            'hdlType' => 'std_logic',
6837 
            'width' => 1,
6838 
          },
6839 
          'reg02_tv_net_x0' => {
6840 
            'attributes' => {
6841 
              'hdlNetAttributes' => [
6842 
              ],
6843 
            },
6844 
            'hdlType' => 'std_logic',
6845 
            'width' => 1,
6846 
          },
6847 
          'reg03_td_net' => {
6848 
            'attributes' => {
6849 
              'hdlNetAttributes' => [
6850 
              ],
6851 
            },
6852 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6853 
            'width' => 32,
6854 
          },
6855 
          'reg03_td_net_x0' => {
6856 
            'attributes' => {
6857 
              'hdlNetAttributes' => [
6858 
              ],
6859 
            },
6860 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6861 
            'width' => 32,
6862 
          },
6863 
          'reg03_tv_net' => {
6864 
            'attributes' => {
6865 
              'hdlNetAttributes' => [
6866 
              ],
6867 
            },
6868 
            'hdlType' => 'std_logic',
6869 
            'width' => 1,
6870 
          },
6871 
          'reg03_tv_net_x0' => {
6872 
            'attributes' => {
6873 
              'hdlNetAttributes' => [
6874 
              ],
6875 
            },
6876 
            'hdlType' => 'std_logic',
6877 
            'width' => 1,
6878 
          },
6879 
          'reg04_td_net' => {
6880 
            'attributes' => {
6881 
              'hdlNetAttributes' => [
6882 
              ],
6883 
            },
6884 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6885 
            'width' => 32,
6886 
          },
6887 
          'reg04_td_net_x0' => {
6888 
            'attributes' => {
6889 
              'hdlNetAttributes' => [
6890 
              ],
6891 
            },
6892 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6893 
            'width' => 32,
6894 
          },
6895 
          'reg04_tv_net' => {
6896 
            'attributes' => {
6897 
              'hdlNetAttributes' => [
6898 
              ],
6899 
            },
6900 
            'hdlType' => 'std_logic',
6901 
            'width' => 1,
6902 
          },
6903 
          'reg04_tv_net_x0' => {
6904 
            'attributes' => {
6905 
              'hdlNetAttributes' => [
6906 
              ],
6907 
            },
6908 
            'hdlType' => 'std_logic',
6909 
            'width' => 1,
6910 
          },
6911 
          'reg05_td_net' => {
6912 
            'attributes' => {
6913 
              'hdlNetAttributes' => [
6914 
              ],
6915 
            },
6916 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6917 
            'width' => 32,
6918 
          },
6919 
          'reg05_td_net_x0' => {
6920 
            'attributes' => {
6921 
              'hdlNetAttributes' => [
6922 
              ],
6923 
            },
6924 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6925 
            'width' => 32,
6926 
          },
6927 
          'reg05_tv_net' => {
6928 
            'attributes' => {
6929 
              'hdlNetAttributes' => [
6930 
              ],
6931 
            },
6932 
            'hdlType' => 'std_logic',
6933 
            'width' => 1,
6934 
          },
6935 
          'reg05_tv_net_x0' => {
6936 
            'attributes' => {
6937 
              'hdlNetAttributes' => [
6938 
              ],
6939 
            },
6940 
            'hdlType' => 'std_logic',
6941 
            'width' => 1,
6942 
          },
6943 
          'reg06_td_net' => {
6944 
            'attributes' => {
6945 
              'hdlNetAttributes' => [
6946 
              ],
6947 
            },
6948 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6949 
            'width' => 32,
6950 
          },
6951 
          'reg06_td_net_x0' => {
6952 
            'attributes' => {
6953 
              'hdlNetAttributes' => [
6954 
              ],
6955 
            },
6956 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6957 
            'width' => 32,
6958 
          },
6959 
          'reg06_tv_net' => {
6960 
            'attributes' => {
6961 
              'hdlNetAttributes' => [
6962 
              ],
6963 
            },
6964 
            'hdlType' => 'std_logic',
6965 
            'width' => 1,
6966 
          },
6967 
          'reg06_tv_net_x0' => {
6968 
            'attributes' => {
6969 
              'hdlNetAttributes' => [
6970 
              ],
6971 
            },
6972 
            'hdlType' => 'std_logic',
6973 
            'width' => 1,
6974 
          },
6975 
          'reg07_td_net' => {
6976 
            'attributes' => {
6977 
              'hdlNetAttributes' => [
6978 
              ],
6979 
            },
6980 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6981 
            'width' => 32,
6982 
          },
6983 
          'reg07_td_net_x0' => {
6984 
            'attributes' => {
6985 
              'hdlNetAttributes' => [
6986 
              ],
6987 
            },
6988 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6989 
            'width' => 32,
6990 
          },
6991 
          'reg07_tv_net' => {
6992 
            'attributes' => {
6993 
              'hdlNetAttributes' => [
6994 
              ],
6995 
            },
6996 
            'hdlType' => 'std_logic',
6997 
            'width' => 1,
6998 
          },
6999 
          'reg07_tv_net_x0' => {
7000 
            'attributes' => {
7001 
              'hdlNetAttributes' => [
7002 
              ],
7003 
            },
7004 
            'hdlType' => 'std_logic',
7005 
            'width' => 1,
7006 
          },
7007 
          'reg08_td_net' => {
7008 
            'attributes' => {
7009 
              'hdlNetAttributes' => [
7010 
              ],
7011 
            },
7012 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7013 
            'width' => 32,
7014 
          },
7015 
          'reg08_td_net_x0' => {
7016 
            'attributes' => {
7017 
              'hdlNetAttributes' => [
7018 
              ],
7019 
            },
7020 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7021 
            'width' => 32,
7022 
          },
7023 
          'reg08_tv_net' => {
7024 
            'attributes' => {
7025 
              'hdlNetAttributes' => [
7026 
              ],
7027 
            },
7028 
            'hdlType' => 'std_logic',
7029 
            'width' => 1,
7030 
          },
7031 
          'reg08_tv_net_x0' => {
7032 
            'attributes' => {
7033 
              'hdlNetAttributes' => [
7034 
              ],
7035 
            },
7036 
            'hdlType' => 'std_logic',
7037 
            'width' => 1,
7038 
          },
7039 
          'reg09_td_net' => {
7040 
            'attributes' => {
7041 
              'hdlNetAttributes' => [
7042 
              ],
7043 
            },
7044 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7045 
            'width' => 32,
7046 
          },
7047 
          'reg09_td_net_x0' => {
7048 
            'attributes' => {
7049 
              'hdlNetAttributes' => [
7050 
              ],
7051 
            },
7052 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7053 
            'width' => 32,
7054 
          },
7055 
          'reg09_tv_net' => {
7056 
            'attributes' => {
7057 
              'hdlNetAttributes' => [
7058 
              ],
7059 
            },
7060 
            'hdlType' => 'std_logic',
7061 
            'width' => 1,
7062 
          },
7063 
          'reg09_tv_net_x0' => {
7064 
            'attributes' => {
7065 
              'hdlNetAttributes' => [
7066 
              ],
7067 
            },
7068 
            'hdlType' => 'std_logic',
7069 
            'width' => 1,
7070 
          },
7071 
          'reg10_td_net' => {
7072 
            'attributes' => {
7073 
              'hdlNetAttributes' => [
7074 
              ],
7075 
            },
7076 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7077 
            'width' => 32,
7078 
          },
7079 
          'reg10_td_net_x0' => {
7080 
            'attributes' => {
7081 
              'hdlNetAttributes' => [
7082 
              ],
7083 
            },
7084 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7085 
            'width' => 32,
7086 
          },
7087 
          'reg10_tv_net' => {
7088 
            'attributes' => {
7089 
              'hdlNetAttributes' => [
7090 
              ],
7091 
            },
7092 
            'hdlType' => 'std_logic',
7093 
            'width' => 1,
7094 
          },
7095 
          'reg10_tv_net_x0' => {
7096 
            'attributes' => {
7097 
              'hdlNetAttributes' => [
7098 
              ],
7099 
            },
7100 
            'hdlType' => 'std_logic',
7101 
            'width' => 1,
7102 
          },
7103 
          'reg11_td_net' => {
7104 
            'attributes' => {
7105 
              'hdlNetAttributes' => [
7106 
              ],
7107 
            },
7108 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7109 
            'width' => 32,
7110 
          },
7111 
          'reg11_td_net_x0' => {
7112 
            'attributes' => {
7113 
              'hdlNetAttributes' => [
7114 
              ],
7115 
            },
7116 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7117 
            'width' => 32,
7118 
          },
7119 
          'reg11_tv_net' => {
7120 
            'attributes' => {
7121 
              'hdlNetAttributes' => [
7122 
              ],
7123 
            },
7124 
            'hdlType' => 'std_logic',
7125 
            'width' => 1,
7126 
          },
7127 
          'reg11_tv_net_x0' => {
7128 
            'attributes' => {
7129 
              'hdlNetAttributes' => [
7130 
              ],
7131 
            },
7132 
            'hdlType' => 'std_logic',
7133 
            'width' => 1,
7134 
          },
7135 
          'reg12_td_net' => {
7136 
            'attributes' => {
7137 
              'hdlNetAttributes' => [
7138 
              ],
7139 
            },
7140 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7141 
            'width' => 32,
7142 
          },
7143 
          'reg12_td_net_x0' => {
7144 
            'attributes' => {
7145 
              'hdlNetAttributes' => [
7146 
              ],
7147 
            },
7148 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7149 
            'width' => 32,
7150 
          },
7151 
          'reg12_tv_net' => {
7152 
            'attributes' => {
7153 
              'hdlNetAttributes' => [
7154 
              ],
7155 
            },
7156 
            'hdlType' => 'std_logic',
7157 
            'width' => 1,
7158 
          },
7159 
          'reg12_tv_net_x0' => {
7160 
            'attributes' => {
7161 
              'hdlNetAttributes' => [
7162 
              ],
7163 
            },
7164 
            'hdlType' => 'std_logic',
7165 
            'width' => 1,
7166 
          },
7167 
          'reg13_td_net' => {
7168 
            'attributes' => {
7169 
              'hdlNetAttributes' => [
7170 
              ],
7171 
            },
7172 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7173 
            'width' => 32,
7174 
          },
7175 
          'reg13_td_net_x0' => {
7176 
            'attributes' => {
7177 
              'hdlNetAttributes' => [
7178 
              ],
7179 
            },
7180 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7181 
            'width' => 32,
7182 
          },
7183 
          'reg13_tv_net' => {
7184 
            'attributes' => {
7185 
              'hdlNetAttributes' => [
7186 
              ],
7187 
            },
7188 
            'hdlType' => 'std_logic',
7189 
            'width' => 1,
7190 
          },
7191 
          'reg13_tv_net_x0' => {
7192 
            'attributes' => {
7193 
              'hdlNetAttributes' => [
7194 
              ],
7195 
            },
7196 
            'hdlType' => 'std_logic',
7197 
            'width' => 1,
7198 
          },
7199 
          'reg14_td_net' => {
7200 
            'attributes' => {
7201 
              'hdlNetAttributes' => [
7202 
              ],
7203 
            },
7204 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7205 
            'width' => 32,
7206 
          },
7207 
          'reg14_td_net_x0' => {
7208 
            'attributes' => {
7209 
              'hdlNetAttributes' => [
7210 
              ],
7211 
            },
7212 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7213 
            'width' => 32,
7214 
          },
7215 
          'reg14_tv_net' => {
7216 
            'attributes' => {
7217 
              'hdlNetAttributes' => [
7218 
              ],
7219 
            },
7220 
            'hdlType' => 'std_logic',
7221 
            'width' => 1,
7222 
          },
7223 
          'reg14_tv_net_x0' => {
7224 
            'attributes' => {
7225 
              'hdlNetAttributes' => [
7226 
              ],
7227 
            },
7228 
            'hdlType' => 'std_logic',
7229 
            'width' => 1,
7230 
          },
7231 
          'to_register10_dout_net' => {
7232 
            'attributes' => {
7233 
              'hdlNetAttributes' => [
7234 
              ],
7235 
            },
7236 
            'hdlType' => 'std_logic',
7237 
            'width' => 1,
7238 
          },
7239 
          'to_register11_dout_net' => {
7240 
            'attributes' => {
7241 
              'hdlNetAttributes' => [
7242 
              ],
7243 
            },
7244 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7245 
            'width' => 32,
7246 
          },
7247 
          'to_register12_dout_net' => {
7248 
            'attributes' => {
7249 
              'hdlNetAttributes' => [
7250 
              ],
7251 
            },
7252 
            'hdlType' => 'std_logic',
7253 
            'width' => 1,
7254 
          },
7255 
          'to_register13_dout_net' => {
7256 
            'attributes' => {
7257 
              'hdlNetAttributes' => [
7258 
              ],
7259 
            },
7260 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7261 
            'width' => 32,
7262 
          },
7263 
          'to_register14_dout_net' => {
7264 
            'attributes' => {
7265 
              'hdlNetAttributes' => [
7266 
              ],
7267 
            },
7268 
            'hdlType' => 'std_logic',
7269 
            'width' => 1,
7270 
          },
7271 
          'to_register15_dout_net' => {
7272 
            'attributes' => {
7273 
              'hdlNetAttributes' => [
7274 
              ],
7275 
            },
7276 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7277 
            'width' => 32,
7278 
          },
7279 
          'to_register16_dout_net' => {
7280 
            'attributes' => {
7281 
              'hdlNetAttributes' => [
7282 
              ],
7283 
            },
7284 
            'hdlType' => 'std_logic',
7285 
            'width' => 1,
7286 
          },
7287 
          'to_register17_dout_net' => {
7288 
            'attributes' => {
7289 
              'hdlNetAttributes' => [
7290 
              ],
7291 
            },
7292 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7293 
            'width' => 32,
7294 
          },
7295 
          'to_register18_dout_net' => {
7296 
            'attributes' => {
7297 
              'hdlNetAttributes' => [
7298 
              ],
7299 
            },
7300 
            'hdlType' => 'std_logic',
7301 
            'width' => 1,
7302 
          },
7303 
          'to_register19_dout_net' => {
7304 
            'attributes' => {
7305 
              'hdlNetAttributes' => [
7306 
              ],
7307 
            },
7308 
            'hdlType' => 'std_logic',
7309 
            'width' => 1,
7310 
          },
7311 
          'to_register1_dout_net' => {
7312 
            'attributes' => {
7313 
              'hdlNetAttributes' => [
7314 
              ],
7315 
            },
7316 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7317 
            'width' => 32,
7318 
          },
7319 
          'to_register20_dout_net' => {
7320 
            'attributes' => {
7321 
              'hdlNetAttributes' => [
7322 
              ],
7323 
            },
7324 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7325 
            'width' => 32,
7326 
          },
7327 
          'to_register21_dout_net' => {
7328 
            'attributes' => {
7329 
              'hdlNetAttributes' => [
7330 
              ],
7331 
            },
7332 
            'hdlType' => 'std_logic',
7333 
            'width' => 1,
7334 
          },
7335 
          'to_register22_dout_net' => {
7336 
            'attributes' => {
7337 
              'hdlNetAttributes' => [
7338 
              ],
7339 
            },
7340 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7341 
            'width' => 32,
7342 
          },
7343 
          'to_register23_dout_net' => {
7344 
            'attributes' => {
7345 
              'hdlNetAttributes' => [
7346 
              ],
7347 
            },
7348 
            'hdlType' => 'std_logic',
7349 
            'width' => 1,
7350 
          },
7351 
          'to_register24_dout_net' => {
7352 
            'attributes' => {
7353 
              'hdlNetAttributes' => [
7354 
              ],
7355 
            },
7356 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7357 
            'width' => 32,
7358 
          },
7359 
          'to_register25_dout_net' => {
7360 
            'attributes' => {
7361 
              'hdlNetAttributes' => [
7362 
              ],
7363 
            },
7364 
            'hdlType' => 'std_logic',
7365 
            'width' => 1,
7366 
          },
7367 
          'to_register26_dout_net' => {
7368 
            'attributes' => {
7369 
              'hdlNetAttributes' => [
7370 
              ],
7371 
            },
7372 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7373 
            'width' => 32,
7374 
          },
7375 
          'to_register27_dout_net' => {
7376 
            'attributes' => {
7377 
              'hdlNetAttributes' => [
7378 
              ],
7379 
            },
7380 
            'hdlType' => 'std_logic',
7381 
            'width' => 1,
7382 
          },
7383 
          'to_register28_dout_net' => {
7384 
            'attributes' => {
7385 
              'hdlNetAttributes' => [
7386 
              ],
7387 
            },
7388 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7389 
            'width' => 32,
7390 
          },
7391 
          'to_register29_dout_net' => {
7392 
            'attributes' => {
7393 
              'hdlNetAttributes' => [
7394 
              ],
7395 
            },
7396 
            'hdlType' => 'std_logic',
7397 
            'width' => 1,
7398 
          },
7399 
          'to_register2_dout_net' => {
7400 
            'attributes' => {
7401 
              'hdlNetAttributes' => [
7402 
              ],
7403 
            },
7404 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7405 
            'width' => 32,
7406 
          },
7407 
          'to_register30_dout_net' => {
7408 
            'attributes' => {
7409 
              'hdlNetAttributes' => [
7410 
              ],
7411 
            },
7412 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7413 
            'width' => 32,
7414 
          },
7415 
          'to_register31_dout_net' => {
7416 
            'attributes' => {
7417 
              'hdlNetAttributes' => [
7418 
              ],
7419 
            },
7420 
            'hdlType' => 'std_logic',
7421 
            'width' => 1,
7422 
          },
7423 
          'to_register32_dout_net' => {
7424 
            'attributes' => {
7425 
              'hdlNetAttributes' => [
7426 
              ],
7427 
            },
7428 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7429 
            'width' => 32,
7430 
          },
7431 
          'to_register33_dout_net' => {
7432 
            'attributes' => {
7433 
              'hdlNetAttributes' => [
7434 
              ],
7435 
            },
7436 
            'hdlType' => 'std_logic',
7437 
            'width' => 1,
7438 
          },
7439 
          'to_register34_dout_net' => {
7440 
            'attributes' => {
7441 
              'hdlNetAttributes' => [
7442 
              ],
7443 
            },
7444 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7445 
            'width' => 32,
7446 
          },
7447 
          'to_register3_dout_net' => {
7448 
            'attributes' => {
7449 
              'hdlNetAttributes' => [
7450 
              ],
7451 
            },
7452 
            'hdlType' => 'std_logic',
7453 
            'width' => 1,
7454 
          },
7455 
          'to_register4_dout_net' => {
7456 
            'attributes' => {
7457 
              'hdlNetAttributes' => [
7458 
              ],
7459 
            },
7460 
            'hdlType' => 'std_logic',
7461 
            'width' => 1,
7462 
          },
7463 
          'to_register5_dout_net' => {
7464 
            'attributes' => {
7465 
              'hdlNetAttributes' => [
7466 
              ],
7467 
            },
7468 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7469 
            'width' => 32,
7470 
          },
7471 
          'to_register6_dout_net' => {
7472 
            'attributes' => {
7473 
              'hdlNetAttributes' => [
7474 
              ],
7475 
            },
7476 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7477 
            'width' => 32,
7478 
          },
7479 
          'to_register7_dout_net' => {
7480 
            'attributes' => {
7481 
              'hdlNetAttributes' => [
7482 
              ],
7483 
            },
7484 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7485 
            'width' => 32,
7486 
          },
7487 
          'to_register8_dout_net' => {
7488 
            'attributes' => {
7489 
              'hdlNetAttributes' => [
7490 
              ],
7491 
            },
7492 
            'hdlType' => 'std_logic',
7493 
            'width' => 1,
7494 
          },
7495 
          'to_register9_dout_net' => {
7496 
            'attributes' => {
7497 
              'hdlNetAttributes' => [
7498 
              ],
7499 
            },
7500 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7501 
            'width' => 32,
7502 
          },
7503 
        },
7504 
        'ports' => {
7505 
          'ce' => {
7506 
            'attributes' => {
7507 
              'defaultHdlValue' => '\'1\'',
7508 
              'domain' => 'default',
7509 
              'group' => 4,
7510 
              'isCe' => 1,
7511 
              'period' => 1,
7512 
            },
7513 
            'direction' => 'in',
7514 
            'hdlType' => 'std_logic',
7515 
            'width' => 1,
7516 
          },
7517 
          'clk' => {
7518 
            'attributes' => {
7519 
              'domain' => 'default',
7520 
              'group' => 4,
7521 
              'isClk' => 1,
7522 
              'period' => 1,
7523 
              'type' => 'logic',
7524 
            },
7525 
            'direction' => 'in',
7526 
            'hdlType' => 'std_logic',
7527 
            'width' => 1,
7528 
          },
7529 
          'debug_in_1i' => {
7530 
            'attributes' => {
7531 
              'bin_pt' => 0,
7532 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
7533 
              'is_floating_block' => 1,
7534 
              'is_gateway_port' => 1,
7535 
              'must_be_hdl_vector' => 1,
7536 
              'period' => 1,
7537 
              'port_id' => 0,
7538 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
7539 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
7540 
              'timingConstraint' => 'none',
7541 
              'type' => 'UFix_32_0',
7542 
            },
7543 
            'direction' => 'in',
7544 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7545 
            'width' => 32,
7546 
          },
7547 
          'debug_in_2i' => {
7548 
            'attributes' => {
7549 
              'bin_pt' => 0,
7550 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
7551 
              'is_floating_block' => 1,
7552 
              'is_gateway_port' => 1,
7553 
              'must_be_hdl_vector' => 1,
7554 
              'period' => 1,
7555 
              'port_id' => 0,
7556 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
7557 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
7558 
              'timingConstraint' => 'none',
7559 
              'type' => 'UFix_32_0',
7560 
            },
7561 
            'direction' => 'in',
7562 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7563 
            'width' => 32,
7564 
          },
7565 
          'debug_in_3i' => {
7566 
            'attributes' => {
7567 
              'bin_pt' => 0,
7568 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
7569 
              'is_floating_block' => 1,
7570 
              'is_gateway_port' => 1,
7571 
              'must_be_hdl_vector' => 1,
7572 
              'period' => 1,
7573 
              'port_id' => 0,
7574 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
7575 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
7576 
              'timingConstraint' => 'none',
7577 
              'type' => 'UFix_32_0',
7578 
            },
7579 
            'direction' => 'in',
7580 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7581 
            'width' => 32,
7582 
          },
7583 
          'debug_in_4i' => {
7584 
            'attributes' => {
7585 
              'bin_pt' => 0,
7586 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
7587 
              'is_floating_block' => 1,
7588 
              'is_gateway_port' => 1,
7589 
              'must_be_hdl_vector' => 1,
7590 
              'period' => 1,
7591 
              'port_id' => 0,
7592 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
7593 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
7594 
              'timingConstraint' => 'none',
7595 
              'type' => 'UFix_32_0',
7596 
            },
7597 
            'direction' => 'in',
7598 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7599 
            'width' => 32,
7600 
          },
7601 
          'dma_host2board_busy' => {
7602 
            'attributes' => {
7603 
              'bin_pt' => 0,
7604 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
7605 
              'is_floating_block' => 1,
7606 
              'is_gateway_port' => 1,
7607 
              'must_be_hdl_vector' => 1,
7608 
              'period' => 1,
7609 
              'port_id' => 0,
7610 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
7611 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
7612 
              'timingConstraint' => 'none',
7613 
              'type' => 'UFix_1_0',
7614 
            },
7615 
            'direction' => 'in',
7616 
            'hdlType' => 'std_logic',
7617 
            'width' => 1,
7618 
          },
7619 
          'dma_host2board_done' => {
7620 
            'attributes' => {
7621 
              'bin_pt' => 0,
7622 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
7623 
              'is_floating_block' => 1,
7624 
              'is_gateway_port' => 1,
7625 
              'must_be_hdl_vector' => 1,
7626 
              'period' => 1,
7627 
              'port_id' => 0,
7628 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
7629 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
7630 
              'timingConstraint' => 'none',
7631 
              'type' => 'UFix_1_0',
7632 
            },
7633 
            'direction' => 'in',
7634 
            'hdlType' => 'std_logic',
7635 
            'width' => 1,
7636 
          },
7637 
          'from_register10_data_out' => {
7638 
            'attributes' => {
7639 
              'bin_pt' => 0,
7640 
              'is_floating_block' => 1,
7641 
              'must_be_hdl_vector' => 1,
7642 
              'period' => 1,
7643 
              'port_id' => 0,
7644 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
7645 
              'type' => 'UFix_32_0',
7646 
            },
7647 
            'direction' => 'in',
7648 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7649 
            'width' => 32,
7650 
          },
7651 
          'from_register11_data_out' => {
7652 
            'attributes' => {
7653 
              'bin_pt' => 0,
7654 
              'is_floating_block' => 1,
7655 
              'must_be_hdl_vector' => 1,
7656 
              'period' => 1,
7657 
              'port_id' => 0,
7658 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
7659 
              'type' => 'UFix_32_0',
7660 
            },
7661 
            'direction' => 'in',
7662 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7663 
            'width' => 32,
7664 
          },
7665 
          'from_register12_data_out' => {
7666 
            'attributes' => {
7667 
              'bin_pt' => 0,
7668 
              'is_floating_block' => 1,
7669 
              'must_be_hdl_vector' => 1,
7670 
              'period' => 1,
7671 
              'port_id' => 0,
7672 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
7673 
              'type' => 'UFix_1_0',
7674 
            },
7675 
            'direction' => 'in',
7676 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7677 
            'width' => 1,
7678 
          },
7679 
          'from_register13_data_out' => {
7680 
            'attributes' => {
7681 
              'bin_pt' => 0,
7682 
              'is_floating_block' => 1,
7683 
              'must_be_hdl_vector' => 1,
7684 
              'period' => 1,
7685 
              'port_id' => 0,
7686 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
7687 
              'type' => 'UFix_32_0',
7688 
            },
7689 
            'direction' => 'in',
7690 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7691 
            'width' => 32,
7692 
          },
7693 
          'from_register14_data_out' => {
7694 
            'attributes' => {
7695 
              'bin_pt' => 0,
7696 
              'is_floating_block' => 1,
7697 
              'must_be_hdl_vector' => 1,
7698 
              'period' => 1,
7699 
              'port_id' => 0,
7700 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
7701 
              'type' => 'UFix_1_0',
7702 
            },
7703 
            'direction' => 'in',
7704 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7705 
            'width' => 1,
7706 
          },
7707 
          'from_register15_data_out' => {
7708 
            'attributes' => {
7709 
              'bin_pt' => 0,
7710 
              'is_floating_block' => 1,
7711 
              'must_be_hdl_vector' => 1,
7712 
              'period' => 1,
7713 
              'port_id' => 0,
7714 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
7715 
              'type' => 'UFix_32_0',
7716 
            },
7717 
            'direction' => 'in',
7718 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7719 
            'width' => 32,
7720 
          },
7721 
          'from_register16_data_out' => {
7722 
            'attributes' => {
7723 
              'bin_pt' => 0,
7724 
              'is_floating_block' => 1,
7725 
              'must_be_hdl_vector' => 1,
7726 
              'period' => 1,
7727 
              'port_id' => 0,
7728 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
7729 
              'type' => 'UFix_1_0',
7730 
            },
7731 
            'direction' => 'in',
7732 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7733 
            'width' => 1,
7734 
          },
7735 
          'from_register17_data_out' => {
7736 
            'attributes' => {
7737 
              'bin_pt' => 0,
7738 
              'is_floating_block' => 1,
7739 
              'must_be_hdl_vector' => 1,
7740 
              'period' => 1,
7741 
              'port_id' => 0,
7742 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
7743 
              'type' => 'UFix_32_0',
7744 
            },
7745 
            'direction' => 'in',
7746 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7747 
            'width' => 32,
7748 
          },
7749 
          'from_register18_data_out' => {
7750 
            'attributes' => {
7751 
              'bin_pt' => 0,
7752 
              'is_floating_block' => 1,
7753 
              'must_be_hdl_vector' => 1,
7754 
              'period' => 1,
7755 
              'port_id' => 0,
7756 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
7757 
              'type' => 'UFix_1_0',
7758 
            },
7759 
            'direction' => 'in',
7760 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7761 
            'width' => 1,
7762 
          },
7763 
          'from_register19_data_out' => {
7764 
            'attributes' => {
7765 
              'bin_pt' => 0,
7766 
              'is_floating_block' => 1,
7767 
              'must_be_hdl_vector' => 1,
7768 
              'period' => 1,
7769 
              'port_id' => 0,
7770 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
7771 
              'type' => 'UFix_32_0',
7772 
            },
7773 
            'direction' => 'in',
7774 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7775 
            'width' => 32,
7776 
          },
7777 
          'from_register1_data_out' => {
7778 
            'attributes' => {
7779 
              'bin_pt' => 0,
7780 
              'is_floating_block' => 1,
7781 
              'must_be_hdl_vector' => 1,
7782 
              'period' => 1,
7783 
              'port_id' => 0,
7784 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
7785 
              'type' => 'UFix_1_0',
7786 
            },
7787 
            'direction' => 'in',
7788 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7789 
            'width' => 1,
7790 
          },
7791 
          'from_register20_data_out' => {
7792 
            'attributes' => {
7793 
              'bin_pt' => 0,
7794 
              'is_floating_block' => 1,
7795 
              'must_be_hdl_vector' => 1,
7796 
              'period' => 1,
7797 
              'port_id' => 0,
7798 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
7799 
              'type' => 'UFix_1_0',
7800 
            },
7801 
            'direction' => 'in',
7802 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7803 
            'width' => 1,
7804 
          },
7805 
          'from_register21_data_out' => {
7806 
            'attributes' => {
7807 
              'bin_pt' => 0,
7808 
              'is_floating_block' => 1,
7809 
              'must_be_hdl_vector' => 1,
7810 
              'period' => 1,
7811 
              'port_id' => 0,
7812 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
7813 
              'type' => 'UFix_32_0',
7814 
            },
7815 
            'direction' => 'in',
7816 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7817 
            'width' => 32,
7818 
          },
7819 
          'from_register22_data_out' => {
7820 
            'attributes' => {
7821 
              'bin_pt' => 0,
7822 
              'is_floating_block' => 1,
7823 
              'must_be_hdl_vector' => 1,
7824 
              'period' => 1,
7825 
              'port_id' => 0,
7826 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
7827 
              'type' => 'UFix_1_0',
7828 
            },
7829 
            'direction' => 'in',
7830 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7831 
            'width' => 1,
7832 
          },
7833 
          'from_register23_data_out' => {
7834 
            'attributes' => {
7835 
              'bin_pt' => 0,
7836 
              'is_floating_block' => 1,
7837 
              'must_be_hdl_vector' => 1,
7838 
              'period' => 1,
7839 
              'port_id' => 0,
7840 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
7841 
              'type' => 'UFix_32_0',
7842 
            },
7843 
            'direction' => 'in',
7844 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7845 
            'width' => 32,
7846 
          },
7847 
          'from_register24_data_out' => {
7848 
            'attributes' => {
7849 
              'bin_pt' => 0,
7850 
              'is_floating_block' => 1,
7851 
              'must_be_hdl_vector' => 1,
7852 
              'period' => 1,
7853 
              'port_id' => 0,
7854 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
7855 
              'type' => 'UFix_1_0',
7856 
            },
7857 
            'direction' => 'in',
7858 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7859 
            'width' => 1,
7860 
          },
7861 
          'from_register25_data_out' => {
7862 
            'attributes' => {
7863 
              'bin_pt' => 0,
7864 
              'is_floating_block' => 1,
7865 
              'must_be_hdl_vector' => 1,
7866 
              'period' => 1,
7867 
              'port_id' => 0,
7868 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
7869 
              'type' => 'UFix_32_0',
7870 
            },
7871 
            'direction' => 'in',
7872 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7873 
            'width' => 32,
7874 
          },
7875 
          'from_register26_data_out' => {
7876 
            'attributes' => {
7877 
              'bin_pt' => 0,
7878 
              'is_floating_block' => 1,
7879 
              'must_be_hdl_vector' => 1,
7880 
              'period' => 1,
7881 
              'port_id' => 0,
7882 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
7883 
              'type' => 'UFix_1_0',
7884 
            },
7885 
            'direction' => 'in',
7886 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7887 
            'width' => 1,
7888 
          },
7889 
          'from_register27_data_out' => {
7890 
            'attributes' => {
7891 
              'bin_pt' => 0,
7892 
              'is_floating_block' => 1,
7893 
              'must_be_hdl_vector' => 1,
7894 
              'period' => 1,
7895 
              'port_id' => 0,
7896 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
7897 
              'type' => 'UFix_32_0',
7898 
            },
7899 
            'direction' => 'in',
7900 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7901 
            'width' => 32,
7902 
          },
7903 
          'from_register28_data_out' => {
7904 
            'attributes' => {
7905 
              'bin_pt' => 0,
7906 
              'is_floating_block' => 1,
7907 
              'must_be_hdl_vector' => 1,
7908 
              'period' => 1,
7909 
              'port_id' => 0,
7910 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
7911 
              'type' => 'UFix_1_0',
7912 
            },
7913 
            'direction' => 'in',
7914 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7915 
            'width' => 1,
7916 
          },
7917 
          'from_register2_data_out' => {
7918 
            'attributes' => {
7919 
              'bin_pt' => 0,
7920 
              'is_floating_block' => 1,
7921 
              'must_be_hdl_vector' => 1,
7922 
              'period' => 1,
7923 
              'port_id' => 0,
7924 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
7925 
              'type' => 'UFix_1_0',
7926 
            },
7927 
            'direction' => 'in',
7928 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7929 
            'width' => 1,
7930 
          },
7931 
          'from_register3_data_out' => {
7932 
            'attributes' => {
7933 
              'bin_pt' => 0,
7934 
              'is_floating_block' => 1,
7935 
              'must_be_hdl_vector' => 1,
7936 
              'period' => 1,
7937 
              'port_id' => 0,
7938 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
7939 
              'type' => 'UFix_32_0',
7940 
            },
7941 
            'direction' => 'in',
7942 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7943 
            'width' => 32,
7944 
          },
7945 
          'from_register4_data_out' => {
7946 
            'attributes' => {
7947 
              'bin_pt' => 0,
7948 
              'is_floating_block' => 1,
7949 
              'must_be_hdl_vector' => 1,
7950 
              'period' => 1,
7951 
              'port_id' => 0,
7952 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
7953 
              'type' => 'UFix_1_0',
7954 
            },
7955 
            'direction' => 'in',
7956 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7957 
            'width' => 1,
7958 
          },
7959 
          'from_register5_data_out' => {
7960 
            'attributes' => {
7961 
              'bin_pt' => 0,
7962 
              'is_floating_block' => 1,
7963 
              'must_be_hdl_vector' => 1,
7964 
              'period' => 1,
7965 
              'port_id' => 0,
7966 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
7967 
              'type' => 'UFix_32_0',
7968 
            },
7969 
            'direction' => 'in',
7970 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7971 
            'width' => 32,
7972 
          },
7973 
          'from_register6_data_out' => {
7974 
            'attributes' => {
7975 
              'bin_pt' => 0,
7976 
              'is_floating_block' => 1,
7977 
              'must_be_hdl_vector' => 1,
7978 
              'period' => 1,
7979 
              'port_id' => 0,
7980 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
7981 
              'type' => 'UFix_1_0',
7982 
            },
7983 
            'direction' => 'in',
7984 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7985 
            'width' => 1,
7986 
          },
7987 
          'from_register7_data_out' => {
7988 
            'attributes' => {
7989 
              'bin_pt' => 0,
7990 
              'is_floating_block' => 1,
7991 
              'must_be_hdl_vector' => 1,
7992 
              'period' => 1,
7993 
              'port_id' => 0,
7994 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
7995 
              'type' => 'UFix_32_0',
7996 
            },
7997 
            'direction' => 'in',
7998 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7999 
            'width' => 32,
8000 
          },
8001 
          'from_register8_data_out' => {
8002 
            'attributes' => {
8003 
              'bin_pt' => 0,
8004 
              'is_floating_block' => 1,
8005 
              'must_be_hdl_vector' => 1,
8006 
              'period' => 1,
8007 
              'port_id' => 0,
8008 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
8009 
              'type' => 'UFix_32_0',
8010 
            },
8011 
            'direction' => 'in',
8012 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8013 
            'width' => 32,
8014 
          },
8015 
          'from_register9_data_out' => {
8016 
            'attributes' => {
8017 
              'bin_pt' => 0,
8018 
              'is_floating_block' => 1,
8019 
              'must_be_hdl_vector' => 1,
8020 
              'period' => 1,
8021 
              'port_id' => 0,
8022 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
8023 
              'type' => 'UFix_1_0',
8024 
            },
8025 
            'direction' => 'in',
8026 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8027 
            'width' => 1,
8028 
          },
8029 
          'reg01_rd' => {
8030 
            'attributes' => {
8031 
              'bin_pt' => 0,
8032 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
8033 
              'is_floating_block' => 1,
8034 
              'is_gateway_port' => 1,
8035 
              'must_be_hdl_vector' => 1,
8036 
              'period' => 1,
8037 
              'port_id' => 0,
8038 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
8039 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
8040 
              'timingConstraint' => 'none',
8041 
              'type' => 'UFix_32_0',
8042 
            },
8043 
            'direction' => 'out',
8044 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8045 
            'width' => 32,
8046 
          },
8047 
          'reg01_rv' => {
8048 
            'attributes' => {
8049 
              'bin_pt' => 0,
8050 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
8051 
              'is_floating_block' => 1,
8052 
              'is_gateway_port' => 1,
8053 
              'must_be_hdl_vector' => 1,
8054 
              'period' => 1,
8055 
              'port_id' => 0,
8056 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
8057 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
8058 
              'timingConstraint' => 'none',
8059 
              'type' => 'UFix_1_0',
8060 
            },
8061 
            'direction' => 'out',
8062 
            'hdlType' => 'std_logic',
8063 
            'width' => 1,
8064 
          },
8065 
          'reg01_td' => {
8066 
            'attributes' => {
8067 
              'bin_pt' => 0,
8068 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
8069 
              'is_floating_block' => 1,
8070 
              'is_gateway_port' => 1,
8071 
              'must_be_hdl_vector' => 1,
8072 
              'period' => 1,
8073 
              'port_id' => 0,
8074 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
8075 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
8076 
              'timingConstraint' => 'none',
8077 
              'type' => 'UFix_32_0',
8078 
            },
8079 
            'direction' => 'in',
8080 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8081 
            'width' => 32,
8082 
          },
8083 
          'reg01_tv' => {
8084 
            'attributes' => {
8085 
              'bin_pt' => 0,
8086 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
8087 
              'is_floating_block' => 1,
8088 
              'is_gateway_port' => 1,
8089 
              'must_be_hdl_vector' => 1,
8090 
              'period' => 1,
8091 
              'port_id' => 0,
8092 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
8093 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
8094 
              'timingConstraint' => 'none',
8095 
              'type' => 'Bool',
8096 
            },
8097 
            'direction' => 'in',
8098 
            'hdlType' => 'std_logic',
8099 
            'width' => 1,
8100 
          },
8101 
          'reg02_rd' => {
8102 
            'attributes' => {
8103 
              'bin_pt' => 0,
8104 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
8105 
              'is_floating_block' => 1,
8106 
              'is_gateway_port' => 1,
8107 
              'must_be_hdl_vector' => 1,
8108 
              'period' => 1,
8109 
              'port_id' => 0,
8110 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
8111 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
8112 
              'timingConstraint' => 'none',
8113 
              'type' => 'UFix_32_0',
8114 
            },
8115 
            'direction' => 'out',
8116 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8117 
            'width' => 32,
8118 
          },
8119 
          'reg02_rv' => {
8120 
            'attributes' => {
8121 
              'bin_pt' => 0,
8122 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
8123 
              'is_floating_block' => 1,
8124 
              'is_gateway_port' => 1,
8125 
              'must_be_hdl_vector' => 1,
8126 
              'period' => 1,
8127 
              'port_id' => 0,
8128 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
8129 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
8130 
              'timingConstraint' => 'none',
8131 
              'type' => 'UFix_1_0',
8132 
            },
8133 
            'direction' => 'out',
8134 
            'hdlType' => 'std_logic',
8135 
            'width' => 1,
8136 
          },
8137 
          'reg02_td' => {
8138 
            'attributes' => {
8139 
              'bin_pt' => 0,
8140 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
8141 
              'is_floating_block' => 1,
8142 
              'is_gateway_port' => 1,
8143 
              'must_be_hdl_vector' => 1,
8144 
              'period' => 1,
8145 
              'port_id' => 0,
8146 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
8147 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
8148 
              'timingConstraint' => 'none',
8149 
              'type' => 'UFix_32_0',
8150 
            },
8151 
            'direction' => 'in',
8152 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8153 
            'width' => 32,
8154 
          },
8155 
          'reg02_tv' => {
8156 
            'attributes' => {
8157 
              'bin_pt' => 0,
8158 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
8159 
              'is_floating_block' => 1,
8160 
              'is_gateway_port' => 1,
8161 
              'must_be_hdl_vector' => 1,
8162 
              'period' => 1,
8163 
              'port_id' => 0,
8164 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
8165 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
8166 
              'timingConstraint' => 'none',
8167 
              'type' => 'Bool',
8168 
            },
8169 
            'direction' => 'in',
8170 
            'hdlType' => 'std_logic',
8171 
            'width' => 1,
8172 
          },
8173 
          'reg03_rd' => {
8174 
            'attributes' => {
8175 
              'bin_pt' => 0,
8176 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
8177 
              'is_floating_block' => 1,
8178 
              'is_gateway_port' => 1,
8179 
              'must_be_hdl_vector' => 1,
8180 
              'period' => 1,
8181 
              'port_id' => 0,
8182 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
8183 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
8184 
              'timingConstraint' => 'none',
8185 
              'type' => 'UFix_32_0',
8186 
            },
8187 
            'direction' => 'out',
8188 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8189 
            'width' => 32,
8190 
          },
8191 
          'reg03_rv' => {
8192 
            'attributes' => {
8193 
              'bin_pt' => 0,
8194 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
8195 
              'is_floating_block' => 1,
8196 
              'is_gateway_port' => 1,
8197 
              'must_be_hdl_vector' => 1,
8198 
              'period' => 1,
8199 
              'port_id' => 0,
8200 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
8201 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
8202 
              'timingConstraint' => 'none',
8203 
              'type' => 'UFix_1_0',
8204 
            },
8205 
            'direction' => 'out',
8206 
            'hdlType' => 'std_logic',
8207 
            'width' => 1,
8208 
          },
8209 
          'reg03_td' => {
8210 
            'attributes' => {
8211 
              'bin_pt' => 0,
8212 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
8213 
              'is_floating_block' => 1,
8214 
              'is_gateway_port' => 1,
8215 
              'must_be_hdl_vector' => 1,
8216 
              'period' => 1,
8217 
              'port_id' => 0,
8218 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
8219 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
8220 
              'timingConstraint' => 'none',
8221 
              'type' => 'UFix_32_0',
8222 
            },
8223 
            'direction' => 'in',
8224 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8225 
            'width' => 32,
8226 
          },
8227 
          'reg03_tv' => {
8228 
            'attributes' => {
8229 
              'bin_pt' => 0,
8230 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
8231 
              'is_floating_block' => 1,
8232 
              'is_gateway_port' => 1,
8233 
              'must_be_hdl_vector' => 1,
8234 
              'period' => 1,
8235 
              'port_id' => 0,
8236 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
8237 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
8238 
              'timingConstraint' => 'none',
8239 
              'type' => 'Bool',
8240 
            },
8241 
            'direction' => 'in',
8242 
            'hdlType' => 'std_logic',
8243 
            'width' => 1,
8244 
          },
8245 
          'reg04_rd' => {
8246 
            'attributes' => {
8247 
              'bin_pt' => 0,
8248 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
8249 
              'is_floating_block' => 1,
8250 
              'is_gateway_port' => 1,
8251 
              'must_be_hdl_vector' => 1,
8252 
              'period' => 1,
8253 
              'port_id' => 0,
8254 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
8255 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
8256 
              'timingConstraint' => 'none',
8257 
              'type' => 'UFix_32_0',
8258 
            },
8259 
            'direction' => 'out',
8260 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8261 
            'width' => 32,
8262 
          },
8263 
          'reg04_rv' => {
8264 
            'attributes' => {
8265 
              'bin_pt' => 0,
8266 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
8267 
              'is_floating_block' => 1,
8268 
              'is_gateway_port' => 1,
8269 
              'must_be_hdl_vector' => 1,
8270 
              'period' => 1,
8271 
              'port_id' => 0,
8272 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
8273 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
8274 
              'timingConstraint' => 'none',
8275 
              'type' => 'UFix_1_0',
8276 
            },
8277 
            'direction' => 'out',
8278 
            'hdlType' => 'std_logic',
8279 
            'width' => 1,
8280 
          },
8281 
          'reg04_td' => {
8282 
            'attributes' => {
8283 
              'bin_pt' => 0,
8284 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
8285 
              'is_floating_block' => 1,
8286 
              'is_gateway_port' => 1,
8287 
              'must_be_hdl_vector' => 1,
8288 
              'period' => 1,
8289 
              'port_id' => 0,
8290 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
8291 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
8292 
              'timingConstraint' => 'none',
8293 
              'type' => 'UFix_32_0',
8294 
            },
8295 
            'direction' => 'in',
8296 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8297 
            'width' => 32,
8298 
          },
8299 
          'reg04_tv' => {
8300 
            'attributes' => {
8301 
              'bin_pt' => 0,
8302 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
8303 
              'is_floating_block' => 1,
8304 
              'is_gateway_port' => 1,
8305 
              'must_be_hdl_vector' => 1,
8306 
              'period' => 1,
8307 
              'port_id' => 0,
8308 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
8309 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
8310 
              'timingConstraint' => 'none',
8311 
              'type' => 'Bool',
8312 
            },
8313 
            'direction' => 'in',
8314 
            'hdlType' => 'std_logic',
8315 
            'width' => 1,
8316 
          },
8317 
          'reg05_rd' => {
8318 
            'attributes' => {
8319 
              'bin_pt' => 0,
8320 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
8321 
              'is_floating_block' => 1,
8322 
              'is_gateway_port' => 1,
8323 
              'must_be_hdl_vector' => 1,
8324 
              'period' => 1,
8325 
              'port_id' => 0,
8326 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
8327 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
8328 
              'timingConstraint' => 'none',
8329 
              'type' => 'UFix_32_0',
8330 
            },
8331 
            'direction' => 'out',
8332 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8333 
            'width' => 32,
8334 
          },
8335 
          'reg05_rv' => {
8336 
            'attributes' => {
8337 
              'bin_pt' => 0,
8338 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
8339 
              'is_floating_block' => 1,
8340 
              'is_gateway_port' => 1,
8341 
              'must_be_hdl_vector' => 1,
8342 
              'period' => 1,
8343 
              'port_id' => 0,
8344 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
8345 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
8346 
              'timingConstraint' => 'none',
8347 
              'type' => 'UFix_1_0',
8348 
            },
8349 
            'direction' => 'out',
8350 
            'hdlType' => 'std_logic',
8351 
            'width' => 1,
8352 
          },
8353 
          'reg05_td' => {
8354 
            'attributes' => {
8355 
              'bin_pt' => 0,
8356 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
8357 
              'is_floating_block' => 1,
8358 
              'is_gateway_port' => 1,
8359 
              'must_be_hdl_vector' => 1,
8360 
              'period' => 1,
8361 
              'port_id' => 0,
8362 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
8363 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
8364 
              'timingConstraint' => 'none',
8365 
              'type' => 'UFix_32_0',
8366 
            },
8367 
            'direction' => 'in',
8368 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8369 
            'width' => 32,
8370 
          },
8371 
          'reg05_tv' => {
8372 
            'attributes' => {
8373 
              'bin_pt' => 0,
8374 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
8375 
              'is_floating_block' => 1,
8376 
              'is_gateway_port' => 1,
8377 
              'must_be_hdl_vector' => 1,
8378 
              'period' => 1,
8379 
              'port_id' => 0,
8380 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
8381 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
8382 
              'timingConstraint' => 'none',
8383 
              'type' => 'Bool',
8384 
            },
8385 
            'direction' => 'in',
8386 
            'hdlType' => 'std_logic',
8387 
            'width' => 1,
8388 
          },
8389 
          'reg06_rd' => {
8390 
            'attributes' => {
8391 
              'bin_pt' => 0,
8392 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
8393 
              'is_floating_block' => 1,
8394 
              'is_gateway_port' => 1,
8395 
              'must_be_hdl_vector' => 1,
8396 
              'period' => 1,
8397 
              'port_id' => 0,
8398 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
8399 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
8400 
              'timingConstraint' => 'none',
8401 
              'type' => 'UFix_32_0',
8402 
            },
8403 
            'direction' => 'out',
8404 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8405 
            'width' => 32,
8406 
          },
8407 
          'reg06_rv' => {
8408 
            'attributes' => {
8409 
              'bin_pt' => 0,
8410 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
8411 
              'is_floating_block' => 1,
8412 
              'is_gateway_port' => 1,
8413 
              'must_be_hdl_vector' => 1,
8414 
              'period' => 1,
8415 
              'port_id' => 0,
8416 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
8417 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
8418 
              'timingConstraint' => 'none',
8419 
              'type' => 'UFix_1_0',
8420 
            },
8421 
            'direction' => 'out',
8422 
            'hdlType' => 'std_logic',
8423 
            'width' => 1,
8424 
          },
8425 
          'reg06_td' => {
8426 
            'attributes' => {
8427 
              'bin_pt' => 0,
8428 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
8429 
              'is_floating_block' => 1,
8430 
              'is_gateway_port' => 1,
8431 
              'must_be_hdl_vector' => 1,
8432 
              'period' => 1,
8433 
              'port_id' => 0,
8434 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
8435 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
8436 
              'timingConstraint' => 'none',
8437 
              'type' => 'UFix_32_0',
8438 
            },
8439 
            'direction' => 'in',
8440 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8441 
            'width' => 32,
8442 
          },
8443 
          'reg06_tv' => {
8444 
            'attributes' => {
8445 
              'bin_pt' => 0,
8446 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
8447 
              'is_floating_block' => 1,
8448 
              'is_gateway_port' => 1,
8449 
              'must_be_hdl_vector' => 1,
8450 
              'period' => 1,
8451 
              'port_id' => 0,
8452 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
8453 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
8454 
              'timingConstraint' => 'none',
8455 
              'type' => 'Bool',
8456 
            },
8457 
            'direction' => 'in',
8458 
            'hdlType' => 'std_logic',
8459 
            'width' => 1,
8460 
          },
8461 
          'reg07_rd' => {
8462 
            'attributes' => {
8463 
              'bin_pt' => 0,
8464 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
8465 
              'is_floating_block' => 1,
8466 
              'is_gateway_port' => 1,
8467 
              'must_be_hdl_vector' => 1,
8468 
              'period' => 1,
8469 
              'port_id' => 0,
8470 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
8471 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
8472 
              'timingConstraint' => 'none',
8473 
              'type' => 'UFix_32_0',
8474 
            },
8475 
            'direction' => 'out',
8476 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8477 
            'width' => 32,
8478 
          },
8479 
          'reg07_rv' => {
8480 
            'attributes' => {
8481 
              'bin_pt' => 0,
8482 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
8483 
              'is_floating_block' => 1,
8484 
              'is_gateway_port' => 1,
8485 
              'must_be_hdl_vector' => 1,
8486 
              'period' => 1,
8487 
              'port_id' => 0,
8488 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
8489 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
8490 
              'timingConstraint' => 'none',
8491 
              'type' => 'UFix_1_0',
8492 
            },
8493 
            'direction' => 'out',
8494 
            'hdlType' => 'std_logic',
8495 
            'width' => 1,
8496 
          },
8497 
          'reg07_td' => {
8498 
            'attributes' => {
8499 
              'bin_pt' => 0,
8500 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
8501 
              'is_floating_block' => 1,
8502 
              'is_gateway_port' => 1,
8503 
              'must_be_hdl_vector' => 1,
8504 
              'period' => 1,
8505 
              'port_id' => 0,
8506 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
8507 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
8508 
              'timingConstraint' => 'none',
8509 
              'type' => 'UFix_32_0',
8510 
            },
8511 
            'direction' => 'in',
8512 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8513 
            'width' => 32,
8514 
          },
8515 
          'reg07_tv' => {
8516 
            'attributes' => {
8517 
              'bin_pt' => 0,
8518 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
8519 
              'is_floating_block' => 1,
8520 
              'is_gateway_port' => 1,
8521 
              'must_be_hdl_vector' => 1,
8522 
              'period' => 1,
8523 
              'port_id' => 0,
8524 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
8525 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
8526 
              'timingConstraint' => 'none',
8527 
              'type' => 'Bool',
8528 
            },
8529 
            'direction' => 'in',
8530 
            'hdlType' => 'std_logic',
8531 
            'width' => 1,
8532 
          },
8533 
          'reg08_rd' => {
8534 
            'attributes' => {
8535 
              'bin_pt' => 0,
8536 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
8537 
              'is_floating_block' => 1,
8538 
              'is_gateway_port' => 1,
8539 
              'must_be_hdl_vector' => 1,
8540 
              'period' => 1,
8541 
              'port_id' => 0,
8542 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
8543 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
8544 
              'timingConstraint' => 'none',
8545 
              'type' => 'UFix_32_0',
8546 
            },
8547 
            'direction' => 'out',
8548 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8549 
            'width' => 32,
8550 
          },
8551 
          'reg08_rv' => {
8552 
            'attributes' => {
8553 
              'bin_pt' => 0,
8554 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
8555 
              'is_floating_block' => 1,
8556 
              'is_gateway_port' => 1,
8557 
              'must_be_hdl_vector' => 1,
8558 
              'period' => 1,
8559 
              'port_id' => 0,
8560 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
8561 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
8562 
              'timingConstraint' => 'none',
8563 
              'type' => 'UFix_1_0',
8564 
            },
8565 
            'direction' => 'out',
8566 
            'hdlType' => 'std_logic',
8567 
            'width' => 1,
8568 
          },
8569 
          'reg08_td' => {
8570 
            'attributes' => {
8571 
              'bin_pt' => 0,
8572 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
8573 
              'is_floating_block' => 1,
8574 
              'is_gateway_port' => 1,
8575 
              'must_be_hdl_vector' => 1,
8576 
              'period' => 1,
8577 
              'port_id' => 0,
8578 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
8579 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
8580 
              'timingConstraint' => 'none',
8581 
              'type' => 'UFix_32_0',
8582 
            },
8583 
            'direction' => 'in',
8584 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8585 
            'width' => 32,
8586 
          },
8587 
          'reg08_tv' => {
8588 
            'attributes' => {
8589 
              'bin_pt' => 0,
8590 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
8591 
              'is_floating_block' => 1,
8592 
              'is_gateway_port' => 1,
8593 
              'must_be_hdl_vector' => 1,
8594 
              'period' => 1,
8595 
              'port_id' => 0,
8596 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
8597 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
8598 
              'timingConstraint' => 'none',
8599 
              'type' => 'Bool',
8600 
            },
8601 
            'direction' => 'in',
8602 
            'hdlType' => 'std_logic',
8603 
            'width' => 1,
8604 
          },
8605 
          'reg09_rd' => {
8606 
            'attributes' => {
8607 
              'bin_pt' => 0,
8608 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
8609 
              'is_floating_block' => 1,
8610 
              'is_gateway_port' => 1,
8611 
              'must_be_hdl_vector' => 1,
8612 
              'period' => 1,
8613 
              'port_id' => 0,
8614 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
8615 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
8616 
              'timingConstraint' => 'none',
8617 
              'type' => 'UFix_32_0',
8618 
            },
8619 
            'direction' => 'out',
8620 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8621 
            'width' => 32,
8622 
          },
8623 
          'reg09_rv' => {
8624 
            'attributes' => {
8625 
              'bin_pt' => 0,
8626 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
8627 
              'is_floating_block' => 1,
8628 
              'is_gateway_port' => 1,
8629 
              'must_be_hdl_vector' => 1,
8630 
              'period' => 1,
8631 
              'port_id' => 0,
8632 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
8633 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
8634 
              'timingConstraint' => 'none',
8635 
              'type' => 'UFix_1_0',
8636 
            },
8637 
            'direction' => 'out',
8638 
            'hdlType' => 'std_logic',
8639 
            'width' => 1,
8640 
          },
8641 
          'reg09_td' => {
8642 
            'attributes' => {
8643 
              'bin_pt' => 0,
8644 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
8645 
              'is_floating_block' => 1,
8646 
              'is_gateway_port' => 1,
8647 
              'must_be_hdl_vector' => 1,
8648 
              'period' => 1,
8649 
              'port_id' => 0,
8650 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
8651 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
8652 
              'timingConstraint' => 'none',
8653 
              'type' => 'UFix_32_0',
8654 
            },
8655 
            'direction' => 'in',
8656 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8657 
            'width' => 32,
8658 
          },
8659 
          'reg09_tv' => {
8660 
            'attributes' => {
8661 
              'bin_pt' => 0,
8662 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
8663 
              'is_floating_block' => 1,
8664 
              'is_gateway_port' => 1,
8665 
              'must_be_hdl_vector' => 1,
8666 
              'period' => 1,
8667 
              'port_id' => 0,
8668 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
8669 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
8670 
              'timingConstraint' => 'none',
8671 
              'type' => 'Bool',
8672 
            },
8673 
            'direction' => 'in',
8674 
            'hdlType' => 'std_logic',
8675 
            'width' => 1,
8676 
          },
8677 
          'reg10_rd' => {
8678 
            'attributes' => {
8679 
              'bin_pt' => 0,
8680 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
8681 
              'is_floating_block' => 1,
8682 
              'is_gateway_port' => 1,
8683 
              'must_be_hdl_vector' => 1,
8684 
              'period' => 1,
8685 
              'port_id' => 0,
8686 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
8687 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
8688 
              'timingConstraint' => 'none',
8689 
              'type' => 'UFix_32_0',
8690 
            },
8691 
            'direction' => 'out',
8692 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8693 
            'width' => 32,
8694 
          },
8695 
          'reg10_rv' => {
8696 
            'attributes' => {
8697 
              'bin_pt' => 0,
8698 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
8699 
              'is_floating_block' => 1,
8700 
              'is_gateway_port' => 1,
8701 
              'must_be_hdl_vector' => 1,
8702 
              'period' => 1,
8703 
              'port_id' => 0,
8704 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
8705 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
8706 
              'timingConstraint' => 'none',
8707 
              'type' => 'UFix_1_0',
8708 
            },
8709 
            'direction' => 'out',
8710 
            'hdlType' => 'std_logic',
8711 
            'width' => 1,
8712 
          },
8713 
          'reg10_td' => {
8714 
            'attributes' => {
8715 
              'bin_pt' => 0,
8716 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
8717 
              'is_floating_block' => 1,
8718 
              'is_gateway_port' => 1,
8719 
              'must_be_hdl_vector' => 1,
8720 
              'period' => 1,
8721 
              'port_id' => 0,
8722 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
8723 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
8724 
              'timingConstraint' => 'none',
8725 
              'type' => 'UFix_32_0',
8726 
            },
8727 
            'direction' => 'in',
8728 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8729 
            'width' => 32,
8730 
          },
8731 
          'reg10_tv' => {
8732 
            'attributes' => {
8733 
              'bin_pt' => 0,
8734 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
8735 
              'is_floating_block' => 1,
8736 
              'is_gateway_port' => 1,
8737 
              'must_be_hdl_vector' => 1,
8738 
              'period' => 1,
8739 
              'port_id' => 0,
8740 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
8741 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
8742 
              'timingConstraint' => 'none',
8743 
              'type' => 'Bool',
8744 
            },
8745 
            'direction' => 'in',
8746 
            'hdlType' => 'std_logic',
8747 
            'width' => 1,
8748 
          },
8749 
          'reg11_rd' => {
8750 
            'attributes' => {
8751 
              'bin_pt' => 0,
8752 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
8753 
              'is_floating_block' => 1,
8754 
              'is_gateway_port' => 1,
8755 
              'must_be_hdl_vector' => 1,
8756 
              'period' => 1,
8757 
              'port_id' => 0,
8758 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
8759 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
8760 
              'timingConstraint' => 'none',
8761 
              'type' => 'UFix_32_0',
8762 
            },
8763 
            'direction' => 'out',
8764 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8765 
            'width' => 32,
8766 
          },
8767 
          'reg11_rv' => {
8768 
            'attributes' => {
8769 
              'bin_pt' => 0,
8770 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
8771 
              'is_floating_block' => 1,
8772 
              'is_gateway_port' => 1,
8773 
              'must_be_hdl_vector' => 1,
8774 
              'period' => 1,
8775 
              'port_id' => 0,
8776 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
8777 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
8778 
              'timingConstraint' => 'none',
8779 
              'type' => 'UFix_1_0',
8780 
            },
8781 
            'direction' => 'out',
8782 
            'hdlType' => 'std_logic',
8783 
            'width' => 1,
8784 
          },
8785 
          'reg11_td' => {
8786 
            'attributes' => {
8787 
              'bin_pt' => 0,
8788 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
8789 
              'is_floating_block' => 1,
8790 
              'is_gateway_port' => 1,
8791 
              'must_be_hdl_vector' => 1,
8792 
              'period' => 1,
8793 
              'port_id' => 0,
8794 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
8795 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
8796 
              'timingConstraint' => 'none',
8797 
              'type' => 'UFix_32_0',
8798 
            },
8799 
            'direction' => 'in',
8800 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8801 
            'width' => 32,
8802 
          },
8803 
          'reg11_tv' => {
8804 
            'attributes' => {
8805 
              'bin_pt' => 0,
8806 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
8807 
              'is_floating_block' => 1,
8808 
              'is_gateway_port' => 1,
8809 
              'must_be_hdl_vector' => 1,
8810 
              'period' => 1,
8811 
              'port_id' => 0,
8812 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
8813 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
8814 
              'timingConstraint' => 'none',
8815 
              'type' => 'Bool',
8816 
            },
8817 
            'direction' => 'in',
8818 
            'hdlType' => 'std_logic',
8819 
            'width' => 1,
8820 
          },
8821 
          'reg12_rd' => {
8822 
            'attributes' => {
8823 
              'bin_pt' => 0,
8824 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
8825 
              'is_floating_block' => 1,
8826 
              'is_gateway_port' => 1,
8827 
              'must_be_hdl_vector' => 1,
8828 
              'period' => 1,
8829 
              'port_id' => 0,
8830 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
8831 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
8832 
              'timingConstraint' => 'none',
8833 
              'type' => 'UFix_32_0',
8834 
            },
8835 
            'direction' => 'out',
8836 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8837 
            'width' => 32,
8838 
          },
8839 
          'reg12_rv' => {
8840 
            'attributes' => {
8841 
              'bin_pt' => 0,
8842 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
8843 
              'is_floating_block' => 1,
8844 
              'is_gateway_port' => 1,
8845 
              'must_be_hdl_vector' => 1,
8846 
              'period' => 1,
8847 
              'port_id' => 0,
8848 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
8849 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
8850 
              'timingConstraint' => 'none',
8851 
              'type' => 'UFix_1_0',
8852 
            },
8853 
            'direction' => 'out',
8854 
            'hdlType' => 'std_logic',
8855 
            'width' => 1,
8856 
          },
8857 
          'reg12_td' => {
8858 
            'attributes' => {
8859 
              'bin_pt' => 0,
8860 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
8861 
              'is_floating_block' => 1,
8862 
              'is_gateway_port' => 1,
8863 
              'must_be_hdl_vector' => 1,
8864 
              'period' => 1,
8865 
              'port_id' => 0,
8866 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
8867 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
8868 
              'timingConstraint' => 'none',
8869 
              'type' => 'UFix_32_0',
8870 
            },
8871 
            'direction' => 'in',
8872 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8873 
            'width' => 32,
8874 
          },
8875 
          'reg12_tv' => {
8876 
            'attributes' => {
8877 
              'bin_pt' => 0,
8878 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
8879 
              'is_floating_block' => 1,
8880 
              'is_gateway_port' => 1,
8881 
              'must_be_hdl_vector' => 1,
8882 
              'period' => 1,
8883 
              'port_id' => 0,
8884 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
8885 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
8886 
              'timingConstraint' => 'none',
8887 
              'type' => 'Bool',
8888 
            },
8889 
            'direction' => 'in',
8890 
            'hdlType' => 'std_logic',
8891 
            'width' => 1,
8892 
          },
8893 
          'reg13_rd' => {
8894 
            'attributes' => {
8895 
              'bin_pt' => 0,
8896 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
8897 
              'is_floating_block' => 1,
8898 
              'is_gateway_port' => 1,
8899 
              'must_be_hdl_vector' => 1,
8900 
              'period' => 1,
8901 
              'port_id' => 0,
8902 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
8903 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
8904 
              'timingConstraint' => 'none',
8905 
              'type' => 'UFix_32_0',
8906 
            },
8907 
            'direction' => 'out',
8908 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8909 
            'width' => 32,
8910 
          },
8911 
          'reg13_rv' => {
8912 
            'attributes' => {
8913 
              'bin_pt' => 0,
8914 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
8915 
              'is_floating_block' => 1,
8916 
              'is_gateway_port' => 1,
8917 
              'must_be_hdl_vector' => 1,
8918 
              'period' => 1,
8919 
              'port_id' => 0,
8920 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
8921 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
8922 
              'timingConstraint' => 'none',
8923 
              'type' => 'UFix_1_0',
8924 
            },
8925 
            'direction' => 'out',
8926 
            'hdlType' => 'std_logic',
8927 
            'width' => 1,
8928 
          },
8929 
          'reg13_td' => {
8930 
            'attributes' => {
8931 
              'bin_pt' => 0,
8932 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
8933 
              'is_floating_block' => 1,
8934 
              'is_gateway_port' => 1,
8935 
              'must_be_hdl_vector' => 1,
8936 
              'period' => 1,
8937 
              'port_id' => 0,
8938 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
8939 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
8940 
              'timingConstraint' => 'none',
8941 
              'type' => 'UFix_32_0',
8942 
            },
8943 
            'direction' => 'in',
8944 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8945 
            'width' => 32,
8946 
          },
8947 
          'reg13_tv' => {
8948 
            'attributes' => {
8949 
              'bin_pt' => 0,
8950 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
8951 
              'is_floating_block' => 1,
8952 
              'is_gateway_port' => 1,
8953 
              'must_be_hdl_vector' => 1,
8954 
              'period' => 1,
8955 
              'port_id' => 0,
8956 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
8957 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
8958 
              'timingConstraint' => 'none',
8959 
              'type' => 'Bool',
8960 
            },
8961 
            'direction' => 'in',
8962 
            'hdlType' => 'std_logic',
8963 
            'width' => 1,
8964 
          },
8965 
          'reg14_rd' => {
8966 
            'attributes' => {
8967 
              'bin_pt' => 0,
8968 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
8969 
              'is_floating_block' => 1,
8970 
              'is_gateway_port' => 1,
8971 
              'must_be_hdl_vector' => 1,
8972 
              'period' => 1,
8973 
              'port_id' => 0,
8974 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
8975 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
8976 
              'timingConstraint' => 'none',
8977 
              'type' => 'UFix_32_0',
8978 
            },
8979 
            'direction' => 'out',
8980 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8981 
            'width' => 32,
8982 
          },
8983 
          'reg14_rv' => {
8984 
            'attributes' => {
8985 
              'bin_pt' => 0,
8986 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
8987 
              'is_floating_block' => 1,
8988 
              'is_gateway_port' => 1,
8989 
              'must_be_hdl_vector' => 1,
8990 
              'period' => 1,
8991 
              'port_id' => 0,
8992 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
8993 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
8994 
              'timingConstraint' => 'none',
8995 
              'type' => 'UFix_1_0',
8996 
            },
8997 
            'direction' => 'out',
8998 
            'hdlType' => 'std_logic',
8999 
            'width' => 1,
9000 
          },
9001 
          'reg14_td' => {
9002 
            'attributes' => {
9003 
              'bin_pt' => 0,
9004 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
9005 
              'is_floating_block' => 1,
9006 
              'is_gateway_port' => 1,
9007 
              'must_be_hdl_vector' => 1,
9008 
              'period' => 1,
9009 
              'port_id' => 0,
9010 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
9011 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
9012 
              'timingConstraint' => 'none',
9013 
              'type' => 'UFix_32_0',
9014 
            },
9015 
            'direction' => 'in',
9016 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9017 
            'width' => 32,
9018 
          },
9019 
          'reg14_tv' => {
9020 
            'attributes' => {
9021 
              'bin_pt' => 0,
9022 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
9023 
              'is_floating_block' => 1,
9024 
              'is_gateway_port' => 1,
9025 
              'must_be_hdl_vector' => 1,
9026 
              'period' => 1,
9027 
              'port_id' => 0,
9028 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
9029 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
9030 
              'timingConstraint' => 'none',
9031 
              'type' => 'Bool',
9032 
            },
9033 
            'direction' => 'in',
9034 
            'hdlType' => 'std_logic',
9035 
            'width' => 1,
9036 
          },
9037 
          'to_register10_ce' => {
9038 
            'attributes' => {
9039 
              'domain' => '',
9040 
              'group' => 1,
9041 
              'isCe' => 1,
9042 
              'is_floating_block' => 1,
9043 
              'period' => 1,
9044 
              'type' => 'logic',
9045 
            },
9046 
            'direction' => 'out',
9047 
            'hdlType' => 'std_logic',
9048 
            'width' => 1,
9049 
          },
9050 
          'to_register10_clk' => {
9051 
            'attributes' => {
9052 
              'domain' => '',
9053 
              'group' => 1,
9054 
              'isClk' => 1,
9055 
              'is_floating_block' => 1,
9056 
              'period' => 1,
9057 
              'type' => 'logic',
9058 
            },
9059 
            'direction' => 'out',
9060 
            'hdlType' => 'std_logic',
9061 
            'width' => 1,
9062 
          },
9063 
          'to_register10_clr' => {
9064 
            'attributes' => {
9065 
              'domain' => '',
9066 
              'group' => 1,
9067 
              'isClr' => 1,
9068 
              'is_floating_block' => 1,
9069 
              'period' => 1,
9070 
              'type' => 'logic',
9071 
              'valid_bit_used' => 0,
9072 
            },
9073 
            'direction' => 'out',
9074 
            'hdlType' => 'std_logic',
9075 
            'width' => 1,
9076 
          },
9077 
          'to_register10_data_in' => {
9078 
            'attributes' => {
9079 
              'bin_pt' => 0,
9080 
              'is_floating_block' => 1,
9081 
              'must_be_hdl_vector' => 1,
9082 
              'period' => 1,
9083 
              'port_id' => 0,
9084 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
9085 
              'type' => 'Bool',
9086 
            },
9087 
            'direction' => 'out',
9088 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9089 
            'width' => 1,
9090 
          },
9091 
          'to_register10_dout' => {
9092 
            'attributes' => {
9093 
              'bin_pt' => 0,
9094 
              'is_floating_block' => 1,
9095 
              'must_be_hdl_vector' => 1,
9096 
              'period' => 1,
9097 
              'port_id' => 0,
9098 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
9099 
              'type' => 'Bool',
9100 
            },
9101 
            'direction' => 'in',
9102 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9103 
            'width' => 1,
9104 
          },
9105 
          'to_register10_en' => {
9106 
            'attributes' => {
9107 
              'bin_pt' => 0,
9108 
              'is_floating_block' => 1,
9109 
              'must_be_hdl_vector' => 1,
9110 
              'period' => 1,
9111 
              'port_id' => 1,
9112 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
9113 
              'type' => 'Bool',
9114 
            },
9115 
            'direction' => 'out',
9116 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9117 
            'width' => 1,
9118 
          },
9119 
          'to_register11_ce' => {
9120 
            'attributes' => {
9121 
              'domain' => '',
9122 
              'group' => 1,
9123 
              'isCe' => 1,
9124 
              'is_floating_block' => 1,
9125 
              'period' => 1,
9126 
              'type' => 'logic',
9127 
            },
9128 
            'direction' => 'out',
9129 
            'hdlType' => 'std_logic',
9130 
            'width' => 1,
9131 
          },
9132 
          'to_register11_clk' => {
9133 
            'attributes' => {
9134 
              'domain' => '',
9135 
              'group' => 1,
9136 
              'isClk' => 1,
9137 
              'is_floating_block' => 1,
9138 
              'period' => 1,
9139 
              'type' => 'logic',
9140 
            },
9141 
            'direction' => 'out',
9142 
            'hdlType' => 'std_logic',
9143 
            'width' => 1,
9144 
          },
9145 
          'to_register11_clr' => {
9146 
            'attributes' => {
9147 
              'domain' => '',
9148 
              'group' => 1,
9149 
              'isClr' => 1,
9150 
              'is_floating_block' => 1,
9151 
              'period' => 1,
9152 
              'type' => 'logic',
9153 
              'valid_bit_used' => 0,
9154 
            },
9155 
            'direction' => 'out',
9156 
            'hdlType' => 'std_logic',
9157 
            'width' => 1,
9158 
          },
9159 
          'to_register11_data_in' => {
9160 
            'attributes' => {
9161 
              'bin_pt' => 0,
9162 
              'is_floating_block' => 1,
9163 
              'must_be_hdl_vector' => 1,
9164 
              'period' => 1,
9165 
              'port_id' => 0,
9166 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
9167 
              'type' => 'UFix_32_0',
9168 
            },
9169 
            'direction' => 'out',
9170 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9171 
            'width' => 32,
9172 
          },
9173 
          'to_register11_dout' => {
9174 
            'attributes' => {
9175 
              'bin_pt' => 0,
9176 
              'is_floating_block' => 1,
9177 
              'must_be_hdl_vector' => 1,
9178 
              'period' => 1,
9179 
              'port_id' => 0,
9180 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
9181 
              'type' => 'UFix_32_0',
9182 
            },
9183 
            'direction' => 'in',
9184 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9185 
            'width' => 32,
9186 
          },
9187 
          'to_register11_en' => {
9188 
            'attributes' => {
9189 
              'bin_pt' => 0,
9190 
              'is_floating_block' => 1,
9191 
              'must_be_hdl_vector' => 1,
9192 
              'period' => 1,
9193 
              'port_id' => 1,
9194 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
9195 
              'type' => 'Bool',
9196 
            },
9197 
            'direction' => 'out',
9198 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9199 
            'width' => 1,
9200 
          },
9201 
          'to_register12_ce' => {
9202 
            'attributes' => {
9203 
              'domain' => '',
9204 
              'group' => 1,
9205 
              'isCe' => 1,
9206 
              'is_floating_block' => 1,
9207 
              'period' => 1,
9208 
              'type' => 'logic',
9209 
            },
9210 
            'direction' => 'out',
9211 
            'hdlType' => 'std_logic',
9212 
            'width' => 1,
9213 
          },
9214 
          'to_register12_clk' => {
9215 
            'attributes' => {
9216 
              'domain' => '',
9217 
              'group' => 1,
9218 
              'isClk' => 1,
9219 
              'is_floating_block' => 1,
9220 
              'period' => 1,
9221 
              'type' => 'logic',
9222 
            },
9223 
            'direction' => 'out',
9224 
            'hdlType' => 'std_logic',
9225 
            'width' => 1,
9226 
          },
9227 
          'to_register12_clr' => {
9228 
            'attributes' => {
9229 
              'domain' => '',
9230 
              'group' => 1,
9231 
              'isClr' => 1,
9232 
              'is_floating_block' => 1,
9233 
              'period' => 1,
9234 
              'type' => 'logic',
9235 
              'valid_bit_used' => 0,
9236 
            },
9237 
            'direction' => 'out',
9238 
            'hdlType' => 'std_logic',
9239 
            'width' => 1,
9240 
          },
9241 
          'to_register12_data_in' => {
9242 
            'attributes' => {
9243 
              'bin_pt' => 0,
9244 
              'is_floating_block' => 1,
9245 
              'must_be_hdl_vector' => 1,
9246 
              'period' => 1,
9247 
              'port_id' => 0,
9248 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
9249 
              'type' => 'Bool',
9250 
            },
9251 
            'direction' => 'out',
9252 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9253 
            'width' => 1,
9254 
          },
9255 
          'to_register12_dout' => {
9256 
            'attributes' => {
9257 
              'bin_pt' => 0,
9258 
              'is_floating_block' => 1,
9259 
              'must_be_hdl_vector' => 1,
9260 
              'period' => 1,
9261 
              'port_id' => 0,
9262 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
9263 
              'type' => 'Bool',
9264 
            },
9265 
            'direction' => 'in',
9266 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9267 
            'width' => 1,
9268 
          },
9269 
          'to_register12_en' => {
9270 
            'attributes' => {
9271 
              'bin_pt' => 0,
9272 
              'is_floating_block' => 1,
9273 
              'must_be_hdl_vector' => 1,
9274 
              'period' => 1,
9275 
              'port_id' => 1,
9276 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
9277 
              'type' => 'Bool',
9278 
            },
9279 
            'direction' => 'out',
9280 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9281 
            'width' => 1,
9282 
          },
9283 
          'to_register13_ce' => {
9284 
            'attributes' => {
9285 
              'domain' => '',
9286 
              'group' => 1,
9287 
              'isCe' => 1,
9288 
              'is_floating_block' => 1,
9289 
              'period' => 1,
9290 
              'type' => 'logic',
9291 
            },
9292 
            'direction' => 'out',
9293 
            'hdlType' => 'std_logic',
9294 
            'width' => 1,
9295 
          },
9296 
          'to_register13_clk' => {
9297 
            'attributes' => {
9298 
              'domain' => '',
9299 
              'group' => 1,
9300 
              'isClk' => 1,
9301 
              'is_floating_block' => 1,
9302 
              'period' => 1,
9303 
              'type' => 'logic',
9304 
            },
9305 
            'direction' => 'out',
9306 
            'hdlType' => 'std_logic',
9307 
            'width' => 1,
9308 
          },
9309 
          'to_register13_clr' => {
9310 
            'attributes' => {
9311 
              'domain' => '',
9312 
              'group' => 1,
9313 
              'isClr' => 1,
9314 
              'is_floating_block' => 1,
9315 
              'period' => 1,
9316 
              'type' => 'logic',
9317 
              'valid_bit_used' => 0,
9318 
            },
9319 
            'direction' => 'out',
9320 
            'hdlType' => 'std_logic',
9321 
            'width' => 1,
9322 
          },
9323 
          'to_register13_data_in' => {
9324 
            'attributes' => {
9325 
              'bin_pt' => 0,
9326 
              'is_floating_block' => 1,
9327 
              'must_be_hdl_vector' => 1,
9328 
              'period' => 1,
9329 
              'port_id' => 0,
9330 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
9331 
              'type' => 'UFix_32_0',
9332 
            },
9333 
            'direction' => 'out',
9334 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9335 
            'width' => 32,
9336 
          },
9337 
          'to_register13_dout' => {
9338 
            'attributes' => {
9339 
              'bin_pt' => 0,
9340 
              'is_floating_block' => 1,
9341 
              'must_be_hdl_vector' => 1,
9342 
              'period' => 1,
9343 
              'port_id' => 0,
9344 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
9345 
              'type' => 'UFix_32_0',
9346 
            },
9347 
            'direction' => 'in',
9348 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9349 
            'width' => 32,
9350 
          },
9351 
          'to_register13_en' => {
9352 
            'attributes' => {
9353 
              'bin_pt' => 0,
9354 
              'is_floating_block' => 1,
9355 
              'must_be_hdl_vector' => 1,
9356 
              'period' => 1,
9357 
              'port_id' => 1,
9358 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
9359 
              'type' => 'Bool',
9360 
            },
9361 
            'direction' => 'out',
9362 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9363 
            'width' => 1,
9364 
          },
9365 
          'to_register14_ce' => {
9366 
            'attributes' => {
9367 
              'domain' => '',
9368 
              'group' => 1,
9369 
              'isCe' => 1,
9370 
              'is_floating_block' => 1,
9371 
              'period' => 1,
9372 
              'type' => 'logic',
9373 
            },
9374 
            'direction' => 'out',
9375 
            'hdlType' => 'std_logic',
9376 
            'width' => 1,
9377 
          },
9378 
          'to_register14_clk' => {
9379 
            'attributes' => {
9380 
              'domain' => '',
9381 
              'group' => 1,
9382 
              'isClk' => 1,
9383 
              'is_floating_block' => 1,
9384 
              'period' => 1,
9385 
              'type' => 'logic',
9386 
            },
9387 
            'direction' => 'out',
9388 
            'hdlType' => 'std_logic',
9389 
            'width' => 1,
9390 
          },
9391 
          'to_register14_clr' => {
9392 
            'attributes' => {
9393 
              'domain' => '',
9394 
              'group' => 1,
9395 
              'isClr' => 1,
9396 
              'is_floating_block' => 1,
9397 
              'period' => 1,
9398 
              'type' => 'logic',
9399 
              'valid_bit_used' => 0,
9400 
            },
9401 
            'direction' => 'out',
9402 
            'hdlType' => 'std_logic',
9403 
            'width' => 1,
9404 
          },
9405 
          'to_register14_data_in' => {
9406 
            'attributes' => {
9407 
              'bin_pt' => 0,
9408 
              'is_floating_block' => 1,
9409 
              'must_be_hdl_vector' => 1,
9410 
              'period' => 1,
9411 
              'port_id' => 0,
9412 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
9413 
              'type' => 'Bool',
9414 
            },
9415 
            'direction' => 'out',
9416 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9417 
            'width' => 1,
9418 
          },
9419 
          'to_register14_dout' => {
9420 
            'attributes' => {
9421 
              'bin_pt' => 0,
9422 
              'is_floating_block' => 1,
9423 
              'must_be_hdl_vector' => 1,
9424 
              'period' => 1,
9425 
              'port_id' => 0,
9426 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
9427 
              'type' => 'Bool',
9428 
            },
9429 
            'direction' => 'in',
9430 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9431 
            'width' => 1,
9432 
          },
9433 
          'to_register14_en' => {
9434 
            'attributes' => {
9435 
              'bin_pt' => 0,
9436 
              'is_floating_block' => 1,
9437 
              'must_be_hdl_vector' => 1,
9438 
              'period' => 1,
9439 
              'port_id' => 1,
9440 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
9441 
              'type' => 'Bool',
9442 
            },
9443 
            'direction' => 'out',
9444 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9445 
            'width' => 1,
9446 
          },
9447 
          'to_register15_ce' => {
9448 
            'attributes' => {
9449 
              'domain' => '',
9450 
              'group' => 1,
9451 
              'isCe' => 1,
9452 
              'is_floating_block' => 1,
9453 
              'period' => 1,
9454 
              'type' => 'logic',
9455 
            },
9456 
            'direction' => 'out',
9457 
            'hdlType' => 'std_logic',
9458 
            'width' => 1,
9459 
          },
9460 
          'to_register15_clk' => {
9461 
            'attributes' => {
9462 
              'domain' => '',
9463 
              'group' => 1,
9464 
              'isClk' => 1,
9465 
              'is_floating_block' => 1,
9466 
              'period' => 1,
9467 
              'type' => 'logic',
9468 
            },
9469 
            'direction' => 'out',
9470 
            'hdlType' => 'std_logic',
9471 
            'width' => 1,
9472 
          },
9473 
          'to_register15_clr' => {
9474 
            'attributes' => {
9475 
              'domain' => '',
9476 
              'group' => 1,
9477 
              'isClr' => 1,
9478 
              'is_floating_block' => 1,
9479 
              'period' => 1,
9480 
              'type' => 'logic',
9481 
              'valid_bit_used' => 0,
9482 
            },
9483 
            'direction' => 'out',
9484 
            'hdlType' => 'std_logic',
9485 
            'width' => 1,
9486 
          },
9487 
          'to_register15_data_in' => {
9488 
            'attributes' => {
9489 
              'bin_pt' => 0,
9490 
              'is_floating_block' => 1,
9491 
              'must_be_hdl_vector' => 1,
9492 
              'period' => 1,
9493 
              'port_id' => 0,
9494 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
9495 
              'type' => 'UFix_32_0',
9496 
            },
9497 
            'direction' => 'out',
9498 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9499 
            'width' => 32,
9500 
          },
9501 
          'to_register15_dout' => {
9502 
            'attributes' => {
9503 
              'bin_pt' => 0,
9504 
              'is_floating_block' => 1,
9505 
              'must_be_hdl_vector' => 1,
9506 
              'period' => 1,
9507 
              'port_id' => 0,
9508 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
9509 
              'type' => 'UFix_32_0',
9510 
            },
9511 
            'direction' => 'in',
9512 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9513 
            'width' => 32,
9514 
          },
9515 
          'to_register15_en' => {
9516 
            'attributes' => {
9517 
              'bin_pt' => 0,
9518 
              'is_floating_block' => 1,
9519 
              'must_be_hdl_vector' => 1,
9520 
              'period' => 1,
9521 
              'port_id' => 1,
9522 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
9523 
              'type' => 'Bool',
9524 
            },
9525 
            'direction' => 'out',
9526 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9527 
            'width' => 1,
9528 
          },
9529 
          'to_register16_ce' => {
9530 
            'attributes' => {
9531 
              'domain' => '',
9532 
              'group' => 1,
9533 
              'isCe' => 1,
9534 
              'is_floating_block' => 1,
9535 
              'period' => 1,
9536 
              'type' => 'logic',
9537 
            },
9538 
            'direction' => 'out',
9539 
            'hdlType' => 'std_logic',
9540 
            'width' => 1,
9541 
          },
9542 
          'to_register16_clk' => {
9543 
            'attributes' => {
9544 
              'domain' => '',
9545 
              'group' => 1,
9546 
              'isClk' => 1,
9547 
              'is_floating_block' => 1,
9548 
              'period' => 1,
9549 
              'type' => 'logic',
9550 
            },
9551 
            'direction' => 'out',
9552 
            'hdlType' => 'std_logic',
9553 
            'width' => 1,
9554 
          },
9555 
          'to_register16_clr' => {
9556 
            'attributes' => {
9557 
              'domain' => '',
9558 
              'group' => 1,
9559 
              'isClr' => 1,
9560 
              'is_floating_block' => 1,
9561 
              'period' => 1,
9562 
              'type' => 'logic',
9563 
              'valid_bit_used' => 0,
9564 
            },
9565 
            'direction' => 'out',
9566 
            'hdlType' => 'std_logic',
9567 
            'width' => 1,
9568 
          },
9569 
          'to_register16_data_in' => {
9570 
            'attributes' => {
9571 
              'bin_pt' => 0,
9572 
              'is_floating_block' => 1,
9573 
              'must_be_hdl_vector' => 1,
9574 
              'period' => 1,
9575 
              'port_id' => 0,
9576 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
9577 
              'type' => 'Bool',
9578 
            },
9579 
            'direction' => 'out',
9580 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9581 
            'width' => 1,
9582 
          },
9583 
          'to_register16_dout' => {
9584 
            'attributes' => {
9585 
              'bin_pt' => 0,
9586 
              'is_floating_block' => 1,
9587 
              'must_be_hdl_vector' => 1,
9588 
              'period' => 1,
9589 
              'port_id' => 0,
9590 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
9591 
              'type' => 'Bool',
9592 
            },
9593 
            'direction' => 'in',
9594 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9595 
            'width' => 1,
9596 
          },
9597 
          'to_register16_en' => {
9598 
            'attributes' => {
9599 
              'bin_pt' => 0,
9600 
              'is_floating_block' => 1,
9601 
              'must_be_hdl_vector' => 1,
9602 
              'period' => 1,
9603 
              'port_id' => 1,
9604 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
9605 
              'type' => 'Bool',
9606 
            },
9607 
            'direction' => 'out',
9608 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9609 
            'width' => 1,
9610 
          },
9611 
          'to_register17_ce' => {
9612 
            'attributes' => {
9613 
              'domain' => '',
9614 
              'group' => 1,
9615 
              'isCe' => 1,
9616 
              'is_floating_block' => 1,
9617 
              'period' => 1,
9618 
              'type' => 'logic',
9619 
            },
9620 
            'direction' => 'out',
9621 
            'hdlType' => 'std_logic',
9622 
            'width' => 1,
9623 
          },
9624 
          'to_register17_clk' => {
9625 
            'attributes' => {
9626 
              'domain' => '',
9627 
              'group' => 1,
9628 
              'isClk' => 1,
9629 
              'is_floating_block' => 1,
9630 
              'period' => 1,
9631 
              'type' => 'logic',
9632 
            },
9633 
            'direction' => 'out',
9634 
            'hdlType' => 'std_logic',
9635 
            'width' => 1,
9636 
          },
9637 
          'to_register17_clr' => {
9638 
            'attributes' => {
9639 
              'domain' => '',
9640 
              'group' => 1,
9641 
              'isClr' => 1,
9642 
              'is_floating_block' => 1,
9643 
              'period' => 1,
9644 
              'type' => 'logic',
9645 
              'valid_bit_used' => 0,
9646 
            },
9647 
            'direction' => 'out',
9648 
            'hdlType' => 'std_logic',
9649 
            'width' => 1,
9650 
          },
9651 
          'to_register17_data_in' => {
9652 
            'attributes' => {
9653 
              'bin_pt' => 0,
9654 
              'is_floating_block' => 1,
9655 
              'must_be_hdl_vector' => 1,
9656 
              'period' => 1,
9657 
              'port_id' => 0,
9658 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
9659 
              'type' => 'UFix_32_0',
9660 
            },
9661 
            'direction' => 'out',
9662 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9663 
            'width' => 32,
9664 
          },
9665 
          'to_register17_dout' => {
9666 
            'attributes' => {
9667 
              'bin_pt' => 0,
9668 
              'is_floating_block' => 1,
9669 
              'must_be_hdl_vector' => 1,
9670 
              'period' => 1,
9671 
              'port_id' => 0,
9672 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
9673 
              'type' => 'UFix_32_0',
9674 
            },
9675 
            'direction' => 'in',
9676 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9677 
            'width' => 32,
9678 
          },
9679 
          'to_register17_en' => {
9680 
            'attributes' => {
9681 
              'bin_pt' => 0,
9682 
              'is_floating_block' => 1,
9683 
              'must_be_hdl_vector' => 1,
9684 
              'period' => 1,
9685 
              'port_id' => 1,
9686 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
9687 
              'type' => 'Bool',
9688 
            },
9689 
            'direction' => 'out',
9690 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9691 
            'width' => 1,
9692 
          },
9693 
          'to_register18_ce' => {
9694 
            'attributes' => {
9695 
              'domain' => '',
9696 
              'group' => 1,
9697 
              'isCe' => 1,
9698 
              'is_floating_block' => 1,
9699 
              'period' => 1,
9700 
              'type' => 'logic',
9701 
            },
9702 
            'direction' => 'out',
9703 
            'hdlType' => 'std_logic',
9704 
            'width' => 1,
9705 
          },
9706 
          'to_register18_clk' => {
9707 
            'attributes' => {
9708 
              'domain' => '',
9709 
              'group' => 1,
9710 
              'isClk' => 1,
9711 
              'is_floating_block' => 1,
9712 
              'period' => 1,
9713 
              'type' => 'logic',
9714 
            },
9715 
            'direction' => 'out',
9716 
            'hdlType' => 'std_logic',
9717 
            'width' => 1,
9718 
          },
9719 
          'to_register18_clr' => {
9720 
            'attributes' => {
9721 
              'domain' => '',
9722 
              'group' => 1,
9723 
              'isClr' => 1,
9724 
              'is_floating_block' => 1,
9725 
              'period' => 1,
9726 
              'type' => 'logic',
9727 
              'valid_bit_used' => 0,
9728 
            },
9729 
            'direction' => 'out',
9730 
            'hdlType' => 'std_logic',
9731 
            'width' => 1,
9732 
          },
9733 
          'to_register18_data_in' => {
9734 
            'attributes' => {
9735 
              'bin_pt' => 0,
9736 
              'is_floating_block' => 1,
9737 
              'must_be_hdl_vector' => 1,
9738 
              'period' => 1,
9739 
              'port_id' => 0,
9740 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
9741 
              'type' => 'UFix_1_0',
9742 
            },
9743 
            'direction' => 'out',
9744 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9745 
            'width' => 1,
9746 
          },
9747 
          'to_register18_dout' => {
9748 
            'attributes' => {
9749 
              'bin_pt' => 0,
9750 
              'is_floating_block' => 1,
9751 
              'must_be_hdl_vector' => 1,
9752 
              'period' => 1,
9753 
              'port_id' => 0,
9754 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
9755 
              'type' => 'UFix_1_0',
9756 
            },
9757 
            'direction' => 'in',
9758 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9759 
            'width' => 1,
9760 
          },
9761 
          'to_register18_en' => {
9762 
            'attributes' => {
9763 
              'bin_pt' => 0,
9764 
              'is_floating_block' => 1,
9765 
              'must_be_hdl_vector' => 1,
9766 
              'period' => 1,
9767 
              'port_id' => 1,
9768 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
9769 
              'type' => 'Bool',
9770 
            },
9771 
            'direction' => 'out',
9772 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9773 
            'width' => 1,
9774 
          },
9775 
          'to_register19_ce' => {
9776 
            'attributes' => {
9777 
              'domain' => '',
9778 
              'group' => 1,
9779 
              'isCe' => 1,
9780 
              'is_floating_block' => 1,
9781 
              'period' => 1,
9782 
              'type' => 'logic',
9783 
            },
9784 
            'direction' => 'out',
9785 
            'hdlType' => 'std_logic',
9786 
            'width' => 1,
9787 
          },
9788 
          'to_register19_clk' => {
9789 
            'attributes' => {
9790 
              'domain' => '',
9791 
              'group' => 1,
9792 
              'isClk' => 1,
9793 
              'is_floating_block' => 1,
9794 
              'period' => 1,
9795 
              'type' => 'logic',
9796 
            },
9797 
            'direction' => 'out',
9798 
            'hdlType' => 'std_logic',
9799 
            'width' => 1,
9800 
          },
9801 
          'to_register19_clr' => {
9802 
            'attributes' => {
9803 
              'domain' => '',
9804 
              'group' => 1,
9805 
              'isClr' => 1,
9806 
              'is_floating_block' => 1,
9807 
              'period' => 1,
9808 
              'type' => 'logic',
9809 
              'valid_bit_used' => 0,
9810 
            },
9811 
            'direction' => 'out',
9812 
            'hdlType' => 'std_logic',
9813 
            'width' => 1,
9814 
          },
9815 
          'to_register19_data_in' => {
9816 
            'attributes' => {
9817 
              'bin_pt' => 0,
9818 
              'is_floating_block' => 1,
9819 
              'must_be_hdl_vector' => 1,
9820 
              'period' => 1,
9821 
              'port_id' => 0,
9822 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
9823 
              'type' => 'UFix_1_0',
9824 
            },
9825 
            'direction' => 'out',
9826 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9827 
            'width' => 1,
9828 
          },
9829 
          'to_register19_dout' => {
9830 
            'attributes' => {
9831 
              'bin_pt' => 0,
9832 
              'is_floating_block' => 1,
9833 
              'must_be_hdl_vector' => 1,
9834 
              'period' => 1,
9835 
              'port_id' => 0,
9836 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
9837 
              'type' => 'UFix_1_0',
9838 
            },
9839 
            'direction' => 'in',
9840 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9841 
            'width' => 1,
9842 
          },
9843 
          'to_register19_en' => {
9844 
            'attributes' => {
9845 
              'bin_pt' => 0,
9846 
              'is_floating_block' => 1,
9847 
              'must_be_hdl_vector' => 1,
9848 
              'period' => 1,
9849 
              'port_id' => 1,
9850 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
9851 
              'type' => 'Bool',
9852 
            },
9853 
            'direction' => 'out',
9854 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9855 
            'width' => 1,
9856 
          },
9857 
          'to_register1_ce' => {
9858 
            'attributes' => {
9859 
              'domain' => '',
9860 
              'group' => 1,
9861 
              'isCe' => 1,
9862 
              'is_floating_block' => 1,
9863 
              'period' => 1,
9864 
              'type' => 'logic',
9865 
            },
9866 
            'direction' => 'out',
9867 
            'hdlType' => 'std_logic',
9868 
            'width' => 1,
9869 
          },
9870 
          'to_register1_clk' => {
9871 
            'attributes' => {
9872 
              'domain' => '',
9873 
              'group' => 1,
9874 
              'isClk' => 1,
9875 
              'is_floating_block' => 1,
9876 
              'period' => 1,
9877 
              'type' => 'logic',
9878 
            },
9879 
            'direction' => 'out',
9880 
            'hdlType' => 'std_logic',
9881 
            'width' => 1,
9882 
          },
9883 
          'to_register1_clr' => {
9884 
            'attributes' => {
9885 
              'domain' => '',
9886 
              'group' => 1,
9887 
              'isClr' => 1,
9888 
              'is_floating_block' => 1,
9889 
              'period' => 1,
9890 
              'type' => 'logic',
9891 
              'valid_bit_used' => 0,
9892 
            },
9893 
            'direction' => 'out',
9894 
            'hdlType' => 'std_logic',
9895 
            'width' => 1,
9896 
          },
9897 
          'to_register1_data_in' => {
9898 
            'attributes' => {
9899 
              'bin_pt' => 0,
9900 
              'is_floating_block' => 1,
9901 
              'must_be_hdl_vector' => 1,
9902 
              'period' => 1,
9903 
              'port_id' => 0,
9904 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
9905 
              'type' => 'UFix_32_0',
9906 
            },
9907 
            'direction' => 'out',
9908 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9909 
            'width' => 32,
9910 
          },
9911 
          'to_register1_dout' => {
9912 
            'attributes' => {
9913 
              'bin_pt' => 0,
9914 
              'is_floating_block' => 1,
9915 
              'must_be_hdl_vector' => 1,
9916 
              'period' => 1,
9917 
              'port_id' => 0,
9918 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
9919 
              'type' => 'UFix_32_0',
9920 
            },
9921 
            'direction' => 'in',
9922 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9923 
            'width' => 32,
9924 
          },
9925 
          'to_register1_en' => {
9926 
            'attributes' => {
9927 
              'bin_pt' => 0,
9928 
              'is_floating_block' => 1,
9929 
              'must_be_hdl_vector' => 1,
9930 
              'period' => 1,
9931 
              'port_id' => 1,
9932 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
9933 
              'type' => 'Bool',
9934 
            },
9935 
            'direction' => 'out',
9936 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9937 
            'width' => 1,
9938 
          },
9939 
          'to_register20_ce' => {
9940 
            'attributes' => {
9941 
              'domain' => '',
9942 
              'group' => 1,
9943 
              'isCe' => 1,
9944 
              'is_floating_block' => 1,
9945 
              'period' => 1,
9946 
              'type' => 'logic',
9947 
            },
9948 
            'direction' => 'out',
9949 
            'hdlType' => 'std_logic',
9950 
            'width' => 1,
9951 
          },
9952 
          'to_register20_clk' => {
9953 
            'attributes' => {
9954 
              'domain' => '',
9955 
              'group' => 1,
9956 
              'isClk' => 1,
9957 
              'is_floating_block' => 1,
9958 
              'period' => 1,
9959 
              'type' => 'logic',
9960 
            },
9961 
            'direction' => 'out',
9962 
            'hdlType' => 'std_logic',
9963 
            'width' => 1,
9964 
          },
9965 
          'to_register20_clr' => {
9966 
            'attributes' => {
9967 
              'domain' => '',
9968 
              'group' => 1,
9969 
              'isClr' => 1,
9970 
              'is_floating_block' => 1,
9971 
              'period' => 1,
9972 
              'type' => 'logic',
9973 
              'valid_bit_used' => 0,
9974 
            },
9975 
            'direction' => 'out',
9976 
            'hdlType' => 'std_logic',
9977 
            'width' => 1,
9978 
          },
9979 
          'to_register20_data_in' => {
9980 
            'attributes' => {
9981 
              'bin_pt' => 0,
9982 
              'is_floating_block' => 1,
9983 
              'must_be_hdl_vector' => 1,
9984 
              'period' => 1,
9985 
              'port_id' => 0,
9986 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
9987 
              'type' => 'UFix_32_0',
9988 
            },
9989 
            'direction' => 'out',
9990 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9991 
            'width' => 32,
9992 
          },
9993 
          'to_register20_dout' => {
9994 
            'attributes' => {
9995 
              'bin_pt' => 0,
9996 
              'is_floating_block' => 1,
9997 
              'must_be_hdl_vector' => 1,
9998 
              'period' => 1,
9999 
              'port_id' => 0,
10000 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
10001 
              'type' => 'UFix_32_0',
10002 
            },
10003 
            'direction' => 'in',
10004 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10005 
            'width' => 32,
10006 
          },
10007 
          'to_register20_en' => {
10008 
            'attributes' => {
10009 
              'bin_pt' => 0,
10010 
              'is_floating_block' => 1,
10011 
              'must_be_hdl_vector' => 1,
10012 
              'period' => 1,
10013 
              'port_id' => 1,
10014 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
10015 
              'type' => 'Bool',
10016 
            },
10017 
            'direction' => 'out',
10018 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10019 
            'width' => 1,
10020 
          },
10021 
          'to_register21_ce' => {
10022 
            'attributes' => {
10023 
              'domain' => '',
10024 
              'group' => 1,
10025 
              'isCe' => 1,
10026 
              'is_floating_block' => 1,
10027 
              'period' => 1,
10028 
              'type' => 'logic',
10029 
            },
10030 
            'direction' => 'out',
10031 
            'hdlType' => 'std_logic',
10032 
            'width' => 1,
10033 
          },
10034 
          'to_register21_clk' => {
10035 
            'attributes' => {
10036 
              'domain' => '',
10037 
              'group' => 1,
10038 
              'isClk' => 1,
10039 
              'is_floating_block' => 1,
10040 
              'period' => 1,
10041 
              'type' => 'logic',
10042 
            },
10043 
            'direction' => 'out',
10044 
            'hdlType' => 'std_logic',
10045 
            'width' => 1,
10046 
          },
10047 
          'to_register21_clr' => {
10048 
            'attributes' => {
10049 
              'domain' => '',
10050 
              'group' => 1,
10051 
              'isClr' => 1,
10052 
              'is_floating_block' => 1,
10053 
              'period' => 1,
10054 
              'type' => 'logic',
10055 
              'valid_bit_used' => 0,
10056 
            },
10057 
            'direction' => 'out',
10058 
            'hdlType' => 'std_logic',
10059 
            'width' => 1,
10060 
          },
10061 
          'to_register21_data_in' => {
10062 
            'attributes' => {
10063 
              'bin_pt' => 0,
10064 
              'is_floating_block' => 1,
10065 
              'must_be_hdl_vector' => 1,
10066 
              'period' => 1,
10067 
              'port_id' => 0,
10068 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
10069 
              'type' => 'Bool',
10070 
            },
10071 
            'direction' => 'out',
10072 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10073 
            'width' => 1,
10074 
          },
10075 
          'to_register21_dout' => {
10076 
            'attributes' => {
10077 
              'bin_pt' => 0,
10078 
              'is_floating_block' => 1,
10079 
              'must_be_hdl_vector' => 1,
10080 
              'period' => 1,
10081 
              'port_id' => 0,
10082 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
10083 
              'type' => 'Bool',
10084 
            },
10085 
            'direction' => 'in',
10086 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10087 
            'width' => 1,
10088 
          },
10089 
          'to_register21_en' => {
10090 
            'attributes' => {
10091 
              'bin_pt' => 0,
10092 
              'is_floating_block' => 1,
10093 
              'must_be_hdl_vector' => 1,
10094 
              'period' => 1,
10095 
              'port_id' => 1,
10096 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
10097 
              'type' => 'Bool',
10098 
            },
10099 
            'direction' => 'out',
10100 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10101 
            'width' => 1,
10102 
          },
10103 
          'to_register22_ce' => {
10104 
            'attributes' => {
10105 
              'domain' => '',
10106 
              'group' => 1,
10107 
              'isCe' => 1,
10108 
              'is_floating_block' => 1,
10109 
              'period' => 1,
10110 
              'type' => 'logic',
10111 
            },
10112 
            'direction' => 'out',
10113 
            'hdlType' => 'std_logic',
10114 
            'width' => 1,
10115 
          },
10116 
          'to_register22_clk' => {
10117 
            'attributes' => {
10118 
              'domain' => '',
10119 
              'group' => 1,
10120 
              'isClk' => 1,
10121 
              'is_floating_block' => 1,
10122 
              'period' => 1,
10123 
              'type' => 'logic',
10124 
            },
10125 
            'direction' => 'out',
10126 
            'hdlType' => 'std_logic',
10127 
            'width' => 1,
10128 
          },
10129 
          'to_register22_clr' => {
10130 
            'attributes' => {
10131 
              'domain' => '',
10132 
              'group' => 1,
10133 
              'isClr' => 1,
10134 
              'is_floating_block' => 1,
10135 
              'period' => 1,
10136 
              'type' => 'logic',
10137 
              'valid_bit_used' => 0,
10138 
            },
10139 
            'direction' => 'out',
10140 
            'hdlType' => 'std_logic',
10141 
            'width' => 1,
10142 
          },
10143 
          'to_register22_data_in' => {
10144 
            'attributes' => {
10145 
              'bin_pt' => 0,
10146 
              'is_floating_block' => 1,
10147 
              'must_be_hdl_vector' => 1,
10148 
              'period' => 1,
10149 
              'port_id' => 0,
10150 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
10151 
              'type' => 'UFix_32_0',
10152 
            },
10153 
            'direction' => 'out',
10154 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10155 
            'width' => 32,
10156 
          },
10157 
          'to_register22_dout' => {
10158 
            'attributes' => {
10159 
              'bin_pt' => 0,
10160 
              'is_floating_block' => 1,
10161 
              'must_be_hdl_vector' => 1,
10162 
              'period' => 1,
10163 
              'port_id' => 0,
10164 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
10165 
              'type' => 'UFix_32_0',
10166 
            },
10167 
            'direction' => 'in',
10168 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10169 
            'width' => 32,
10170 
          },
10171 
          'to_register22_en' => {
10172 
            'attributes' => {
10173 
              'bin_pt' => 0,
10174 
              'is_floating_block' => 1,
10175 
              'must_be_hdl_vector' => 1,
10176 
              'period' => 1,
10177 
              'port_id' => 1,
10178 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
10179 
              'type' => 'Bool',
10180 
            },
10181 
            'direction' => 'out',
10182 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10183 
            'width' => 1,
10184 
          },
10185 
          'to_register23_ce' => {
10186 
            'attributes' => {
10187 
              'domain' => '',
10188 
              'group' => 1,
10189 
              'isCe' => 1,
10190 
              'is_floating_block' => 1,
10191 
              'period' => 1,
10192 
              'type' => 'logic',
10193 
            },
10194 
            'direction' => 'out',
10195 
            'hdlType' => 'std_logic',
10196 
            'width' => 1,
10197 
          },
10198 
          'to_register23_clk' => {
10199 
            'attributes' => {
10200 
              'domain' => '',
10201 
              'group' => 1,
10202 
              'isClk' => 1,
10203 
              'is_floating_block' => 1,
10204 
              'period' => 1,
10205 
              'type' => 'logic',
10206 
            },
10207 
            'direction' => 'out',
10208 
            'hdlType' => 'std_logic',
10209 
            'width' => 1,
10210 
          },
10211 
          'to_register23_clr' => {
10212 
            'attributes' => {
10213 
              'domain' => '',
10214 
              'group' => 1,
10215 
              'isClr' => 1,
10216 
              'is_floating_block' => 1,
10217 
              'period' => 1,
10218 
              'type' => 'logic',
10219 
              'valid_bit_used' => 0,
10220 
            },
10221 
            'direction' => 'out',
10222 
            'hdlType' => 'std_logic',
10223 
            'width' => 1,
10224 
          },
10225 
          'to_register23_data_in' => {
10226 
            'attributes' => {
10227 
              'bin_pt' => 0,
10228 
              'is_floating_block' => 1,
10229 
              'must_be_hdl_vector' => 1,
10230 
              'period' => 1,
10231 
              'port_id' => 0,
10232 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
10233 
              'type' => 'Bool',
10234 
            },
10235 
            'direction' => 'out',
10236 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10237 
            'width' => 1,
10238 
          },
10239 
          'to_register23_dout' => {
10240 
            'attributes' => {
10241 
              'bin_pt' => 0,
10242 
              'is_floating_block' => 1,
10243 
              'must_be_hdl_vector' => 1,
10244 
              'period' => 1,
10245 
              'port_id' => 0,
10246 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
10247 
              'type' => 'Bool',
10248 
            },
10249 
            'direction' => 'in',
10250 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10251 
            'width' => 1,
10252 
          },
10253 
          'to_register23_en' => {
10254 
            'attributes' => {
10255 
              'bin_pt' => 0,
10256 
              'is_floating_block' => 1,
10257 
              'must_be_hdl_vector' => 1,
10258 
              'period' => 1,
10259 
              'port_id' => 1,
10260 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
10261 
              'type' => 'Bool',
10262 
            },
10263 
            'direction' => 'out',
10264 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10265 
            'width' => 1,
10266 
          },
10267 
          'to_register24_ce' => {
10268 
            'attributes' => {
10269 
              'domain' => '',
10270 
              'group' => 1,
10271 
              'isCe' => 1,
10272 
              'is_floating_block' => 1,
10273 
              'period' => 1,
10274 
              'type' => 'logic',
10275 
            },
10276 
            'direction' => 'out',
10277 
            'hdlType' => 'std_logic',
10278 
            'width' => 1,
10279 
          },
10280 
          'to_register24_clk' => {
10281 
            'attributes' => {
10282 
              'domain' => '',
10283 
              'group' => 1,
10284 
              'isClk' => 1,
10285 
              'is_floating_block' => 1,
10286 
              'period' => 1,
10287 
              'type' => 'logic',
10288 
            },
10289 
            'direction' => 'out',
10290 
            'hdlType' => 'std_logic',
10291 
            'width' => 1,
10292 
          },
10293 
          'to_register24_clr' => {
10294 
            'attributes' => {
10295 
              'domain' => '',
10296 
              'group' => 1,
10297 
              'isClr' => 1,
10298 
              'is_floating_block' => 1,
10299 
              'period' => 1,
10300 
              'type' => 'logic',
10301 
              'valid_bit_used' => 0,
10302 
            },
10303 
            'direction' => 'out',
10304 
            'hdlType' => 'std_logic',
10305 
            'width' => 1,
10306 
          },
10307 
          'to_register24_data_in' => {
10308 
            'attributes' => {
10309 
              'bin_pt' => 0,
10310 
              'is_floating_block' => 1,
10311 
              'must_be_hdl_vector' => 1,
10312 
              'period' => 1,
10313 
              'port_id' => 0,
10314 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
10315 
              'type' => 'UFix_32_0',
10316 
            },
10317 
            'direction' => 'out',
10318 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10319 
            'width' => 32,
10320 
          },
10321 
          'to_register24_dout' => {
10322 
            'attributes' => {
10323 
              'bin_pt' => 0,
10324 
              'is_floating_block' => 1,
10325 
              'must_be_hdl_vector' => 1,
10326 
              'period' => 1,
10327 
              'port_id' => 0,
10328 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
10329 
              'type' => 'UFix_32_0',
10330 
            },
10331 
            'direction' => 'in',
10332 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10333 
            'width' => 32,
10334 
          },
10335 
          'to_register24_en' => {
10336 
            'attributes' => {
10337 
              'bin_pt' => 0,
10338 
              'is_floating_block' => 1,
10339 
              'must_be_hdl_vector' => 1,
10340 
              'period' => 1,
10341 
              'port_id' => 1,
10342 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
10343 
              'type' => 'Bool',
10344 
            },
10345 
            'direction' => 'out',
10346 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10347 
            'width' => 1,
10348 
          },
10349 
          'to_register25_ce' => {
10350 
            'attributes' => {
10351 
              'domain' => '',
10352 
              'group' => 1,
10353 
              'isCe' => 1,
10354 
              'is_floating_block' => 1,
10355 
              'period' => 1,
10356 
              'type' => 'logic',
10357 
            },
10358 
            'direction' => 'out',
10359 
            'hdlType' => 'std_logic',
10360 
            'width' => 1,
10361 
          },
10362 
          'to_register25_clk' => {
10363 
            'attributes' => {
10364 
              'domain' => '',
10365 
              'group' => 1,
10366 
              'isClk' => 1,
10367 
              'is_floating_block' => 1,
10368 
              'period' => 1,
10369 
              'type' => 'logic',
10370 
            },
10371 
            'direction' => 'out',
10372 
            'hdlType' => 'std_logic',
10373 
            'width' => 1,
10374 
          },
10375 
          'to_register25_clr' => {
10376 
            'attributes' => {
10377 
              'domain' => '',
10378 
              'group' => 1,
10379 
              'isClr' => 1,
10380 
              'is_floating_block' => 1,
10381 
              'period' => 1,
10382 
              'type' => 'logic',
10383 
              'valid_bit_used' => 0,
10384 
            },
10385 
            'direction' => 'out',
10386 
            'hdlType' => 'std_logic',
10387 
            'width' => 1,
10388 
          },
10389 
          'to_register25_data_in' => {
10390 
            'attributes' => {
10391 
              'bin_pt' => 0,
10392 
              'is_floating_block' => 1,
10393 
              'must_be_hdl_vector' => 1,
10394 
              'period' => 1,
10395 
              'port_id' => 0,
10396 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
10397 
              'type' => 'Bool',
10398 
            },
10399 
            'direction' => 'out',
10400 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10401 
            'width' => 1,
10402 
          },
10403 
          'to_register25_dout' => {
10404 
            'attributes' => {
10405 
              'bin_pt' => 0,
10406 
              'is_floating_block' => 1,
10407 
              'must_be_hdl_vector' => 1,
10408 
              'period' => 1,
10409 
              'port_id' => 0,
10410 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
10411 
              'type' => 'Bool',
10412 
            },
10413 
            'direction' => 'in',
10414 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10415 
            'width' => 1,
10416 
          },
10417 
          'to_register25_en' => {
10418 
            'attributes' => {
10419 
              'bin_pt' => 0,
10420 
              'is_floating_block' => 1,
10421 
              'must_be_hdl_vector' => 1,
10422 
              'period' => 1,
10423 
              'port_id' => 1,
10424 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
10425 
              'type' => 'Bool',
10426 
            },
10427 
            'direction' => 'out',
10428 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10429 
            'width' => 1,
10430 
          },
10431 
          'to_register26_ce' => {
10432 
            'attributes' => {
10433 
              'domain' => '',
10434 
              'group' => 1,
10435 
              'isCe' => 1,
10436 
              'is_floating_block' => 1,
10437 
              'period' => 1,
10438 
              'type' => 'logic',
10439 
            },
10440 
            'direction' => 'out',
10441 
            'hdlType' => 'std_logic',
10442 
            'width' => 1,
10443 
          },
10444 
          'to_register26_clk' => {
10445 
            'attributes' => {
10446 
              'domain' => '',
10447 
              'group' => 1,
10448 
              'isClk' => 1,
10449 
              'is_floating_block' => 1,
10450 
              'period' => 1,
10451 
              'type' => 'logic',
10452 
            },
10453 
            'direction' => 'out',
10454 
            'hdlType' => 'std_logic',
10455 
            'width' => 1,
10456 
          },
10457 
          'to_register26_clr' => {
10458 
            'attributes' => {
10459 
              'domain' => '',
10460 
              'group' => 1,
10461 
              'isClr' => 1,
10462 
              'is_floating_block' => 1,
10463 
              'period' => 1,
10464 
              'type' => 'logic',
10465 
              'valid_bit_used' => 0,
10466 
            },
10467 
            'direction' => 'out',
10468 
            'hdlType' => 'std_logic',
10469 
            'width' => 1,
10470 
          },
10471 
          'to_register26_data_in' => {
10472 
            'attributes' => {
10473 
              'bin_pt' => 0,
10474 
              'is_floating_block' => 1,
10475 
              'must_be_hdl_vector' => 1,
10476 
              'period' => 1,
10477 
              'port_id' => 0,
10478 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
10479 
              'type' => 'UFix_32_0',
10480 
            },
10481 
            'direction' => 'out',
10482 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10483 
            'width' => 32,
10484 
          },
10485 
          'to_register26_dout' => {
10486 
            'attributes' => {
10487 
              'bin_pt' => 0,
10488 
              'is_floating_block' => 1,
10489 
              'must_be_hdl_vector' => 1,
10490 
              'period' => 1,
10491 
              'port_id' => 0,
10492 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
10493 
              'type' => 'UFix_32_0',
10494 
            },
10495 
            'direction' => 'in',
10496 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10497 
            'width' => 32,
10498 
          },
10499 
          'to_register26_en' => {
10500 
            'attributes' => {
10501 
              'bin_pt' => 0,
10502 
              'is_floating_block' => 1,
10503 
              'must_be_hdl_vector' => 1,
10504 
              'period' => 1,
10505 
              'port_id' => 1,
10506 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
10507 
              'type' => 'Bool',
10508 
            },
10509 
            'direction' => 'out',
10510 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10511 
            'width' => 1,
10512 
          },
10513 
          'to_register27_ce' => {
10514 
            'attributes' => {
10515 
              'domain' => '',
10516 
              'group' => 1,
10517 
              'isCe' => 1,
10518 
              'is_floating_block' => 1,
10519 
              'period' => 1,
10520 
              'type' => 'logic',
10521 
            },
10522 
            'direction' => 'out',
10523 
            'hdlType' => 'std_logic',
10524 
            'width' => 1,
10525 
          },
10526 
          'to_register27_clk' => {
10527 
            'attributes' => {
10528 
              'domain' => '',
10529 
              'group' => 1,
10530 
              'isClk' => 1,
10531 
              'is_floating_block' => 1,
10532 
              'period' => 1,
10533 
              'type' => 'logic',
10534 
            },
10535 
            'direction' => 'out',
10536 
            'hdlType' => 'std_logic',
10537 
            'width' => 1,
10538 
          },
10539 
          'to_register27_clr' => {
10540 
            'attributes' => {
10541 
              'domain' => '',
10542 
              'group' => 1,
10543 
              'isClr' => 1,
10544 
              'is_floating_block' => 1,
10545 
              'period' => 1,
10546 
              'type' => 'logic',
10547 
              'valid_bit_used' => 0,
10548 
            },
10549 
            'direction' => 'out',
10550 
            'hdlType' => 'std_logic',
10551 
            'width' => 1,
10552 
          },
10553 
          'to_register27_data_in' => {
10554 
            'attributes' => {
10555 
              'bin_pt' => 0,
10556 
              'is_floating_block' => 1,
10557 
              'must_be_hdl_vector' => 1,
10558 
              'period' => 1,
10559 
              'port_id' => 0,
10560 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
10561 
              'type' => 'Bool',
10562 
            },
10563 
            'direction' => 'out',
10564 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10565 
            'width' => 1,
10566 
          },
10567 
          'to_register27_dout' => {
10568 
            'attributes' => {
10569 
              'bin_pt' => 0,
10570 
              'is_floating_block' => 1,
10571 
              'must_be_hdl_vector' => 1,
10572 
              'period' => 1,
10573 
              'port_id' => 0,
10574 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
10575 
              'type' => 'Bool',
10576 
            },
10577 
            'direction' => 'in',
10578 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10579 
            'width' => 1,
10580 
          },
10581 
          'to_register27_en' => {
10582 
            'attributes' => {
10583 
              'bin_pt' => 0,
10584 
              'is_floating_block' => 1,
10585 
              'must_be_hdl_vector' => 1,
10586 
              'period' => 1,
10587 
              'port_id' => 1,
10588 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
10589 
              'type' => 'Bool',
10590 
            },
10591 
            'direction' => 'out',
10592 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10593 
            'width' => 1,
10594 
          },
10595 
          'to_register28_ce' => {
10596 
            'attributes' => {
10597 
              'domain' => '',
10598 
              'group' => 1,
10599 
              'isCe' => 1,
10600 
              'is_floating_block' => 1,
10601 
              'period' => 1,
10602 
              'type' => 'logic',
10603 
            },
10604 
            'direction' => 'out',
10605 
            'hdlType' => 'std_logic',
10606 
            'width' => 1,
10607 
          },
10608 
          'to_register28_clk' => {
10609 
            'attributes' => {
10610 
              'domain' => '',
10611 
              'group' => 1,
10612 
              'isClk' => 1,
10613 
              'is_floating_block' => 1,
10614 
              'period' => 1,
10615 
              'type' => 'logic',
10616 
            },
10617 
            'direction' => 'out',
10618 
            'hdlType' => 'std_logic',
10619 
            'width' => 1,
10620 
          },
10621 
          'to_register28_clr' => {
10622 
            'attributes' => {
10623 
              'domain' => '',
10624 
              'group' => 1,
10625 
              'isClr' => 1,
10626 
              'is_floating_block' => 1,
10627 
              'period' => 1,
10628 
              'type' => 'logic',
10629 
              'valid_bit_used' => 0,
10630 
            },
10631 
            'direction' => 'out',
10632 
            'hdlType' => 'std_logic',
10633 
            'width' => 1,
10634 
          },
10635 
          'to_register28_data_in' => {
10636 
            'attributes' => {
10637 
              'bin_pt' => 0,
10638 
              'is_floating_block' => 1,
10639 
              'must_be_hdl_vector' => 1,
10640 
              'period' => 1,
10641 
              'port_id' => 0,
10642 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
10643 
              'type' => 'UFix_32_0',
10644 
            },
10645 
            'direction' => 'out',
10646 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10647 
            'width' => 32,
10648 
          },
10649 
          'to_register28_dout' => {
10650 
            'attributes' => {
10651 
              'bin_pt' => 0,
10652 
              'is_floating_block' => 1,
10653 
              'must_be_hdl_vector' => 1,
10654 
              'period' => 1,
10655 
              'port_id' => 0,
10656 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
10657 
              'type' => 'UFix_32_0',
10658 
            },
10659 
            'direction' => 'in',
10660 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10661 
            'width' => 32,
10662 
          },
10663 
          'to_register28_en' => {
10664 
            'attributes' => {
10665 
              'bin_pt' => 0,
10666 
              'is_floating_block' => 1,
10667 
              'must_be_hdl_vector' => 1,
10668 
              'period' => 1,
10669 
              'port_id' => 1,
10670 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
10671 
              'type' => 'Bool',
10672 
            },
10673 
            'direction' => 'out',
10674 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10675 
            'width' => 1,
10676 
          },
10677 
          'to_register29_ce' => {
10678 
            'attributes' => {
10679 
              'domain' => '',
10680 
              'group' => 1,
10681 
              'isCe' => 1,
10682 
              'is_floating_block' => 1,
10683 
              'period' => 1,
10684 
              'type' => 'logic',
10685 
            },
10686 
            'direction' => 'out',
10687 
            'hdlType' => 'std_logic',
10688 
            'width' => 1,
10689 
          },
10690 
          'to_register29_clk' => {
10691 
            'attributes' => {
10692 
              'domain' => '',
10693 
              'group' => 1,
10694 
              'isClk' => 1,
10695 
              'is_floating_block' => 1,
10696 
              'period' => 1,
10697 
              'type' => 'logic',
10698 
            },
10699 
            'direction' => 'out',
10700 
            'hdlType' => 'std_logic',
10701 
            'width' => 1,
10702 
          },
10703 
          'to_register29_clr' => {
10704 
            'attributes' => {
10705 
              'domain' => '',
10706 
              'group' => 1,
10707 
              'isClr' => 1,
10708 
              'is_floating_block' => 1,
10709 
              'period' => 1,
10710 
              'type' => 'logic',
10711 
              'valid_bit_used' => 0,
10712 
            },
10713 
            'direction' => 'out',
10714 
            'hdlType' => 'std_logic',
10715 
            'width' => 1,
10716 
          },
10717 
          'to_register29_data_in' => {
10718 
            'attributes' => {
10719 
              'bin_pt' => 0,
10720 
              'is_floating_block' => 1,
10721 
              'must_be_hdl_vector' => 1,
10722 
              'period' => 1,
10723 
              'port_id' => 0,
10724 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
10725 
              'type' => 'Bool',
10726 
            },
10727 
            'direction' => 'out',
10728 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10729 
            'width' => 1,
10730 
          },
10731 
          'to_register29_dout' => {
10732 
            'attributes' => {
10733 
              'bin_pt' => 0,
10734 
              'is_floating_block' => 1,
10735 
              'must_be_hdl_vector' => 1,
10736 
              'period' => 1,
10737 
              'port_id' => 0,
10738 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
10739 
              'type' => 'Bool',
10740 
            },
10741 
            'direction' => 'in',
10742 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10743 
            'width' => 1,
10744 
          },
10745 
          'to_register29_en' => {
10746 
            'attributes' => {
10747 
              'bin_pt' => 0,
10748 
              'is_floating_block' => 1,
10749 
              'must_be_hdl_vector' => 1,
10750 
              'period' => 1,
10751 
              'port_id' => 1,
10752 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
10753 
              'type' => 'Bool',
10754 
            },
10755 
            'direction' => 'out',
10756 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10757 
            'width' => 1,
10758 
          },
10759 
          'to_register2_ce' => {
10760 
            'attributes' => {
10761 
              'domain' => '',
10762 
              'group' => 1,
10763 
              'isCe' => 1,
10764 
              'is_floating_block' => 1,
10765 
              'period' => 1,
10766 
              'type' => 'logic',
10767 
            },
10768 
            'direction' => 'out',
10769 
            'hdlType' => 'std_logic',
10770 
            'width' => 1,
10771 
          },
10772 
          'to_register2_clk' => {
10773 
            'attributes' => {
10774 
              'domain' => '',
10775 
              'group' => 1,
10776 
              'isClk' => 1,
10777 
              'is_floating_block' => 1,
10778 
              'period' => 1,
10779 
              'type' => 'logic',
10780 
            },
10781 
            'direction' => 'out',
10782 
            'hdlType' => 'std_logic',
10783 
            'width' => 1,
10784 
          },
10785 
          'to_register2_clr' => {
10786 
            'attributes' => {
10787 
              'domain' => '',
10788 
              'group' => 1,
10789 
              'isClr' => 1,
10790 
              'is_floating_block' => 1,
10791 
              'period' => 1,
10792 
              'type' => 'logic',
10793 
              'valid_bit_used' => 0,
10794 
            },
10795 
            'direction' => 'out',
10796 
            'hdlType' => 'std_logic',
10797 
            'width' => 1,
10798 
          },
10799 
          'to_register2_data_in' => {
10800 
            'attributes' => {
10801 
              'bin_pt' => 0,
10802 
              'is_floating_block' => 1,
10803 
              'must_be_hdl_vector' => 1,
10804 
              'period' => 1,
10805 
              'port_id' => 0,
10806 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
10807 
              'type' => 'UFix_32_0',
10808 
            },
10809 
            'direction' => 'out',
10810 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10811 
            'width' => 32,
10812 
          },
10813 
          'to_register2_dout' => {
10814 
            'attributes' => {
10815 
              'bin_pt' => 0,
10816 
              'is_floating_block' => 1,
10817 
              'must_be_hdl_vector' => 1,
10818 
              'period' => 1,
10819 
              'port_id' => 0,
10820 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
10821 
              'type' => 'UFix_32_0',
10822 
            },
10823 
            'direction' => 'in',
10824 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10825 
            'width' => 32,
10826 
          },
10827 
          'to_register2_en' => {
10828 
            'attributes' => {
10829 
              'bin_pt' => 0,
10830 
              'is_floating_block' => 1,
10831 
              'must_be_hdl_vector' => 1,
10832 
              'period' => 1,
10833 
              'port_id' => 1,
10834 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
10835 
              'type' => 'Bool',
10836 
            },
10837 
            'direction' => 'out',
10838 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10839 
            'width' => 1,
10840 
          },
10841 
          'to_register30_ce' => {
10842 
            'attributes' => {
10843 
              'domain' => '',
10844 
              'group' => 1,
10845 
              'isCe' => 1,
10846 
              'is_floating_block' => 1,
10847 
              'period' => 1,
10848 
              'type' => 'logic',
10849 
            },
10850 
            'direction' => 'out',
10851 
            'hdlType' => 'std_logic',
10852 
            'width' => 1,
10853 
          },
10854 
          'to_register30_clk' => {
10855 
            'attributes' => {
10856 
              'domain' => '',
10857 
              'group' => 1,
10858 
              'isClk' => 1,
10859 
              'is_floating_block' => 1,
10860 
              'period' => 1,
10861 
              'type' => 'logic',
10862 
            },
10863 
            'direction' => 'out',
10864 
            'hdlType' => 'std_logic',
10865 
            'width' => 1,
10866 
          },
10867 
          'to_register30_clr' => {
10868 
            'attributes' => {
10869 
              'domain' => '',
10870 
              'group' => 1,
10871 
              'isClr' => 1,
10872 
              'is_floating_block' => 1,
10873 
              'period' => 1,
10874 
              'type' => 'logic',
10875 
              'valid_bit_used' => 0,
10876 
            },
10877 
            'direction' => 'out',
10878 
            'hdlType' => 'std_logic',
10879 
            'width' => 1,
10880 
          },
10881 
          'to_register30_data_in' => {
10882 
            'attributes' => {
10883 
              'bin_pt' => 0,
10884 
              'is_floating_block' => 1,
10885 
              'must_be_hdl_vector' => 1,
10886 
              'period' => 1,
10887 
              'port_id' => 0,
10888 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
10889 
              'type' => 'UFix_32_0',
10890 
            },
10891 
            'direction' => 'out',
10892 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10893 
            'width' => 32,
10894 
          },
10895 
          'to_register30_dout' => {
10896 
            'attributes' => {
10897 
              'bin_pt' => 0,
10898 
              'is_floating_block' => 1,
10899 
              'must_be_hdl_vector' => 1,
10900 
              'period' => 1,
10901 
              'port_id' => 0,
10902 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
10903 
              'type' => 'UFix_32_0',
10904 
            },
10905 
            'direction' => 'in',
10906 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10907 
            'width' => 32,
10908 
          },
10909 
          'to_register30_en' => {
10910 
            'attributes' => {
10911 
              'bin_pt' => 0,
10912 
              'is_floating_block' => 1,
10913 
              'must_be_hdl_vector' => 1,
10914 
              'period' => 1,
10915 
              'port_id' => 1,
10916 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
10917 
              'type' => 'Bool',
10918 
            },
10919 
            'direction' => 'out',
10920 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10921 
            'width' => 1,
10922 
          },
10923 
          'to_register31_ce' => {
10924 
            'attributes' => {
10925 
              'domain' => '',
10926 
              'group' => 1,
10927 
              'isCe' => 1,
10928 
              'is_floating_block' => 1,
10929 
              'period' => 1,
10930 
              'type' => 'logic',
10931 
            },
10932 
            'direction' => 'out',
10933 
            'hdlType' => 'std_logic',
10934 
            'width' => 1,
10935 
          },
10936 
          'to_register31_clk' => {
10937 
            'attributes' => {
10938 
              'domain' => '',
10939 
              'group' => 1,
10940 
              'isClk' => 1,
10941 
              'is_floating_block' => 1,
10942 
              'period' => 1,
10943 
              'type' => 'logic',
10944 
            },
10945 
            'direction' => 'out',
10946 
            'hdlType' => 'std_logic',
10947 
            'width' => 1,
10948 
          },
10949 
          'to_register31_clr' => {
10950 
            'attributes' => {
10951 
              'domain' => '',
10952 
              'group' => 1,
10953 
              'isClr' => 1,
10954 
              'is_floating_block' => 1,
10955 
              'period' => 1,
10956 
              'type' => 'logic',
10957 
              'valid_bit_used' => 0,
10958 
            },
10959 
            'direction' => 'out',
10960 
            'hdlType' => 'std_logic',
10961 
            'width' => 1,
10962 
          },
10963 
          'to_register31_data_in' => {
10964 
            'attributes' => {
10965 
              'bin_pt' => 0,
10966 
              'is_floating_block' => 1,
10967 
              'must_be_hdl_vector' => 1,
10968 
              'period' => 1,
10969 
              'port_id' => 0,
10970 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
10971 
              'type' => 'Bool',
10972 
            },
10973 
            'direction' => 'out',
10974 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10975 
            'width' => 1,
10976 
          },
10977 
          'to_register31_dout' => {
10978 
            'attributes' => {
10979 
              'bin_pt' => 0,
10980 
              'is_floating_block' => 1,
10981 
              'must_be_hdl_vector' => 1,
10982 
              'period' => 1,
10983 
              'port_id' => 0,
10984 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
10985 
              'type' => 'Bool',
10986 
            },
10987 
            'direction' => 'in',
10988 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10989 
            'width' => 1,
10990 
          },
10991 
          'to_register31_en' => {
10992 
            'attributes' => {
10993 
              'bin_pt' => 0,
10994 
              'is_floating_block' => 1,
10995 
              'must_be_hdl_vector' => 1,
10996 
              'period' => 1,
10997 
              'port_id' => 1,
10998 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
10999 
              'type' => 'Bool',
11000 
            },
11001 
            'direction' => 'out',
11002 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11003 
            'width' => 1,
11004 
          },
11005 
          'to_register32_ce' => {
11006 
            'attributes' => {
11007 
              'domain' => '',
11008 
              'group' => 1,
11009 
              'isCe' => 1,
11010 
              'is_floating_block' => 1,
11011 
              'period' => 1,
11012 
              'type' => 'logic',
11013 
            },
11014 
            'direction' => 'out',
11015 
            'hdlType' => 'std_logic',
11016 
            'width' => 1,
11017 
          },
11018 
          'to_register32_clk' => {
11019 
            'attributes' => {
11020 
              'domain' => '',
11021 
              'group' => 1,
11022 
              'isClk' => 1,
11023 
              'is_floating_block' => 1,
11024 
              'period' => 1,
11025 
              'type' => 'logic',
11026 
            },
11027 
            'direction' => 'out',
11028 
            'hdlType' => 'std_logic',
11029 
            'width' => 1,
11030 
          },
11031 
          'to_register32_clr' => {
11032 
            'attributes' => {
11033 
              'domain' => '',
11034 
              'group' => 1,
11035 
              'isClr' => 1,
11036 
              'is_floating_block' => 1,
11037 
              'period' => 1,
11038 
              'type' => 'logic',
11039 
              'valid_bit_used' => 0,
11040 
            },
11041 
            'direction' => 'out',
11042 
            'hdlType' => 'std_logic',
11043 
            'width' => 1,
11044 
          },
11045 
          'to_register32_data_in' => {
11046 
            'attributes' => {
11047 
              'bin_pt' => 0,
11048 
              'is_floating_block' => 1,
11049 
              'must_be_hdl_vector' => 1,
11050 
              'period' => 1,
11051 
              'port_id' => 0,
11052 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
11053 
              'type' => 'UFix_32_0',
11054 
            },
11055 
            'direction' => 'out',
11056 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11057 
            'width' => 32,
11058 
          },
11059 
          'to_register32_dout' => {
11060 
            'attributes' => {
11061 
              'bin_pt' => 0,
11062 
              'is_floating_block' => 1,
11063 
              'must_be_hdl_vector' => 1,
11064 
              'period' => 1,
11065 
              'port_id' => 0,
11066 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
11067 
              'type' => 'UFix_32_0',
11068 
            },
11069 
            'direction' => 'in',
11070 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11071 
            'width' => 32,
11072 
          },
11073 
          'to_register32_en' => {
11074 
            'attributes' => {
11075 
              'bin_pt' => 0,
11076 
              'is_floating_block' => 1,
11077 
              'must_be_hdl_vector' => 1,
11078 
              'period' => 1,
11079 
              'port_id' => 1,
11080 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
11081 
              'type' => 'Bool',
11082 
            },
11083 
            'direction' => 'out',
11084 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11085 
            'width' => 1,
11086 
          },
11087 
          'to_register33_ce' => {
11088 
            'attributes' => {
11089 
              'domain' => '',
11090 
              'group' => 1,
11091 
              'isCe' => 1,
11092 
              'is_floating_block' => 1,
11093 
              'period' => 1,
11094 
              'type' => 'logic',
11095 
            },
11096 
            'direction' => 'out',
11097 
            'hdlType' => 'std_logic',
11098 
            'width' => 1,
11099 
          },
11100 
          'to_register33_clk' => {
11101 
            'attributes' => {
11102 
              'domain' => '',
11103 
              'group' => 1,
11104 
              'isClk' => 1,
11105 
              'is_floating_block' => 1,
11106 
              'period' => 1,
11107 
              'type' => 'logic',
11108 
            },
11109 
            'direction' => 'out',
11110 
            'hdlType' => 'std_logic',
11111 
            'width' => 1,
11112 
          },
11113 
          'to_register33_clr' => {
11114 
            'attributes' => {
11115 
              'domain' => '',
11116 
              'group' => 1,
11117 
              'isClr' => 1,
11118 
              'is_floating_block' => 1,
11119 
              'period' => 1,
11120 
              'type' => 'logic',
11121 
              'valid_bit_used' => 0,
11122 
            },
11123 
            'direction' => 'out',
11124 
            'hdlType' => 'std_logic',
11125 
            'width' => 1,
11126 
          },
11127 
          'to_register33_data_in' => {
11128 
            'attributes' => {
11129 
              'bin_pt' => 0,
11130 
              'is_floating_block' => 1,
11131 
              'must_be_hdl_vector' => 1,
11132 
              'period' => 1,
11133 
              'port_id' => 0,
11134 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
11135 
              'type' => 'Bool',
11136 
            },
11137 
            'direction' => 'out',
11138 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11139 
            'width' => 1,
11140 
          },
11141 
          'to_register33_dout' => {
11142 
            'attributes' => {
11143 
              'bin_pt' => 0,
11144 
              'is_floating_block' => 1,
11145 
              'must_be_hdl_vector' => 1,
11146 
              'period' => 1,
11147 
              'port_id' => 0,
11148 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
11149 
              'type' => 'Bool',
11150 
            },
11151 
            'direction' => 'in',
11152 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11153 
            'width' => 1,
11154 
          },
11155 
          'to_register33_en' => {
11156 
            'attributes' => {
11157 
              'bin_pt' => 0,
11158 
              'is_floating_block' => 1,
11159 
              'must_be_hdl_vector' => 1,
11160 
              'period' => 1,
11161 
              'port_id' => 1,
11162 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
11163 
              'type' => 'Bool',
11164 
            },
11165 
            'direction' => 'out',
11166 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11167 
            'width' => 1,
11168 
          },
11169 
          'to_register34_ce' => {
11170 
            'attributes' => {
11171 
              'domain' => '',
11172 
              'group' => 1,
11173 
              'isCe' => 1,
11174 
              'is_floating_block' => 1,
11175 
              'period' => 1,
11176 
              'type' => 'logic',
11177 
            },
11178 
            'direction' => 'out',
11179 
            'hdlType' => 'std_logic',
11180 
            'width' => 1,
11181 
          },
11182 
          'to_register34_clk' => {
11183 
            'attributes' => {
11184 
              'domain' => '',
11185 
              'group' => 1,
11186 
              'isClk' => 1,
11187 
              'is_floating_block' => 1,
11188 
              'period' => 1,
11189 
              'type' => 'logic',
11190 
            },
11191 
            'direction' => 'out',
11192 
            'hdlType' => 'std_logic',
11193 
            'width' => 1,
11194 
          },
11195 
          'to_register34_clr' => {
11196 
            'attributes' => {
11197 
              'domain' => '',
11198 
              'group' => 1,
11199 
              'isClr' => 1,
11200 
              'is_floating_block' => 1,
11201 
              'period' => 1,
11202 
              'type' => 'logic',
11203 
              'valid_bit_used' => 0,
11204 
            },
11205 
            'direction' => 'out',
11206 
            'hdlType' => 'std_logic',
11207 
            'width' => 1,
11208 
          },
11209 
          'to_register34_data_in' => {
11210 
            'attributes' => {
11211 
              'bin_pt' => 0,
11212 
              'is_floating_block' => 1,
11213 
              'must_be_hdl_vector' => 1,
11214 
              'period' => 1,
11215 
              'port_id' => 0,
11216 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
11217 
              'type' => 'UFix_32_0',
11218 
            },
11219 
            'direction' => 'out',
11220 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11221 
            'width' => 32,
11222 
          },
11223 
          'to_register34_dout' => {
11224 
            'attributes' => {
11225 
              'bin_pt' => 0,
11226 
              'is_floating_block' => 1,
11227 
              'must_be_hdl_vector' => 1,
11228 
              'period' => 1,
11229 
              'port_id' => 0,
11230 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
11231 
              'type' => 'UFix_32_0',
11232 
            },
11233 
            'direction' => 'in',
11234 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11235 
            'width' => 32,
11236 
          },
11237 
          'to_register34_en' => {
11238 
            'attributes' => {
11239 
              'bin_pt' => 0,
11240 
              'is_floating_block' => 1,
11241 
              'must_be_hdl_vector' => 1,
11242 
              'period' => 1,
11243 
              'port_id' => 1,
11244 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
11245 
              'type' => 'Bool',
11246 
            },
11247 
            'direction' => 'out',
11248 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11249 
            'width' => 1,
11250 
          },
11251 
          'to_register3_ce' => {
11252 
            'attributes' => {
11253 
              'domain' => '',
11254 
              'group' => 1,
11255 
              'isCe' => 1,
11256 
              'is_floating_block' => 1,
11257 
              'period' => 1,
11258 
              'type' => 'logic',
11259 
            },
11260 
            'direction' => 'out',
11261 
            'hdlType' => 'std_logic',
11262 
            'width' => 1,
11263 
          },
11264 
          'to_register3_clk' => {
11265 
            'attributes' => {
11266 
              'domain' => '',
11267 
              'group' => 1,
11268 
              'isClk' => 1,
11269 
              'is_floating_block' => 1,
11270 
              'period' => 1,
11271 
              'type' => 'logic',
11272 
            },
11273 
            'direction' => 'out',
11274 
            'hdlType' => 'std_logic',
11275 
            'width' => 1,
11276 
          },
11277 
          'to_register3_clr' => {
11278 
            'attributes' => {
11279 
              'domain' => '',
11280 
              'group' => 1,
11281 
              'isClr' => 1,
11282 
              'is_floating_block' => 1,
11283 
              'period' => 1,
11284 
              'type' => 'logic',
11285 
              'valid_bit_used' => 0,
11286 
            },
11287 
            'direction' => 'out',
11288 
            'hdlType' => 'std_logic',
11289 
            'width' => 1,
11290 
          },
11291 
          'to_register3_data_in' => {
11292 
            'attributes' => {
11293 
              'bin_pt' => 0,
11294 
              'is_floating_block' => 1,
11295 
              'must_be_hdl_vector' => 1,
11296 
              'period' => 1,
11297 
              'port_id' => 0,
11298 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
11299 
              'type' => 'Bool',
11300 
            },
11301 
            'direction' => 'out',
11302 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11303 
            'width' => 1,
11304 
          },
11305 
          'to_register3_dout' => {
11306 
            'attributes' => {
11307 
              'bin_pt' => 0,
11308 
              'is_floating_block' => 1,
11309 
              'must_be_hdl_vector' => 1,
11310 
              'period' => 1,
11311 
              'port_id' => 0,
11312 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
11313 
              'type' => 'Bool',
11314 
            },
11315 
            'direction' => 'in',
11316 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11317 
            'width' => 1,
11318 
          },
11319 
          'to_register3_en' => {
11320 
            'attributes' => {
11321 
              'bin_pt' => 0,
11322 
              'is_floating_block' => 1,
11323 
              'must_be_hdl_vector' => 1,
11324 
              'period' => 1,
11325 
              'port_id' => 1,
11326 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
11327 
              'type' => 'Bool',
11328 
            },
11329 
            'direction' => 'out',
11330 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11331 
            'width' => 1,
11332 
          },
11333 
          'to_register4_ce' => {
11334 
            'attributes' => {
11335 
              'domain' => '',
11336 
              'group' => 1,
11337 
              'isCe' => 1,
11338 
              'is_floating_block' => 1,
11339 
              'period' => 1,
11340 
              'type' => 'logic',
11341 
            },
11342 
            'direction' => 'out',
11343 
            'hdlType' => 'std_logic',
11344 
            'width' => 1,
11345 
          },
11346 
          'to_register4_clk' => {
11347 
            'attributes' => {
11348 
              'domain' => '',
11349 
              'group' => 1,
11350 
              'isClk' => 1,
11351 
              'is_floating_block' => 1,
11352 
              'period' => 1,
11353 
              'type' => 'logic',
11354 
            },
11355 
            'direction' => 'out',
11356 
            'hdlType' => 'std_logic',
11357 
            'width' => 1,
11358 
          },
11359 
          'to_register4_clr' => {
11360 
            'attributes' => {
11361 
              'domain' => '',
11362 
              'group' => 1,
11363 
              'isClr' => 1,
11364 
              'is_floating_block' => 1,
11365 
              'period' => 1,
11366 
              'type' => 'logic',
11367 
              'valid_bit_used' => 0,
11368 
            },
11369 
            'direction' => 'out',
11370 
            'hdlType' => 'std_logic',
11371 
            'width' => 1,
11372 
          },
11373 
          'to_register4_data_in' => {
11374 
            'attributes' => {
11375 
              'bin_pt' => 0,
11376 
              'is_floating_block' => 1,
11377 
              'must_be_hdl_vector' => 1,
11378 
              'period' => 1,
11379 
              'port_id' => 0,
11380 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
11381 
              'type' => 'Bool',
11382 
            },
11383 
            'direction' => 'out',
11384 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11385 
            'width' => 1,
11386 
          },
11387 
          'to_register4_dout' => {
11388 
            'attributes' => {
11389 
              'bin_pt' => 0,
11390 
              'is_floating_block' => 1,
11391 
              'must_be_hdl_vector' => 1,
11392 
              'period' => 1,
11393 
              'port_id' => 0,
11394 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
11395 
              'type' => 'Bool',
11396 
            },
11397 
            'direction' => 'in',
11398 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11399 
            'width' => 1,
11400 
          },
11401 
          'to_register4_en' => {
11402 
            'attributes' => {
11403 
              'bin_pt' => 0,
11404 
              'is_floating_block' => 1,
11405 
              'must_be_hdl_vector' => 1,
11406 
              'period' => 1,
11407 
              'port_id' => 1,
11408 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
11409 
              'type' => 'Bool',
11410 
            },
11411 
            'direction' => 'out',
11412 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11413 
            'width' => 1,
11414 
          },
11415 
          'to_register5_ce' => {
11416 
            'attributes' => {
11417 
              'domain' => '',
11418 
              'group' => 1,
11419 
              'isCe' => 1,
11420 
              'is_floating_block' => 1,
11421 
              'period' => 1,
11422 
              'type' => 'logic',
11423 
            },
11424 
            'direction' => 'out',
11425 
            'hdlType' => 'std_logic',
11426 
            'width' => 1,
11427 
          },
11428 
          'to_register5_clk' => {
11429 
            'attributes' => {
11430 
              'domain' => '',
11431 
              'group' => 1,
11432 
              'isClk' => 1,
11433 
              'is_floating_block' => 1,
11434 
              'period' => 1,
11435 
              'type' => 'logic',
11436 
            },
11437 
            'direction' => 'out',
11438 
            'hdlType' => 'std_logic',
11439 
            'width' => 1,
11440 
          },
11441 
          'to_register5_clr' => {
11442 
            'attributes' => {
11443 
              'domain' => '',
11444 
              'group' => 1,
11445 
              'isClr' => 1,
11446 
              'is_floating_block' => 1,
11447 
              'period' => 1,
11448 
              'type' => 'logic',
11449 
              'valid_bit_used' => 0,
11450 
            },
11451 
            'direction' => 'out',
11452 
            'hdlType' => 'std_logic',
11453 
            'width' => 1,
11454 
          },
11455 
          'to_register5_data_in' => {
11456 
            'attributes' => {
11457 
              'bin_pt' => 0,
11458 
              'is_floating_block' => 1,
11459 
              'must_be_hdl_vector' => 1,
11460 
              'period' => 1,
11461 
              'port_id' => 0,
11462 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
11463 
              'type' => 'UFix_32_0',
11464 
            },
11465 
            'direction' => 'out',
11466 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11467 
            'width' => 32,
11468 
          },
11469 
          'to_register5_dout' => {
11470 
            'attributes' => {
11471 
              'bin_pt' => 0,
11472 
              'is_floating_block' => 1,
11473 
              'must_be_hdl_vector' => 1,
11474 
              'period' => 1,
11475 
              'port_id' => 0,
11476 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
11477 
              'type' => 'UFix_32_0',
11478 
            },
11479 
            'direction' => 'in',
11480 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11481 
            'width' => 32,
11482 
          },
11483 
          'to_register5_en' => {
11484 
            'attributes' => {
11485 
              'bin_pt' => 0,
11486 
              'is_floating_block' => 1,
11487 
              'must_be_hdl_vector' => 1,
11488 
              'period' => 1,
11489 
              'port_id' => 1,
11490 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11491 
              'type' => 'Bool',
11492 
            },
11493 
            'direction' => 'out',
11494 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11495 
            'width' => 1,
11496 
          },
11497 
          'to_register6_ce' => {
11498 
            'attributes' => {
11499 
              'domain' => '',
11500 
              'group' => 1,
11501 
              'isCe' => 1,
11502 
              'is_floating_block' => 1,
11503 
              'period' => 1,
11504 
              'type' => 'logic',
11505 
            },
11506 
            'direction' => 'out',
11507 
            'hdlType' => 'std_logic',
11508 
            'width' => 1,
11509 
          },
11510 
          'to_register6_clk' => {
11511 
            'attributes' => {
11512 
              'domain' => '',
11513 
              'group' => 1,
11514 
              'isClk' => 1,
11515 
              'is_floating_block' => 1,
11516 
              'period' => 1,
11517 
              'type' => 'logic',
11518 
            },
11519 
            'direction' => 'out',
11520 
            'hdlType' => 'std_logic',
11521 
            'width' => 1,
11522 
          },
11523 
          'to_register6_clr' => {
11524 
            'attributes' => {
11525 
              'domain' => '',
11526 
              'group' => 1,
11527 
              'isClr' => 1,
11528 
              'is_floating_block' => 1,
11529 
              'period' => 1,
11530 
              'type' => 'logic',
11531 
              'valid_bit_used' => 0,
11532 
            },
11533 
            'direction' => 'out',
11534 
            'hdlType' => 'std_logic',
11535 
            'width' => 1,
11536 
          },
11537 
          'to_register6_data_in' => {
11538 
            'attributes' => {
11539 
              'bin_pt' => 0,
11540 
              'is_floating_block' => 1,
11541 
              'must_be_hdl_vector' => 1,
11542 
              'period' => 1,
11543 
              'port_id' => 0,
11544 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
11545 
              'type' => 'UFix_32_0',
11546 
            },
11547 
            'direction' => 'out',
11548 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11549 
            'width' => 32,
11550 
          },
11551 
          'to_register6_dout' => {
11552 
            'attributes' => {
11553 
              'bin_pt' => 0,
11554 
              'is_floating_block' => 1,
11555 
              'must_be_hdl_vector' => 1,
11556 
              'period' => 1,
11557 
              'port_id' => 0,
11558 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
11559 
              'type' => 'UFix_32_0',
11560 
            },
11561 
            'direction' => 'in',
11562 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11563 
            'width' => 32,
11564 
          },
11565 
          'to_register6_en' => {
11566 
            'attributes' => {
11567 
              'bin_pt' => 0,
11568 
              'is_floating_block' => 1,
11569 
              'must_be_hdl_vector' => 1,
11570 
              'period' => 1,
11571 
              'port_id' => 1,
11572 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
11573 
              'type' => 'Bool',
11574 
            },
11575 
            'direction' => 'out',
11576 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11577 
            'width' => 1,
11578 
          },
11579 
          'to_register7_ce' => {
11580 
            'attributes' => {
11581 
              'domain' => '',
11582 
              'group' => 1,
11583 
              'isCe' => 1,
11584 
              'is_floating_block' => 1,
11585 
              'period' => 1,
11586 
              'type' => 'logic',
11587 
            },
11588 
            'direction' => 'out',
11589 
            'hdlType' => 'std_logic',
11590 
            'width' => 1,
11591 
          },
11592 
          'to_register7_clk' => {
11593 
            'attributes' => {
11594 
              'domain' => '',
11595 
              'group' => 1,
11596 
              'isClk' => 1,
11597 
              'is_floating_block' => 1,
11598 
              'period' => 1,
11599 
              'type' => 'logic',
11600 
            },
11601 
            'direction' => 'out',
11602 
            'hdlType' => 'std_logic',
11603 
            'width' => 1,
11604 
          },
11605 
          'to_register7_clr' => {
11606 
            'attributes' => {
11607 
              'domain' => '',
11608 
              'group' => 1,
11609 
              'isClr' => 1,
11610 
              'is_floating_block' => 1,
11611 
              'period' => 1,
11612 
              'type' => 'logic',
11613 
              'valid_bit_used' => 0,
11614 
            },
11615 
            'direction' => 'out',
11616 
            'hdlType' => 'std_logic',
11617 
            'width' => 1,
11618 
          },
11619 
          'to_register7_data_in' => {
11620 
            'attributes' => {
11621 
              'bin_pt' => 0,
11622 
              'is_floating_block' => 1,
11623 
              'must_be_hdl_vector' => 1,
11624 
              'period' => 1,
11625 
              'port_id' => 0,
11626 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
11627 
              'type' => 'UFix_32_0',
11628 
            },
11629 
            'direction' => 'out',
11630 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11631 
            'width' => 32,
11632 
          },
11633 
          'to_register7_dout' => {
11634 
            'attributes' => {
11635 
              'bin_pt' => 0,
11636 
              'is_floating_block' => 1,
11637 
              'must_be_hdl_vector' => 1,
11638 
              'period' => 1,
11639 
              'port_id' => 0,
11640 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
11641 
              'type' => 'UFix_32_0',
11642 
            },
11643 
            'direction' => 'in',
11644 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11645 
            'width' => 32,
11646 
          },
11647 
          'to_register7_en' => {
11648 
            'attributes' => {
11649 
              'bin_pt' => 0,
11650 
              'is_floating_block' => 1,
11651 
              'must_be_hdl_vector' => 1,
11652 
              'period' => 1,
11653 
              'port_id' => 1,
11654 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11655 
              'type' => 'Bool',
11656 
            },
11657 
            'direction' => 'out',
11658 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11659 
            'width' => 1,
11660 
          },
11661 
          'to_register8_ce' => {
11662 
            'attributes' => {
11663 
              'domain' => '',
11664 
              'group' => 1,
11665 
              'isCe' => 1,
11666 
              'is_floating_block' => 1,
11667 
              'period' => 1,
11668 
              'type' => 'logic',
11669 
            },
11670 
            'direction' => 'out',
11671 
            'hdlType' => 'std_logic',
11672 
            'width' => 1,
11673 
          },
11674 
          'to_register8_clk' => {
11675 
            'attributes' => {
11676 
              'domain' => '',
11677 
              'group' => 1,
11678 
              'isClk' => 1,
11679 
              'is_floating_block' => 1,
11680 
              'period' => 1,
11681 
              'type' => 'logic',
11682 
            },
11683 
            'direction' => 'out',
11684 
            'hdlType' => 'std_logic',
11685 
            'width' => 1,
11686 
          },
11687 
          'to_register8_clr' => {
11688 
            'attributes' => {
11689 
              'domain' => '',
11690 
              'group' => 1,
11691 
              'isClr' => 1,
11692 
              'is_floating_block' => 1,
11693 
              'period' => 1,
11694 
              'type' => 'logic',
11695 
              'valid_bit_used' => 0,
11696 
            },
11697 
            'direction' => 'out',
11698 
            'hdlType' => 'std_logic',
11699 
            'width' => 1,
11700 
          },
11701 
          'to_register8_data_in' => {
11702 
            'attributes' => {
11703 
              'bin_pt' => 0,
11704 
              'is_floating_block' => 1,
11705 
              'must_be_hdl_vector' => 1,
11706 
              'period' => 1,
11707 
              'port_id' => 0,
11708 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11709 
              'type' => 'Bool',
11710 
            },
11711 
            'direction' => 'out',
11712 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11713 
            'width' => 1,
11714 
          },
11715 
          'to_register8_dout' => {
11716 
            'attributes' => {
11717 
              'bin_pt' => 0,
11718 
              'is_floating_block' => 1,
11719 
              'must_be_hdl_vector' => 1,
11720 
              'period' => 1,
11721 
              'port_id' => 0,
11722 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11723 
              'type' => 'Bool',
11724 
            },
11725 
            'direction' => 'in',
11726 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11727 
            'width' => 1,
11728 
          },
11729 
          'to_register8_en' => {
11730 
            'attributes' => {
11731 
              'bin_pt' => 0,
11732 
              'is_floating_block' => 1,
11733 
              'must_be_hdl_vector' => 1,
11734 
              'period' => 1,
11735 
              'port_id' => 1,
11736 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11737 
              'type' => 'Bool',
11738 
            },
11739 
            'direction' => 'out',
11740 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11741 
            'width' => 1,
11742 
          },
11743 
          'to_register9_ce' => {
11744 
            'attributes' => {
11745 
              'domain' => '',
11746 
              'group' => 1,
11747 
              'isCe' => 1,
11748 
              'is_floating_block' => 1,
11749 
              'period' => 1,
11750 
              'type' => 'logic',
11751 
            },
11752 
            'direction' => 'out',
11753 
            'hdlType' => 'std_logic',
11754 
            'width' => 1,
11755 
          },
11756 
          'to_register9_clk' => {
11757 
            'attributes' => {
11758 
              'domain' => '',
11759 
              'group' => 1,
11760 
              'isClk' => 1,
11761 
              'is_floating_block' => 1,
11762 
              'period' => 1,
11763 
              'type' => 'logic',
11764 
            },
11765 
            'direction' => 'out',
11766 
            'hdlType' => 'std_logic',
11767 
            'width' => 1,
11768 
          },
11769 
          'to_register9_clr' => {
11770 
            'attributes' => {
11771 
              'domain' => '',
11772 
              'group' => 1,
11773 
              'isClr' => 1,
11774 
              'is_floating_block' => 1,
11775 
              'period' => 1,
11776 
              'type' => 'logic',
11777 
              'valid_bit_used' => 0,
11778 
            },
11779 
            'direction' => 'out',
11780 
            'hdlType' => 'std_logic',
11781 
            'width' => 1,
11782 
          },
11783 
          'to_register9_data_in' => {
11784 
            'attributes' => {
11785 
              'bin_pt' => 0,
11786 
              'is_floating_block' => 1,
11787 
              'must_be_hdl_vector' => 1,
11788 
              'period' => 1,
11789 
              'port_id' => 0,
11790 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11791 
              'type' => 'UFix_32_0',
11792 
            },
11793 
            'direction' => 'out',
11794 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11795 
            'width' => 32,
11796 
          },
11797 
          'to_register9_dout' => {
11798 
            'attributes' => {
11799 
              'bin_pt' => 0,
11800 
              'is_floating_block' => 1,
11801 
              'must_be_hdl_vector' => 1,
11802 
              'period' => 1,
11803 
              'port_id' => 0,
11804 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11805 
              'type' => 'UFix_32_0',
11806 
            },
11807 
            'direction' => 'in',
11808 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11809 
            'width' => 32,
11810 
          },
11811 
          'to_register9_en' => {
11812 
            'attributes' => {
11813 
              'bin_pt' => 0,
11814 
              'is_floating_block' => 1,
11815 
              'must_be_hdl_vector' => 1,
11816 
              'period' => 1,
11817 
              'port_id' => 1,
11818 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11819 
              'type' => 'Bool',
11820 
            },
11821 
            'direction' => 'out',
11822 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11823 
            'width' => 1,
11824 
          },
11825 
        },
11826 
        'subblocks' => {
11827 
          'default_clock_driver_x0' => {
11828 
            'connections' => {
11829 
              'ce_1' => 'ce_1_sg',
11830 
              'clk_1' => 'clk_1_sg',
11831 
              'sysce' => [
11832 
                'constant',
11833 
                '\'1\'',
11834 
              ],
11835 
              'sysce_clr' => [
11836 
                'constant',
11837 
                '\'0\'',
11838 
              ],
11839 
              'sysclk' => 'clkNet',
11840 
            },
11841 
            'entity' => {
11842 
              'attributes' => {
11843 
                'domain' => 'default',
11844 
                'hdlArchAttributes' => [
11845 
                  [
11846 
                    'syn_noprune',
11847 
                    'boolean',
11848 
                    'true',
11849 
                  ],
11850 
                  [
11851 
                    'optimize_primitives',
11852 
                    'boolean',
11853 
                    'false',
11854 
                  ],
11855 
                  [
11856 
                    'dont_touch',
11857 
                    'boolean',
11858 
                    'true',
11859 
                  ],
11860 
                ],
11861 
                'hdlEntityAttributes' => [
11862 
                ],
11863 
                'isClkDriver' => 1,
11864 
              },
11865 
              'entityName' => 'default_clock_driver',
11866 
              'ports' => {
11867 
                'ce_1' => {
11868 
                  'attributes' => {
11869 
                    'domain' => 'default',
11870 
                    'group' => 1,
11871 
                    'isCe' => 1,
11872 
                    'period' => 1,
11873 
                    'type' => 'logic',
11874 
                  },
11875 
                  'direction' => 'out',
11876 
                  'hdlType' => 'std_logic',
11877 
                  'width' => 1,
11878 
                },
11879 
                'clk_1' => {
11880 
                  'attributes' => {
11881 
                    'domain' => 'default',
11882 
                    'group' => 1,
11883 
                    'isClk' => 1,
11884 
                    'period' => 1,
11885 
                    'type' => 'logic',
11886 
                  },
11887 
                  'direction' => 'out',
11888 
                  'hdlType' => 'std_logic',
11889 
                  'width' => 1,
11890 
                },
11891 
                'sysce' => {
11892 
                  'attributes' => {
11893 
                    'group' => 4,
11894 
                    'isCe' => 1,
11895 
                    'period' => 1,
11896 
                  },
11897 
                  'direction' => 'in',
11898 
                  'hdlType' => 'std_logic',
11899 
                  'width' => 1,
11900 
                },
11901 
                'sysce_clr' => {
11902 
                  'attributes' => {
11903 
                    'group' => 4,
11904 
                    'isClr' => 1,
11905 
                    'period' => 1,
11906 
                  },
11907 
                  'direction' => 'in',
11908 
                  'hdlType' => 'std_logic',
11909 
                  'width' => 1,
11910 
                },
11911 
                'sysclk' => {
11912 
                  'attributes' => {
11913 
                    'group' => 4,
11914 
                    'isClk' => 1,
11915 
                    'period' => 1,
11916 
                  },
11917 
                  'direction' => 'in',
11918 
                  'hdlType' => 'std_logic',
11919 
                  'width' => 1,
11920 
                },
11921 
              },
11922 
            },
11923 
            'entityName' => 'default_clock_driver',
11924 
          },
11925 
          'inout_logic_x0' => {
11926 
            'connections' => {
11927 
              'data_in' => 'debug_in_2i_net_x0',
11928 
              'data_in_x0' => 'reg04_tv_net_x0',
11929 
              'data_in_x1' => 'reg04_td_net_x0',
11930 
              'data_in_x10' => 'debug_in_3i_net_x0',
11931 
              'data_in_x11' => 'debug_in_4i_net_x0',
11932 
              'data_in_x12' => 'reg09_tv_net_x0',
11933 
              'data_in_x13' => 'reg09_td_net_x0',
11934 
              'data_in_x14' => 'reg10_tv_net_x0',
11935 
              'data_in_x15' => 'reg10_td_net_x0',
11936 
              'data_in_x16' => 'reg08_tv_net_x0',
11937 
              'data_in_x17' => 'reg08_td_net_x0',
11938 
              'data_in_x18' => 'reg11_tv_net_x0',
11939 
              'data_in_x19' => 'reg11_td_net_x0',
11940 
              'data_in_x2' => 'reg05_tv_net_x0',
11941 
              'data_in_x20' => 'reg12_tv_net_x0',
11942 
              'data_in_x21' => 'reg01_tv_net_x0',
11943 
              'data_in_x22' => 'reg12_td_net_x0',
11944 
              'data_in_x23' => 'reg13_tv_net_x0',
11945 
              'data_in_x24' => 'reg13_td_net_x0',
11946 
              'data_in_x25' => 'reg14_tv_net_x0',
11947 
              'data_in_x26' => 'reg14_td_net_x0',
11948 
              'data_in_x27' => 'reg02_tv_net_x0',
11949 
              'data_in_x28' => 'reg02_td_net_x0',
11950 
              'data_in_x29' => 'debug_in_1i_net_x0',
11951 
              'data_in_x3' => 'reg05_td_net_x0',
11952 
              'data_in_x30' => 'reg01_td_net_x0',
11953 
              'data_in_x31' => 'reg03_tv_net_x0',
11954 
              'data_in_x32' => 'reg03_td_net_x0',
11955 
              'data_in_x4' => 'reg06_tv_net_x0',
11956 
              'data_in_x5' => 'reg06_td_net_x0',
11957 
              'data_in_x6' => 'reg07_tv_net_x0',
11958 
              'data_in_x7' => 'reg07_td_net_x0',
11959 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
11960 
              'data_in_x9' => 'dma_host2board_done_net_x0',
11961 
              'data_out' => 'from_register1_data_out_net',
11962 
              'data_out_x0' => 'from_register10_data_out_net',
11963 
              'data_out_x1' => 'from_register11_data_out_net',
11964 
              'data_out_x10' => 'from_register2_data_out_net',
11965 
              'data_out_x11' => 'from_register20_data_out_net',
11966 
              'data_out_x12' => 'from_register21_data_out_net',
11967 
              'data_out_x13' => 'from_register22_data_out_net',
11968 
              'data_out_x14' => 'from_register23_data_out_net',
11969 
              'data_out_x15' => 'from_register24_data_out_net',
11970 
              'data_out_x16' => 'from_register25_data_out_net',
11971 
              'data_out_x17' => 'from_register26_data_out_net',
11972 
              'data_out_x18' => 'from_register27_data_out_net',
11973 
              'data_out_x19' => 'from_register28_data_out_net',
11974 
              'data_out_x2' => 'from_register12_data_out_net',
11975 
              'data_out_x20' => 'from_register3_data_out_net',
11976 
              'data_out_x21' => 'from_register4_data_out_net',
11977 
              'data_out_x22' => 'from_register5_data_out_net',
11978 
              'data_out_x23' => 'from_register6_data_out_net',
11979 
              'data_out_x24' => 'from_register7_data_out_net',
11980 
              'data_out_x25' => 'from_register8_data_out_net',
11981 
              'data_out_x26' => 'from_register9_data_out_net',
11982 
              'data_out_x3' => 'from_register13_data_out_net',
11983 
              'data_out_x4' => 'from_register14_data_out_net',
11984 
              'data_out_x5' => 'from_register15_data_out_net',
11985 
              'data_out_x6' => 'from_register16_data_out_net',
11986 
              'data_out_x7' => 'from_register17_data_out_net',
11987 
              'data_out_x8' => 'from_register18_data_out_net',
11988 
              'data_out_x9' => 'from_register19_data_out_net',
11989 
              'debug_in_1i' => 'debug_in_1i_net',
11990 
              'debug_in_2i' => 'debug_in_2i_net',
11991 
              'debug_in_3i' => 'debug_in_3i_net',
11992 
              'debug_in_4i' => 'debug_in_4i_net',
11993 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
11994 
              'dma_host2board_done' => 'dma_host2board_done_net',
11995 
              'en' => 'constant5_op_net_x0',
11996 
              'en_x0' => 'constant5_op_net_x1',
11997 
              'en_x1' => 'constant5_op_net_x2',
11998 
              'en_x10' => 'constant5_op_net_x11',
11999 
              'en_x11' => 'constant5_op_net_x12',
12000 
              'en_x12' => 'constant1_op_net_x0',
12001 
              'en_x13' => 'constant1_op_net_x1',
12002 
              'en_x14' => 'constant1_op_net_x2',
12003 
              'en_x15' => 'constant1_op_net_x3',
12004 
              'en_x16' => 'constant1_op_net_x4',
12005 
              'en_x17' => 'constant1_op_net_x5',
12006 
              'en_x18' => 'constant1_op_net_x6',
12007 
              'en_x19' => 'constant1_op_net_x7',
12008 
              'en_x2' => 'constant5_op_net_x3',
12009 
              'en_x20' => 'constant1_op_net_x8',
12010 
              'en_x21' => 'constant5_op_net_x13',
12011 
              'en_x22' => 'constant1_op_net_x9',
12012 
              'en_x23' => 'constant1_op_net_x10',
12013 
              'en_x24' => 'constant1_op_net_x11',
12014 
              'en_x25' => 'constant1_op_net_x12',
12015 
              'en_x26' => 'constant1_op_net_x13',
12016 
              'en_x27' => 'constant5_op_net_x14',
12017 
              'en_x28' => 'constant5_op_net_x15',
12018 
              'en_x29' => 'constant5_op_net_x16',
12019 
              'en_x3' => 'constant5_op_net_x4',
12020 
              'en_x30' => 'constant5_op_net_x17',
12021 
              'en_x31' => 'constant5_op_net_x18',
12022 
              'en_x32' => 'constant5_op_net_x19',
12023 
              'en_x4' => 'constant5_op_net_x5',
12024 
              'en_x5' => 'constant5_op_net_x6',
12025 
              'en_x6' => 'constant5_op_net_x7',
12026 
              'en_x7' => 'constant5_op_net_x8',
12027 
              'en_x8' => 'constant5_op_net_x9',
12028 
              'en_x9' => 'constant5_op_net_x10',
12029 
              'reg01_rd' => 'from_register3_data_out_net_x0',
12030 
              'reg01_rv' => 'from_register1_data_out_net_x0',
12031 
              'reg01_td' => 'reg01_td_net',
12032 
              'reg01_tv' => 'reg01_tv_net',
12033 
              'reg02_rd' => 'from_register5_data_out_net_x0',
12034 
              'reg02_rv' => 'from_register2_data_out_net_x0',
12035 
              'reg02_td' => 'reg02_td_net',
12036 
              'reg02_tv' => 'reg02_tv_net',
12037 
              'reg03_rd' => 'from_register7_data_out_net_x0',
12038 
              'reg03_rv' => 'from_register6_data_out_net_x0',
12039 
              'reg03_td' => 'reg03_td_net',
12040 
              'reg03_tv' => 'reg03_tv_net',
12041 
              'reg04_rd' => 'from_register8_data_out_net_x0',
12042 
              'reg04_rv' => 'from_register4_data_out_net_x0',
12043 
              'reg04_td' => 'reg04_td_net',
12044 
              'reg04_tv' => 'reg04_tv_net',
12045 
              'reg05_rd' => 'from_register10_data_out_net_x0',
12046 
              'reg05_rv' => 'from_register9_data_out_net_x0',
12047 
              'reg05_td' => 'reg05_td_net',
12048 
              'reg05_tv' => 'reg05_tv_net',
12049 
              'reg06_rd' => 'from_register11_data_out_net_x0',
12050 
              'reg06_rv' => 'from_register12_data_out_net_x0',
12051 
              'reg06_td' => 'reg06_td_net',
12052 
              'reg06_tv' => 'reg06_tv_net',
12053 
              'reg07_rd' => 'from_register13_data_out_net_x0',
12054 
              'reg07_rv' => 'from_register14_data_out_net_x0',
12055 
              'reg07_td' => 'reg07_td_net',
12056 
              'reg07_tv' => 'reg07_tv_net',
12057 
              'reg08_rd' => 'from_register15_data_out_net_x0',
12058 
              'reg08_rv' => 'from_register16_data_out_net_x0',
12059 
              'reg08_td' => 'reg08_td_net',
12060 
              'reg08_tv' => 'reg08_tv_net',
12061 
              'reg09_rd' => 'from_register17_data_out_net_x0',
12062 
              'reg09_rv' => 'from_register18_data_out_net_x0',
12063 
              'reg09_td' => 'reg09_td_net',
12064 
              'reg09_tv' => 'reg09_tv_net',
12065 
              'reg10_rd' => 'from_register19_data_out_net_x0',
12066 
              'reg10_rv' => 'from_register20_data_out_net_x0',
12067 
              'reg10_td' => 'reg10_td_net',
12068 
              'reg10_tv' => 'reg10_tv_net',
12069 
              'reg11_rd' => 'from_register21_data_out_net_x0',
12070 
              'reg11_rv' => 'from_register22_data_out_net_x0',
12071 
              'reg11_td' => 'reg11_td_net',
12072 
              'reg11_tv' => 'reg11_tv_net',
12073 
              'reg12_rd' => 'from_register23_data_out_net_x0',
12074 
              'reg12_rv' => 'from_register24_data_out_net_x0',
12075 
              'reg12_td' => 'reg12_td_net',
12076 
              'reg12_tv' => 'reg12_tv_net',
12077 
              'reg13_rd' => 'from_register25_data_out_net_x0',
12078 
              'reg13_rv' => 'from_register26_data_out_net_x0',
12079 
              'reg13_td' => 'reg13_td_net',
12080 
              'reg13_tv' => 'reg13_tv_net',
12081 
              'reg14_rd' => 'from_register27_data_out_net_x0',
12082 
              'reg14_rv' => 'from_register28_data_out_net_x0',
12083 
              'reg14_td' => 'reg14_td_net',
12084 
              'reg14_tv' => 'reg14_tv_net',
12085 
            },
12086 
            'entity' => {
12087 
              'attributes' => {
12088 
                'entityAlreadyNetlisted' => 1,
12089 
                'hdlKind' => 'vhdl',
12090 
                'isDesign' => 1,
12091 
                'simulinkName' => 'INOUT_LOGIC',
12092 
              },
12093 
              'entityName' => 'inout_logic',
12094 
              'ports' => {
12095 
                'data_in' => {
12096 
                  'attributes' => {
12097 
                    'bin_pt' => 0,
12098 
                    'is_floating_block' => 1,
12099 
                    'must_be_hdl_vector' => 1,
12100 
                    'period' => 1,
12101 
                    'port_id' => 0,
12102 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12103 
                    'type' => 'UFix_32_0',
12104 
                  },
12105 
                  'direction' => 'out',
12106 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12107 
                  'width' => 32,
12108 
                },
12109 
                'data_in_x0' => {
12110 
                  'attributes' => {
12111 
                    'bin_pt' => 0,
12112 
                    'is_floating_block' => 1,
12113 
                    'must_be_hdl_vector' => 1,
12114 
                    'period' => 1,
12115 
                    'port_id' => 0,
12116 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12117 
                    'type' => 'Bool',
12118 
                  },
12119 
                  'direction' => 'out',
12120 
                  'hdlType' => 'std_logic',
12121 
                  'width' => 1,
12122 
                },
12123 
                'data_in_x1' => {
12124 
                  'attributes' => {
12125 
                    'bin_pt' => 0,
12126 
                    'is_floating_block' => 1,
12127 
                    'must_be_hdl_vector' => 1,
12128 
                    'period' => 1,
12129 
                    'port_id' => 0,
12130 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12131 
                    'type' => 'UFix_32_0',
12132 
                  },
12133 
                  'direction' => 'out',
12134 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12135 
                  'width' => 32,
12136 
                },
12137 
                'data_in_x10' => {
12138 
                  'attributes' => {
12139 
                    'bin_pt' => 0,
12140 
                    'is_floating_block' => 1,
12141 
                    'must_be_hdl_vector' => 1,
12142 
                    'period' => 1,
12143 
                    'port_id' => 0,
12144 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12145 
                    'type' => 'UFix_32_0',
12146 
                  },
12147 
                  'direction' => 'out',
12148 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12149 
                  'width' => 32,
12150 
                },
12151 
                'data_in_x11' => {
12152 
                  'attributes' => {
12153 
                    'bin_pt' => 0,
12154 
                    'is_floating_block' => 1,
12155 
                    'must_be_hdl_vector' => 1,
12156 
                    'period' => 1,
12157 
                    'port_id' => 0,
12158 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12159 
                    'type' => 'UFix_32_0',
12160 
                  },
12161 
                  'direction' => 'out',
12162 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12163 
                  'width' => 32,
12164 
                },
12165 
                'data_in_x12' => {
12166 
                  'attributes' => {
12167 
                    'bin_pt' => 0,
12168 
                    'is_floating_block' => 1,
12169 
                    'must_be_hdl_vector' => 1,
12170 
                    'period' => 1,
12171 
                    'port_id' => 0,
12172 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12173 
                    'type' => 'Bool',
12174 
                  },
12175 
                  'direction' => 'out',
12176 
                  'hdlType' => 'std_logic',
12177 
                  'width' => 1,
12178 
                },
12179 
                'data_in_x13' => {
12180 
                  'attributes' => {
12181 
                    'bin_pt' => 0,
12182 
                    'is_floating_block' => 1,
12183 
                    'must_be_hdl_vector' => 1,
12184 
                    'period' => 1,
12185 
                    'port_id' => 0,
12186 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12187 
                    'type' => 'UFix_32_0',
12188 
                  },
12189 
                  'direction' => 'out',
12190 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12191 
                  'width' => 32,
12192 
                },
12193 
                'data_in_x14' => {
12194 
                  'attributes' => {
12195 
                    'bin_pt' => 0,
12196 
                    'is_floating_block' => 1,
12197 
                    'must_be_hdl_vector' => 1,
12198 
                    'period' => 1,
12199 
                    'port_id' => 0,
12200 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12201 
                    'type' => 'Bool',
12202 
                  },
12203 
                  'direction' => 'out',
12204 
                  'hdlType' => 'std_logic',
12205 
                  'width' => 1,
12206 
                },
12207 
                'data_in_x15' => {
12208 
                  'attributes' => {
12209 
                    'bin_pt' => 0,
12210 
                    'is_floating_block' => 1,
12211 
                    'must_be_hdl_vector' => 1,
12212 
                    'period' => 1,
12213 
                    'port_id' => 0,
12214 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12215 
                    'type' => 'UFix_32_0',
12216 
                  },
12217 
                  'direction' => 'out',
12218 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12219 
                  'width' => 32,
12220 
                },
12221 
                'data_in_x16' => {
12222 
                  'attributes' => {
12223 
                    'bin_pt' => 0,
12224 
                    'is_floating_block' => 1,
12225 
                    'must_be_hdl_vector' => 1,
12226 
                    'period' => 1,
12227 
                    'port_id' => 0,
12228 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12229 
                    'type' => 'Bool',
12230 
                  },
12231 
                  'direction' => 'out',
12232 
                  'hdlType' => 'std_logic',
12233 
                  'width' => 1,
12234 
                },
12235 
                'data_in_x17' => {
12236 
                  'attributes' => {
12237 
                    'bin_pt' => 0,
12238 
                    'is_floating_block' => 1,
12239 
                    'must_be_hdl_vector' => 1,
12240 
                    'period' => 1,
12241 
                    'port_id' => 0,
12242 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12243 
                    'type' => 'UFix_32_0',
12244 
                  },
12245 
                  'direction' => 'out',
12246 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12247 
                  'width' => 32,
12248 
                },
12249 
                'data_in_x18' => {
12250 
                  'attributes' => {
12251 
                    'bin_pt' => 0,
12252 
                    'is_floating_block' => 1,
12253 
                    'must_be_hdl_vector' => 1,
12254 
                    'period' => 1,
12255 
                    'port_id' => 0,
12256 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12257 
                    'type' => 'Bool',
12258 
                  },
12259 
                  'direction' => 'out',
12260 
                  'hdlType' => 'std_logic',
12261 
                  'width' => 1,
12262 
                },
12263 
                'data_in_x19' => {
12264 
                  'attributes' => {
12265 
                    'bin_pt' => 0,
12266 
                    'is_floating_block' => 1,
12267 
                    'must_be_hdl_vector' => 1,
12268 
                    'period' => 1,
12269 
                    'port_id' => 0,
12270 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12271 
                    'type' => 'UFix_32_0',
12272 
                  },
12273 
                  'direction' => 'out',
12274 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12275 
                  'width' => 32,
12276 
                },
12277 
                'data_in_x2' => {
12278 
                  'attributes' => {
12279 
                    'bin_pt' => 0,
12280 
                    'is_floating_block' => 1,
12281 
                    'must_be_hdl_vector' => 1,
12282 
                    'period' => 1,
12283 
                    'port_id' => 0,
12284 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12285 
                    'type' => 'Bool',
12286 
                  },
12287 
                  'direction' => 'out',
12288 
                  'hdlType' => 'std_logic',
12289 
                  'width' => 1,
12290 
                },
12291 
                'data_in_x20' => {
12292 
                  'attributes' => {
12293 
                    'bin_pt' => 0,
12294 
                    'is_floating_block' => 1,
12295 
                    'must_be_hdl_vector' => 1,
12296 
                    'period' => 1,
12297 
                    'port_id' => 0,
12298 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12299 
                    'type' => 'Bool',
12300 
                  },
12301 
                  'direction' => 'out',
12302 
                  'hdlType' => 'std_logic',
12303 
                  'width' => 1,
12304 
                },
12305 
                'data_in_x21' => {
12306 
                  'attributes' => {
12307 
                    'bin_pt' => 0,
12308 
                    'is_floating_block' => 1,
12309 
                    'must_be_hdl_vector' => 1,
12310 
                    'period' => 1,
12311 
                    'port_id' => 0,
12312 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12313 
                    'type' => 'Bool',
12314 
                  },
12315 
                  'direction' => 'out',
12316 
                  'hdlType' => 'std_logic',
12317 
                  'width' => 1,
12318 
                },
12319 
                'data_in_x22' => {
12320 
                  'attributes' => {
12321 
                    'bin_pt' => 0,
12322 
                    'is_floating_block' => 1,
12323 
                    'must_be_hdl_vector' => 1,
12324 
                    'period' => 1,
12325 
                    'port_id' => 0,
12326 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12327 
                    'type' => 'UFix_32_0',
12328 
                  },
12329 
                  'direction' => 'out',
12330 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12331 
                  'width' => 32,
12332 
                },
12333 
                'data_in_x23' => {
12334 
                  'attributes' => {
12335 
                    'bin_pt' => 0,
12336 
                    'is_floating_block' => 1,
12337 
                    'must_be_hdl_vector' => 1,
12338 
                    'period' => 1,
12339 
                    'port_id' => 0,
12340 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12341 
                    'type' => 'Bool',
12342 
                  },
12343 
                  'direction' => 'out',
12344 
                  'hdlType' => 'std_logic',
12345 
                  'width' => 1,
12346 
                },
12347 
                'data_in_x24' => {
12348 
                  'attributes' => {
12349 
                    'bin_pt' => 0,
12350 
                    'is_floating_block' => 1,
12351 
                    'must_be_hdl_vector' => 1,
12352 
                    'period' => 1,
12353 
                    'port_id' => 0,
12354 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12355 
                    'type' => 'UFix_32_0',
12356 
                  },
12357 
                  'direction' => 'out',
12358 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12359 
                  'width' => 32,
12360 
                },
12361 
                'data_in_x25' => {
12362 
                  'attributes' => {
12363 
                    'bin_pt' => 0,
12364 
                    'is_floating_block' => 1,
12365 
                    'must_be_hdl_vector' => 1,
12366 
                    'period' => 1,
12367 
                    'port_id' => 0,
12368 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12369 
                    'type' => 'Bool',
12370 
                  },
12371 
                  'direction' => 'out',
12372 
                  'hdlType' => 'std_logic',
12373 
                  'width' => 1,
12374 
                },
12375 
                'data_in_x26' => {
12376 
                  'attributes' => {
12377 
                    'bin_pt' => 0,
12378 
                    'is_floating_block' => 1,
12379 
                    'must_be_hdl_vector' => 1,
12380 
                    'period' => 1,
12381 
                    'port_id' => 0,
12382 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12383 
                    'type' => 'UFix_32_0',
12384 
                  },
12385 
                  'direction' => 'out',
12386 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12387 
                  'width' => 32,
12388 
                },
12389 
                'data_in_x27' => {
12390 
                  'attributes' => {
12391 
                    'bin_pt' => 0,
12392 
                    'is_floating_block' => 1,
12393 
                    'must_be_hdl_vector' => 1,
12394 
                    'period' => 1,
12395 
                    'port_id' => 0,
12396 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12397 
                    'type' => 'Bool',
12398 
                  },
12399 
                  'direction' => 'out',
12400 
                  'hdlType' => 'std_logic',
12401 
                  'width' => 1,
12402 
                },
12403 
                'data_in_x28' => {
12404 
                  'attributes' => {
12405 
                    'bin_pt' => 0,
12406 
                    'is_floating_block' => 1,
12407 
                    'must_be_hdl_vector' => 1,
12408 
                    'period' => 1,
12409 
                    'port_id' => 0,
12410 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12411 
                    'type' => 'UFix_32_0',
12412 
                  },
12413 
                  'direction' => 'out',
12414 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12415 
                  'width' => 32,
12416 
                },
12417 
                'data_in_x29' => {
12418 
                  'attributes' => {
12419 
                    'bin_pt' => 0,
12420 
                    'is_floating_block' => 1,
12421 
                    'must_be_hdl_vector' => 1,
12422 
                    'period' => 1,
12423 
                    'port_id' => 0,
12424 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12425 
                    'type' => 'UFix_32_0',
12426 
                  },
12427 
                  'direction' => 'out',
12428 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12429 
                  'width' => 32,
12430 
                },
12431 
                'data_in_x3' => {
12432 
                  'attributes' => {
12433 
                    'bin_pt' => 0,
12434 
                    'is_floating_block' => 1,
12435 
                    'must_be_hdl_vector' => 1,
12436 
                    'period' => 1,
12437 
                    'port_id' => 0,
12438 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12439 
                    'type' => 'UFix_32_0',
12440 
                  },
12441 
                  'direction' => 'out',
12442 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12443 
                  'width' => 32,
12444 
                },
12445 
                'data_in_x30' => {
12446 
                  'attributes' => {
12447 
                    'bin_pt' => 0,
12448 
                    'is_floating_block' => 1,
12449 
                    'must_be_hdl_vector' => 1,
12450 
                    'period' => 1,
12451 
                    'port_id' => 0,
12452 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12453 
                    'type' => 'UFix_32_0',
12454 
                  },
12455 
                  'direction' => 'out',
12456 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12457 
                  'width' => 32,
12458 
                },
12459 
                'data_in_x31' => {
12460 
                  'attributes' => {
12461 
                    'bin_pt' => 0,
12462 
                    'is_floating_block' => 1,
12463 
                    'must_be_hdl_vector' => 1,
12464 
                    'period' => 1,
12465 
                    'port_id' => 0,
12466 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12467 
                    'type' => 'Bool',
12468 
                  },
12469 
                  'direction' => 'out',
12470 
                  'hdlType' => 'std_logic',
12471 
                  'width' => 1,
12472 
                },
12473 
                'data_in_x32' => {
12474 
                  'attributes' => {
12475 
                    'bin_pt' => 0,
12476 
                    'is_floating_block' => 1,
12477 
                    'must_be_hdl_vector' => 1,
12478 
                    'period' => 1,
12479 
                    'port_id' => 0,
12480 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12481 
                    'type' => 'UFix_32_0',
12482 
                  },
12483 
                  'direction' => 'out',
12484 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12485 
                  'width' => 32,
12486 
                },
12487 
                'data_in_x4' => {
12488 
                  'attributes' => {
12489 
                    'bin_pt' => 0,
12490 
                    'is_floating_block' => 1,
12491 
                    'must_be_hdl_vector' => 1,
12492 
                    'period' => 1,
12493 
                    'port_id' => 0,
12494 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12495 
                    'type' => 'Bool',
12496 
                  },
12497 
                  'direction' => 'out',
12498 
                  'hdlType' => 'std_logic',
12499 
                  'width' => 1,
12500 
                },
12501 
                'data_in_x5' => {
12502 
                  'attributes' => {
12503 
                    'bin_pt' => 0,
12504 
                    'is_floating_block' => 1,
12505 
                    'must_be_hdl_vector' => 1,
12506 
                    'period' => 1,
12507 
                    'port_id' => 0,
12508 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12509 
                    'type' => 'UFix_32_0',
12510 
                  },
12511 
                  'direction' => 'out',
12512 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12513 
                  'width' => 32,
12514 
                },
12515 
                'data_in_x6' => {
12516 
                  'attributes' => {
12517 
                    'bin_pt' => 0,
12518 
                    'is_floating_block' => 1,
12519 
                    'must_be_hdl_vector' => 1,
12520 
                    'period' => 1,
12521 
                    'port_id' => 0,
12522 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12523 
                    'type' => 'Bool',
12524 
                  },
12525 
                  'direction' => 'out',
12526 
                  'hdlType' => 'std_logic',
12527 
                  'width' => 1,
12528 
                },
12529 
                'data_in_x7' => {
12530 
                  'attributes' => {
12531 
                    'bin_pt' => 0,
12532 
                    'is_floating_block' => 1,
12533 
                    'must_be_hdl_vector' => 1,
12534 
                    'period' => 1,
12535 
                    'port_id' => 0,
12536 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12537 
                    'type' => 'UFix_32_0',
12538 
                  },
12539 
                  'direction' => 'out',
12540 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12541 
                  'width' => 32,
12542 
                },
12543 
                'data_in_x8' => {
12544 
                  'attributes' => {
12545 
                    'bin_pt' => 0,
12546 
                    'is_floating_block' => 1,
12547 
                    'must_be_hdl_vector' => 1,
12548 
                    'period' => 1,
12549 
                    'port_id' => 0,
12550 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12551 
                    'type' => 'UFix_1_0',
12552 
                  },
12553 
                  'direction' => 'out',
12554 
                  'hdlType' => 'std_logic',
12555 
                  'width' => 1,
12556 
                },
12557 
                'data_in_x9' => {
12558 
                  'attributes' => {
12559 
                    'bin_pt' => 0,
12560 
                    'is_floating_block' => 1,
12561 
                    'must_be_hdl_vector' => 1,
12562 
                    'period' => 1,
12563 
                    'port_id' => 0,
12564 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12565 
                    'type' => 'UFix_1_0',
12566 
                  },
12567 
                  'direction' => 'out',
12568 
                  'hdlType' => 'std_logic',
12569 
                  'width' => 1,
12570 
                },
12571 
                'data_out' => {
12572 
                  'attributes' => {
12573 
                    'bin_pt' => 0,
12574 
                    'is_floating_block' => 1,
12575 
                    'must_be_hdl_vector' => 1,
12576 
                    'period' => 1,
12577 
                    'port_id' => 0,
12578 
                    'simulinkName' => 'INOUT_LOGIC/From Register1',
12579 
                    'type' => 'UFix_1_0',
12580 
                  },
12581 
                  'direction' => 'in',
12582 
                  'hdlType' => 'std_logic',
12583 
                  'width' => 1,
12584 
                },
12585 
                'data_out_x0' => {
12586 
                  'attributes' => {
12587 
                    'bin_pt' => 0,
12588 
                    'is_floating_block' => 1,
12589 
                    'must_be_hdl_vector' => 1,
12590 
                    'period' => 1,
12591 
                    'port_id' => 0,
12592 
                    'simulinkName' => 'INOUT_LOGIC/From Register10',
12593 
                    'type' => 'UFix_32_0',
12594 
                  },
12595 
                  'direction' => 'in',
12596 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12597 
                  'width' => 32,
12598 
                },
12599 
                'data_out_x1' => {
12600 
                  'attributes' => {
12601 
                    'bin_pt' => 0,
12602 
                    'is_floating_block' => 1,
12603 
                    'must_be_hdl_vector' => 1,
12604 
                    'period' => 1,
12605 
                    'port_id' => 0,
12606 
                    'simulinkName' => 'INOUT_LOGIC/From Register11',
12607 
                    'type' => 'UFix_32_0',
12608 
                  },
12609 
                  'direction' => 'in',
12610 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12611 
                  'width' => 32,
12612 
                },
12613 
                'data_out_x10' => {
12614 
                  'attributes' => {
12615 
                    'bin_pt' => 0,
12616 
                    'is_floating_block' => 1,
12617 
                    'must_be_hdl_vector' => 1,
12618 
                    'period' => 1,
12619 
                    'port_id' => 0,
12620 
                    'simulinkName' => 'INOUT_LOGIC/From Register2',
12621 
                    'type' => 'UFix_1_0',
12622 
                  },
12623 
                  'direction' => 'in',
12624 
                  'hdlType' => 'std_logic',
12625 
                  'width' => 1,
12626 
                },
12627 
                'data_out_x11' => {
12628 
                  'attributes' => {
12629 
                    'bin_pt' => 0,
12630 
                    'is_floating_block' => 1,
12631 
                    'must_be_hdl_vector' => 1,
12632 
                    'period' => 1,
12633 
                    'port_id' => 0,
12634 
                    'simulinkName' => 'INOUT_LOGIC/From Register20',
12635 
                    'type' => 'UFix_1_0',
12636 
                  },
12637 
                  'direction' => 'in',
12638 
                  'hdlType' => 'std_logic',
12639 
                  'width' => 1,
12640 
                },
12641 
                'data_out_x12' => {
12642 
                  'attributes' => {
12643 
                    'bin_pt' => 0,
12644 
                    'is_floating_block' => 1,
12645 
                    'must_be_hdl_vector' => 1,
12646 
                    'period' => 1,
12647 
                    'port_id' => 0,
12648 
                    'simulinkName' => 'INOUT_LOGIC/From Register21',
12649 
                    'type' => 'UFix_32_0',
12650 
                  },
12651 
                  'direction' => 'in',
12652 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12653 
                  'width' => 32,
12654 
                },
12655 
                'data_out_x13' => {
12656 
                  'attributes' => {
12657 
                    'bin_pt' => 0,
12658 
                    'is_floating_block' => 1,
12659 
                    'must_be_hdl_vector' => 1,
12660 
                    'period' => 1,
12661 
                    'port_id' => 0,
12662 
                    'simulinkName' => 'INOUT_LOGIC/From Register22',
12663 
                    'type' => 'UFix_1_0',
12664 
                  },
12665 
                  'direction' => 'in',
12666 
                  'hdlType' => 'std_logic',
12667 
                  'width' => 1,
12668 
                },
12669 
                'data_out_x14' => {
12670 
                  'attributes' => {
12671 
                    'bin_pt' => 0,
12672 
                    'is_floating_block' => 1,
12673 
                    'must_be_hdl_vector' => 1,
12674 
                    'period' => 1,
12675 
                    'port_id' => 0,
12676 
                    'simulinkName' => 'INOUT_LOGIC/From Register23',
12677 
                    'type' => 'UFix_32_0',
12678 
                  },
12679 
                  'direction' => 'in',
12680 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12681 
                  'width' => 32,
12682 
                },
12683 
                'data_out_x15' => {
12684 
                  'attributes' => {
12685 
                    'bin_pt' => 0,
12686 
                    'is_floating_block' => 1,
12687 
                    'must_be_hdl_vector' => 1,
12688 
                    'period' => 1,
12689 
                    'port_id' => 0,
12690 
                    'simulinkName' => 'INOUT_LOGIC/From Register24',
12691 
                    'type' => 'UFix_1_0',
12692 
                  },
12693 
                  'direction' => 'in',
12694 
                  'hdlType' => 'std_logic',
12695 
                  'width' => 1,
12696 
                },
12697 
                'data_out_x16' => {
12698 
                  'attributes' => {
12699 
                    'bin_pt' => 0,
12700 
                    'is_floating_block' => 1,
12701 
                    'must_be_hdl_vector' => 1,
12702 
                    'period' => 1,
12703 
                    'port_id' => 0,
12704 
                    'simulinkName' => 'INOUT_LOGIC/From Register25',
12705 
                    'type' => 'UFix_32_0',
12706 
                  },
12707 
                  'direction' => 'in',
12708 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12709 
                  'width' => 32,
12710 
                },
12711 
                'data_out_x17' => {
12712 
                  'attributes' => {
12713 
                    'bin_pt' => 0,
12714 
                    'is_floating_block' => 1,
12715 
                    'must_be_hdl_vector' => 1,
12716 
                    'period' => 1,
12717 
                    'port_id' => 0,
12718 
                    'simulinkName' => 'INOUT_LOGIC/From Register26',
12719 
                    'type' => 'UFix_1_0',
12720 
                  },
12721 
                  'direction' => 'in',
12722 
                  'hdlType' => 'std_logic',
12723 
                  'width' => 1,
12724 
                },
12725 
                'data_out_x18' => {
12726 
                  'attributes' => {
12727 
                    'bin_pt' => 0,
12728 
                    'is_floating_block' => 1,
12729 
                    'must_be_hdl_vector' => 1,
12730 
                    'period' => 1,
12731 
                    'port_id' => 0,
12732 
                    'simulinkName' => 'INOUT_LOGIC/From Register27',
12733 
                    'type' => 'UFix_32_0',
12734 
                  },
12735 
                  'direction' => 'in',
12736 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12737 
                  'width' => 32,
12738 
                },
12739 
                'data_out_x19' => {
12740 
                  'attributes' => {
12741 
                    'bin_pt' => 0,
12742 
                    'is_floating_block' => 1,
12743 
                    'must_be_hdl_vector' => 1,
12744 
                    'period' => 1,
12745 
                    'port_id' => 0,
12746 
                    'simulinkName' => 'INOUT_LOGIC/From Register28',
12747 
                    'type' => 'UFix_1_0',
12748 
                  },
12749 
                  'direction' => 'in',
12750 
                  'hdlType' => 'std_logic',
12751 
                  'width' => 1,
12752 
                },
12753 
                'data_out_x2' => {
12754 
                  'attributes' => {
12755 
                    'bin_pt' => 0,
12756 
                    'is_floating_block' => 1,
12757 
                    'must_be_hdl_vector' => 1,
12758 
                    'period' => 1,
12759 
                    'port_id' => 0,
12760 
                    'simulinkName' => 'INOUT_LOGIC/From Register12',
12761 
                    'type' => 'UFix_1_0',
12762 
                  },
12763 
                  'direction' => 'in',
12764 
                  'hdlType' => 'std_logic',
12765 
                  'width' => 1,
12766 
                },
12767 
                'data_out_x20' => {
12768 
                  'attributes' => {
12769 
                    'bin_pt' => 0,
12770 
                    'is_floating_block' => 1,
12771 
                    'must_be_hdl_vector' => 1,
12772 
                    'period' => 1,
12773 
                    'port_id' => 0,
12774 
                    'simulinkName' => 'INOUT_LOGIC/From Register3',
12775 
                    'type' => 'UFix_32_0',
12776 
                  },
12777 
                  'direction' => 'in',
12778 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12779 
                  'width' => 32,
12780 
                },
12781 
                'data_out_x21' => {
12782 
                  'attributes' => {
12783 
                    'bin_pt' => 0,
12784 
                    'is_floating_block' => 1,
12785 
                    'must_be_hdl_vector' => 1,
12786 
                    'period' => 1,
12787 
                    'port_id' => 0,
12788 
                    'simulinkName' => 'INOUT_LOGIC/From Register4',
12789 
                    'type' => 'UFix_1_0',
12790 
                  },
12791 
                  'direction' => 'in',
12792 
                  'hdlType' => 'std_logic',
12793 
                  'width' => 1,
12794 
                },
12795 
                'data_out_x22' => {
12796 
                  'attributes' => {
12797 
                    'bin_pt' => 0,
12798 
                    'is_floating_block' => 1,
12799 
                    'must_be_hdl_vector' => 1,
12800 
                    'period' => 1,
12801 
                    'port_id' => 0,
12802 
                    'simulinkName' => 'INOUT_LOGIC/From Register5',
12803 
                    'type' => 'UFix_32_0',
12804 
                  },
12805 
                  'direction' => 'in',
12806 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12807 
                  'width' => 32,
12808 
                },
12809 
                'data_out_x23' => {
12810 
                  'attributes' => {
12811 
                    'bin_pt' => 0,
12812 
                    'is_floating_block' => 1,
12813 
                    'must_be_hdl_vector' => 1,
12814 
                    'period' => 1,
12815 
                    'port_id' => 0,
12816 
                    'simulinkName' => 'INOUT_LOGIC/From Register6',
12817 
                    'type' => 'UFix_1_0',
12818 
                  },
12819 
                  'direction' => 'in',
12820 
                  'hdlType' => 'std_logic',
12821 
                  'width' => 1,
12822 
                },
12823 
                'data_out_x24' => {
12824 
                  'attributes' => {
12825 
                    'bin_pt' => 0,
12826 
                    'is_floating_block' => 1,
12827 
                    'must_be_hdl_vector' => 1,
12828 
                    'period' => 1,
12829 
                    'port_id' => 0,
12830 
                    'simulinkName' => 'INOUT_LOGIC/From Register7',
12831 
                    'type' => 'UFix_32_0',
12832 
                  },
12833 
                  'direction' => 'in',
12834 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12835 
                  'width' => 32,
12836 
                },
12837 
                'data_out_x25' => {
12838 
                  'attributes' => {
12839 
                    'bin_pt' => 0,
12840 
                    'is_floating_block' => 1,
12841 
                    'must_be_hdl_vector' => 1,
12842 
                    'period' => 1,
12843 
                    'port_id' => 0,
12844 
                    'simulinkName' => 'INOUT_LOGIC/From Register8',
12845 
                    'type' => 'UFix_32_0',
12846 
                  },
12847 
                  'direction' => 'in',
12848 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12849 
                  'width' => 32,
12850 
                },
12851 
                'data_out_x26' => {
12852 
                  'attributes' => {
12853 
                    'bin_pt' => 0,
12854 
                    'is_floating_block' => 1,
12855 
                    'must_be_hdl_vector' => 1,
12856 
                    'period' => 1,
12857 
                    'port_id' => 0,
12858 
                    'simulinkName' => 'INOUT_LOGIC/From Register9',
12859 
                    'type' => 'UFix_1_0',
12860 
                  },
12861 
                  'direction' => 'in',
12862 
                  'hdlType' => 'std_logic',
12863 
                  'width' => 1,
12864 
                },
12865 
                'data_out_x3' => {
12866 
                  'attributes' => {
12867 
                    'bin_pt' => 0,
12868 
                    'is_floating_block' => 1,
12869 
                    'must_be_hdl_vector' => 1,
12870 
                    'period' => 1,
12871 
                    'port_id' => 0,
12872 
                    'simulinkName' => 'INOUT_LOGIC/From Register13',
12873 
                    'type' => 'UFix_32_0',
12874 
                  },
12875 
                  'direction' => 'in',
12876 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12877 
                  'width' => 32,
12878 
                },
12879 
                'data_out_x4' => {
12880 
                  'attributes' => {
12881 
                    'bin_pt' => 0,
12882 
                    'is_floating_block' => 1,
12883 
                    'must_be_hdl_vector' => 1,
12884 
                    'period' => 1,
12885 
                    'port_id' => 0,
12886 
                    'simulinkName' => 'INOUT_LOGIC/From Register14',
12887 
                    'type' => 'UFix_1_0',
12888 
                  },
12889 
                  'direction' => 'in',
12890 
                  'hdlType' => 'std_logic',
12891 
                  'width' => 1,
12892 
                },
12893 
                'data_out_x5' => {
12894 
                  'attributes' => {
12895 
                    'bin_pt' => 0,
12896 
                    'is_floating_block' => 1,
12897 
                    'must_be_hdl_vector' => 1,
12898 
                    'period' => 1,
12899 
                    'port_id' => 0,
12900 
                    'simulinkName' => 'INOUT_LOGIC/From Register15',
12901 
                    'type' => 'UFix_32_0',
12902 
                  },
12903 
                  'direction' => 'in',
12904 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12905 
                  'width' => 32,
12906 
                },
12907 
                'data_out_x6' => {
12908 
                  'attributes' => {
12909 
                    'bin_pt' => 0,
12910 
                    'is_floating_block' => 1,
12911 
                    'must_be_hdl_vector' => 1,
12912 
                    'period' => 1,
12913 
                    'port_id' => 0,
12914 
                    'simulinkName' => 'INOUT_LOGIC/From Register16',
12915 
                    'type' => 'UFix_1_0',
12916 
                  },
12917 
                  'direction' => 'in',
12918 
                  'hdlType' => 'std_logic',
12919 
                  'width' => 1,
12920 
                },
12921 
                'data_out_x7' => {
12922 
                  'attributes' => {
12923 
                    'bin_pt' => 0,
12924 
                    'is_floating_block' => 1,
12925 
                    'must_be_hdl_vector' => 1,
12926 
                    'period' => 1,
12927 
                    'port_id' => 0,
12928 
                    'simulinkName' => 'INOUT_LOGIC/From Register17',
12929 
                    'type' => 'UFix_32_0',
12930 
                  },
12931 
                  'direction' => 'in',
12932 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12933 
                  'width' => 32,
12934 
                },
12935 
                'data_out_x8' => {
12936 
                  'attributes' => {
12937 
                    'bin_pt' => 0,
12938 
                    'is_floating_block' => 1,
12939 
                    'must_be_hdl_vector' => 1,
12940 
                    'period' => 1,
12941 
                    'port_id' => 0,
12942 
                    'simulinkName' => 'INOUT_LOGIC/From Register18',
12943 
                    'type' => 'UFix_1_0',
12944 
                  },
12945 
                  'direction' => 'in',
12946 
                  'hdlType' => 'std_logic',
12947 
                  'width' => 1,
12948 
                },
12949 
                'data_out_x9' => {
12950 
                  'attributes' => {
12951 
                    'bin_pt' => 0,
12952 
                    'is_floating_block' => 1,
12953 
                    'must_be_hdl_vector' => 1,
12954 
                    'period' => 1,
12955 
                    'port_id' => 0,
12956 
                    'simulinkName' => 'INOUT_LOGIC/From Register19',
12957 
                    'type' => 'UFix_32_0',
12958 
                  },
12959 
                  'direction' => 'in',
12960 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12961 
                  'width' => 32,
12962 
                },
12963 
                'debug_in_1i' => {
12964 
                  'attributes' => {
12965 
                    'bin_pt' => 0,
12966 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
12967 
                    'is_floating_block' => 1,
12968 
                    'is_gateway_port' => 1,
12969 
                    'must_be_hdl_vector' => 1,
12970 
                    'period' => 1,
12971 
                    'port_id' => 0,
12972 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_1i',
12973 
                    'source_block' => 'INOUT_LOGIC',
12974 
                    'timingConstraint' => 'none',
12975 
                    'type' => 'UFix_32_0',
12976 
                  },
12977 
                  'direction' => 'in',
12978 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12979 
                  'width' => 32,
12980 
                },
12981 
                'debug_in_2i' => {
12982 
                  'attributes' => {
12983 
                    'bin_pt' => 0,
12984 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
12985 
                    'is_floating_block' => 1,
12986 
                    'is_gateway_port' => 1,
12987 
                    'must_be_hdl_vector' => 1,
12988 
                    'period' => 1,
12989 
                    'port_id' => 0,
12990 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_2i',
12991 
                    'source_block' => 'INOUT_LOGIC',
12992 
                    'timingConstraint' => 'none',
12993 
                    'type' => 'UFix_32_0',
12994 
                  },
12995 
                  'direction' => 'in',
12996 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12997 
                  'width' => 32,
12998 
                },
12999 
                'debug_in_3i' => {
13000 
                  'attributes' => {
13001 
                    'bin_pt' => 0,
13002 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
13003 
                    'is_floating_block' => 1,
13004 
                    'is_gateway_port' => 1,
13005 
                    'must_be_hdl_vector' => 1,
13006 
                    'period' => 1,
13007 
                    'port_id' => 0,
13008 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_3i',
13009 
                    'source_block' => 'INOUT_LOGIC',
13010 
                    'timingConstraint' => 'none',
13011 
                    'type' => 'UFix_32_0',
13012 
                  },
13013 
                  'direction' => 'in',
13014 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13015 
                  'width' => 32,
13016 
                },
13017 
                'debug_in_4i' => {
13018 
                  'attributes' => {
13019 
                    'bin_pt' => 0,
13020 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
13021 
                    'is_floating_block' => 1,
13022 
                    'is_gateway_port' => 1,
13023 
                    'must_be_hdl_vector' => 1,
13024 
                    'period' => 1,
13025 
                    'port_id' => 0,
13026 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_4i',
13027 
                    'source_block' => 'INOUT_LOGIC',
13028 
                    'timingConstraint' => 'none',
13029 
                    'type' => 'UFix_32_0',
13030 
                  },
13031 
                  'direction' => 'in',
13032 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13033 
                  'width' => 32,
13034 
                },
13035 
                'dma_host2board_busy' => {
13036 
                  'attributes' => {
13037 
                    'bin_pt' => 0,
13038 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
13039 
                    'is_floating_block' => 1,
13040 
                    'is_gateway_port' => 1,
13041 
                    'must_be_hdl_vector' => 1,
13042 
                    'period' => 1,
13043 
                    'port_id' => 0,
13044 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Busy',
13045 
                    'source_block' => 'INOUT_LOGIC',
13046 
                    'timingConstraint' => 'none',
13047 
                    'type' => 'UFix_1_0',
13048 
                  },
13049 
                  'direction' => 'in',
13050 
                  'hdlType' => 'std_logic',
13051 
                  'width' => 1,
13052 
                },
13053 
                'dma_host2board_done' => {
13054 
                  'attributes' => {
13055 
                    'bin_pt' => 0,
13056 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
13057 
                    'is_floating_block' => 1,
13058 
                    'is_gateway_port' => 1,
13059 
                    'must_be_hdl_vector' => 1,
13060 
                    'period' => 1,
13061 
                    'port_id' => 0,
13062 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Done',
13063 
                    'source_block' => 'INOUT_LOGIC',
13064 
                    'timingConstraint' => 'none',
13065 
                    'type' => 'UFix_1_0',
13066 
                  },
13067 
                  'direction' => 'in',
13068 
                  'hdlType' => 'std_logic',
13069 
                  'width' => 1,
13070 
                },
13071 
                'en' => {
13072 
                  'attributes' => {
13073 
                    'bin_pt' => 0,
13074 
                    'is_floating_block' => 1,
13075 
                    'must_be_hdl_vector' => 1,
13076 
                    'period' => 1,
13077 
                    'port_id' => 0,
13078 
                    'simulinkName' => 'INOUT_LOGIC/en',
13079 
                    'type' => 'Bool',
13080 
                  },
13081 
                  'direction' => 'out',
13082 
                  'hdlType' => 'std_logic',
13083 
                  'width' => 1,
13084 
                },
13085 
                'en_x0' => {
13086 
                  'attributes' => {
13087 
                    'bin_pt' => 0,
13088 
                    'is_floating_block' => 1,
13089 
                    'must_be_hdl_vector' => 1,
13090 
                    'period' => 1,
13091 
                    'port_id' => 0,
13092 
                    'simulinkName' => 'INOUT_LOGIC/en',
13093 
                    'type' => 'Bool',
13094 
                  },
13095 
                  'direction' => 'out',
13096 
                  'hdlType' => 'std_logic',
13097 
                  'width' => 1,
13098 
                },
13099 
                'en_x1' => {
13100 
                  'attributes' => {
13101 
                    'bin_pt' => 0,
13102 
                    'is_floating_block' => 1,
13103 
                    'must_be_hdl_vector' => 1,
13104 
                    'period' => 1,
13105 
                    'port_id' => 0,
13106 
                    'simulinkName' => 'INOUT_LOGIC/en',
13107 
                    'type' => 'Bool',
13108 
                  },
13109 
                  'direction' => 'out',
13110 
                  'hdlType' => 'std_logic',
13111 
                  'width' => 1,
13112 
                },
13113 
                'en_x10' => {
13114 
                  'attributes' => {
13115 
                    'bin_pt' => 0,
13116 
                    'is_floating_block' => 1,
13117 
                    'must_be_hdl_vector' => 1,
13118 
                    'period' => 1,
13119 
                    'port_id' => 0,
13120 
                    'simulinkName' => 'INOUT_LOGIC/en',
13121 
                    'type' => 'Bool',
13122 
                  },
13123 
                  'direction' => 'out',
13124 
                  'hdlType' => 'std_logic',
13125 
                  'width' => 1,
13126 
                },
13127 
                'en_x11' => {
13128 
                  'attributes' => {
13129 
                    'bin_pt' => 0,
13130 
                    'is_floating_block' => 1,
13131 
                    'must_be_hdl_vector' => 1,
13132 
                    'period' => 1,
13133 
                    'port_id' => 0,
13134 
                    'simulinkName' => 'INOUT_LOGIC/en',
13135 
                    'type' => 'Bool',
13136 
                  },
13137 
                  'direction' => 'out',
13138 
                  'hdlType' => 'std_logic',
13139 
                  'width' => 1,
13140 
                },
13141 
                'en_x12' => {
13142 
                  'attributes' => {
13143 
                    'bin_pt' => 0,
13144 
                    'is_floating_block' => 1,
13145 
                    'must_be_hdl_vector' => 1,
13146 
                    'period' => 1,
13147 
                    'port_id' => 0,
13148 
                    'simulinkName' => 'INOUT_LOGIC/en',
13149 
                    'type' => 'Bool',
13150 
                  },
13151 
                  'direction' => 'out',
13152 
                  'hdlType' => 'std_logic',
13153 
                  'width' => 1,
13154 
                },
13155 
                'en_x13' => {
13156 
                  'attributes' => {
13157 
                    'bin_pt' => 0,
13158 
                    'is_floating_block' => 1,
13159 
                    'must_be_hdl_vector' => 1,
13160 
                    'period' => 1,
13161 
                    'port_id' => 0,
13162 
                    'simulinkName' => 'INOUT_LOGIC/en',
13163 
                    'type' => 'Bool',
13164 
                  },
13165 
                  'direction' => 'out',
13166 
                  'hdlType' => 'std_logic',
13167 
                  'width' => 1,
13168 
                },
13169 
                'en_x14' => {
13170 
                  'attributes' => {
13171 
                    'bin_pt' => 0,
13172 
                    'is_floating_block' => 1,
13173 
                    'must_be_hdl_vector' => 1,
13174 
                    'period' => 1,
13175 
                    'port_id' => 0,
13176 
                    'simulinkName' => 'INOUT_LOGIC/en',
13177 
                    'type' => 'Bool',
13178 
                  },
13179 
                  'direction' => 'out',
13180 
                  'hdlType' => 'std_logic',
13181 
                  'width' => 1,
13182 
                },
13183 
                'en_x15' => {
13184 
                  'attributes' => {
13185 
                    'bin_pt' => 0,
13186 
                    'is_floating_block' => 1,
13187 
                    'must_be_hdl_vector' => 1,
13188 
                    'period' => 1,
13189 
                    'port_id' => 0,
13190 
                    'simulinkName' => 'INOUT_LOGIC/en',
13191 
                    'type' => 'Bool',
13192 
                  },
13193 
                  'direction' => 'out',
13194 
                  'hdlType' => 'std_logic',
13195 
                  'width' => 1,
13196 
                },
13197 
                'en_x16' => {
13198 
                  'attributes' => {
13199 
                    'bin_pt' => 0,
13200 
                    'is_floating_block' => 1,
13201 
                    'must_be_hdl_vector' => 1,
13202 
                    'period' => 1,
13203 
                    'port_id' => 0,
13204 
                    'simulinkName' => 'INOUT_LOGIC/en',
13205 
                    'type' => 'Bool',
13206 
                  },
13207 
                  'direction' => 'out',
13208 
                  'hdlType' => 'std_logic',
13209 
                  'width' => 1,
13210 
                },
13211 
                'en_x17' => {
13212 
                  'attributes' => {
13213 
                    'bin_pt' => 0,
13214 
                    'is_floating_block' => 1,
13215 
                    'must_be_hdl_vector' => 1,
13216 
                    'period' => 1,
13217 
                    'port_id' => 0,
13218 
                    'simulinkName' => 'INOUT_LOGIC/en',
13219 
                    'type' => 'Bool',
13220 
                  },
13221 
                  'direction' => 'out',
13222 
                  'hdlType' => 'std_logic',
13223 
                  'width' => 1,
13224 
                },
13225 
                'en_x18' => {
13226 
                  'attributes' => {
13227 
                    'bin_pt' => 0,
13228 
                    'is_floating_block' => 1,
13229 
                    'must_be_hdl_vector' => 1,
13230 
                    'period' => 1,
13231 
                    'port_id' => 0,
13232 
                    'simulinkName' => 'INOUT_LOGIC/en',
13233 
                    'type' => 'Bool',
13234 
                  },
13235 
                  'direction' => 'out',
13236 
                  'hdlType' => 'std_logic',
13237 
                  'width' => 1,
13238 
                },
13239 
                'en_x19' => {
13240 
                  'attributes' => {
13241 
                    'bin_pt' => 0,
13242 
                    'is_floating_block' => 1,
13243 
                    'must_be_hdl_vector' => 1,
13244 
                    'period' => 1,
13245 
                    'port_id' => 0,
13246 
                    'simulinkName' => 'INOUT_LOGIC/en',
13247 
                    'type' => 'Bool',
13248 
                  },
13249 
                  'direction' => 'out',
13250 
                  'hdlType' => 'std_logic',
13251 
                  'width' => 1,
13252 
                },
13253 
                'en_x2' => {
13254 
                  'attributes' => {
13255 
                    'bin_pt' => 0,
13256 
                    'is_floating_block' => 1,
13257 
                    'must_be_hdl_vector' => 1,
13258 
                    'period' => 1,
13259 
                    'port_id' => 0,
13260 
                    'simulinkName' => 'INOUT_LOGIC/en',
13261 
                    'type' => 'Bool',
13262 
                  },
13263 
                  'direction' => 'out',
13264 
                  'hdlType' => 'std_logic',
13265 
                  'width' => 1,
13266 
                },
13267 
                'en_x20' => {
13268 
                  'attributes' => {
13269 
                    'bin_pt' => 0,
13270 
                    'is_floating_block' => 1,
13271 
                    'must_be_hdl_vector' => 1,
13272 
                    'period' => 1,
13273 
                    'port_id' => 0,
13274 
                    'simulinkName' => 'INOUT_LOGIC/en',
13275 
                    'type' => 'Bool',
13276 
                  },
13277 
                  'direction' => 'out',
13278 
                  'hdlType' => 'std_logic',
13279 
                  'width' => 1,
13280 
                },
13281 
                'en_x21' => {
13282 
                  'attributes' => {
13283 
                    'bin_pt' => 0,
13284 
                    'is_floating_block' => 1,
13285 
                    'must_be_hdl_vector' => 1,
13286 
                    'period' => 1,
13287 
                    'port_id' => 0,
13288 
                    'simulinkName' => 'INOUT_LOGIC/en',
13289 
                    'type' => 'Bool',
13290 
                  },
13291 
                  'direction' => 'out',
13292 
                  'hdlType' => 'std_logic',
13293 
                  'width' => 1,
13294 
                },
13295 
                'en_x22' => {
13296 
                  'attributes' => {
13297 
                    'bin_pt' => 0,
13298 
                    'is_floating_block' => 1,
13299 
                    'must_be_hdl_vector' => 1,
13300 
                    'period' => 1,
13301 
                    'port_id' => 0,
13302 
                    'simulinkName' => 'INOUT_LOGIC/en',
13303 
                    'type' => 'Bool',
13304 
                  },
13305 
                  'direction' => 'out',
13306 
                  'hdlType' => 'std_logic',
13307 
                  'width' => 1,
13308 
                },
13309 
                'en_x23' => {
13310 
                  'attributes' => {
13311 
                    'bin_pt' => 0,
13312 
                    'is_floating_block' => 1,
13313 
                    'must_be_hdl_vector' => 1,
13314 
                    'period' => 1,
13315 
                    'port_id' => 0,
13316 
                    'simulinkName' => 'INOUT_LOGIC/en',
13317 
                    'type' => 'Bool',
13318 
                  },
13319 
                  'direction' => 'out',
13320 
                  'hdlType' => 'std_logic',
13321 
                  'width' => 1,
13322 
                },
13323 
                'en_x24' => {
13324 
                  'attributes' => {
13325 
                    'bin_pt' => 0,
13326 
                    'is_floating_block' => 1,
13327 
                    'must_be_hdl_vector' => 1,
13328 
                    'period' => 1,
13329 
                    'port_id' => 0,
13330 
                    'simulinkName' => 'INOUT_LOGIC/en',
13331 
                    'type' => 'Bool',
13332 
                  },
13333 
                  'direction' => 'out',
13334 
                  'hdlType' => 'std_logic',
13335 
                  'width' => 1,
13336 
                },
13337 
                'en_x25' => {
13338 
                  'attributes' => {
13339 
                    'bin_pt' => 0,
13340 
                    'is_floating_block' => 1,
13341 
                    'must_be_hdl_vector' => 1,
13342 
                    'period' => 1,
13343 
                    'port_id' => 0,
13344 
                    'simulinkName' => 'INOUT_LOGIC/en',
13345 
                    'type' => 'Bool',
13346 
                  },
13347 
                  'direction' => 'out',
13348 
                  'hdlType' => 'std_logic',
13349 
                  'width' => 1,
13350 
                },
13351 
                'en_x26' => {
13352 
                  'attributes' => {
13353 
                    'bin_pt' => 0,
13354 
                    'is_floating_block' => 1,
13355 
                    'must_be_hdl_vector' => 1,
13356 
                    'period' => 1,
13357 
                    'port_id' => 0,
13358 
                    'simulinkName' => 'INOUT_LOGIC/en',
13359 
                    'type' => 'Bool',
13360 
                  },
13361 
                  'direction' => 'out',
13362 
                  'hdlType' => 'std_logic',
13363 
                  'width' => 1,
13364 
                },
13365 
                'en_x27' => {
13366 
                  'attributes' => {
13367 
                    'bin_pt' => 0,
13368 
                    'is_floating_block' => 1,
13369 
                    'must_be_hdl_vector' => 1,
13370 
                    'period' => 1,
13371 
                    'port_id' => 0,
13372 
                    'simulinkName' => 'INOUT_LOGIC/en',
13373 
                    'type' => 'Bool',
13374 
                  },
13375 
                  'direction' => 'out',
13376 
                  'hdlType' => 'std_logic',
13377 
                  'width' => 1,
13378 
                },
13379 
                'en_x28' => {
13380 
                  'attributes' => {
13381 
                    'bin_pt' => 0,
13382 
                    'is_floating_block' => 1,
13383 
                    'must_be_hdl_vector' => 1,
13384 
                    'period' => 1,
13385 
                    'port_id' => 0,
13386 
                    'simulinkName' => 'INOUT_LOGIC/en',
13387 
                    'type' => 'Bool',
13388 
                  },
13389 
                  'direction' => 'out',
13390 
                  'hdlType' => 'std_logic',
13391 
                  'width' => 1,
13392 
                },
13393 
                'en_x29' => {
13394 
                  'attributes' => {
13395 
                    'bin_pt' => 0,
13396 
                    'is_floating_block' => 1,
13397 
                    'must_be_hdl_vector' => 1,
13398 
                    'period' => 1,
13399 
                    'port_id' => 0,
13400 
                    'simulinkName' => 'INOUT_LOGIC/en',
13401 
                    'type' => 'Bool',
13402 
                  },
13403 
                  'direction' => 'out',
13404 
                  'hdlType' => 'std_logic',
13405 
                  'width' => 1,
13406 
                },
13407 
                'en_x3' => {
13408 
                  'attributes' => {
13409 
                    'bin_pt' => 0,
13410 
                    'is_floating_block' => 1,
13411 
                    'must_be_hdl_vector' => 1,
13412 
                    'period' => 1,
13413 
                    'port_id' => 0,
13414 
                    'simulinkName' => 'INOUT_LOGIC/en',
13415 
                    'type' => 'Bool',
13416 
                  },
13417 
                  'direction' => 'out',
13418 
                  'hdlType' => 'std_logic',
13419 
                  'width' => 1,
13420 
                },
13421 
                'en_x30' => {
13422 
                  'attributes' => {
13423 
                    'bin_pt' => 0,
13424 
                    'is_floating_block' => 1,
13425 
                    'must_be_hdl_vector' => 1,
13426 
                    'period' => 1,
13427 
                    'port_id' => 0,
13428 
                    'simulinkName' => 'INOUT_LOGIC/en',
13429 
                    'type' => 'Bool',
13430 
                  },
13431 
                  'direction' => 'out',
13432 
                  'hdlType' => 'std_logic',
13433 
                  'width' => 1,
13434 
                },
13435 
                'en_x31' => {
13436 
                  'attributes' => {
13437 
                    'bin_pt' => 0,
13438 
                    'is_floating_block' => 1,
13439 
                    'must_be_hdl_vector' => 1,
13440 
                    'period' => 1,
13441 
                    'port_id' => 0,
13442 
                    'simulinkName' => 'INOUT_LOGIC/en',
13443 
                    'type' => 'Bool',
13444 
                  },
13445 
                  'direction' => 'out',
13446 
                  'hdlType' => 'std_logic',
13447 
                  'width' => 1,
13448 
                },
13449 
                'en_x32' => {
13450 
                  'attributes' => {
13451 
                    'bin_pt' => 0,
13452 
                    'is_floating_block' => 1,
13453 
                    'must_be_hdl_vector' => 1,
13454 
                    'period' => 1,
13455 
                    'port_id' => 0,
13456 
                    'simulinkName' => 'INOUT_LOGIC/en',
13457 
                    'type' => 'Bool',
13458 
                  },
13459 
                  'direction' => 'out',
13460 
                  'hdlType' => 'std_logic',
13461 
                  'width' => 1,
13462 
                },
13463 
                'en_x4' => {
13464 
                  'attributes' => {
13465 
                    'bin_pt' => 0,
13466 
                    'is_floating_block' => 1,
13467 
                    'must_be_hdl_vector' => 1,
13468 
                    'period' => 1,
13469 
                    'port_id' => 0,
13470 
                    'simulinkName' => 'INOUT_LOGIC/en',
13471 
                    'type' => 'Bool',
13472 
                  },
13473 
                  'direction' => 'out',
13474 
                  'hdlType' => 'std_logic',
13475 
                  'width' => 1,
13476 
                },
13477 
                'en_x5' => {
13478 
                  'attributes' => {
13479 
                    'bin_pt' => 0,
13480 
                    'is_floating_block' => 1,
13481 
                    'must_be_hdl_vector' => 1,
13482 
                    'period' => 1,
13483 
                    'port_id' => 0,
13484 
                    'simulinkName' => 'INOUT_LOGIC/en',
13485 
                    'type' => 'Bool',
13486 
                  },
13487 
                  'direction' => 'out',
13488 
                  'hdlType' => 'std_logic',
13489 
                  'width' => 1,
13490 
                },
13491 
                'en_x6' => {
13492 
                  'attributes' => {
13493 
                    'bin_pt' => 0,
13494 
                    'is_floating_block' => 1,
13495 
                    'must_be_hdl_vector' => 1,
13496 
                    'period' => 1,
13497 
                    'port_id' => 0,
13498 
                    'simulinkName' => 'INOUT_LOGIC/en',
13499 
                    'type' => 'Bool',
13500 
                  },
13501 
                  'direction' => 'out',
13502 
                  'hdlType' => 'std_logic',
13503 
                  'width' => 1,
13504 
                },
13505 
                'en_x7' => {
13506 
                  'attributes' => {
13507 
                    'bin_pt' => 0,
13508 
                    'is_floating_block' => 1,
13509 
                    'must_be_hdl_vector' => 1,
13510 
                    'period' => 1,
13511 
                    'port_id' => 0,
13512 
                    'simulinkName' => 'INOUT_LOGIC/en',
13513 
                    'type' => 'Bool',
13514 
                  },
13515 
                  'direction' => 'out',
13516 
                  'hdlType' => 'std_logic',
13517 
                  'width' => 1,
13518 
                },
13519 
                'en_x8' => {
13520 
                  'attributes' => {
13521 
                    'bin_pt' => 0,
13522 
                    'is_floating_block' => 1,
13523 
                    'must_be_hdl_vector' => 1,
13524 
                    'period' => 1,
13525 
                    'port_id' => 0,
13526 
                    'simulinkName' => 'INOUT_LOGIC/en',
13527 
                    'type' => 'Bool',
13528 
                  },
13529 
                  'direction' => 'out',
13530 
                  'hdlType' => 'std_logic',
13531 
                  'width' => 1,
13532 
                },
13533 
                'en_x9' => {
13534 
                  'attributes' => {
13535 
                    'bin_pt' => 0,
13536 
                    'is_floating_block' => 1,
13537 
                    'must_be_hdl_vector' => 1,
13538 
                    'period' => 1,
13539 
                    'port_id' => 0,
13540 
                    'simulinkName' => 'INOUT_LOGIC/en',
13541 
                    'type' => 'Bool',
13542 
                  },
13543 
                  'direction' => 'out',
13544 
                  'hdlType' => 'std_logic',
13545 
                  'width' => 1,
13546 
                },
13547 
                'reg01_rd' => {
13548 
                  'attributes' => {
13549 
                    'bin_pt' => 0,
13550 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
13551 
                    'is_floating_block' => 1,
13552 
                    'is_gateway_port' => 1,
13553 
                    'must_be_hdl_vector' => 1,
13554 
                    'period' => 1,
13555 
                    'port_id' => 0,
13556 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rd',
13557 
                    'source_block' => 'INOUT_LOGIC',
13558 
                    'timingConstraint' => 'none',
13559 
                    'type' => 'UFix_32_0',
13560 
                  },
13561 
                  'direction' => 'out',
13562 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13563 
                  'width' => 32,
13564 
                },
13565 
                'reg01_rv' => {
13566 
                  'attributes' => {
13567 
                    'bin_pt' => 0,
13568 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
13569 
                    'is_floating_block' => 1,
13570 
                    'is_gateway_port' => 1,
13571 
                    'must_be_hdl_vector' => 1,
13572 
                    'period' => 1,
13573 
                    'port_id' => 0,
13574 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rv',
13575 
                    'source_block' => 'INOUT_LOGIC',
13576 
                    'timingConstraint' => 'none',
13577 
                    'type' => 'UFix_1_0',
13578 
                  },
13579 
                  'direction' => 'out',
13580 
                  'hdlType' => 'std_logic',
13581 
                  'width' => 1,
13582 
                },
13583 
                'reg01_td' => {
13584 
                  'attributes' => {
13585 
                    'bin_pt' => 0,
13586 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
13587 
                    'is_floating_block' => 1,
13588 
                    'is_gateway_port' => 1,
13589 
                    'must_be_hdl_vector' => 1,
13590 
                    'period' => 1,
13591 
                    'port_id' => 0,
13592 
                    'simulinkName' => 'INOUT_LOGIC/reg01_td',
13593 
                    'source_block' => 'INOUT_LOGIC',
13594 
                    'timingConstraint' => 'none',
13595 
                    'type' => 'UFix_32_0',
13596 
                  },
13597 
                  'direction' => 'in',
13598 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13599 
                  'width' => 32,
13600 
                },
13601 
                'reg01_tv' => {
13602 
                  'attributes' => {
13603 
                    'bin_pt' => 0,
13604 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
13605 
                    'is_floating_block' => 1,
13606 
                    'is_gateway_port' => 1,
13607 
                    'must_be_hdl_vector' => 1,
13608 
                    'period' => 1,
13609 
                    'port_id' => 0,
13610 
                    'simulinkName' => 'INOUT_LOGIC/reg01_tv',
13611 
                    'source_block' => 'INOUT_LOGIC',
13612 
                    'timingConstraint' => 'none',
13613 
                    'type' => 'Bool',
13614 
                  },
13615 
                  'direction' => 'in',
13616 
                  'hdlType' => 'std_logic',
13617 
                  'width' => 1,
13618 
                },
13619 
                'reg02_rd' => {
13620 
                  'attributes' => {
13621 
                    'bin_pt' => 0,
13622 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
13623 
                    'is_floating_block' => 1,
13624 
                    'is_gateway_port' => 1,
13625 
                    'must_be_hdl_vector' => 1,
13626 
                    'period' => 1,
13627 
                    'port_id' => 0,
13628 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rd',
13629 
                    'source_block' => 'INOUT_LOGIC',
13630 
                    'timingConstraint' => 'none',
13631 
                    'type' => 'UFix_32_0',
13632 
                  },
13633 
                  'direction' => 'out',
13634 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13635 
                  'width' => 32,
13636 
                },
13637 
                'reg02_rv' => {
13638 
                  'attributes' => {
13639 
                    'bin_pt' => 0,
13640 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
13641 
                    'is_floating_block' => 1,
13642 
                    'is_gateway_port' => 1,
13643 
                    'must_be_hdl_vector' => 1,
13644 
                    'period' => 1,
13645 
                    'port_id' => 0,
13646 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rv',
13647 
                    'source_block' => 'INOUT_LOGIC',
13648 
                    'timingConstraint' => 'none',
13649 
                    'type' => 'UFix_1_0',
13650 
                  },
13651 
                  'direction' => 'out',
13652 
                  'hdlType' => 'std_logic',
13653 
                  'width' => 1,
13654 
                },
13655 
                'reg02_td' => {
13656 
                  'attributes' => {
13657 
                    'bin_pt' => 0,
13658 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
13659 
                    'is_floating_block' => 1,
13660 
                    'is_gateway_port' => 1,
13661 
                    'must_be_hdl_vector' => 1,
13662 
                    'period' => 1,
13663 
                    'port_id' => 0,
13664 
                    'simulinkName' => 'INOUT_LOGIC/reg02_td',
13665 
                    'source_block' => 'INOUT_LOGIC',
13666 
                    'timingConstraint' => 'none',
13667 
                    'type' => 'UFix_32_0',
13668 
                  },
13669 
                  'direction' => 'in',
13670 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13671 
                  'width' => 32,
13672 
                },
13673 
                'reg02_tv' => {
13674 
                  'attributes' => {
13675 
                    'bin_pt' => 0,
13676 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
13677 
                    'is_floating_block' => 1,
13678 
                    'is_gateway_port' => 1,
13679 
                    'must_be_hdl_vector' => 1,
13680 
                    'period' => 1,
13681 
                    'port_id' => 0,
13682 
                    'simulinkName' => 'INOUT_LOGIC/reg02_tv',
13683 
                    'source_block' => 'INOUT_LOGIC',
13684 
                    'timingConstraint' => 'none',
13685 
                    'type' => 'Bool',
13686 
                  },
13687 
                  'direction' => 'in',
13688 
                  'hdlType' => 'std_logic',
13689 
                  'width' => 1,
13690 
                },
13691 
                'reg03_rd' => {
13692 
                  'attributes' => {
13693 
                    'bin_pt' => 0,
13694 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
13695 
                    'is_floating_block' => 1,
13696 
                    'is_gateway_port' => 1,
13697 
                    'must_be_hdl_vector' => 1,
13698 
                    'period' => 1,
13699 
                    'port_id' => 0,
13700 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rd',
13701 
                    'source_block' => 'INOUT_LOGIC',
13702 
                    'timingConstraint' => 'none',
13703 
                    'type' => 'UFix_32_0',
13704 
                  },
13705 
                  'direction' => 'out',
13706 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13707 
                  'width' => 32,
13708 
                },
13709 
                'reg03_rv' => {
13710 
                  'attributes' => {
13711 
                    'bin_pt' => 0,
13712 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
13713 
                    'is_floating_block' => 1,
13714 
                    'is_gateway_port' => 1,
13715 
                    'must_be_hdl_vector' => 1,
13716 
                    'period' => 1,
13717 
                    'port_id' => 0,
13718 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rv',
13719 
                    'source_block' => 'INOUT_LOGIC',
13720 
                    'timingConstraint' => 'none',
13721 
                    'type' => 'UFix_1_0',
13722 
                  },
13723 
                  'direction' => 'out',
13724 
                  'hdlType' => 'std_logic',
13725 
                  'width' => 1,
13726 
                },
13727 
                'reg03_td' => {
13728 
                  'attributes' => {
13729 
                    'bin_pt' => 0,
13730 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
13731 
                    'is_floating_block' => 1,
13732 
                    'is_gateway_port' => 1,
13733 
                    'must_be_hdl_vector' => 1,
13734 
                    'period' => 1,
13735 
                    'port_id' => 0,
13736 
                    'simulinkName' => 'INOUT_LOGIC/reg03_td',
13737 
                    'source_block' => 'INOUT_LOGIC',
13738 
                    'timingConstraint' => 'none',
13739 
                    'type' => 'UFix_32_0',
13740 
                  },
13741 
                  'direction' => 'in',
13742 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13743 
                  'width' => 32,
13744 
                },
13745 
                'reg03_tv' => {
13746 
                  'attributes' => {
13747 
                    'bin_pt' => 0,
13748 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
13749 
                    'is_floating_block' => 1,
13750 
                    'is_gateway_port' => 1,
13751 
                    'must_be_hdl_vector' => 1,
13752 
                    'period' => 1,
13753 
                    'port_id' => 0,
13754 
                    'simulinkName' => 'INOUT_LOGIC/reg03_tv',
13755 
                    'source_block' => 'INOUT_LOGIC',
13756 
                    'timingConstraint' => 'none',
13757 
                    'type' => 'Bool',
13758 
                  },
13759 
                  'direction' => 'in',
13760 
                  'hdlType' => 'std_logic',
13761 
                  'width' => 1,
13762 
                },
13763 
                'reg04_rd' => {
13764 
                  'attributes' => {
13765 
                    'bin_pt' => 0,
13766 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
13767 
                    'is_floating_block' => 1,
13768 
                    'is_gateway_port' => 1,
13769 
                    'must_be_hdl_vector' => 1,
13770 
                    'period' => 1,
13771 
                    'port_id' => 0,
13772 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rd',
13773 
                    'source_block' => 'INOUT_LOGIC',
13774 
                    'timingConstraint' => 'none',
13775 
                    'type' => 'UFix_32_0',
13776 
                  },
13777 
                  'direction' => 'out',
13778 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13779 
                  'width' => 32,
13780 
                },
13781 
                'reg04_rv' => {
13782 
                  'attributes' => {
13783 
                    'bin_pt' => 0,
13784 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
13785 
                    'is_floating_block' => 1,
13786 
                    'is_gateway_port' => 1,
13787 
                    'must_be_hdl_vector' => 1,
13788 
                    'period' => 1,
13789 
                    'port_id' => 0,
13790 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rv',
13791 
                    'source_block' => 'INOUT_LOGIC',
13792 
                    'timingConstraint' => 'none',
13793 
                    'type' => 'UFix_1_0',
13794 
                  },
13795 
                  'direction' => 'out',
13796 
                  'hdlType' => 'std_logic',
13797 
                  'width' => 1,
13798 
                },
13799 
                'reg04_td' => {
13800 
                  'attributes' => {
13801 
                    'bin_pt' => 0,
13802 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
13803 
                    'is_floating_block' => 1,
13804 
                    'is_gateway_port' => 1,
13805 
                    'must_be_hdl_vector' => 1,
13806 
                    'period' => 1,
13807 
                    'port_id' => 0,
13808 
                    'simulinkName' => 'INOUT_LOGIC/reg04_td',
13809 
                    'source_block' => 'INOUT_LOGIC',
13810 
                    'timingConstraint' => 'none',
13811 
                    'type' => 'UFix_32_0',
13812 
                  },
13813 
                  'direction' => 'in',
13814 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13815 
                  'width' => 32,
13816 
                },
13817 
                'reg04_tv' => {
13818 
                  'attributes' => {
13819 
                    'bin_pt' => 0,
13820 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
13821 
                    'is_floating_block' => 1,
13822 
                    'is_gateway_port' => 1,
13823 
                    'must_be_hdl_vector' => 1,
13824 
                    'period' => 1,
13825 
                    'port_id' => 0,
13826 
                    'simulinkName' => 'INOUT_LOGIC/reg04_tv',
13827 
                    'source_block' => 'INOUT_LOGIC',
13828 
                    'timingConstraint' => 'none',
13829 
                    'type' => 'Bool',
13830 
                  },
13831 
                  'direction' => 'in',
13832 
                  'hdlType' => 'std_logic',
13833 
                  'width' => 1,
13834 
                },
13835 
                'reg05_rd' => {
13836 
                  'attributes' => {
13837 
                    'bin_pt' => 0,
13838 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
13839 
                    'is_floating_block' => 1,
13840 
                    'is_gateway_port' => 1,
13841 
                    'must_be_hdl_vector' => 1,
13842 
                    'period' => 1,
13843 
                    'port_id' => 0,
13844 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rd',
13845 
                    'source_block' => 'INOUT_LOGIC',
13846 
                    'timingConstraint' => 'none',
13847 
                    'type' => 'UFix_32_0',
13848 
                  },
13849 
                  'direction' => 'out',
13850 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13851 
                  'width' => 32,
13852 
                },
13853 
                'reg05_rv' => {
13854 
                  'attributes' => {
13855 
                    'bin_pt' => 0,
13856 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
13857 
                    'is_floating_block' => 1,
13858 
                    'is_gateway_port' => 1,
13859 
                    'must_be_hdl_vector' => 1,
13860 
                    'period' => 1,
13861 
                    'port_id' => 0,
13862 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rv',
13863 
                    'source_block' => 'INOUT_LOGIC',
13864 
                    'timingConstraint' => 'none',
13865 
                    'type' => 'UFix_1_0',
13866 
                  },
13867 
                  'direction' => 'out',
13868 
                  'hdlType' => 'std_logic',
13869 
                  'width' => 1,
13870 
                },
13871 
                'reg05_td' => {
13872 
                  'attributes' => {
13873 
                    'bin_pt' => 0,
13874 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
13875 
                    'is_floating_block' => 1,
13876 
                    'is_gateway_port' => 1,
13877 
                    'must_be_hdl_vector' => 1,
13878 
                    'period' => 1,
13879 
                    'port_id' => 0,
13880 
                    'simulinkName' => 'INOUT_LOGIC/reg05_td',
13881 
                    'source_block' => 'INOUT_LOGIC',
13882 
                    'timingConstraint' => 'none',
13883 
                    'type' => 'UFix_32_0',
13884 
                  },
13885 
                  'direction' => 'in',
13886 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13887 
                  'width' => 32,
13888 
                },
13889 
                'reg05_tv' => {
13890 
                  'attributes' => {
13891 
                    'bin_pt' => 0,
13892 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
13893 
                    'is_floating_block' => 1,
13894 
                    'is_gateway_port' => 1,
13895 
                    'must_be_hdl_vector' => 1,
13896 
                    'period' => 1,
13897 
                    'port_id' => 0,
13898 
                    'simulinkName' => 'INOUT_LOGIC/reg05_tv',
13899 
                    'source_block' => 'INOUT_LOGIC',
13900 
                    'timingConstraint' => 'none',
13901 
                    'type' => 'Bool',
13902 
                  },
13903 
                  'direction' => 'in',
13904 
                  'hdlType' => 'std_logic',
13905 
                  'width' => 1,
13906 
                },
13907 
                'reg06_rd' => {
13908 
                  'attributes' => {
13909 
                    'bin_pt' => 0,
13910 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
13911 
                    'is_floating_block' => 1,
13912 
                    'is_gateway_port' => 1,
13913 
                    'must_be_hdl_vector' => 1,
13914 
                    'period' => 1,
13915 
                    'port_id' => 0,
13916 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rd',
13917 
                    'source_block' => 'INOUT_LOGIC',
13918 
                    'timingConstraint' => 'none',
13919 
                    'type' => 'UFix_32_0',
13920 
                  },
13921 
                  'direction' => 'out',
13922 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13923 
                  'width' => 32,
13924 
                },
13925 
                'reg06_rv' => {
13926 
                  'attributes' => {
13927 
                    'bin_pt' => 0,
13928 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
13929 
                    'is_floating_block' => 1,
13930 
                    'is_gateway_port' => 1,
13931 
                    'must_be_hdl_vector' => 1,
13932 
                    'period' => 1,
13933 
                    'port_id' => 0,
13934 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rv',
13935 
                    'source_block' => 'INOUT_LOGIC',
13936 
                    'timingConstraint' => 'none',
13937 
                    'type' => 'UFix_1_0',
13938 
                  },
13939 
                  'direction' => 'out',
13940 
                  'hdlType' => 'std_logic',
13941 
                  'width' => 1,
13942 
                },
13943 
                'reg06_td' => {
13944 
                  'attributes' => {
13945 
                    'bin_pt' => 0,
13946 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
13947 
                    'is_floating_block' => 1,
13948 
                    'is_gateway_port' => 1,
13949 
                    'must_be_hdl_vector' => 1,
13950 
                    'period' => 1,
13951 
                    'port_id' => 0,
13952 
                    'simulinkName' => 'INOUT_LOGIC/reg06_td',
13953 
                    'source_block' => 'INOUT_LOGIC',
13954 
                    'timingConstraint' => 'none',
13955 
                    'type' => 'UFix_32_0',
13956 
                  },
13957 
                  'direction' => 'in',
13958 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13959 
                  'width' => 32,
13960 
                },
13961 
                'reg06_tv' => {
13962 
                  'attributes' => {
13963 
                    'bin_pt' => 0,
13964 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
13965 
                    'is_floating_block' => 1,
13966 
                    'is_gateway_port' => 1,
13967 
                    'must_be_hdl_vector' => 1,
13968 
                    'period' => 1,
13969 
                    'port_id' => 0,
13970 
                    'simulinkName' => 'INOUT_LOGIC/reg06_tv',
13971 
                    'source_block' => 'INOUT_LOGIC',
13972 
                    'timingConstraint' => 'none',
13973 
                    'type' => 'Bool',
13974 
                  },
13975 
                  'direction' => 'in',
13976 
                  'hdlType' => 'std_logic',
13977 
                  'width' => 1,
13978 
                },
13979 
                'reg07_rd' => {
13980 
                  'attributes' => {
13981 
                    'bin_pt' => 0,
13982 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
13983 
                    'is_floating_block' => 1,
13984 
                    'is_gateway_port' => 1,
13985 
                    'must_be_hdl_vector' => 1,
13986 
                    'period' => 1,
13987 
                    'port_id' => 0,
13988 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rd',
13989 
                    'source_block' => 'INOUT_LOGIC',
13990 
                    'timingConstraint' => 'none',
13991 
                    'type' => 'UFix_32_0',
13992 
                  },
13993 
                  'direction' => 'out',
13994 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13995 
                  'width' => 32,
13996 
                },
13997 
                'reg07_rv' => {
13998 
                  'attributes' => {
13999 
                    'bin_pt' => 0,
14000 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
14001 
                    'is_floating_block' => 1,
14002 
                    'is_gateway_port' => 1,
14003 
                    'must_be_hdl_vector' => 1,
14004 
                    'period' => 1,
14005 
                    'port_id' => 0,
14006 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rv',
14007 
                    'source_block' => 'INOUT_LOGIC',
14008 
                    'timingConstraint' => 'none',
14009 
                    'type' => 'UFix_1_0',
14010 
                  },
14011 
                  'direction' => 'out',
14012 
                  'hdlType' => 'std_logic',
14013 
                  'width' => 1,
14014 
                },
14015 
                'reg07_td' => {
14016 
                  'attributes' => {
14017 
                    'bin_pt' => 0,
14018 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
14019 
                    'is_floating_block' => 1,
14020 
                    'is_gateway_port' => 1,
14021 
                    'must_be_hdl_vector' => 1,
14022 
                    'period' => 1,
14023 
                    'port_id' => 0,
14024 
                    'simulinkName' => 'INOUT_LOGIC/reg07_td',
14025 
                    'source_block' => 'INOUT_LOGIC',
14026 
                    'timingConstraint' => 'none',
14027 
                    'type' => 'UFix_32_0',
14028 
                  },
14029 
                  'direction' => 'in',
14030 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14031 
                  'width' => 32,
14032 
                },
14033 
                'reg07_tv' => {
14034 
                  'attributes' => {
14035 
                    'bin_pt' => 0,
14036 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
14037 
                    'is_floating_block' => 1,
14038 
                    'is_gateway_port' => 1,
14039 
                    'must_be_hdl_vector' => 1,
14040 
                    'period' => 1,
14041 
                    'port_id' => 0,
14042 
                    'simulinkName' => 'INOUT_LOGIC/reg07_tv',
14043 
                    'source_block' => 'INOUT_LOGIC',
14044 
                    'timingConstraint' => 'none',
14045 
                    'type' => 'Bool',
14046 
                  },
14047 
                  'direction' => 'in',
14048 
                  'hdlType' => 'std_logic',
14049 
                  'width' => 1,
14050 
                },
14051 
                'reg08_rd' => {
14052 
                  'attributes' => {
14053 
                    'bin_pt' => 0,
14054 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
14055 
                    'is_floating_block' => 1,
14056 
                    'is_gateway_port' => 1,
14057 
                    'must_be_hdl_vector' => 1,
14058 
                    'period' => 1,
14059 
                    'port_id' => 0,
14060 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rd',
14061 
                    'source_block' => 'INOUT_LOGIC',
14062 
                    'timingConstraint' => 'none',
14063 
                    'type' => 'UFix_32_0',
14064 
                  },
14065 
                  'direction' => 'out',
14066 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14067 
                  'width' => 32,
14068 
                },
14069 
                'reg08_rv' => {
14070 
                  'attributes' => {
14071 
                    'bin_pt' => 0,
14072 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
14073 
                    'is_floating_block' => 1,
14074 
                    'is_gateway_port' => 1,
14075 
                    'must_be_hdl_vector' => 1,
14076 
                    'period' => 1,
14077 
                    'port_id' => 0,
14078 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rv',
14079 
                    'source_block' => 'INOUT_LOGIC',
14080 
                    'timingConstraint' => 'none',
14081 
                    'type' => 'UFix_1_0',
14082 
                  },
14083 
                  'direction' => 'out',
14084 
                  'hdlType' => 'std_logic',
14085 
                  'width' => 1,
14086 
                },
14087 
                'reg08_td' => {
14088 
                  'attributes' => {
14089 
                    'bin_pt' => 0,
14090 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
14091 
                    'is_floating_block' => 1,
14092 
                    'is_gateway_port' => 1,
14093 
                    'must_be_hdl_vector' => 1,
14094 
                    'period' => 1,
14095 
                    'port_id' => 0,
14096 
                    'simulinkName' => 'INOUT_LOGIC/reg08_td',
14097 
                    'source_block' => 'INOUT_LOGIC',
14098 
                    'timingConstraint' => 'none',
14099 
                    'type' => 'UFix_32_0',
14100 
                  },
14101 
                  'direction' => 'in',
14102 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14103 
                  'width' => 32,
14104 
                },
14105 
                'reg08_tv' => {
14106 
                  'attributes' => {
14107 
                    'bin_pt' => 0,
14108 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
14109 
                    'is_floating_block' => 1,
14110 
                    'is_gateway_port' => 1,
14111 
                    'must_be_hdl_vector' => 1,
14112 
                    'period' => 1,
14113 
                    'port_id' => 0,
14114 
                    'simulinkName' => 'INOUT_LOGIC/reg08_tv',
14115 
                    'source_block' => 'INOUT_LOGIC',
14116 
                    'timingConstraint' => 'none',
14117 
                    'type' => 'Bool',
14118 
                  },
14119 
                  'direction' => 'in',
14120 
                  'hdlType' => 'std_logic',
14121 
                  'width' => 1,
14122 
                },
14123 
                'reg09_rd' => {
14124 
                  'attributes' => {
14125 
                    'bin_pt' => 0,
14126 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
14127 
                    'is_floating_block' => 1,
14128 
                    'is_gateway_port' => 1,
14129 
                    'must_be_hdl_vector' => 1,
14130 
                    'period' => 1,
14131 
                    'port_id' => 0,
14132 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rd',
14133 
                    'source_block' => 'INOUT_LOGIC',
14134 
                    'timingConstraint' => 'none',
14135 
                    'type' => 'UFix_32_0',
14136 
                  },
14137 
                  'direction' => 'out',
14138 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14139 
                  'width' => 32,
14140 
                },
14141 
                'reg09_rv' => {
14142 
                  'attributes' => {
14143 
                    'bin_pt' => 0,
14144 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
14145 
                    'is_floating_block' => 1,
14146 
                    'is_gateway_port' => 1,
14147 
                    'must_be_hdl_vector' => 1,
14148 
                    'period' => 1,
14149 
                    'port_id' => 0,
14150 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rv',
14151 
                    'source_block' => 'INOUT_LOGIC',
14152 
                    'timingConstraint' => 'none',
14153 
                    'type' => 'UFix_1_0',
14154 
                  },
14155 
                  'direction' => 'out',
14156 
                  'hdlType' => 'std_logic',
14157 
                  'width' => 1,
14158 
                },
14159 
                'reg09_td' => {
14160 
                  'attributes' => {
14161 
                    'bin_pt' => 0,
14162 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
14163 
                    'is_floating_block' => 1,
14164 
                    'is_gateway_port' => 1,
14165 
                    'must_be_hdl_vector' => 1,
14166 
                    'period' => 1,
14167 
                    'port_id' => 0,
14168 
                    'simulinkName' => 'INOUT_LOGIC/reg09_td',
14169 
                    'source_block' => 'INOUT_LOGIC',
14170 
                    'timingConstraint' => 'none',
14171 
                    'type' => 'UFix_32_0',
14172 
                  },
14173 
                  'direction' => 'in',
14174 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14175 
                  'width' => 32,
14176 
                },
14177 
                'reg09_tv' => {
14178 
                  'attributes' => {
14179 
                    'bin_pt' => 0,
14180 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
14181 
                    'is_floating_block' => 1,
14182 
                    'is_gateway_port' => 1,
14183 
                    'must_be_hdl_vector' => 1,
14184 
                    'period' => 1,
14185 
                    'port_id' => 0,
14186 
                    'simulinkName' => 'INOUT_LOGIC/reg09_tv',
14187 
                    'source_block' => 'INOUT_LOGIC',
14188 
                    'timingConstraint' => 'none',
14189 
                    'type' => 'Bool',
14190 
                  },
14191 
                  'direction' => 'in',
14192 
                  'hdlType' => 'std_logic',
14193 
                  'width' => 1,
14194 
                },
14195 
                'reg10_rd' => {
14196 
                  'attributes' => {
14197 
                    'bin_pt' => 0,
14198 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
14199 
                    'is_floating_block' => 1,
14200 
                    'is_gateway_port' => 1,
14201 
                    'must_be_hdl_vector' => 1,
14202 
                    'period' => 1,
14203 
                    'port_id' => 0,
14204 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rd',
14205 
                    'source_block' => 'INOUT_LOGIC',
14206 
                    'timingConstraint' => 'none',
14207 
                    'type' => 'UFix_32_0',
14208 
                  },
14209 
                  'direction' => 'out',
14210 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14211 
                  'width' => 32,
14212 
                },
14213 
                'reg10_rv' => {
14214 
                  'attributes' => {
14215 
                    'bin_pt' => 0,
14216 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
14217 
                    'is_floating_block' => 1,
14218 
                    'is_gateway_port' => 1,
14219 
                    'must_be_hdl_vector' => 1,
14220 
                    'period' => 1,
14221 
                    'port_id' => 0,
14222 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rv',
14223 
                    'source_block' => 'INOUT_LOGIC',
14224 
                    'timingConstraint' => 'none',
14225 
                    'type' => 'UFix_1_0',
14226 
                  },
14227 
                  'direction' => 'out',
14228 
                  'hdlType' => 'std_logic',
14229 
                  'width' => 1,
14230 
                },
14231 
                'reg10_td' => {
14232 
                  'attributes' => {
14233 
                    'bin_pt' => 0,
14234 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
14235 
                    'is_floating_block' => 1,
14236 
                    'is_gateway_port' => 1,
14237 
                    'must_be_hdl_vector' => 1,
14238 
                    'period' => 1,
14239 
                    'port_id' => 0,
14240 
                    'simulinkName' => 'INOUT_LOGIC/reg10_td',
14241 
                    'source_block' => 'INOUT_LOGIC',
14242 
                    'timingConstraint' => 'none',
14243 
                    'type' => 'UFix_32_0',
14244 
                  },
14245 
                  'direction' => 'in',
14246 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14247 
                  'width' => 32,
14248 
                },
14249 
                'reg10_tv' => {
14250 
                  'attributes' => {
14251 
                    'bin_pt' => 0,
14252 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
14253 
                    'is_floating_block' => 1,
14254 
                    'is_gateway_port' => 1,
14255 
                    'must_be_hdl_vector' => 1,
14256 
                    'period' => 1,
14257 
                    'port_id' => 0,
14258 
                    'simulinkName' => 'INOUT_LOGIC/reg10_tv',
14259 
                    'source_block' => 'INOUT_LOGIC',
14260 
                    'timingConstraint' => 'none',
14261 
                    'type' => 'Bool',
14262 
                  },
14263 
                  'direction' => 'in',
14264 
                  'hdlType' => 'std_logic',
14265 
                  'width' => 1,
14266 
                },
14267 
                'reg11_rd' => {
14268 
                  'attributes' => {
14269 
                    'bin_pt' => 0,
14270 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
14271 
                    'is_floating_block' => 1,
14272 
                    'is_gateway_port' => 1,
14273 
                    'must_be_hdl_vector' => 1,
14274 
                    'period' => 1,
14275 
                    'port_id' => 0,
14276 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rd',
14277 
                    'source_block' => 'INOUT_LOGIC',
14278 
                    'timingConstraint' => 'none',
14279 
                    'type' => 'UFix_32_0',
14280 
                  },
14281 
                  'direction' => 'out',
14282 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14283 
                  'width' => 32,
14284 
                },
14285 
                'reg11_rv' => {
14286 
                  'attributes' => {
14287 
                    'bin_pt' => 0,
14288 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
14289 
                    'is_floating_block' => 1,
14290 
                    'is_gateway_port' => 1,
14291 
                    'must_be_hdl_vector' => 1,
14292 
                    'period' => 1,
14293 
                    'port_id' => 0,
14294 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rv',
14295 
                    'source_block' => 'INOUT_LOGIC',
14296 
                    'timingConstraint' => 'none',
14297 
                    'type' => 'UFix_1_0',
14298 
                  },
14299 
                  'direction' => 'out',
14300 
                  'hdlType' => 'std_logic',
14301 
                  'width' => 1,
14302 
                },
14303 
                'reg11_td' => {
14304 
                  'attributes' => {
14305 
                    'bin_pt' => 0,
14306 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
14307 
                    'is_floating_block' => 1,
14308 
                    'is_gateway_port' => 1,
14309 
                    'must_be_hdl_vector' => 1,
14310 
                    'period' => 1,
14311 
                    'port_id' => 0,
14312 
                    'simulinkName' => 'INOUT_LOGIC/reg11_td',
14313 
                    'source_block' => 'INOUT_LOGIC',
14314 
                    'timingConstraint' => 'none',
14315 
                    'type' => 'UFix_32_0',
14316 
                  },
14317 
                  'direction' => 'in',
14318 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14319 
                  'width' => 32,
14320 
                },
14321 
                'reg11_tv' => {
14322 
                  'attributes' => {
14323 
                    'bin_pt' => 0,
14324 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
14325 
                    'is_floating_block' => 1,
14326 
                    'is_gateway_port' => 1,
14327 
                    'must_be_hdl_vector' => 1,
14328 
                    'period' => 1,
14329 
                    'port_id' => 0,
14330 
                    'simulinkName' => 'INOUT_LOGIC/reg11_tv',
14331 
                    'source_block' => 'INOUT_LOGIC',
14332 
                    'timingConstraint' => 'none',
14333 
                    'type' => 'Bool',
14334 
                  },
14335 
                  'direction' => 'in',
14336 
                  'hdlType' => 'std_logic',
14337 
                  'width' => 1,
14338 
                },
14339 
                'reg12_rd' => {
14340 
                  'attributes' => {
14341 
                    'bin_pt' => 0,
14342 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
14343 
                    'is_floating_block' => 1,
14344 
                    'is_gateway_port' => 1,
14345 
                    'must_be_hdl_vector' => 1,
14346 
                    'period' => 1,
14347 
                    'port_id' => 0,
14348 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rd',
14349 
                    'source_block' => 'INOUT_LOGIC',
14350 
                    'timingConstraint' => 'none',
14351 
                    'type' => 'UFix_32_0',
14352 
                  },
14353 
                  'direction' => 'out',
14354 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14355 
                  'width' => 32,
14356 
                },
14357 
                'reg12_rv' => {
14358 
                  'attributes' => {
14359 
                    'bin_pt' => 0,
14360 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
14361 
                    'is_floating_block' => 1,
14362 
                    'is_gateway_port' => 1,
14363 
                    'must_be_hdl_vector' => 1,
14364 
                    'period' => 1,
14365 
                    'port_id' => 0,
14366 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rv',
14367 
                    'source_block' => 'INOUT_LOGIC',
14368 
                    'timingConstraint' => 'none',
14369 
                    'type' => 'UFix_1_0',
14370 
                  },
14371 
                  'direction' => 'out',
14372 
                  'hdlType' => 'std_logic',
14373 
                  'width' => 1,
14374 
                },
14375 
                'reg12_td' => {
14376 
                  'attributes' => {
14377 
                    'bin_pt' => 0,
14378 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
14379 
                    'is_floating_block' => 1,
14380 
                    'is_gateway_port' => 1,
14381 
                    'must_be_hdl_vector' => 1,
14382 
                    'period' => 1,
14383 
                    'port_id' => 0,
14384 
                    'simulinkName' => 'INOUT_LOGIC/reg12_td',
14385 
                    'source_block' => 'INOUT_LOGIC',
14386 
                    'timingConstraint' => 'none',
14387 
                    'type' => 'UFix_32_0',
14388 
                  },
14389 
                  'direction' => 'in',
14390 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14391 
                  'width' => 32,
14392 
                },
14393 
                'reg12_tv' => {
14394 
                  'attributes' => {
14395 
                    'bin_pt' => 0,
14396 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
14397 
                    'is_floating_block' => 1,
14398 
                    'is_gateway_port' => 1,
14399 
                    'must_be_hdl_vector' => 1,
14400 
                    'period' => 1,
14401 
                    'port_id' => 0,
14402 
                    'simulinkName' => 'INOUT_LOGIC/reg12_tv',
14403 
                    'source_block' => 'INOUT_LOGIC',
14404 
                    'timingConstraint' => 'none',
14405 
                    'type' => 'Bool',
14406 
                  },
14407 
                  'direction' => 'in',
14408 
                  'hdlType' => 'std_logic',
14409 
                  'width' => 1,
14410 
                },
14411 
                'reg13_rd' => {
14412 
                  'attributes' => {
14413 
                    'bin_pt' => 0,
14414 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
14415 
                    'is_floating_block' => 1,
14416 
                    'is_gateway_port' => 1,
14417 
                    'must_be_hdl_vector' => 1,
14418 
                    'period' => 1,
14419 
                    'port_id' => 0,
14420 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rd',
14421 
                    'source_block' => 'INOUT_LOGIC',
14422 
                    'timingConstraint' => 'none',
14423 
                    'type' => 'UFix_32_0',
14424 
                  },
14425 
                  'direction' => 'out',
14426 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14427 
                  'width' => 32,
14428 
                },
14429 
                'reg13_rv' => {
14430 
                  'attributes' => {
14431 
                    'bin_pt' => 0,
14432 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
14433 
                    'is_floating_block' => 1,
14434 
                    'is_gateway_port' => 1,
14435 
                    'must_be_hdl_vector' => 1,
14436 
                    'period' => 1,
14437 
                    'port_id' => 0,
14438 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rv',
14439 
                    'source_block' => 'INOUT_LOGIC',
14440 
                    'timingConstraint' => 'none',
14441 
                    'type' => 'UFix_1_0',
14442 
                  },
14443 
                  'direction' => 'out',
14444 
                  'hdlType' => 'std_logic',
14445 
                  'width' => 1,
14446 
                },
14447 
                'reg13_td' => {
14448 
                  'attributes' => {
14449 
                    'bin_pt' => 0,
14450 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
14451 
                    'is_floating_block' => 1,
14452 
                    'is_gateway_port' => 1,
14453 
                    'must_be_hdl_vector' => 1,
14454 
                    'period' => 1,
14455 
                    'port_id' => 0,
14456 
                    'simulinkName' => 'INOUT_LOGIC/reg13_td',
14457 
                    'source_block' => 'INOUT_LOGIC',
14458 
                    'timingConstraint' => 'none',
14459 
                    'type' => 'UFix_32_0',
14460 
                  },
14461 
                  'direction' => 'in',
14462 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14463 
                  'width' => 32,
14464 
                },
14465 
                'reg13_tv' => {
14466 
                  'attributes' => {
14467 
                    'bin_pt' => 0,
14468 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
14469 
                    'is_floating_block' => 1,
14470 
                    'is_gateway_port' => 1,
14471 
                    'must_be_hdl_vector' => 1,
14472 
                    'period' => 1,
14473 
                    'port_id' => 0,
14474 
                    'simulinkName' => 'INOUT_LOGIC/reg13_tv',
14475 
                    'source_block' => 'INOUT_LOGIC',
14476 
                    'timingConstraint' => 'none',
14477 
                    'type' => 'Bool',
14478 
                  },
14479 
                  'direction' => 'in',
14480 
                  'hdlType' => 'std_logic',
14481 
                  'width' => 1,
14482 
                },
14483 
                'reg14_rd' => {
14484 
                  'attributes' => {
14485 
                    'bin_pt' => 0,
14486 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
14487 
                    'is_floating_block' => 1,
14488 
                    'is_gateway_port' => 1,
14489 
                    'must_be_hdl_vector' => 1,
14490 
                    'period' => 1,
14491 
                    'port_id' => 0,
14492 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rd',
14493 
                    'source_block' => 'INOUT_LOGIC',
14494 
                    'timingConstraint' => 'none',
14495 
                    'type' => 'UFix_32_0',
14496 
                  },
14497 
                  'direction' => 'out',
14498 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14499 
                  'width' => 32,
14500 
                },
14501 
                'reg14_rv' => {
14502 
                  'attributes' => {
14503 
                    'bin_pt' => 0,
14504 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
14505 
                    'is_floating_block' => 1,
14506 
                    'is_gateway_port' => 1,
14507 
                    'must_be_hdl_vector' => 1,
14508 
                    'period' => 1,
14509 
                    'port_id' => 0,
14510 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rv',
14511 
                    'source_block' => 'INOUT_LOGIC',
14512 
                    'timingConstraint' => 'none',
14513 
                    'type' => 'UFix_1_0',
14514 
                  },
14515 
                  'direction' => 'out',
14516 
                  'hdlType' => 'std_logic',
14517 
                  'width' => 1,
14518 
                },
14519 
                'reg14_td' => {
14520 
                  'attributes' => {
14521 
                    'bin_pt' => 0,
14522 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
14523 
                    'is_floating_block' => 1,
14524 
                    'is_gateway_port' => 1,
14525 
                    'must_be_hdl_vector' => 1,
14526 
                    'period' => 1,
14527 
                    'port_id' => 0,
14528 
                    'simulinkName' => 'INOUT_LOGIC/reg14_td',
14529 
                    'source_block' => 'INOUT_LOGIC',
14530 
                    'timingConstraint' => 'none',
14531 
                    'type' => 'UFix_32_0',
14532 
                  },
14533 
                  'direction' => 'in',
14534 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14535 
                  'width' => 32,
14536 
                },
14537 
                'reg14_tv' => {
14538 
                  'attributes' => {
14539 
                    'bin_pt' => 0,
14540 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
14541 
                    'is_floating_block' => 1,
14542 
                    'is_gateway_port' => 1,
14543 
                    'must_be_hdl_vector' => 1,
14544 
                    'period' => 1,
14545 
                    'port_id' => 0,
14546 
                    'simulinkName' => 'INOUT_LOGIC/reg14_tv',
14547 
                    'source_block' => 'INOUT_LOGIC',
14548 
                    'timingConstraint' => 'none',
14549 
                    'type' => 'Bool',
14550 
                  },
14551 
                  'direction' => 'in',
14552 
                  'hdlType' => 'std_logic',
14553 
                  'width' => 1,
14554 
                },
14555 
              },
14556 
            },
14557 
            'entityName' => 'inout_logic',
14558 
          },
14559 
          'persistentdff_inst' => {
14560 
            'connections' => {
14561 
              'clk' => 'clkNet',
14562 
              'd' => 'persistentdff_inst_q',
14563 
              'q' => 'persistentdff_inst_q',
14564 
            },
14565 
            'entity' => {
14566 
              'attributes' => {
14567 
                'entityAlreadyNetlisted' => 1,
14568 
                'hdlCompAttributes' => [
14569 
                  [
14570 
                    'syn_black_box',
14571 
                    'boolean',
14572 
                    'true',
14573 
                  ],
14574 
                  [
14575 
                    'box_type',
14576 
                    'string',
14577 
                    '"black_box"',
14578 
                  ],
14579 
                ],
14580 
                'is_persistent_dff' => 1,
14581 
                'needsComponentDeclaration' => 1,
14582 
              },
14583 
              'entityName' => 'xlpersistentdff',
14584 
              'ports' => {
14585 
                'clk' => {
14586 
                  'direction' => 'in',
14587 
                  'hdlType' => 'std_logic',
14588 
                  'width' => 1,
14589 
                },
14590 
                'd' => {
14591 
                  'direction' => 'in',
14592 
                  'hdlType' => 'std_logic',
14593 
                  'width' => 1,
14594 
                },
14595 
                'q' => {
14596 
                  'direction' => 'out',
14597 
                  'hdlType' => 'std_logic',
14598 
                  'width' => 1,
14599 
                },
14600 
              },
14601 
            },
14602 
            'entityName' => 'xlpersistentdff',
14603 
          },
14604 
        },
14605 
      },
14606 
      'entityName' => 'inout_logic_cw',
14607 
    },
14608 
    'sysgen_gw_clk' => {
14609 
      'connections' => {
14610 
        'clk' => '.clk',
14611 
      },
14612 
      'entity' => {
14613 
        'attributes' => {
14614 
          'entityAlreadyNetlisted' => 1,
14615 
          'isClk' => 1,
14616 
          'isGateway' => 1,
14617 
          'is_floating_block' => 1,
14618 
        },
14619 
        'entityName' => 'sysgen_gw_clk',
14620 
        'ports' => {
14621 
          'clk' => {
14622 
            'attributes' => {
14623 
              'isClk' => 1,
14624 
            },
14625 
            'direction' => 'out',
14626 
            'hdlType' => 'std_logic',
14627 
            'width' => 1,
14628 
          },
14629 
        },
14630 
      },
14631 
      'entityName' => 'sysgen_gw_clk',
14632 
    },
14633 
    'to_register1' => {
14634 
      'connections' => {
14635 
        'ce' => 'sysgen_dut.to_register1_ce',
14636 
        'clk' => 'sysgen_dut.to_register1_clk',
14637 
        'clr' => 'sysgen_dut.to_register1_clr',
14638 
        'data_in' => 'sysgen_dut.to_register1_data_in',
14639 
        'dout' => 'to_register1.dout',
14640 
        'en' => 'sysgen_dut.to_register1_en',
14641 
      },
14642 
      'entity' => {
14643 
        'attributes' => {
14644 
          'entityAlreadyNetlisted' => 1,
14645 
          'generics' => [
14646 
          ],
14647 
          'is_floating_block' => 1,
14648 
          'mask' => {
14649 
            'Block_Handle' => 38.0009765625,
14650 
            'Block_handle' => 38.0009765625,
14651 
            'MDL_Handle' => 3.0009765625,
14652 
            'MDL_handle' => 3.0009765625,
14653 
            'arith_type' => 1,
14654 
            'bin_pt' => 14,
14655 
            'block_config' => 'sysgen_blockset:toreg_config',
14656 
            'block_handle' => 38.0009765625,
14657 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14658 
            'block_type' => 'toreg',
14659 
            'dbl_ovrd' => 0,
14660 
            'explicit_data_type' => 0,
14661 
            'init' => 0,
14662 
            'init_bit_vector' => '00000000000000000000000000000000b',
14663 
            'mdl_handle' => 3.0009765625,
14664 
            'model_handle' => 3.0009765625,
14665 
            'n_bits' => 16,
14666 
            'ownership' => 1,
14667 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14668 
            'shared_memory_name' => 'debug2i',
14669 
          },
14670 
          'needs_vhdl_wrapper' => 0,
14671 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14672 
        },
14673 
        'entityName' => 'x',
14674 
        'ports' => {
14675 
          'ce' => {
14676 
            'attributes' => {
14677 
              'domain' => '',
14678 
              'group' => 1,
14679 
              'isCe' => 1,
14680 
              'is_floating_block' => 1,
14681 
              'period' => 1,
14682 
              'type' => 'logic',
14683 
            },
14684 
            'direction' => 'in',
14685 
            'hdlType' => 'std_logic',
14686 
            'width' => 1,
14687 
          },
14688 
          'clk' => {
14689 
            'attributes' => {
14690 
              'domain' => '',
14691 
              'group' => 1,
14692 
              'isClk' => 1,
14693 
              'is_floating_block' => 1,
14694 
              'period' => 1,
14695 
              'type' => 'logic',
14696 
            },
14697 
            'direction' => 'in',
14698 
            'hdlType' => 'std_logic',
14699 
            'width' => 1,
14700 
          },
14701 
          'clr' => {
14702 
            'attributes' => {
14703 
              'domain' => '',
14704 
              'group' => 1,
14705 
              'isClr' => 1,
14706 
              'is_floating_block' => 1,
14707 
              'period' => 1,
14708 
              'type' => 'logic',
14709 
              'valid_bit_used' => 0,
14710 
            },
14711 
            'direction' => 'in',
14712 
            'hdlType' => 'std_logic',
14713 
            'width' => 1,
14714 
          },
14715 
          'data_in' => {
14716 
            'attributes' => {
14717 
              'bin_pt' => 0,
14718 
              'is_floating_block' => 1,
14719 
              'must_be_hdl_vector' => 1,
14720 
              'period' => 1,
14721 
              'port_id' => 0,
14722 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
14723 
              'type' => 'UFix_32_0',
14724 
            },
14725 
            'direction' => 'in',
14726 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14727 
            'width' => 32,
14728 
          },
14729 
          'dout' => {
14730 
            'attributes' => {
14731 
              'bin_pt' => 0,
14732 
              'is_floating_block' => 1,
14733 
              'must_be_hdl_vector' => 1,
14734 
              'period' => 1,
14735 
              'port_id' => 0,
14736 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
14737 
              'type' => 'UFix_32_0',
14738 
            },
14739 
            'direction' => 'out',
14740 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14741 
            'width' => 32,
14742 
          },
14743 
          'en' => {
14744 
            'attributes' => {
14745 
              'bin_pt' => 0,
14746 
              'is_floating_block' => 1,
14747 
              'must_be_hdl_vector' => 1,
14748 
              'period' => 1,
14749 
              'port_id' => 1,
14750 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
14751 
              'type' => 'Bool',
14752 
            },
14753 
            'direction' => 'in',
14754 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14755 
            'width' => 1,
14756 
          },
14757 
        },
14758 
      },
14759 
      'entityName' => 'x',
14760 
    },
14761 
    'to_register10' => {
14762 
      'connections' => {
14763 
        'ce' => 'sysgen_dut.to_register10_ce',
14764 
        'clk' => 'sysgen_dut.to_register10_clk',
14765 
        'clr' => 'sysgen_dut.to_register10_clr',
14766 
        'data_in' => 'sysgen_dut.to_register10_data_in',
14767 
        'dout' => 'to_register10.dout',
14768 
        'en' => 'sysgen_dut.to_register10_en',
14769 
      },
14770 
      'entity' => {
14771 
        'attributes' => {
14772 
          'entityAlreadyNetlisted' => 1,
14773 
          'generics' => [
14774 
          ],
14775 
          'is_floating_block' => 1,
14776 
          'mask' => {
14777 
            'Block_Handle' => 39.0009765625,
14778 
            'Block_handle' => 39.0009765625,
14779 
            'MDL_Handle' => 3.0009765625,
14780 
            'MDL_handle' => 3.0009765625,
14781 
            'arith_type' => 1,
14782 
            'bin_pt' => 14,
14783 
            'block_config' => 'sysgen_blockset:toreg_config',
14784 
            'block_handle' => 39.0009765625,
14785 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14786 
            'block_type' => 'toreg',
14787 
            'dbl_ovrd' => 0,
14788 
            'explicit_data_type' => 0,
14789 
            'init' => 0,
14790 
            'init_bit_vector' => '0b',
14791 
            'mdl_handle' => 3.0009765625,
14792 
            'model_handle' => 3.0009765625,
14793 
            'n_bits' => 16,
14794 
            'ownership' => 1,
14795 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14796 
            'shared_memory_name' => 'register04tv',
14797 
          },
14798 
          'needs_vhdl_wrapper' => 0,
14799 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14800 
        },
14801 
        'entityName' => 'x_x0',
14802 
        'ports' => {
14803 
          'ce' => {
14804 
            'attributes' => {
14805 
              'domain' => '',
14806 
              'group' => 1,
14807 
              'isCe' => 1,
14808 
              'is_floating_block' => 1,
14809 
              'period' => 1,
14810 
              'type' => 'logic',
14811 
            },
14812 
            'direction' => 'in',
14813 
            'hdlType' => 'std_logic',
14814 
            'width' => 1,
14815 
          },
14816 
          'clk' => {
14817 
            'attributes' => {
14818 
              'domain' => '',
14819 
              'group' => 1,
14820 
              'isClk' => 1,
14821 
              'is_floating_block' => 1,
14822 
              'period' => 1,
14823 
              'type' => 'logic',
14824 
            },
14825 
            'direction' => 'in',
14826 
            'hdlType' => 'std_logic',
14827 
            'width' => 1,
14828 
          },
14829 
          'clr' => {
14830 
            'attributes' => {
14831 
              'domain' => '',
14832 
              'group' => 1,
14833 
              'isClr' => 1,
14834 
              'is_floating_block' => 1,
14835 
              'period' => 1,
14836 
              'type' => 'logic',
14837 
              'valid_bit_used' => 0,
14838 
            },
14839 
            'direction' => 'in',
14840 
            'hdlType' => 'std_logic',
14841 
            'width' => 1,
14842 
          },
14843 
          'data_in' => {
14844 
            'attributes' => {
14845 
              'bin_pt' => 0,
14846 
              'is_floating_block' => 1,
14847 
              'must_be_hdl_vector' => 1,
14848 
              'period' => 1,
14849 
              'port_id' => 0,
14850 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
14851 
              'type' => 'Bool',
14852 
            },
14853 
            'direction' => 'in',
14854 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14855 
            'width' => 1,
14856 
          },
14857 
          'dout' => {
14858 
            'attributes' => {
14859 
              'bin_pt' => 0,
14860 
              'is_floating_block' => 1,
14861 
              'must_be_hdl_vector' => 1,
14862 
              'period' => 1,
14863 
              'port_id' => 0,
14864 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
14865 
              'type' => 'Bool',
14866 
            },
14867 
            'direction' => 'out',
14868 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14869 
            'width' => 1,
14870 
          },
14871 
          'en' => {
14872 
            'attributes' => {
14873 
              'bin_pt' => 0,
14874 
              'is_floating_block' => 1,
14875 
              'must_be_hdl_vector' => 1,
14876 
              'period' => 1,
14877 
              'port_id' => 1,
14878 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
14879 
              'type' => 'Bool',
14880 
            },
14881 
            'direction' => 'in',
14882 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14883 
            'width' => 1,
14884 
          },
14885 
        },
14886 
      },
14887 
      'entityName' => 'x_x0',
14888 
    },
14889 
    'to_register11' => {
14890 
      'connections' => {
14891 
        'ce' => 'sysgen_dut.to_register11_ce',
14892 
        'clk' => 'sysgen_dut.to_register11_clk',
14893 
        'clr' => 'sysgen_dut.to_register11_clr',
14894 
        'data_in' => 'sysgen_dut.to_register11_data_in',
14895 
        'dout' => 'to_register11.dout',
14896 
        'en' => 'sysgen_dut.to_register11_en',
14897 
      },
14898 
      'entity' => {
14899 
        'attributes' => {
14900 
          'entityAlreadyNetlisted' => 1,
14901 
          'generics' => [
14902 
          ],
14903 
          'is_floating_block' => 1,
14904 
          'mask' => {
14905 
            'Block_Handle' => 40.0009765625,
14906 
            'Block_handle' => 40.0009765625,
14907 
            'MDL_Handle' => 3.0009765625,
14908 
            'MDL_handle' => 3.0009765625,
14909 
            'arith_type' => 1,
14910 
            'bin_pt' => 14,
14911 
            'block_config' => 'sysgen_blockset:toreg_config',
14912 
            'block_handle' => 40.0009765625,
14913 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14914 
            'block_type' => 'toreg',
14915 
            'dbl_ovrd' => 0,
14916 
            'explicit_data_type' => 0,
14917 
            'init' => 0,
14918 
            'init_bit_vector' => '00000000000000000000000000000000b',
14919 
            'mdl_handle' => 3.0009765625,
14920 
            'model_handle' => 3.0009765625,
14921 
            'n_bits' => 16,
14922 
            'ownership' => 1,
14923 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14924 
            'shared_memory_name' => 'register04td',
14925 
          },
14926 
          'needs_vhdl_wrapper' => 0,
14927 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14928 
        },
14929 
        'entityName' => 'x_x1',
14930 
        'ports' => {
14931 
          'ce' => {
14932 
            'attributes' => {
14933 
              'domain' => '',
14934 
              'group' => 1,
14935 
              'isCe' => 1,
14936 
              'is_floating_block' => 1,
14937 
              'period' => 1,
14938 
              'type' => 'logic',
14939 
            },
14940 
            'direction' => 'in',
14941 
            'hdlType' => 'std_logic',
14942 
            'width' => 1,
14943 
          },
14944 
          'clk' => {
14945 
            'attributes' => {
14946 
              'domain' => '',
14947 
              'group' => 1,
14948 
              'isClk' => 1,
14949 
              'is_floating_block' => 1,
14950 
              'period' => 1,
14951 
              'type' => 'logic',
14952 
            },
14953 
            'direction' => 'in',
14954 
            'hdlType' => 'std_logic',
14955 
            'width' => 1,
14956 
          },
14957 
          'clr' => {
14958 
            'attributes' => {
14959 
              'domain' => '',
14960 
              'group' => 1,
14961 
              'isClr' => 1,
14962 
              'is_floating_block' => 1,
14963 
              'period' => 1,
14964 
              'type' => 'logic',
14965 
              'valid_bit_used' => 0,
14966 
            },
14967 
            'direction' => 'in',
14968 
            'hdlType' => 'std_logic',
14969 
            'width' => 1,
14970 
          },
14971 
          'data_in' => {
14972 
            'attributes' => {
14973 
              'bin_pt' => 0,
14974 
              'is_floating_block' => 1,
14975 
              'must_be_hdl_vector' => 1,
14976 
              'period' => 1,
14977 
              'port_id' => 0,
14978 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
14979 
              'type' => 'UFix_32_0',
14980 
            },
14981 
            'direction' => 'in',
14982 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14983 
            'width' => 32,
14984 
          },
14985 
          'dout' => {
14986 
            'attributes' => {
14987 
              'bin_pt' => 0,
14988 
              'is_floating_block' => 1,
14989 
              'must_be_hdl_vector' => 1,
14990 
              'period' => 1,
14991 
              'port_id' => 0,
14992 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
14993 
              'type' => 'UFix_32_0',
14994 
            },
14995 
            'direction' => 'out',
14996 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14997 
            'width' => 32,
14998 
          },
14999 
          'en' => {
15000 
            'attributes' => {
15001 
              'bin_pt' => 0,
15002 
              'is_floating_block' => 1,
15003 
              'must_be_hdl_vector' => 1,
15004 
              'period' => 1,
15005 
              'port_id' => 1,
15006 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
15007 
              'type' => 'Bool',
15008 
            },
15009 
            'direction' => 'in',
15010 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15011 
            'width' => 1,
15012 
          },
15013 
        },
15014 
      },
15015 
      'entityName' => 'x_x1',
15016 
    },
15017 
    'to_register12' => {
15018 
      'connections' => {
15019 
        'ce' => 'sysgen_dut.to_register12_ce',
15020 
        'clk' => 'sysgen_dut.to_register12_clk',
15021 
        'clr' => 'sysgen_dut.to_register12_clr',
15022 
        'data_in' => 'sysgen_dut.to_register12_data_in',
15023 
        'dout' => 'to_register12.dout',
15024 
        'en' => 'sysgen_dut.to_register12_en',
15025 
      },
15026 
      'entity' => {
15027 
        'attributes' => {
15028 
          'entityAlreadyNetlisted' => 1,
15029 
          'generics' => [
15030 
          ],
15031 
          'is_floating_block' => 1,
15032 
          'mask' => {
15033 
            'Block_Handle' => 41.0009765625,
15034 
            'Block_handle' => 41.0009765625,
15035 
            'MDL_Handle' => 3.0009765625,
15036 
            'MDL_handle' => 3.0009765625,
15037 
            'arith_type' => 1,
15038 
            'bin_pt' => 14,
15039 
            'block_config' => 'sysgen_blockset:toreg_config',
15040 
            'block_handle' => 41.0009765625,
15041 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
15042 
            'block_type' => 'toreg',
15043 
            'dbl_ovrd' => 0,
15044 
            'explicit_data_type' => 0,
15045 
            'init' => 0,
15046 
            'init_bit_vector' => '0b',
15047 
            'mdl_handle' => 3.0009765625,
15048 
            'model_handle' => 3.0009765625,
15049 
            'n_bits' => 16,
15050 
            'ownership' => 1,
15051 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15052 
            'shared_memory_name' => 'register05tv',
15053 
          },
15054 
          'needs_vhdl_wrapper' => 0,
15055 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
15056 
        },
15057 
        'entityName' => 'x_x2',
15058 
        'ports' => {
15059 
          'ce' => {
15060 
            'attributes' => {
15061 
              'domain' => '',
15062 
              'group' => 1,
15063 
              'isCe' => 1,
15064 
              'is_floating_block' => 1,
15065 
              'period' => 1,
15066 
              'type' => 'logic',
15067 
            },
15068 
            'direction' => 'in',
15069 
            'hdlType' => 'std_logic',
15070 
            'width' => 1,
15071 
          },
15072 
          'clk' => {
15073 
            'attributes' => {
15074 
              'domain' => '',
15075 
              'group' => 1,
15076 
              'isClk' => 1,
15077 
              'is_floating_block' => 1,
15078 
              'period' => 1,
15079 
              'type' => 'logic',
15080 
            },
15081 
            'direction' => 'in',
15082 
            'hdlType' => 'std_logic',
15083 
            'width' => 1,
15084 
          },
15085 
          'clr' => {
15086 
            'attributes' => {
15087 
              'domain' => '',
15088 
              'group' => 1,
15089 
              'isClr' => 1,
15090 
              'is_floating_block' => 1,
15091 
              'period' => 1,
15092 
              'type' => 'logic',
15093 
              'valid_bit_used' => 0,
15094 
            },
15095 
            'direction' => 'in',
15096 
            'hdlType' => 'std_logic',
15097 
            'width' => 1,
15098 
          },
15099 
          'data_in' => {
15100 
            'attributes' => {
15101 
              'bin_pt' => 0,
15102 
              'is_floating_block' => 1,
15103 
              'must_be_hdl_vector' => 1,
15104 
              'period' => 1,
15105 
              'port_id' => 0,
15106 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
15107 
              'type' => 'Bool',
15108 
            },
15109 
            'direction' => 'in',
15110 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15111 
            'width' => 1,
15112 
          },
15113 
          'dout' => {
15114 
            'attributes' => {
15115 
              'bin_pt' => 0,
15116 
              'is_floating_block' => 1,
15117 
              'must_be_hdl_vector' => 1,
15118 
              'period' => 1,
15119 
              'port_id' => 0,
15120 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
15121 
              'type' => 'Bool',
15122 
            },
15123 
            'direction' => 'out',
15124 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15125 
            'width' => 1,
15126 
          },
15127 
          'en' => {
15128 
            'attributes' => {
15129 
              'bin_pt' => 0,
15130 
              'is_floating_block' => 1,
15131 
              'must_be_hdl_vector' => 1,
15132 
              'period' => 1,
15133 
              'port_id' => 1,
15134 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
15135 
              'type' => 'Bool',
15136 
            },
15137 
            'direction' => 'in',
15138 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15139 
            'width' => 1,
15140 
          },
15141 
        },
15142 
      },
15143 
      'entityName' => 'x_x2',
15144 
    },
15145 
    'to_register13' => {
15146 
      'connections' => {
15147 
        'ce' => 'sysgen_dut.to_register13_ce',
15148 
        'clk' => 'sysgen_dut.to_register13_clk',
15149 
        'clr' => 'sysgen_dut.to_register13_clr',
15150 
        'data_in' => 'sysgen_dut.to_register13_data_in',
15151 
        'dout' => 'to_register13.dout',
15152 
        'en' => 'sysgen_dut.to_register13_en',
15153 
      },
15154 
      'entity' => {
15155 
        'attributes' => {
15156 
          'entityAlreadyNetlisted' => 1,
15157 
          'generics' => [
15158 
          ],
15159 
          'is_floating_block' => 1,
15160 
          'mask' => {
15161 
            'Block_Handle' => 42.0009765625,
15162 
            'Block_handle' => 42.0009765625,
15163 
            'MDL_Handle' => 3.0009765625,
15164 
            'MDL_handle' => 3.0009765625,
15165 
            'arith_type' => 1,
15166 
            'bin_pt' => 14,
15167 
            'block_config' => 'sysgen_blockset:toreg_config',
15168 
            'block_handle' => 42.0009765625,
15169 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
15170 
            'block_type' => 'toreg',
15171 
            'dbl_ovrd' => 0,
15172 
            'explicit_data_type' => 0,
15173 
            'init' => 0,
15174 
            'init_bit_vector' => '00000000000000000000000000000000b',
15175 
            'mdl_handle' => 3.0009765625,
15176 
            'model_handle' => 3.0009765625,
15177 
            'n_bits' => 16,
15178 
            'ownership' => 1,
15179 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15180 
            'shared_memory_name' => 'register05td',
15181 
          },
15182 
          'needs_vhdl_wrapper' => 0,
15183 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
15184 
        },
15185 
        'entityName' => 'x_x3',
15186 
        'ports' => {
15187 
          'ce' => {
15188 
            'attributes' => {
15189 
              'domain' => '',
15190 
              'group' => 1,
15191 
              'isCe' => 1,
15192 
              'is_floating_block' => 1,
15193 
              'period' => 1,
15194 
              'type' => 'logic',
15195 
            },
15196 
            'direction' => 'in',
15197 
            'hdlType' => 'std_logic',
15198 
            'width' => 1,
15199 
          },
15200 
          'clk' => {
15201 
            'attributes' => {
15202 
              'domain' => '',
15203 
              'group' => 1,
15204 
              'isClk' => 1,
15205 
              'is_floating_block' => 1,
15206 
              'period' => 1,
15207 
              'type' => 'logic',
15208 
            },
15209 
            'direction' => 'in',
15210 
            'hdlType' => 'std_logic',
15211 
            'width' => 1,
15212 
          },
15213 
          'clr' => {
15214 
            'attributes' => {
15215 
              'domain' => '',
15216 
              'group' => 1,
15217 
              'isClr' => 1,
15218 
              'is_floating_block' => 1,
15219 
              'period' => 1,
15220 
              'type' => 'logic',
15221 
              'valid_bit_used' => 0,
15222 
            },
15223 
            'direction' => 'in',
15224 
            'hdlType' => 'std_logic',
15225 
            'width' => 1,
15226 
          },
15227 
          'data_in' => {
15228 
            'attributes' => {
15229 
              'bin_pt' => 0,
15230 
              'is_floating_block' => 1,
15231 
              'must_be_hdl_vector' => 1,
15232 
              'period' => 1,
15233 
              'port_id' => 0,
15234 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
15235 
              'type' => 'UFix_32_0',
15236 
            },
15237 
            'direction' => 'in',
15238 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15239 
            'width' => 32,
15240 
          },
15241 
          'dout' => {
15242 
            'attributes' => {
15243 
              'bin_pt' => 0,
15244 
              'is_floating_block' => 1,
15245 
              'must_be_hdl_vector' => 1,
15246 
              'period' => 1,
15247 
              'port_id' => 0,
15248 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
15249 
              'type' => 'UFix_32_0',
15250 
            },
15251 
            'direction' => 'out',
15252 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15253 
            'width' => 32,
15254 
          },
15255 
          'en' => {
15256 
            'attributes' => {
15257 
              'bin_pt' => 0,
15258 
              'is_floating_block' => 1,
15259 
              'must_be_hdl_vector' => 1,
15260 
              'period' => 1,
15261 
              'port_id' => 1,
15262 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
15263 
              'type' => 'Bool',
15264 
            },
15265 
            'direction' => 'in',
15266 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15267 
            'width' => 1,
15268 
          },
15269 
        },
15270 
      },
15271 
      'entityName' => 'x_x3',
15272 
    },
15273 
    'to_register14' => {
15274 
      'connections' => {
15275 
        'ce' => 'sysgen_dut.to_register14_ce',
15276 
        'clk' => 'sysgen_dut.to_register14_clk',
15277 
        'clr' => 'sysgen_dut.to_register14_clr',
15278 
        'data_in' => 'sysgen_dut.to_register14_data_in',
15279 
        'dout' => 'to_register14.dout',
15280 
        'en' => 'sysgen_dut.to_register14_en',
15281 
      },
15282 
      'entity' => {
15283 
        'attributes' => {
15284 
          'entityAlreadyNetlisted' => 1,
15285 
          'generics' => [
15286 
          ],
15287 
          'is_floating_block' => 1,
15288 
          'mask' => {
15289 
            'Block_Handle' => 43.0009765625,
15290 
            'Block_handle' => 43.0009765625,
15291 
            'MDL_Handle' => 3.0009765625,
15292 
            'MDL_handle' => 3.0009765625,
15293 
            'arith_type' => 1,
15294 
            'bin_pt' => 14,
15295 
            'block_config' => 'sysgen_blockset:toreg_config',
15296 
            'block_handle' => 43.0009765625,
15297 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
15298 
            'block_type' => 'toreg',
15299 
            'dbl_ovrd' => 0,
15300 
            'explicit_data_type' => 0,
15301 
            'init' => 0,
15302 
            'init_bit_vector' => '0b',
15303 
            'mdl_handle' => 3.0009765625,
15304 
            'model_handle' => 3.0009765625,
15305 
            'n_bits' => 16,
15306 
            'ownership' => 1,
15307 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15308 
            'shared_memory_name' => 'register06tv',
15309 
          },
15310 
          'needs_vhdl_wrapper' => 0,
15311 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
15312 
        },
15313 
        'entityName' => 'x_x4',
15314 
        'ports' => {
15315 
          'ce' => {
15316 
            'attributes' => {
15317 
              'domain' => '',
15318 
              'group' => 1,
15319 
              'isCe' => 1,
15320 
              'is_floating_block' => 1,
15321 
              'period' => 1,
15322 
              'type' => 'logic',
15323 
            },
15324 
            'direction' => 'in',
15325 
            'hdlType' => 'std_logic',
15326 
            'width' => 1,
15327 
          },
15328 
          'clk' => {
15329 
            'attributes' => {
15330 
              'domain' => '',
15331 
              'group' => 1,
15332 
              'isClk' => 1,
15333 
              'is_floating_block' => 1,
15334 
              'period' => 1,
15335 
              'type' => 'logic',
15336 
            },
15337 
            'direction' => 'in',
15338 
            'hdlType' => 'std_logic',
15339 
            'width' => 1,
15340 
          },
15341 
          'clr' => {
15342 
            'attributes' => {
15343 
              'domain' => '',
15344 
              'group' => 1,
15345 
              'isClr' => 1,
15346 
              'is_floating_block' => 1,
15347 
              'period' => 1,
15348 
              'type' => 'logic',
15349 
              'valid_bit_used' => 0,
15350 
            },
15351 
            'direction' => 'in',
15352 
            'hdlType' => 'std_logic',
15353 
            'width' => 1,
15354 
          },
15355 
          'data_in' => {
15356 
            'attributes' => {
15357 
              'bin_pt' => 0,
15358 
              'is_floating_block' => 1,
15359 
              'must_be_hdl_vector' => 1,
15360 
              'period' => 1,
15361 
              'port_id' => 0,
15362 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
15363 
              'type' => 'Bool',
15364 
            },
15365 
            'direction' => 'in',
15366 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15367 
            'width' => 1,
15368 
          },
15369 
          'dout' => {
15370 
            'attributes' => {
15371 
              'bin_pt' => 0,
15372 
              'is_floating_block' => 1,
15373 
              'must_be_hdl_vector' => 1,
15374 
              'period' => 1,
15375 
              'port_id' => 0,
15376 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
15377 
              'type' => 'Bool',
15378 
            },
15379 
            'direction' => 'out',
15380 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15381 
            'width' => 1,
15382 
          },
15383 
          'en' => {
15384 
            'attributes' => {
15385 
              'bin_pt' => 0,
15386 
              'is_floating_block' => 1,
15387 
              'must_be_hdl_vector' => 1,
15388 
              'period' => 1,
15389 
              'port_id' => 1,
15390 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
15391 
              'type' => 'Bool',
15392 
            },
15393 
            'direction' => 'in',
15394 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15395 
            'width' => 1,
15396 
          },
15397 
        },
15398 
      },
15399 
      'entityName' => 'x_x4',
15400 
    },
15401 
    'to_register15' => {
15402 
      'connections' => {
15403 
        'ce' => 'sysgen_dut.to_register15_ce',
15404 
        'clk' => 'sysgen_dut.to_register15_clk',
15405 
        'clr' => 'sysgen_dut.to_register15_clr',
15406 
        'data_in' => 'sysgen_dut.to_register15_data_in',
15407 
        'dout' => 'to_register15.dout',
15408 
        'en' => 'sysgen_dut.to_register15_en',
15409 
      },
15410 
      'entity' => {
15411 
        'attributes' => {
15412 
          'entityAlreadyNetlisted' => 1,
15413 
          'generics' => [
15414 
          ],
15415 
          'is_floating_block' => 1,
15416 
          'mask' => {
15417 
            'Block_Handle' => 44.0009765625,
15418 
            'Block_handle' => 44.0009765625,
15419 
            'MDL_Handle' => 3.0009765625,
15420 
            'MDL_handle' => 3.0009765625,
15421 
            'arith_type' => 1,
15422 
            'bin_pt' => 14,
15423 
            'block_config' => 'sysgen_blockset:toreg_config',
15424 
            'block_handle' => 44.0009765625,
15425 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
15426 
            'block_type' => 'toreg',
15427 
            'dbl_ovrd' => 0,
15428 
            'explicit_data_type' => 0,
15429 
            'init' => 0,
15430 
            'init_bit_vector' => '00000000000000000000000000000000b',
15431 
            'mdl_handle' => 3.0009765625,
15432 
            'model_handle' => 3.0009765625,
15433 
            'n_bits' => 16,
15434 
            'ownership' => 1,
15435 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15436 
            'shared_memory_name' => 'register06td',
15437 
          },
15438 
          'needs_vhdl_wrapper' => 0,
15439 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
15440 
        },
15441 
        'entityName' => 'x_x5',
15442 
        'ports' => {
15443 
          'ce' => {
15444 
            'attributes' => {
15445 
              'domain' => '',
15446 
              'group' => 1,
15447 
              'isCe' => 1,
15448 
              'is_floating_block' => 1,
15449 
              'period' => 1,
15450 
              'type' => 'logic',
15451 
            },
15452 
            'direction' => 'in',
15453 
            'hdlType' => 'std_logic',
15454 
            'width' => 1,
15455 
          },
15456 
          'clk' => {
15457 
            'attributes' => {
15458 
              'domain' => '',
15459 
              'group' => 1,
15460 
              'isClk' => 1,
15461 
              'is_floating_block' => 1,
15462 
              'period' => 1,
15463 
              'type' => 'logic',
15464 
            },
15465 
            'direction' => 'in',
15466 
            'hdlType' => 'std_logic',
15467 
            'width' => 1,
15468 
          },
15469 
          'clr' => {
15470 
            'attributes' => {
15471 
              'domain' => '',
15472 
              'group' => 1,
15473 
              'isClr' => 1,
15474 
              'is_floating_block' => 1,
15475 
              'period' => 1,
15476 
              'type' => 'logic',
15477 
              'valid_bit_used' => 0,
15478 
            },
15479 
            'direction' => 'in',
15480 
            'hdlType' => 'std_logic',
15481 
            'width' => 1,
15482 
          },
15483 
          'data_in' => {
15484 
            'attributes' => {
15485 
              'bin_pt' => 0,
15486 
              'is_floating_block' => 1,
15487 
              'must_be_hdl_vector' => 1,
15488 
              'period' => 1,
15489 
              'port_id' => 0,
15490 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
15491 
              'type' => 'UFix_32_0',
15492 
            },
15493 
            'direction' => 'in',
15494 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15495 
            'width' => 32,
15496 
          },
15497 
          'dout' => {
15498 
            'attributes' => {
15499 
              'bin_pt' => 0,
15500 
              'is_floating_block' => 1,
15501 
              'must_be_hdl_vector' => 1,
15502 
              'period' => 1,
15503 
              'port_id' => 0,
15504 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
15505 
              'type' => 'UFix_32_0',
15506 
            },
15507 
            'direction' => 'out',
15508 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15509 
            'width' => 32,
15510 
          },
15511 
          'en' => {
15512 
            'attributes' => {
15513 
              'bin_pt' => 0,
15514 
              'is_floating_block' => 1,
15515 
              'must_be_hdl_vector' => 1,
15516 
              'period' => 1,
15517 
              'port_id' => 1,
15518 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
15519 
              'type' => 'Bool',
15520 
            },
15521 
            'direction' => 'in',
15522 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15523 
            'width' => 1,
15524 
          },
15525 
        },
15526 
      },
15527 
      'entityName' => 'x_x5',
15528 
    },
15529 
    'to_register16' => {
15530 
      'connections' => {
15531 
        'ce' => 'sysgen_dut.to_register16_ce',
15532 
        'clk' => 'sysgen_dut.to_register16_clk',
15533 
        'clr' => 'sysgen_dut.to_register16_clr',
15534 
        'data_in' => 'sysgen_dut.to_register16_data_in',
15535 
        'dout' => 'to_register16.dout',
15536 
        'en' => 'sysgen_dut.to_register16_en',
15537 
      },
15538 
      'entity' => {
15539 
        'attributes' => {
15540 
          'entityAlreadyNetlisted' => 1,
15541 
          'generics' => [
15542 
          ],
15543 
          'is_floating_block' => 1,
15544 
          'mask' => {
15545 
            'Block_Handle' => 45.0009765625,
15546 
            'Block_handle' => 45.0009765625,
15547 
            'MDL_Handle' => 3.0009765625,
15548 
            'MDL_handle' => 3.0009765625,
15549 
            'arith_type' => 1,
15550 
            'bin_pt' => 14,
15551 
            'block_config' => 'sysgen_blockset:toreg_config',
15552 
            'block_handle' => 45.0009765625,
15553 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15554 
            'block_type' => 'toreg',
15555 
            'dbl_ovrd' => 0,
15556 
            'explicit_data_type' => 0,
15557 
            'init' => 0,
15558 
            'init_bit_vector' => '0b',
15559 
            'mdl_handle' => 3.0009765625,
15560 
            'model_handle' => 3.0009765625,
15561 
            'n_bits' => 16,
15562 
            'ownership' => 1,
15563 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15564 
            'shared_memory_name' => 'register07tv',
15565 
          },
15566 
          'needs_vhdl_wrapper' => 0,
15567 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15568 
        },
15569 
        'entityName' => 'x_x6',
15570 
        'ports' => {
15571 
          'ce' => {
15572 
            'attributes' => {
15573 
              'domain' => '',
15574 
              'group' => 1,
15575 
              'isCe' => 1,
15576 
              'is_floating_block' => 1,
15577 
              'period' => 1,
15578 
              'type' => 'logic',
15579 
            },
15580 
            'direction' => 'in',
15581 
            'hdlType' => 'std_logic',
15582 
            'width' => 1,
15583 
          },
15584 
          'clk' => {
15585 
            'attributes' => {
15586 
              'domain' => '',
15587 
              'group' => 1,
15588 
              'isClk' => 1,
15589 
              'is_floating_block' => 1,
15590 
              'period' => 1,
15591 
              'type' => 'logic',
15592 
            },
15593 
            'direction' => 'in',
15594 
            'hdlType' => 'std_logic',
15595 
            'width' => 1,
15596 
          },
15597 
          'clr' => {
15598 
            'attributes' => {
15599 
              'domain' => '',
15600 
              'group' => 1,
15601 
              'isClr' => 1,
15602 
              'is_floating_block' => 1,
15603 
              'period' => 1,
15604 
              'type' => 'logic',
15605 
              'valid_bit_used' => 0,
15606 
            },
15607 
            'direction' => 'in',
15608 
            'hdlType' => 'std_logic',
15609 
            'width' => 1,
15610 
          },
15611 
          'data_in' => {
15612 
            'attributes' => {
15613 
              'bin_pt' => 0,
15614 
              'is_floating_block' => 1,
15615 
              'must_be_hdl_vector' => 1,
15616 
              'period' => 1,
15617 
              'port_id' => 0,
15618 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
15619 
              'type' => 'Bool',
15620 
            },
15621 
            'direction' => 'in',
15622 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15623 
            'width' => 1,
15624 
          },
15625 
          'dout' => {
15626 
            'attributes' => {
15627 
              'bin_pt' => 0,
15628 
              'is_floating_block' => 1,
15629 
              'must_be_hdl_vector' => 1,
15630 
              'period' => 1,
15631 
              'port_id' => 0,
15632 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
15633 
              'type' => 'Bool',
15634 
            },
15635 
            'direction' => 'out',
15636 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15637 
            'width' => 1,
15638 
          },
15639 
          'en' => {
15640 
            'attributes' => {
15641 
              'bin_pt' => 0,
15642 
              'is_floating_block' => 1,
15643 
              'must_be_hdl_vector' => 1,
15644 
              'period' => 1,
15645 
              'port_id' => 1,
15646 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
15647 
              'type' => 'Bool',
15648 
            },
15649 
            'direction' => 'in',
15650 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15651 
            'width' => 1,
15652 
          },
15653 
        },
15654 
      },
15655 
      'entityName' => 'x_x6',
15656 
    },
15657 
    'to_register17' => {
15658 
      'connections' => {
15659 
        'ce' => 'sysgen_dut.to_register17_ce',
15660 
        'clk' => 'sysgen_dut.to_register17_clk',
15661 
        'clr' => 'sysgen_dut.to_register17_clr',
15662 
        'data_in' => 'sysgen_dut.to_register17_data_in',
15663 
        'dout' => 'to_register17.dout',
15664 
        'en' => 'sysgen_dut.to_register17_en',
15665 
      },
15666 
      'entity' => {
15667 
        'attributes' => {
15668 
          'entityAlreadyNetlisted' => 1,
15669 
          'generics' => [
15670 
          ],
15671 
          'is_floating_block' => 1,
15672 
          'mask' => {
15673 
            'Block_Handle' => 46.0009765625,
15674 
            'Block_handle' => 46.0009765625,
15675 
            'MDL_Handle' => 3.0009765625,
15676 
            'MDL_handle' => 3.0009765625,
15677 
            'arith_type' => 1,
15678 
            'bin_pt' => 14,
15679 
            'block_config' => 'sysgen_blockset:toreg_config',
15680 
            'block_handle' => 46.0009765625,
15681 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15682 
            'block_type' => 'toreg',
15683 
            'dbl_ovrd' => 0,
15684 
            'explicit_data_type' => 0,
15685 
            'init' => 0,
15686 
            'init_bit_vector' => '00000000000000000000000000000000b',
15687 
            'mdl_handle' => 3.0009765625,
15688 
            'model_handle' => 3.0009765625,
15689 
            'n_bits' => 16,
15690 
            'ownership' => 1,
15691 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15692 
            'shared_memory_name' => 'register07td',
15693 
          },
15694 
          'needs_vhdl_wrapper' => 0,
15695 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15696 
        },
15697 
        'entityName' => 'x_x7',
15698 
        'ports' => {
15699 
          'ce' => {
15700 
            'attributes' => {
15701 
              'domain' => '',
15702 
              'group' => 1,
15703 
              'isCe' => 1,
15704 
              'is_floating_block' => 1,
15705 
              'period' => 1,
15706 
              'type' => 'logic',
15707 
            },
15708 
            'direction' => 'in',
15709 
            'hdlType' => 'std_logic',
15710 
            'width' => 1,
15711 
          },
15712 
          'clk' => {
15713 
            'attributes' => {
15714 
              'domain' => '',
15715 
              'group' => 1,
15716 
              'isClk' => 1,
15717 
              'is_floating_block' => 1,
15718 
              'period' => 1,
15719 
              'type' => 'logic',
15720 
            },
15721 
            'direction' => 'in',
15722 
            'hdlType' => 'std_logic',
15723 
            'width' => 1,
15724 
          },
15725 
          'clr' => {
15726 
            'attributes' => {
15727 
              'domain' => '',
15728 
              'group' => 1,
15729 
              'isClr' => 1,
15730 
              'is_floating_block' => 1,
15731 
              'period' => 1,
15732 
              'type' => 'logic',
15733 
              'valid_bit_used' => 0,
15734 
            },
15735 
            'direction' => 'in',
15736 
            'hdlType' => 'std_logic',
15737 
            'width' => 1,
15738 
          },
15739 
          'data_in' => {
15740 
            'attributes' => {
15741 
              'bin_pt' => 0,
15742 
              'is_floating_block' => 1,
15743 
              'must_be_hdl_vector' => 1,
15744 
              'period' => 1,
15745 
              'port_id' => 0,
15746 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
15747 
              'type' => 'UFix_32_0',
15748 
            },
15749 
            'direction' => 'in',
15750 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15751 
            'width' => 32,
15752 
          },
15753 
          'dout' => {
15754 
            'attributes' => {
15755 
              'bin_pt' => 0,
15756 
              'is_floating_block' => 1,
15757 
              'must_be_hdl_vector' => 1,
15758 
              'period' => 1,
15759 
              'port_id' => 0,
15760 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
15761 
              'type' => 'UFix_32_0',
15762 
            },
15763 
            'direction' => 'out',
15764 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15765 
            'width' => 32,
15766 
          },
15767 
          'en' => {
15768 
            'attributes' => {
15769 
              'bin_pt' => 0,
15770 
              'is_floating_block' => 1,
15771 
              'must_be_hdl_vector' => 1,
15772 
              'period' => 1,
15773 
              'port_id' => 1,
15774 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
15775 
              'type' => 'Bool',
15776 
            },
15777 
            'direction' => 'in',
15778 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15779 
            'width' => 1,
15780 
          },
15781 
        },
15782 
      },
15783 
      'entityName' => 'x_x7',
15784 
    },
15785 
    'to_register18' => {
15786 
      'connections' => {
15787 
        'ce' => 'sysgen_dut.to_register18_ce',
15788 
        'clk' => 'sysgen_dut.to_register18_clk',
15789 
        'clr' => 'sysgen_dut.to_register18_clr',
15790 
        'data_in' => 'sysgen_dut.to_register18_data_in',
15791 
        'dout' => 'to_register18.dout',
15792 
        'en' => 'sysgen_dut.to_register18_en',
15793 
      },
15794 
      'entity' => {
15795 
        'attributes' => {
15796 
          'entityAlreadyNetlisted' => 1,
15797 
          'generics' => [
15798 
          ],
15799 
          'is_floating_block' => 1,
15800 
          'mask' => {
15801 
            'Block_Handle' => 47.0009765625,
15802 
            'Block_handle' => 47.0009765625,
15803 
            'MDL_Handle' => 3.0009765625,
15804 
            'MDL_handle' => 3.0009765625,
15805 
            'arith_type' => 1,
15806 
            'bin_pt' => 14,
15807 
            'block_config' => 'sysgen_blockset:toreg_config',
15808 
            'block_handle' => 47.0009765625,
15809 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15810 
            'block_type' => 'toreg',
15811 
            'dbl_ovrd' => 0,
15812 
            'explicit_data_type' => 0,
15813 
            'init' => 0,
15814 
            'init_bit_vector' => '0b',
15815 
            'mdl_handle' => 3.0009765625,
15816 
            'model_handle' => 3.0009765625,
15817 
            'n_bits' => 16,
15818 
            'ownership' => 1,
15819 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15820 
            'shared_memory_name' => 'DMA_Host2Board_Busy',
15821 
          },
15822 
          'needs_vhdl_wrapper' => 0,
15823 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15824 
        },
15825 
        'entityName' => 'x_x8',
15826 
        'ports' => {
15827 
          'ce' => {
15828 
            'attributes' => {
15829 
              'domain' => '',
15830 
              'group' => 1,
15831 
              'isCe' => 1,
15832 
              'is_floating_block' => 1,
15833 
              'period' => 1,
15834 
              'type' => 'logic',
15835 
            },
15836 
            'direction' => 'in',
15837 
            'hdlType' => 'std_logic',
15838 
            'width' => 1,
15839 
          },
15840 
          'clk' => {
15841 
            'attributes' => {
15842 
              'domain' => '',
15843 
              'group' => 1,
15844 
              'isClk' => 1,
15845 
              'is_floating_block' => 1,
15846 
              'period' => 1,
15847 
              'type' => 'logic',
15848 
            },
15849 
            'direction' => 'in',
15850 
            'hdlType' => 'std_logic',
15851 
            'width' => 1,
15852 
          },
15853 
          'clr' => {
15854 
            'attributes' => {
15855 
              'domain' => '',
15856 
              'group' => 1,
15857 
              'isClr' => 1,
15858 
              'is_floating_block' => 1,
15859 
              'period' => 1,
15860 
              'type' => 'logic',
15861 
              'valid_bit_used' => 0,
15862 
            },
15863 
            'direction' => 'in',
15864 
            'hdlType' => 'std_logic',
15865 
            'width' => 1,
15866 
          },
15867 
          'data_in' => {
15868 
            'attributes' => {
15869 
              'bin_pt' => 0,
15870 
              'is_floating_block' => 1,
15871 
              'must_be_hdl_vector' => 1,
15872 
              'period' => 1,
15873 
              'port_id' => 0,
15874 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
15875 
              'type' => 'UFix_1_0',
15876 
            },
15877 
            'direction' => 'in',
15878 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15879 
            'width' => 1,
15880 
          },
15881 
          'dout' => {
15882 
            'attributes' => {
15883 
              'bin_pt' => 0,
15884 
              'is_floating_block' => 1,
15885 
              'must_be_hdl_vector' => 1,
15886 
              'period' => 1,
15887 
              'port_id' => 0,
15888 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
15889 
              'type' => 'UFix_1_0',
15890 
            },
15891 
            'direction' => 'out',
15892 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15893 
            'width' => 1,
15894 
          },
15895 
          'en' => {
15896 
            'attributes' => {
15897 
              'bin_pt' => 0,
15898 
              'is_floating_block' => 1,
15899 
              'must_be_hdl_vector' => 1,
15900 
              'period' => 1,
15901 
              'port_id' => 1,
15902 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
15903 
              'type' => 'Bool',
15904 
            },
15905 
            'direction' => 'in',
15906 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15907 
            'width' => 1,
15908 
          },
15909 
        },
15910 
      },
15911 
      'entityName' => 'x_x8',
15912 
    },
15913 
    'to_register19' => {
15914 
      'connections' => {
15915 
        'ce' => 'sysgen_dut.to_register19_ce',
15916 
        'clk' => 'sysgen_dut.to_register19_clk',
15917 
        'clr' => 'sysgen_dut.to_register19_clr',
15918 
        'data_in' => 'sysgen_dut.to_register19_data_in',
15919 
        'dout' => 'to_register19.dout',
15920 
        'en' => 'sysgen_dut.to_register19_en',
15921 
      },
15922 
      'entity' => {
15923 
        'attributes' => {
15924 
          'entityAlreadyNetlisted' => 1,
15925 
          'generics' => [
15926 
          ],
15927 
          'is_floating_block' => 1,
15928 
          'mask' => {
15929 
            'Block_Handle' => 48.0009765625,
15930 
            'Block_handle' => 48.0009765625,
15931 
            'MDL_Handle' => 3.0009765625,
15932 
            'MDL_handle' => 3.0009765625,
15933 
            'arith_type' => 1,
15934 
            'bin_pt' => 14,
15935 
            'block_config' => 'sysgen_blockset:toreg_config',
15936 
            'block_handle' => 48.0009765625,
15937 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
15938 
            'block_type' => 'toreg',
15939 
            'dbl_ovrd' => 0,
15940 
            'explicit_data_type' => 0,
15941 
            'init' => 0,
15942 
            'init_bit_vector' => '0b',
15943 
            'mdl_handle' => 3.0009765625,
15944 
            'model_handle' => 3.0009765625,
15945 
            'n_bits' => 16,
15946 
            'ownership' => 1,
15947 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15948 
            'shared_memory_name' => 'DMA_Host2Board_Done',
15949 
          },
15950 
          'needs_vhdl_wrapper' => 0,
15951 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
15952 
        },
15953 
        'entityName' => 'x_x9',
15954 
        'ports' => {
15955 
          'ce' => {
15956 
            'attributes' => {
15957 
              'domain' => '',
15958 
              'group' => 1,
15959 
              'isCe' => 1,
15960 
              'is_floating_block' => 1,
15961 
              'period' => 1,
15962 
              'type' => 'logic',
15963 
            },
15964 
            'direction' => 'in',
15965 
            'hdlType' => 'std_logic',
15966 
            'width' => 1,
15967 
          },
15968 
          'clk' => {
15969 
            'attributes' => {
15970 
              'domain' => '',
15971 
              'group' => 1,
15972 
              'isClk' => 1,
15973 
              'is_floating_block' => 1,
15974 
              'period' => 1,
15975 
              'type' => 'logic',
15976 
            },
15977 
            'direction' => 'in',
15978 
            'hdlType' => 'std_logic',
15979 
            'width' => 1,
15980 
          },
15981 
          'clr' => {
15982 
            'attributes' => {
15983 
              'domain' => '',
15984 
              'group' => 1,
15985 
              'isClr' => 1,
15986 
              'is_floating_block' => 1,
15987 
              'period' => 1,
15988 
              'type' => 'logic',
15989 
              'valid_bit_used' => 0,
15990 
            },
15991 
            'direction' => 'in',
15992 
            'hdlType' => 'std_logic',
15993 
            'width' => 1,
15994 
          },
15995 
          'data_in' => {
15996 
            'attributes' => {
15997 
              'bin_pt' => 0,
15998 
              'is_floating_block' => 1,
15999 
              'must_be_hdl_vector' => 1,
16000 
              'period' => 1,
16001 
              'port_id' => 0,
16002 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
16003 
              'type' => 'UFix_1_0',
16004 
            },
16005 
            'direction' => 'in',
16006 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16007 
            'width' => 1,
16008 
          },
16009 
          'dout' => {
16010 
            'attributes' => {
16011 
              'bin_pt' => 0,
16012 
              'is_floating_block' => 1,
16013 
              'must_be_hdl_vector' => 1,
16014 
              'period' => 1,
16015 
              'port_id' => 0,
16016 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
16017 
              'type' => 'UFix_1_0',
16018 
            },
16019 
            'direction' => 'out',
16020 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16021 
            'width' => 1,
16022 
          },
16023 
          'en' => {
16024 
            'attributes' => {
16025 
              'bin_pt' => 0,
16026 
              'is_floating_block' => 1,
16027 
              'must_be_hdl_vector' => 1,
16028 
              'period' => 1,
16029 
              'port_id' => 1,
16030 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
16031 
              'type' => 'Bool',
16032 
            },
16033 
            'direction' => 'in',
16034 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16035 
            'width' => 1,
16036 
          },
16037 
        },
16038 
      },
16039 
      'entityName' => 'x_x9',
16040 
    },
16041 
    'to_register2' => {
16042 
      'connections' => {
16043 
        'ce' => 'sysgen_dut.to_register2_ce',
16044 
        'clk' => 'sysgen_dut.to_register2_clk',
16045 
        'clr' => 'sysgen_dut.to_register2_clr',
16046 
        'data_in' => 'sysgen_dut.to_register2_data_in',
16047 
        'dout' => 'to_register2.dout',
16048 
        'en' => 'sysgen_dut.to_register2_en',
16049 
      },
16050 
      'entity' => {
16051 
        'attributes' => {
16052 
          'entityAlreadyNetlisted' => 1,
16053 
          'generics' => [
16054 
          ],
16055 
          'is_floating_block' => 1,
16056 
          'mask' => {
16057 
            'Block_Handle' => 49.0009765625,
16058 
            'Block_handle' => 49.0009765625,
16059 
            'MDL_Handle' => 3.0009765625,
16060 
            'MDL_handle' => 3.0009765625,
16061 
            'arith_type' => 1,
16062 
            'bin_pt' => 14,
16063 
            'block_config' => 'sysgen_blockset:toreg_config',
16064 
            'block_handle' => 49.0009765625,
16065 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
16066 
            'block_type' => 'toreg',
16067 
            'dbl_ovrd' => 0,
16068 
            'explicit_data_type' => 0,
16069 
            'init' => 0,
16070 
            'init_bit_vector' => '00000000000000000000000000000000b',
16071 
            'mdl_handle' => 3.0009765625,
16072 
            'model_handle' => 3.0009765625,
16073 
            'n_bits' => 16,
16074 
            'ownership' => 1,
16075 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16076 
            'shared_memory_name' => 'debug3i',
16077 
          },
16078 
          'needs_vhdl_wrapper' => 0,
16079 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
16080 
        },
16081 
        'entityName' => 'x_x10',
16082 
        'ports' => {
16083 
          'ce' => {
16084 
            'attributes' => {
16085 
              'domain' => '',
16086 
              'group' => 1,
16087 
              'isCe' => 1,
16088 
              'is_floating_block' => 1,
16089 
              'period' => 1,
16090 
              'type' => 'logic',
16091 
            },
16092 
            'direction' => 'in',
16093 
            'hdlType' => 'std_logic',
16094 
            'width' => 1,
16095 
          },
16096 
          'clk' => {
16097 
            'attributes' => {
16098 
              'domain' => '',
16099 
              'group' => 1,
16100 
              'isClk' => 1,
16101 
              'is_floating_block' => 1,
16102 
              'period' => 1,
16103 
              'type' => 'logic',
16104 
            },
16105 
            'direction' => 'in',
16106 
            'hdlType' => 'std_logic',
16107 
            'width' => 1,
16108 
          },
16109 
          'clr' => {
16110 
            'attributes' => {
16111 
              'domain' => '',
16112 
              'group' => 1,
16113 
              'isClr' => 1,
16114 
              'is_floating_block' => 1,
16115 
              'period' => 1,
16116 
              'type' => 'logic',
16117 
              'valid_bit_used' => 0,
16118 
            },
16119 
            'direction' => 'in',
16120 
            'hdlType' => 'std_logic',
16121 
            'width' => 1,
16122 
          },
16123 
          'data_in' => {
16124 
            'attributes' => {
16125 
              'bin_pt' => 0,
16126 
              'is_floating_block' => 1,
16127 
              'must_be_hdl_vector' => 1,
16128 
              'period' => 1,
16129 
              'port_id' => 0,
16130 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
16131 
              'type' => 'UFix_32_0',
16132 
            },
16133 
            'direction' => 'in',
16134 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16135 
            'width' => 32,
16136 
          },
16137 
          'dout' => {
16138 
            'attributes' => {
16139 
              'bin_pt' => 0,
16140 
              'is_floating_block' => 1,
16141 
              'must_be_hdl_vector' => 1,
16142 
              'period' => 1,
16143 
              'port_id' => 0,
16144 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
16145 
              'type' => 'UFix_32_0',
16146 
            },
16147 
            'direction' => 'out',
16148 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16149 
            'width' => 32,
16150 
          },
16151 
          'en' => {
16152 
            'attributes' => {
16153 
              'bin_pt' => 0,
16154 
              'is_floating_block' => 1,
16155 
              'must_be_hdl_vector' => 1,
16156 
              'period' => 1,
16157 
              'port_id' => 1,
16158 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
16159 
              'type' => 'Bool',
16160 
            },
16161 
            'direction' => 'in',
16162 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16163 
            'width' => 1,
16164 
          },
16165 
        },
16166 
      },
16167 
      'entityName' => 'x_x10',
16168 
    },
16169 
    'to_register20' => {
16170 
      'connections' => {
16171 
        'ce' => 'sysgen_dut.to_register20_ce',
16172 
        'clk' => 'sysgen_dut.to_register20_clk',
16173 
        'clr' => 'sysgen_dut.to_register20_clr',
16174 
        'data_in' => 'sysgen_dut.to_register20_data_in',
16175 
        'dout' => 'to_register20.dout',
16176 
        'en' => 'sysgen_dut.to_register20_en',
16177 
      },
16178 
      'entity' => {
16179 
        'attributes' => {
16180 
          'entityAlreadyNetlisted' => 1,
16181 
          'generics' => [
16182 
          ],
16183 
          'is_floating_block' => 1,
16184 
          'mask' => {
16185 
            'Block_Handle' => 50.0009765625,
16186 
            'Block_handle' => 50.0009765625,
16187 
            'MDL_Handle' => 3.0009765625,
16188 
            'MDL_handle' => 3.0009765625,
16189 
            'arith_type' => 1,
16190 
            'bin_pt' => 14,
16191 
            'block_config' => 'sysgen_blockset:toreg_config',
16192 
            'block_handle' => 50.0009765625,
16193 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
16194 
            'block_type' => 'toreg',
16195 
            'dbl_ovrd' => 0,
16196 
            'explicit_data_type' => 0,
16197 
            'init' => 0,
16198 
            'init_bit_vector' => '00000000000000000000000000000000b',
16199 
            'mdl_handle' => 3.0009765625,
16200 
            'model_handle' => 3.0009765625,
16201 
            'n_bits' => 16,
16202 
            'ownership' => 1,
16203 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16204 
            'shared_memory_name' => 'debug4i',
16205 
          },
16206 
          'needs_vhdl_wrapper' => 0,
16207 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
16208 
        },
16209 
        'entityName' => 'x_x11',
16210 
        'ports' => {
16211 
          'ce' => {
16212 
            'attributes' => {
16213 
              'domain' => '',
16214 
              'group' => 1,
16215 
              'isCe' => 1,
16216 
              'is_floating_block' => 1,
16217 
              'period' => 1,
16218 
              'type' => 'logic',
16219 
            },
16220 
            'direction' => 'in',
16221 
            'hdlType' => 'std_logic',
16222 
            'width' => 1,
16223 
          },
16224 
          'clk' => {
16225 
            'attributes' => {
16226 
              'domain' => '',
16227 
              'group' => 1,
16228 
              'isClk' => 1,
16229 
              'is_floating_block' => 1,
16230 
              'period' => 1,
16231 
              'type' => 'logic',
16232 
            },
16233 
            'direction' => 'in',
16234 
            'hdlType' => 'std_logic',
16235 
            'width' => 1,
16236 
          },
16237 
          'clr' => {
16238 
            'attributes' => {
16239 
              'domain' => '',
16240 
              'group' => 1,
16241 
              'isClr' => 1,
16242 
              'is_floating_block' => 1,
16243 
              'period' => 1,
16244 
              'type' => 'logic',
16245 
              'valid_bit_used' => 0,
16246 
            },
16247 
            'direction' => 'in',
16248 
            'hdlType' => 'std_logic',
16249 
            'width' => 1,
16250 
          },
16251 
          'data_in' => {
16252 
            'attributes' => {
16253 
              'bin_pt' => 0,
16254 
              'is_floating_block' => 1,
16255 
              'must_be_hdl_vector' => 1,
16256 
              'period' => 1,
16257 
              'port_id' => 0,
16258 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
16259 
              'type' => 'UFix_32_0',
16260 
            },
16261 
            'direction' => 'in',
16262 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16263 
            'width' => 32,
16264 
          },
16265 
          'dout' => {
16266 
            'attributes' => {
16267 
              'bin_pt' => 0,
16268 
              'is_floating_block' => 1,
16269 
              'must_be_hdl_vector' => 1,
16270 
              'period' => 1,
16271 
              'port_id' => 0,
16272 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
16273 
              'type' => 'UFix_32_0',
16274 
            },
16275 
            'direction' => 'out',
16276 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16277 
            'width' => 32,
16278 
          },
16279 
          'en' => {
16280 
            'attributes' => {
16281 
              'bin_pt' => 0,
16282 
              'is_floating_block' => 1,
16283 
              'must_be_hdl_vector' => 1,
16284 
              'period' => 1,
16285 
              'port_id' => 1,
16286 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
16287 
              'type' => 'Bool',
16288 
            },
16289 
            'direction' => 'in',
16290 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16291 
            'width' => 1,
16292 
          },
16293 
        },
16294 
      },
16295 
      'entityName' => 'x_x11',
16296 
    },
16297 
    'to_register21' => {
16298 
      'connections' => {
16299 
        'ce' => 'sysgen_dut.to_register21_ce',
16300 
        'clk' => 'sysgen_dut.to_register21_clk',
16301 
        'clr' => 'sysgen_dut.to_register21_clr',
16302 
        'data_in' => 'sysgen_dut.to_register21_data_in',
16303 
        'dout' => 'to_register21.dout',
16304 
        'en' => 'sysgen_dut.to_register21_en',
16305 
      },
16306 
      'entity' => {
16307 
        'attributes' => {
16308 
          'entityAlreadyNetlisted' => 1,
16309 
          'generics' => [
16310 
          ],
16311 
          'is_floating_block' => 1,
16312 
          'mask' => {
16313 
            'Block_Handle' => 51.0009765625,
16314 
            'Block_handle' => 51.0009765625,
16315 
            'MDL_Handle' => 3.0009765625,
16316 
            'MDL_handle' => 3.0009765625,
16317 
            'arith_type' => 1,
16318 
            'bin_pt' => 14,
16319 
            'block_config' => 'sysgen_blockset:toreg_config',
16320 
            'block_handle' => 51.0009765625,
16321 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
16322 
            'block_type' => 'toreg',
16323 
            'dbl_ovrd' => 0,
16324 
            'explicit_data_type' => 0,
16325 
            'init' => 0,
16326 
            'init_bit_vector' => '0b',
16327 
            'mdl_handle' => 3.0009765625,
16328 
            'model_handle' => 3.0009765625,
16329 
            'n_bits' => 16,
16330 
            'ownership' => 1,
16331 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16332 
            'shared_memory_name' => 'register09tv',
16333 
          },
16334 
          'needs_vhdl_wrapper' => 0,
16335 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
16336 
        },
16337 
        'entityName' => 'x_x12',
16338 
        'ports' => {
16339 
          'ce' => {
16340 
            'attributes' => {
16341 
              'domain' => '',
16342 
              'group' => 1,
16343 
              'isCe' => 1,
16344 
              'is_floating_block' => 1,
16345 
              'period' => 1,
16346 
              'type' => 'logic',
16347 
            },
16348 
            'direction' => 'in',
16349 
            'hdlType' => 'std_logic',
16350 
            'width' => 1,
16351 
          },
16352 
          'clk' => {
16353 
            'attributes' => {
16354 
              'domain' => '',
16355 
              'group' => 1,
16356 
              'isClk' => 1,
16357 
              'is_floating_block' => 1,
16358 
              'period' => 1,
16359 
              'type' => 'logic',
16360 
            },
16361 
            'direction' => 'in',
16362 
            'hdlType' => 'std_logic',
16363 
            'width' => 1,
16364 
          },
16365 
          'clr' => {
16366 
            'attributes' => {
16367 
              'domain' => '',
16368 
              'group' => 1,
16369 
              'isClr' => 1,
16370 
              'is_floating_block' => 1,
16371 
              'period' => 1,
16372 
              'type' => 'logic',
16373 
              'valid_bit_used' => 0,
16374 
            },
16375 
            'direction' => 'in',
16376 
            'hdlType' => 'std_logic',
16377 
            'width' => 1,
16378 
          },
16379 
          'data_in' => {
16380 
            'attributes' => {
16381 
              'bin_pt' => 0,
16382 
              'is_floating_block' => 1,
16383 
              'must_be_hdl_vector' => 1,
16384 
              'period' => 1,
16385 
              'port_id' => 0,
16386 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
16387 
              'type' => 'Bool',
16388 
            },
16389 
            'direction' => 'in',
16390 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16391 
            'width' => 1,
16392 
          },
16393 
          'dout' => {
16394 
            'attributes' => {
16395 
              'bin_pt' => 0,
16396 
              'is_floating_block' => 1,
16397 
              'must_be_hdl_vector' => 1,
16398 
              'period' => 1,
16399 
              'port_id' => 0,
16400 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
16401 
              'type' => 'Bool',
16402 
            },
16403 
            'direction' => 'out',
16404 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16405 
            'width' => 1,
16406 
          },
16407 
          'en' => {
16408 
            'attributes' => {
16409 
              'bin_pt' => 0,
16410 
              'is_floating_block' => 1,
16411 
              'must_be_hdl_vector' => 1,
16412 
              'period' => 1,
16413 
              'port_id' => 1,
16414 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
16415 
              'type' => 'Bool',
16416 
            },
16417 
            'direction' => 'in',
16418 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16419 
            'width' => 1,
16420 
          },
16421 
        },
16422 
      },
16423 
      'entityName' => 'x_x12',
16424 
    },
16425 
    'to_register22' => {
16426 
      'connections' => {
16427 
        'ce' => 'sysgen_dut.to_register22_ce',
16428 
        'clk' => 'sysgen_dut.to_register22_clk',
16429 
        'clr' => 'sysgen_dut.to_register22_clr',
16430 
        'data_in' => 'sysgen_dut.to_register22_data_in',
16431 
        'dout' => 'to_register22.dout',
16432 
        'en' => 'sysgen_dut.to_register22_en',
16433 
      },
16434 
      'entity' => {
16435 
        'attributes' => {
16436 
          'entityAlreadyNetlisted' => 1,
16437 
          'generics' => [
16438 
          ],
16439 
          'is_floating_block' => 1,
16440 
          'mask' => {
16441 
            'Block_Handle' => 52.0009765625,
16442 
            'Block_handle' => 52.0009765625,
16443 
            'MDL_Handle' => 3.0009765625,
16444 
            'MDL_handle' => 3.0009765625,
16445 
            'arith_type' => 1,
16446 
            'bin_pt' => 14,
16447 
            'block_config' => 'sysgen_blockset:toreg_config',
16448 
            'block_handle' => 52.0009765625,
16449 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16450 
            'block_type' => 'toreg',
16451 
            'dbl_ovrd' => 0,
16452 
            'explicit_data_type' => 0,
16453 
            'init' => 0,
16454 
            'init_bit_vector' => '00000000000000000000000000000000b',
16455 
            'mdl_handle' => 3.0009765625,
16456 
            'model_handle' => 3.0009765625,
16457 
            'n_bits' => 16,
16458 
            'ownership' => 1,
16459 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16460 
            'shared_memory_name' => 'register09td',
16461 
          },
16462 
          'needs_vhdl_wrapper' => 0,
16463 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16464 
        },
16465 
        'entityName' => 'x_x13',
16466 
        'ports' => {
16467 
          'ce' => {
16468 
            'attributes' => {
16469 
              'domain' => '',
16470 
              'group' => 1,
16471 
              'isCe' => 1,
16472 
              'is_floating_block' => 1,
16473 
              'period' => 1,
16474 
              'type' => 'logic',
16475 
            },
16476 
            'direction' => 'in',
16477 
            'hdlType' => 'std_logic',
16478 
            'width' => 1,
16479 
          },
16480 
          'clk' => {
16481 
            'attributes' => {
16482 
              'domain' => '',
16483 
              'group' => 1,
16484 
              'isClk' => 1,
16485 
              'is_floating_block' => 1,
16486 
              'period' => 1,
16487 
              'type' => 'logic',
16488 
            },
16489 
            'direction' => 'in',
16490 
            'hdlType' => 'std_logic',
16491 
            'width' => 1,
16492 
          },
16493 
          'clr' => {
16494 
            'attributes' => {
16495 
              'domain' => '',
16496 
              'group' => 1,
16497 
              'isClr' => 1,
16498 
              'is_floating_block' => 1,
16499 
              'period' => 1,
16500 
              'type' => 'logic',
16501 
              'valid_bit_used' => 0,
16502 
            },
16503 
            'direction' => 'in',
16504 
            'hdlType' => 'std_logic',
16505 
            'width' => 1,
16506 
          },
16507 
          'data_in' => {
16508 
            'attributes' => {
16509 
              'bin_pt' => 0,
16510 
              'is_floating_block' => 1,
16511 
              'must_be_hdl_vector' => 1,
16512 
              'period' => 1,
16513 
              'port_id' => 0,
16514 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
16515 
              'type' => 'UFix_32_0',
16516 
            },
16517 
            'direction' => 'in',
16518 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16519 
            'width' => 32,
16520 
          },
16521 
          'dout' => {
16522 
            'attributes' => {
16523 
              'bin_pt' => 0,
16524 
              'is_floating_block' => 1,
16525 
              'must_be_hdl_vector' => 1,
16526 
              'period' => 1,
16527 
              'port_id' => 0,
16528 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
16529 
              'type' => 'UFix_32_0',
16530 
            },
16531 
            'direction' => 'out',
16532 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16533 
            'width' => 32,
16534 
          },
16535 
          'en' => {
16536 
            'attributes' => {
16537 
              'bin_pt' => 0,
16538 
              'is_floating_block' => 1,
16539 
              'must_be_hdl_vector' => 1,
16540 
              'period' => 1,
16541 
              'port_id' => 1,
16542 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
16543 
              'type' => 'Bool',
16544 
            },
16545 
            'direction' => 'in',
16546 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16547 
            'width' => 1,
16548 
          },
16549 
        },
16550 
      },
16551 
      'entityName' => 'x_x13',
16552 
    },
16553 
    'to_register23' => {
16554 
      'connections' => {
16555 
        'ce' => 'sysgen_dut.to_register23_ce',
16556 
        'clk' => 'sysgen_dut.to_register23_clk',
16557 
        'clr' => 'sysgen_dut.to_register23_clr',
16558 
        'data_in' => 'sysgen_dut.to_register23_data_in',
16559 
        'dout' => 'to_register23.dout',
16560 
        'en' => 'sysgen_dut.to_register23_en',
16561 
      },
16562 
      'entity' => {
16563 
        'attributes' => {
16564 
          'entityAlreadyNetlisted' => 1,
16565 
          'generics' => [
16566 
          ],
16567 
          'is_floating_block' => 1,
16568 
          'mask' => {
16569 
            'Block_Handle' => 53.0009765625,
16570 
            'Block_handle' => 53.0009765625,
16571 
            'MDL_Handle' => 3.0009765625,
16572 
            'MDL_handle' => 3.0009765625,
16573 
            'arith_type' => 1,
16574 
            'bin_pt' => 14,
16575 
            'block_config' => 'sysgen_blockset:toreg_config',
16576 
            'block_handle' => 53.0009765625,
16577 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16578 
            'block_type' => 'toreg',
16579 
            'dbl_ovrd' => 0,
16580 
            'explicit_data_type' => 0,
16581 
            'init' => 0,
16582 
            'init_bit_vector' => '0b',
16583 
            'mdl_handle' => 3.0009765625,
16584 
            'model_handle' => 3.0009765625,
16585 
            'n_bits' => 16,
16586 
            'ownership' => 1,
16587 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16588 
            'shared_memory_name' => 'register10tv',
16589 
          },
16590 
          'needs_vhdl_wrapper' => 0,
16591 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16592 
        },
16593 
        'entityName' => 'x_x14',
16594 
        'ports' => {
16595 
          'ce' => {
16596 
            'attributes' => {
16597 
              'domain' => '',
16598 
              'group' => 1,
16599 
              'isCe' => 1,
16600 
              'is_floating_block' => 1,
16601 
              'period' => 1,
16602 
              'type' => 'logic',
16603 
            },
16604 
            'direction' => 'in',
16605 
            'hdlType' => 'std_logic',
16606 
            'width' => 1,
16607 
          },
16608 
          'clk' => {
16609 
            'attributes' => {
16610 
              'domain' => '',
16611 
              'group' => 1,
16612 
              'isClk' => 1,
16613 
              'is_floating_block' => 1,
16614 
              'period' => 1,
16615 
              'type' => 'logic',
16616 
            },
16617 
            'direction' => 'in',
16618 
            'hdlType' => 'std_logic',
16619 
            'width' => 1,
16620 
          },
16621 
          'clr' => {
16622 
            'attributes' => {
16623 
              'domain' => '',
16624 
              'group' => 1,
16625 
              'isClr' => 1,
16626 
              'is_floating_block' => 1,
16627 
              'period' => 1,
16628 
              'type' => 'logic',
16629 
              'valid_bit_used' => 0,
16630 
            },
16631 
            'direction' => 'in',
16632 
            'hdlType' => 'std_logic',
16633 
            'width' => 1,
16634 
          },
16635 
          'data_in' => {
16636 
            'attributes' => {
16637 
              'bin_pt' => 0,
16638 
              'is_floating_block' => 1,
16639 
              'must_be_hdl_vector' => 1,
16640 
              'period' => 1,
16641 
              'port_id' => 0,
16642 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
16643 
              'type' => 'Bool',
16644 
            },
16645 
            'direction' => 'in',
16646 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16647 
            'width' => 1,
16648 
          },
16649 
          'dout' => {
16650 
            'attributes' => {
16651 
              'bin_pt' => 0,
16652 
              'is_floating_block' => 1,
16653 
              'must_be_hdl_vector' => 1,
16654 
              'period' => 1,
16655 
              'port_id' => 0,
16656 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
16657 
              'type' => 'Bool',
16658 
            },
16659 
            'direction' => 'out',
16660 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16661 
            'width' => 1,
16662 
          },
16663 
          'en' => {
16664 
            'attributes' => {
16665 
              'bin_pt' => 0,
16666 
              'is_floating_block' => 1,
16667 
              'must_be_hdl_vector' => 1,
16668 
              'period' => 1,
16669 
              'port_id' => 1,
16670 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
16671 
              'type' => 'Bool',
16672 
            },
16673 
            'direction' => 'in',
16674 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16675 
            'width' => 1,
16676 
          },
16677 
        },
16678 
      },
16679 
      'entityName' => 'x_x14',
16680 
    },
16681 
    'to_register24' => {
16682 
      'connections' => {
16683 
        'ce' => 'sysgen_dut.to_register24_ce',
16684 
        'clk' => 'sysgen_dut.to_register24_clk',
16685 
        'clr' => 'sysgen_dut.to_register24_clr',
16686 
        'data_in' => 'sysgen_dut.to_register24_data_in',
16687 
        'dout' => 'to_register24.dout',
16688 
        'en' => 'sysgen_dut.to_register24_en',
16689 
      },
16690 
      'entity' => {
16691 
        'attributes' => {
16692 
          'entityAlreadyNetlisted' => 1,
16693 
          'generics' => [
16694 
          ],
16695 
          'is_floating_block' => 1,
16696 
          'mask' => {
16697 
            'Block_Handle' => 54.0009765625,
16698 
            'Block_handle' => 54.0009765625,
16699 
            'MDL_Handle' => 3.0009765625,
16700 
            'MDL_handle' => 3.0009765625,
16701 
            'arith_type' => 1,
16702 
            'bin_pt' => 14,
16703 
            'block_config' => 'sysgen_blockset:toreg_config',
16704 
            'block_handle' => 54.0009765625,
16705 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16706 
            'block_type' => 'toreg',
16707 
            'dbl_ovrd' => 0,
16708 
            'explicit_data_type' => 0,
16709 
            'init' => 0,
16710 
            'init_bit_vector' => '00000000000000000000000000000000b',
16711 
            'mdl_handle' => 3.0009765625,
16712 
            'model_handle' => 3.0009765625,
16713 
            'n_bits' => 16,
16714 
            'ownership' => 1,
16715 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16716 
            'shared_memory_name' => 'register10td',
16717 
          },
16718 
          'needs_vhdl_wrapper' => 0,
16719 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16720 
        },
16721 
        'entityName' => 'x_x15',
16722 
        'ports' => {
16723 
          'ce' => {
16724 
            'attributes' => {
16725 
              'domain' => '',
16726 
              'group' => 1,
16727 
              'isCe' => 1,
16728 
              'is_floating_block' => 1,
16729 
              'period' => 1,
16730 
              'type' => 'logic',
16731 
            },
16732 
            'direction' => 'in',
16733 
            'hdlType' => 'std_logic',
16734 
            'width' => 1,
16735 
          },
16736 
          'clk' => {
16737 
            'attributes' => {
16738 
              'domain' => '',
16739 
              'group' => 1,
16740 
              'isClk' => 1,
16741 
              'is_floating_block' => 1,
16742 
              'period' => 1,
16743 
              'type' => 'logic',
16744 
            },
16745 
            'direction' => 'in',
16746 
            'hdlType' => 'std_logic',
16747 
            'width' => 1,
16748 
          },
16749 
          'clr' => {
16750 
            'attributes' => {
16751 
              'domain' => '',
16752 
              'group' => 1,
16753 
              'isClr' => 1,
16754 
              'is_floating_block' => 1,
16755 
              'period' => 1,
16756 
              'type' => 'logic',
16757 
              'valid_bit_used' => 0,
16758 
            },
16759 
            'direction' => 'in',
16760 
            'hdlType' => 'std_logic',
16761 
            'width' => 1,
16762 
          },
16763 
          'data_in' => {
16764 
            'attributes' => {
16765 
              'bin_pt' => 0,
16766 
              'is_floating_block' => 1,
16767 
              'must_be_hdl_vector' => 1,
16768 
              'period' => 1,
16769 
              'port_id' => 0,
16770 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
16771 
              'type' => 'UFix_32_0',
16772 
            },
16773 
            'direction' => 'in',
16774 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16775 
            'width' => 32,
16776 
          },
16777 
          'dout' => {
16778 
            'attributes' => {
16779 
              'bin_pt' => 0,
16780 
              'is_floating_block' => 1,
16781 
              'must_be_hdl_vector' => 1,
16782 
              'period' => 1,
16783 
              'port_id' => 0,
16784 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
16785 
              'type' => 'UFix_32_0',
16786 
            },
16787 
            'direction' => 'out',
16788 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16789 
            'width' => 32,
16790 
          },
16791 
          'en' => {
16792 
            'attributes' => {
16793 
              'bin_pt' => 0,
16794 
              'is_floating_block' => 1,
16795 
              'must_be_hdl_vector' => 1,
16796 
              'period' => 1,
16797 
              'port_id' => 1,
16798 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
16799 
              'type' => 'Bool',
16800 
            },
16801 
            'direction' => 'in',
16802 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16803 
            'width' => 1,
16804 
          },
16805 
        },
16806 
      },
16807 
      'entityName' => 'x_x15',
16808 
    },
16809 
    'to_register25' => {
16810 
      'connections' => {
16811 
        'ce' => 'sysgen_dut.to_register25_ce',
16812 
        'clk' => 'sysgen_dut.to_register25_clk',
16813 
        'clr' => 'sysgen_dut.to_register25_clr',
16814 
        'data_in' => 'sysgen_dut.to_register25_data_in',
16815 
        'dout' => 'to_register25.dout',
16816 
        'en' => 'sysgen_dut.to_register25_en',
16817 
      },
16818 
      'entity' => {
16819 
        'attributes' => {
16820 
          'entityAlreadyNetlisted' => 1,
16821 
          'generics' => [
16822 
          ],
16823 
          'is_floating_block' => 1,
16824 
          'mask' => {
16825 
            'Block_Handle' => 55.0009765625,
16826 
            'Block_handle' => 55.0009765625,
16827 
            'MDL_Handle' => 3.0009765625,
16828 
            'MDL_handle' => 3.0009765625,
16829 
            'arith_type' => 1,
16830 
            'bin_pt' => 14,
16831 
            'block_config' => 'sysgen_blockset:toreg_config',
16832 
            'block_handle' => 55.0009765625,
16833 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16834 
            'block_type' => 'toreg',
16835 
            'dbl_ovrd' => 0,
16836 
            'explicit_data_type' => 0,
16837 
            'init' => 0,
16838 
            'init_bit_vector' => '0b',
16839 
            'mdl_handle' => 3.0009765625,
16840 
            'model_handle' => 3.0009765625,
16841 
            'n_bits' => 16,
16842 
            'ownership' => 1,
16843 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16844 
            'shared_memory_name' => 'register08tv',
16845 
          },
16846 
          'needs_vhdl_wrapper' => 0,
16847 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16848 
        },
16849 
        'entityName' => 'x_x16',
16850 
        'ports' => {
16851 
          'ce' => {
16852 
            'attributes' => {
16853 
              'domain' => '',
16854 
              'group' => 1,
16855 
              'isCe' => 1,
16856 
              'is_floating_block' => 1,
16857 
              'period' => 1,
16858 
              'type' => 'logic',
16859 
            },
16860 
            'direction' => 'in',
16861 
            'hdlType' => 'std_logic',
16862 
            'width' => 1,
16863 
          },
16864 
          'clk' => {
16865 
            'attributes' => {
16866 
              'domain' => '',
16867 
              'group' => 1,
16868 
              'isClk' => 1,
16869 
              'is_floating_block' => 1,
16870 
              'period' => 1,
16871 
              'type' => 'logic',
16872 
            },
16873 
            'direction' => 'in',
16874 
            'hdlType' => 'std_logic',
16875 
            'width' => 1,
16876 
          },
16877 
          'clr' => {
16878 
            'attributes' => {
16879 
              'domain' => '',
16880 
              'group' => 1,
16881 
              'isClr' => 1,
16882 
              'is_floating_block' => 1,
16883 
              'period' => 1,
16884 
              'type' => 'logic',
16885 
              'valid_bit_used' => 0,
16886 
            },
16887 
            'direction' => 'in',
16888 
            'hdlType' => 'std_logic',
16889 
            'width' => 1,
16890 
          },
16891 
          'data_in' => {
16892 
            'attributes' => {
16893 
              'bin_pt' => 0,
16894 
              'is_floating_block' => 1,
16895 
              'must_be_hdl_vector' => 1,
16896 
              'period' => 1,
16897 
              'port_id' => 0,
16898 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
16899 
              'type' => 'Bool',
16900 
            },
16901 
            'direction' => 'in',
16902 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16903 
            'width' => 1,
16904 
          },
16905 
          'dout' => {
16906 
            'attributes' => {
16907 
              'bin_pt' => 0,
16908 
              'is_floating_block' => 1,
16909 
              'must_be_hdl_vector' => 1,
16910 
              'period' => 1,
16911 
              'port_id' => 0,
16912 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
16913 
              'type' => 'Bool',
16914 
            },
16915 
            'direction' => 'out',
16916 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16917 
            'width' => 1,
16918 
          },
16919 
          'en' => {
16920 
            'attributes' => {
16921 
              'bin_pt' => 0,
16922 
              'is_floating_block' => 1,
16923 
              'must_be_hdl_vector' => 1,
16924 
              'period' => 1,
16925 
              'port_id' => 1,
16926 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
16927 
              'type' => 'Bool',
16928 
            },
16929 
            'direction' => 'in',
16930 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16931 
            'width' => 1,
16932 
          },
16933 
        },
16934 
      },
16935 
      'entityName' => 'x_x16',
16936 
    },
16937 
    'to_register26' => {
16938 
      'connections' => {
16939 
        'ce' => 'sysgen_dut.to_register26_ce',
16940 
        'clk' => 'sysgen_dut.to_register26_clk',
16941 
        'clr' => 'sysgen_dut.to_register26_clr',
16942 
        'data_in' => 'sysgen_dut.to_register26_data_in',
16943 
        'dout' => 'to_register26.dout',
16944 
        'en' => 'sysgen_dut.to_register26_en',
16945 
      },
16946 
      'entity' => {
16947 
        'attributes' => {
16948 
          'entityAlreadyNetlisted' => 1,
16949 
          'generics' => [
16950 
          ],
16951 
          'is_floating_block' => 1,
16952 
          'mask' => {
16953 
            'Block_Handle' => 56.0009765625,
16954 
            'Block_handle' => 56.0009765625,
16955 
            'MDL_Handle' => 3.0009765625,
16956 
            'MDL_handle' => 3.0009765625,
16957 
            'arith_type' => 1,
16958 
            'bin_pt' => 14,
16959 
            'block_config' => 'sysgen_blockset:toreg_config',
16960 
            'block_handle' => 56.0009765625,
16961 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
16962 
            'block_type' => 'toreg',
16963 
            'dbl_ovrd' => 0,
16964 
            'explicit_data_type' => 0,
16965 
            'init' => 0,
16966 
            'init_bit_vector' => '00000000000000000000000000000000b',
16967 
            'mdl_handle' => 3.0009765625,
16968 
            'model_handle' => 3.0009765625,
16969 
            'n_bits' => 16,
16970 
            'ownership' => 1,
16971 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16972 
            'shared_memory_name' => 'register08td',
16973 
          },
16974 
          'needs_vhdl_wrapper' => 0,
16975 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
16976 
        },
16977 
        'entityName' => 'x_x17',
16978 
        'ports' => {
16979 
          'ce' => {
16980 
            'attributes' => {
16981 
              'domain' => '',
16982 
              'group' => 1,
16983 
              'isCe' => 1,
16984 
              'is_floating_block' => 1,
16985 
              'period' => 1,
16986 
              'type' => 'logic',
16987 
            },
16988 
            'direction' => 'in',
16989 
            'hdlType' => 'std_logic',
16990 
            'width' => 1,
16991 
          },
16992 
          'clk' => {
16993 
            'attributes' => {
16994 
              'domain' => '',
16995 
              'group' => 1,
16996 
              'isClk' => 1,
16997 
              'is_floating_block' => 1,
16998 
              'period' => 1,
16999 
              'type' => 'logic',
17000 
            },
17001 
            'direction' => 'in',
17002 
            'hdlType' => 'std_logic',
17003 
            'width' => 1,
17004 
          },
17005 
          'clr' => {
17006 
            'attributes' => {
17007 
              'domain' => '',
17008 
              'group' => 1,
17009 
              'isClr' => 1,
17010 
              'is_floating_block' => 1,
17011 
              'period' => 1,
17012 
              'type' => 'logic',
17013 
              'valid_bit_used' => 0,
17014 
            },
17015 
            'direction' => 'in',
17016 
            'hdlType' => 'std_logic',
17017 
            'width' => 1,
17018 
          },
17019 
          'data_in' => {
17020 
            'attributes' => {
17021 
              'bin_pt' => 0,
17022 
              'is_floating_block' => 1,
17023 
              'must_be_hdl_vector' => 1,
17024 
              'period' => 1,
17025 
              'port_id' => 0,
17026 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
17027 
              'type' => 'UFix_32_0',
17028 
            },
17029 
            'direction' => 'in',
17030 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17031 
            'width' => 32,
17032 
          },
17033 
          'dout' => {
17034 
            'attributes' => {
17035 
              'bin_pt' => 0,
17036 
              'is_floating_block' => 1,
17037 
              'must_be_hdl_vector' => 1,
17038 
              'period' => 1,
17039 
              'port_id' => 0,
17040 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
17041 
              'type' => 'UFix_32_0',
17042 
            },
17043 
            'direction' => 'out',
17044 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17045 
            'width' => 32,
17046 
          },
17047 
          'en' => {
17048 
            'attributes' => {
17049 
              'bin_pt' => 0,
17050 
              'is_floating_block' => 1,
17051 
              'must_be_hdl_vector' => 1,
17052 
              'period' => 1,
17053 
              'port_id' => 1,
17054 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
17055 
              'type' => 'Bool',
17056 
            },
17057 
            'direction' => 'in',
17058 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17059 
            'width' => 1,
17060 
          },
17061 
        },
17062 
      },
17063 
      'entityName' => 'x_x17',
17064 
    },
17065 
    'to_register27' => {
17066 
      'connections' => {
17067 
        'ce' => 'sysgen_dut.to_register27_ce',
17068 
        'clk' => 'sysgen_dut.to_register27_clk',
17069 
        'clr' => 'sysgen_dut.to_register27_clr',
17070 
        'data_in' => 'sysgen_dut.to_register27_data_in',
17071 
        'dout' => 'to_register27.dout',
17072 
        'en' => 'sysgen_dut.to_register27_en',
17073 
      },
17074 
      'entity' => {
17075 
        'attributes' => {
17076 
          'entityAlreadyNetlisted' => 1,
17077 
          'generics' => [
17078 
          ],
17079 
          'is_floating_block' => 1,
17080 
          'mask' => {
17081 
            'Block_Handle' => 57.0009765625,
17082 
            'Block_handle' => 57.0009765625,
17083 
            'MDL_Handle' => 3.0009765625,
17084 
            'MDL_handle' => 3.0009765625,
17085 
            'arith_type' => 1,
17086 
            'bin_pt' => 14,
17087 
            'block_config' => 'sysgen_blockset:toreg_config',
17088 
            'block_handle' => 57.0009765625,
17089 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
17090 
            'block_type' => 'toreg',
17091 
            'dbl_ovrd' => 0,
17092 
            'explicit_data_type' => 0,
17093 
            'init' => 0,
17094 
            'init_bit_vector' => '0b',
17095 
            'mdl_handle' => 3.0009765625,
17096 
            'model_handle' => 3.0009765625,
17097 
            'n_bits' => 16,
17098 
            'ownership' => 1,
17099 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17100 
            'shared_memory_name' => 'register11tv',
17101 
          },
17102 
          'needs_vhdl_wrapper' => 0,
17103 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
17104 
        },
17105 
        'entityName' => 'x_x18',
17106 
        'ports' => {
17107 
          'ce' => {
17108 
            'attributes' => {
17109 
              'domain' => '',
17110 
              'group' => 1,
17111 
              'isCe' => 1,
17112 
              'is_floating_block' => 1,
17113 
              'period' => 1,
17114 
              'type' => 'logic',
17115 
            },
17116 
            'direction' => 'in',
17117 
            'hdlType' => 'std_logic',
17118 
            'width' => 1,
17119 
          },
17120 
          'clk' => {
17121 
            'attributes' => {
17122 
              'domain' => '',
17123 
              'group' => 1,
17124 
              'isClk' => 1,
17125 
              'is_floating_block' => 1,
17126 
              'period' => 1,
17127 
              'type' => 'logic',
17128 
            },
17129 
            'direction' => 'in',
17130 
            'hdlType' => 'std_logic',
17131 
            'width' => 1,
17132 
          },
17133 
          'clr' => {
17134 
            'attributes' => {
17135 
              'domain' => '',
17136 
              'group' => 1,
17137 
              'isClr' => 1,
17138 
              'is_floating_block' => 1,
17139 
              'period' => 1,
17140 
              'type' => 'logic',
17141 
              'valid_bit_used' => 0,
17142 
            },
17143 
            'direction' => 'in',
17144 
            'hdlType' => 'std_logic',
17145 
            'width' => 1,
17146 
          },
17147 
          'data_in' => {
17148 
            'attributes' => {
17149 
              'bin_pt' => 0,
17150 
              'is_floating_block' => 1,
17151 
              'must_be_hdl_vector' => 1,
17152 
              'period' => 1,
17153 
              'port_id' => 0,
17154 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
17155 
              'type' => 'Bool',
17156 
            },
17157 
            'direction' => 'in',
17158 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17159 
            'width' => 1,
17160 
          },
17161 
          'dout' => {
17162 
            'attributes' => {
17163 
              'bin_pt' => 0,
17164 
              'is_floating_block' => 1,
17165 
              'must_be_hdl_vector' => 1,
17166 
              'period' => 1,
17167 
              'port_id' => 0,
17168 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
17169 
              'type' => 'Bool',
17170 
            },
17171 
            'direction' => 'out',
17172 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17173 
            'width' => 1,
17174 
          },
17175 
          'en' => {
17176 
            'attributes' => {
17177 
              'bin_pt' => 0,
17178 
              'is_floating_block' => 1,
17179 
              'must_be_hdl_vector' => 1,
17180 
              'period' => 1,
17181 
              'port_id' => 1,
17182 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
17183 
              'type' => 'Bool',
17184 
            },
17185 
            'direction' => 'in',
17186 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17187 
            'width' => 1,
17188 
          },
17189 
        },
17190 
      },
17191 
      'entityName' => 'x_x18',
17192 
    },
17193 
    'to_register28' => {
17194 
      'connections' => {
17195 
        'ce' => 'sysgen_dut.to_register28_ce',
17196 
        'clk' => 'sysgen_dut.to_register28_clk',
17197 
        'clr' => 'sysgen_dut.to_register28_clr',
17198 
        'data_in' => 'sysgen_dut.to_register28_data_in',
17199 
        'dout' => 'to_register28.dout',
17200 
        'en' => 'sysgen_dut.to_register28_en',
17201 
      },
17202 
      'entity' => {
17203 
        'attributes' => {
17204 
          'entityAlreadyNetlisted' => 1,
17205 
          'generics' => [
17206 
          ],
17207 
          'is_floating_block' => 1,
17208 
          'mask' => {
17209 
            'Block_Handle' => 58.0009765625,
17210 
            'Block_handle' => 58.0009765625,
17211 
            'MDL_Handle' => 3.0009765625,
17212 
            'MDL_handle' => 3.0009765625,
17213 
            'arith_type' => 1,
17214 
            'bin_pt' => 14,
17215 
            'block_config' => 'sysgen_blockset:toreg_config',
17216 
            'block_handle' => 58.0009765625,
17217 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
17218 
            'block_type' => 'toreg',
17219 
            'dbl_ovrd' => 0,
17220 
            'explicit_data_type' => 0,
17221 
            'init' => 0,
17222 
            'init_bit_vector' => '00000000000000000000000000000000b',
17223 
            'mdl_handle' => 3.0009765625,
17224 
            'model_handle' => 3.0009765625,
17225 
            'n_bits' => 16,
17226 
            'ownership' => 1,
17227 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17228 
            'shared_memory_name' => 'register11td',
17229 
          },
17230 
          'needs_vhdl_wrapper' => 0,
17231 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
17232 
        },
17233 
        'entityName' => 'x_x19',
17234 
        'ports' => {
17235 
          'ce' => {
17236 
            'attributes' => {
17237 
              'domain' => '',
17238 
              'group' => 1,
17239 
              'isCe' => 1,
17240 
              'is_floating_block' => 1,
17241 
              'period' => 1,
17242 
              'type' => 'logic',
17243 
            },
17244 
            'direction' => 'in',
17245 
            'hdlType' => 'std_logic',
17246 
            'width' => 1,
17247 
          },
17248 
          'clk' => {
17249 
            'attributes' => {
17250 
              'domain' => '',
17251 
              'group' => 1,
17252 
              'isClk' => 1,
17253 
              'is_floating_block' => 1,
17254 
              'period' => 1,
17255 
              'type' => 'logic',
17256 
            },
17257 
            'direction' => 'in',
17258 
            'hdlType' => 'std_logic',
17259 
            'width' => 1,
17260 
          },
17261 
          'clr' => {
17262 
            'attributes' => {
17263 
              'domain' => '',
17264 
              'group' => 1,
17265 
              'isClr' => 1,
17266 
              'is_floating_block' => 1,
17267 
              'period' => 1,
17268 
              'type' => 'logic',
17269 
              'valid_bit_used' => 0,
17270 
            },
17271 
            'direction' => 'in',
17272 
            'hdlType' => 'std_logic',
17273 
            'width' => 1,
17274 
          },
17275 
          'data_in' => {
17276 
            'attributes' => {
17277 
              'bin_pt' => 0,
17278 
              'is_floating_block' => 1,
17279 
              'must_be_hdl_vector' => 1,
17280 
              'period' => 1,
17281 
              'port_id' => 0,
17282 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
17283 
              'type' => 'UFix_32_0',
17284 
            },
17285 
            'direction' => 'in',
17286 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17287 
            'width' => 32,
17288 
          },
17289 
          'dout' => {
17290 
            'attributes' => {
17291 
              'bin_pt' => 0,
17292 
              'is_floating_block' => 1,
17293 
              'must_be_hdl_vector' => 1,
17294 
              'period' => 1,
17295 
              'port_id' => 0,
17296 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
17297 
              'type' => 'UFix_32_0',
17298 
            },
17299 
            'direction' => 'out',
17300 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17301 
            'width' => 32,
17302 
          },
17303 
          'en' => {
17304 
            'attributes' => {
17305 
              'bin_pt' => 0,
17306 
              'is_floating_block' => 1,
17307 
              'must_be_hdl_vector' => 1,
17308 
              'period' => 1,
17309 
              'port_id' => 1,
17310 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
17311 
              'type' => 'Bool',
17312 
            },
17313 
            'direction' => 'in',
17314 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17315 
            'width' => 1,
17316 
          },
17317 
        },
17318 
      },
17319 
      'entityName' => 'x_x19',
17320 
    },
17321 
    'to_register29' => {
17322 
      'connections' => {
17323 
        'ce' => 'sysgen_dut.to_register29_ce',
17324 
        'clk' => 'sysgen_dut.to_register29_clk',
17325 
        'clr' => 'sysgen_dut.to_register29_clr',
17326 
        'data_in' => 'sysgen_dut.to_register29_data_in',
17327 
        'dout' => 'to_register29.dout',
17328 
        'en' => 'sysgen_dut.to_register29_en',
17329 
      },
17330 
      'entity' => {
17331 
        'attributes' => {
17332 
          'entityAlreadyNetlisted' => 1,
17333 
          'generics' => [
17334 
          ],
17335 
          'is_floating_block' => 1,
17336 
          'mask' => {
17337 
            'Block_Handle' => 59.0009765625,
17338 
            'Block_handle' => 59.0009765625,
17339 
            'MDL_Handle' => 3.0009765625,
17340 
            'MDL_handle' => 3.0009765625,
17341 
            'arith_type' => 1,
17342 
            'bin_pt' => 14,
17343 
            'block_config' => 'sysgen_blockset:toreg_config',
17344 
            'block_handle' => 59.0009765625,
17345 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
17346 
            'block_type' => 'toreg',
17347 
            'dbl_ovrd' => 0,
17348 
            'explicit_data_type' => 0,
17349 
            'init' => 0,
17350 
            'init_bit_vector' => '0b',
17351 
            'mdl_handle' => 3.0009765625,
17352 
            'model_handle' => 3.0009765625,
17353 
            'n_bits' => 16,
17354 
            'ownership' => 1,
17355 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17356 
            'shared_memory_name' => 'register12tv',
17357 
          },
17358 
          'needs_vhdl_wrapper' => 0,
17359 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
17360 
        },
17361 
        'entityName' => 'x_x20',
17362 
        'ports' => {
17363 
          'ce' => {
17364 
            'attributes' => {
17365 
              'domain' => '',
17366 
              'group' => 1,
17367 
              'isCe' => 1,
17368 
              'is_floating_block' => 1,
17369 
              'period' => 1,
17370 
              'type' => 'logic',
17371 
            },
17372 
            'direction' => 'in',
17373 
            'hdlType' => 'std_logic',
17374 
            'width' => 1,
17375 
          },
17376 
          'clk' => {
17377 
            'attributes' => {
17378 
              'domain' => '',
17379 
              'group' => 1,
17380 
              'isClk' => 1,
17381 
              'is_floating_block' => 1,
17382 
              'period' => 1,
17383 
              'type' => 'logic',
17384 
            },
17385 
            'direction' => 'in',
17386 
            'hdlType' => 'std_logic',
17387 
            'width' => 1,
17388 
          },
17389 
          'clr' => {
17390 
            'attributes' => {
17391 
              'domain' => '',
17392 
              'group' => 1,
17393 
              'isClr' => 1,
17394 
              'is_floating_block' => 1,
17395 
              'period' => 1,
17396 
              'type' => 'logic',
17397 
              'valid_bit_used' => 0,
17398 
            },
17399 
            'direction' => 'in',
17400 
            'hdlType' => 'std_logic',
17401 
            'width' => 1,
17402 
          },
17403 
          'data_in' => {
17404 
            'attributes' => {
17405 
              'bin_pt' => 0,
17406 
              'is_floating_block' => 1,
17407 
              'must_be_hdl_vector' => 1,
17408 
              'period' => 1,
17409 
              'port_id' => 0,
17410 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
17411 
              'type' => 'Bool',
17412 
            },
17413 
            'direction' => 'in',
17414 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17415 
            'width' => 1,
17416 
          },
17417 
          'dout' => {
17418 
            'attributes' => {
17419 
              'bin_pt' => 0,
17420 
              'is_floating_block' => 1,
17421 
              'must_be_hdl_vector' => 1,
17422 
              'period' => 1,
17423 
              'port_id' => 0,
17424 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
17425 
              'type' => 'Bool',
17426 
            },
17427 
            'direction' => 'out',
17428 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17429 
            'width' => 1,
17430 
          },
17431 
          'en' => {
17432 
            'attributes' => {
17433 
              'bin_pt' => 0,
17434 
              'is_floating_block' => 1,
17435 
              'must_be_hdl_vector' => 1,
17436 
              'period' => 1,
17437 
              'port_id' => 1,
17438 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
17439 
              'type' => 'Bool',
17440 
            },
17441 
            'direction' => 'in',
17442 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17443 
            'width' => 1,
17444 
          },
17445 
        },
17446 
      },
17447 
      'entityName' => 'x_x20',
17448 
    },
17449 
    'to_register3' => {
17450 
      'connections' => {
17451 
        'ce' => 'sysgen_dut.to_register3_ce',
17452 
        'clk' => 'sysgen_dut.to_register3_clk',
17453 
        'clr' => 'sysgen_dut.to_register3_clr',
17454 
        'data_in' => 'sysgen_dut.to_register3_data_in',
17455 
        'dout' => 'to_register3.dout',
17456 
        'en' => 'sysgen_dut.to_register3_en',
17457 
      },
17458 
      'entity' => {
17459 
        'attributes' => {
17460 
          'entityAlreadyNetlisted' => 1,
17461 
          'generics' => [
17462 
          ],
17463 
          'is_floating_block' => 1,
17464 
          'mask' => {
17465 
            'Block_Handle' => 60.0009765625,
17466 
            'Block_handle' => 60.0009765625,
17467 
            'MDL_Handle' => 3.0009765625,
17468 
            'MDL_handle' => 3.0009765625,
17469 
            'arith_type' => 1,
17470 
            'bin_pt' => 14,
17471 
            'block_config' => 'sysgen_blockset:toreg_config',
17472 
            'block_handle' => 60.0009765625,
17473 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17474 
            'block_type' => 'toreg',
17475 
            'dbl_ovrd' => 0,
17476 
            'explicit_data_type' => 0,
17477 
            'init' => 0,
17478 
            'init_bit_vector' => '0b',
17479 
            'mdl_handle' => 3.0009765625,
17480 
            'model_handle' => 3.0009765625,
17481 
            'n_bits' => 16,
17482 
            'ownership' => 1,
17483 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17484 
            'shared_memory_name' => 'register01tv',
17485 
          },
17486 
          'needs_vhdl_wrapper' => 0,
17487 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17488 
        },
17489 
        'entityName' => 'x_x21',
17490 
        'ports' => {
17491 
          'ce' => {
17492 
            'attributes' => {
17493 
              'domain' => '',
17494 
              'group' => 1,
17495 
              'isCe' => 1,
17496 
              'is_floating_block' => 1,
17497 
              'period' => 1,
17498 
              'type' => 'logic',
17499 
            },
17500 
            'direction' => 'in',
17501 
            'hdlType' => 'std_logic',
17502 
            'width' => 1,
17503 
          },
17504 
          'clk' => {
17505 
            'attributes' => {
17506 
              'domain' => '',
17507 
              'group' => 1,
17508 
              'isClk' => 1,
17509 
              'is_floating_block' => 1,
17510 
              'period' => 1,
17511 
              'type' => 'logic',
17512 
            },
17513 
            'direction' => 'in',
17514 
            'hdlType' => 'std_logic',
17515 
            'width' => 1,
17516 
          },
17517 
          'clr' => {
17518 
            'attributes' => {
17519 
              'domain' => '',
17520 
              'group' => 1,
17521 
              'isClr' => 1,
17522 
              'is_floating_block' => 1,
17523 
              'period' => 1,
17524 
              'type' => 'logic',
17525 
              'valid_bit_used' => 0,
17526 
            },
17527 
            'direction' => 'in',
17528 
            'hdlType' => 'std_logic',
17529 
            'width' => 1,
17530 
          },
17531 
          'data_in' => {
17532 
            'attributes' => {
17533 
              'bin_pt' => 0,
17534 
              'is_floating_block' => 1,
17535 
              'must_be_hdl_vector' => 1,
17536 
              'period' => 1,
17537 
              'port_id' => 0,
17538 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
17539 
              'type' => 'Bool',
17540 
            },
17541 
            'direction' => 'in',
17542 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17543 
            'width' => 1,
17544 
          },
17545 
          'dout' => {
17546 
            'attributes' => {
17547 
              'bin_pt' => 0,
17548 
              'is_floating_block' => 1,
17549 
              'must_be_hdl_vector' => 1,
17550 
              'period' => 1,
17551 
              'port_id' => 0,
17552 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
17553 
              'type' => 'Bool',
17554 
            },
17555 
            'direction' => 'out',
17556 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17557 
            'width' => 1,
17558 
          },
17559 
          'en' => {
17560 
            'attributes' => {
17561 
              'bin_pt' => 0,
17562 
              'is_floating_block' => 1,
17563 
              'must_be_hdl_vector' => 1,
17564 
              'period' => 1,
17565 
              'port_id' => 1,
17566 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
17567 
              'type' => 'Bool',
17568 
            },
17569 
            'direction' => 'in',
17570 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17571 
            'width' => 1,
17572 
          },
17573 
        },
17574 
      },
17575 
      'entityName' => 'x_x21',
17576 
    },
17577 
    'to_register30' => {
17578 
      'connections' => {
17579 
        'ce' => 'sysgen_dut.to_register30_ce',
17580 
        'clk' => 'sysgen_dut.to_register30_clk',
17581 
        'clr' => 'sysgen_dut.to_register30_clr',
17582 
        'data_in' => 'sysgen_dut.to_register30_data_in',
17583 
        'dout' => 'to_register30.dout',
17584 
        'en' => 'sysgen_dut.to_register30_en',
17585 
      },
17586 
      'entity' => {
17587 
        'attributes' => {
17588 
          'entityAlreadyNetlisted' => 1,
17589 
          'generics' => [
17590 
          ],
17591 
          'is_floating_block' => 1,
17592 
          'mask' => {
17593 
            'Block_Handle' => 61.0009765625,
17594 
            'Block_handle' => 61.0009765625,
17595 
            'MDL_Handle' => 3.0009765625,
17596 
            'MDL_handle' => 3.0009765625,
17597 
            'arith_type' => 1,
17598 
            'bin_pt' => 14,
17599 
            'block_config' => 'sysgen_blockset:toreg_config',
17600 
            'block_handle' => 61.0009765625,
17601 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17602 
            'block_type' => 'toreg',
17603 
            'dbl_ovrd' => 0,
17604 
            'explicit_data_type' => 0,
17605 
            'init' => 0,
17606 
            'init_bit_vector' => '00000000000000000000000000000000b',
17607 
            'mdl_handle' => 3.0009765625,
17608 
            'model_handle' => 3.0009765625,
17609 
            'n_bits' => 16,
17610 
            'ownership' => 1,
17611 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17612 
            'shared_memory_name' => 'register12td',
17613 
          },
17614 
          'needs_vhdl_wrapper' => 0,
17615 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17616 
        },
17617 
        'entityName' => 'x_x22',
17618 
        'ports' => {
17619 
          'ce' => {
17620 
            'attributes' => {
17621 
              'domain' => '',
17622 
              'group' => 1,
17623 
              'isCe' => 1,
17624 
              'is_floating_block' => 1,
17625 
              'period' => 1,
17626 
              'type' => 'logic',
17627 
            },
17628 
            'direction' => 'in',
17629 
            'hdlType' => 'std_logic',
17630 
            'width' => 1,
17631 
          },
17632 
          'clk' => {
17633 
            'attributes' => {
17634 
              'domain' => '',
17635 
              'group' => 1,
17636 
              'isClk' => 1,
17637 
              'is_floating_block' => 1,
17638 
              'period' => 1,
17639 
              'type' => 'logic',
17640 
            },
17641 
            'direction' => 'in',
17642 
            'hdlType' => 'std_logic',
17643 
            'width' => 1,
17644 
          },
17645 
          'clr' => {
17646 
            'attributes' => {
17647 
              'domain' => '',
17648 
              'group' => 1,
17649 
              'isClr' => 1,
17650 
              'is_floating_block' => 1,
17651 
              'period' => 1,
17652 
              'type' => 'logic',
17653 
              'valid_bit_used' => 0,
17654 
            },
17655 
            'direction' => 'in',
17656 
            'hdlType' => 'std_logic',
17657 
            'width' => 1,
17658 
          },
17659 
          'data_in' => {
17660 
            'attributes' => {
17661 
              'bin_pt' => 0,
17662 
              'is_floating_block' => 1,
17663 
              'must_be_hdl_vector' => 1,
17664 
              'period' => 1,
17665 
              'port_id' => 0,
17666 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
17667 
              'type' => 'UFix_32_0',
17668 
            },
17669 
            'direction' => 'in',
17670 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17671 
            'width' => 32,
17672 
          },
17673 
          'dout' => {
17674 
            'attributes' => {
17675 
              'bin_pt' => 0,
17676 
              'is_floating_block' => 1,
17677 
              'must_be_hdl_vector' => 1,
17678 
              'period' => 1,
17679 
              'port_id' => 0,
17680 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
17681 
              'type' => 'UFix_32_0',
17682 
            },
17683 
            'direction' => 'out',
17684 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17685 
            'width' => 32,
17686 
          },
17687 
          'en' => {
17688 
            'attributes' => {
17689 
              'bin_pt' => 0,
17690 
              'is_floating_block' => 1,
17691 
              'must_be_hdl_vector' => 1,
17692 
              'period' => 1,
17693 
              'port_id' => 1,
17694 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
17695 
              'type' => 'Bool',
17696 
            },
17697 
            'direction' => 'in',
17698 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17699 
            'width' => 1,
17700 
          },
17701 
        },
17702 
      },
17703 
      'entityName' => 'x_x22',
17704 
    },
17705 
    'to_register31' => {
17706 
      'connections' => {
17707 
        'ce' => 'sysgen_dut.to_register31_ce',
17708 
        'clk' => 'sysgen_dut.to_register31_clk',
17709 
        'clr' => 'sysgen_dut.to_register31_clr',
17710 
        'data_in' => 'sysgen_dut.to_register31_data_in',
17711 
        'dout' => 'to_register31.dout',
17712 
        'en' => 'sysgen_dut.to_register31_en',
17713 
      },
17714 
      'entity' => {
17715 
        'attributes' => {
17716 
          'entityAlreadyNetlisted' => 1,
17717 
          'generics' => [
17718 
          ],
17719 
          'is_floating_block' => 1,
17720 
          'mask' => {
17721 
            'Block_Handle' => 62.0009765625,
17722 
            'Block_handle' => 62.0009765625,
17723 
            'MDL_Handle' => 3.0009765625,
17724 
            'MDL_handle' => 3.0009765625,
17725 
            'arith_type' => 1,
17726 
            'bin_pt' => 14,
17727 
            'block_config' => 'sysgen_blockset:toreg_config',
17728 
            'block_handle' => 62.0009765625,
17729 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17730 
            'block_type' => 'toreg',
17731 
            'dbl_ovrd' => 0,
17732 
            'explicit_data_type' => 0,
17733 
            'init' => 0,
17734 
            'init_bit_vector' => '0b',
17735 
            'mdl_handle' => 3.0009765625,
17736 
            'model_handle' => 3.0009765625,
17737 
            'n_bits' => 16,
17738 
            'ownership' => 1,
17739 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17740 
            'shared_memory_name' => 'register13tv',
17741 
          },
17742 
          'needs_vhdl_wrapper' => 0,
17743 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17744 
        },
17745 
        'entityName' => 'x_x23',
17746 
        'ports' => {
17747 
          'ce' => {
17748 
            'attributes' => {
17749 
              'domain' => '',
17750 
              'group' => 1,
17751 
              'isCe' => 1,
17752 
              'is_floating_block' => 1,
17753 
              'period' => 1,
17754 
              'type' => 'logic',
17755 
            },
17756 
            'direction' => 'in',
17757 
            'hdlType' => 'std_logic',
17758 
            'width' => 1,
17759 
          },
17760 
          'clk' => {
17761 
            'attributes' => {
17762 
              'domain' => '',
17763 
              'group' => 1,
17764 
              'isClk' => 1,
17765 
              'is_floating_block' => 1,
17766 
              'period' => 1,
17767 
              'type' => 'logic',
17768 
            },
17769 
            'direction' => 'in',
17770 
            'hdlType' => 'std_logic',
17771 
            'width' => 1,
17772 
          },
17773 
          'clr' => {
17774 
            'attributes' => {
17775 
              'domain' => '',
17776 
              'group' => 1,
17777 
              'isClr' => 1,
17778 
              'is_floating_block' => 1,
17779 
              'period' => 1,
17780 
              'type' => 'logic',
17781 
              'valid_bit_used' => 0,
17782 
            },
17783 
            'direction' => 'in',
17784 
            'hdlType' => 'std_logic',
17785 
            'width' => 1,
17786 
          },
17787 
          'data_in' => {
17788 
            'attributes' => {
17789 
              'bin_pt' => 0,
17790 
              'is_floating_block' => 1,
17791 
              'must_be_hdl_vector' => 1,
17792 
              'period' => 1,
17793 
              'port_id' => 0,
17794 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
17795 
              'type' => 'Bool',
17796 
            },
17797 
            'direction' => 'in',
17798 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17799 
            'width' => 1,
17800 
          },
17801 
          'dout' => {
17802 
            'attributes' => {
17803 
              'bin_pt' => 0,
17804 
              'is_floating_block' => 1,
17805 
              'must_be_hdl_vector' => 1,
17806 
              'period' => 1,
17807 
              'port_id' => 0,
17808 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
17809 
              'type' => 'Bool',
17810 
            },
17811 
            'direction' => 'out',
17812 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17813 
            'width' => 1,
17814 
          },
17815 
          'en' => {
17816 
            'attributes' => {
17817 
              'bin_pt' => 0,
17818 
              'is_floating_block' => 1,
17819 
              'must_be_hdl_vector' => 1,
17820 
              'period' => 1,
17821 
              'port_id' => 1,
17822 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
17823 
              'type' => 'Bool',
17824 
            },
17825 
            'direction' => 'in',
17826 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17827 
            'width' => 1,
17828 
          },
17829 
        },
17830 
      },
17831 
      'entityName' => 'x_x23',
17832 
    },
17833 
    'to_register32' => {
17834 
      'connections' => {
17835 
        'ce' => 'sysgen_dut.to_register32_ce',
17836 
        'clk' => 'sysgen_dut.to_register32_clk',
17837 
        'clr' => 'sysgen_dut.to_register32_clr',
17838 
        'data_in' => 'sysgen_dut.to_register32_data_in',
17839 
        'dout' => 'to_register32.dout',
17840 
        'en' => 'sysgen_dut.to_register32_en',
17841 
      },
17842 
      'entity' => {
17843 
        'attributes' => {
17844 
          'entityAlreadyNetlisted' => 1,
17845 
          'generics' => [
17846 
          ],
17847 
          'is_floating_block' => 1,
17848 
          'mask' => {
17849 
            'Block_Handle' => 63.0009765625,
17850 
            'Block_handle' => 63.0009765625,
17851 
            'MDL_Handle' => 3.0009765625,
17852 
            'MDL_handle' => 3.0009765625,
17853 
            'arith_type' => 1,
17854 
            'bin_pt' => 14,
17855 
            'block_config' => 'sysgen_blockset:toreg_config',
17856 
            'block_handle' => 63.0009765625,
17857 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17858 
            'block_type' => 'toreg',
17859 
            'dbl_ovrd' => 0,
17860 
            'explicit_data_type' => 0,
17861 
            'init' => 0,
17862 
            'init_bit_vector' => '00000000000000000000000000000000b',
17863 
            'mdl_handle' => 3.0009765625,
17864 
            'model_handle' => 3.0009765625,
17865 
            'n_bits' => 16,
17866 
            'ownership' => 1,
17867 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17868 
            'shared_memory_name' => 'register13td',
17869 
          },
17870 
          'needs_vhdl_wrapper' => 0,
17871 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17872 
        },
17873 
        'entityName' => 'x_x24',
17874 
        'ports' => {
17875 
          'ce' => {
17876 
            'attributes' => {
17877 
              'domain' => '',
17878 
              'group' => 1,
17879 
              'isCe' => 1,
17880 
              'is_floating_block' => 1,
17881 
              'period' => 1,
17882 
              'type' => 'logic',
17883 
            },
17884 
            'direction' => 'in',
17885 
            'hdlType' => 'std_logic',
17886 
            'width' => 1,
17887 
          },
17888 
          'clk' => {
17889 
            'attributes' => {
17890 
              'domain' => '',
17891 
              'group' => 1,
17892 
              'isClk' => 1,
17893 
              'is_floating_block' => 1,
17894 
              'period' => 1,
17895 
              'type' => 'logic',
17896 
            },
17897 
            'direction' => 'in',
17898 
            'hdlType' => 'std_logic',
17899 
            'width' => 1,
17900 
          },
17901 
          'clr' => {
17902 
            'attributes' => {
17903 
              'domain' => '',
17904 
              'group' => 1,
17905 
              'isClr' => 1,
17906 
              'is_floating_block' => 1,
17907 
              'period' => 1,
17908 
              'type' => 'logic',
17909 
              'valid_bit_used' => 0,
17910 
            },
17911 
            'direction' => 'in',
17912 
            'hdlType' => 'std_logic',
17913 
            'width' => 1,
17914 
          },
17915 
          'data_in' => {
17916 
            'attributes' => {
17917 
              'bin_pt' => 0,
17918 
              'is_floating_block' => 1,
17919 
              'must_be_hdl_vector' => 1,
17920 
              'period' => 1,
17921 
              'port_id' => 0,
17922 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
17923 
              'type' => 'UFix_32_0',
17924 
            },
17925 
            'direction' => 'in',
17926 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17927 
            'width' => 32,
17928 
          },
17929 
          'dout' => {
17930 
            'attributes' => {
17931 
              'bin_pt' => 0,
17932 
              'is_floating_block' => 1,
17933 
              'must_be_hdl_vector' => 1,
17934 
              'period' => 1,
17935 
              'port_id' => 0,
17936 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
17937 
              'type' => 'UFix_32_0',
17938 
            },
17939 
            'direction' => 'out',
17940 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17941 
            'width' => 32,
17942 
          },
17943 
          'en' => {
17944 
            'attributes' => {
17945 
              'bin_pt' => 0,
17946 
              'is_floating_block' => 1,
17947 
              'must_be_hdl_vector' => 1,
17948 
              'period' => 1,
17949 
              'port_id' => 1,
17950 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
17951 
              'type' => 'Bool',
17952 
            },
17953 
            'direction' => 'in',
17954 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17955 
            'width' => 1,
17956 
          },
17957 
        },
17958 
      },
17959 
      'entityName' => 'x_x24',
17960 
    },
17961 
    'to_register33' => {
17962 
      'connections' => {
17963 
        'ce' => 'sysgen_dut.to_register33_ce',
17964 
        'clk' => 'sysgen_dut.to_register33_clk',
17965 
        'clr' => 'sysgen_dut.to_register33_clr',
17966 
        'data_in' => 'sysgen_dut.to_register33_data_in',
17967 
        'dout' => 'to_register33.dout',
17968 
        'en' => 'sysgen_dut.to_register33_en',
17969 
      },
17970 
      'entity' => {
17971 
        'attributes' => {
17972 
          'entityAlreadyNetlisted' => 1,
17973 
          'generics' => [
17974 
          ],
17975 
          'is_floating_block' => 1,
17976 
          'mask' => {
17977 
            'Block_Handle' => 64.0009765625,
17978 
            'Block_handle' => 64.0009765625,
17979 
            'MDL_Handle' => 3.0009765625,
17980 
            'MDL_handle' => 3.0009765625,
17981 
            'arith_type' => 1,
17982 
            'bin_pt' => 14,
17983 
            'block_config' => 'sysgen_blockset:toreg_config',
17984 
            'block_handle' => 64.0009765625,
17985 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
17986 
            'block_type' => 'toreg',
17987 
            'dbl_ovrd' => 0,
17988 
            'explicit_data_type' => 0,
17989 
            'init' => 0,
17990 
            'init_bit_vector' => '0b',
17991 
            'mdl_handle' => 3.0009765625,
17992 
            'model_handle' => 3.0009765625,
17993 
            'n_bits' => 16,
17994 
            'ownership' => 1,
17995 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17996 
            'shared_memory_name' => 'register14tv',
17997 
          },
17998 
          'needs_vhdl_wrapper' => 0,
17999 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
18000 
        },
18001 
        'entityName' => 'x_x25',
18002 
        'ports' => {
18003 
          'ce' => {
18004 
            'attributes' => {
18005 
              'domain' => '',
18006 
              'group' => 1,
18007 
              'isCe' => 1,
18008 
              'is_floating_block' => 1,
18009 
              'period' => 1,
18010 
              'type' => 'logic',
18011 
            },
18012 
            'direction' => 'in',
18013 
            'hdlType' => 'std_logic',
18014 
            'width' => 1,
18015 
          },
18016 
          'clk' => {
18017 
            'attributes' => {
18018 
              'domain' => '',
18019 
              'group' => 1,
18020 
              'isClk' => 1,
18021 
              'is_floating_block' => 1,
18022 
              'period' => 1,
18023 
              'type' => 'logic',
18024 
            },
18025 
            'direction' => 'in',
18026 
            'hdlType' => 'std_logic',
18027 
            'width' => 1,
18028 
          },
18029 
          'clr' => {
18030 
            'attributes' => {
18031 
              'domain' => '',
18032 
              'group' => 1,
18033 
              'isClr' => 1,
18034 
              'is_floating_block' => 1,
18035 
              'period' => 1,
18036 
              'type' => 'logic',
18037 
              'valid_bit_used' => 0,
18038 
            },
18039 
            'direction' => 'in',
18040 
            'hdlType' => 'std_logic',
18041 
            'width' => 1,
18042 
          },
18043 
          'data_in' => {
18044 
            'attributes' => {
18045 
              'bin_pt' => 0,
18046 
              'is_floating_block' => 1,
18047 
              'must_be_hdl_vector' => 1,
18048 
              'period' => 1,
18049 
              'port_id' => 0,
18050 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
18051 
              'type' => 'Bool',
18052 
            },
18053 
            'direction' => 'in',
18054 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18055 
            'width' => 1,
18056 
          },
18057 
          'dout' => {
18058 
            'attributes' => {
18059 
              'bin_pt' => 0,
18060 
              'is_floating_block' => 1,
18061 
              'must_be_hdl_vector' => 1,
18062 
              'period' => 1,
18063 
              'port_id' => 0,
18064 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
18065 
              'type' => 'Bool',
18066 
            },
18067 
            'direction' => 'out',
18068 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18069 
            'width' => 1,
18070 
          },
18071 
          'en' => {
18072 
            'attributes' => {
18073 
              'bin_pt' => 0,
18074 
              'is_floating_block' => 1,
18075 
              'must_be_hdl_vector' => 1,
18076 
              'period' => 1,
18077 
              'port_id' => 1,
18078 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
18079 
              'type' => 'Bool',
18080 
            },
18081 
            'direction' => 'in',
18082 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18083 
            'width' => 1,
18084 
          },
18085 
        },
18086 
      },
18087 
      'entityName' => 'x_x25',
18088 
    },
18089 
    'to_register34' => {
18090 
      'connections' => {
18091 
        'ce' => 'sysgen_dut.to_register34_ce',
18092 
        'clk' => 'sysgen_dut.to_register34_clk',
18093 
        'clr' => 'sysgen_dut.to_register34_clr',
18094 
        'data_in' => 'sysgen_dut.to_register34_data_in',
18095 
        'dout' => 'to_register34.dout',
18096 
        'en' => 'sysgen_dut.to_register34_en',
18097 
      },
18098 
      'entity' => {
18099 
        'attributes' => {
18100 
          'entityAlreadyNetlisted' => 1,
18101 
          'generics' => [
18102 
          ],
18103 
          'is_floating_block' => 1,
18104 
          'mask' => {
18105 
            'Block_Handle' => 65.0009765625,
18106 
            'Block_handle' => 65.0009765625,
18107 
            'MDL_Handle' => 3.0009765625,
18108 
            'MDL_handle' => 3.0009765625,
18109 
            'arith_type' => 1,
18110 
            'bin_pt' => 14,
18111 
            'block_config' => 'sysgen_blockset:toreg_config',
18112 
            'block_handle' => 65.0009765625,
18113 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
18114 
            'block_type' => 'toreg',
18115 
            'dbl_ovrd' => 0,
18116 
            'explicit_data_type' => 0,
18117 
            'init' => 0,
18118 
            'init_bit_vector' => '00000000000000000000000000000000b',
18119 
            'mdl_handle' => 3.0009765625,
18120 
            'model_handle' => 3.0009765625,
18121 
            'n_bits' => 16,
18122 
            'ownership' => 1,
18123 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18124 
            'shared_memory_name' => 'register14td',
18125 
          },
18126 
          'needs_vhdl_wrapper' => 0,
18127 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
18128 
        },
18129 
        'entityName' => 'x_x26',
18130 
        'ports' => {
18131 
          'ce' => {
18132 
            'attributes' => {
18133 
              'domain' => '',
18134 
              'group' => 1,
18135 
              'isCe' => 1,
18136 
              'is_floating_block' => 1,
18137 
              'period' => 1,
18138 
              'type' => 'logic',
18139 
            },
18140 
            'direction' => 'in',
18141 
            'hdlType' => 'std_logic',
18142 
            'width' => 1,
18143 
          },
18144 
          'clk' => {
18145 
            'attributes' => {
18146 
              'domain' => '',
18147 
              'group' => 1,
18148 
              'isClk' => 1,
18149 
              'is_floating_block' => 1,
18150 
              'period' => 1,
18151 
              'type' => 'logic',
18152 
            },
18153 
            'direction' => 'in',
18154 
            'hdlType' => 'std_logic',
18155 
            'width' => 1,
18156 
          },
18157 
          'clr' => {
18158 
            'attributes' => {
18159 
              'domain' => '',
18160 
              'group' => 1,
18161 
              'isClr' => 1,
18162 
              'is_floating_block' => 1,
18163 
              'period' => 1,
18164 
              'type' => 'logic',
18165 
              'valid_bit_used' => 0,
18166 
            },
18167 
            'direction' => 'in',
18168 
            'hdlType' => 'std_logic',
18169 
            'width' => 1,
18170 
          },
18171 
          'data_in' => {
18172 
            'attributes' => {
18173 
              'bin_pt' => 0,
18174 
              'is_floating_block' => 1,
18175 
              'must_be_hdl_vector' => 1,
18176 
              'period' => 1,
18177 
              'port_id' => 0,
18178 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
18179 
              'type' => 'UFix_32_0',
18180 
            },
18181 
            'direction' => 'in',
18182 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18183 
            'width' => 32,
18184 
          },
18185 
          'dout' => {
18186 
            'attributes' => {
18187 
              'bin_pt' => 0,
18188 
              'is_floating_block' => 1,
18189 
              'must_be_hdl_vector' => 1,
18190 
              'period' => 1,
18191 
              'port_id' => 0,
18192 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
18193 
              'type' => 'UFix_32_0',
18194 
            },
18195 
            'direction' => 'out',
18196 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18197 
            'width' => 32,
18198 
          },
18199 
          'en' => {
18200 
            'attributes' => {
18201 
              'bin_pt' => 0,
18202 
              'is_floating_block' => 1,
18203 
              'must_be_hdl_vector' => 1,
18204 
              'period' => 1,
18205 
              'port_id' => 1,
18206 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
18207 
              'type' => 'Bool',
18208 
            },
18209 
            'direction' => 'in',
18210 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18211 
            'width' => 1,
18212 
          },
18213 
        },
18214 
      },
18215 
      'entityName' => 'x_x26',
18216 
    },
18217 
    'to_register4' => {
18218 
      'connections' => {
18219 
        'ce' => 'sysgen_dut.to_register4_ce',
18220 
        'clk' => 'sysgen_dut.to_register4_clk',
18221 
        'clr' => 'sysgen_dut.to_register4_clr',
18222 
        'data_in' => 'sysgen_dut.to_register4_data_in',
18223 
        'dout' => 'to_register4.dout',
18224 
        'en' => 'sysgen_dut.to_register4_en',
18225 
      },
18226 
      'entity' => {
18227 
        'attributes' => {
18228 
          'entityAlreadyNetlisted' => 1,
18229 
          'generics' => [
18230 
          ],
18231 
          'is_floating_block' => 1,
18232 
          'mask' => {
18233 
            'Block_Handle' => 66.0009765625,
18234 
            'Block_handle' => 66.0009765625,
18235 
            'MDL_Handle' => 3.0009765625,
18236 
            'MDL_handle' => 3.0009765625,
18237 
            'arith_type' => 1,
18238 
            'bin_pt' => 14,
18239 
            'block_config' => 'sysgen_blockset:toreg_config',
18240 
            'block_handle' => 66.0009765625,
18241 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
18242 
            'block_type' => 'toreg',
18243 
            'dbl_ovrd' => 0,
18244 
            'explicit_data_type' => 0,
18245 
            'init' => 0,
18246 
            'init_bit_vector' => '0b',
18247 
            'mdl_handle' => 3.0009765625,
18248 
            'model_handle' => 3.0009765625,
18249 
            'n_bits' => 16,
18250 
            'ownership' => 1,
18251 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18252 
            'shared_memory_name' => 'register02tv',
18253 
          },
18254 
          'needs_vhdl_wrapper' => 0,
18255 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
18256 
        },
18257 
        'entityName' => 'x_x27',
18258 
        'ports' => {
18259 
          'ce' => {
18260 
            'attributes' => {
18261 
              'domain' => '',
18262 
              'group' => 1,
18263 
              'isCe' => 1,
18264 
              'is_floating_block' => 1,
18265 
              'period' => 1,
18266 
              'type' => 'logic',
18267 
            },
18268 
            'direction' => 'in',
18269 
            'hdlType' => 'std_logic',
18270 
            'width' => 1,
18271 
          },
18272 
          'clk' => {
18273 
            'attributes' => {
18274 
              'domain' => '',
18275 
              'group' => 1,
18276 
              'isClk' => 1,
18277 
              'is_floating_block' => 1,
18278 
              'period' => 1,
18279 
              'type' => 'logic',
18280 
            },
18281 
            'direction' => 'in',
18282 
            'hdlType' => 'std_logic',
18283 
            'width' => 1,
18284 
          },
18285 
          'clr' => {
18286 
            'attributes' => {
18287 
              'domain' => '',
18288 
              'group' => 1,
18289 
              'isClr' => 1,
18290 
              'is_floating_block' => 1,
18291 
              'period' => 1,
18292 
              'type' => 'logic',
18293 
              'valid_bit_used' => 0,
18294 
            },
18295 
            'direction' => 'in',
18296 
            'hdlType' => 'std_logic',
18297 
            'width' => 1,
18298 
          },
18299 
          'data_in' => {
18300 
            'attributes' => {
18301 
              'bin_pt' => 0,
18302 
              'is_floating_block' => 1,
18303 
              'must_be_hdl_vector' => 1,
18304 
              'period' => 1,
18305 
              'port_id' => 0,
18306 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
18307 
              'type' => 'Bool',
18308 
            },
18309 
            'direction' => 'in',
18310 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18311 
            'width' => 1,
18312 
          },
18313 
          'dout' => {
18314 
            'attributes' => {
18315 
              'bin_pt' => 0,
18316 
              'is_floating_block' => 1,
18317 
              'must_be_hdl_vector' => 1,
18318 
              'period' => 1,
18319 
              'port_id' => 0,
18320 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
18321 
              'type' => 'Bool',
18322 
            },
18323 
            'direction' => 'out',
18324 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18325 
            'width' => 1,
18326 
          },
18327 
          'en' => {
18328 
            'attributes' => {
18329 
              'bin_pt' => 0,
18330 
              'is_floating_block' => 1,
18331 
              'must_be_hdl_vector' => 1,
18332 
              'period' => 1,
18333 
              'port_id' => 1,
18334 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
18335 
              'type' => 'Bool',
18336 
            },
18337 
            'direction' => 'in',
18338 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18339 
            'width' => 1,
18340 
          },
18341 
        },
18342 
      },
18343 
      'entityName' => 'x_x27',
18344 
    },
18345 
    'to_register5' => {
18346 
      'connections' => {
18347 
        'ce' => 'sysgen_dut.to_register5_ce',
18348 
        'clk' => 'sysgen_dut.to_register5_clk',
18349 
        'clr' => 'sysgen_dut.to_register5_clr',
18350 
        'data_in' => 'sysgen_dut.to_register5_data_in',
18351 
        'dout' => 'to_register5.dout',
18352 
        'en' => 'sysgen_dut.to_register5_en',
18353 
      },
18354 
      'entity' => {
18355 
        'attributes' => {
18356 
          'entityAlreadyNetlisted' => 1,
18357 
          'generics' => [
18358 
          ],
18359 
          'is_floating_block' => 1,
18360 
          'mask' => {
18361 
            'Block_Handle' => 67.0009765625,
18362 
            'Block_handle' => 67.0009765625,
18363 
            'MDL_Handle' => 3.0009765625,
18364 
            'MDL_handle' => 3.0009765625,
18365 
            'arith_type' => 1,
18366 
            'bin_pt' => 14,
18367 
            'block_config' => 'sysgen_blockset:toreg_config',
18368 
            'block_handle' => 67.0009765625,
18369 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
18370 
            'block_type' => 'toreg',
18371 
            'dbl_ovrd' => 0,
18372 
            'explicit_data_type' => 0,
18373 
            'init' => 0,
18374 
            'init_bit_vector' => '00000000000000000000000000000000b',
18375 
            'mdl_handle' => 3.0009765625,
18376 
            'model_handle' => 3.0009765625,
18377 
            'n_bits' => 16,
18378 
            'ownership' => 1,
18379 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18380 
            'shared_memory_name' => 'register02td',
18381 
          },
18382 
          'needs_vhdl_wrapper' => 0,
18383 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
18384 
        },
18385 
        'entityName' => 'x_x28',
18386 
        'ports' => {
18387 
          'ce' => {
18388 
            'attributes' => {
18389 
              'domain' => '',
18390 
              'group' => 1,
18391 
              'isCe' => 1,
18392 
              'is_floating_block' => 1,
18393 
              'period' => 1,
18394 
              'type' => 'logic',
18395 
            },
18396 
            'direction' => 'in',
18397 
            'hdlType' => 'std_logic',
18398 
            'width' => 1,
18399 
          },
18400 
          'clk' => {
18401 
            'attributes' => {
18402 
              'domain' => '',
18403 
              'group' => 1,
18404 
              'isClk' => 1,
18405 
              'is_floating_block' => 1,
18406 
              'period' => 1,
18407 
              'type' => 'logic',
18408 
            },
18409 
            'direction' => 'in',
18410 
            'hdlType' => 'std_logic',
18411 
            'width' => 1,
18412 
          },
18413 
          'clr' => {
18414 
            'attributes' => {
18415 
              'domain' => '',
18416 
              'group' => 1,
18417 
              'isClr' => 1,
18418 
              'is_floating_block' => 1,
18419 
              'period' => 1,
18420 
              'type' => 'logic',
18421 
              'valid_bit_used' => 0,
18422 
            },
18423 
            'direction' => 'in',
18424 
            'hdlType' => 'std_logic',
18425 
            'width' => 1,
18426 
          },
18427 
          'data_in' => {
18428 
            'attributes' => {
18429 
              'bin_pt' => 0,
18430 
              'is_floating_block' => 1,
18431 
              'must_be_hdl_vector' => 1,
18432 
              'period' => 1,
18433 
              'port_id' => 0,
18434 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
18435 
              'type' => 'UFix_32_0',
18436 
            },
18437 
            'direction' => 'in',
18438 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18439 
            'width' => 32,
18440 
          },
18441 
          'dout' => {
18442 
            'attributes' => {
18443 
              'bin_pt' => 0,
18444 
              'is_floating_block' => 1,
18445 
              'must_be_hdl_vector' => 1,
18446 
              'period' => 1,
18447 
              'port_id' => 0,
18448 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
18449 
              'type' => 'UFix_32_0',
18450 
            },
18451 
            'direction' => 'out',
18452 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18453 
            'width' => 32,
18454 
          },
18455 
          'en' => {
18456 
            'attributes' => {
18457 
              'bin_pt' => 0,
18458 
              'is_floating_block' => 1,
18459 
              'must_be_hdl_vector' => 1,
18460 
              'period' => 1,
18461 
              'port_id' => 1,
18462 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
18463 
              'type' => 'Bool',
18464 
            },
18465 
            'direction' => 'in',
18466 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18467 
            'width' => 1,
18468 
          },
18469 
        },
18470 
      },
18471 
      'entityName' => 'x_x28',
18472 
    },
18473 
    'to_register6' => {
18474 
      'connections' => {
18475 
        'ce' => 'sysgen_dut.to_register6_ce',
18476 
        'clk' => 'sysgen_dut.to_register6_clk',
18477 
        'clr' => 'sysgen_dut.to_register6_clr',
18478 
        'data_in' => 'sysgen_dut.to_register6_data_in',
18479 
        'dout' => 'to_register6.dout',
18480 
        'en' => 'sysgen_dut.to_register6_en',
18481 
      },
18482 
      'entity' => {
18483 
        'attributes' => {
18484 
          'entityAlreadyNetlisted' => 1,
18485 
          'generics' => [
18486 
          ],
18487 
          'is_floating_block' => 1,
18488 
          'mask' => {
18489 
            'Block_Handle' => 68.0009765625,
18490 
            'Block_handle' => 68.0009765625,
18491 
            'MDL_Handle' => 3.0009765625,
18492 
            'MDL_handle' => 3.0009765625,
18493 
            'arith_type' => 1,
18494 
            'bin_pt' => 14,
18495 
            'block_config' => 'sysgen_blockset:toreg_config',
18496 
            'block_handle' => 68.0009765625,
18497 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18498 
            'block_type' => 'toreg',
18499 
            'dbl_ovrd' => 0,
18500 
            'explicit_data_type' => 0,
18501 
            'init' => 0,
18502 
            'init_bit_vector' => '00000000000000000000000000000000b',
18503 
            'mdl_handle' => 3.0009765625,
18504 
            'model_handle' => 3.0009765625,
18505 
            'n_bits' => 16,
18506 
            'ownership' => 1,
18507 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18508 
            'shared_memory_name' => 'debug1i',
18509 
          },
18510 
          'needs_vhdl_wrapper' => 0,
18511 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18512 
        },
18513 
        'entityName' => 'x_x29',
18514 
        'ports' => {
18515 
          'ce' => {
18516 
            'attributes' => {
18517 
              'domain' => '',
18518 
              'group' => 1,
18519 
              'isCe' => 1,
18520 
              'is_floating_block' => 1,
18521 
              'period' => 1,
18522 
              'type' => 'logic',
18523 
            },
18524 
            'direction' => 'in',
18525 
            'hdlType' => 'std_logic',
18526 
            'width' => 1,
18527 
          },
18528 
          'clk' => {
18529 
            'attributes' => {
18530 
              'domain' => '',
18531 
              'group' => 1,
18532 
              'isClk' => 1,
18533 
              'is_floating_block' => 1,
18534 
              'period' => 1,
18535 
              'type' => 'logic',
18536 
            },
18537 
            'direction' => 'in',
18538 
            'hdlType' => 'std_logic',
18539 
            'width' => 1,
18540 
          },
18541 
          'clr' => {
18542 
            'attributes' => {
18543 
              'domain' => '',
18544 
              'group' => 1,
18545 
              'isClr' => 1,
18546 
              'is_floating_block' => 1,
18547 
              'period' => 1,
18548 
              'type' => 'logic',
18549 
              'valid_bit_used' => 0,
18550 
            },
18551 
            'direction' => 'in',
18552 
            'hdlType' => 'std_logic',
18553 
            'width' => 1,
18554 
          },
18555 
          'data_in' => {
18556 
            'attributes' => {
18557 
              'bin_pt' => 0,
18558 
              'is_floating_block' => 1,
18559 
              'must_be_hdl_vector' => 1,
18560 
              'period' => 1,
18561 
              'port_id' => 0,
18562 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
18563 
              'type' => 'UFix_32_0',
18564 
            },
18565 
            'direction' => 'in',
18566 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18567 
            'width' => 32,
18568 
          },
18569 
          'dout' => {
18570 
            'attributes' => {
18571 
              'bin_pt' => 0,
18572 
              'is_floating_block' => 1,
18573 
              'must_be_hdl_vector' => 1,
18574 
              'period' => 1,
18575 
              'port_id' => 0,
18576 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
18577 
              'type' => 'UFix_32_0',
18578 
            },
18579 
            'direction' => 'out',
18580 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18581 
            'width' => 32,
18582 
          },
18583 
          'en' => {
18584 
            'attributes' => {
18585 
              'bin_pt' => 0,
18586 
              'is_floating_block' => 1,
18587 
              'must_be_hdl_vector' => 1,
18588 
              'period' => 1,
18589 
              'port_id' => 1,
18590 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
18591 
              'type' => 'Bool',
18592 
            },
18593 
            'direction' => 'in',
18594 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18595 
            'width' => 1,
18596 
          },
18597 
        },
18598 
      },
18599 
      'entityName' => 'x_x29',
18600 
    },
18601 
    'to_register7' => {
18602 
      'connections' => {
18603 
        'ce' => 'sysgen_dut.to_register7_ce',
18604 
        'clk' => 'sysgen_dut.to_register7_clk',
18605 
        'clr' => 'sysgen_dut.to_register7_clr',
18606 
        'data_in' => 'sysgen_dut.to_register7_data_in',
18607 
        'dout' => 'to_register7.dout',
18608 
        'en' => 'sysgen_dut.to_register7_en',
18609 
      },
18610 
      'entity' => {
18611 
        'attributes' => {
18612 
          'entityAlreadyNetlisted' => 1,
18613 
          'generics' => [
18614 
          ],
18615 
          'is_floating_block' => 1,
18616 
          'mask' => {
18617 
            'Block_Handle' => 69.0009765625,
18618 
            'Block_handle' => 69.0009765625,
18619 
            'MDL_Handle' => 3.0009765625,
18620 
            'MDL_handle' => 3.0009765625,
18621 
            'arith_type' => 1,
18622 
            'bin_pt' => 14,
18623 
            'block_config' => 'sysgen_blockset:toreg_config',
18624 
            'block_handle' => 69.0009765625,
18625 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18626 
            'block_type' => 'toreg',
18627 
            'dbl_ovrd' => 0,
18628 
            'explicit_data_type' => 0,
18629 
            'init' => 0,
18630 
            'init_bit_vector' => '00000000000000000000000000000000b',
18631 
            'mdl_handle' => 3.0009765625,
18632 
            'model_handle' => 3.0009765625,
18633 
            'n_bits' => 16,
18634 
            'ownership' => 1,
18635 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18636 
            'shared_memory_name' => 'register01td',
18637 
          },
18638 
          'needs_vhdl_wrapper' => 0,
18639 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18640 
        },
18641 
        'entityName' => 'x_x30',
18642 
        'ports' => {
18643 
          'ce' => {
18644 
            'attributes' => {
18645 
              'domain' => '',
18646 
              'group' => 1,
18647 
              'isCe' => 1,
18648 
              'is_floating_block' => 1,
18649 
              'period' => 1,
18650 
              'type' => 'logic',
18651 
            },
18652 
            'direction' => 'in',
18653 
            'hdlType' => 'std_logic',
18654 
            'width' => 1,
18655 
          },
18656 
          'clk' => {
18657 
            'attributes' => {
18658 
              'domain' => '',
18659 
              'group' => 1,
18660 
              'isClk' => 1,
18661 
              'is_floating_block' => 1,
18662 
              'period' => 1,
18663 
              'type' => 'logic',
18664 
            },
18665 
            'direction' => 'in',
18666 
            'hdlType' => 'std_logic',
18667 
            'width' => 1,
18668 
          },
18669 
          'clr' => {
18670 
            'attributes' => {
18671 
              'domain' => '',
18672 
              'group' => 1,
18673 
              'isClr' => 1,
18674 
              'is_floating_block' => 1,
18675 
              'period' => 1,
18676 
              'type' => 'logic',
18677 
              'valid_bit_used' => 0,
18678 
            },
18679 
            'direction' => 'in',
18680 
            'hdlType' => 'std_logic',
18681 
            'width' => 1,
18682 
          },
18683 
          'data_in' => {
18684 
            'attributes' => {
18685 
              'bin_pt' => 0,
18686 
              'is_floating_block' => 1,
18687 
              'must_be_hdl_vector' => 1,
18688 
              'period' => 1,
18689 
              'port_id' => 0,
18690 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
18691 
              'type' => 'UFix_32_0',
18692 
            },
18693 
            'direction' => 'in',
18694 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18695 
            'width' => 32,
18696 
          },
18697 
          'dout' => {
18698 
            'attributes' => {
18699 
              'bin_pt' => 0,
18700 
              'is_floating_block' => 1,
18701 
              'must_be_hdl_vector' => 1,
18702 
              'period' => 1,
18703 
              'port_id' => 0,
18704 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
18705 
              'type' => 'UFix_32_0',
18706 
            },
18707 
            'direction' => 'out',
18708 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18709 
            'width' => 32,
18710 
          },
18711 
          'en' => {
18712 
            'attributes' => {
18713 
              'bin_pt' => 0,
18714 
              'is_floating_block' => 1,
18715 
              'must_be_hdl_vector' => 1,
18716 
              'period' => 1,
18717 
              'port_id' => 1,
18718 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
18719 
              'type' => 'Bool',
18720 
            },
18721 
            'direction' => 'in',
18722 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18723 
            'width' => 1,
18724 
          },
18725 
        },
18726 
      },
18727 
      'entityName' => 'x_x30',
18728 
    },
18729 
    'to_register8' => {
18730 
      'connections' => {
18731 
        'ce' => 'sysgen_dut.to_register8_ce',
18732 
        'clk' => 'sysgen_dut.to_register8_clk',
18733 
        'clr' => 'sysgen_dut.to_register8_clr',
18734 
        'data_in' => 'sysgen_dut.to_register8_data_in',
18735 
        'dout' => 'to_register8.dout',
18736 
        'en' => 'sysgen_dut.to_register8_en',
18737 
      },
18738 
      'entity' => {
18739 
        'attributes' => {
18740 
          'entityAlreadyNetlisted' => 1,
18741 
          'generics' => [
18742 
          ],
18743 
          'is_floating_block' => 1,
18744 
          'mask' => {
18745 
            'Block_Handle' => 70.0009765625,
18746 
            'Block_handle' => 70.0009765625,
18747 
            'MDL_Handle' => 3.0009765625,
18748 
            'MDL_handle' => 3.0009765625,
18749 
            'arith_type' => 1,
18750 
            'bin_pt' => 14,
18751 
            'block_config' => 'sysgen_blockset:toreg_config',
18752 
            'block_handle' => 70.0009765625,
18753 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18754 
            'block_type' => 'toreg',
18755 
            'dbl_ovrd' => 0,
18756 
            'explicit_data_type' => 0,
18757 
            'init' => 0,
18758 
            'init_bit_vector' => '0b',
18759 
            'mdl_handle' => 3.0009765625,
18760 
            'model_handle' => 3.0009765625,
18761 
            'n_bits' => 16,
18762 
            'ownership' => 1,
18763 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18764 
            'shared_memory_name' => 'register03tv',
18765 
          },
18766 
          'needs_vhdl_wrapper' => 0,
18767 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18768 
        },
18769 
        'entityName' => 'x_x31',
18770 
        'ports' => {
18771 
          'ce' => {
18772 
            'attributes' => {
18773 
              'domain' => '',
18774 
              'group' => 1,
18775 
              'isCe' => 1,
18776 
              'is_floating_block' => 1,
18777 
              'period' => 1,
18778 
              'type' => 'logic',
18779 
            },
18780 
            'direction' => 'in',
18781 
            'hdlType' => 'std_logic',
18782 
            'width' => 1,
18783 
          },
18784 
          'clk' => {
18785 
            'attributes' => {
18786 
              'domain' => '',
18787 
              'group' => 1,
18788 
              'isClk' => 1,
18789 
              'is_floating_block' => 1,
18790 
              'period' => 1,
18791 
              'type' => 'logic',
18792 
            },
18793 
            'direction' => 'in',
18794 
            'hdlType' => 'std_logic',
18795 
            'width' => 1,
18796 
          },
18797 
          'clr' => {
18798 
            'attributes' => {
18799 
              'domain' => '',
18800 
              'group' => 1,
18801 
              'isClr' => 1,
18802 
              'is_floating_block' => 1,
18803 
              'period' => 1,
18804 
              'type' => 'logic',
18805 
              'valid_bit_used' => 0,
18806 
            },
18807 
            'direction' => 'in',
18808 
            'hdlType' => 'std_logic',
18809 
            'width' => 1,
18810 
          },
18811 
          'data_in' => {
18812 
            'attributes' => {
18813 
              'bin_pt' => 0,
18814 
              'is_floating_block' => 1,
18815 
              'must_be_hdl_vector' => 1,
18816 
              'period' => 1,
18817 
              'port_id' => 0,
18818 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
18819 
              'type' => 'Bool',
18820 
            },
18821 
            'direction' => 'in',
18822 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18823 
            'width' => 1,
18824 
          },
18825 
          'dout' => {
18826 
            'attributes' => {
18827 
              'bin_pt' => 0,
18828 
              'is_floating_block' => 1,
18829 
              'must_be_hdl_vector' => 1,
18830 
              'period' => 1,
18831 
              'port_id' => 0,
18832 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
18833 
              'type' => 'Bool',
18834 
            },
18835 
            'direction' => 'out',
18836 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18837 
            'width' => 1,
18838 
          },
18839 
          'en' => {
18840 
            'attributes' => {
18841 
              'bin_pt' => 0,
18842 
              'is_floating_block' => 1,
18843 
              'must_be_hdl_vector' => 1,
18844 
              'period' => 1,
18845 
              'port_id' => 1,
18846 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
18847 
              'type' => 'Bool',
18848 
            },
18849 
            'direction' => 'in',
18850 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18851 
            'width' => 1,
18852 
          },
18853 
        },
18854 
      },
18855 
      'entityName' => 'x_x31',
18856 
    },
18857 
    'to_register9' => {
18858 
      'connections' => {
18859 
        'ce' => 'sysgen_dut.to_register9_ce',
18860 
        'clk' => 'sysgen_dut.to_register9_clk',
18861 
        'clr' => 'sysgen_dut.to_register9_clr',
18862 
        'data_in' => 'sysgen_dut.to_register9_data_in',
18863 
        'dout' => 'to_register9.dout',
18864 
        'en' => 'sysgen_dut.to_register9_en',
18865 
      },
18866 
      'entity' => {
18867 
        'attributes' => {
18868 
          'entityAlreadyNetlisted' => 1,
18869 
          'generics' => [
18870 
          ],
18871 
          'is_floating_block' => 1,
18872 
          'mask' => {
18873 
            'Block_Handle' => 71.0009765625,
18874 
            'Block_handle' => 71.0009765625,
18875 
            'MDL_Handle' => 3.0009765625,
18876 
            'MDL_handle' => 3.0009765625,
18877 
            'arith_type' => 1,
18878 
            'bin_pt' => 14,
18879 
            'block_config' => 'sysgen_blockset:toreg_config',
18880 
            'block_handle' => 71.0009765625,
18881 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
18882 
            'block_type' => 'toreg',
18883 
            'dbl_ovrd' => 0,
18884 
            'explicit_data_type' => 0,
18885 
            'init' => 0,
18886 
            'init_bit_vector' => '00000000000000000000000000000000b',
18887 
            'mdl_handle' => 3.0009765625,
18888 
            'model_handle' => 3.0009765625,
18889 
            'n_bits' => 16,
18890 
            'ownership' => 1,
18891 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18892 
            'shared_memory_name' => 'register03td',
18893 
          },
18894 
          'needs_vhdl_wrapper' => 0,
18895 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
18896 
        },
18897 
        'entityName' => 'x_x32',
18898 
        'ports' => {
18899 
          'ce' => {
18900 
            'attributes' => {
18901 
              'domain' => '',
18902 
              'group' => 1,
18903 
              'isCe' => 1,
18904 
              'is_floating_block' => 1,
18905 
              'period' => 1,
18906 
              'type' => 'logic',
18907 
            },
18908 
            'direction' => 'in',
18909 
            'hdlType' => 'std_logic',
18910 
            'width' => 1,
18911 
          },
18912 
          'clk' => {
18913 
            'attributes' => {
18914 
              'domain' => '',
18915 
              'group' => 1,
18916 
              'isClk' => 1,
18917 
              'is_floating_block' => 1,
18918 
              'period' => 1,
18919 
              'type' => 'logic',
18920 
            },
18921 
            'direction' => 'in',
18922 
            'hdlType' => 'std_logic',
18923 
            'width' => 1,
18924 
          },
18925 
          'clr' => {
18926 
            'attributes' => {
18927 
              'domain' => '',
18928 
              'group' => 1,
18929 
              'isClr' => 1,
18930 
              'is_floating_block' => 1,
18931 
              'period' => 1,
18932 
              'type' => 'logic',
18933 
              'valid_bit_used' => 0,
18934 
            },
18935 
            'direction' => 'in',
18936 
            'hdlType' => 'std_logic',
18937 
            'width' => 1,
18938 
          },
18939 
          'data_in' => {
18940 
            'attributes' => {
18941 
              'bin_pt' => 0,
18942 
              'is_floating_block' => 1,
18943 
              'must_be_hdl_vector' => 1,
18944 
              'period' => 1,
18945 
              'port_id' => 0,
18946 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
18947 
              'type' => 'UFix_32_0',
18948 
            },
18949 
            'direction' => 'in',
18950 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18951 
            'width' => 32,
18952 
          },
18953 
          'dout' => {
18954 
            'attributes' => {
18955 
              'bin_pt' => 0,
18956 
              'is_floating_block' => 1,
18957 
              'must_be_hdl_vector' => 1,
18958 
              'period' => 1,
18959 
              'port_id' => 0,
18960 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
18961 
              'type' => 'UFix_32_0',
18962 
            },
18963 
            'direction' => 'out',
18964 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18965 
            'width' => 32,
18966 
          },
18967 
          'en' => {
18968 
            'attributes' => {
18969 
              'bin_pt' => 0,
18970 
              'is_floating_block' => 1,
18971 
              'must_be_hdl_vector' => 1,
18972 
              'period' => 1,
18973 
              'port_id' => 1,
18974 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
18975 
              'type' => 'Bool',
18976 
            },
18977 
            'direction' => 'in',
18978 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18979 
            'width' => 1,
18980 
          },
18981 
        },
18982 
      },
18983 
      'entityName' => 'x_x32',
18984 
    },
18985 
  },
18986 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.