OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0,
4 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
5 
    'Impl_file' => 'ISE Defaults',
6 
    'Impl_file_sgadvanced' => '',
7 
    'Synth_file' => 'XST Defaults',
8 
    'Synth_file_sgadvanced' => '',
9 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
10 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
11 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
12 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
13 
    'base_system_period_hardware' => 5,
14 
    'base_system_period_simulink' => '8e-009',
15 
    'block_icon_display' => 'Default',
16 
    'block_type' => 'sysgen',
17 
    'block_version' => '',
18 
    'ce_clr' => 0,
19 
    'clkWrapper' => 'inout_logic_cw',
20 
    'clkWrapperFile' => 'inout_logic_cw.vhd',
21 
    'clock_loc' => '',
22 
    'clock_wrapper' => 'Clock Enables',
23 
    'clock_wrapper_sgadvanced' => '',
24 
    'compilation' => 'NGC Netlist',
25 
    'compilation_lut' => {
26 
      'keys' => [
27 
        'HDL Netlist',
28 
        'Bitstream',
29 
        'NGC Netlist',
30 
      ],
31 
      'values' => [
32 
        'target1',
33 
        'target2',
34 
        'target3',
35 
      ],
36 
    },
37 
    'compilation_target' => 'NGC Netlist',
38 
    'core_generation' => 1,
39 
    'core_generation_sgadvanced' => '',
40 
    'core_is_deployed' => 0,
41 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c00613f6911dfdaa6',
42 
    'coregen_part_family' => 'virtex6',
43 
    'createTestbench' => 0,
44 
    'create_interface_document' => 'off',
45 
    'dbl_ovrd' => -1,
46 
    'dbl_ovrd_sgadvanced' => '',
47 
    'dcm_info' => {
48 
    },
49 
    'dcm_input_clock_period' => 5,
50 
    'deprecated_control' => 'off',
51 
    'deprecated_control_sgadvanced' => '',
52 
    'design' => 'inout_logic',
53 
    'designFile' => 'inout_logic.vhd',
54 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\pcie-v6-ml605_ISE12_OpenCores\\MySysGen\\PCIe_UserLogic_00.mdl',
55 
    'device' => 'xc6vlx240t-3ff784',
56 
    'device_speed' => -3,
57 
    'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
58 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
59 
    'entityNamingInstrs' => {
60 
      'nameMap' => undef,
61 
      'namesAlreadyUsed' => {
62 
        'default_clock_driver' => 1,
63 
        'inout_logic_cw' => 1,
64 
      },
65 
    },
66 
    'eval_field' => 0,
67 
    'fileAttributes' => {
68 
      'nonleaf_results.vhd' => {
69 
        'producer' => 'nonleafNetlister',
70 
      },
71 
    },
72 
    'files' => [
73 
      'xlpersistentdff.ngc',
74 
      'synopsis',
75 
      'inout_logic.vhd',
76 
      'xlpersistentdff.ngc',
77 
      'inout_logic_cw.vhd',
78 
      'inout_logic_cw.ucf',
79 
      'inout_logic_cw.xcf',
80 
      'inout_logic_cw.sdc',
81 
      'xst_inout_logic.prj',
82 
      'xst_inout_logic.scr',
83 
      'vcom.do',
84 
      'isim_inout_logic.prj',
85 
      'globals',
86 
      'hdlFiles',
87 
    ],
88 
    'fxdptinstalled' => 1,
89 
    'generateUsing71FrontEnd' => 1,
90 
    'generating_island_subsystem_handle' => 4.0009765625,
91 
    'generating_subsystem_handle' => 4.0009765625,
92 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
93 
    'has_advanced_control' => 0,
94 
    'hdlDir' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl',
95 
    'hdlKind' => 'vhdl',
96 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
97 
    'impl_file' => 'ISE Defaults*',
98 
    'incr_netlist' => 'off',
99 
    'incr_netlist_sgadvanced' => '',
100 
    'infoedit' => ' System Generator',
101 
    'isCombinatorial' => 1,
102 
    'isdeployed' => 0,
103 
    'ise_version' => '12.3i',
104 
    'master_sysgen_token_handle' => 5.0009765625,
105 
    'matlab' => 'C:/Programmi/MATLAB/R2010a',
106 
    'matlab_fixedpoint' => 1,
107 
    'mdlHandle' => 3.0009765625,
108 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
109 
    'modelDiagnostics' => [
110 
      {
111 
        'count' => 339,
112 
        'isMask' => 0,
113 
        'type' => 'PCIe_UserLogic_00 Total blocks',
114 
      },
115 
      {
116 
        'count' => 4,
117 
        'isMask' => 0,
118 
        'type' => 'DiscretePulseGenerator',
119 
      },
120 
      {
121 
        'count' => 327,
122 
        'isMask' => 0,
123 
        'type' => 'S-Function',
124 
      },
125 
      {
126 
        'count' => 4,
127 
        'isMask' => 0,
128 
        'type' => 'SubSystem',
129 
      },
130 
      {
131 
        'count' => 4,
132 
        'isMask' => 0,
133 
        'type' => 'Terminator',
134 
      },
135 
      {
136 
        'count' => 23,
137 
        'isMask' => 1,
138 
        'type' => 'Xilinx Constant Block Block',
139 
      },
140 
      {
141 
        'count' => 1,
142 
        'isMask' => 1,
143 
        'type' => 'Xilinx Counter Block',
144 
      },
145 
      {
146 
        'count' => 44,
147 
        'isMask' => 1,
148 
        'type' => 'Xilinx Gateway In Block',
149 
      },
150 
      {
151 
        'count' => 39,
152 
        'isMask' => 1,
153 
        'type' => 'Xilinx Gateway Out Block',
154 
      },
155 
      {
156 
        'count' => 2,
157 
        'isMask' => 1,
158 
        'type' => 'Xilinx Inverter Block',
159 
      },
160 
      {
161 
        'count' => 1,
162 
        'isMask' => 1,
163 
        'type' => 'Xilinx Logical Block Block',
164 
      },
165 
      {
166 
        'count' => 78,
167 
        'isMask' => 1,
168 
        'type' => 'Xilinx Register Block',
169 
      },
170 
      {
171 
        'count' => 62,
172 
        'isMask' => 1,
173 
        'type' => 'Xilinx Shared Memory Based From Register Block',
174 
      },
175 
      {
176 
        'count' => 62,
177 
        'isMask' => 1,
178 
        'type' => 'Xilinx Shared Memory Based To Register Block',
179 
      },
180 
      {
181 
        'count' => 1,
182 
        'isMask' => 1,
183 
        'type' => 'Xilinx Subsystem Generator Block',
184 
      },
185 
      {
186 
        'count' => 2,
187 
        'isMask' => 1,
188 
        'type' => 'Xilinx System Generator Block',
189 
      },
190 
      {
191 
        'count' => 14,
192 
        'isMask' => 1,
193 
        'type' => 'Xilinx Type Converter Block',
194 
      },
195 
    ],
196 
    'model_globals_initialized' => 1,
197 
    'model_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
198 
    'myxilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
199 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
200 
    'ngc_config' => {
201 
      'include_cf' => 1,
202 
      'include_clockwrapper' => 1,
203 
    },
204 
    'ngc_files' => [
205 
      'xlpersistentdff.ngc',
206 
    ],
207 
    'num_sim_cycles' => 1250000000,
208 
    'package' => 'ff784',
209 
    'part' => 'xc6vlx240t',
210 
    'partFamily' => 'virtex6',
211 
    'port_data_types_enabled' => 1,
212 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
213 
    'preserve_hierarchy' => 0,
214 
    'proj_type' => 'Project Navigator',
215 
    'proj_type_sgadvanced' => '',
216 
    'run_coregen' => 'off',
217 
    'run_coregen_sgadvanced' => '',
218 
    'sample_time_colors_enabled' => 1,
219 
    'sampletimecolors' => 1,
220 
    'sdcFile' => 'inout_logic_cw.sdc',
221 
    'settings_fcn' => 'xlngcsettings',
222 
    'sg_blockgui_xml' => '',
223 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
224 
    'sg_list_contents' => '',
225 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
226 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
227 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
228 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
229 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
230 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
231 
fprintf(\'\',\'COMMENT: end icon graphics\');
232 
fprintf(\'\',\'COMMENT: begin icon text\');
233 
fprintf(\'\',\'COMMENT: end icon text\');',
234 
    'sg_version' => '',
235 
    'sggui_pos' => '-1,-1,-1,-1',
236 
    'simulation_island_subsystem_handle' => 4.0009765625,
237 
    'simulinkName' => 'parking_lot',
238 
    'simulink_accelerator_running' => 0,
239 
    'simulink_debugger_running' => 0,
240 
    'simulink_period' => '8e-009',
241 
    'speed' => -3,
242 
    'synth_file' => 'XST Defaults*',
243 
    'synthesisTool' => 'XST',
244 
    'synthesis_language' => 'vhdl',
245 
    'synthesis_tool' => 'XST',
246 
    'synthesis_tool_sgadvanced' => '',
247 
    'sysclk_period' => 5,
248 
    'sysgen' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
249 
    'sysgenRoot' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
250 
    'sysgenTokenSettings' => {
251 
      'Impl_file' => 'ISE Defaults',
252 
      'Impl_file_sgadvanced' => '',
253 
      'Synth_file' => 'XST Defaults',
254 
      'Synth_file_sgadvanced' => '',
255 
      'base_system_period_hardware' => 5,
256 
      'base_system_period_simulink' => '8e-009',
257 
      'block_icon_display' => 'Default',
258 
      'block_type' => 'sysgen',
259 
      'block_version' => '',
260 
      'ce_clr' => 0,
261 
      'clock_loc' => '',
262 
      'clock_wrapper' => 'Clock Enables',
263 
      'clock_wrapper_sgadvanced' => '',
264 
      'compilation' => 'NGC Netlist',
265 
      'compilation_lut' => {
266 
        'keys' => [
267 
          'HDL Netlist',
268 
          'Bitstream',
269 
          'NGC Netlist',
270 
        ],
271 
        'values' => [
272 
          'target1',
273 
          'target2',
274 
          'target3',
275 
        ],
276 
      },
277 
      'core_generation' => 1,
278 
      'core_generation_sgadvanced' => '',
279 
      'coregen_part_family' => 'virtex6',
280 
      'create_interface_document' => 'off',
281 
      'dbl_ovrd' => -1,
282 
      'dbl_ovrd_sgadvanced' => '',
283 
      'dcm_input_clock_period' => 5,
284 
      'deprecated_control' => 'off',
285 
      'deprecated_control_sgadvanced' => '',
286 
      'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
287 
      'eval_field' => 0,
288 
      'has_advanced_control' => 0,
289 
      'impl_file' => 'ISE Defaults*',
290 
      'incr_netlist' => 'off',
291 
      'incr_netlist_sgadvanced' => '',
292 
      'infoedit' => ' System Generator',
293 
      'master_sysgen_token_handle' => 5.0009765625,
294 
      'ngc_config' => {
295 
        'include_cf' => 1,
296 
        'include_clockwrapper' => 1,
297 
      },
298 
      'package' => 'ff784',
299 
      'part' => 'xc6vlx240t',
300 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
301 
      'preserve_hierarchy' => 0,
302 
      'proj_type' => 'Project Navigator',
303 
      'proj_type_sgadvanced' => '',
304 
      'run_coregen' => 'off',
305 
      'run_coregen_sgadvanced' => '',
306 
      'settings_fcn' => 'xlngcsettings',
307 
      'sg_blockgui_xml' => '',
308 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
309 
      'sg_list_contents' => '',
310 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
311 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
312 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
313 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
314 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
315 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
316 
fprintf(\'\',\'COMMENT: end icon graphics\');
317 
fprintf(\'\',\'COMMENT: begin icon text\');
318 
fprintf(\'\',\'COMMENT: end icon text\');',
319 
      'sggui_pos' => '-1,-1,-1,-1',
320 
      'simulation_island_subsystem_handle' => 4.0009765625,
321 
      'simulink_period' => '8e-009',
322 
      'speed' => -3,
323 
      'synth_file' => 'XST Defaults*',
324 
      'synthesis_language' => 'vhdl',
325 
      'synthesis_tool' => 'XST',
326 
      'synthesis_tool_sgadvanced' => '',
327 
      'sysclk_period' => 5,
328 
      'testbench' => 0,
329 
      'testbench_sgadvanced' => '',
330 
      'trim_vbits' => 1,
331 
      'trim_vbits_sgadvanced' => '',
332 
      'xilinx_device' => 'xc6vlx240t-3ff784',
333 
      'xilinxfamily' => 'virtex6',
334 
    },
335 
    'sysgen_Root' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
336 
    'systemClockPeriod' => 5,
337 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
338 
    'testbench' => 0,
339 
    'testbench_sgadvanced' => '',
340 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/sysgen',
341 
    'trim_vbits' => 1,
342 
    'trim_vbits_sgadvanced' => '',
343 
    'ucfFile' => 'inout_logic_cw.ucf',
344 
    'use_ce_syn_keep' => 1,
345 
    'use_strict_names' => 1,
346 
    'user_tips_enabled' => 0,
347 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
348 
    'using71Netlister' => 1,
349 
    'verilog_files' => [
350 
      'conv_pkg.v',
351 
      'synth_reg.v',
352 
      'synth_reg_w_init.v',
353 
      'convert_type.v',
354 
    ],
355 
    'version' => '',
356 
    'vhdl_files' => [
357 
      'conv_pkg.vhd',
358 
      'synth_reg.vhd',
359 
      'synth_reg_w_init.vhd',
360 
    ],
361 
    'vsimtime' => '6875000275.000000 ns',
362 
    'xcfFile' => 'inout_logic_cw.xcf',
363 
    'xilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
364 
    'xilinx_device' => 'xc6vlx240t-3ff784',
365 
    'xilinx_family' => 'virtex6',
366 
    'xilinx_package' => 'ff784',
367 
    'xilinx_part' => 'xc6vlx240t',
368 
    'xilinxdevice' => 'xc6vlx240t-3ff784',
369 
    'xilinxfamily' => 'virtex6',
370 
    'xilinxpart' => 'xc6vlx240t',
371 
  },
372 
  'entityName' => '',
373 
  'nets' => {
374 
    '.clk' => {
375 
      'hdlType' => 'std_logic',
376 
      'width' => 1,
377 
    },
378 
    '.debug_in_1i' => {
379 
      'hdlType' => 'std_logic_vector(31 downto 0)',
380 
      'width' => 32,
381 
    },
382 
    '.debug_in_2i' => {
383 
      'hdlType' => 'std_logic_vector(31 downto 0)',
384 
      'width' => 32,
385 
    },
386 
    '.debug_in_3i' => {
387 
      'hdlType' => 'std_logic_vector(31 downto 0)',
388 
      'width' => 32,
389 
    },
390 
    '.debug_in_4i' => {
391 
      'hdlType' => 'std_logic_vector(31 downto 0)',
392 
      'width' => 32,
393 
    },
394 
    '.dma_host2board_busy' => {
395 
      'hdlType' => 'std_logic',
396 
      'width' => 1,
397 
    },
398 
    '.dma_host2board_done' => {
399 
      'hdlType' => 'std_logic',
400 
      'width' => 1,
401 
    },
402 
    '.reg01_td' => {
403 
      'hdlType' => 'std_logic_vector(31 downto 0)',
404 
      'width' => 32,
405 
    },
406 
    '.reg01_tv' => {
407 
      'hdlType' => 'std_logic',
408 
      'width' => 1,
409 
    },
410 
    '.reg02_td' => {
411 
      'hdlType' => 'std_logic_vector(31 downto 0)',
412 
      'width' => 32,
413 
    },
414 
    '.reg02_tv' => {
415 
      'hdlType' => 'std_logic',
416 
      'width' => 1,
417 
    },
418 
    '.reg03_td' => {
419 
      'hdlType' => 'std_logic_vector(31 downto 0)',
420 
      'width' => 32,
421 
    },
422 
    '.reg03_tv' => {
423 
      'hdlType' => 'std_logic',
424 
      'width' => 1,
425 
    },
426 
    '.reg04_td' => {
427 
      'hdlType' => 'std_logic_vector(31 downto 0)',
428 
      'width' => 32,
429 
    },
430 
    '.reg04_tv' => {
431 
      'hdlType' => 'std_logic',
432 
      'width' => 1,
433 
    },
434 
    '.reg05_td' => {
435 
      'hdlType' => 'std_logic_vector(31 downto 0)',
436 
      'width' => 32,
437 
    },
438 
    '.reg05_tv' => {
439 
      'hdlType' => 'std_logic',
440 
      'width' => 1,
441 
    },
442 
    '.reg06_td' => {
443 
      'hdlType' => 'std_logic_vector(31 downto 0)',
444 
      'width' => 32,
445 
    },
446 
    '.reg06_tv' => {
447 
      'hdlType' => 'std_logic',
448 
      'width' => 1,
449 
    },
450 
    '.reg07_td' => {
451 
      'hdlType' => 'std_logic_vector(31 downto 0)',
452 
      'width' => 32,
453 
    },
454 
    '.reg07_tv' => {
455 
      'hdlType' => 'std_logic',
456 
      'width' => 1,
457 
    },
458 
    '.reg08_td' => {
459 
      'hdlType' => 'std_logic_vector(31 downto 0)',
460 
      'width' => 32,
461 
    },
462 
    '.reg08_tv' => {
463 
      'hdlType' => 'std_logic',
464 
      'width' => 1,
465 
    },
466 
    '.reg09_td' => {
467 
      'hdlType' => 'std_logic_vector(31 downto 0)',
468 
      'width' => 32,
469 
    },
470 
    '.reg09_tv' => {
471 
      'hdlType' => 'std_logic',
472 
      'width' => 1,
473 
    },
474 
    '.reg10_td' => {
475 
      'hdlType' => 'std_logic_vector(31 downto 0)',
476 
      'width' => 32,
477 
    },
478 
    '.reg10_tv' => {
479 
      'hdlType' => 'std_logic',
480 
      'width' => 1,
481 
    },
482 
    '.reg11_td' => {
483 
      'hdlType' => 'std_logic_vector(31 downto 0)',
484 
      'width' => 32,
485 
    },
486 
    '.reg11_tv' => {
487 
      'hdlType' => 'std_logic',
488 
      'width' => 1,
489 
    },
490 
    '.reg12_td' => {
491 
      'hdlType' => 'std_logic_vector(31 downto 0)',
492 
      'width' => 32,
493 
    },
494 
    '.reg12_tv' => {
495 
      'hdlType' => 'std_logic',
496 
      'width' => 1,
497 
    },
498 
    '.reg13_td' => {
499 
      'hdlType' => 'std_logic_vector(31 downto 0)',
500 
      'width' => 32,
501 
    },
502 
    '.reg13_tv' => {
503 
      'hdlType' => 'std_logic',
504 
      'width' => 1,
505 
    },
506 
    '.reg14_td' => {
507 
      'hdlType' => 'std_logic_vector(31 downto 0)',
508 
      'width' => 32,
509 
    },
510 
    '.reg14_tv' => {
511 
      'hdlType' => 'std_logic',
512 
      'width' => 1,
513 
    },
514 
    'from_register1.data_out' => {
515 
      'hdlType' => 'std_logic',
516 
      'width' => 1,
517 
    },
518 
    'from_register10.data_out' => {
519 
      'hdlType' => 'std_logic_vector(31 downto 0)',
520 
      'width' => 32,
521 
    },
522 
    'from_register11.data_out' => {
523 
      'hdlType' => 'std_logic_vector(31 downto 0)',
524 
      'width' => 32,
525 
    },
526 
    'from_register12.data_out' => {
527 
      'hdlType' => 'std_logic',
528 
      'width' => 1,
529 
    },
530 
    'from_register13.data_out' => {
531 
      'hdlType' => 'std_logic_vector(31 downto 0)',
532 
      'width' => 32,
533 
    },
534 
    'from_register14.data_out' => {
535 
      'hdlType' => 'std_logic',
536 
      'width' => 1,
537 
    },
538 
    'from_register15.data_out' => {
539 
      'hdlType' => 'std_logic_vector(31 downto 0)',
540 
      'width' => 32,
541 
    },
542 
    'from_register16.data_out' => {
543 
      'hdlType' => 'std_logic',
544 
      'width' => 1,
545 
    },
546 
    'from_register17.data_out' => {
547 
      'hdlType' => 'std_logic_vector(31 downto 0)',
548 
      'width' => 32,
549 
    },
550 
    'from_register18.data_out' => {
551 
      'hdlType' => 'std_logic',
552 
      'width' => 1,
553 
    },
554 
    'from_register19.data_out' => {
555 
      'hdlType' => 'std_logic_vector(31 downto 0)',
556 
      'width' => 32,
557 
    },
558 
    'from_register2.data_out' => {
559 
      'hdlType' => 'std_logic',
560 
      'width' => 1,
561 
    },
562 
    'from_register20.data_out' => {
563 
      'hdlType' => 'std_logic',
564 
      'width' => 1,
565 
    },
566 
    'from_register21.data_out' => {
567 
      'hdlType' => 'std_logic_vector(31 downto 0)',
568 
      'width' => 32,
569 
    },
570 
    'from_register22.data_out' => {
571 
      'hdlType' => 'std_logic',
572 
      'width' => 1,
573 
    },
574 
    'from_register23.data_out' => {
575 
      'hdlType' => 'std_logic_vector(31 downto 0)',
576 
      'width' => 32,
577 
    },
578 
    'from_register24.data_out' => {
579 
      'hdlType' => 'std_logic',
580 
      'width' => 1,
581 
    },
582 
    'from_register25.data_out' => {
583 
      'hdlType' => 'std_logic_vector(31 downto 0)',
584 
      'width' => 32,
585 
    },
586 
    'from_register26.data_out' => {
587 
      'hdlType' => 'std_logic',
588 
      'width' => 1,
589 
    },
590 
    'from_register27.data_out' => {
591 
      'hdlType' => 'std_logic_vector(31 downto 0)',
592 
      'width' => 32,
593 
    },
594 
    'from_register28.data_out' => {
595 
      'hdlType' => 'std_logic',
596 
      'width' => 1,
597 
    },
598 
    'from_register3.data_out' => {
599 
      'hdlType' => 'std_logic_vector(31 downto 0)',
600 
      'width' => 32,
601 
    },
602 
    'from_register4.data_out' => {
603 
      'hdlType' => 'std_logic',
604 
      'width' => 1,
605 
    },
606 
    'from_register5.data_out' => {
607 
      'hdlType' => 'std_logic_vector(31 downto 0)',
608 
      'width' => 32,
609 
    },
610 
    'from_register6.data_out' => {
611 
      'hdlType' => 'std_logic',
612 
      'width' => 1,
613 
    },
614 
    'from_register7.data_out' => {
615 
      'hdlType' => 'std_logic_vector(31 downto 0)',
616 
      'width' => 32,
617 
    },
618 
    'from_register8.data_out' => {
619 
      'hdlType' => 'std_logic_vector(31 downto 0)',
620 
      'width' => 32,
621 
    },
622 
    'from_register9.data_out' => {
623 
      'hdlType' => 'std_logic',
624 
      'width' => 1,
625 
    },
626 
    'sysgen_dut.reg01_rd' => {
627 
      'hdlType' => 'std_logic_vector(31 downto 0)',
628 
      'width' => 32,
629 
    },
630 
    'sysgen_dut.reg01_rv' => {
631 
      'hdlType' => 'std_logic',
632 
      'width' => 1,
633 
    },
634 
    'sysgen_dut.reg02_rd' => {
635 
      'hdlType' => 'std_logic_vector(31 downto 0)',
636 
      'width' => 32,
637 
    },
638 
    'sysgen_dut.reg02_rv' => {
639 
      'hdlType' => 'std_logic',
640 
      'width' => 1,
641 
    },
642 
    'sysgen_dut.reg03_rd' => {
643 
      'hdlType' => 'std_logic_vector(31 downto 0)',
644 
      'width' => 32,
645 
    },
646 
    'sysgen_dut.reg03_rv' => {
647 
      'hdlType' => 'std_logic',
648 
      'width' => 1,
649 
    },
650 
    'sysgen_dut.reg04_rd' => {
651 
      'hdlType' => 'std_logic_vector(31 downto 0)',
652 
      'width' => 32,
653 
    },
654 
    'sysgen_dut.reg04_rv' => {
655 
      'hdlType' => 'std_logic',
656 
      'width' => 1,
657 
    },
658 
    'sysgen_dut.reg05_rd' => {
659 
      'hdlType' => 'std_logic_vector(31 downto 0)',
660 
      'width' => 32,
661 
    },
662 
    'sysgen_dut.reg05_rv' => {
663 
      'hdlType' => 'std_logic',
664 
      'width' => 1,
665 
    },
666 
    'sysgen_dut.reg06_rd' => {
667 
      'hdlType' => 'std_logic_vector(31 downto 0)',
668 
      'width' => 32,
669 
    },
670 
    'sysgen_dut.reg06_rv' => {
671 
      'hdlType' => 'std_logic',
672 
      'width' => 1,
673 
    },
674 
    'sysgen_dut.reg07_rd' => {
675 
      'hdlType' => 'std_logic_vector(31 downto 0)',
676 
      'width' => 32,
677 
    },
678 
    'sysgen_dut.reg07_rv' => {
679 
      'hdlType' => 'std_logic',
680 
      'width' => 1,
681 
    },
682 
    'sysgen_dut.reg08_rd' => {
683 
      'hdlType' => 'std_logic_vector(31 downto 0)',
684 
      'width' => 32,
685 
    },
686 
    'sysgen_dut.reg08_rv' => {
687 
      'hdlType' => 'std_logic',
688 
      'width' => 1,
689 
    },
690 
    'sysgen_dut.reg09_rd' => {
691 
      'hdlType' => 'std_logic_vector(31 downto 0)',
692 
      'width' => 32,
693 
    },
694 
    'sysgen_dut.reg09_rv' => {
695 
      'hdlType' => 'std_logic',
696 
      'width' => 1,
697 
    },
698 
    'sysgen_dut.reg10_rd' => {
699 
      'hdlType' => 'std_logic_vector(31 downto 0)',
700 
      'width' => 32,
701 
    },
702 
    'sysgen_dut.reg10_rv' => {
703 
      'hdlType' => 'std_logic',
704 
      'width' => 1,
705 
    },
706 
    'sysgen_dut.reg11_rd' => {
707 
      'hdlType' => 'std_logic_vector(31 downto 0)',
708 
      'width' => 32,
709 
    },
710 
    'sysgen_dut.reg11_rv' => {
711 
      'hdlType' => 'std_logic',
712 
      'width' => 1,
713 
    },
714 
    'sysgen_dut.reg12_rd' => {
715 
      'hdlType' => 'std_logic_vector(31 downto 0)',
716 
      'width' => 32,
717 
    },
718 
    'sysgen_dut.reg12_rv' => {
719 
      'hdlType' => 'std_logic',
720 
      'width' => 1,
721 
    },
722 
    'sysgen_dut.reg13_rd' => {
723 
      'hdlType' => 'std_logic_vector(31 downto 0)',
724 
      'width' => 32,
725 
    },
726 
    'sysgen_dut.reg13_rv' => {
727 
      'hdlType' => 'std_logic',
728 
      'width' => 1,
729 
    },
730 
    'sysgen_dut.reg14_rd' => {
731 
      'hdlType' => 'std_logic_vector(31 downto 0)',
732 
      'width' => 32,
733 
    },
734 
    'sysgen_dut.reg14_rv' => {
735 
      'hdlType' => 'std_logic',
736 
      'width' => 1,
737 
    },
738 
    'sysgen_dut.to_register10_ce' => {
739 
      'hdlType' => 'std_logic',
740 
      'width' => 1,
741 
    },
742 
    'sysgen_dut.to_register10_clk' => {
743 
      'hdlType' => 'std_logic',
744 
      'width' => 1,
745 
    },
746 
    'sysgen_dut.to_register10_clr' => {
747 
      'hdlType' => 'std_logic',
748 
      'width' => 1,
749 
    },
750 
    'sysgen_dut.to_register10_data_in' => {
751 
      'hdlType' => 'std_logic',
752 
      'width' => 1,
753 
    },
754 
    'sysgen_dut.to_register10_en' => {
755 
      'hdlType' => 'std_logic',
756 
      'width' => 1,
757 
    },
758 
    'sysgen_dut.to_register11_ce' => {
759 
      'hdlType' => 'std_logic',
760 
      'width' => 1,
761 
    },
762 
    'sysgen_dut.to_register11_clk' => {
763 
      'hdlType' => 'std_logic',
764 
      'width' => 1,
765 
    },
766 
    'sysgen_dut.to_register11_clr' => {
767 
      'hdlType' => 'std_logic',
768 
      'width' => 1,
769 
    },
770 
    'sysgen_dut.to_register11_data_in' => {
771 
      'hdlType' => 'std_logic_vector(31 downto 0)',
772 
      'width' => 32,
773 
    },
774 
    'sysgen_dut.to_register11_en' => {
775 
      'hdlType' => 'std_logic',
776 
      'width' => 1,
777 
    },
778 
    'sysgen_dut.to_register12_ce' => {
779 
      'hdlType' => 'std_logic',
780 
      'width' => 1,
781 
    },
782 
    'sysgen_dut.to_register12_clk' => {
783 
      'hdlType' => 'std_logic',
784 
      'width' => 1,
785 
    },
786 
    'sysgen_dut.to_register12_clr' => {
787 
      'hdlType' => 'std_logic',
788 
      'width' => 1,
789 
    },
790 
    'sysgen_dut.to_register12_data_in' => {
791 
      'hdlType' => 'std_logic',
792 
      'width' => 1,
793 
    },
794 
    'sysgen_dut.to_register12_en' => {
795 
      'hdlType' => 'std_logic',
796 
      'width' => 1,
797 
    },
798 
    'sysgen_dut.to_register13_ce' => {
799 
      'hdlType' => 'std_logic',
800 
      'width' => 1,
801 
    },
802 
    'sysgen_dut.to_register13_clk' => {
803 
      'hdlType' => 'std_logic',
804 
      'width' => 1,
805 
    },
806 
    'sysgen_dut.to_register13_clr' => {
807 
      'hdlType' => 'std_logic',
808 
      'width' => 1,
809 
    },
810 
    'sysgen_dut.to_register13_data_in' => {
811 
      'hdlType' => 'std_logic_vector(31 downto 0)',
812 
      'width' => 32,
813 
    },
814 
    'sysgen_dut.to_register13_en' => {
815 
      'hdlType' => 'std_logic',
816 
      'width' => 1,
817 
    },
818 
    'sysgen_dut.to_register14_ce' => {
819 
      'hdlType' => 'std_logic',
820 
      'width' => 1,
821 
    },
822 
    'sysgen_dut.to_register14_clk' => {
823 
      'hdlType' => 'std_logic',
824 
      'width' => 1,
825 
    },
826 
    'sysgen_dut.to_register14_clr' => {
827 
      'hdlType' => 'std_logic',
828 
      'width' => 1,
829 
    },
830 
    'sysgen_dut.to_register14_data_in' => {
831 
      'hdlType' => 'std_logic',
832 
      'width' => 1,
833 
    },
834 
    'sysgen_dut.to_register14_en' => {
835 
      'hdlType' => 'std_logic',
836 
      'width' => 1,
837 
    },
838 
    'sysgen_dut.to_register15_ce' => {
839 
      'hdlType' => 'std_logic',
840 
      'width' => 1,
841 
    },
842 
    'sysgen_dut.to_register15_clk' => {
843 
      'hdlType' => 'std_logic',
844 
      'width' => 1,
845 
    },
846 
    'sysgen_dut.to_register15_clr' => {
847 
      'hdlType' => 'std_logic',
848 
      'width' => 1,
849 
    },
850 
    'sysgen_dut.to_register15_data_in' => {
851 
      'hdlType' => 'std_logic_vector(31 downto 0)',
852 
      'width' => 32,
853 
    },
854 
    'sysgen_dut.to_register15_en' => {
855 
      'hdlType' => 'std_logic',
856 
      'width' => 1,
857 
    },
858 
    'sysgen_dut.to_register16_ce' => {
859 
      'hdlType' => 'std_logic',
860 
      'width' => 1,
861 
    },
862 
    'sysgen_dut.to_register16_clk' => {
863 
      'hdlType' => 'std_logic',
864 
      'width' => 1,
865 
    },
866 
    'sysgen_dut.to_register16_clr' => {
867 
      'hdlType' => 'std_logic',
868 
      'width' => 1,
869 
    },
870 
    'sysgen_dut.to_register16_data_in' => {
871 
      'hdlType' => 'std_logic',
872 
      'width' => 1,
873 
    },
874 
    'sysgen_dut.to_register16_en' => {
875 
      'hdlType' => 'std_logic',
876 
      'width' => 1,
877 
    },
878 
    'sysgen_dut.to_register17_ce' => {
879 
      'hdlType' => 'std_logic',
880 
      'width' => 1,
881 
    },
882 
    'sysgen_dut.to_register17_clk' => {
883 
      'hdlType' => 'std_logic',
884 
      'width' => 1,
885 
    },
886 
    'sysgen_dut.to_register17_clr' => {
887 
      'hdlType' => 'std_logic',
888 
      'width' => 1,
889 
    },
890 
    'sysgen_dut.to_register17_data_in' => {
891 
      'hdlType' => 'std_logic_vector(31 downto 0)',
892 
      'width' => 32,
893 
    },
894 
    'sysgen_dut.to_register17_en' => {
895 
      'hdlType' => 'std_logic',
896 
      'width' => 1,
897 
    },
898 
    'sysgen_dut.to_register18_ce' => {
899 
      'hdlType' => 'std_logic',
900 
      'width' => 1,
901 
    },
902 
    'sysgen_dut.to_register18_clk' => {
903 
      'hdlType' => 'std_logic',
904 
      'width' => 1,
905 
    },
906 
    'sysgen_dut.to_register18_clr' => {
907 
      'hdlType' => 'std_logic',
908 
      'width' => 1,
909 
    },
910 
    'sysgen_dut.to_register18_data_in' => {
911 
      'hdlType' => 'std_logic',
912 
      'width' => 1,
913 
    },
914 
    'sysgen_dut.to_register18_en' => {
915 
      'hdlType' => 'std_logic',
916 
      'width' => 1,
917 
    },
918 
    'sysgen_dut.to_register19_ce' => {
919 
      'hdlType' => 'std_logic',
920 
      'width' => 1,
921 
    },
922 
    'sysgen_dut.to_register19_clk' => {
923 
      'hdlType' => 'std_logic',
924 
      'width' => 1,
925 
    },
926 
    'sysgen_dut.to_register19_clr' => {
927 
      'hdlType' => 'std_logic',
928 
      'width' => 1,
929 
    },
930 
    'sysgen_dut.to_register19_data_in' => {
931 
      'hdlType' => 'std_logic',
932 
      'width' => 1,
933 
    },
934 
    'sysgen_dut.to_register19_en' => {
935 
      'hdlType' => 'std_logic',
936 
      'width' => 1,
937 
    },
938 
    'sysgen_dut.to_register1_ce' => {
939 
      'hdlType' => 'std_logic',
940 
      'width' => 1,
941 
    },
942 
    'sysgen_dut.to_register1_clk' => {
943 
      'hdlType' => 'std_logic',
944 
      'width' => 1,
945 
    },
946 
    'sysgen_dut.to_register1_clr' => {
947 
      'hdlType' => 'std_logic',
948 
      'width' => 1,
949 
    },
950 
    'sysgen_dut.to_register1_data_in' => {
951 
      'hdlType' => 'std_logic_vector(31 downto 0)',
952 
      'width' => 32,
953 
    },
954 
    'sysgen_dut.to_register1_en' => {
955 
      'hdlType' => 'std_logic',
956 
      'width' => 1,
957 
    },
958 
    'sysgen_dut.to_register20_ce' => {
959 
      'hdlType' => 'std_logic',
960 
      'width' => 1,
961 
    },
962 
    'sysgen_dut.to_register20_clk' => {
963 
      'hdlType' => 'std_logic',
964 
      'width' => 1,
965 
    },
966 
    'sysgen_dut.to_register20_clr' => {
967 
      'hdlType' => 'std_logic',
968 
      'width' => 1,
969 
    },
970 
    'sysgen_dut.to_register20_data_in' => {
971 
      'hdlType' => 'std_logic_vector(31 downto 0)',
972 
      'width' => 32,
973 
    },
974 
    'sysgen_dut.to_register20_en' => {
975 
      'hdlType' => 'std_logic',
976 
      'width' => 1,
977 
    },
978 
    'sysgen_dut.to_register21_ce' => {
979 
      'hdlType' => 'std_logic',
980 
      'width' => 1,
981 
    },
982 
    'sysgen_dut.to_register21_clk' => {
983 
      'hdlType' => 'std_logic',
984 
      'width' => 1,
985 
    },
986 
    'sysgen_dut.to_register21_clr' => {
987 
      'hdlType' => 'std_logic',
988 
      'width' => 1,
989 
    },
990 
    'sysgen_dut.to_register21_data_in' => {
991 
      'hdlType' => 'std_logic',
992 
      'width' => 1,
993 
    },
994 
    'sysgen_dut.to_register21_en' => {
995 
      'hdlType' => 'std_logic',
996 
      'width' => 1,
997 
    },
998 
    'sysgen_dut.to_register22_ce' => {
999 
      'hdlType' => 'std_logic',
1000 
      'width' => 1,
1001 
    },
1002 
    'sysgen_dut.to_register22_clk' => {
1003 
      'hdlType' => 'std_logic',
1004 
      'width' => 1,
1005 
    },
1006 
    'sysgen_dut.to_register22_clr' => {
1007 
      'hdlType' => 'std_logic',
1008 
      'width' => 1,
1009 
    },
1010 
    'sysgen_dut.to_register22_data_in' => {
1011 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1012 
      'width' => 32,
1013 
    },
1014 
    'sysgen_dut.to_register22_en' => {
1015 
      'hdlType' => 'std_logic',
1016 
      'width' => 1,
1017 
    },
1018 
    'sysgen_dut.to_register23_ce' => {
1019 
      'hdlType' => 'std_logic',
1020 
      'width' => 1,
1021 
    },
1022 
    'sysgen_dut.to_register23_clk' => {
1023 
      'hdlType' => 'std_logic',
1024 
      'width' => 1,
1025 
    },
1026 
    'sysgen_dut.to_register23_clr' => {
1027 
      'hdlType' => 'std_logic',
1028 
      'width' => 1,
1029 
    },
1030 
    'sysgen_dut.to_register23_data_in' => {
1031 
      'hdlType' => 'std_logic',
1032 
      'width' => 1,
1033 
    },
1034 
    'sysgen_dut.to_register23_en' => {
1035 
      'hdlType' => 'std_logic',
1036 
      'width' => 1,
1037 
    },
1038 
    'sysgen_dut.to_register24_ce' => {
1039 
      'hdlType' => 'std_logic',
1040 
      'width' => 1,
1041 
    },
1042 
    'sysgen_dut.to_register24_clk' => {
1043 
      'hdlType' => 'std_logic',
1044 
      'width' => 1,
1045 
    },
1046 
    'sysgen_dut.to_register24_clr' => {
1047 
      'hdlType' => 'std_logic',
1048 
      'width' => 1,
1049 
    },
1050 
    'sysgen_dut.to_register24_data_in' => {
1051 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1052 
      'width' => 32,
1053 
    },
1054 
    'sysgen_dut.to_register24_en' => {
1055 
      'hdlType' => 'std_logic',
1056 
      'width' => 1,
1057 
    },
1058 
    'sysgen_dut.to_register25_ce' => {
1059 
      'hdlType' => 'std_logic',
1060 
      'width' => 1,
1061 
    },
1062 
    'sysgen_dut.to_register25_clk' => {
1063 
      'hdlType' => 'std_logic',
1064 
      'width' => 1,
1065 
    },
1066 
    'sysgen_dut.to_register25_clr' => {
1067 
      'hdlType' => 'std_logic',
1068 
      'width' => 1,
1069 
    },
1070 
    'sysgen_dut.to_register25_data_in' => {
1071 
      'hdlType' => 'std_logic',
1072 
      'width' => 1,
1073 
    },
1074 
    'sysgen_dut.to_register25_en' => {
1075 
      'hdlType' => 'std_logic',
1076 
      'width' => 1,
1077 
    },
1078 
    'sysgen_dut.to_register26_ce' => {
1079 
      'hdlType' => 'std_logic',
1080 
      'width' => 1,
1081 
    },
1082 
    'sysgen_dut.to_register26_clk' => {
1083 
      'hdlType' => 'std_logic',
1084 
      'width' => 1,
1085 
    },
1086 
    'sysgen_dut.to_register26_clr' => {
1087 
      'hdlType' => 'std_logic',
1088 
      'width' => 1,
1089 
    },
1090 
    'sysgen_dut.to_register26_data_in' => {
1091 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1092 
      'width' => 32,
1093 
    },
1094 
    'sysgen_dut.to_register26_en' => {
1095 
      'hdlType' => 'std_logic',
1096 
      'width' => 1,
1097 
    },
1098 
    'sysgen_dut.to_register27_ce' => {
1099 
      'hdlType' => 'std_logic',
1100 
      'width' => 1,
1101 
    },
1102 
    'sysgen_dut.to_register27_clk' => {
1103 
      'hdlType' => 'std_logic',
1104 
      'width' => 1,
1105 
    },
1106 
    'sysgen_dut.to_register27_clr' => {
1107 
      'hdlType' => 'std_logic',
1108 
      'width' => 1,
1109 
    },
1110 
    'sysgen_dut.to_register27_data_in' => {
1111 
      'hdlType' => 'std_logic',
1112 
      'width' => 1,
1113 
    },
1114 
    'sysgen_dut.to_register27_en' => {
1115 
      'hdlType' => 'std_logic',
1116 
      'width' => 1,
1117 
    },
1118 
    'sysgen_dut.to_register28_ce' => {
1119 
      'hdlType' => 'std_logic',
1120 
      'width' => 1,
1121 
    },
1122 
    'sysgen_dut.to_register28_clk' => {
1123 
      'hdlType' => 'std_logic',
1124 
      'width' => 1,
1125 
    },
1126 
    'sysgen_dut.to_register28_clr' => {
1127 
      'hdlType' => 'std_logic',
1128 
      'width' => 1,
1129 
    },
1130 
    'sysgen_dut.to_register28_data_in' => {
1131 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1132 
      'width' => 32,
1133 
    },
1134 
    'sysgen_dut.to_register28_en' => {
1135 
      'hdlType' => 'std_logic',
1136 
      'width' => 1,
1137 
    },
1138 
    'sysgen_dut.to_register29_ce' => {
1139 
      'hdlType' => 'std_logic',
1140 
      'width' => 1,
1141 
    },
1142 
    'sysgen_dut.to_register29_clk' => {
1143 
      'hdlType' => 'std_logic',
1144 
      'width' => 1,
1145 
    },
1146 
    'sysgen_dut.to_register29_clr' => {
1147 
      'hdlType' => 'std_logic',
1148 
      'width' => 1,
1149 
    },
1150 
    'sysgen_dut.to_register29_data_in' => {
1151 
      'hdlType' => 'std_logic',
1152 
      'width' => 1,
1153 
    },
1154 
    'sysgen_dut.to_register29_en' => {
1155 
      'hdlType' => 'std_logic',
1156 
      'width' => 1,
1157 
    },
1158 
    'sysgen_dut.to_register2_ce' => {
1159 
      'hdlType' => 'std_logic',
1160 
      'width' => 1,
1161 
    },
1162 
    'sysgen_dut.to_register2_clk' => {
1163 
      'hdlType' => 'std_logic',
1164 
      'width' => 1,
1165 
    },
1166 
    'sysgen_dut.to_register2_clr' => {
1167 
      'hdlType' => 'std_logic',
1168 
      'width' => 1,
1169 
    },
1170 
    'sysgen_dut.to_register2_data_in' => {
1171 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1172 
      'width' => 32,
1173 
    },
1174 
    'sysgen_dut.to_register2_en' => {
1175 
      'hdlType' => 'std_logic',
1176 
      'width' => 1,
1177 
    },
1178 
    'sysgen_dut.to_register30_ce' => {
1179 
      'hdlType' => 'std_logic',
1180 
      'width' => 1,
1181 
    },
1182 
    'sysgen_dut.to_register30_clk' => {
1183 
      'hdlType' => 'std_logic',
1184 
      'width' => 1,
1185 
    },
1186 
    'sysgen_dut.to_register30_clr' => {
1187 
      'hdlType' => 'std_logic',
1188 
      'width' => 1,
1189 
    },
1190 
    'sysgen_dut.to_register30_data_in' => {
1191 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1192 
      'width' => 32,
1193 
    },
1194 
    'sysgen_dut.to_register30_en' => {
1195 
      'hdlType' => 'std_logic',
1196 
      'width' => 1,
1197 
    },
1198 
    'sysgen_dut.to_register31_ce' => {
1199 
      'hdlType' => 'std_logic',
1200 
      'width' => 1,
1201 
    },
1202 
    'sysgen_dut.to_register31_clk' => {
1203 
      'hdlType' => 'std_logic',
1204 
      'width' => 1,
1205 
    },
1206 
    'sysgen_dut.to_register31_clr' => {
1207 
      'hdlType' => 'std_logic',
1208 
      'width' => 1,
1209 
    },
1210 
    'sysgen_dut.to_register31_data_in' => {
1211 
      'hdlType' => 'std_logic',
1212 
      'width' => 1,
1213 
    },
1214 
    'sysgen_dut.to_register31_en' => {
1215 
      'hdlType' => 'std_logic',
1216 
      'width' => 1,
1217 
    },
1218 
    'sysgen_dut.to_register32_ce' => {
1219 
      'hdlType' => 'std_logic',
1220 
      'width' => 1,
1221 
    },
1222 
    'sysgen_dut.to_register32_clk' => {
1223 
      'hdlType' => 'std_logic',
1224 
      'width' => 1,
1225 
    },
1226 
    'sysgen_dut.to_register32_clr' => {
1227 
      'hdlType' => 'std_logic',
1228 
      'width' => 1,
1229 
    },
1230 
    'sysgen_dut.to_register32_data_in' => {
1231 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1232 
      'width' => 32,
1233 
    },
1234 
    'sysgen_dut.to_register32_en' => {
1235 
      'hdlType' => 'std_logic',
1236 
      'width' => 1,
1237 
    },
1238 
    'sysgen_dut.to_register33_ce' => {
1239 
      'hdlType' => 'std_logic',
1240 
      'width' => 1,
1241 
    },
1242 
    'sysgen_dut.to_register33_clk' => {
1243 
      'hdlType' => 'std_logic',
1244 
      'width' => 1,
1245 
    },
1246 
    'sysgen_dut.to_register33_clr' => {
1247 
      'hdlType' => 'std_logic',
1248 
      'width' => 1,
1249 
    },
1250 
    'sysgen_dut.to_register33_data_in' => {
1251 
      'hdlType' => 'std_logic',
1252 
      'width' => 1,
1253 
    },
1254 
    'sysgen_dut.to_register33_en' => {
1255 
      'hdlType' => 'std_logic',
1256 
      'width' => 1,
1257 
    },
1258 
    'sysgen_dut.to_register34_ce' => {
1259 
      'hdlType' => 'std_logic',
1260 
      'width' => 1,
1261 
    },
1262 
    'sysgen_dut.to_register34_clk' => {
1263 
      'hdlType' => 'std_logic',
1264 
      'width' => 1,
1265 
    },
1266 
    'sysgen_dut.to_register34_clr' => {
1267 
      'hdlType' => 'std_logic',
1268 
      'width' => 1,
1269 
    },
1270 
    'sysgen_dut.to_register34_data_in' => {
1271 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1272 
      'width' => 32,
1273 
    },
1274 
    'sysgen_dut.to_register34_en' => {
1275 
      'hdlType' => 'std_logic',
1276 
      'width' => 1,
1277 
    },
1278 
    'sysgen_dut.to_register3_ce' => {
1279 
      'hdlType' => 'std_logic',
1280 
      'width' => 1,
1281 
    },
1282 
    'sysgen_dut.to_register3_clk' => {
1283 
      'hdlType' => 'std_logic',
1284 
      'width' => 1,
1285 
    },
1286 
    'sysgen_dut.to_register3_clr' => {
1287 
      'hdlType' => 'std_logic',
1288 
      'width' => 1,
1289 
    },
1290 
    'sysgen_dut.to_register3_data_in' => {
1291 
      'hdlType' => 'std_logic',
1292 
      'width' => 1,
1293 
    },
1294 
    'sysgen_dut.to_register3_en' => {
1295 
      'hdlType' => 'std_logic',
1296 
      'width' => 1,
1297 
    },
1298 
    'sysgen_dut.to_register4_ce' => {
1299 
      'hdlType' => 'std_logic',
1300 
      'width' => 1,
1301 
    },
1302 
    'sysgen_dut.to_register4_clk' => {
1303 
      'hdlType' => 'std_logic',
1304 
      'width' => 1,
1305 
    },
1306 
    'sysgen_dut.to_register4_clr' => {
1307 
      'hdlType' => 'std_logic',
1308 
      'width' => 1,
1309 
    },
1310 
    'sysgen_dut.to_register4_data_in' => {
1311 
      'hdlType' => 'std_logic',
1312 
      'width' => 1,
1313 
    },
1314 
    'sysgen_dut.to_register4_en' => {
1315 
      'hdlType' => 'std_logic',
1316 
      'width' => 1,
1317 
    },
1318 
    'sysgen_dut.to_register5_ce' => {
1319 
      'hdlType' => 'std_logic',
1320 
      'width' => 1,
1321 
    },
1322 
    'sysgen_dut.to_register5_clk' => {
1323 
      'hdlType' => 'std_logic',
1324 
      'width' => 1,
1325 
    },
1326 
    'sysgen_dut.to_register5_clr' => {
1327 
      'hdlType' => 'std_logic',
1328 
      'width' => 1,
1329 
    },
1330 
    'sysgen_dut.to_register5_data_in' => {
1331 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1332 
      'width' => 32,
1333 
    },
1334 
    'sysgen_dut.to_register5_en' => {
1335 
      'hdlType' => 'std_logic',
1336 
      'width' => 1,
1337 
    },
1338 
    'sysgen_dut.to_register6_ce' => {
1339 
      'hdlType' => 'std_logic',
1340 
      'width' => 1,
1341 
    },
1342 
    'sysgen_dut.to_register6_clk' => {
1343 
      'hdlType' => 'std_logic',
1344 
      'width' => 1,
1345 
    },
1346 
    'sysgen_dut.to_register6_clr' => {
1347 
      'hdlType' => 'std_logic',
1348 
      'width' => 1,
1349 
    },
1350 
    'sysgen_dut.to_register6_data_in' => {
1351 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1352 
      'width' => 32,
1353 
    },
1354 
    'sysgen_dut.to_register6_en' => {
1355 
      'hdlType' => 'std_logic',
1356 
      'width' => 1,
1357 
    },
1358 
    'sysgen_dut.to_register7_ce' => {
1359 
      'hdlType' => 'std_logic',
1360 
      'width' => 1,
1361 
    },
1362 
    'sysgen_dut.to_register7_clk' => {
1363 
      'hdlType' => 'std_logic',
1364 
      'width' => 1,
1365 
    },
1366 
    'sysgen_dut.to_register7_clr' => {
1367 
      'hdlType' => 'std_logic',
1368 
      'width' => 1,
1369 
    },
1370 
    'sysgen_dut.to_register7_data_in' => {
1371 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1372 
      'width' => 32,
1373 
    },
1374 
    'sysgen_dut.to_register7_en' => {
1375 
      'hdlType' => 'std_logic',
1376 
      'width' => 1,
1377 
    },
1378 
    'sysgen_dut.to_register8_ce' => {
1379 
      'hdlType' => 'std_logic',
1380 
      'width' => 1,
1381 
    },
1382 
    'sysgen_dut.to_register8_clk' => {
1383 
      'hdlType' => 'std_logic',
1384 
      'width' => 1,
1385 
    },
1386 
    'sysgen_dut.to_register8_clr' => {
1387 
      'hdlType' => 'std_logic',
1388 
      'width' => 1,
1389 
    },
1390 
    'sysgen_dut.to_register8_data_in' => {
1391 
      'hdlType' => 'std_logic',
1392 
      'width' => 1,
1393 
    },
1394 
    'sysgen_dut.to_register8_en' => {
1395 
      'hdlType' => 'std_logic',
1396 
      'width' => 1,
1397 
    },
1398 
    'sysgen_dut.to_register9_ce' => {
1399 
      'hdlType' => 'std_logic',
1400 
      'width' => 1,
1401 
    },
1402 
    'sysgen_dut.to_register9_clk' => {
1403 
      'hdlType' => 'std_logic',
1404 
      'width' => 1,
1405 
    },
1406 
    'sysgen_dut.to_register9_clr' => {
1407 
      'hdlType' => 'std_logic',
1408 
      'width' => 1,
1409 
    },
1410 
    'sysgen_dut.to_register9_data_in' => {
1411 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1412 
      'width' => 32,
1413 
    },
1414 
    'sysgen_dut.to_register9_en' => {
1415 
      'hdlType' => 'std_logic',
1416 
      'width' => 1,
1417 
    },
1418 
    'to_register1.dout' => {
1419 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1420 
      'width' => 32,
1421 
    },
1422 
    'to_register10.dout' => {
1423 
      'hdlType' => 'std_logic',
1424 
      'width' => 1,
1425 
    },
1426 
    'to_register11.dout' => {
1427 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1428 
      'width' => 32,
1429 
    },
1430 
    'to_register12.dout' => {
1431 
      'hdlType' => 'std_logic',
1432 
      'width' => 1,
1433 
    },
1434 
    'to_register13.dout' => {
1435 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1436 
      'width' => 32,
1437 
    },
1438 
    'to_register14.dout' => {
1439 
      'hdlType' => 'std_logic',
1440 
      'width' => 1,
1441 
    },
1442 
    'to_register15.dout' => {
1443 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1444 
      'width' => 32,
1445 
    },
1446 
    'to_register16.dout' => {
1447 
      'hdlType' => 'std_logic',
1448 
      'width' => 1,
1449 
    },
1450 
    'to_register17.dout' => {
1451 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1452 
      'width' => 32,
1453 
    },
1454 
    'to_register18.dout' => {
1455 
      'hdlType' => 'std_logic',
1456 
      'width' => 1,
1457 
    },
1458 
    'to_register19.dout' => {
1459 
      'hdlType' => 'std_logic',
1460 
      'width' => 1,
1461 
    },
1462 
    'to_register2.dout' => {
1463 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1464 
      'width' => 32,
1465 
    },
1466 
    'to_register20.dout' => {
1467 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1468 
      'width' => 32,
1469 
    },
1470 
    'to_register21.dout' => {
1471 
      'hdlType' => 'std_logic',
1472 
      'width' => 1,
1473 
    },
1474 
    'to_register22.dout' => {
1475 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1476 
      'width' => 32,
1477 
    },
1478 
    'to_register23.dout' => {
1479 
      'hdlType' => 'std_logic',
1480 
      'width' => 1,
1481 
    },
1482 
    'to_register24.dout' => {
1483 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1484 
      'width' => 32,
1485 
    },
1486 
    'to_register25.dout' => {
1487 
      'hdlType' => 'std_logic',
1488 
      'width' => 1,
1489 
    },
1490 
    'to_register26.dout' => {
1491 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1492 
      'width' => 32,
1493 
    },
1494 
    'to_register27.dout' => {
1495 
      'hdlType' => 'std_logic',
1496 
      'width' => 1,
1497 
    },
1498 
    'to_register28.dout' => {
1499 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1500 
      'width' => 32,
1501 
    },
1502 
    'to_register29.dout' => {
1503 
      'hdlType' => 'std_logic',
1504 
      'width' => 1,
1505 
    },
1506 
    'to_register3.dout' => {
1507 
      'hdlType' => 'std_logic',
1508 
      'width' => 1,
1509 
    },
1510 
    'to_register30.dout' => {
1511 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1512 
      'width' => 32,
1513 
    },
1514 
    'to_register31.dout' => {
1515 
      'hdlType' => 'std_logic',
1516 
      'width' => 1,
1517 
    },
1518 
    'to_register32.dout' => {
1519 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1520 
      'width' => 32,
1521 
    },
1522 
    'to_register33.dout' => {
1523 
      'hdlType' => 'std_logic',
1524 
      'width' => 1,
1525 
    },
1526 
    'to_register34.dout' => {
1527 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1528 
      'width' => 32,
1529 
    },
1530 
    'to_register4.dout' => {
1531 
      'hdlType' => 'std_logic',
1532 
      'width' => 1,
1533 
    },
1534 
    'to_register5.dout' => {
1535 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1536 
      'width' => 32,
1537 
    },
1538 
    'to_register6.dout' => {
1539 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1540 
      'width' => 32,
1541 
    },
1542 
    'to_register7.dout' => {
1543 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1544 
      'width' => 32,
1545 
    },
1546 
    'to_register8.dout' => {
1547 
      'hdlType' => 'std_logic',
1548 
      'width' => 1,
1549 
    },
1550 
    'to_register9.dout' => {
1551 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1552 
      'width' => 32,
1553 
    },
1554 
  },
1555 
  'subblocks' => {
1556 
    'debug_in_1i' => {
1557 
      'connections' => {
1558 
        'debug_in_1i' => '.debug_in_1i',
1559 
      },
1560 
      'entity' => {
1561 
        'attributes' => {
1562 
          'entityAlreadyNetlisted' => 1,
1563 
          'isGateway' => 1,
1564 
          'is_floating_block' => 1,
1565 
        },
1566 
        'entityName' => 'debug_in_1i',
1567 
        'ports' => {
1568 
          'debug_in_1i' => {
1569 
            'attributes' => {
1570 
              'bin_pt' => 0,
1571 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
1572 
              'is_floating_block' => 1,
1573 
              'is_gateway_port' => 1,
1574 
              'must_be_hdl_vector' => 1,
1575 
              'period' => 1,
1576 
              'port_id' => 0,
1577 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
1578 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
1579 
              'timingConstraint' => 'none',
1580 
              'type' => 'UFix_32_0',
1581 
            },
1582 
            'direction' => 'out',
1583 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1584 
            'width' => 32,
1585 
          },
1586 
        },
1587 
      },
1588 
      'entityName' => 'debug_in_1i',
1589 
    },
1590 
    'debug_in_2i' => {
1591 
      'connections' => {
1592 
        'debug_in_2i' => '.debug_in_2i',
1593 
      },
1594 
      'entity' => {
1595 
        'attributes' => {
1596 
          'entityAlreadyNetlisted' => 1,
1597 
          'isGateway' => 1,
1598 
          'is_floating_block' => 1,
1599 
        },
1600 
        'entityName' => 'debug_in_2i',
1601 
        'ports' => {
1602 
          'debug_in_2i' => {
1603 
            'attributes' => {
1604 
              'bin_pt' => 0,
1605 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
1606 
              'is_floating_block' => 1,
1607 
              'is_gateway_port' => 1,
1608 
              'must_be_hdl_vector' => 1,
1609 
              'period' => 1,
1610 
              'port_id' => 0,
1611 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
1612 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
1613 
              'timingConstraint' => 'none',
1614 
              'type' => 'UFix_32_0',
1615 
            },
1616 
            'direction' => 'out',
1617 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1618 
            'width' => 32,
1619 
          },
1620 
        },
1621 
      },
1622 
      'entityName' => 'debug_in_2i',
1623 
    },
1624 
    'debug_in_3i' => {
1625 
      'connections' => {
1626 
        'debug_in_3i' => '.debug_in_3i',
1627 
      },
1628 
      'entity' => {
1629 
        'attributes' => {
1630 
          'entityAlreadyNetlisted' => 1,
1631 
          'isGateway' => 1,
1632 
          'is_floating_block' => 1,
1633 
        },
1634 
        'entityName' => 'debug_in_3i',
1635 
        'ports' => {
1636 
          'debug_in_3i' => {
1637 
            'attributes' => {
1638 
              'bin_pt' => 0,
1639 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
1640 
              'is_floating_block' => 1,
1641 
              'is_gateway_port' => 1,
1642 
              'must_be_hdl_vector' => 1,
1643 
              'period' => 1,
1644 
              'port_id' => 0,
1645 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
1646 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
1647 
              'timingConstraint' => 'none',
1648 
              'type' => 'UFix_32_0',
1649 
            },
1650 
            'direction' => 'out',
1651 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1652 
            'width' => 32,
1653 
          },
1654 
        },
1655 
      },
1656 
      'entityName' => 'debug_in_3i',
1657 
    },
1658 
    'debug_in_4i' => {
1659 
      'connections' => {
1660 
        'debug_in_4i' => '.debug_in_4i',
1661 
      },
1662 
      'entity' => {
1663 
        'attributes' => {
1664 
          'entityAlreadyNetlisted' => 1,
1665 
          'isGateway' => 1,
1666 
          'is_floating_block' => 1,
1667 
        },
1668 
        'entityName' => 'debug_in_4i',
1669 
        'ports' => {
1670 
          'debug_in_4i' => {
1671 
            'attributes' => {
1672 
              'bin_pt' => 0,
1673 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
1674 
              'is_floating_block' => 1,
1675 
              'is_gateway_port' => 1,
1676 
              'must_be_hdl_vector' => 1,
1677 
              'period' => 1,
1678 
              'port_id' => 0,
1679 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
1680 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
1681 
              'timingConstraint' => 'none',
1682 
              'type' => 'UFix_32_0',
1683 
            },
1684 
            'direction' => 'out',
1685 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1686 
            'width' => 32,
1687 
          },
1688 
        },
1689 
      },
1690 
      'entityName' => 'debug_in_4i',
1691 
    },
1692 
    'dma_host2board_busy' => {
1693 
      'connections' => {
1694 
        'dma_host2board_busy' => '.dma_host2board_busy',
1695 
      },
1696 
      'entity' => {
1697 
        'attributes' => {
1698 
          'entityAlreadyNetlisted' => 1,
1699 
          'isGateway' => 1,
1700 
          'is_floating_block' => 1,
1701 
        },
1702 
        'entityName' => 'dma_host2board_busy',
1703 
        'ports' => {
1704 
          'dma_host2board_busy' => {
1705 
            'attributes' => {
1706 
              'bin_pt' => 0,
1707 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
1708 
              'is_floating_block' => 1,
1709 
              'is_gateway_port' => 1,
1710 
              'must_be_hdl_vector' => 1,
1711 
              'period' => 1,
1712 
              'port_id' => 0,
1713 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
1714 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
1715 
              'timingConstraint' => 'none',
1716 
              'type' => 'UFix_1_0',
1717 
            },
1718 
            'direction' => 'out',
1719 
            'hdlType' => 'std_logic',
1720 
            'width' => 1,
1721 
          },
1722 
        },
1723 
      },
1724 
      'entityName' => 'dma_host2board_busy',
1725 
    },
1726 
    'dma_host2board_done' => {
1727 
      'connections' => {
1728 
        'dma_host2board_done' => '.dma_host2board_done',
1729 
      },
1730 
      'entity' => {
1731 
        'attributes' => {
1732 
          'entityAlreadyNetlisted' => 1,
1733 
          'isGateway' => 1,
1734 
          'is_floating_block' => 1,
1735 
        },
1736 
        'entityName' => 'dma_host2board_done',
1737 
        'ports' => {
1738 
          'dma_host2board_done' => {
1739 
            'attributes' => {
1740 
              'bin_pt' => 0,
1741 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
1742 
              'is_floating_block' => 1,
1743 
              'is_gateway_port' => 1,
1744 
              'must_be_hdl_vector' => 1,
1745 
              'period' => 1,
1746 
              'port_id' => 0,
1747 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
1748 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
1749 
              'timingConstraint' => 'none',
1750 
              'type' => 'UFix_1_0',
1751 
            },
1752 
            'direction' => 'out',
1753 
            'hdlType' => 'std_logic',
1754 
            'width' => 1,
1755 
          },
1756 
        },
1757 
      },
1758 
      'entityName' => 'dma_host2board_done',
1759 
    },
1760 
    'from_register1' => {
1761 
      'connections' => {
1762 
        'data_out' => 'from_register1.data_out',
1763 
      },
1764 
      'entity' => {
1765 
        'attributes' => {
1766 
          'entityAlreadyNetlisted' => 1,
1767 
          'generics' => [
1768 
          ],
1769 
          'is_floating_block' => 1,
1770 
          'mask' => {
1771 
            'Block_Handle' => 10.0009765625,
1772 
            'Block_handle' => 10.0009765625,
1773 
            'MDL_Handle' => 3.0009765625,
1774 
            'MDL_handle' => 3.0009765625,
1775 
            'arith_type' => 2,
1776 
            'bin_pt' => 0,
1777 
            'block_config' => 'sysgen_blockset:fromreg_config',
1778 
            'block_handle' => 10.0009765625,
1779 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1780 
            'block_type' => 'fromreg',
1781 
            'dbl_ovrd' => 0,
1782 
            'init' => 0,
1783 
            'init_bit_vector' => '0b',
1784 
            'mdl_handle' => 3.0009765625,
1785 
            'model_handle' => 3.0009765625,
1786 
            'n_bits' => 1,
1787 
            'ownership' => 2,
1788 
            'period' => '8e-009',
1789 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1790 
            'shared_memory_name' => 'register01rv',
1791 
          },
1792 
          'needs_vhdl_wrapper' => 0,
1793 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1794 
        },
1795 
        'entityName' => 'x_x61',
1796 
        'ports' => {
1797 
          'data_out' => {
1798 
            'attributes' => {
1799 
              'bin_pt' => 0,
1800 
              'is_floating_block' => 1,
1801 
              'must_be_hdl_vector' => 1,
1802 
              'period' => 1,
1803 
              'port_id' => 0,
1804 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
1805 
              'type' => 'UFix_1_0',
1806 
            },
1807 
            'direction' => 'out',
1808 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1809 
            'width' => 1,
1810 
          },
1811 
        },
1812 
      },
1813 
      'entityName' => 'x_x61',
1814 
    },
1815 
    'from_register10' => {
1816 
      'connections' => {
1817 
        'data_out' => 'from_register10.data_out',
1818 
      },
1819 
      'entity' => {
1820 
        'attributes' => {
1821 
          'entityAlreadyNetlisted' => 1,
1822 
          'generics' => [
1823 
          ],
1824 
          'is_floating_block' => 1,
1825 
          'mask' => {
1826 
            'Block_Handle' => 11.0009765625,
1827 
            'Block_handle' => 11.0009765625,
1828 
            'MDL_Handle' => 3.0009765625,
1829 
            'MDL_handle' => 3.0009765625,
1830 
            'arith_type' => 2,
1831 
            'bin_pt' => 0,
1832 
            'block_config' => 'sysgen_blockset:fromreg_config',
1833 
            'block_handle' => 11.0009765625,
1834 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1835 
            'block_type' => 'fromreg',
1836 
            'dbl_ovrd' => 0,
1837 
            'init' => 0,
1838 
            'init_bit_vector' => '00000000000000000000000000000000b',
1839 
            'mdl_handle' => 3.0009765625,
1840 
            'model_handle' => 3.0009765625,
1841 
            'n_bits' => 32,
1842 
            'ownership' => 2,
1843 
            'period' => '8e-009',
1844 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1845 
            'shared_memory_name' => 'register05rd',
1846 
          },
1847 
          'needs_vhdl_wrapper' => 0,
1848 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1849 
        },
1850 
        'entityName' => 'x_x62',
1851 
        'ports' => {
1852 
          'data_out' => {
1853 
            'attributes' => {
1854 
              'bin_pt' => 0,
1855 
              'is_floating_block' => 1,
1856 
              'must_be_hdl_vector' => 1,
1857 
              'period' => 1,
1858 
              'port_id' => 0,
1859 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
1860 
              'type' => 'UFix_32_0',
1861 
            },
1862 
            'direction' => 'out',
1863 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1864 
            'width' => 32,
1865 
          },
1866 
        },
1867 
      },
1868 
      'entityName' => 'x_x62',
1869 
    },
1870 
    'from_register11' => {
1871 
      'connections' => {
1872 
        'data_out' => 'from_register11.data_out',
1873 
      },
1874 
      'entity' => {
1875 
        'attributes' => {
1876 
          'entityAlreadyNetlisted' => 1,
1877 
          'generics' => [
1878 
          ],
1879 
          'is_floating_block' => 1,
1880 
          'mask' => {
1881 
            'Block_Handle' => 12.0009765625,
1882 
            'Block_handle' => 12.0009765625,
1883 
            'MDL_Handle' => 3.0009765625,
1884 
            'MDL_handle' => 3.0009765625,
1885 
            'arith_type' => 2,
1886 
            'bin_pt' => 0,
1887 
            'block_config' => 'sysgen_blockset:fromreg_config',
1888 
            'block_handle' => 12.0009765625,
1889 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1890 
            'block_type' => 'fromreg',
1891 
            'dbl_ovrd' => 0,
1892 
            'init' => 0,
1893 
            'init_bit_vector' => '00000000000000000000000000000000b',
1894 
            'mdl_handle' => 3.0009765625,
1895 
            'model_handle' => 3.0009765625,
1896 
            'n_bits' => 32,
1897 
            'ownership' => 2,
1898 
            'period' => '8e-009',
1899 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1900 
            'shared_memory_name' => 'register06rd',
1901 
          },
1902 
          'needs_vhdl_wrapper' => 0,
1903 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1904 
        },
1905 
        'entityName' => 'x_x63',
1906 
        'ports' => {
1907 
          'data_out' => {
1908 
            'attributes' => {
1909 
              'bin_pt' => 0,
1910 
              'is_floating_block' => 1,
1911 
              'must_be_hdl_vector' => 1,
1912 
              'period' => 1,
1913 
              'port_id' => 0,
1914 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
1915 
              'type' => 'UFix_32_0',
1916 
            },
1917 
            'direction' => 'out',
1918 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1919 
            'width' => 32,
1920 
          },
1921 
        },
1922 
      },
1923 
      'entityName' => 'x_x63',
1924 
    },
1925 
    'from_register12' => {
1926 
      'connections' => {
1927 
        'data_out' => 'from_register12.data_out',
1928 
      },
1929 
      'entity' => {
1930 
        'attributes' => {
1931 
          'entityAlreadyNetlisted' => 1,
1932 
          'generics' => [
1933 
          ],
1934 
          'is_floating_block' => 1,
1935 
          'mask' => {
1936 
            'Block_Handle' => 13.0009765625,
1937 
            'Block_handle' => 13.0009765625,
1938 
            'MDL_Handle' => 3.0009765625,
1939 
            'MDL_handle' => 3.0009765625,
1940 
            'arith_type' => 2,
1941 
            'bin_pt' => 0,
1942 
            'block_config' => 'sysgen_blockset:fromreg_config',
1943 
            'block_handle' => 13.0009765625,
1944 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1945 
            'block_type' => 'fromreg',
1946 
            'dbl_ovrd' => 0,
1947 
            'init' => 0,
1948 
            'init_bit_vector' => '0b',
1949 
            'mdl_handle' => 3.0009765625,
1950 
            'model_handle' => 3.0009765625,
1951 
            'n_bits' => 1,
1952 
            'ownership' => 2,
1953 
            'period' => '8e-009',
1954 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1955 
            'shared_memory_name' => 'register06rv',
1956 
          },
1957 
          'needs_vhdl_wrapper' => 0,
1958 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1959 
        },
1960 
        'entityName' => 'x_x64',
1961 
        'ports' => {
1962 
          'data_out' => {
1963 
            'attributes' => {
1964 
              'bin_pt' => 0,
1965 
              'is_floating_block' => 1,
1966 
              'must_be_hdl_vector' => 1,
1967 
              'period' => 1,
1968 
              'port_id' => 0,
1969 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
1970 
              'type' => 'UFix_1_0',
1971 
            },
1972 
            'direction' => 'out',
1973 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1974 
            'width' => 1,
1975 
          },
1976 
        },
1977 
      },
1978 
      'entityName' => 'x_x64',
1979 
    },
1980 
    'from_register13' => {
1981 
      'connections' => {
1982 
        'data_out' => 'from_register13.data_out',
1983 
      },
1984 
      'entity' => {
1985 
        'attributes' => {
1986 
          'entityAlreadyNetlisted' => 1,
1987 
          'generics' => [
1988 
          ],
1989 
          'is_floating_block' => 1,
1990 
          'mask' => {
1991 
            'Block_Handle' => 14.0009765625,
1992 
            'Block_handle' => 14.0009765625,
1993 
            'MDL_Handle' => 3.0009765625,
1994 
            'MDL_handle' => 3.0009765625,
1995 
            'arith_type' => 2,
1996 
            'bin_pt' => 0,
1997 
            'block_config' => 'sysgen_blockset:fromreg_config',
1998 
            'block_handle' => 14.0009765625,
1999 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
2000 
            'block_type' => 'fromreg',
2001 
            'dbl_ovrd' => 0,
2002 
            'init' => 0,
2003 
            'init_bit_vector' => '00000000000000000000000000000000b',
2004 
            'mdl_handle' => 3.0009765625,
2005 
            'model_handle' => 3.0009765625,
2006 
            'n_bits' => 32,
2007 
            'ownership' => 2,
2008 
            'period' => '8e-009',
2009 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2010 
            'shared_memory_name' => 'register07rd',
2011 
          },
2012 
          'needs_vhdl_wrapper' => 0,
2013 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
2014 
        },
2015 
        'entityName' => 'x_x65',
2016 
        'ports' => {
2017 
          'data_out' => {
2018 
            'attributes' => {
2019 
              'bin_pt' => 0,
2020 
              'is_floating_block' => 1,
2021 
              'must_be_hdl_vector' => 1,
2022 
              'period' => 1,
2023 
              'port_id' => 0,
2024 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
2025 
              'type' => 'UFix_32_0',
2026 
            },
2027 
            'direction' => 'out',
2028 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2029 
            'width' => 32,
2030 
          },
2031 
        },
2032 
      },
2033 
      'entityName' => 'x_x65',
2034 
    },
2035 
    'from_register14' => {
2036 
      'connections' => {
2037 
        'data_out' => 'from_register14.data_out',
2038 
      },
2039 
      'entity' => {
2040 
        'attributes' => {
2041 
          'entityAlreadyNetlisted' => 1,
2042 
          'generics' => [
2043 
          ],
2044 
          'is_floating_block' => 1,
2045 
          'mask' => {
2046 
            'Block_Handle' => 15.0009765625,
2047 
            'Block_handle' => 15.0009765625,
2048 
            'MDL_Handle' => 3.0009765625,
2049 
            'MDL_handle' => 3.0009765625,
2050 
            'arith_type' => 2,
2051 
            'bin_pt' => 0,
2052 
            'block_config' => 'sysgen_blockset:fromreg_config',
2053 
            'block_handle' => 15.0009765625,
2054 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2055 
            'block_type' => 'fromreg',
2056 
            'dbl_ovrd' => 0,
2057 
            'init' => 0,
2058 
            'init_bit_vector' => '0b',
2059 
            'mdl_handle' => 3.0009765625,
2060 
            'model_handle' => 3.0009765625,
2061 
            'n_bits' => 1,
2062 
            'ownership' => 2,
2063 
            'period' => '8e-009',
2064 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2065 
            'shared_memory_name' => 'register07rv',
2066 
          },
2067 
          'needs_vhdl_wrapper' => 0,
2068 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2069 
        },
2070 
        'entityName' => 'x_x66',
2071 
        'ports' => {
2072 
          'data_out' => {
2073 
            'attributes' => {
2074 
              'bin_pt' => 0,
2075 
              'is_floating_block' => 1,
2076 
              'must_be_hdl_vector' => 1,
2077 
              'period' => 1,
2078 
              'port_id' => 0,
2079 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
2080 
              'type' => 'UFix_1_0',
2081 
            },
2082 
            'direction' => 'out',
2083 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2084 
            'width' => 1,
2085 
          },
2086 
        },
2087 
      },
2088 
      'entityName' => 'x_x66',
2089 
    },
2090 
    'from_register15' => {
2091 
      'connections' => {
2092 
        'data_out' => 'from_register15.data_out',
2093 
      },
2094 
      'entity' => {
2095 
        'attributes' => {
2096 
          'entityAlreadyNetlisted' => 1,
2097 
          'generics' => [
2098 
          ],
2099 
          'is_floating_block' => 1,
2100 
          'mask' => {
2101 
            'Block_Handle' => 16.0009765625,
2102 
            'Block_handle' => 16.0009765625,
2103 
            'MDL_Handle' => 3.0009765625,
2104 
            'MDL_handle' => 3.0009765625,
2105 
            'arith_type' => 2,
2106 
            'bin_pt' => 0,
2107 
            'block_config' => 'sysgen_blockset:fromreg_config',
2108 
            'block_handle' => 16.0009765625,
2109 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2110 
            'block_type' => 'fromreg',
2111 
            'dbl_ovrd' => 0,
2112 
            'init' => 0,
2113 
            'init_bit_vector' => '00000000000000000000000000000000b',
2114 
            'mdl_handle' => 3.0009765625,
2115 
            'model_handle' => 3.0009765625,
2116 
            'n_bits' => 32,
2117 
            'ownership' => 2,
2118 
            'period' => '8e-009',
2119 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2120 
            'shared_memory_name' => 'register08rd',
2121 
          },
2122 
          'needs_vhdl_wrapper' => 0,
2123 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2124 
        },
2125 
        'entityName' => 'x_x67',
2126 
        'ports' => {
2127 
          'data_out' => {
2128 
            'attributes' => {
2129 
              'bin_pt' => 0,
2130 
              'is_floating_block' => 1,
2131 
              'must_be_hdl_vector' => 1,
2132 
              'period' => 1,
2133 
              'port_id' => 0,
2134 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
2135 
              'type' => 'UFix_32_0',
2136 
            },
2137 
            'direction' => 'out',
2138 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2139 
            'width' => 32,
2140 
          },
2141 
        },
2142 
      },
2143 
      'entityName' => 'x_x67',
2144 
    },
2145 
    'from_register16' => {
2146 
      'connections' => {
2147 
        'data_out' => 'from_register16.data_out',
2148 
      },
2149 
      'entity' => {
2150 
        'attributes' => {
2151 
          'entityAlreadyNetlisted' => 1,
2152 
          'generics' => [
2153 
          ],
2154 
          'is_floating_block' => 1,
2155 
          'mask' => {
2156 
            'Block_Handle' => 17.0009765625,
2157 
            'Block_handle' => 17.0009765625,
2158 
            'MDL_Handle' => 3.0009765625,
2159 
            'MDL_handle' => 3.0009765625,
2160 
            'arith_type' => 2,
2161 
            'bin_pt' => 0,
2162 
            'block_config' => 'sysgen_blockset:fromreg_config',
2163 
            'block_handle' => 17.0009765625,
2164 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2165 
            'block_type' => 'fromreg',
2166 
            'dbl_ovrd' => 0,
2167 
            'init' => 0,
2168 
            'init_bit_vector' => '0b',
2169 
            'mdl_handle' => 3.0009765625,
2170 
            'model_handle' => 3.0009765625,
2171 
            'n_bits' => 1,
2172 
            'ownership' => 2,
2173 
            'period' => '8e-009',
2174 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2175 
            'shared_memory_name' => 'register08rv',
2176 
          },
2177 
          'needs_vhdl_wrapper' => 0,
2178 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2179 
        },
2180 
        'entityName' => 'x_x68',
2181 
        'ports' => {
2182 
          'data_out' => {
2183 
            'attributes' => {
2184 
              'bin_pt' => 0,
2185 
              'is_floating_block' => 1,
2186 
              'must_be_hdl_vector' => 1,
2187 
              'period' => 1,
2188 
              'port_id' => 0,
2189 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
2190 
              'type' => 'UFix_1_0',
2191 
            },
2192 
            'direction' => 'out',
2193 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2194 
            'width' => 1,
2195 
          },
2196 
        },
2197 
      },
2198 
      'entityName' => 'x_x68',
2199 
    },
2200 
    'from_register17' => {
2201 
      'connections' => {
2202 
        'data_out' => 'from_register17.data_out',
2203 
      },
2204 
      'entity' => {
2205 
        'attributes' => {
2206 
          'entityAlreadyNetlisted' => 1,
2207 
          'generics' => [
2208 
          ],
2209 
          'is_floating_block' => 1,
2210 
          'mask' => {
2211 
            'Block_Handle' => 18.0009765625,
2212 
            'Block_handle' => 18.0009765625,
2213 
            'MDL_Handle' => 3.0009765625,
2214 
            'MDL_handle' => 3.0009765625,
2215 
            'arith_type' => 2,
2216 
            'bin_pt' => 0,
2217 
            'block_config' => 'sysgen_blockset:fromreg_config',
2218 
            'block_handle' => 18.0009765625,
2219 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2220 
            'block_type' => 'fromreg',
2221 
            'dbl_ovrd' => 0,
2222 
            'init' => 0,
2223 
            'init_bit_vector' => '00000000000000000000000000000000b',
2224 
            'mdl_handle' => 3.0009765625,
2225 
            'model_handle' => 3.0009765625,
2226 
            'n_bits' => 32,
2227 
            'ownership' => 2,
2228 
            'period' => '8e-009',
2229 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2230 
            'shared_memory_name' => 'register09rd',
2231 
          },
2232 
          'needs_vhdl_wrapper' => 0,
2233 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2234 
        },
2235 
        'entityName' => 'x_x69',
2236 
        'ports' => {
2237 
          'data_out' => {
2238 
            'attributes' => {
2239 
              'bin_pt' => 0,
2240 
              'is_floating_block' => 1,
2241 
              'must_be_hdl_vector' => 1,
2242 
              'period' => 1,
2243 
              'port_id' => 0,
2244 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
2245 
              'type' => 'UFix_32_0',
2246 
            },
2247 
            'direction' => 'out',
2248 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2249 
            'width' => 32,
2250 
          },
2251 
        },
2252 
      },
2253 
      'entityName' => 'x_x69',
2254 
    },
2255 
    'from_register18' => {
2256 
      'connections' => {
2257 
        'data_out' => 'from_register18.data_out',
2258 
      },
2259 
      'entity' => {
2260 
        'attributes' => {
2261 
          'entityAlreadyNetlisted' => 1,
2262 
          'generics' => [
2263 
          ],
2264 
          'is_floating_block' => 1,
2265 
          'mask' => {
2266 
            'Block_Handle' => 19.0009765625,
2267 
            'Block_handle' => 19.0009765625,
2268 
            'MDL_Handle' => 3.0009765625,
2269 
            'MDL_handle' => 3.0009765625,
2270 
            'arith_type' => 2,
2271 
            'bin_pt' => 0,
2272 
            'block_config' => 'sysgen_blockset:fromreg_config',
2273 
            'block_handle' => 19.0009765625,
2274 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2275 
            'block_type' => 'fromreg',
2276 
            'dbl_ovrd' => 0,
2277 
            'init' => 0,
2278 
            'init_bit_vector' => '0b',
2279 
            'mdl_handle' => 3.0009765625,
2280 
            'model_handle' => 3.0009765625,
2281 
            'n_bits' => 1,
2282 
            'ownership' => 2,
2283 
            'period' => '8e-009',
2284 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2285 
            'shared_memory_name' => 'register09rv',
2286 
          },
2287 
          'needs_vhdl_wrapper' => 0,
2288 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2289 
        },
2290 
        'entityName' => 'x_x70',
2291 
        'ports' => {
2292 
          'data_out' => {
2293 
            'attributes' => {
2294 
              'bin_pt' => 0,
2295 
              'is_floating_block' => 1,
2296 
              'must_be_hdl_vector' => 1,
2297 
              'period' => 1,
2298 
              'port_id' => 0,
2299 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
2300 
              'type' => 'UFix_1_0',
2301 
            },
2302 
            'direction' => 'out',
2303 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2304 
            'width' => 1,
2305 
          },
2306 
        },
2307 
      },
2308 
      'entityName' => 'x_x70',
2309 
    },
2310 
    'from_register19' => {
2311 
      'connections' => {
2312 
        'data_out' => 'from_register19.data_out',
2313 
      },
2314 
      'entity' => {
2315 
        'attributes' => {
2316 
          'entityAlreadyNetlisted' => 1,
2317 
          'generics' => [
2318 
          ],
2319 
          'is_floating_block' => 1,
2320 
          'mask' => {
2321 
            'Block_Handle' => 20.0009765625,
2322 
            'Block_handle' => 20.0009765625,
2323 
            'MDL_Handle' => 3.0009765625,
2324 
            'MDL_handle' => 3.0009765625,
2325 
            'arith_type' => 2,
2326 
            'bin_pt' => 0,
2327 
            'block_config' => 'sysgen_blockset:fromreg_config',
2328 
            'block_handle' => 20.0009765625,
2329 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2330 
            'block_type' => 'fromreg',
2331 
            'dbl_ovrd' => 0,
2332 
            'init' => 0,
2333 
            'init_bit_vector' => '00000000000000000000000000000000b',
2334 
            'mdl_handle' => 3.0009765625,
2335 
            'model_handle' => 3.0009765625,
2336 
            'n_bits' => 32,
2337 
            'ownership' => 2,
2338 
            'period' => '8e-009',
2339 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2340 
            'shared_memory_name' => 'register10rd',
2341 
          },
2342 
          'needs_vhdl_wrapper' => 0,
2343 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2344 
        },
2345 
        'entityName' => 'x_x71',
2346 
        'ports' => {
2347 
          'data_out' => {
2348 
            'attributes' => {
2349 
              'bin_pt' => 0,
2350 
              'is_floating_block' => 1,
2351 
              'must_be_hdl_vector' => 1,
2352 
              'period' => 1,
2353 
              'port_id' => 0,
2354 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
2355 
              'type' => 'UFix_32_0',
2356 
            },
2357 
            'direction' => 'out',
2358 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2359 
            'width' => 32,
2360 
          },
2361 
        },
2362 
      },
2363 
      'entityName' => 'x_x71',
2364 
    },
2365 
    'from_register2' => {
2366 
      'connections' => {
2367 
        'data_out' => 'from_register2.data_out',
2368 
      },
2369 
      'entity' => {
2370 
        'attributes' => {
2371 
          'entityAlreadyNetlisted' => 1,
2372 
          'generics' => [
2373 
          ],
2374 
          'is_floating_block' => 1,
2375 
          'mask' => {
2376 
            'Block_Handle' => 21.0009765625,
2377 
            'Block_handle' => 21.0009765625,
2378 
            'MDL_Handle' => 3.0009765625,
2379 
            'MDL_handle' => 3.0009765625,
2380 
            'arith_type' => 2,
2381 
            'bin_pt' => 0,
2382 
            'block_config' => 'sysgen_blockset:fromreg_config',
2383 
            'block_handle' => 21.0009765625,
2384 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2385 
            'block_type' => 'fromreg',
2386 
            'dbl_ovrd' => 0,
2387 
            'init' => 0,
2388 
            'init_bit_vector' => '0b',
2389 
            'mdl_handle' => 3.0009765625,
2390 
            'model_handle' => 3.0009765625,
2391 
            'n_bits' => 1,
2392 
            'ownership' => 2,
2393 
            'period' => '8e-009',
2394 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2395 
            'shared_memory_name' => 'register02rv',
2396 
          },
2397 
          'needs_vhdl_wrapper' => 0,
2398 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2399 
        },
2400 
        'entityName' => 'x_x72',
2401 
        'ports' => {
2402 
          'data_out' => {
2403 
            'attributes' => {
2404 
              'bin_pt' => 0,
2405 
              'is_floating_block' => 1,
2406 
              'must_be_hdl_vector' => 1,
2407 
              'period' => 1,
2408 
              'port_id' => 0,
2409 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
2410 
              'type' => 'UFix_1_0',
2411 
            },
2412 
            'direction' => 'out',
2413 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2414 
            'width' => 1,
2415 
          },
2416 
        },
2417 
      },
2418 
      'entityName' => 'x_x72',
2419 
    },
2420 
    'from_register20' => {
2421 
      'connections' => {
2422 
        'data_out' => 'from_register20.data_out',
2423 
      },
2424 
      'entity' => {
2425 
        'attributes' => {
2426 
          'entityAlreadyNetlisted' => 1,
2427 
          'generics' => [
2428 
          ],
2429 
          'is_floating_block' => 1,
2430 
          'mask' => {
2431 
            'Block_Handle' => 22.0009765625,
2432 
            'Block_handle' => 22.0009765625,
2433 
            'MDL_Handle' => 3.0009765625,
2434 
            'MDL_handle' => 3.0009765625,
2435 
            'arith_type' => 2,
2436 
            'bin_pt' => 0,
2437 
            'block_config' => 'sysgen_blockset:fromreg_config',
2438 
            'block_handle' => 22.0009765625,
2439 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2440 
            'block_type' => 'fromreg',
2441 
            'dbl_ovrd' => 0,
2442 
            'init' => 0,
2443 
            'init_bit_vector' => '0b',
2444 
            'mdl_handle' => 3.0009765625,
2445 
            'model_handle' => 3.0009765625,
2446 
            'n_bits' => 1,
2447 
            'ownership' => 2,
2448 
            'period' => '8e-009',
2449 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2450 
            'shared_memory_name' => 'register10rv',
2451 
          },
2452 
          'needs_vhdl_wrapper' => 0,
2453 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2454 
        },
2455 
        'entityName' => 'x_x73',
2456 
        'ports' => {
2457 
          'data_out' => {
2458 
            'attributes' => {
2459 
              'bin_pt' => 0,
2460 
              'is_floating_block' => 1,
2461 
              'must_be_hdl_vector' => 1,
2462 
              'period' => 1,
2463 
              'port_id' => 0,
2464 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
2465 
              'type' => 'UFix_1_0',
2466 
            },
2467 
            'direction' => 'out',
2468 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2469 
            'width' => 1,
2470 
          },
2471 
        },
2472 
      },
2473 
      'entityName' => 'x_x73',
2474 
    },
2475 
    'from_register21' => {
2476 
      'connections' => {
2477 
        'data_out' => 'from_register21.data_out',
2478 
      },
2479 
      'entity' => {
2480 
        'attributes' => {
2481 
          'entityAlreadyNetlisted' => 1,
2482 
          'generics' => [
2483 
          ],
2484 
          'is_floating_block' => 1,
2485 
          'mask' => {
2486 
            'Block_Handle' => 23.0009765625,
2487 
            'Block_handle' => 23.0009765625,
2488 
            'MDL_Handle' => 3.0009765625,
2489 
            'MDL_handle' => 3.0009765625,
2490 
            'arith_type' => 2,
2491 
            'bin_pt' => 0,
2492 
            'block_config' => 'sysgen_blockset:fromreg_config',
2493 
            'block_handle' => 23.0009765625,
2494 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2495 
            'block_type' => 'fromreg',
2496 
            'dbl_ovrd' => 0,
2497 
            'init' => 0,
2498 
            'init_bit_vector' => '00000000000000000000000000000000b',
2499 
            'mdl_handle' => 3.0009765625,
2500 
            'model_handle' => 3.0009765625,
2501 
            'n_bits' => 32,
2502 
            'ownership' => 2,
2503 
            'period' => '8e-009',
2504 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2505 
            'shared_memory_name' => 'register11rd',
2506 
          },
2507 
          'needs_vhdl_wrapper' => 0,
2508 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2509 
        },
2510 
        'entityName' => 'x_x74',
2511 
        'ports' => {
2512 
          'data_out' => {
2513 
            'attributes' => {
2514 
              'bin_pt' => 0,
2515 
              'is_floating_block' => 1,
2516 
              'must_be_hdl_vector' => 1,
2517 
              'period' => 1,
2518 
              'port_id' => 0,
2519 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
2520 
              'type' => 'UFix_32_0',
2521 
            },
2522 
            'direction' => 'out',
2523 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2524 
            'width' => 32,
2525 
          },
2526 
        },
2527 
      },
2528 
      'entityName' => 'x_x74',
2529 
    },
2530 
    'from_register22' => {
2531 
      'connections' => {
2532 
        'data_out' => 'from_register22.data_out',
2533 
      },
2534 
      'entity' => {
2535 
        'attributes' => {
2536 
          'entityAlreadyNetlisted' => 1,
2537 
          'generics' => [
2538 
          ],
2539 
          'is_floating_block' => 1,
2540 
          'mask' => {
2541 
            'Block_Handle' => 24.0009765625,
2542 
            'Block_handle' => 24.0009765625,
2543 
            'MDL_Handle' => 3.0009765625,
2544 
            'MDL_handle' => 3.0009765625,
2545 
            'arith_type' => 2,
2546 
            'bin_pt' => 0,
2547 
            'block_config' => 'sysgen_blockset:fromreg_config',
2548 
            'block_handle' => 24.0009765625,
2549 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2550 
            'block_type' => 'fromreg',
2551 
            'dbl_ovrd' => 0,
2552 
            'init' => 0,
2553 
            'init_bit_vector' => '0b',
2554 
            'mdl_handle' => 3.0009765625,
2555 
            'model_handle' => 3.0009765625,
2556 
            'n_bits' => 1,
2557 
            'ownership' => 2,
2558 
            'period' => '8e-009',
2559 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2560 
            'shared_memory_name' => 'register11rv',
2561 
          },
2562 
          'needs_vhdl_wrapper' => 0,
2563 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2564 
        },
2565 
        'entityName' => 'x_x75',
2566 
        'ports' => {
2567 
          'data_out' => {
2568 
            'attributes' => {
2569 
              'bin_pt' => 0,
2570 
              'is_floating_block' => 1,
2571 
              'must_be_hdl_vector' => 1,
2572 
              'period' => 1,
2573 
              'port_id' => 0,
2574 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
2575 
              'type' => 'UFix_1_0',
2576 
            },
2577 
            'direction' => 'out',
2578 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2579 
            'width' => 1,
2580 
          },
2581 
        },
2582 
      },
2583 
      'entityName' => 'x_x75',
2584 
    },
2585 
    'from_register23' => {
2586 
      'connections' => {
2587 
        'data_out' => 'from_register23.data_out',
2588 
      },
2589 
      'entity' => {
2590 
        'attributes' => {
2591 
          'entityAlreadyNetlisted' => 1,
2592 
          'generics' => [
2593 
          ],
2594 
          'is_floating_block' => 1,
2595 
          'mask' => {
2596 
            'Block_Handle' => 25.0009765625,
2597 
            'Block_handle' => 25.0009765625,
2598 
            'MDL_Handle' => 3.0009765625,
2599 
            'MDL_handle' => 3.0009765625,
2600 
            'arith_type' => 2,
2601 
            'bin_pt' => 0,
2602 
            'block_config' => 'sysgen_blockset:fromreg_config',
2603 
            'block_handle' => 25.0009765625,
2604 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2605 
            'block_type' => 'fromreg',
2606 
            'dbl_ovrd' => 0,
2607 
            'init' => 0,
2608 
            'init_bit_vector' => '00000000000000000000000000000000b',
2609 
            'mdl_handle' => 3.0009765625,
2610 
            'model_handle' => 3.0009765625,
2611 
            'n_bits' => 32,
2612 
            'ownership' => 2,
2613 
            'period' => '8e-009',
2614 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2615 
            'shared_memory_name' => 'register12rd',
2616 
          },
2617 
          'needs_vhdl_wrapper' => 0,
2618 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2619 
        },
2620 
        'entityName' => 'x_x76',
2621 
        'ports' => {
2622 
          'data_out' => {
2623 
            'attributes' => {
2624 
              'bin_pt' => 0,
2625 
              'is_floating_block' => 1,
2626 
              'must_be_hdl_vector' => 1,
2627 
              'period' => 1,
2628 
              'port_id' => 0,
2629 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
2630 
              'type' => 'UFix_32_0',
2631 
            },
2632 
            'direction' => 'out',
2633 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2634 
            'width' => 32,
2635 
          },
2636 
        },
2637 
      },
2638 
      'entityName' => 'x_x76',
2639 
    },
2640 
    'from_register24' => {
2641 
      'connections' => {
2642 
        'data_out' => 'from_register24.data_out',
2643 
      },
2644 
      'entity' => {
2645 
        'attributes' => {
2646 
          'entityAlreadyNetlisted' => 1,
2647 
          'generics' => [
2648 
          ],
2649 
          'is_floating_block' => 1,
2650 
          'mask' => {
2651 
            'Block_Handle' => 26.0009765625,
2652 
            'Block_handle' => 26.0009765625,
2653 
            'MDL_Handle' => 3.0009765625,
2654 
            'MDL_handle' => 3.0009765625,
2655 
            'arith_type' => 2,
2656 
            'bin_pt' => 0,
2657 
            'block_config' => 'sysgen_blockset:fromreg_config',
2658 
            'block_handle' => 26.0009765625,
2659 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2660 
            'block_type' => 'fromreg',
2661 
            'dbl_ovrd' => 0,
2662 
            'init' => 0,
2663 
            'init_bit_vector' => '0b',
2664 
            'mdl_handle' => 3.0009765625,
2665 
            'model_handle' => 3.0009765625,
2666 
            'n_bits' => 1,
2667 
            'ownership' => 2,
2668 
            'period' => '8e-009',
2669 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2670 
            'shared_memory_name' => 'register12rv',
2671 
          },
2672 
          'needs_vhdl_wrapper' => 0,
2673 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2674 
        },
2675 
        'entityName' => 'x_x77',
2676 
        'ports' => {
2677 
          'data_out' => {
2678 
            'attributes' => {
2679 
              'bin_pt' => 0,
2680 
              'is_floating_block' => 1,
2681 
              'must_be_hdl_vector' => 1,
2682 
              'period' => 1,
2683 
              'port_id' => 0,
2684 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
2685 
              'type' => 'UFix_1_0',
2686 
            },
2687 
            'direction' => 'out',
2688 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2689 
            'width' => 1,
2690 
          },
2691 
        },
2692 
      },
2693 
      'entityName' => 'x_x77',
2694 
    },
2695 
    'from_register25' => {
2696 
      'connections' => {
2697 
        'data_out' => 'from_register25.data_out',
2698 
      },
2699 
      'entity' => {
2700 
        'attributes' => {
2701 
          'entityAlreadyNetlisted' => 1,
2702 
          'generics' => [
2703 
          ],
2704 
          'is_floating_block' => 1,
2705 
          'mask' => {
2706 
            'Block_Handle' => 27.0009765625,
2707 
            'Block_handle' => 27.0009765625,
2708 
            'MDL_Handle' => 3.0009765625,
2709 
            'MDL_handle' => 3.0009765625,
2710 
            'arith_type' => 2,
2711 
            'bin_pt' => 0,
2712 
            'block_config' => 'sysgen_blockset:fromreg_config',
2713 
            'block_handle' => 27.0009765625,
2714 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2715 
            'block_type' => 'fromreg',
2716 
            'dbl_ovrd' => 0,
2717 
            'init' => 0,
2718 
            'init_bit_vector' => '00000000000000000000000000000000b',
2719 
            'mdl_handle' => 3.0009765625,
2720 
            'model_handle' => 3.0009765625,
2721 
            'n_bits' => 32,
2722 
            'ownership' => 2,
2723 
            'period' => '8e-009',
2724 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2725 
            'shared_memory_name' => 'register13rd',
2726 
          },
2727 
          'needs_vhdl_wrapper' => 0,
2728 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2729 
        },
2730 
        'entityName' => 'x_x78',
2731 
        'ports' => {
2732 
          'data_out' => {
2733 
            'attributes' => {
2734 
              'bin_pt' => 0,
2735 
              'is_floating_block' => 1,
2736 
              'must_be_hdl_vector' => 1,
2737 
              'period' => 1,
2738 
              'port_id' => 0,
2739 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
2740 
              'type' => 'UFix_32_0',
2741 
            },
2742 
            'direction' => 'out',
2743 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2744 
            'width' => 32,
2745 
          },
2746 
        },
2747 
      },
2748 
      'entityName' => 'x_x78',
2749 
    },
2750 
    'from_register26' => {
2751 
      'connections' => {
2752 
        'data_out' => 'from_register26.data_out',
2753 
      },
2754 
      'entity' => {
2755 
        'attributes' => {
2756 
          'entityAlreadyNetlisted' => 1,
2757 
          'generics' => [
2758 
          ],
2759 
          'is_floating_block' => 1,
2760 
          'mask' => {
2761 
            'Block_Handle' => 28.0009765625,
2762 
            'Block_handle' => 28.0009765625,
2763 
            'MDL_Handle' => 3.0009765625,
2764 
            'MDL_handle' => 3.0009765625,
2765 
            'arith_type' => 2,
2766 
            'bin_pt' => 0,
2767 
            'block_config' => 'sysgen_blockset:fromreg_config',
2768 
            'block_handle' => 28.0009765625,
2769 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2770 
            'block_type' => 'fromreg',
2771 
            'dbl_ovrd' => 0,
2772 
            'init' => 0,
2773 
            'init_bit_vector' => '0b',
2774 
            'mdl_handle' => 3.0009765625,
2775 
            'model_handle' => 3.0009765625,
2776 
            'n_bits' => 1,
2777 
            'ownership' => 2,
2778 
            'period' => '8e-009',
2779 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2780 
            'shared_memory_name' => 'register13rv',
2781 
          },
2782 
          'needs_vhdl_wrapper' => 0,
2783 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2784 
        },
2785 
        'entityName' => 'x_x79',
2786 
        'ports' => {
2787 
          'data_out' => {
2788 
            'attributes' => {
2789 
              'bin_pt' => 0,
2790 
              'is_floating_block' => 1,
2791 
              'must_be_hdl_vector' => 1,
2792 
              'period' => 1,
2793 
              'port_id' => 0,
2794 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
2795 
              'type' => 'UFix_1_0',
2796 
            },
2797 
            'direction' => 'out',
2798 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2799 
            'width' => 1,
2800 
          },
2801 
        },
2802 
      },
2803 
      'entityName' => 'x_x79',
2804 
    },
2805 
    'from_register27' => {
2806 
      'connections' => {
2807 
        'data_out' => 'from_register27.data_out',
2808 
      },
2809 
      'entity' => {
2810 
        'attributes' => {
2811 
          'entityAlreadyNetlisted' => 1,
2812 
          'generics' => [
2813 
          ],
2814 
          'is_floating_block' => 1,
2815 
          'mask' => {
2816 
            'Block_Handle' => 29.0009765625,
2817 
            'Block_handle' => 29.0009765625,
2818 
            'MDL_Handle' => 3.0009765625,
2819 
            'MDL_handle' => 3.0009765625,
2820 
            'arith_type' => 2,
2821 
            'bin_pt' => 0,
2822 
            'block_config' => 'sysgen_blockset:fromreg_config',
2823 
            'block_handle' => 29.0009765625,
2824 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2825 
            'block_type' => 'fromreg',
2826 
            'dbl_ovrd' => 0,
2827 
            'init' => 0,
2828 
            'init_bit_vector' => '00000000000000000000000000000000b',
2829 
            'mdl_handle' => 3.0009765625,
2830 
            'model_handle' => 3.0009765625,
2831 
            'n_bits' => 32,
2832 
            'ownership' => 2,
2833 
            'period' => '8e-009',
2834 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2835 
            'shared_memory_name' => 'register14rd',
2836 
          },
2837 
          'needs_vhdl_wrapper' => 0,
2838 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2839 
        },
2840 
        'entityName' => 'x_x80',
2841 
        'ports' => {
2842 
          'data_out' => {
2843 
            'attributes' => {
2844 
              'bin_pt' => 0,
2845 
              'is_floating_block' => 1,
2846 
              'must_be_hdl_vector' => 1,
2847 
              'period' => 1,
2848 
              'port_id' => 0,
2849 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
2850 
              'type' => 'UFix_32_0',
2851 
            },
2852 
            'direction' => 'out',
2853 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2854 
            'width' => 32,
2855 
          },
2856 
        },
2857 
      },
2858 
      'entityName' => 'x_x80',
2859 
    },
2860 
    'from_register28' => {
2861 
      'connections' => {
2862 
        'data_out' => 'from_register28.data_out',
2863 
      },
2864 
      'entity' => {
2865 
        'attributes' => {
2866 
          'entityAlreadyNetlisted' => 1,
2867 
          'generics' => [
2868 
          ],
2869 
          'is_floating_block' => 1,
2870 
          'mask' => {
2871 
            'Block_Handle' => 30.0009765625,
2872 
            'Block_handle' => 30.0009765625,
2873 
            'MDL_Handle' => 3.0009765625,
2874 
            'MDL_handle' => 3.0009765625,
2875 
            'arith_type' => 2,
2876 
            'bin_pt' => 0,
2877 
            'block_config' => 'sysgen_blockset:fromreg_config',
2878 
            'block_handle' => 30.0009765625,
2879 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2880 
            'block_type' => 'fromreg',
2881 
            'dbl_ovrd' => 0,
2882 
            'init' => 0,
2883 
            'init_bit_vector' => '0b',
2884 
            'mdl_handle' => 3.0009765625,
2885 
            'model_handle' => 3.0009765625,
2886 
            'n_bits' => 1,
2887 
            'ownership' => 2,
2888 
            'period' => '8e-009',
2889 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2890 
            'shared_memory_name' => 'register14rv',
2891 
          },
2892 
          'needs_vhdl_wrapper' => 0,
2893 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2894 
        },
2895 
        'entityName' => 'x_x81',
2896 
        'ports' => {
2897 
          'data_out' => {
2898 
            'attributes' => {
2899 
              'bin_pt' => 0,
2900 
              'is_floating_block' => 1,
2901 
              'must_be_hdl_vector' => 1,
2902 
              'period' => 1,
2903 
              'port_id' => 0,
2904 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
2905 
              'type' => 'UFix_1_0',
2906 
            },
2907 
            'direction' => 'out',
2908 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2909 
            'width' => 1,
2910 
          },
2911 
        },
2912 
      },
2913 
      'entityName' => 'x_x81',
2914 
    },
2915 
    'from_register3' => {
2916 
      'connections' => {
2917 
        'data_out' => 'from_register3.data_out',
2918 
      },
2919 
      'entity' => {
2920 
        'attributes' => {
2921 
          'entityAlreadyNetlisted' => 1,
2922 
          'generics' => [
2923 
          ],
2924 
          'is_floating_block' => 1,
2925 
          'mask' => {
2926 
            'Block_Handle' => 31.0009765625,
2927 
            'Block_handle' => 31.0009765625,
2928 
            'MDL_Handle' => 3.0009765625,
2929 
            'MDL_handle' => 3.0009765625,
2930 
            'arith_type' => 2,
2931 
            'bin_pt' => 0,
2932 
            'block_config' => 'sysgen_blockset:fromreg_config',
2933 
            'block_handle' => 31.0009765625,
2934 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2935 
            'block_type' => 'fromreg',
2936 
            'dbl_ovrd' => 0,
2937 
            'init' => 0,
2938 
            'init_bit_vector' => '00000000000000000000000000000000b',
2939 
            'mdl_handle' => 3.0009765625,
2940 
            'model_handle' => 3.0009765625,
2941 
            'n_bits' => 32,
2942 
            'ownership' => 2,
2943 
            'period' => '8e-009',
2944 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2945 
            'shared_memory_name' => 'register01rd',
2946 
          },
2947 
          'needs_vhdl_wrapper' => 0,
2948 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2949 
        },
2950 
        'entityName' => 'x_x82',
2951 
        'ports' => {
2952 
          'data_out' => {
2953 
            'attributes' => {
2954 
              'bin_pt' => 0,
2955 
              'is_floating_block' => 1,
2956 
              'must_be_hdl_vector' => 1,
2957 
              'period' => 1,
2958 
              'port_id' => 0,
2959 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
2960 
              'type' => 'UFix_32_0',
2961 
            },
2962 
            'direction' => 'out',
2963 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2964 
            'width' => 32,
2965 
          },
2966 
        },
2967 
      },
2968 
      'entityName' => 'x_x82',
2969 
    },
2970 
    'from_register4' => {
2971 
      'connections' => {
2972 
        'data_out' => 'from_register4.data_out',
2973 
      },
2974 
      'entity' => {
2975 
        'attributes' => {
2976 
          'entityAlreadyNetlisted' => 1,
2977 
          'generics' => [
2978 
          ],
2979 
          'is_floating_block' => 1,
2980 
          'mask' => {
2981 
            'Block_Handle' => 32.0009765625,
2982 
            'Block_handle' => 32.0009765625,
2983 
            'MDL_Handle' => 3.0009765625,
2984 
            'MDL_handle' => 3.0009765625,
2985 
            'arith_type' => 2,
2986 
            'bin_pt' => 0,
2987 
            'block_config' => 'sysgen_blockset:fromreg_config',
2988 
            'block_handle' => 32.0009765625,
2989 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
2990 
            'block_type' => 'fromreg',
2991 
            'dbl_ovrd' => 0,
2992 
            'init' => 0,
2993 
            'init_bit_vector' => '0b',
2994 
            'mdl_handle' => 3.0009765625,
2995 
            'model_handle' => 3.0009765625,
2996 
            'n_bits' => 1,
2997 
            'ownership' => 2,
2998 
            'period' => '8e-009',
2999 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3000 
            'shared_memory_name' => 'register04rv',
3001 
          },
3002 
          'needs_vhdl_wrapper' => 0,
3003 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
3004 
        },
3005 
        'entityName' => 'x_x83',
3006 
        'ports' => {
3007 
          'data_out' => {
3008 
            'attributes' => {
3009 
              'bin_pt' => 0,
3010 
              'is_floating_block' => 1,
3011 
              'must_be_hdl_vector' => 1,
3012 
              'period' => 1,
3013 
              'port_id' => 0,
3014 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
3015 
              'type' => 'UFix_1_0',
3016 
            },
3017 
            'direction' => 'out',
3018 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3019 
            'width' => 1,
3020 
          },
3021 
        },
3022 
      },
3023 
      'entityName' => 'x_x83',
3024 
    },
3025 
    'from_register5' => {
3026 
      'connections' => {
3027 
        'data_out' => 'from_register5.data_out',
3028 
      },
3029 
      'entity' => {
3030 
        'attributes' => {
3031 
          'entityAlreadyNetlisted' => 1,
3032 
          'generics' => [
3033 
          ],
3034 
          'is_floating_block' => 1,
3035 
          'mask' => {
3036 
            'Block_Handle' => 33.0009765625,
3037 
            'Block_handle' => 33.0009765625,
3038 
            'MDL_Handle' => 3.0009765625,
3039 
            'MDL_handle' => 3.0009765625,
3040 
            'arith_type' => 2,
3041 
            'bin_pt' => 0,
3042 
            'block_config' => 'sysgen_blockset:fromreg_config',
3043 
            'block_handle' => 33.0009765625,
3044 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
3045 
            'block_type' => 'fromreg',
3046 
            'dbl_ovrd' => 0,
3047 
            'init' => 0,
3048 
            'init_bit_vector' => '00000000000000000000000000000000b',
3049 
            'mdl_handle' => 3.0009765625,
3050 
            'model_handle' => 3.0009765625,
3051 
            'n_bits' => 32,
3052 
            'ownership' => 2,
3053 
            'period' => '8e-009',
3054 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3055 
            'shared_memory_name' => 'register02rd',
3056 
          },
3057 
          'needs_vhdl_wrapper' => 0,
3058 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
3059 
        },
3060 
        'entityName' => 'x_x84',
3061 
        'ports' => {
3062 
          'data_out' => {
3063 
            'attributes' => {
3064 
              'bin_pt' => 0,
3065 
              'is_floating_block' => 1,
3066 
              'must_be_hdl_vector' => 1,
3067 
              'period' => 1,
3068 
              'port_id' => 0,
3069 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
3070 
              'type' => 'UFix_32_0',
3071 
            },
3072 
            'direction' => 'out',
3073 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3074 
            'width' => 32,
3075 
          },
3076 
        },
3077 
      },
3078 
      'entityName' => 'x_x84',
3079 
    },
3080 
    'from_register6' => {
3081 
      'connections' => {
3082 
        'data_out' => 'from_register6.data_out',
3083 
      },
3084 
      'entity' => {
3085 
        'attributes' => {
3086 
          'entityAlreadyNetlisted' => 1,
3087 
          'generics' => [
3088 
          ],
3089 
          'is_floating_block' => 1,
3090 
          'mask' => {
3091 
            'Block_Handle' => 34.0009765625,
3092 
            'Block_handle' => 34.0009765625,
3093 
            'MDL_Handle' => 3.0009765625,
3094 
            'MDL_handle' => 3.0009765625,
3095 
            'arith_type' => 2,
3096 
            'bin_pt' => 0,
3097 
            'block_config' => 'sysgen_blockset:fromreg_config',
3098 
            'block_handle' => 34.0009765625,
3099 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3100 
            'block_type' => 'fromreg',
3101 
            'dbl_ovrd' => 0,
3102 
            'init' => 0,
3103 
            'init_bit_vector' => '0b',
3104 
            'mdl_handle' => 3.0009765625,
3105 
            'model_handle' => 3.0009765625,
3106 
            'n_bits' => 1,
3107 
            'ownership' => 2,
3108 
            'period' => '8e-009',
3109 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3110 
            'shared_memory_name' => 'register03rv',
3111 
          },
3112 
          'needs_vhdl_wrapper' => 0,
3113 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3114 
        },
3115 
        'entityName' => 'x_x85',
3116 
        'ports' => {
3117 
          'data_out' => {
3118 
            'attributes' => {
3119 
              'bin_pt' => 0,
3120 
              'is_floating_block' => 1,
3121 
              'must_be_hdl_vector' => 1,
3122 
              'period' => 1,
3123 
              'port_id' => 0,
3124 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
3125 
              'type' => 'UFix_1_0',
3126 
            },
3127 
            'direction' => 'out',
3128 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3129 
            'width' => 1,
3130 
          },
3131 
        },
3132 
      },
3133 
      'entityName' => 'x_x85',
3134 
    },
3135 
    'from_register7' => {
3136 
      'connections' => {
3137 
        'data_out' => 'from_register7.data_out',
3138 
      },
3139 
      'entity' => {
3140 
        'attributes' => {
3141 
          'entityAlreadyNetlisted' => 1,
3142 
          'generics' => [
3143 
          ],
3144 
          'is_floating_block' => 1,
3145 
          'mask' => {
3146 
            'Block_Handle' => 35.0009765625,
3147 
            'Block_handle' => 35.0009765625,
3148 
            'MDL_Handle' => 3.0009765625,
3149 
            'MDL_handle' => 3.0009765625,
3150 
            'arith_type' => 2,
3151 
            'bin_pt' => 0,
3152 
            'block_config' => 'sysgen_blockset:fromreg_config',
3153 
            'block_handle' => 35.0009765625,
3154 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3155 
            'block_type' => 'fromreg',
3156 
            'dbl_ovrd' => 0,
3157 
            'init' => 0,
3158 
            'init_bit_vector' => '00000000000000000000000000000000b',
3159 
            'mdl_handle' => 3.0009765625,
3160 
            'model_handle' => 3.0009765625,
3161 
            'n_bits' => 32,
3162 
            'ownership' => 2,
3163 
            'period' => '8e-009',
3164 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3165 
            'shared_memory_name' => 'register03rd',
3166 
          },
3167 
          'needs_vhdl_wrapper' => 0,
3168 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3169 
        },
3170 
        'entityName' => 'x_x86',
3171 
        'ports' => {
3172 
          'data_out' => {
3173 
            'attributes' => {
3174 
              'bin_pt' => 0,
3175 
              'is_floating_block' => 1,
3176 
              'must_be_hdl_vector' => 1,
3177 
              'period' => 1,
3178 
              'port_id' => 0,
3179 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
3180 
              'type' => 'UFix_32_0',
3181 
            },
3182 
            'direction' => 'out',
3183 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3184 
            'width' => 32,
3185 
          },
3186 
        },
3187 
      },
3188 
      'entityName' => 'x_x86',
3189 
    },
3190 
    'from_register8' => {
3191 
      'connections' => {
3192 
        'data_out' => 'from_register8.data_out',
3193 
      },
3194 
      'entity' => {
3195 
        'attributes' => {
3196 
          'entityAlreadyNetlisted' => 1,
3197 
          'generics' => [
3198 
          ],
3199 
          'is_floating_block' => 1,
3200 
          'mask' => {
3201 
            'Block_Handle' => 36.0009765625,
3202 
            'Block_handle' => 36.0009765625,
3203 
            'MDL_Handle' => 3.0009765625,
3204 
            'MDL_handle' => 3.0009765625,
3205 
            'arith_type' => 2,
3206 
            'bin_pt' => 0,
3207 
            'block_config' => 'sysgen_blockset:fromreg_config',
3208 
            'block_handle' => 36.0009765625,
3209 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3210 
            'block_type' => 'fromreg',
3211 
            'dbl_ovrd' => 0,
3212 
            'init' => 0,
3213 
            'init_bit_vector' => '00000000000000000000000000000000b',
3214 
            'mdl_handle' => 3.0009765625,
3215 
            'model_handle' => 3.0009765625,
3216 
            'n_bits' => 32,
3217 
            'ownership' => 2,
3218 
            'period' => '8e-009',
3219 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3220 
            'shared_memory_name' => 'register04rd',
3221 
          },
3222 
          'needs_vhdl_wrapper' => 0,
3223 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3224 
        },
3225 
        'entityName' => 'x_x87',
3226 
        'ports' => {
3227 
          'data_out' => {
3228 
            'attributes' => {
3229 
              'bin_pt' => 0,
3230 
              'is_floating_block' => 1,
3231 
              'must_be_hdl_vector' => 1,
3232 
              'period' => 1,
3233 
              'port_id' => 0,
3234 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
3235 
              'type' => 'UFix_32_0',
3236 
            },
3237 
            'direction' => 'out',
3238 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3239 
            'width' => 32,
3240 
          },
3241 
        },
3242 
      },
3243 
      'entityName' => 'x_x87',
3244 
    },
3245 
    'from_register9' => {
3246 
      'connections' => {
3247 
        'data_out' => 'from_register9.data_out',
3248 
      },
3249 
      'entity' => {
3250 
        'attributes' => {
3251 
          'entityAlreadyNetlisted' => 1,
3252 
          'generics' => [
3253 
          ],
3254 
          'is_floating_block' => 1,
3255 
          'mask' => {
3256 
            'Block_Handle' => 37.0009765625,
3257 
            'Block_handle' => 37.0009765625,
3258 
            'MDL_Handle' => 3.0009765625,
3259 
            'MDL_handle' => 3.0009765625,
3260 
            'arith_type' => 2,
3261 
            'bin_pt' => 0,
3262 
            'block_config' => 'sysgen_blockset:fromreg_config',
3263 
            'block_handle' => 37.0009765625,
3264 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3265 
            'block_type' => 'fromreg',
3266 
            'dbl_ovrd' => 0,
3267 
            'init' => 0,
3268 
            'init_bit_vector' => '0b',
3269 
            'mdl_handle' => 3.0009765625,
3270 
            'model_handle' => 3.0009765625,
3271 
            'n_bits' => 1,
3272 
            'ownership' => 2,
3273 
            'period' => '8e-009',
3274 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3275 
            'shared_memory_name' => 'register05rv',
3276 
          },
3277 
          'needs_vhdl_wrapper' => 0,
3278 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3279 
        },
3280 
        'entityName' => 'x_x88',
3281 
        'ports' => {
3282 
          'data_out' => {
3283 
            'attributes' => {
3284 
              'bin_pt' => 0,
3285 
              'is_floating_block' => 1,
3286 
              'must_be_hdl_vector' => 1,
3287 
              'period' => 1,
3288 
              'port_id' => 0,
3289 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
3290 
              'type' => 'UFix_1_0',
3291 
            },
3292 
            'direction' => 'out',
3293 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3294 
            'width' => 1,
3295 
          },
3296 
        },
3297 
      },
3298 
      'entityName' => 'x_x88',
3299 
    },
3300 
    'reg01_rd' => {
3301 
      'connections' => {
3302 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
3303 
      },
3304 
      'entity' => {
3305 
        'attributes' => {
3306 
          'entityAlreadyNetlisted' => 1,
3307 
          'isGateway' => 1,
3308 
          'is_floating_block' => 1,
3309 
        },
3310 
        'entityName' => 'reg01_rd',
3311 
        'ports' => {
3312 
          'reg01_rd' => {
3313 
            'attributes' => {
3314 
              'bin_pt' => 0,
3315 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
3316 
              'is_floating_block' => 1,
3317 
              'is_gateway_port' => 1,
3318 
              'must_be_hdl_vector' => 1,
3319 
              'period' => 1,
3320 
              'port_id' => 0,
3321 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
3322 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
3323 
              'timingConstraint' => 'none',
3324 
              'type' => 'UFix_32_0',
3325 
            },
3326 
            'direction' => 'in',
3327 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3328 
            'width' => 32,
3329 
          },
3330 
        },
3331 
      },
3332 
      'entityName' => 'reg01_rd',
3333 
    },
3334 
    'reg01_rv' => {
3335 
      'connections' => {
3336 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
3337 
      },
3338 
      'entity' => {
3339 
        'attributes' => {
3340 
          'entityAlreadyNetlisted' => 1,
3341 
          'isGateway' => 1,
3342 
          'is_floating_block' => 1,
3343 
        },
3344 
        'entityName' => 'reg01_rv',
3345 
        'ports' => {
3346 
          'reg01_rv' => {
3347 
            'attributes' => {
3348 
              'bin_pt' => 0,
3349 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
3350 
              'is_floating_block' => 1,
3351 
              'is_gateway_port' => 1,
3352 
              'must_be_hdl_vector' => 1,
3353 
              'period' => 1,
3354 
              'port_id' => 0,
3355 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
3356 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
3357 
              'timingConstraint' => 'none',
3358 
              'type' => 'UFix_1_0',
3359 
            },
3360 
            'direction' => 'in',
3361 
            'hdlType' => 'std_logic',
3362 
            'width' => 1,
3363 
          },
3364 
        },
3365 
      },
3366 
      'entityName' => 'reg01_rv',
3367 
    },
3368 
    'reg01_td' => {
3369 
      'connections' => {
3370 
        'reg01_td' => '.reg01_td',
3371 
      },
3372 
      'entity' => {
3373 
        'attributes' => {
3374 
          'entityAlreadyNetlisted' => 1,
3375 
          'isGateway' => 1,
3376 
          'is_floating_block' => 1,
3377 
        },
3378 
        'entityName' => 'reg01_td',
3379 
        'ports' => {
3380 
          'reg01_td' => {
3381 
            'attributes' => {
3382 
              'bin_pt' => 0,
3383 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
3384 
              'is_floating_block' => 1,
3385 
              'is_gateway_port' => 1,
3386 
              'must_be_hdl_vector' => 1,
3387 
              'period' => 1,
3388 
              'port_id' => 0,
3389 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
3390 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
3391 
              'timingConstraint' => 'none',
3392 
              'type' => 'UFix_32_0',
3393 
            },
3394 
            'direction' => 'out',
3395 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3396 
            'width' => 32,
3397 
          },
3398 
        },
3399 
      },
3400 
      'entityName' => 'reg01_td',
3401 
    },
3402 
    'reg01_tv' => {
3403 
      'connections' => {
3404 
        'reg01_tv' => '.reg01_tv',
3405 
      },
3406 
      'entity' => {
3407 
        'attributes' => {
3408 
          'entityAlreadyNetlisted' => 1,
3409 
          'isGateway' => 1,
3410 
          'is_floating_block' => 1,
3411 
        },
3412 
        'entityName' => 'reg01_tv',
3413 
        'ports' => {
3414 
          'reg01_tv' => {
3415 
            'attributes' => {
3416 
              'bin_pt' => 0,
3417 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
3418 
              'is_floating_block' => 1,
3419 
              'is_gateway_port' => 1,
3420 
              'must_be_hdl_vector' => 1,
3421 
              'period' => 1,
3422 
              'port_id' => 0,
3423 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
3424 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
3425 
              'timingConstraint' => 'none',
3426 
              'type' => 'Bool',
3427 
            },
3428 
            'direction' => 'out',
3429 
            'hdlType' => 'std_logic',
3430 
            'width' => 1,
3431 
          },
3432 
        },
3433 
      },
3434 
      'entityName' => 'reg01_tv',
3435 
    },
3436 
    'reg02_rd' => {
3437 
      'connections' => {
3438 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
3439 
      },
3440 
      'entity' => {
3441 
        'attributes' => {
3442 
          'entityAlreadyNetlisted' => 1,
3443 
          'isGateway' => 1,
3444 
          'is_floating_block' => 1,
3445 
        },
3446 
        'entityName' => 'reg02_rd',
3447 
        'ports' => {
3448 
          'reg02_rd' => {
3449 
            'attributes' => {
3450 
              'bin_pt' => 0,
3451 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
3452 
              'is_floating_block' => 1,
3453 
              'is_gateway_port' => 1,
3454 
              'must_be_hdl_vector' => 1,
3455 
              'period' => 1,
3456 
              'port_id' => 0,
3457 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
3458 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
3459 
              'timingConstraint' => 'none',
3460 
              'type' => 'UFix_32_0',
3461 
            },
3462 
            'direction' => 'in',
3463 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3464 
            'width' => 32,
3465 
          },
3466 
        },
3467 
      },
3468 
      'entityName' => 'reg02_rd',
3469 
    },
3470 
    'reg02_rv' => {
3471 
      'connections' => {
3472 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
3473 
      },
3474 
      'entity' => {
3475 
        'attributes' => {
3476 
          'entityAlreadyNetlisted' => 1,
3477 
          'isGateway' => 1,
3478 
          'is_floating_block' => 1,
3479 
        },
3480 
        'entityName' => 'reg02_rv',
3481 
        'ports' => {
3482 
          'reg02_rv' => {
3483 
            'attributes' => {
3484 
              'bin_pt' => 0,
3485 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
3486 
              'is_floating_block' => 1,
3487 
              'is_gateway_port' => 1,
3488 
              'must_be_hdl_vector' => 1,
3489 
              'period' => 1,
3490 
              'port_id' => 0,
3491 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
3492 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
3493 
              'timingConstraint' => 'none',
3494 
              'type' => 'UFix_1_0',
3495 
            },
3496 
            'direction' => 'in',
3497 
            'hdlType' => 'std_logic',
3498 
            'width' => 1,
3499 
          },
3500 
        },
3501 
      },
3502 
      'entityName' => 'reg02_rv',
3503 
    },
3504 
    'reg02_td' => {
3505 
      'connections' => {
3506 
        'reg02_td' => '.reg02_td',
3507 
      },
3508 
      'entity' => {
3509 
        'attributes' => {
3510 
          'entityAlreadyNetlisted' => 1,
3511 
          'isGateway' => 1,
3512 
          'is_floating_block' => 1,
3513 
        },
3514 
        'entityName' => 'reg02_td',
3515 
        'ports' => {
3516 
          'reg02_td' => {
3517 
            'attributes' => {
3518 
              'bin_pt' => 0,
3519 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
3520 
              'is_floating_block' => 1,
3521 
              'is_gateway_port' => 1,
3522 
              'must_be_hdl_vector' => 1,
3523 
              'period' => 1,
3524 
              'port_id' => 0,
3525 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
3526 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
3527 
              'timingConstraint' => 'none',
3528 
              'type' => 'UFix_32_0',
3529 
            },
3530 
            'direction' => 'out',
3531 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3532 
            'width' => 32,
3533 
          },
3534 
        },
3535 
      },
3536 
      'entityName' => 'reg02_td',
3537 
    },
3538 
    'reg02_tv' => {
3539 
      'connections' => {
3540 
        'reg02_tv' => '.reg02_tv',
3541 
      },
3542 
      'entity' => {
3543 
        'attributes' => {
3544 
          'entityAlreadyNetlisted' => 1,
3545 
          'isGateway' => 1,
3546 
          'is_floating_block' => 1,
3547 
        },
3548 
        'entityName' => 'reg02_tv',
3549 
        'ports' => {
3550 
          'reg02_tv' => {
3551 
            'attributes' => {
3552 
              'bin_pt' => 0,
3553 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
3554 
              'is_floating_block' => 1,
3555 
              'is_gateway_port' => 1,
3556 
              'must_be_hdl_vector' => 1,
3557 
              'period' => 1,
3558 
              'port_id' => 0,
3559 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
3560 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
3561 
              'timingConstraint' => 'none',
3562 
              'type' => 'Bool',
3563 
            },
3564 
            'direction' => 'out',
3565 
            'hdlType' => 'std_logic',
3566 
            'width' => 1,
3567 
          },
3568 
        },
3569 
      },
3570 
      'entityName' => 'reg02_tv',
3571 
    },
3572 
    'reg03_rd' => {
3573 
      'connections' => {
3574 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
3575 
      },
3576 
      'entity' => {
3577 
        'attributes' => {
3578 
          'entityAlreadyNetlisted' => 1,
3579 
          'isGateway' => 1,
3580 
          'is_floating_block' => 1,
3581 
        },
3582 
        'entityName' => 'reg03_rd',
3583 
        'ports' => {
3584 
          'reg03_rd' => {
3585 
            'attributes' => {
3586 
              'bin_pt' => 0,
3587 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
3588 
              'is_floating_block' => 1,
3589 
              'is_gateway_port' => 1,
3590 
              'must_be_hdl_vector' => 1,
3591 
              'period' => 1,
3592 
              'port_id' => 0,
3593 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
3594 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
3595 
              'timingConstraint' => 'none',
3596 
              'type' => 'UFix_32_0',
3597 
            },
3598 
            'direction' => 'in',
3599 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3600 
            'width' => 32,
3601 
          },
3602 
        },
3603 
      },
3604 
      'entityName' => 'reg03_rd',
3605 
    },
3606 
    'reg03_rv' => {
3607 
      'connections' => {
3608 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
3609 
      },
3610 
      'entity' => {
3611 
        'attributes' => {
3612 
          'entityAlreadyNetlisted' => 1,
3613 
          'isGateway' => 1,
3614 
          'is_floating_block' => 1,
3615 
        },
3616 
        'entityName' => 'reg03_rv',
3617 
        'ports' => {
3618 
          'reg03_rv' => {
3619 
            'attributes' => {
3620 
              'bin_pt' => 0,
3621 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
3622 
              'is_floating_block' => 1,
3623 
              'is_gateway_port' => 1,
3624 
              'must_be_hdl_vector' => 1,
3625 
              'period' => 1,
3626 
              'port_id' => 0,
3627 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
3628 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
3629 
              'timingConstraint' => 'none',
3630 
              'type' => 'UFix_1_0',
3631 
            },
3632 
            'direction' => 'in',
3633 
            'hdlType' => 'std_logic',
3634 
            'width' => 1,
3635 
          },
3636 
        },
3637 
      },
3638 
      'entityName' => 'reg03_rv',
3639 
    },
3640 
    'reg03_td' => {
3641 
      'connections' => {
3642 
        'reg03_td' => '.reg03_td',
3643 
      },
3644 
      'entity' => {
3645 
        'attributes' => {
3646 
          'entityAlreadyNetlisted' => 1,
3647 
          'isGateway' => 1,
3648 
          'is_floating_block' => 1,
3649 
        },
3650 
        'entityName' => 'reg03_td',
3651 
        'ports' => {
3652 
          'reg03_td' => {
3653 
            'attributes' => {
3654 
              'bin_pt' => 0,
3655 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
3656 
              'is_floating_block' => 1,
3657 
              'is_gateway_port' => 1,
3658 
              'must_be_hdl_vector' => 1,
3659 
              'period' => 1,
3660 
              'port_id' => 0,
3661 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
3662 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
3663 
              'timingConstraint' => 'none',
3664 
              'type' => 'UFix_32_0',
3665 
            },
3666 
            'direction' => 'out',
3667 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3668 
            'width' => 32,
3669 
          },
3670 
        },
3671 
      },
3672 
      'entityName' => 'reg03_td',
3673 
    },
3674 
    'reg03_tv' => {
3675 
      'connections' => {
3676 
        'reg03_tv' => '.reg03_tv',
3677 
      },
3678 
      'entity' => {
3679 
        'attributes' => {
3680 
          'entityAlreadyNetlisted' => 1,
3681 
          'isGateway' => 1,
3682 
          'is_floating_block' => 1,
3683 
        },
3684 
        'entityName' => 'reg03_tv',
3685 
        'ports' => {
3686 
          'reg03_tv' => {
3687 
            'attributes' => {
3688 
              'bin_pt' => 0,
3689 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
3690 
              'is_floating_block' => 1,
3691 
              'is_gateway_port' => 1,
3692 
              'must_be_hdl_vector' => 1,
3693 
              'period' => 1,
3694 
              'port_id' => 0,
3695 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
3696 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
3697 
              'timingConstraint' => 'none',
3698 
              'type' => 'Bool',
3699 
            },
3700 
            'direction' => 'out',
3701 
            'hdlType' => 'std_logic',
3702 
            'width' => 1,
3703 
          },
3704 
        },
3705 
      },
3706 
      'entityName' => 'reg03_tv',
3707 
    },
3708 
    'reg04_rd' => {
3709 
      'connections' => {
3710 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
3711 
      },
3712 
      'entity' => {
3713 
        'attributes' => {
3714 
          'entityAlreadyNetlisted' => 1,
3715 
          'isGateway' => 1,
3716 
          'is_floating_block' => 1,
3717 
        },
3718 
        'entityName' => 'reg04_rd',
3719 
        'ports' => {
3720 
          'reg04_rd' => {
3721 
            'attributes' => {
3722 
              'bin_pt' => 0,
3723 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
3724 
              'is_floating_block' => 1,
3725 
              'is_gateway_port' => 1,
3726 
              'must_be_hdl_vector' => 1,
3727 
              'period' => 1,
3728 
              'port_id' => 0,
3729 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
3730 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
3731 
              'timingConstraint' => 'none',
3732 
              'type' => 'UFix_32_0',
3733 
            },
3734 
            'direction' => 'in',
3735 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3736 
            'width' => 32,
3737 
          },
3738 
        },
3739 
      },
3740 
      'entityName' => 'reg04_rd',
3741 
    },
3742 
    'reg04_rv' => {
3743 
      'connections' => {
3744 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
3745 
      },
3746 
      'entity' => {
3747 
        'attributes' => {
3748 
          'entityAlreadyNetlisted' => 1,
3749 
          'isGateway' => 1,
3750 
          'is_floating_block' => 1,
3751 
        },
3752 
        'entityName' => 'reg04_rv',
3753 
        'ports' => {
3754 
          'reg04_rv' => {
3755 
            'attributes' => {
3756 
              'bin_pt' => 0,
3757 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
3758 
              'is_floating_block' => 1,
3759 
              'is_gateway_port' => 1,
3760 
              'must_be_hdl_vector' => 1,
3761 
              'period' => 1,
3762 
              'port_id' => 0,
3763 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
3764 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
3765 
              'timingConstraint' => 'none',
3766 
              'type' => 'UFix_1_0',
3767 
            },
3768 
            'direction' => 'in',
3769 
            'hdlType' => 'std_logic',
3770 
            'width' => 1,
3771 
          },
3772 
        },
3773 
      },
3774 
      'entityName' => 'reg04_rv',
3775 
    },
3776 
    'reg04_td' => {
3777 
      'connections' => {
3778 
        'reg04_td' => '.reg04_td',
3779 
      },
3780 
      'entity' => {
3781 
        'attributes' => {
3782 
          'entityAlreadyNetlisted' => 1,
3783 
          'isGateway' => 1,
3784 
          'is_floating_block' => 1,
3785 
        },
3786 
        'entityName' => 'reg04_td',
3787 
        'ports' => {
3788 
          'reg04_td' => {
3789 
            'attributes' => {
3790 
              'bin_pt' => 0,
3791 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
3792 
              'is_floating_block' => 1,
3793 
              'is_gateway_port' => 1,
3794 
              'must_be_hdl_vector' => 1,
3795 
              'period' => 1,
3796 
              'port_id' => 0,
3797 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
3798 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
3799 
              'timingConstraint' => 'none',
3800 
              'type' => 'UFix_32_0',
3801 
            },
3802 
            'direction' => 'out',
3803 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3804 
            'width' => 32,
3805 
          },
3806 
        },
3807 
      },
3808 
      'entityName' => 'reg04_td',
3809 
    },
3810 
    'reg04_tv' => {
3811 
      'connections' => {
3812 
        'reg04_tv' => '.reg04_tv',
3813 
      },
3814 
      'entity' => {
3815 
        'attributes' => {
3816 
          'entityAlreadyNetlisted' => 1,
3817 
          'isGateway' => 1,
3818 
          'is_floating_block' => 1,
3819 
        },
3820 
        'entityName' => 'reg04_tv',
3821 
        'ports' => {
3822 
          'reg04_tv' => {
3823 
            'attributes' => {
3824 
              'bin_pt' => 0,
3825 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
3826 
              'is_floating_block' => 1,
3827 
              'is_gateway_port' => 1,
3828 
              'must_be_hdl_vector' => 1,
3829 
              'period' => 1,
3830 
              'port_id' => 0,
3831 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
3832 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
3833 
              'timingConstraint' => 'none',
3834 
              'type' => 'Bool',
3835 
            },
3836 
            'direction' => 'out',
3837 
            'hdlType' => 'std_logic',
3838 
            'width' => 1,
3839 
          },
3840 
        },
3841 
      },
3842 
      'entityName' => 'reg04_tv',
3843 
    },
3844 
    'reg05_rd' => {
3845 
      'connections' => {
3846 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
3847 
      },
3848 
      'entity' => {
3849 
        'attributes' => {
3850 
          'entityAlreadyNetlisted' => 1,
3851 
          'isGateway' => 1,
3852 
          'is_floating_block' => 1,
3853 
        },
3854 
        'entityName' => 'reg05_rd',
3855 
        'ports' => {
3856 
          'reg05_rd' => {
3857 
            'attributes' => {
3858 
              'bin_pt' => 0,
3859 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
3860 
              'is_floating_block' => 1,
3861 
              'is_gateway_port' => 1,
3862 
              'must_be_hdl_vector' => 1,
3863 
              'period' => 1,
3864 
              'port_id' => 0,
3865 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
3866 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
3867 
              'timingConstraint' => 'none',
3868 
              'type' => 'UFix_32_0',
3869 
            },
3870 
            'direction' => 'in',
3871 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3872 
            'width' => 32,
3873 
          },
3874 
        },
3875 
      },
3876 
      'entityName' => 'reg05_rd',
3877 
    },
3878 
    'reg05_rv' => {
3879 
      'connections' => {
3880 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
3881 
      },
3882 
      'entity' => {
3883 
        'attributes' => {
3884 
          'entityAlreadyNetlisted' => 1,
3885 
          'isGateway' => 1,
3886 
          'is_floating_block' => 1,
3887 
        },
3888 
        'entityName' => 'reg05_rv',
3889 
        'ports' => {
3890 
          'reg05_rv' => {
3891 
            'attributes' => {
3892 
              'bin_pt' => 0,
3893 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
3894 
              'is_floating_block' => 1,
3895 
              'is_gateway_port' => 1,
3896 
              'must_be_hdl_vector' => 1,
3897 
              'period' => 1,
3898 
              'port_id' => 0,
3899 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
3900 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
3901 
              'timingConstraint' => 'none',
3902 
              'type' => 'UFix_1_0',
3903 
            },
3904 
            'direction' => 'in',
3905 
            'hdlType' => 'std_logic',
3906 
            'width' => 1,
3907 
          },
3908 
        },
3909 
      },
3910 
      'entityName' => 'reg05_rv',
3911 
    },
3912 
    'reg05_td' => {
3913 
      'connections' => {
3914 
        'reg05_td' => '.reg05_td',
3915 
      },
3916 
      'entity' => {
3917 
        'attributes' => {
3918 
          'entityAlreadyNetlisted' => 1,
3919 
          'isGateway' => 1,
3920 
          'is_floating_block' => 1,
3921 
        },
3922 
        'entityName' => 'reg05_td',
3923 
        'ports' => {
3924 
          'reg05_td' => {
3925 
            'attributes' => {
3926 
              'bin_pt' => 0,
3927 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
3928 
              'is_floating_block' => 1,
3929 
              'is_gateway_port' => 1,
3930 
              'must_be_hdl_vector' => 1,
3931 
              'period' => 1,
3932 
              'port_id' => 0,
3933 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
3934 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
3935 
              'timingConstraint' => 'none',
3936 
              'type' => 'UFix_32_0',
3937 
            },
3938 
            'direction' => 'out',
3939 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3940 
            'width' => 32,
3941 
          },
3942 
        },
3943 
      },
3944 
      'entityName' => 'reg05_td',
3945 
    },
3946 
    'reg05_tv' => {
3947 
      'connections' => {
3948 
        'reg05_tv' => '.reg05_tv',
3949 
      },
3950 
      'entity' => {
3951 
        'attributes' => {
3952 
          'entityAlreadyNetlisted' => 1,
3953 
          'isGateway' => 1,
3954 
          'is_floating_block' => 1,
3955 
        },
3956 
        'entityName' => 'reg05_tv',
3957 
        'ports' => {
3958 
          'reg05_tv' => {
3959 
            'attributes' => {
3960 
              'bin_pt' => 0,
3961 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
3962 
              'is_floating_block' => 1,
3963 
              'is_gateway_port' => 1,
3964 
              'must_be_hdl_vector' => 1,
3965 
              'period' => 1,
3966 
              'port_id' => 0,
3967 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
3968 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
3969 
              'timingConstraint' => 'none',
3970 
              'type' => 'Bool',
3971 
            },
3972 
            'direction' => 'out',
3973 
            'hdlType' => 'std_logic',
3974 
            'width' => 1,
3975 
          },
3976 
        },
3977 
      },
3978 
      'entityName' => 'reg05_tv',
3979 
    },
3980 
    'reg06_rd' => {
3981 
      'connections' => {
3982 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
3983 
      },
3984 
      'entity' => {
3985 
        'attributes' => {
3986 
          'entityAlreadyNetlisted' => 1,
3987 
          'isGateway' => 1,
3988 
          'is_floating_block' => 1,
3989 
        },
3990 
        'entityName' => 'reg06_rd',
3991 
        'ports' => {
3992 
          'reg06_rd' => {
3993 
            'attributes' => {
3994 
              'bin_pt' => 0,
3995 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
3996 
              'is_floating_block' => 1,
3997 
              'is_gateway_port' => 1,
3998 
              'must_be_hdl_vector' => 1,
3999 
              'period' => 1,
4000 
              'port_id' => 0,
4001 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
4002 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
4003 
              'timingConstraint' => 'none',
4004 
              'type' => 'UFix_32_0',
4005 
            },
4006 
            'direction' => 'in',
4007 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4008 
            'width' => 32,
4009 
          },
4010 
        },
4011 
      },
4012 
      'entityName' => 'reg06_rd',
4013 
    },
4014 
    'reg06_rv' => {
4015 
      'connections' => {
4016 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
4017 
      },
4018 
      'entity' => {
4019 
        'attributes' => {
4020 
          'entityAlreadyNetlisted' => 1,
4021 
          'isGateway' => 1,
4022 
          'is_floating_block' => 1,
4023 
        },
4024 
        'entityName' => 'reg06_rv',
4025 
        'ports' => {
4026 
          'reg06_rv' => {
4027 
            'attributes' => {
4028 
              'bin_pt' => 0,
4029 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
4030 
              'is_floating_block' => 1,
4031 
              'is_gateway_port' => 1,
4032 
              'must_be_hdl_vector' => 1,
4033 
              'period' => 1,
4034 
              'port_id' => 0,
4035 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
4036 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
4037 
              'timingConstraint' => 'none',
4038 
              'type' => 'UFix_1_0',
4039 
            },
4040 
            'direction' => 'in',
4041 
            'hdlType' => 'std_logic',
4042 
            'width' => 1,
4043 
          },
4044 
        },
4045 
      },
4046 
      'entityName' => 'reg06_rv',
4047 
    },
4048 
    'reg06_td' => {
4049 
      'connections' => {
4050 
        'reg06_td' => '.reg06_td',
4051 
      },
4052 
      'entity' => {
4053 
        'attributes' => {
4054 
          'entityAlreadyNetlisted' => 1,
4055 
          'isGateway' => 1,
4056 
          'is_floating_block' => 1,
4057 
        },
4058 
        'entityName' => 'reg06_td',
4059 
        'ports' => {
4060 
          'reg06_td' => {
4061 
            'attributes' => {
4062 
              'bin_pt' => 0,
4063 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
4064 
              'is_floating_block' => 1,
4065 
              'is_gateway_port' => 1,
4066 
              'must_be_hdl_vector' => 1,
4067 
              'period' => 1,
4068 
              'port_id' => 0,
4069 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
4070 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
4071 
              'timingConstraint' => 'none',
4072 
              'type' => 'UFix_32_0',
4073 
            },
4074 
            'direction' => 'out',
4075 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4076 
            'width' => 32,
4077 
          },
4078 
        },
4079 
      },
4080 
      'entityName' => 'reg06_td',
4081 
    },
4082 
    'reg06_tv' => {
4083 
      'connections' => {
4084 
        'reg06_tv' => '.reg06_tv',
4085 
      },
4086 
      'entity' => {
4087 
        'attributes' => {
4088 
          'entityAlreadyNetlisted' => 1,
4089 
          'isGateway' => 1,
4090 
          'is_floating_block' => 1,
4091 
        },
4092 
        'entityName' => 'reg06_tv',
4093 
        'ports' => {
4094 
          'reg06_tv' => {
4095 
            'attributes' => {
4096 
              'bin_pt' => 0,
4097 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
4098 
              'is_floating_block' => 1,
4099 
              'is_gateway_port' => 1,
4100 
              'must_be_hdl_vector' => 1,
4101 
              'period' => 1,
4102 
              'port_id' => 0,
4103 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
4104 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
4105 
              'timingConstraint' => 'none',
4106 
              'type' => 'Bool',
4107 
            },
4108 
            'direction' => 'out',
4109 
            'hdlType' => 'std_logic',
4110 
            'width' => 1,
4111 
          },
4112 
        },
4113 
      },
4114 
      'entityName' => 'reg06_tv',
4115 
    },
4116 
    'reg07_rd' => {
4117 
      'connections' => {
4118 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
4119 
      },
4120 
      'entity' => {
4121 
        'attributes' => {
4122 
          'entityAlreadyNetlisted' => 1,
4123 
          'isGateway' => 1,
4124 
          'is_floating_block' => 1,
4125 
        },
4126 
        'entityName' => 'reg07_rd',
4127 
        'ports' => {
4128 
          'reg07_rd' => {
4129 
            'attributes' => {
4130 
              'bin_pt' => 0,
4131 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
4132 
              'is_floating_block' => 1,
4133 
              'is_gateway_port' => 1,
4134 
              'must_be_hdl_vector' => 1,
4135 
              'period' => 1,
4136 
              'port_id' => 0,
4137 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
4138 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
4139 
              'timingConstraint' => 'none',
4140 
              'type' => 'UFix_32_0',
4141 
            },
4142 
            'direction' => 'in',
4143 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4144 
            'width' => 32,
4145 
          },
4146 
        },
4147 
      },
4148 
      'entityName' => 'reg07_rd',
4149 
    },
4150 
    'reg07_rv' => {
4151 
      'connections' => {
4152 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
4153 
      },
4154 
      'entity' => {
4155 
        'attributes' => {
4156 
          'entityAlreadyNetlisted' => 1,
4157 
          'isGateway' => 1,
4158 
          'is_floating_block' => 1,
4159 
        },
4160 
        'entityName' => 'reg07_rv',
4161 
        'ports' => {
4162 
          'reg07_rv' => {
4163 
            'attributes' => {
4164 
              'bin_pt' => 0,
4165 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
4166 
              'is_floating_block' => 1,
4167 
              'is_gateway_port' => 1,
4168 
              'must_be_hdl_vector' => 1,
4169 
              'period' => 1,
4170 
              'port_id' => 0,
4171 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
4172 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
4173 
              'timingConstraint' => 'none',
4174 
              'type' => 'UFix_1_0',
4175 
            },
4176 
            'direction' => 'in',
4177 
            'hdlType' => 'std_logic',
4178 
            'width' => 1,
4179 
          },
4180 
        },
4181 
      },
4182 
      'entityName' => 'reg07_rv',
4183 
    },
4184 
    'reg07_td' => {
4185 
      'connections' => {
4186 
        'reg07_td' => '.reg07_td',
4187 
      },
4188 
      'entity' => {
4189 
        'attributes' => {
4190 
          'entityAlreadyNetlisted' => 1,
4191 
          'isGateway' => 1,
4192 
          'is_floating_block' => 1,
4193 
        },
4194 
        'entityName' => 'reg07_td',
4195 
        'ports' => {
4196 
          'reg07_td' => {
4197 
            'attributes' => {
4198 
              'bin_pt' => 0,
4199 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
4200 
              'is_floating_block' => 1,
4201 
              'is_gateway_port' => 1,
4202 
              'must_be_hdl_vector' => 1,
4203 
              'period' => 1,
4204 
              'port_id' => 0,
4205 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
4206 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
4207 
              'timingConstraint' => 'none',
4208 
              'type' => 'UFix_32_0',
4209 
            },
4210 
            'direction' => 'out',
4211 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4212 
            'width' => 32,
4213 
          },
4214 
        },
4215 
      },
4216 
      'entityName' => 'reg07_td',
4217 
    },
4218 
    'reg07_tv' => {
4219 
      'connections' => {
4220 
        'reg07_tv' => '.reg07_tv',
4221 
      },
4222 
      'entity' => {
4223 
        'attributes' => {
4224 
          'entityAlreadyNetlisted' => 1,
4225 
          'isGateway' => 1,
4226 
          'is_floating_block' => 1,
4227 
        },
4228 
        'entityName' => 'reg07_tv',
4229 
        'ports' => {
4230 
          'reg07_tv' => {
4231 
            'attributes' => {
4232 
              'bin_pt' => 0,
4233 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
4234 
              'is_floating_block' => 1,
4235 
              'is_gateway_port' => 1,
4236 
              'must_be_hdl_vector' => 1,
4237 
              'period' => 1,
4238 
              'port_id' => 0,
4239 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
4240 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
4241 
              'timingConstraint' => 'none',
4242 
              'type' => 'Bool',
4243 
            },
4244 
            'direction' => 'out',
4245 
            'hdlType' => 'std_logic',
4246 
            'width' => 1,
4247 
          },
4248 
        },
4249 
      },
4250 
      'entityName' => 'reg07_tv',
4251 
    },
4252 
    'reg08_rd' => {
4253 
      'connections' => {
4254 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
4255 
      },
4256 
      'entity' => {
4257 
        'attributes' => {
4258 
          'entityAlreadyNetlisted' => 1,
4259 
          'isGateway' => 1,
4260 
          'is_floating_block' => 1,
4261 
        },
4262 
        'entityName' => 'reg08_rd',
4263 
        'ports' => {
4264 
          'reg08_rd' => {
4265 
            'attributes' => {
4266 
              'bin_pt' => 0,
4267 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
4268 
              'is_floating_block' => 1,
4269 
              'is_gateway_port' => 1,
4270 
              'must_be_hdl_vector' => 1,
4271 
              'period' => 1,
4272 
              'port_id' => 0,
4273 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
4274 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
4275 
              'timingConstraint' => 'none',
4276 
              'type' => 'UFix_32_0',
4277 
            },
4278 
            'direction' => 'in',
4279 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4280 
            'width' => 32,
4281 
          },
4282 
        },
4283 
      },
4284 
      'entityName' => 'reg08_rd',
4285 
    },
4286 
    'reg08_rv' => {
4287 
      'connections' => {
4288 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
4289 
      },
4290 
      'entity' => {
4291 
        'attributes' => {
4292 
          'entityAlreadyNetlisted' => 1,
4293 
          'isGateway' => 1,
4294 
          'is_floating_block' => 1,
4295 
        },
4296 
        'entityName' => 'reg08_rv',
4297 
        'ports' => {
4298 
          'reg08_rv' => {
4299 
            'attributes' => {
4300 
              'bin_pt' => 0,
4301 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
4302 
              'is_floating_block' => 1,
4303 
              'is_gateway_port' => 1,
4304 
              'must_be_hdl_vector' => 1,
4305 
              'period' => 1,
4306 
              'port_id' => 0,
4307 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
4308 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
4309 
              'timingConstraint' => 'none',
4310 
              'type' => 'UFix_1_0',
4311 
            },
4312 
            'direction' => 'in',
4313 
            'hdlType' => 'std_logic',
4314 
            'width' => 1,
4315 
          },
4316 
        },
4317 
      },
4318 
      'entityName' => 'reg08_rv',
4319 
    },
4320 
    'reg08_td' => {
4321 
      'connections' => {
4322 
        'reg08_td' => '.reg08_td',
4323 
      },
4324 
      'entity' => {
4325 
        'attributes' => {
4326 
          'entityAlreadyNetlisted' => 1,
4327 
          'isGateway' => 1,
4328 
          'is_floating_block' => 1,
4329 
        },
4330 
        'entityName' => 'reg08_td',
4331 
        'ports' => {
4332 
          'reg08_td' => {
4333 
            'attributes' => {
4334 
              'bin_pt' => 0,
4335 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
4336 
              'is_floating_block' => 1,
4337 
              'is_gateway_port' => 1,
4338 
              'must_be_hdl_vector' => 1,
4339 
              'period' => 1,
4340 
              'port_id' => 0,
4341 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
4342 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
4343 
              'timingConstraint' => 'none',
4344 
              'type' => 'UFix_32_0',
4345 
            },
4346 
            'direction' => 'out',
4347 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4348 
            'width' => 32,
4349 
          },
4350 
        },
4351 
      },
4352 
      'entityName' => 'reg08_td',
4353 
    },
4354 
    'reg08_tv' => {
4355 
      'connections' => {
4356 
        'reg08_tv' => '.reg08_tv',
4357 
      },
4358 
      'entity' => {
4359 
        'attributes' => {
4360 
          'entityAlreadyNetlisted' => 1,
4361 
          'isGateway' => 1,
4362 
          'is_floating_block' => 1,
4363 
        },
4364 
        'entityName' => 'reg08_tv',
4365 
        'ports' => {
4366 
          'reg08_tv' => {
4367 
            'attributes' => {
4368 
              'bin_pt' => 0,
4369 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
4370 
              'is_floating_block' => 1,
4371 
              'is_gateway_port' => 1,
4372 
              'must_be_hdl_vector' => 1,
4373 
              'period' => 1,
4374 
              'port_id' => 0,
4375 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
4376 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
4377 
              'timingConstraint' => 'none',
4378 
              'type' => 'Bool',
4379 
            },
4380 
            'direction' => 'out',
4381 
            'hdlType' => 'std_logic',
4382 
            'width' => 1,
4383 
          },
4384 
        },
4385 
      },
4386 
      'entityName' => 'reg08_tv',
4387 
    },
4388 
    'reg09_rd' => {
4389 
      'connections' => {
4390 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
4391 
      },
4392 
      'entity' => {
4393 
        'attributes' => {
4394 
          'entityAlreadyNetlisted' => 1,
4395 
          'isGateway' => 1,
4396 
          'is_floating_block' => 1,
4397 
        },
4398 
        'entityName' => 'reg09_rd',
4399 
        'ports' => {
4400 
          'reg09_rd' => {
4401 
            'attributes' => {
4402 
              'bin_pt' => 0,
4403 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
4404 
              'is_floating_block' => 1,
4405 
              'is_gateway_port' => 1,
4406 
              'must_be_hdl_vector' => 1,
4407 
              'period' => 1,
4408 
              'port_id' => 0,
4409 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
4410 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
4411 
              'timingConstraint' => 'none',
4412 
              'type' => 'UFix_32_0',
4413 
            },
4414 
            'direction' => 'in',
4415 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4416 
            'width' => 32,
4417 
          },
4418 
        },
4419 
      },
4420 
      'entityName' => 'reg09_rd',
4421 
    },
4422 
    'reg09_rv' => {
4423 
      'connections' => {
4424 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
4425 
      },
4426 
      'entity' => {
4427 
        'attributes' => {
4428 
          'entityAlreadyNetlisted' => 1,
4429 
          'isGateway' => 1,
4430 
          'is_floating_block' => 1,
4431 
        },
4432 
        'entityName' => 'reg09_rv',
4433 
        'ports' => {
4434 
          'reg09_rv' => {
4435 
            'attributes' => {
4436 
              'bin_pt' => 0,
4437 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
4438 
              'is_floating_block' => 1,
4439 
              'is_gateway_port' => 1,
4440 
              'must_be_hdl_vector' => 1,
4441 
              'period' => 1,
4442 
              'port_id' => 0,
4443 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
4444 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
4445 
              'timingConstraint' => 'none',
4446 
              'type' => 'UFix_1_0',
4447 
            },
4448 
            'direction' => 'in',
4449 
            'hdlType' => 'std_logic',
4450 
            'width' => 1,
4451 
          },
4452 
        },
4453 
      },
4454 
      'entityName' => 'reg09_rv',
4455 
    },
4456 
    'reg09_td' => {
4457 
      'connections' => {
4458 
        'reg09_td' => '.reg09_td',
4459 
      },
4460 
      'entity' => {
4461 
        'attributes' => {
4462 
          'entityAlreadyNetlisted' => 1,
4463 
          'isGateway' => 1,
4464 
          'is_floating_block' => 1,
4465 
        },
4466 
        'entityName' => 'reg09_td',
4467 
        'ports' => {
4468 
          'reg09_td' => {
4469 
            'attributes' => {
4470 
              'bin_pt' => 0,
4471 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
4472 
              'is_floating_block' => 1,
4473 
              'is_gateway_port' => 1,
4474 
              'must_be_hdl_vector' => 1,
4475 
              'period' => 1,
4476 
              'port_id' => 0,
4477 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
4478 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
4479 
              'timingConstraint' => 'none',
4480 
              'type' => 'UFix_32_0',
4481 
            },
4482 
            'direction' => 'out',
4483 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4484 
            'width' => 32,
4485 
          },
4486 
        },
4487 
      },
4488 
      'entityName' => 'reg09_td',
4489 
    },
4490 
    'reg09_tv' => {
4491 
      'connections' => {
4492 
        'reg09_tv' => '.reg09_tv',
4493 
      },
4494 
      'entity' => {
4495 
        'attributes' => {
4496 
          'entityAlreadyNetlisted' => 1,
4497 
          'isGateway' => 1,
4498 
          'is_floating_block' => 1,
4499 
        },
4500 
        'entityName' => 'reg09_tv',
4501 
        'ports' => {
4502 
          'reg09_tv' => {
4503 
            'attributes' => {
4504 
              'bin_pt' => 0,
4505 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
4506 
              'is_floating_block' => 1,
4507 
              'is_gateway_port' => 1,
4508 
              'must_be_hdl_vector' => 1,
4509 
              'period' => 1,
4510 
              'port_id' => 0,
4511 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
4512 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
4513 
              'timingConstraint' => 'none',
4514 
              'type' => 'Bool',
4515 
            },
4516 
            'direction' => 'out',
4517 
            'hdlType' => 'std_logic',
4518 
            'width' => 1,
4519 
          },
4520 
        },
4521 
      },
4522 
      'entityName' => 'reg09_tv',
4523 
    },
4524 
    'reg10_rd' => {
4525 
      'connections' => {
4526 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
4527 
      },
4528 
      'entity' => {
4529 
        'attributes' => {
4530 
          'entityAlreadyNetlisted' => 1,
4531 
          'isGateway' => 1,
4532 
          'is_floating_block' => 1,
4533 
        },
4534 
        'entityName' => 'reg10_rd',
4535 
        'ports' => {
4536 
          'reg10_rd' => {
4537 
            'attributes' => {
4538 
              'bin_pt' => 0,
4539 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
4540 
              'is_floating_block' => 1,
4541 
              'is_gateway_port' => 1,
4542 
              'must_be_hdl_vector' => 1,
4543 
              'period' => 1,
4544 
              'port_id' => 0,
4545 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
4546 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
4547 
              'timingConstraint' => 'none',
4548 
              'type' => 'UFix_32_0',
4549 
            },
4550 
            'direction' => 'in',
4551 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4552 
            'width' => 32,
4553 
          },
4554 
        },
4555 
      },
4556 
      'entityName' => 'reg10_rd',
4557 
    },
4558 
    'reg10_rv' => {
4559 
      'connections' => {
4560 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
4561 
      },
4562 
      'entity' => {
4563 
        'attributes' => {
4564 
          'entityAlreadyNetlisted' => 1,
4565 
          'isGateway' => 1,
4566 
          'is_floating_block' => 1,
4567 
        },
4568 
        'entityName' => 'reg10_rv',
4569 
        'ports' => {
4570 
          'reg10_rv' => {
4571 
            'attributes' => {
4572 
              'bin_pt' => 0,
4573 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
4574 
              'is_floating_block' => 1,
4575 
              'is_gateway_port' => 1,
4576 
              'must_be_hdl_vector' => 1,
4577 
              'period' => 1,
4578 
              'port_id' => 0,
4579 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
4580 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
4581 
              'timingConstraint' => 'none',
4582 
              'type' => 'UFix_1_0',
4583 
            },
4584 
            'direction' => 'in',
4585 
            'hdlType' => 'std_logic',
4586 
            'width' => 1,
4587 
          },
4588 
        },
4589 
      },
4590 
      'entityName' => 'reg10_rv',
4591 
    },
4592 
    'reg10_td' => {
4593 
      'connections' => {
4594 
        'reg10_td' => '.reg10_td',
4595 
      },
4596 
      'entity' => {
4597 
        'attributes' => {
4598 
          'entityAlreadyNetlisted' => 1,
4599 
          'isGateway' => 1,
4600 
          'is_floating_block' => 1,
4601 
        },
4602 
        'entityName' => 'reg10_td',
4603 
        'ports' => {
4604 
          'reg10_td' => {
4605 
            'attributes' => {
4606 
              'bin_pt' => 0,
4607 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
4608 
              'is_floating_block' => 1,
4609 
              'is_gateway_port' => 1,
4610 
              'must_be_hdl_vector' => 1,
4611 
              'period' => 1,
4612 
              'port_id' => 0,
4613 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
4614 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
4615 
              'timingConstraint' => 'none',
4616 
              'type' => 'UFix_32_0',
4617 
            },
4618 
            'direction' => 'out',
4619 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4620 
            'width' => 32,
4621 
          },
4622 
        },
4623 
      },
4624 
      'entityName' => 'reg10_td',
4625 
    },
4626 
    'reg10_tv' => {
4627 
      'connections' => {
4628 
        'reg10_tv' => '.reg10_tv',
4629 
      },
4630 
      'entity' => {
4631 
        'attributes' => {
4632 
          'entityAlreadyNetlisted' => 1,
4633 
          'isGateway' => 1,
4634 
          'is_floating_block' => 1,
4635 
        },
4636 
        'entityName' => 'reg10_tv',
4637 
        'ports' => {
4638 
          'reg10_tv' => {
4639 
            'attributes' => {
4640 
              'bin_pt' => 0,
4641 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
4642 
              'is_floating_block' => 1,
4643 
              'is_gateway_port' => 1,
4644 
              'must_be_hdl_vector' => 1,
4645 
              'period' => 1,
4646 
              'port_id' => 0,
4647 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
4648 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
4649 
              'timingConstraint' => 'none',
4650 
              'type' => 'Bool',
4651 
            },
4652 
            'direction' => 'out',
4653 
            'hdlType' => 'std_logic',
4654 
            'width' => 1,
4655 
          },
4656 
        },
4657 
      },
4658 
      'entityName' => 'reg10_tv',
4659 
    },
4660 
    'reg11_rd' => {
4661 
      'connections' => {
4662 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
4663 
      },
4664 
      'entity' => {
4665 
        'attributes' => {
4666 
          'entityAlreadyNetlisted' => 1,
4667 
          'isGateway' => 1,
4668 
          'is_floating_block' => 1,
4669 
        },
4670 
        'entityName' => 'reg11_rd',
4671 
        'ports' => {
4672 
          'reg11_rd' => {
4673 
            'attributes' => {
4674 
              'bin_pt' => 0,
4675 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
4676 
              'is_floating_block' => 1,
4677 
              'is_gateway_port' => 1,
4678 
              'must_be_hdl_vector' => 1,
4679 
              'period' => 1,
4680 
              'port_id' => 0,
4681 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
4682 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
4683 
              'timingConstraint' => 'none',
4684 
              'type' => 'UFix_32_0',
4685 
            },
4686 
            'direction' => 'in',
4687 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4688 
            'width' => 32,
4689 
          },
4690 
        },
4691 
      },
4692 
      'entityName' => 'reg11_rd',
4693 
    },
4694 
    'reg11_rv' => {
4695 
      'connections' => {
4696 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
4697 
      },
4698 
      'entity' => {
4699 
        'attributes' => {
4700 
          'entityAlreadyNetlisted' => 1,
4701 
          'isGateway' => 1,
4702 
          'is_floating_block' => 1,
4703 
        },
4704 
        'entityName' => 'reg11_rv',
4705 
        'ports' => {
4706 
          'reg11_rv' => {
4707 
            'attributes' => {
4708 
              'bin_pt' => 0,
4709 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
4710 
              'is_floating_block' => 1,
4711 
              'is_gateway_port' => 1,
4712 
              'must_be_hdl_vector' => 1,
4713 
              'period' => 1,
4714 
              'port_id' => 0,
4715 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
4716 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
4717 
              'timingConstraint' => 'none',
4718 
              'type' => 'UFix_1_0',
4719 
            },
4720 
            'direction' => 'in',
4721 
            'hdlType' => 'std_logic',
4722 
            'width' => 1,
4723 
          },
4724 
        },
4725 
      },
4726 
      'entityName' => 'reg11_rv',
4727 
    },
4728 
    'reg11_td' => {
4729 
      'connections' => {
4730 
        'reg11_td' => '.reg11_td',
4731 
      },
4732 
      'entity' => {
4733 
        'attributes' => {
4734 
          'entityAlreadyNetlisted' => 1,
4735 
          'isGateway' => 1,
4736 
          'is_floating_block' => 1,
4737 
        },
4738 
        'entityName' => 'reg11_td',
4739 
        'ports' => {
4740 
          'reg11_td' => {
4741 
            'attributes' => {
4742 
              'bin_pt' => 0,
4743 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
4744 
              'is_floating_block' => 1,
4745 
              'is_gateway_port' => 1,
4746 
              'must_be_hdl_vector' => 1,
4747 
              'period' => 1,
4748 
              'port_id' => 0,
4749 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
4750 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
4751 
              'timingConstraint' => 'none',
4752 
              'type' => 'UFix_32_0',
4753 
            },
4754 
            'direction' => 'out',
4755 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4756 
            'width' => 32,
4757 
          },
4758 
        },
4759 
      },
4760 
      'entityName' => 'reg11_td',
4761 
    },
4762 
    'reg11_tv' => {
4763 
      'connections' => {
4764 
        'reg11_tv' => '.reg11_tv',
4765 
      },
4766 
      'entity' => {
4767 
        'attributes' => {
4768 
          'entityAlreadyNetlisted' => 1,
4769 
          'isGateway' => 1,
4770 
          'is_floating_block' => 1,
4771 
        },
4772 
        'entityName' => 'reg11_tv',
4773 
        'ports' => {
4774 
          'reg11_tv' => {
4775 
            'attributes' => {
4776 
              'bin_pt' => 0,
4777 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
4778 
              'is_floating_block' => 1,
4779 
              'is_gateway_port' => 1,
4780 
              'must_be_hdl_vector' => 1,
4781 
              'period' => 1,
4782 
              'port_id' => 0,
4783 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
4784 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
4785 
              'timingConstraint' => 'none',
4786 
              'type' => 'Bool',
4787 
            },
4788 
            'direction' => 'out',
4789 
            'hdlType' => 'std_logic',
4790 
            'width' => 1,
4791 
          },
4792 
        },
4793 
      },
4794 
      'entityName' => 'reg11_tv',
4795 
    },
4796 
    'reg12_rd' => {
4797 
      'connections' => {
4798 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
4799 
      },
4800 
      'entity' => {
4801 
        'attributes' => {
4802 
          'entityAlreadyNetlisted' => 1,
4803 
          'isGateway' => 1,
4804 
          'is_floating_block' => 1,
4805 
        },
4806 
        'entityName' => 'reg12_rd',
4807 
        'ports' => {
4808 
          'reg12_rd' => {
4809 
            'attributes' => {
4810 
              'bin_pt' => 0,
4811 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
4812 
              'is_floating_block' => 1,
4813 
              'is_gateway_port' => 1,
4814 
              'must_be_hdl_vector' => 1,
4815 
              'period' => 1,
4816 
              'port_id' => 0,
4817 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
4818 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
4819 
              'timingConstraint' => 'none',
4820 
              'type' => 'UFix_32_0',
4821 
            },
4822 
            'direction' => 'in',
4823 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4824 
            'width' => 32,
4825 
          },
4826 
        },
4827 
      },
4828 
      'entityName' => 'reg12_rd',
4829 
    },
4830 
    'reg12_rv' => {
4831 
      'connections' => {
4832 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
4833 
      },
4834 
      'entity' => {
4835 
        'attributes' => {
4836 
          'entityAlreadyNetlisted' => 1,
4837 
          'isGateway' => 1,
4838 
          'is_floating_block' => 1,
4839 
        },
4840 
        'entityName' => 'reg12_rv',
4841 
        'ports' => {
4842 
          'reg12_rv' => {
4843 
            'attributes' => {
4844 
              'bin_pt' => 0,
4845 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
4846 
              'is_floating_block' => 1,
4847 
              'is_gateway_port' => 1,
4848 
              'must_be_hdl_vector' => 1,
4849 
              'period' => 1,
4850 
              'port_id' => 0,
4851 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
4852 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
4853 
              'timingConstraint' => 'none',
4854 
              'type' => 'UFix_1_0',
4855 
            },
4856 
            'direction' => 'in',
4857 
            'hdlType' => 'std_logic',
4858 
            'width' => 1,
4859 
          },
4860 
        },
4861 
      },
4862 
      'entityName' => 'reg12_rv',
4863 
    },
4864 
    'reg12_td' => {
4865 
      'connections' => {
4866 
        'reg12_td' => '.reg12_td',
4867 
      },
4868 
      'entity' => {
4869 
        'attributes' => {
4870 
          'entityAlreadyNetlisted' => 1,
4871 
          'isGateway' => 1,
4872 
          'is_floating_block' => 1,
4873 
        },
4874 
        'entityName' => 'reg12_td',
4875 
        'ports' => {
4876 
          'reg12_td' => {
4877 
            'attributes' => {
4878 
              'bin_pt' => 0,
4879 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
4880 
              'is_floating_block' => 1,
4881 
              'is_gateway_port' => 1,
4882 
              'must_be_hdl_vector' => 1,
4883 
              'period' => 1,
4884 
              'port_id' => 0,
4885 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
4886 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
4887 
              'timingConstraint' => 'none',
4888 
              'type' => 'UFix_32_0',
4889 
            },
4890 
            'direction' => 'out',
4891 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4892 
            'width' => 32,
4893 
          },
4894 
        },
4895 
      },
4896 
      'entityName' => 'reg12_td',
4897 
    },
4898 
    'reg12_tv' => {
4899 
      'connections' => {
4900 
        'reg12_tv' => '.reg12_tv',
4901 
      },
4902 
      'entity' => {
4903 
        'attributes' => {
4904 
          'entityAlreadyNetlisted' => 1,
4905 
          'isGateway' => 1,
4906 
          'is_floating_block' => 1,
4907 
        },
4908 
        'entityName' => 'reg12_tv',
4909 
        'ports' => {
4910 
          'reg12_tv' => {
4911 
            'attributes' => {
4912 
              'bin_pt' => 0,
4913 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
4914 
              'is_floating_block' => 1,
4915 
              'is_gateway_port' => 1,
4916 
              'must_be_hdl_vector' => 1,
4917 
              'period' => 1,
4918 
              'port_id' => 0,
4919 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
4920 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
4921 
              'timingConstraint' => 'none',
4922 
              'type' => 'Bool',
4923 
            },
4924 
            'direction' => 'out',
4925 
            'hdlType' => 'std_logic',
4926 
            'width' => 1,
4927 
          },
4928 
        },
4929 
      },
4930 
      'entityName' => 'reg12_tv',
4931 
    },
4932 
    'reg13_rd' => {
4933 
      'connections' => {
4934 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
4935 
      },
4936 
      'entity' => {
4937 
        'attributes' => {
4938 
          'entityAlreadyNetlisted' => 1,
4939 
          'isGateway' => 1,
4940 
          'is_floating_block' => 1,
4941 
        },
4942 
        'entityName' => 'reg13_rd',
4943 
        'ports' => {
4944 
          'reg13_rd' => {
4945 
            'attributes' => {
4946 
              'bin_pt' => 0,
4947 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
4948 
              'is_floating_block' => 1,
4949 
              'is_gateway_port' => 1,
4950 
              'must_be_hdl_vector' => 1,
4951 
              'period' => 1,
4952 
              'port_id' => 0,
4953 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
4954 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
4955 
              'timingConstraint' => 'none',
4956 
              'type' => 'UFix_32_0',
4957 
            },
4958 
            'direction' => 'in',
4959 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4960 
            'width' => 32,
4961 
          },
4962 
        },
4963 
      },
4964 
      'entityName' => 'reg13_rd',
4965 
    },
4966 
    'reg13_rv' => {
4967 
      'connections' => {
4968 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
4969 
      },
4970 
      'entity' => {
4971 
        'attributes' => {
4972 
          'entityAlreadyNetlisted' => 1,
4973 
          'isGateway' => 1,
4974 
          'is_floating_block' => 1,
4975 
        },
4976 
        'entityName' => 'reg13_rv',
4977 
        'ports' => {
4978 
          'reg13_rv' => {
4979 
            'attributes' => {
4980 
              'bin_pt' => 0,
4981 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
4982 
              'is_floating_block' => 1,
4983 
              'is_gateway_port' => 1,
4984 
              'must_be_hdl_vector' => 1,
4985 
              'period' => 1,
4986 
              'port_id' => 0,
4987 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
4988 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
4989 
              'timingConstraint' => 'none',
4990 
              'type' => 'UFix_1_0',
4991 
            },
4992 
            'direction' => 'in',
4993 
            'hdlType' => 'std_logic',
4994 
            'width' => 1,
4995 
          },
4996 
        },
4997 
      },
4998 
      'entityName' => 'reg13_rv',
4999 
    },
5000 
    'reg13_td' => {
5001 
      'connections' => {
5002 
        'reg13_td' => '.reg13_td',
5003 
      },
5004 
      'entity' => {
5005 
        'attributes' => {
5006 
          'entityAlreadyNetlisted' => 1,
5007 
          'isGateway' => 1,
5008 
          'is_floating_block' => 1,
5009 
        },
5010 
        'entityName' => 'reg13_td',
5011 
        'ports' => {
5012 
          'reg13_td' => {
5013 
            'attributes' => {
5014 
              'bin_pt' => 0,
5015 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
5016 
              'is_floating_block' => 1,
5017 
              'is_gateway_port' => 1,
5018 
              'must_be_hdl_vector' => 1,
5019 
              'period' => 1,
5020 
              'port_id' => 0,
5021 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
5022 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
5023 
              'timingConstraint' => 'none',
5024 
              'type' => 'UFix_32_0',
5025 
            },
5026 
            'direction' => 'out',
5027 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5028 
            'width' => 32,
5029 
          },
5030 
        },
5031 
      },
5032 
      'entityName' => 'reg13_td',
5033 
    },
5034 
    'reg13_tv' => {
5035 
      'connections' => {
5036 
        'reg13_tv' => '.reg13_tv',
5037 
      },
5038 
      'entity' => {
5039 
        'attributes' => {
5040 
          'entityAlreadyNetlisted' => 1,
5041 
          'isGateway' => 1,
5042 
          'is_floating_block' => 1,
5043 
        },
5044 
        'entityName' => 'reg13_tv',
5045 
        'ports' => {
5046 
          'reg13_tv' => {
5047 
            'attributes' => {
5048 
              'bin_pt' => 0,
5049 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
5050 
              'is_floating_block' => 1,
5051 
              'is_gateway_port' => 1,
5052 
              'must_be_hdl_vector' => 1,
5053 
              'period' => 1,
5054 
              'port_id' => 0,
5055 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
5056 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
5057 
              'timingConstraint' => 'none',
5058 
              'type' => 'Bool',
5059 
            },
5060 
            'direction' => 'out',
5061 
            'hdlType' => 'std_logic',
5062 
            'width' => 1,
5063 
          },
5064 
        },
5065 
      },
5066 
      'entityName' => 'reg13_tv',
5067 
    },
5068 
    'reg14_rd' => {
5069 
      'connections' => {
5070 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5071 
      },
5072 
      'entity' => {
5073 
        'attributes' => {
5074 
          'entityAlreadyNetlisted' => 1,
5075 
          'isGateway' => 1,
5076 
          'is_floating_block' => 1,
5077 
        },
5078 
        'entityName' => 'reg14_rd',
5079 
        'ports' => {
5080 
          'reg14_rd' => {
5081 
            'attributes' => {
5082 
              'bin_pt' => 0,
5083 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
5084 
              'is_floating_block' => 1,
5085 
              'is_gateway_port' => 1,
5086 
              'must_be_hdl_vector' => 1,
5087 
              'period' => 1,
5088 
              'port_id' => 0,
5089 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
5090 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
5091 
              'timingConstraint' => 'none',
5092 
              'type' => 'UFix_32_0',
5093 
            },
5094 
            'direction' => 'in',
5095 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5096 
            'width' => 32,
5097 
          },
5098 
        },
5099 
      },
5100 
      'entityName' => 'reg14_rd',
5101 
    },
5102 
    'reg14_rv' => {
5103 
      'connections' => {
5104 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5105 
      },
5106 
      'entity' => {
5107 
        'attributes' => {
5108 
          'entityAlreadyNetlisted' => 1,
5109 
          'isGateway' => 1,
5110 
          'is_floating_block' => 1,
5111 
        },
5112 
        'entityName' => 'reg14_rv',
5113 
        'ports' => {
5114 
          'reg14_rv' => {
5115 
            'attributes' => {
5116 
              'bin_pt' => 0,
5117 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
5118 
              'is_floating_block' => 1,
5119 
              'is_gateway_port' => 1,
5120 
              'must_be_hdl_vector' => 1,
5121 
              'period' => 1,
5122 
              'port_id' => 0,
5123 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
5124 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
5125 
              'timingConstraint' => 'none',
5126 
              'type' => 'UFix_1_0',
5127 
            },
5128 
            'direction' => 'in',
5129 
            'hdlType' => 'std_logic',
5130 
            'width' => 1,
5131 
          },
5132 
        },
5133 
      },
5134 
      'entityName' => 'reg14_rv',
5135 
    },
5136 
    'reg14_td' => {
5137 
      'connections' => {
5138 
        'reg14_td' => '.reg14_td',
5139 
      },
5140 
      'entity' => {
5141 
        'attributes' => {
5142 
          'entityAlreadyNetlisted' => 1,
5143 
          'isGateway' => 1,
5144 
          'is_floating_block' => 1,
5145 
        },
5146 
        'entityName' => 'reg14_td',
5147 
        'ports' => {
5148 
          'reg14_td' => {
5149 
            'attributes' => {
5150 
              'bin_pt' => 0,
5151 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
5152 
              'is_floating_block' => 1,
5153 
              'is_gateway_port' => 1,
5154 
              'must_be_hdl_vector' => 1,
5155 
              'period' => 1,
5156 
              'port_id' => 0,
5157 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
5158 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
5159 
              'timingConstraint' => 'none',
5160 
              'type' => 'UFix_32_0',
5161 
            },
5162 
            'direction' => 'out',
5163 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5164 
            'width' => 32,
5165 
          },
5166 
        },
5167 
      },
5168 
      'entityName' => 'reg14_td',
5169 
    },
5170 
    'reg14_tv' => {
5171 
      'connections' => {
5172 
        'reg14_tv' => '.reg14_tv',
5173 
      },
5174 
      'entity' => {
5175 
        'attributes' => {
5176 
          'entityAlreadyNetlisted' => 1,
5177 
          'isGateway' => 1,
5178 
          'is_floating_block' => 1,
5179 
        },
5180 
        'entityName' => 'reg14_tv',
5181 
        'ports' => {
5182 
          'reg14_tv' => {
5183 
            'attributes' => {
5184 
              'bin_pt' => 0,
5185 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
5186 
              'is_floating_block' => 1,
5187 
              'is_gateway_port' => 1,
5188 
              'must_be_hdl_vector' => 1,
5189 
              'period' => 1,
5190 
              'port_id' => 0,
5191 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
5192 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
5193 
              'timingConstraint' => 'none',
5194 
              'type' => 'Bool',
5195 
            },
5196 
            'direction' => 'out',
5197 
            'hdlType' => 'std_logic',
5198 
            'width' => 1,
5199 
          },
5200 
        },
5201 
      },
5202 
      'entityName' => 'reg14_tv',
5203 
    },
5204 
    'sysgen_dut' => {
5205 
      'connections' => {
5206 
        'clk' => '.clk',
5207 
        'debug_in_1i' => '.debug_in_1i',
5208 
        'debug_in_2i' => '.debug_in_2i',
5209 
        'debug_in_3i' => '.debug_in_3i',
5210 
        'debug_in_4i' => '.debug_in_4i',
5211 
        'dma_host2board_busy' => '.dma_host2board_busy',
5212 
        'dma_host2board_done' => '.dma_host2board_done',
5213 
        'from_register10_data_out' => 'from_register10.data_out',
5214 
        'from_register11_data_out' => 'from_register11.data_out',
5215 
        'from_register12_data_out' => 'from_register12.data_out',
5216 
        'from_register13_data_out' => 'from_register13.data_out',
5217 
        'from_register14_data_out' => 'from_register14.data_out',
5218 
        'from_register15_data_out' => 'from_register15.data_out',
5219 
        'from_register16_data_out' => 'from_register16.data_out',
5220 
        'from_register17_data_out' => 'from_register17.data_out',
5221 
        'from_register18_data_out' => 'from_register18.data_out',
5222 
        'from_register19_data_out' => 'from_register19.data_out',
5223 
        'from_register1_data_out' => 'from_register1.data_out',
5224 
        'from_register20_data_out' => 'from_register20.data_out',
5225 
        'from_register21_data_out' => 'from_register21.data_out',
5226 
        'from_register22_data_out' => 'from_register22.data_out',
5227 
        'from_register23_data_out' => 'from_register23.data_out',
5228 
        'from_register24_data_out' => 'from_register24.data_out',
5229 
        'from_register25_data_out' => 'from_register25.data_out',
5230 
        'from_register26_data_out' => 'from_register26.data_out',
5231 
        'from_register27_data_out' => 'from_register27.data_out',
5232 
        'from_register28_data_out' => 'from_register28.data_out',
5233 
        'from_register2_data_out' => 'from_register2.data_out',
5234 
        'from_register3_data_out' => 'from_register3.data_out',
5235 
        'from_register4_data_out' => 'from_register4.data_out',
5236 
        'from_register5_data_out' => 'from_register5.data_out',
5237 
        'from_register6_data_out' => 'from_register6.data_out',
5238 
        'from_register7_data_out' => 'from_register7.data_out',
5239 
        'from_register8_data_out' => 'from_register8.data_out',
5240 
        'from_register9_data_out' => 'from_register9.data_out',
5241 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5242 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5243 
        'reg01_td' => '.reg01_td',
5244 
        'reg01_tv' => '.reg01_tv',
5245 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5246 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5247 
        'reg02_td' => '.reg02_td',
5248 
        'reg02_tv' => '.reg02_tv',
5249 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5250 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5251 
        'reg03_td' => '.reg03_td',
5252 
        'reg03_tv' => '.reg03_tv',
5253 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5254 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5255 
        'reg04_td' => '.reg04_td',
5256 
        'reg04_tv' => '.reg04_tv',
5257 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5258 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5259 
        'reg05_td' => '.reg05_td',
5260 
        'reg05_tv' => '.reg05_tv',
5261 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5262 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5263 
        'reg06_td' => '.reg06_td',
5264 
        'reg06_tv' => '.reg06_tv',
5265 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5266 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5267 
        'reg07_td' => '.reg07_td',
5268 
        'reg07_tv' => '.reg07_tv',
5269 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5270 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5271 
        'reg08_td' => '.reg08_td',
5272 
        'reg08_tv' => '.reg08_tv',
5273 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5274 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5275 
        'reg09_td' => '.reg09_td',
5276 
        'reg09_tv' => '.reg09_tv',
5277 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5278 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5279 
        'reg10_td' => '.reg10_td',
5280 
        'reg10_tv' => '.reg10_tv',
5281 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5282 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5283 
        'reg11_td' => '.reg11_td',
5284 
        'reg11_tv' => '.reg11_tv',
5285 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5286 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5287 
        'reg12_td' => '.reg12_td',
5288 
        'reg12_tv' => '.reg12_tv',
5289 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5290 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5291 
        'reg13_td' => '.reg13_td',
5292 
        'reg13_tv' => '.reg13_tv',
5293 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5294 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5295 
        'reg14_td' => '.reg14_td',
5296 
        'reg14_tv' => '.reg14_tv',
5297 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5298 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5299 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5300 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5301 
        'to_register10_dout' => 'to_register10.dout',
5302 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5303 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5304 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5305 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5306 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5307 
        'to_register11_dout' => 'to_register11.dout',
5308 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5309 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5310 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5311 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5312 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5313 
        'to_register12_dout' => 'to_register12.dout',
5314 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5315 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5316 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5317 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5318 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5319 
        'to_register13_dout' => 'to_register13.dout',
5320 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5321 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5322 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5323 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5324 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5325 
        'to_register14_dout' => 'to_register14.dout',
5326 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5327 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5328 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5329 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5330 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5331 
        'to_register15_dout' => 'to_register15.dout',
5332 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5333 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5334 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5335 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5336 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5337 
        'to_register16_dout' => 'to_register16.dout',
5338 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5339 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5340 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5341 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5342 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5343 
        'to_register17_dout' => 'to_register17.dout',
5344 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5345 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5346 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5347 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5348 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5349 
        'to_register18_dout' => 'to_register18.dout',
5350 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5351 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5352 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5353 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5354 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5355 
        'to_register19_dout' => 'to_register19.dout',
5356 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5357 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5358 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5359 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5360 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5361 
        'to_register1_dout' => 'to_register1.dout',
5362 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5363 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5364 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5365 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5366 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5367 
        'to_register20_dout' => 'to_register20.dout',
5368 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5369 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5370 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5371 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5372 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5373 
        'to_register21_dout' => 'to_register21.dout',
5374 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5375 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5376 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5377 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5378 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5379 
        'to_register22_dout' => 'to_register22.dout',
5380 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5381 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5382 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5383 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5384 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5385 
        'to_register23_dout' => 'to_register23.dout',
5386 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5387 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5388 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5389 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5390 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5391 
        'to_register24_dout' => 'to_register24.dout',
5392 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5393 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5394 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5395 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5396 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5397 
        'to_register25_dout' => 'to_register25.dout',
5398 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5399 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5400 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5401 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5402 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5403 
        'to_register26_dout' => 'to_register26.dout',
5404 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5405 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5406 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5407 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5408 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5409 
        'to_register27_dout' => 'to_register27.dout',
5410 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5411 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5412 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5413 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5414 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5415 
        'to_register28_dout' => 'to_register28.dout',
5416 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5417 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5418 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5419 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5420 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5421 
        'to_register29_dout' => 'to_register29.dout',
5422 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5423 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5424 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5425 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5426 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5427 
        'to_register2_dout' => 'to_register2.dout',
5428 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5429 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5430 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5431 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5432 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5433 
        'to_register30_dout' => 'to_register30.dout',
5434 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5435 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5436 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5437 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5438 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5439 
        'to_register31_dout' => 'to_register31.dout',
5440 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5441 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5442 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5443 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5444 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5445 
        'to_register32_dout' => 'to_register32.dout',
5446 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5447 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5448 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5449 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5450 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5451 
        'to_register33_dout' => 'to_register33.dout',
5452 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5453 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5454 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5455 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5456 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5457 
        'to_register34_dout' => 'to_register34.dout',
5458 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5459 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5460 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5461 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5462 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5463 
        'to_register3_dout' => 'to_register3.dout',
5464 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5465 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5466 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5467 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5468 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5469 
        'to_register4_dout' => 'to_register4.dout',
5470 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5471 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5472 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5473 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5474 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5475 
        'to_register5_dout' => 'to_register5.dout',
5476 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5477 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5478 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5479 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5480 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5481 
        'to_register6_dout' => 'to_register6.dout',
5482 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5483 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5484 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5485 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5486 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5487 
        'to_register7_dout' => 'to_register7.dout',
5488 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5489 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5490 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5491 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5492 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5493 
        'to_register8_dout' => 'to_register8.dout',
5494 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5495 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5496 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5497 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5498 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5499 
        'to_register9_dout' => 'to_register9.dout',
5500 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5501 
      },
5502 
      'entity' => {
5503 
        'attributes' => {
5504 
          'entityAlreadyNetlisted' => 1,
5505 
          'hdlArchAttributes' => [
5506 
          ],
5507 
          'hdlEntityAttributes' => [
5508 
          ],
5509 
          'isClkWrapper' => 1,
5510 
        },
5511 
        'connections' => {
5512 
          'clk' => 'clkNet',
5513 
          'debug_in_1i' => 'debug_in_1i_net',
5514 
          'debug_in_2i' => 'debug_in_2i_net',
5515 
          'debug_in_3i' => 'debug_in_3i_net',
5516 
          'debug_in_4i' => 'debug_in_4i_net',
5517 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5518 
          'dma_host2board_done' => 'dma_host2board_done_net',
5519 
          'from_register10_data_out' => 'from_register10_data_out_net',
5520 
          'from_register11_data_out' => 'from_register11_data_out_net',
5521 
          'from_register12_data_out' => 'from_register12_data_out_net',
5522 
          'from_register13_data_out' => 'from_register13_data_out_net',
5523 
          'from_register14_data_out' => 'from_register14_data_out_net',
5524 
          'from_register15_data_out' => 'from_register15_data_out_net',
5525 
          'from_register16_data_out' => 'from_register16_data_out_net',
5526 
          'from_register17_data_out' => 'from_register17_data_out_net',
5527 
          'from_register18_data_out' => 'from_register18_data_out_net',
5528 
          'from_register19_data_out' => 'from_register19_data_out_net',
5529 
          'from_register1_data_out' => 'from_register1_data_out_net',
5530 
          'from_register20_data_out' => 'from_register20_data_out_net',
5531 
          'from_register21_data_out' => 'from_register21_data_out_net',
5532 
          'from_register22_data_out' => 'from_register22_data_out_net',
5533 
          'from_register23_data_out' => 'from_register23_data_out_net',
5534 
          'from_register24_data_out' => 'from_register24_data_out_net',
5535 
          'from_register25_data_out' => 'from_register25_data_out_net',
5536 
          'from_register26_data_out' => 'from_register26_data_out_net',
5537 
          'from_register27_data_out' => 'from_register27_data_out_net',
5538 
          'from_register28_data_out' => 'from_register28_data_out_net',
5539 
          'from_register2_data_out' => 'from_register2_data_out_net',
5540 
          'from_register3_data_out' => 'from_register3_data_out_net',
5541 
          'from_register4_data_out' => 'from_register4_data_out_net',
5542 
          'from_register5_data_out' => 'from_register5_data_out_net',
5543 
          'from_register6_data_out' => 'from_register6_data_out_net',
5544 
          'from_register7_data_out' => 'from_register7_data_out_net',
5545 
          'from_register8_data_out' => 'from_register8_data_out_net',
5546 
          'from_register9_data_out' => 'from_register9_data_out_net',
5547 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5548 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5549 
          'reg01_td' => 'reg01_td_net',
5550 
          'reg01_tv' => 'reg01_tv_net',
5551 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5552 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5553 
          'reg02_td' => 'reg02_td_net',
5554 
          'reg02_tv' => 'reg02_tv_net',
5555 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5556 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5557 
          'reg03_td' => 'reg03_td_net',
5558 
          'reg03_tv' => 'reg03_tv_net',
5559 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5560 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5561 
          'reg04_td' => 'reg04_td_net',
5562 
          'reg04_tv' => 'reg04_tv_net',
5563 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5564 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5565 
          'reg05_td' => 'reg05_td_net',
5566 
          'reg05_tv' => 'reg05_tv_net',
5567 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5568 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5569 
          'reg06_td' => 'reg06_td_net',
5570 
          'reg06_tv' => 'reg06_tv_net',
5571 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5572 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5573 
          'reg07_td' => 'reg07_td_net',
5574 
          'reg07_tv' => 'reg07_tv_net',
5575 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5576 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5577 
          'reg08_td' => 'reg08_td_net',
5578 
          'reg08_tv' => 'reg08_tv_net',
5579 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5580 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5581 
          'reg09_td' => 'reg09_td_net',
5582 
          'reg09_tv' => 'reg09_tv_net',
5583 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5584 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5585 
          'reg10_td' => 'reg10_td_net',
5586 
          'reg10_tv' => 'reg10_tv_net',
5587 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5588 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5589 
          'reg11_td' => 'reg11_td_net',
5590 
          'reg11_tv' => 'reg11_tv_net',
5591 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5592 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5593 
          'reg12_td' => 'reg12_td_net',
5594 
          'reg12_tv' => 'reg12_tv_net',
5595 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5596 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5597 
          'reg13_td' => 'reg13_td_net',
5598 
          'reg13_tv' => 'reg13_tv_net',
5599 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5600 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5601 
          'reg14_td' => 'reg14_td_net',
5602 
          'reg14_tv' => 'reg14_tv_net',
5603 
          'to_register10_ce' => 'ce_1_sg',
5604 
          'to_register10_clk' => 'clk_1_sg',
5605 
          'to_register10_clr' => [
5606 
            'constant',
5607 
            '\'0\'',
5608 
          ],
5609 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5610 
          'to_register10_dout' => 'to_register10_dout_net',
5611 
          'to_register10_en' => 'constant5_op_net_x1',
5612 
          'to_register11_ce' => 'ce_1_sg',
5613 
          'to_register11_clk' => 'clk_1_sg',
5614 
          'to_register11_clr' => [
5615 
            'constant',
5616 
            '\'0\'',
5617 
          ],
5618 
          'to_register11_data_in' => 'reg04_td_net_x0',
5619 
          'to_register11_dout' => 'to_register11_dout_net',
5620 
          'to_register11_en' => 'constant5_op_net_x2',
5621 
          'to_register12_ce' => 'ce_1_sg',
5622 
          'to_register12_clk' => 'clk_1_sg',
5623 
          'to_register12_clr' => [
5624 
            'constant',
5625 
            '\'0\'',
5626 
          ],
5627 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5628 
          'to_register12_dout' => 'to_register12_dout_net',
5629 
          'to_register12_en' => 'constant5_op_net_x3',
5630 
          'to_register13_ce' => 'ce_1_sg',
5631 
          'to_register13_clk' => 'clk_1_sg',
5632 
          'to_register13_clr' => [
5633 
            'constant',
5634 
            '\'0\'',
5635 
          ],
5636 
          'to_register13_data_in' => 'reg05_td_net_x0',
5637 
          'to_register13_dout' => 'to_register13_dout_net',
5638 
          'to_register13_en' => 'constant5_op_net_x4',
5639 
          'to_register14_ce' => 'ce_1_sg',
5640 
          'to_register14_clk' => 'clk_1_sg',
5641 
          'to_register14_clr' => [
5642 
            'constant',
5643 
            '\'0\'',
5644 
          ],
5645 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5646 
          'to_register14_dout' => 'to_register14_dout_net',
5647 
          'to_register14_en' => 'constant5_op_net_x5',
5648 
          'to_register15_ce' => 'ce_1_sg',
5649 
          'to_register15_clk' => 'clk_1_sg',
5650 
          'to_register15_clr' => [
5651 
            'constant',
5652 
            '\'0\'',
5653 
          ],
5654 
          'to_register15_data_in' => 'reg06_td_net_x0',
5655 
          'to_register15_dout' => 'to_register15_dout_net',
5656 
          'to_register15_en' => 'constant5_op_net_x6',
5657 
          'to_register16_ce' => 'ce_1_sg',
5658 
          'to_register16_clk' => 'clk_1_sg',
5659 
          'to_register16_clr' => [
5660 
            'constant',
5661 
            '\'0\'',
5662 
          ],
5663 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5664 
          'to_register16_dout' => 'to_register16_dout_net',
5665 
          'to_register16_en' => 'constant5_op_net_x7',
5666 
          'to_register17_ce' => 'ce_1_sg',
5667 
          'to_register17_clk' => 'clk_1_sg',
5668 
          'to_register17_clr' => [
5669 
            'constant',
5670 
            '\'0\'',
5671 
          ],
5672 
          'to_register17_data_in' => 'reg07_td_net_x0',
5673 
          'to_register17_dout' => 'to_register17_dout_net',
5674 
          'to_register17_en' => 'constant5_op_net_x8',
5675 
          'to_register18_ce' => 'ce_1_sg',
5676 
          'to_register18_clk' => 'clk_1_sg',
5677 
          'to_register18_clr' => [
5678 
            'constant',
5679 
            '\'0\'',
5680 
          ],
5681 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5682 
          'to_register18_dout' => 'to_register18_dout_net',
5683 
          'to_register18_en' => 'constant5_op_net_x9',
5684 
          'to_register19_ce' => 'ce_1_sg',
5685 
          'to_register19_clk' => 'clk_1_sg',
5686 
          'to_register19_clr' => [
5687 
            'constant',
5688 
            '\'0\'',
5689 
          ],
5690 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5691 
          'to_register19_dout' => 'to_register19_dout_net',
5692 
          'to_register19_en' => 'constant5_op_net_x10',
5693 
          'to_register1_ce' => 'ce_1_sg',
5694 
          'to_register1_clk' => 'clk_1_sg',
5695 
          'to_register1_clr' => [
5696 
            'constant',
5697 
            '\'0\'',
5698 
          ],
5699 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5700 
          'to_register1_dout' => 'to_register1_dout_net',
5701 
          'to_register1_en' => 'constant5_op_net_x0',
5702 
          'to_register20_ce' => 'ce_1_sg',
5703 
          'to_register20_clk' => 'clk_1_sg',
5704 
          'to_register20_clr' => [
5705 
            'constant',
5706 
            '\'0\'',
5707 
          ],
5708 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5709 
          'to_register20_dout' => 'to_register20_dout_net',
5710 
          'to_register20_en' => 'constant5_op_net_x12',
5711 
          'to_register21_ce' => 'ce_1_sg',
5712 
          'to_register21_clk' => 'clk_1_sg',
5713 
          'to_register21_clr' => [
5714 
            'constant',
5715 
            '\'0\'',
5716 
          ],
5717 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5718 
          'to_register21_dout' => 'to_register21_dout_net',
5719 
          'to_register21_en' => 'constant1_op_net_x0',
5720 
          'to_register22_ce' => 'ce_1_sg',
5721 
          'to_register22_clk' => 'clk_1_sg',
5722 
          'to_register22_clr' => [
5723 
            'constant',
5724 
            '\'0\'',
5725 
          ],
5726 
          'to_register22_data_in' => 'reg09_td_net_x0',
5727 
          'to_register22_dout' => 'to_register22_dout_net',
5728 
          'to_register22_en' => 'constant1_op_net_x1',
5729 
          'to_register23_ce' => 'ce_1_sg',
5730 
          'to_register23_clk' => 'clk_1_sg',
5731 
          'to_register23_clr' => [
5732 
            'constant',
5733 
            '\'0\'',
5734 
          ],
5735 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5736 
          'to_register23_dout' => 'to_register23_dout_net',
5737 
          'to_register23_en' => 'constant1_op_net_x2',
5738 
          'to_register24_ce' => 'ce_1_sg',
5739 
          'to_register24_clk' => 'clk_1_sg',
5740 
          'to_register24_clr' => [
5741 
            'constant',
5742 
            '\'0\'',
5743 
          ],
5744 
          'to_register24_data_in' => 'reg10_td_net_x0',
5745 
          'to_register24_dout' => 'to_register24_dout_net',
5746 
          'to_register24_en' => 'constant1_op_net_x3',
5747 
          'to_register25_ce' => 'ce_1_sg',
5748 
          'to_register25_clk' => 'clk_1_sg',
5749 
          'to_register25_clr' => [
5750 
            'constant',
5751 
            '\'0\'',
5752 
          ],
5753 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5754 
          'to_register25_dout' => 'to_register25_dout_net',
5755 
          'to_register25_en' => 'constant1_op_net_x4',
5756 
          'to_register26_ce' => 'ce_1_sg',
5757 
          'to_register26_clk' => 'clk_1_sg',
5758 
          'to_register26_clr' => [
5759 
            'constant',
5760 
            '\'0\'',
5761 
          ],
5762 
          'to_register26_data_in' => 'reg08_td_net_x0',
5763 
          'to_register26_dout' => 'to_register26_dout_net',
5764 
          'to_register26_en' => 'constant1_op_net_x5',
5765 
          'to_register27_ce' => 'ce_1_sg',
5766 
          'to_register27_clk' => 'clk_1_sg',
5767 
          'to_register27_clr' => [
5768 
            'constant',
5769 
            '\'0\'',
5770 
          ],
5771 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5772 
          'to_register27_dout' => 'to_register27_dout_net',
5773 
          'to_register27_en' => 'constant1_op_net_x6',
5774 
          'to_register28_ce' => 'ce_1_sg',
5775 
          'to_register28_clk' => 'clk_1_sg',
5776 
          'to_register28_clr' => [
5777 
            'constant',
5778 
            '\'0\'',
5779 
          ],
5780 
          'to_register28_data_in' => 'reg11_td_net_x0',
5781 
          'to_register28_dout' => 'to_register28_dout_net',
5782 
          'to_register28_en' => 'constant1_op_net_x7',
5783 
          'to_register29_ce' => 'ce_1_sg',
5784 
          'to_register29_clk' => 'clk_1_sg',
5785 
          'to_register29_clr' => [
5786 
            'constant',
5787 
            '\'0\'',
5788 
          ],
5789 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5790 
          'to_register29_dout' => 'to_register29_dout_net',
5791 
          'to_register29_en' => 'constant1_op_net_x8',
5792 
          'to_register2_ce' => 'ce_1_sg',
5793 
          'to_register2_clk' => 'clk_1_sg',
5794 
          'to_register2_clr' => [
5795 
            'constant',
5796 
            '\'0\'',
5797 
          ],
5798 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5799 
          'to_register2_dout' => 'to_register2_dout_net',
5800 
          'to_register2_en' => 'constant5_op_net_x11',
5801 
          'to_register30_ce' => 'ce_1_sg',
5802 
          'to_register30_clk' => 'clk_1_sg',
5803 
          'to_register30_clr' => [
5804 
            'constant',
5805 
            '\'0\'',
5806 
          ],
5807 
          'to_register30_data_in' => 'reg12_td_net_x0',
5808 
          'to_register30_dout' => 'to_register30_dout_net',
5809 
          'to_register30_en' => 'constant1_op_net_x9',
5810 
          'to_register31_ce' => 'ce_1_sg',
5811 
          'to_register31_clk' => 'clk_1_sg',
5812 
          'to_register31_clr' => [
5813 
            'constant',
5814 
            '\'0\'',
5815 
          ],
5816 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5817 
          'to_register31_dout' => 'to_register31_dout_net',
5818 
          'to_register31_en' => 'constant1_op_net_x10',
5819 
          'to_register32_ce' => 'ce_1_sg',
5820 
          'to_register32_clk' => 'clk_1_sg',
5821 
          'to_register32_clr' => [
5822 
            'constant',
5823 
            '\'0\'',
5824 
          ],
5825 
          'to_register32_data_in' => 'reg13_td_net_x0',
5826 
          'to_register32_dout' => 'to_register32_dout_net',
5827 
          'to_register32_en' => 'constant1_op_net_x11',
5828 
          'to_register33_ce' => 'ce_1_sg',
5829 
          'to_register33_clk' => 'clk_1_sg',
5830 
          'to_register33_clr' => [
5831 
            'constant',
5832 
            '\'0\'',
5833 
          ],
5834 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5835 
          'to_register33_dout' => 'to_register33_dout_net',
5836 
          'to_register33_en' => 'constant1_op_net_x12',
5837 
          'to_register34_ce' => 'ce_1_sg',
5838 
          'to_register34_clk' => 'clk_1_sg',
5839 
          'to_register34_clr' => [
5840 
            'constant',
5841 
            '\'0\'',
5842 
          ],
5843 
          'to_register34_data_in' => 'reg14_td_net_x0',
5844 
          'to_register34_dout' => 'to_register34_dout_net',
5845 
          'to_register34_en' => 'constant1_op_net_x13',
5846 
          'to_register3_ce' => 'ce_1_sg',
5847 
          'to_register3_clk' => 'clk_1_sg',
5848 
          'to_register3_clr' => [
5849 
            'constant',
5850 
            '\'0\'',
5851 
          ],
5852 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5853 
          'to_register3_dout' => 'to_register3_dout_net',
5854 
          'to_register3_en' => 'constant5_op_net_x13',
5855 
          'to_register4_ce' => 'ce_1_sg',
5856 
          'to_register4_clk' => 'clk_1_sg',
5857 
          'to_register4_clr' => [
5858 
            'constant',
5859 
            '\'0\'',
5860 
          ],
5861 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5862 
          'to_register4_dout' => 'to_register4_dout_net',
5863 
          'to_register4_en' => 'constant5_op_net_x14',
5864 
          'to_register5_ce' => 'ce_1_sg',
5865 
          'to_register5_clk' => 'clk_1_sg',
5866 
          'to_register5_clr' => [
5867 
            'constant',
5868 
            '\'0\'',
5869 
          ],
5870 
          'to_register5_data_in' => 'reg02_td_net_x0',
5871 
          'to_register5_dout' => 'to_register5_dout_net',
5872 
          'to_register5_en' => 'constant5_op_net_x15',
5873 
          'to_register6_ce' => 'ce_1_sg',
5874 
          'to_register6_clk' => 'clk_1_sg',
5875 
          'to_register6_clr' => [
5876 
            'constant',
5877 
            '\'0\'',
5878 
          ],
5879 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5880 
          'to_register6_dout' => 'to_register6_dout_net',
5881 
          'to_register6_en' => 'constant5_op_net_x16',
5882 
          'to_register7_ce' => 'ce_1_sg',
5883 
          'to_register7_clk' => 'clk_1_sg',
5884 
          'to_register7_clr' => [
5885 
            'constant',
5886 
            '\'0\'',
5887 
          ],
5888 
          'to_register7_data_in' => 'reg01_td_net_x0',
5889 
          'to_register7_dout' => 'to_register7_dout_net',
5890 
          'to_register7_en' => 'constant5_op_net_x17',
5891 
          'to_register8_ce' => 'ce_1_sg',
5892 
          'to_register8_clk' => 'clk_1_sg',
5893 
          'to_register8_clr' => [
5894 
            'constant',
5895 
            '\'0\'',
5896 
          ],
5897 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5898 
          'to_register8_dout' => 'to_register8_dout_net',
5899 
          'to_register8_en' => 'constant5_op_net_x18',
5900 
          'to_register9_ce' => 'ce_1_sg',
5901 
          'to_register9_clk' => 'clk_1_sg',
5902 
          'to_register9_clr' => [
5903 
            'constant',
5904 
            '\'0\'',
5905 
          ],
5906 
          'to_register9_data_in' => 'reg03_td_net_x0',
5907 
          'to_register9_dout' => 'to_register9_dout_net',
5908 
          'to_register9_en' => 'constant5_op_net_x19',
5909 
        },
5910 
        'entityName' => 'inout_logic_cw',
5911 
        'nets' => {
5912 
          'ce_1_sg' => {
5913 
            'attributes' => {
5914 
              'hdlNetAttributes' => [
5915 
                [
5916 
                  'MAX_FANOUT',
5917 
                  'string',
5918 
                  '"REDUCE"',
5919 
                ],
5920 
              ],
5921 
            },
5922 
            'hdlType' => 'std_logic',
5923 
            'width' => 1,
5924 
          },
5925 
          'clkNet' => {
5926 
            'attributes' => {
5927 
              'hdlNetAttributes' => [
5928 
              ],
5929 
            },
5930 
            'hdlType' => 'std_logic',
5931 
            'width' => 1,
5932 
          },
5933 
          'clk_1_sg' => {
5934 
            'attributes' => {
5935 
              'hdlNetAttributes' => [
5936 
              ],
5937 
            },
5938 
            'hdlType' => 'std_logic',
5939 
            'width' => 1,
5940 
          },
5941 
          'constant1_op_net_x0' => {
5942 
            'attributes' => {
5943 
              'hdlNetAttributes' => [
5944 
              ],
5945 
            },
5946 
            'hdlType' => 'std_logic',
5947 
            'width' => 1,
5948 
          },
5949 
          'constant1_op_net_x1' => {
5950 
            'attributes' => {
5951 
              'hdlNetAttributes' => [
5952 
              ],
5953 
            },
5954 
            'hdlType' => 'std_logic',
5955 
            'width' => 1,
5956 
          },
5957 
          'constant1_op_net_x10' => {
5958 
            'attributes' => {
5959 
              'hdlNetAttributes' => [
5960 
              ],
5961 
            },
5962 
            'hdlType' => 'std_logic',
5963 
            'width' => 1,
5964 
          },
5965 
          'constant1_op_net_x11' => {
5966 
            'attributes' => {
5967 
              'hdlNetAttributes' => [
5968 
              ],
5969 
            },
5970 
            'hdlType' => 'std_logic',
5971 
            'width' => 1,
5972 
          },
5973 
          'constant1_op_net_x12' => {
5974 
            'attributes' => {
5975 
              'hdlNetAttributes' => [
5976 
              ],
5977 
            },
5978 
            'hdlType' => 'std_logic',
5979 
            'width' => 1,
5980 
          },
5981 
          'constant1_op_net_x13' => {
5982 
            'attributes' => {
5983 
              'hdlNetAttributes' => [
5984 
              ],
5985 
            },
5986 
            'hdlType' => 'std_logic',
5987 
            'width' => 1,
5988 
          },
5989 
          'constant1_op_net_x2' => {
5990 
            'attributes' => {
5991 
              'hdlNetAttributes' => [
5992 
              ],
5993 
            },
5994 
            'hdlType' => 'std_logic',
5995 
            'width' => 1,
5996 
          },
5997 
          'constant1_op_net_x3' => {
5998 
            'attributes' => {
5999 
              'hdlNetAttributes' => [
6000 
              ],
6001 
            },
6002 
            'hdlType' => 'std_logic',
6003 
            'width' => 1,
6004 
          },
6005 
          'constant1_op_net_x4' => {
6006 
            'attributes' => {
6007 
              'hdlNetAttributes' => [
6008 
              ],
6009 
            },
6010 
            'hdlType' => 'std_logic',
6011 
            'width' => 1,
6012 
          },
6013 
          'constant1_op_net_x5' => {
6014 
            'attributes' => {
6015 
              'hdlNetAttributes' => [
6016 
              ],
6017 
            },
6018 
            'hdlType' => 'std_logic',
6019 
            'width' => 1,
6020 
          },
6021 
          'constant1_op_net_x6' => {
6022 
            'attributes' => {
6023 
              'hdlNetAttributes' => [
6024 
              ],
6025 
            },
6026 
            'hdlType' => 'std_logic',
6027 
            'width' => 1,
6028 
          },
6029 
          'constant1_op_net_x7' => {
6030 
            'attributes' => {
6031 
              'hdlNetAttributes' => [
6032 
              ],
6033 
            },
6034 
            'hdlType' => 'std_logic',
6035 
            'width' => 1,
6036 
          },
6037 
          'constant1_op_net_x8' => {
6038 
            'attributes' => {
6039 
              'hdlNetAttributes' => [
6040 
              ],
6041 
            },
6042 
            'hdlType' => 'std_logic',
6043 
            'width' => 1,
6044 
          },
6045 
          'constant1_op_net_x9' => {
6046 
            'attributes' => {
6047 
              'hdlNetAttributes' => [
6048 
              ],
6049 
            },
6050 
            'hdlType' => 'std_logic',
6051 
            'width' => 1,
6052 
          },
6053 
          'constant5_op_net_x0' => {
6054 
            'attributes' => {
6055 
              'hdlNetAttributes' => [
6056 
              ],
6057 
            },
6058 
            'hdlType' => 'std_logic',
6059 
            'width' => 1,
6060 
          },
6061 
          'constant5_op_net_x1' => {
6062 
            'attributes' => {
6063 
              'hdlNetAttributes' => [
6064 
              ],
6065 
            },
6066 
            'hdlType' => 'std_logic',
6067 
            'width' => 1,
6068 
          },
6069 
          'constant5_op_net_x10' => {
6070 
            'attributes' => {
6071 
              'hdlNetAttributes' => [
6072 
              ],
6073 
            },
6074 
            'hdlType' => 'std_logic',
6075 
            'width' => 1,
6076 
          },
6077 
          'constant5_op_net_x11' => {
6078 
            'attributes' => {
6079 
              'hdlNetAttributes' => [
6080 
              ],
6081 
            },
6082 
            'hdlType' => 'std_logic',
6083 
            'width' => 1,
6084 
          },
6085 
          'constant5_op_net_x12' => {
6086 
            'attributes' => {
6087 
              'hdlNetAttributes' => [
6088 
              ],
6089 
            },
6090 
            'hdlType' => 'std_logic',
6091 
            'width' => 1,
6092 
          },
6093 
          'constant5_op_net_x13' => {
6094 
            'attributes' => {
6095 
              'hdlNetAttributes' => [
6096 
              ],
6097 
            },
6098 
            'hdlType' => 'std_logic',
6099 
            'width' => 1,
6100 
          },
6101 
          'constant5_op_net_x14' => {
6102 
            'attributes' => {
6103 
              'hdlNetAttributes' => [
6104 
              ],
6105 
            },
6106 
            'hdlType' => 'std_logic',
6107 
            'width' => 1,
6108 
          },
6109 
          'constant5_op_net_x15' => {
6110 
            'attributes' => {
6111 
              'hdlNetAttributes' => [
6112 
              ],
6113 
            },
6114 
            'hdlType' => 'std_logic',
6115 
            'width' => 1,
6116 
          },
6117 
          'constant5_op_net_x16' => {
6118 
            'attributes' => {
6119 
              'hdlNetAttributes' => [
6120 
              ],
6121 
            },
6122 
            'hdlType' => 'std_logic',
6123 
            'width' => 1,
6124 
          },
6125 
          'constant5_op_net_x17' => {
6126 
            'attributes' => {
6127 
              'hdlNetAttributes' => [
6128 
              ],
6129 
            },
6130 
            'hdlType' => 'std_logic',
6131 
            'width' => 1,
6132 
          },
6133 
          'constant5_op_net_x18' => {
6134 
            'attributes' => {
6135 
              'hdlNetAttributes' => [
6136 
              ],
6137 
            },
6138 
            'hdlType' => 'std_logic',
6139 
            'width' => 1,
6140 
          },
6141 
          'constant5_op_net_x19' => {
6142 
            'attributes' => {
6143 
              'hdlNetAttributes' => [
6144 
              ],
6145 
            },
6146 
            'hdlType' => 'std_logic',
6147 
            'width' => 1,
6148 
          },
6149 
          'constant5_op_net_x2' => {
6150 
            'attributes' => {
6151 
              'hdlNetAttributes' => [
6152 
              ],
6153 
            },
6154 
            'hdlType' => 'std_logic',
6155 
            'width' => 1,
6156 
          },
6157 
          'constant5_op_net_x3' => {
6158 
            'attributes' => {
6159 
              'hdlNetAttributes' => [
6160 
              ],
6161 
            },
6162 
            'hdlType' => 'std_logic',
6163 
            'width' => 1,
6164 
          },
6165 
          'constant5_op_net_x4' => {
6166 
            'attributes' => {
6167 
              'hdlNetAttributes' => [
6168 
              ],
6169 
            },
6170 
            'hdlType' => 'std_logic',
6171 
            'width' => 1,
6172 
          },
6173 
          'constant5_op_net_x5' => {
6174 
            'attributes' => {
6175 
              'hdlNetAttributes' => [
6176 
              ],
6177 
            },
6178 
            'hdlType' => 'std_logic',
6179 
            'width' => 1,
6180 
          },
6181 
          'constant5_op_net_x6' => {
6182 
            'attributes' => {
6183 
              'hdlNetAttributes' => [
6184 
              ],
6185 
            },
6186 
            'hdlType' => 'std_logic',
6187 
            'width' => 1,
6188 
          },
6189 
          'constant5_op_net_x7' => {
6190 
            'attributes' => {
6191 
              'hdlNetAttributes' => [
6192 
              ],
6193 
            },
6194 
            'hdlType' => 'std_logic',
6195 
            'width' => 1,
6196 
          },
6197 
          'constant5_op_net_x8' => {
6198 
            'attributes' => {
6199 
              'hdlNetAttributes' => [
6200 
              ],
6201 
            },
6202 
            'hdlType' => 'std_logic',
6203 
            'width' => 1,
6204 
          },
6205 
          'constant5_op_net_x9' => {
6206 
            'attributes' => {
6207 
              'hdlNetAttributes' => [
6208 
              ],
6209 
            },
6210 
            'hdlType' => 'std_logic',
6211 
            'width' => 1,
6212 
          },
6213 
          'debug_in_1i_net' => {
6214 
            'attributes' => {
6215 
              'hdlNetAttributes' => [
6216 
              ],
6217 
            },
6218 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6219 
            'width' => 32,
6220 
          },
6221 
          'debug_in_1i_net_x0' => {
6222 
            'attributes' => {
6223 
              'hdlNetAttributes' => [
6224 
              ],
6225 
            },
6226 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6227 
            'width' => 32,
6228 
          },
6229 
          'debug_in_2i_net' => {
6230 
            'attributes' => {
6231 
              'hdlNetAttributes' => [
6232 
              ],
6233 
            },
6234 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6235 
            'width' => 32,
6236 
          },
6237 
          'debug_in_2i_net_x0' => {
6238 
            'attributes' => {
6239 
              'hdlNetAttributes' => [
6240 
              ],
6241 
            },
6242 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6243 
            'width' => 32,
6244 
          },
6245 
          'debug_in_3i_net' => {
6246 
            'attributes' => {
6247 
              'hdlNetAttributes' => [
6248 
              ],
6249 
            },
6250 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6251 
            'width' => 32,
6252 
          },
6253 
          'debug_in_3i_net_x0' => {
6254 
            'attributes' => {
6255 
              'hdlNetAttributes' => [
6256 
              ],
6257 
            },
6258 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6259 
            'width' => 32,
6260 
          },
6261 
          'debug_in_4i_net' => {
6262 
            'attributes' => {
6263 
              'hdlNetAttributes' => [
6264 
              ],
6265 
            },
6266 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6267 
            'width' => 32,
6268 
          },
6269 
          'debug_in_4i_net_x0' => {
6270 
            'attributes' => {
6271 
              'hdlNetAttributes' => [
6272 
              ],
6273 
            },
6274 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6275 
            'width' => 32,
6276 
          },
6277 
          'dma_host2board_busy_net' => {
6278 
            'attributes' => {
6279 
              'hdlNetAttributes' => [
6280 
              ],
6281 
            },
6282 
            'hdlType' => 'std_logic',
6283 
            'width' => 1,
6284 
          },
6285 
          'dma_host2board_busy_net_x0' => {
6286 
            'attributes' => {
6287 
              'hdlNetAttributes' => [
6288 
              ],
6289 
            },
6290 
            'hdlType' => 'std_logic',
6291 
            'width' => 1,
6292 
          },
6293 
          'dma_host2board_done_net' => {
6294 
            'attributes' => {
6295 
              'hdlNetAttributes' => [
6296 
              ],
6297 
            },
6298 
            'hdlType' => 'std_logic',
6299 
            'width' => 1,
6300 
          },
6301 
          'dma_host2board_done_net_x0' => {
6302 
            'attributes' => {
6303 
              'hdlNetAttributes' => [
6304 
              ],
6305 
            },
6306 
            'hdlType' => 'std_logic',
6307 
            'width' => 1,
6308 
          },
6309 
          'from_register10_data_out_net' => {
6310 
            'attributes' => {
6311 
              'hdlNetAttributes' => [
6312 
              ],
6313 
            },
6314 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6315 
            'width' => 32,
6316 
          },
6317 
          'from_register10_data_out_net_x0' => {
6318 
            'attributes' => {
6319 
              'hdlNetAttributes' => [
6320 
              ],
6321 
            },
6322 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6323 
            'width' => 32,
6324 
          },
6325 
          'from_register11_data_out_net' => {
6326 
            'attributes' => {
6327 
              'hdlNetAttributes' => [
6328 
              ],
6329 
            },
6330 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6331 
            'width' => 32,
6332 
          },
6333 
          'from_register11_data_out_net_x0' => {
6334 
            'attributes' => {
6335 
              'hdlNetAttributes' => [
6336 
              ],
6337 
            },
6338 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6339 
            'width' => 32,
6340 
          },
6341 
          'from_register12_data_out_net' => {
6342 
            'attributes' => {
6343 
              'hdlNetAttributes' => [
6344 
              ],
6345 
            },
6346 
            'hdlType' => 'std_logic',
6347 
            'width' => 1,
6348 
          },
6349 
          'from_register12_data_out_net_x0' => {
6350 
            'attributes' => {
6351 
              'hdlNetAttributes' => [
6352 
              ],
6353 
            },
6354 
            'hdlType' => 'std_logic',
6355 
            'width' => 1,
6356 
          },
6357 
          'from_register13_data_out_net' => {
6358 
            'attributes' => {
6359 
              'hdlNetAttributes' => [
6360 
              ],
6361 
            },
6362 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6363 
            'width' => 32,
6364 
          },
6365 
          'from_register13_data_out_net_x0' => {
6366 
            'attributes' => {
6367 
              'hdlNetAttributes' => [
6368 
              ],
6369 
            },
6370 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6371 
            'width' => 32,
6372 
          },
6373 
          'from_register14_data_out_net' => {
6374 
            'attributes' => {
6375 
              'hdlNetAttributes' => [
6376 
              ],
6377 
            },
6378 
            'hdlType' => 'std_logic',
6379 
            'width' => 1,
6380 
          },
6381 
          'from_register14_data_out_net_x0' => {
6382 
            'attributes' => {
6383 
              'hdlNetAttributes' => [
6384 
              ],
6385 
            },
6386 
            'hdlType' => 'std_logic',
6387 
            'width' => 1,
6388 
          },
6389 
          'from_register15_data_out_net' => {
6390 
            'attributes' => {
6391 
              'hdlNetAttributes' => [
6392 
              ],
6393 
            },
6394 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6395 
            'width' => 32,
6396 
          },
6397 
          'from_register15_data_out_net_x0' => {
6398 
            'attributes' => {
6399 
              'hdlNetAttributes' => [
6400 
              ],
6401 
            },
6402 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6403 
            'width' => 32,
6404 
          },
6405 
          'from_register16_data_out_net' => {
6406 
            'attributes' => {
6407 
              'hdlNetAttributes' => [
6408 
              ],
6409 
            },
6410 
            'hdlType' => 'std_logic',
6411 
            'width' => 1,
6412 
          },
6413 
          'from_register16_data_out_net_x0' => {
6414 
            'attributes' => {
6415 
              'hdlNetAttributes' => [
6416 
              ],
6417 
            },
6418 
            'hdlType' => 'std_logic',
6419 
            'width' => 1,
6420 
          },
6421 
          'from_register17_data_out_net' => {
6422 
            'attributes' => {
6423 
              'hdlNetAttributes' => [
6424 
              ],
6425 
            },
6426 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6427 
            'width' => 32,
6428 
          },
6429 
          'from_register17_data_out_net_x0' => {
6430 
            'attributes' => {
6431 
              'hdlNetAttributes' => [
6432 
              ],
6433 
            },
6434 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6435 
            'width' => 32,
6436 
          },
6437 
          'from_register18_data_out_net' => {
6438 
            'attributes' => {
6439 
              'hdlNetAttributes' => [
6440 
              ],
6441 
            },
6442 
            'hdlType' => 'std_logic',
6443 
            'width' => 1,
6444 
          },
6445 
          'from_register18_data_out_net_x0' => {
6446 
            'attributes' => {
6447 
              'hdlNetAttributes' => [
6448 
              ],
6449 
            },
6450 
            'hdlType' => 'std_logic',
6451 
            'width' => 1,
6452 
          },
6453 
          'from_register19_data_out_net' => {
6454 
            'attributes' => {
6455 
              'hdlNetAttributes' => [
6456 
              ],
6457 
            },
6458 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6459 
            'width' => 32,
6460 
          },
6461 
          'from_register19_data_out_net_x0' => {
6462 
            'attributes' => {
6463 
              'hdlNetAttributes' => [
6464 
              ],
6465 
            },
6466 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6467 
            'width' => 32,
6468 
          },
6469 
          'from_register1_data_out_net' => {
6470 
            'attributes' => {
6471 
              'hdlNetAttributes' => [
6472 
              ],
6473 
            },
6474 
            'hdlType' => 'std_logic',
6475 
            'width' => 1,
6476 
          },
6477 
          'from_register1_data_out_net_x0' => {
6478 
            'attributes' => {
6479 
              'hdlNetAttributes' => [
6480 
              ],
6481 
            },
6482 
            'hdlType' => 'std_logic',
6483 
            'width' => 1,
6484 
          },
6485 
          'from_register20_data_out_net' => {
6486 
            'attributes' => {
6487 
              'hdlNetAttributes' => [
6488 
              ],
6489 
            },
6490 
            'hdlType' => 'std_logic',
6491 
            'width' => 1,
6492 
          },
6493 
          'from_register20_data_out_net_x0' => {
6494 
            'attributes' => {
6495 
              'hdlNetAttributes' => [
6496 
              ],
6497 
            },
6498 
            'hdlType' => 'std_logic',
6499 
            'width' => 1,
6500 
          },
6501 
          'from_register21_data_out_net' => {
6502 
            'attributes' => {
6503 
              'hdlNetAttributes' => [
6504 
              ],
6505 
            },
6506 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6507 
            'width' => 32,
6508 
          },
6509 
          'from_register21_data_out_net_x0' => {
6510 
            'attributes' => {
6511 
              'hdlNetAttributes' => [
6512 
              ],
6513 
            },
6514 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6515 
            'width' => 32,
6516 
          },
6517 
          'from_register22_data_out_net' => {
6518 
            'attributes' => {
6519 
              'hdlNetAttributes' => [
6520 
              ],
6521 
            },
6522 
            'hdlType' => 'std_logic',
6523 
            'width' => 1,
6524 
          },
6525 
          'from_register22_data_out_net_x0' => {
6526 
            'attributes' => {
6527 
              'hdlNetAttributes' => [
6528 
              ],
6529 
            },
6530 
            'hdlType' => 'std_logic',
6531 
            'width' => 1,
6532 
          },
6533 
          'from_register23_data_out_net' => {
6534 
            'attributes' => {
6535 
              'hdlNetAttributes' => [
6536 
              ],
6537 
            },
6538 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6539 
            'width' => 32,
6540 
          },
6541 
          'from_register23_data_out_net_x0' => {
6542 
            'attributes' => {
6543 
              'hdlNetAttributes' => [
6544 
              ],
6545 
            },
6546 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6547 
            'width' => 32,
6548 
          },
6549 
          'from_register24_data_out_net' => {
6550 
            'attributes' => {
6551 
              'hdlNetAttributes' => [
6552 
              ],
6553 
            },
6554 
            'hdlType' => 'std_logic',
6555 
            'width' => 1,
6556 
          },
6557 
          'from_register24_data_out_net_x0' => {
6558 
            'attributes' => {
6559 
              'hdlNetAttributes' => [
6560 
              ],
6561 
            },
6562 
            'hdlType' => 'std_logic',
6563 
            'width' => 1,
6564 
          },
6565 
          'from_register25_data_out_net' => {
6566 
            'attributes' => {
6567 
              'hdlNetAttributes' => [
6568 
              ],
6569 
            },
6570 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6571 
            'width' => 32,
6572 
          },
6573 
          'from_register25_data_out_net_x0' => {
6574 
            'attributes' => {
6575 
              'hdlNetAttributes' => [
6576 
              ],
6577 
            },
6578 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6579 
            'width' => 32,
6580 
          },
6581 
          'from_register26_data_out_net' => {
6582 
            'attributes' => {
6583 
              'hdlNetAttributes' => [
6584 
              ],
6585 
            },
6586 
            'hdlType' => 'std_logic',
6587 
            'width' => 1,
6588 
          },
6589 
          'from_register26_data_out_net_x0' => {
6590 
            'attributes' => {
6591 
              'hdlNetAttributes' => [
6592 
              ],
6593 
            },
6594 
            'hdlType' => 'std_logic',
6595 
            'width' => 1,
6596 
          },
6597 
          'from_register27_data_out_net' => {
6598 
            'attributes' => {
6599 
              'hdlNetAttributes' => [
6600 
              ],
6601 
            },
6602 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6603 
            'width' => 32,
6604 
          },
6605 
          'from_register27_data_out_net_x0' => {
6606 
            'attributes' => {
6607 
              'hdlNetAttributes' => [
6608 
              ],
6609 
            },
6610 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6611 
            'width' => 32,
6612 
          },
6613 
          'from_register28_data_out_net' => {
6614 
            'attributes' => {
6615 
              'hdlNetAttributes' => [
6616 
              ],
6617 
            },
6618 
            'hdlType' => 'std_logic',
6619 
            'width' => 1,
6620 
          },
6621 
          'from_register28_data_out_net_x0' => {
6622 
            'attributes' => {
6623 
              'hdlNetAttributes' => [
6624 
              ],
6625 
            },
6626 
            'hdlType' => 'std_logic',
6627 
            'width' => 1,
6628 
          },
6629 
          'from_register2_data_out_net' => {
6630 
            'attributes' => {
6631 
              'hdlNetAttributes' => [
6632 
              ],
6633 
            },
6634 
            'hdlType' => 'std_logic',
6635 
            'width' => 1,
6636 
          },
6637 
          'from_register2_data_out_net_x0' => {
6638 
            'attributes' => {
6639 
              'hdlNetAttributes' => [
6640 
              ],
6641 
            },
6642 
            'hdlType' => 'std_logic',
6643 
            'width' => 1,
6644 
          },
6645 
          'from_register3_data_out_net' => {
6646 
            'attributes' => {
6647 
              'hdlNetAttributes' => [
6648 
              ],
6649 
            },
6650 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6651 
            'width' => 32,
6652 
          },
6653 
          'from_register3_data_out_net_x0' => {
6654 
            'attributes' => {
6655 
              'hdlNetAttributes' => [
6656 
              ],
6657 
            },
6658 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6659 
            'width' => 32,
6660 
          },
6661 
          'from_register4_data_out_net' => {
6662 
            'attributes' => {
6663 
              'hdlNetAttributes' => [
6664 
              ],
6665 
            },
6666 
            'hdlType' => 'std_logic',
6667 
            'width' => 1,
6668 
          },
6669 
          'from_register4_data_out_net_x0' => {
6670 
            'attributes' => {
6671 
              'hdlNetAttributes' => [
6672 
              ],
6673 
            },
6674 
            'hdlType' => 'std_logic',
6675 
            'width' => 1,
6676 
          },
6677 
          'from_register5_data_out_net' => {
6678 
            'attributes' => {
6679 
              'hdlNetAttributes' => [
6680 
              ],
6681 
            },
6682 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6683 
            'width' => 32,
6684 
          },
6685 
          'from_register5_data_out_net_x0' => {
6686 
            'attributes' => {
6687 
              'hdlNetAttributes' => [
6688 
              ],
6689 
            },
6690 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6691 
            'width' => 32,
6692 
          },
6693 
          'from_register6_data_out_net' => {
6694 
            'attributes' => {
6695 
              'hdlNetAttributes' => [
6696 
              ],
6697 
            },
6698 
            'hdlType' => 'std_logic',
6699 
            'width' => 1,
6700 
          },
6701 
          'from_register6_data_out_net_x0' => {
6702 
            'attributes' => {
6703 
              'hdlNetAttributes' => [
6704 
              ],
6705 
            },
6706 
            'hdlType' => 'std_logic',
6707 
            'width' => 1,
6708 
          },
6709 
          'from_register7_data_out_net' => {
6710 
            'attributes' => {
6711 
              'hdlNetAttributes' => [
6712 
              ],
6713 
            },
6714 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6715 
            'width' => 32,
6716 
          },
6717 
          'from_register7_data_out_net_x0' => {
6718 
            'attributes' => {
6719 
              'hdlNetAttributes' => [
6720 
              ],
6721 
            },
6722 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6723 
            'width' => 32,
6724 
          },
6725 
          'from_register8_data_out_net' => {
6726 
            'attributes' => {
6727 
              'hdlNetAttributes' => [
6728 
              ],
6729 
            },
6730 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6731 
            'width' => 32,
6732 
          },
6733 
          'from_register8_data_out_net_x0' => {
6734 
            'attributes' => {
6735 
              'hdlNetAttributes' => [
6736 
              ],
6737 
            },
6738 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6739 
            'width' => 32,
6740 
          },
6741 
          'from_register9_data_out_net' => {
6742 
            'attributes' => {
6743 
              'hdlNetAttributes' => [
6744 
              ],
6745 
            },
6746 
            'hdlType' => 'std_logic',
6747 
            'width' => 1,
6748 
          },
6749 
          'from_register9_data_out_net_x0' => {
6750 
            'attributes' => {
6751 
              'hdlNetAttributes' => [
6752 
              ],
6753 
            },
6754 
            'hdlType' => 'std_logic',
6755 
            'width' => 1,
6756 
          },
6757 
          'persistentdff_inst_q' => {
6758 
            'attributes' => {
6759 
              'hdlNetAttributes' => [
6760 
                [
6761 
                  'syn_keep',
6762 
                  'boolean',
6763 
                  'true',
6764 
                ],
6765 
                [
6766 
                  'keep',
6767 
                  'boolean',
6768 
                  'true',
6769 
                ],
6770 
                [
6771 
                  'preserve_signal',
6772 
                  'boolean',
6773 
                  'true',
6774 
                ],
6775 
              ],
6776 
            },
6777 
            'hdlType' => 'std_logic',
6778 
            'width' => 1,
6779 
          },
6780 
          'reg01_td_net' => {
6781 
            'attributes' => {
6782 
              'hdlNetAttributes' => [
6783 
              ],
6784 
            },
6785 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6786 
            'width' => 32,
6787 
          },
6788 
          'reg01_td_net_x0' => {
6789 
            'attributes' => {
6790 
              'hdlNetAttributes' => [
6791 
              ],
6792 
            },
6793 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6794 
            'width' => 32,
6795 
          },
6796 
          'reg01_tv_net' => {
6797 
            'attributes' => {
6798 
              'hdlNetAttributes' => [
6799 
              ],
6800 
            },
6801 
            'hdlType' => 'std_logic',
6802 
            'width' => 1,
6803 
          },
6804 
          'reg01_tv_net_x0' => {
6805 
            'attributes' => {
6806 
              'hdlNetAttributes' => [
6807 
              ],
6808 
            },
6809 
            'hdlType' => 'std_logic',
6810 
            'width' => 1,
6811 
          },
6812 
          'reg02_td_net' => {
6813 
            'attributes' => {
6814 
              'hdlNetAttributes' => [
6815 
              ],
6816 
            },
6817 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6818 
            'width' => 32,
6819 
          },
6820 
          'reg02_td_net_x0' => {
6821 
            'attributes' => {
6822 
              'hdlNetAttributes' => [
6823 
              ],
6824 
            },
6825 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6826 
            'width' => 32,
6827 
          },
6828 
          'reg02_tv_net' => {
6829 
            'attributes' => {
6830 
              'hdlNetAttributes' => [
6831 
              ],
6832 
            },
6833 
            'hdlType' => 'std_logic',
6834 
            'width' => 1,
6835 
          },
6836 
          'reg02_tv_net_x0' => {
6837 
            'attributes' => {
6838 
              'hdlNetAttributes' => [
6839 
              ],
6840 
            },
6841 
            'hdlType' => 'std_logic',
6842 
            'width' => 1,
6843 
          },
6844 
          'reg03_td_net' => {
6845 
            'attributes' => {
6846 
              'hdlNetAttributes' => [
6847 
              ],
6848 
            },
6849 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6850 
            'width' => 32,
6851 
          },
6852 
          'reg03_td_net_x0' => {
6853 
            'attributes' => {
6854 
              'hdlNetAttributes' => [
6855 
              ],
6856 
            },
6857 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6858 
            'width' => 32,
6859 
          },
6860 
          'reg03_tv_net' => {
6861 
            'attributes' => {
6862 
              'hdlNetAttributes' => [
6863 
              ],
6864 
            },
6865 
            'hdlType' => 'std_logic',
6866 
            'width' => 1,
6867 
          },
6868 
          'reg03_tv_net_x0' => {
6869 
            'attributes' => {
6870 
              'hdlNetAttributes' => [
6871 
              ],
6872 
            },
6873 
            'hdlType' => 'std_logic',
6874 
            'width' => 1,
6875 
          },
6876 
          'reg04_td_net' => {
6877 
            'attributes' => {
6878 
              'hdlNetAttributes' => [
6879 
              ],
6880 
            },
6881 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6882 
            'width' => 32,
6883 
          },
6884 
          'reg04_td_net_x0' => {
6885 
            'attributes' => {
6886 
              'hdlNetAttributes' => [
6887 
              ],
6888 
            },
6889 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6890 
            'width' => 32,
6891 
          },
6892 
          'reg04_tv_net' => {
6893 
            'attributes' => {
6894 
              'hdlNetAttributes' => [
6895 
              ],
6896 
            },
6897 
            'hdlType' => 'std_logic',
6898 
            'width' => 1,
6899 
          },
6900 
          'reg04_tv_net_x0' => {
6901 
            'attributes' => {
6902 
              'hdlNetAttributes' => [
6903 
              ],
6904 
            },
6905 
            'hdlType' => 'std_logic',
6906 
            'width' => 1,
6907 
          },
6908 
          'reg05_td_net' => {
6909 
            'attributes' => {
6910 
              'hdlNetAttributes' => [
6911 
              ],
6912 
            },
6913 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6914 
            'width' => 32,
6915 
          },
6916 
          'reg05_td_net_x0' => {
6917 
            'attributes' => {
6918 
              'hdlNetAttributes' => [
6919 
              ],
6920 
            },
6921 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6922 
            'width' => 32,
6923 
          },
6924 
          'reg05_tv_net' => {
6925 
            'attributes' => {
6926 
              'hdlNetAttributes' => [
6927 
              ],
6928 
            },
6929 
            'hdlType' => 'std_logic',
6930 
            'width' => 1,
6931 
          },
6932 
          'reg05_tv_net_x0' => {
6933 
            'attributes' => {
6934 
              'hdlNetAttributes' => [
6935 
              ],
6936 
            },
6937 
            'hdlType' => 'std_logic',
6938 
            'width' => 1,
6939 
          },
6940 
          'reg06_td_net' => {
6941 
            'attributes' => {
6942 
              'hdlNetAttributes' => [
6943 
              ],
6944 
            },
6945 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6946 
            'width' => 32,
6947 
          },
6948 
          'reg06_td_net_x0' => {
6949 
            'attributes' => {
6950 
              'hdlNetAttributes' => [
6951 
              ],
6952 
            },
6953 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6954 
            'width' => 32,
6955 
          },
6956 
          'reg06_tv_net' => {
6957 
            'attributes' => {
6958 
              'hdlNetAttributes' => [
6959 
              ],
6960 
            },
6961 
            'hdlType' => 'std_logic',
6962 
            'width' => 1,
6963 
          },
6964 
          'reg06_tv_net_x0' => {
6965 
            'attributes' => {
6966 
              'hdlNetAttributes' => [
6967 
              ],
6968 
            },
6969 
            'hdlType' => 'std_logic',
6970 
            'width' => 1,
6971 
          },
6972 
          'reg07_td_net' => {
6973 
            'attributes' => {
6974 
              'hdlNetAttributes' => [
6975 
              ],
6976 
            },
6977 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6978 
            'width' => 32,
6979 
          },
6980 
          'reg07_td_net_x0' => {
6981 
            'attributes' => {
6982 
              'hdlNetAttributes' => [
6983 
              ],
6984 
            },
6985 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6986 
            'width' => 32,
6987 
          },
6988 
          'reg07_tv_net' => {
6989 
            'attributes' => {
6990 
              'hdlNetAttributes' => [
6991 
              ],
6992 
            },
6993 
            'hdlType' => 'std_logic',
6994 
            'width' => 1,
6995 
          },
6996 
          'reg07_tv_net_x0' => {
6997 
            'attributes' => {
6998 
              'hdlNetAttributes' => [
6999 
              ],
7000 
            },
7001 
            'hdlType' => 'std_logic',
7002 
            'width' => 1,
7003 
          },
7004 
          'reg08_td_net' => {
7005 
            'attributes' => {
7006 
              'hdlNetAttributes' => [
7007 
              ],
7008 
            },
7009 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7010 
            'width' => 32,
7011 
          },
7012 
          'reg08_td_net_x0' => {
7013 
            'attributes' => {
7014 
              'hdlNetAttributes' => [
7015 
              ],
7016 
            },
7017 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7018 
            'width' => 32,
7019 
          },
7020 
          'reg08_tv_net' => {
7021 
            'attributes' => {
7022 
              'hdlNetAttributes' => [
7023 
              ],
7024 
            },
7025 
            'hdlType' => 'std_logic',
7026 
            'width' => 1,
7027 
          },
7028 
          'reg08_tv_net_x0' => {
7029 
            'attributes' => {
7030 
              'hdlNetAttributes' => [
7031 
              ],
7032 
            },
7033 
            'hdlType' => 'std_logic',
7034 
            'width' => 1,
7035 
          },
7036 
          'reg09_td_net' => {
7037 
            'attributes' => {
7038 
              'hdlNetAttributes' => [
7039 
              ],
7040 
            },
7041 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7042 
            'width' => 32,
7043 
          },
7044 
          'reg09_td_net_x0' => {
7045 
            'attributes' => {
7046 
              'hdlNetAttributes' => [
7047 
              ],
7048 
            },
7049 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7050 
            'width' => 32,
7051 
          },
7052 
          'reg09_tv_net' => {
7053 
            'attributes' => {
7054 
              'hdlNetAttributes' => [
7055 
              ],
7056 
            },
7057 
            'hdlType' => 'std_logic',
7058 
            'width' => 1,
7059 
          },
7060 
          'reg09_tv_net_x0' => {
7061 
            'attributes' => {
7062 
              'hdlNetAttributes' => [
7063 
              ],
7064 
            },
7065 
            'hdlType' => 'std_logic',
7066 
            'width' => 1,
7067 
          },
7068 
          'reg10_td_net' => {
7069 
            'attributes' => {
7070 
              'hdlNetAttributes' => [
7071 
              ],
7072 
            },
7073 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7074 
            'width' => 32,
7075 
          },
7076 
          'reg10_td_net_x0' => {
7077 
            'attributes' => {
7078 
              'hdlNetAttributes' => [
7079 
              ],
7080 
            },
7081 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7082 
            'width' => 32,
7083 
          },
7084 
          'reg10_tv_net' => {
7085 
            'attributes' => {
7086 
              'hdlNetAttributes' => [
7087 
              ],
7088 
            },
7089 
            'hdlType' => 'std_logic',
7090 
            'width' => 1,
7091 
          },
7092 
          'reg10_tv_net_x0' => {
7093 
            'attributes' => {
7094 
              'hdlNetAttributes' => [
7095 
              ],
7096 
            },
7097 
            'hdlType' => 'std_logic',
7098 
            'width' => 1,
7099 
          },
7100 
          'reg11_td_net' => {
7101 
            'attributes' => {
7102 
              'hdlNetAttributes' => [
7103 
              ],
7104 
            },
7105 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7106 
            'width' => 32,
7107 
          },
7108 
          'reg11_td_net_x0' => {
7109 
            'attributes' => {
7110 
              'hdlNetAttributes' => [
7111 
              ],
7112 
            },
7113 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7114 
            'width' => 32,
7115 
          },
7116 
          'reg11_tv_net' => {
7117 
            'attributes' => {
7118 
              'hdlNetAttributes' => [
7119 
              ],
7120 
            },
7121 
            'hdlType' => 'std_logic',
7122 
            'width' => 1,
7123 
          },
7124 
          'reg11_tv_net_x0' => {
7125 
            'attributes' => {
7126 
              'hdlNetAttributes' => [
7127 
              ],
7128 
            },
7129 
            'hdlType' => 'std_logic',
7130 
            'width' => 1,
7131 
          },
7132 
          'reg12_td_net' => {
7133 
            'attributes' => {
7134 
              'hdlNetAttributes' => [
7135 
              ],
7136 
            },
7137 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7138 
            'width' => 32,
7139 
          },
7140 
          'reg12_td_net_x0' => {
7141 
            'attributes' => {
7142 
              'hdlNetAttributes' => [
7143 
              ],
7144 
            },
7145 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7146 
            'width' => 32,
7147 
          },
7148 
          'reg12_tv_net' => {
7149 
            'attributes' => {
7150 
              'hdlNetAttributes' => [
7151 
              ],
7152 
            },
7153 
            'hdlType' => 'std_logic',
7154 
            'width' => 1,
7155 
          },
7156 
          'reg12_tv_net_x0' => {
7157 
            'attributes' => {
7158 
              'hdlNetAttributes' => [
7159 
              ],
7160 
            },
7161 
            'hdlType' => 'std_logic',
7162 
            'width' => 1,
7163 
          },
7164 
          'reg13_td_net' => {
7165 
            'attributes' => {
7166 
              'hdlNetAttributes' => [
7167 
              ],
7168 
            },
7169 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7170 
            'width' => 32,
7171 
          },
7172 
          'reg13_td_net_x0' => {
7173 
            'attributes' => {
7174 
              'hdlNetAttributes' => [
7175 
              ],
7176 
            },
7177 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7178 
            'width' => 32,
7179 
          },
7180 
          'reg13_tv_net' => {
7181 
            'attributes' => {
7182 
              'hdlNetAttributes' => [
7183 
              ],
7184 
            },
7185 
            'hdlType' => 'std_logic',
7186 
            'width' => 1,
7187 
          },
7188 
          'reg13_tv_net_x0' => {
7189 
            'attributes' => {
7190 
              'hdlNetAttributes' => [
7191 
              ],
7192 
            },
7193 
            'hdlType' => 'std_logic',
7194 
            'width' => 1,
7195 
          },
7196 
          'reg14_td_net' => {
7197 
            'attributes' => {
7198 
              'hdlNetAttributes' => [
7199 
              ],
7200 
            },
7201 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7202 
            'width' => 32,
7203 
          },
7204 
          'reg14_td_net_x0' => {
7205 
            'attributes' => {
7206 
              'hdlNetAttributes' => [
7207 
              ],
7208 
            },
7209 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7210 
            'width' => 32,
7211 
          },
7212 
          'reg14_tv_net' => {
7213 
            'attributes' => {
7214 
              'hdlNetAttributes' => [
7215 
              ],
7216 
            },
7217 
            'hdlType' => 'std_logic',
7218 
            'width' => 1,
7219 
          },
7220 
          'reg14_tv_net_x0' => {
7221 
            'attributes' => {
7222 
              'hdlNetAttributes' => [
7223 
              ],
7224 
            },
7225 
            'hdlType' => 'std_logic',
7226 
            'width' => 1,
7227 
          },
7228 
          'to_register10_dout_net' => {
7229 
            'attributes' => {
7230 
              'hdlNetAttributes' => [
7231 
              ],
7232 
            },
7233 
            'hdlType' => 'std_logic',
7234 
            'width' => 1,
7235 
          },
7236 
          'to_register11_dout_net' => {
7237 
            'attributes' => {
7238 
              'hdlNetAttributes' => [
7239 
              ],
7240 
            },
7241 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7242 
            'width' => 32,
7243 
          },
7244 
          'to_register12_dout_net' => {
7245 
            'attributes' => {
7246 
              'hdlNetAttributes' => [
7247 
              ],
7248 
            },
7249 
            'hdlType' => 'std_logic',
7250 
            'width' => 1,
7251 
          },
7252 
          'to_register13_dout_net' => {
7253 
            'attributes' => {
7254 
              'hdlNetAttributes' => [
7255 
              ],
7256 
            },
7257 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7258 
            'width' => 32,
7259 
          },
7260 
          'to_register14_dout_net' => {
7261 
            'attributes' => {
7262 
              'hdlNetAttributes' => [
7263 
              ],
7264 
            },
7265 
            'hdlType' => 'std_logic',
7266 
            'width' => 1,
7267 
          },
7268 
          'to_register15_dout_net' => {
7269 
            'attributes' => {
7270 
              'hdlNetAttributes' => [
7271 
              ],
7272 
            },
7273 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7274 
            'width' => 32,
7275 
          },
7276 
          'to_register16_dout_net' => {
7277 
            'attributes' => {
7278 
              'hdlNetAttributes' => [
7279 
              ],
7280 
            },
7281 
            'hdlType' => 'std_logic',
7282 
            'width' => 1,
7283 
          },
7284 
          'to_register17_dout_net' => {
7285 
            'attributes' => {
7286 
              'hdlNetAttributes' => [
7287 
              ],
7288 
            },
7289 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7290 
            'width' => 32,
7291 
          },
7292 
          'to_register18_dout_net' => {
7293 
            'attributes' => {
7294 
              'hdlNetAttributes' => [
7295 
              ],
7296 
            },
7297 
            'hdlType' => 'std_logic',
7298 
            'width' => 1,
7299 
          },
7300 
          'to_register19_dout_net' => {
7301 
            'attributes' => {
7302 
              'hdlNetAttributes' => [
7303 
              ],
7304 
            },
7305 
            'hdlType' => 'std_logic',
7306 
            'width' => 1,
7307 
          },
7308 
          'to_register1_dout_net' => {
7309 
            'attributes' => {
7310 
              'hdlNetAttributes' => [
7311 
              ],
7312 
            },
7313 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7314 
            'width' => 32,
7315 
          },
7316 
          'to_register20_dout_net' => {
7317 
            'attributes' => {
7318 
              'hdlNetAttributes' => [
7319 
              ],
7320 
            },
7321 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7322 
            'width' => 32,
7323 
          },
7324 
          'to_register21_dout_net' => {
7325 
            'attributes' => {
7326 
              'hdlNetAttributes' => [
7327 
              ],
7328 
            },
7329 
            'hdlType' => 'std_logic',
7330 
            'width' => 1,
7331 
          },
7332 
          'to_register22_dout_net' => {
7333 
            'attributes' => {
7334 
              'hdlNetAttributes' => [
7335 
              ],
7336 
            },
7337 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7338 
            'width' => 32,
7339 
          },
7340 
          'to_register23_dout_net' => {
7341 
            'attributes' => {
7342 
              'hdlNetAttributes' => [
7343 
              ],
7344 
            },
7345 
            'hdlType' => 'std_logic',
7346 
            'width' => 1,
7347 
          },
7348 
          'to_register24_dout_net' => {
7349 
            'attributes' => {
7350 
              'hdlNetAttributes' => [
7351 
              ],
7352 
            },
7353 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7354 
            'width' => 32,
7355 
          },
7356 
          'to_register25_dout_net' => {
7357 
            'attributes' => {
7358 
              'hdlNetAttributes' => [
7359 
              ],
7360 
            },
7361 
            'hdlType' => 'std_logic',
7362 
            'width' => 1,
7363 
          },
7364 
          'to_register26_dout_net' => {
7365 
            'attributes' => {
7366 
              'hdlNetAttributes' => [
7367 
              ],
7368 
            },
7369 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7370 
            'width' => 32,
7371 
          },
7372 
          'to_register27_dout_net' => {
7373 
            'attributes' => {
7374 
              'hdlNetAttributes' => [
7375 
              ],
7376 
            },
7377 
            'hdlType' => 'std_logic',
7378 
            'width' => 1,
7379 
          },
7380 
          'to_register28_dout_net' => {
7381 
            'attributes' => {
7382 
              'hdlNetAttributes' => [
7383 
              ],
7384 
            },
7385 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7386 
            'width' => 32,
7387 
          },
7388 
          'to_register29_dout_net' => {
7389 
            'attributes' => {
7390 
              'hdlNetAttributes' => [
7391 
              ],
7392 
            },
7393 
            'hdlType' => 'std_logic',
7394 
            'width' => 1,
7395 
          },
7396 
          'to_register2_dout_net' => {
7397 
            'attributes' => {
7398 
              'hdlNetAttributes' => [
7399 
              ],
7400 
            },
7401 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7402 
            'width' => 32,
7403 
          },
7404 
          'to_register30_dout_net' => {
7405 
            'attributes' => {
7406 
              'hdlNetAttributes' => [
7407 
              ],
7408 
            },
7409 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7410 
            'width' => 32,
7411 
          },
7412 
          'to_register31_dout_net' => {
7413 
            'attributes' => {
7414 
              'hdlNetAttributes' => [
7415 
              ],
7416 
            },
7417 
            'hdlType' => 'std_logic',
7418 
            'width' => 1,
7419 
          },
7420 
          'to_register32_dout_net' => {
7421 
            'attributes' => {
7422 
              'hdlNetAttributes' => [
7423 
              ],
7424 
            },
7425 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7426 
            'width' => 32,
7427 
          },
7428 
          'to_register33_dout_net' => {
7429 
            'attributes' => {
7430 
              'hdlNetAttributes' => [
7431 
              ],
7432 
            },
7433 
            'hdlType' => 'std_logic',
7434 
            'width' => 1,
7435 
          },
7436 
          'to_register34_dout_net' => {
7437 
            'attributes' => {
7438 
              'hdlNetAttributes' => [
7439 
              ],
7440 
            },
7441 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7442 
            'width' => 32,
7443 
          },
7444 
          'to_register3_dout_net' => {
7445 
            'attributes' => {
7446 
              'hdlNetAttributes' => [
7447 
              ],
7448 
            },
7449 
            'hdlType' => 'std_logic',
7450 
            'width' => 1,
7451 
          },
7452 
          'to_register4_dout_net' => {
7453 
            'attributes' => {
7454 
              'hdlNetAttributes' => [
7455 
              ],
7456 
            },
7457 
            'hdlType' => 'std_logic',
7458 
            'width' => 1,
7459 
          },
7460 
          'to_register5_dout_net' => {
7461 
            'attributes' => {
7462 
              'hdlNetAttributes' => [
7463 
              ],
7464 
            },
7465 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7466 
            'width' => 32,
7467 
          },
7468 
          'to_register6_dout_net' => {
7469 
            'attributes' => {
7470 
              'hdlNetAttributes' => [
7471 
              ],
7472 
            },
7473 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7474 
            'width' => 32,
7475 
          },
7476 
          'to_register7_dout_net' => {
7477 
            'attributes' => {
7478 
              'hdlNetAttributes' => [
7479 
              ],
7480 
            },
7481 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7482 
            'width' => 32,
7483 
          },
7484 
          'to_register8_dout_net' => {
7485 
            'attributes' => {
7486 
              'hdlNetAttributes' => [
7487 
              ],
7488 
            },
7489 
            'hdlType' => 'std_logic',
7490 
            'width' => 1,
7491 
          },
7492 
          'to_register9_dout_net' => {
7493 
            'attributes' => {
7494 
              'hdlNetAttributes' => [
7495 
              ],
7496 
            },
7497 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7498 
            'width' => 32,
7499 
          },
7500 
        },
7501 
        'ports' => {
7502 
          'ce' => {
7503 
            'attributes' => {
7504 
              'defaultHdlValue' => '\'1\'',
7505 
              'domain' => 'default',
7506 
              'group' => 4,
7507 
              'isCe' => 1,
7508 
              'period' => 1,
7509 
            },
7510 
            'direction' => 'in',
7511 
            'hdlType' => 'std_logic',
7512 
            'width' => 1,
7513 
          },
7514 
          'clk' => {
7515 
            'attributes' => {
7516 
              'domain' => 'default',
7517 
              'group' => 4,
7518 
              'isClk' => 1,
7519 
              'period' => 1,
7520 
              'type' => 'logic',
7521 
            },
7522 
            'direction' => 'in',
7523 
            'hdlType' => 'std_logic',
7524 
            'width' => 1,
7525 
          },
7526 
          'debug_in_1i' => {
7527 
            'attributes' => {
7528 
              'bin_pt' => 0,
7529 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
7530 
              'is_floating_block' => 1,
7531 
              'is_gateway_port' => 1,
7532 
              'must_be_hdl_vector' => 1,
7533 
              'period' => 1,
7534 
              'port_id' => 0,
7535 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
7536 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
7537 
              'timingConstraint' => 'none',
7538 
              'type' => 'UFix_32_0',
7539 
            },
7540 
            'direction' => 'in',
7541 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7542 
            'width' => 32,
7543 
          },
7544 
          'debug_in_2i' => {
7545 
            'attributes' => {
7546 
              'bin_pt' => 0,
7547 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
7548 
              'is_floating_block' => 1,
7549 
              'is_gateway_port' => 1,
7550 
              'must_be_hdl_vector' => 1,
7551 
              'period' => 1,
7552 
              'port_id' => 0,
7553 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
7554 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
7555 
              'timingConstraint' => 'none',
7556 
              'type' => 'UFix_32_0',
7557 
            },
7558 
            'direction' => 'in',
7559 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7560 
            'width' => 32,
7561 
          },
7562 
          'debug_in_3i' => {
7563 
            'attributes' => {
7564 
              'bin_pt' => 0,
7565 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
7566 
              'is_floating_block' => 1,
7567 
              'is_gateway_port' => 1,
7568 
              'must_be_hdl_vector' => 1,
7569 
              'period' => 1,
7570 
              'port_id' => 0,
7571 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
7572 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
7573 
              'timingConstraint' => 'none',
7574 
              'type' => 'UFix_32_0',
7575 
            },
7576 
            'direction' => 'in',
7577 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7578 
            'width' => 32,
7579 
          },
7580 
          'debug_in_4i' => {
7581 
            'attributes' => {
7582 
              'bin_pt' => 0,
7583 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
7584 
              'is_floating_block' => 1,
7585 
              'is_gateway_port' => 1,
7586 
              'must_be_hdl_vector' => 1,
7587 
              'period' => 1,
7588 
              'port_id' => 0,
7589 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
7590 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
7591 
              'timingConstraint' => 'none',
7592 
              'type' => 'UFix_32_0',
7593 
            },
7594 
            'direction' => 'in',
7595 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7596 
            'width' => 32,
7597 
          },
7598 
          'dma_host2board_busy' => {
7599 
            'attributes' => {
7600 
              'bin_pt' => 0,
7601 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
7602 
              'is_floating_block' => 1,
7603 
              'is_gateway_port' => 1,
7604 
              'must_be_hdl_vector' => 1,
7605 
              'period' => 1,
7606 
              'port_id' => 0,
7607 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
7608 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
7609 
              'timingConstraint' => 'none',
7610 
              'type' => 'UFix_1_0',
7611 
            },
7612 
            'direction' => 'in',
7613 
            'hdlType' => 'std_logic',
7614 
            'width' => 1,
7615 
          },
7616 
          'dma_host2board_done' => {
7617 
            'attributes' => {
7618 
              'bin_pt' => 0,
7619 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
7620 
              'is_floating_block' => 1,
7621 
              'is_gateway_port' => 1,
7622 
              'must_be_hdl_vector' => 1,
7623 
              'period' => 1,
7624 
              'port_id' => 0,
7625 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
7626 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
7627 
              'timingConstraint' => 'none',
7628 
              'type' => 'UFix_1_0',
7629 
            },
7630 
            'direction' => 'in',
7631 
            'hdlType' => 'std_logic',
7632 
            'width' => 1,
7633 
          },
7634 
          'from_register10_data_out' => {
7635 
            'attributes' => {
7636 
              'bin_pt' => 0,
7637 
              'is_floating_block' => 1,
7638 
              'must_be_hdl_vector' => 1,
7639 
              'period' => 1,
7640 
              'port_id' => 0,
7641 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
7642 
              'type' => 'UFix_32_0',
7643 
            },
7644 
            'direction' => 'in',
7645 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7646 
            'width' => 32,
7647 
          },
7648 
          'from_register11_data_out' => {
7649 
            'attributes' => {
7650 
              'bin_pt' => 0,
7651 
              'is_floating_block' => 1,
7652 
              'must_be_hdl_vector' => 1,
7653 
              'period' => 1,
7654 
              'port_id' => 0,
7655 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
7656 
              'type' => 'UFix_32_0',
7657 
            },
7658 
            'direction' => 'in',
7659 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7660 
            'width' => 32,
7661 
          },
7662 
          'from_register12_data_out' => {
7663 
            'attributes' => {
7664 
              'bin_pt' => 0,
7665 
              'is_floating_block' => 1,
7666 
              'must_be_hdl_vector' => 1,
7667 
              'period' => 1,
7668 
              'port_id' => 0,
7669 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
7670 
              'type' => 'UFix_1_0',
7671 
            },
7672 
            'direction' => 'in',
7673 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7674 
            'width' => 1,
7675 
          },
7676 
          'from_register13_data_out' => {
7677 
            'attributes' => {
7678 
              'bin_pt' => 0,
7679 
              'is_floating_block' => 1,
7680 
              'must_be_hdl_vector' => 1,
7681 
              'period' => 1,
7682 
              'port_id' => 0,
7683 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
7684 
              'type' => 'UFix_32_0',
7685 
            },
7686 
            'direction' => 'in',
7687 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7688 
            'width' => 32,
7689 
          },
7690 
          'from_register14_data_out' => {
7691 
            'attributes' => {
7692 
              'bin_pt' => 0,
7693 
              'is_floating_block' => 1,
7694 
              'must_be_hdl_vector' => 1,
7695 
              'period' => 1,
7696 
              'port_id' => 0,
7697 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
7698 
              'type' => 'UFix_1_0',
7699 
            },
7700 
            'direction' => 'in',
7701 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7702 
            'width' => 1,
7703 
          },
7704 
          'from_register15_data_out' => {
7705 
            'attributes' => {
7706 
              'bin_pt' => 0,
7707 
              'is_floating_block' => 1,
7708 
              'must_be_hdl_vector' => 1,
7709 
              'period' => 1,
7710 
              'port_id' => 0,
7711 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
7712 
              'type' => 'UFix_32_0',
7713 
            },
7714 
            'direction' => 'in',
7715 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7716 
            'width' => 32,
7717 
          },
7718 
          'from_register16_data_out' => {
7719 
            'attributes' => {
7720 
              'bin_pt' => 0,
7721 
              'is_floating_block' => 1,
7722 
              'must_be_hdl_vector' => 1,
7723 
              'period' => 1,
7724 
              'port_id' => 0,
7725 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
7726 
              'type' => 'UFix_1_0',
7727 
            },
7728 
            'direction' => 'in',
7729 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7730 
            'width' => 1,
7731 
          },
7732 
          'from_register17_data_out' => {
7733 
            'attributes' => {
7734 
              'bin_pt' => 0,
7735 
              'is_floating_block' => 1,
7736 
              'must_be_hdl_vector' => 1,
7737 
              'period' => 1,
7738 
              'port_id' => 0,
7739 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
7740 
              'type' => 'UFix_32_0',
7741 
            },
7742 
            'direction' => 'in',
7743 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7744 
            'width' => 32,
7745 
          },
7746 
          'from_register18_data_out' => {
7747 
            'attributes' => {
7748 
              'bin_pt' => 0,
7749 
              'is_floating_block' => 1,
7750 
              'must_be_hdl_vector' => 1,
7751 
              'period' => 1,
7752 
              'port_id' => 0,
7753 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
7754 
              'type' => 'UFix_1_0',
7755 
            },
7756 
            'direction' => 'in',
7757 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7758 
            'width' => 1,
7759 
          },
7760 
          'from_register19_data_out' => {
7761 
            'attributes' => {
7762 
              'bin_pt' => 0,
7763 
              'is_floating_block' => 1,
7764 
              'must_be_hdl_vector' => 1,
7765 
              'period' => 1,
7766 
              'port_id' => 0,
7767 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
7768 
              'type' => 'UFix_32_0',
7769 
            },
7770 
            'direction' => 'in',
7771 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7772 
            'width' => 32,
7773 
          },
7774 
          'from_register1_data_out' => {
7775 
            'attributes' => {
7776 
              'bin_pt' => 0,
7777 
              'is_floating_block' => 1,
7778 
              'must_be_hdl_vector' => 1,
7779 
              'period' => 1,
7780 
              'port_id' => 0,
7781 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
7782 
              'type' => 'UFix_1_0',
7783 
            },
7784 
            'direction' => 'in',
7785 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7786 
            'width' => 1,
7787 
          },
7788 
          'from_register20_data_out' => {
7789 
            'attributes' => {
7790 
              'bin_pt' => 0,
7791 
              'is_floating_block' => 1,
7792 
              'must_be_hdl_vector' => 1,
7793 
              'period' => 1,
7794 
              'port_id' => 0,
7795 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
7796 
              'type' => 'UFix_1_0',
7797 
            },
7798 
            'direction' => 'in',
7799 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7800 
            'width' => 1,
7801 
          },
7802 
          'from_register21_data_out' => {
7803 
            'attributes' => {
7804 
              'bin_pt' => 0,
7805 
              'is_floating_block' => 1,
7806 
              'must_be_hdl_vector' => 1,
7807 
              'period' => 1,
7808 
              'port_id' => 0,
7809 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
7810 
              'type' => 'UFix_32_0',
7811 
            },
7812 
            'direction' => 'in',
7813 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7814 
            'width' => 32,
7815 
          },
7816 
          'from_register22_data_out' => {
7817 
            'attributes' => {
7818 
              'bin_pt' => 0,
7819 
              'is_floating_block' => 1,
7820 
              'must_be_hdl_vector' => 1,
7821 
              'period' => 1,
7822 
              'port_id' => 0,
7823 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
7824 
              'type' => 'UFix_1_0',
7825 
            },
7826 
            'direction' => 'in',
7827 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7828 
            'width' => 1,
7829 
          },
7830 
          'from_register23_data_out' => {
7831 
            'attributes' => {
7832 
              'bin_pt' => 0,
7833 
              'is_floating_block' => 1,
7834 
              'must_be_hdl_vector' => 1,
7835 
              'period' => 1,
7836 
              'port_id' => 0,
7837 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
7838 
              'type' => 'UFix_32_0',
7839 
            },
7840 
            'direction' => 'in',
7841 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7842 
            'width' => 32,
7843 
          },
7844 
          'from_register24_data_out' => {
7845 
            'attributes' => {
7846 
              'bin_pt' => 0,
7847 
              'is_floating_block' => 1,
7848 
              'must_be_hdl_vector' => 1,
7849 
              'period' => 1,
7850 
              'port_id' => 0,
7851 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
7852 
              'type' => 'UFix_1_0',
7853 
            },
7854 
            'direction' => 'in',
7855 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7856 
            'width' => 1,
7857 
          },
7858 
          'from_register25_data_out' => {
7859 
            'attributes' => {
7860 
              'bin_pt' => 0,
7861 
              'is_floating_block' => 1,
7862 
              'must_be_hdl_vector' => 1,
7863 
              'period' => 1,
7864 
              'port_id' => 0,
7865 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
7866 
              'type' => 'UFix_32_0',
7867 
            },
7868 
            'direction' => 'in',
7869 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7870 
            'width' => 32,
7871 
          },
7872 
          'from_register26_data_out' => {
7873 
            'attributes' => {
7874 
              'bin_pt' => 0,
7875 
              'is_floating_block' => 1,
7876 
              'must_be_hdl_vector' => 1,
7877 
              'period' => 1,
7878 
              'port_id' => 0,
7879 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
7880 
              'type' => 'UFix_1_0',
7881 
            },
7882 
            'direction' => 'in',
7883 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7884 
            'width' => 1,
7885 
          },
7886 
          'from_register27_data_out' => {
7887 
            'attributes' => {
7888 
              'bin_pt' => 0,
7889 
              'is_floating_block' => 1,
7890 
              'must_be_hdl_vector' => 1,
7891 
              'period' => 1,
7892 
              'port_id' => 0,
7893 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
7894 
              'type' => 'UFix_32_0',
7895 
            },
7896 
            'direction' => 'in',
7897 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7898 
            'width' => 32,
7899 
          },
7900 
          'from_register28_data_out' => {
7901 
            'attributes' => {
7902 
              'bin_pt' => 0,
7903 
              'is_floating_block' => 1,
7904 
              'must_be_hdl_vector' => 1,
7905 
              'period' => 1,
7906 
              'port_id' => 0,
7907 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
7908 
              'type' => 'UFix_1_0',
7909 
            },
7910 
            'direction' => 'in',
7911 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7912 
            'width' => 1,
7913 
          },
7914 
          'from_register2_data_out' => {
7915 
            'attributes' => {
7916 
              'bin_pt' => 0,
7917 
              'is_floating_block' => 1,
7918 
              'must_be_hdl_vector' => 1,
7919 
              'period' => 1,
7920 
              'port_id' => 0,
7921 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
7922 
              'type' => 'UFix_1_0',
7923 
            },
7924 
            'direction' => 'in',
7925 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7926 
            'width' => 1,
7927 
          },
7928 
          'from_register3_data_out' => {
7929 
            'attributes' => {
7930 
              'bin_pt' => 0,
7931 
              'is_floating_block' => 1,
7932 
              'must_be_hdl_vector' => 1,
7933 
              'period' => 1,
7934 
              'port_id' => 0,
7935 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
7936 
              'type' => 'UFix_32_0',
7937 
            },
7938 
            'direction' => 'in',
7939 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7940 
            'width' => 32,
7941 
          },
7942 
          'from_register4_data_out' => {
7943 
            'attributes' => {
7944 
              'bin_pt' => 0,
7945 
              'is_floating_block' => 1,
7946 
              'must_be_hdl_vector' => 1,
7947 
              'period' => 1,
7948 
              'port_id' => 0,
7949 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
7950 
              'type' => 'UFix_1_0',
7951 
            },
7952 
            'direction' => 'in',
7953 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7954 
            'width' => 1,
7955 
          },
7956 
          'from_register5_data_out' => {
7957 
            'attributes' => {
7958 
              'bin_pt' => 0,
7959 
              'is_floating_block' => 1,
7960 
              'must_be_hdl_vector' => 1,
7961 
              'period' => 1,
7962 
              'port_id' => 0,
7963 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
7964 
              'type' => 'UFix_32_0',
7965 
            },
7966 
            'direction' => 'in',
7967 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7968 
            'width' => 32,
7969 
          },
7970 
          'from_register6_data_out' => {
7971 
            'attributes' => {
7972 
              'bin_pt' => 0,
7973 
              'is_floating_block' => 1,
7974 
              'must_be_hdl_vector' => 1,
7975 
              'period' => 1,
7976 
              'port_id' => 0,
7977 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
7978 
              'type' => 'UFix_1_0',
7979 
            },
7980 
            'direction' => 'in',
7981 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7982 
            'width' => 1,
7983 
          },
7984 
          'from_register7_data_out' => {
7985 
            'attributes' => {
7986 
              'bin_pt' => 0,
7987 
              'is_floating_block' => 1,
7988 
              'must_be_hdl_vector' => 1,
7989 
              'period' => 1,
7990 
              'port_id' => 0,
7991 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
7992 
              'type' => 'UFix_32_0',
7993 
            },
7994 
            'direction' => 'in',
7995 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7996 
            'width' => 32,
7997 
          },
7998 
          'from_register8_data_out' => {
7999 
            'attributes' => {
8000 
              'bin_pt' => 0,
8001 
              'is_floating_block' => 1,
8002 
              'must_be_hdl_vector' => 1,
8003 
              'period' => 1,
8004 
              'port_id' => 0,
8005 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
8006 
              'type' => 'UFix_32_0',
8007 
            },
8008 
            'direction' => 'in',
8009 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8010 
            'width' => 32,
8011 
          },
8012 
          'from_register9_data_out' => {
8013 
            'attributes' => {
8014 
              'bin_pt' => 0,
8015 
              'is_floating_block' => 1,
8016 
              'must_be_hdl_vector' => 1,
8017 
              'period' => 1,
8018 
              'port_id' => 0,
8019 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
8020 
              'type' => 'UFix_1_0',
8021 
            },
8022 
            'direction' => 'in',
8023 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8024 
            'width' => 1,
8025 
          },
8026 
          'reg01_rd' => {
8027 
            'attributes' => {
8028 
              'bin_pt' => 0,
8029 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
8030 
              'is_floating_block' => 1,
8031 
              'is_gateway_port' => 1,
8032 
              'must_be_hdl_vector' => 1,
8033 
              'period' => 1,
8034 
              'port_id' => 0,
8035 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
8036 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
8037 
              'timingConstraint' => 'none',
8038 
              'type' => 'UFix_32_0',
8039 
            },
8040 
            'direction' => 'out',
8041 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8042 
            'width' => 32,
8043 
          },
8044 
          'reg01_rv' => {
8045 
            'attributes' => {
8046 
              'bin_pt' => 0,
8047 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
8048 
              'is_floating_block' => 1,
8049 
              'is_gateway_port' => 1,
8050 
              'must_be_hdl_vector' => 1,
8051 
              'period' => 1,
8052 
              'port_id' => 0,
8053 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
8054 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
8055 
              'timingConstraint' => 'none',
8056 
              'type' => 'UFix_1_0',
8057 
            },
8058 
            'direction' => 'out',
8059 
            'hdlType' => 'std_logic',
8060 
            'width' => 1,
8061 
          },
8062 
          'reg01_td' => {
8063 
            'attributes' => {
8064 
              'bin_pt' => 0,
8065 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
8066 
              'is_floating_block' => 1,
8067 
              'is_gateway_port' => 1,
8068 
              'must_be_hdl_vector' => 1,
8069 
              'period' => 1,
8070 
              'port_id' => 0,
8071 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
8072 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
8073 
              'timingConstraint' => 'none',
8074 
              'type' => 'UFix_32_0',
8075 
            },
8076 
            'direction' => 'in',
8077 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8078 
            'width' => 32,
8079 
          },
8080 
          'reg01_tv' => {
8081 
            'attributes' => {
8082 
              'bin_pt' => 0,
8083 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
8084 
              'is_floating_block' => 1,
8085 
              'is_gateway_port' => 1,
8086 
              'must_be_hdl_vector' => 1,
8087 
              'period' => 1,
8088 
              'port_id' => 0,
8089 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
8090 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
8091 
              'timingConstraint' => 'none',
8092 
              'type' => 'Bool',
8093 
            },
8094 
            'direction' => 'in',
8095 
            'hdlType' => 'std_logic',
8096 
            'width' => 1,
8097 
          },
8098 
          'reg02_rd' => {
8099 
            'attributes' => {
8100 
              'bin_pt' => 0,
8101 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
8102 
              'is_floating_block' => 1,
8103 
              'is_gateway_port' => 1,
8104 
              'must_be_hdl_vector' => 1,
8105 
              'period' => 1,
8106 
              'port_id' => 0,
8107 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
8108 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
8109 
              'timingConstraint' => 'none',
8110 
              'type' => 'UFix_32_0',
8111 
            },
8112 
            'direction' => 'out',
8113 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8114 
            'width' => 32,
8115 
          },
8116 
          'reg02_rv' => {
8117 
            'attributes' => {
8118 
              'bin_pt' => 0,
8119 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
8120 
              'is_floating_block' => 1,
8121 
              'is_gateway_port' => 1,
8122 
              'must_be_hdl_vector' => 1,
8123 
              'period' => 1,
8124 
              'port_id' => 0,
8125 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
8126 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
8127 
              'timingConstraint' => 'none',
8128 
              'type' => 'UFix_1_0',
8129 
            },
8130 
            'direction' => 'out',
8131 
            'hdlType' => 'std_logic',
8132 
            'width' => 1,
8133 
          },
8134 
          'reg02_td' => {
8135 
            'attributes' => {
8136 
              'bin_pt' => 0,
8137 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
8138 
              'is_floating_block' => 1,
8139 
              'is_gateway_port' => 1,
8140 
              'must_be_hdl_vector' => 1,
8141 
              'period' => 1,
8142 
              'port_id' => 0,
8143 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
8144 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
8145 
              'timingConstraint' => 'none',
8146 
              'type' => 'UFix_32_0',
8147 
            },
8148 
            'direction' => 'in',
8149 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8150 
            'width' => 32,
8151 
          },
8152 
          'reg02_tv' => {
8153 
            'attributes' => {
8154 
              'bin_pt' => 0,
8155 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
8156 
              'is_floating_block' => 1,
8157 
              'is_gateway_port' => 1,
8158 
              'must_be_hdl_vector' => 1,
8159 
              'period' => 1,
8160 
              'port_id' => 0,
8161 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
8162 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
8163 
              'timingConstraint' => 'none',
8164 
              'type' => 'Bool',
8165 
            },
8166 
            'direction' => 'in',
8167 
            'hdlType' => 'std_logic',
8168 
            'width' => 1,
8169 
          },
8170 
          'reg03_rd' => {
8171 
            'attributes' => {
8172 
              'bin_pt' => 0,
8173 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
8174 
              'is_floating_block' => 1,
8175 
              'is_gateway_port' => 1,
8176 
              'must_be_hdl_vector' => 1,
8177 
              'period' => 1,
8178 
              'port_id' => 0,
8179 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
8180 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
8181 
              'timingConstraint' => 'none',
8182 
              'type' => 'UFix_32_0',
8183 
            },
8184 
            'direction' => 'out',
8185 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8186 
            'width' => 32,
8187 
          },
8188 
          'reg03_rv' => {
8189 
            'attributes' => {
8190 
              'bin_pt' => 0,
8191 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
8192 
              'is_floating_block' => 1,
8193 
              'is_gateway_port' => 1,
8194 
              'must_be_hdl_vector' => 1,
8195 
              'period' => 1,
8196 
              'port_id' => 0,
8197 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
8198 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
8199 
              'timingConstraint' => 'none',
8200 
              'type' => 'UFix_1_0',
8201 
            },
8202 
            'direction' => 'out',
8203 
            'hdlType' => 'std_logic',
8204 
            'width' => 1,
8205 
          },
8206 
          'reg03_td' => {
8207 
            'attributes' => {
8208 
              'bin_pt' => 0,
8209 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
8210 
              'is_floating_block' => 1,
8211 
              'is_gateway_port' => 1,
8212 
              'must_be_hdl_vector' => 1,
8213 
              'period' => 1,
8214 
              'port_id' => 0,
8215 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
8216 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
8217 
              'timingConstraint' => 'none',
8218 
              'type' => 'UFix_32_0',
8219 
            },
8220 
            'direction' => 'in',
8221 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8222 
            'width' => 32,
8223 
          },
8224 
          'reg03_tv' => {
8225 
            'attributes' => {
8226 
              'bin_pt' => 0,
8227 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
8228 
              'is_floating_block' => 1,
8229 
              'is_gateway_port' => 1,
8230 
              'must_be_hdl_vector' => 1,
8231 
              'period' => 1,
8232 
              'port_id' => 0,
8233 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
8234 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
8235 
              'timingConstraint' => 'none',
8236 
              'type' => 'Bool',
8237 
            },
8238 
            'direction' => 'in',
8239 
            'hdlType' => 'std_logic',
8240 
            'width' => 1,
8241 
          },
8242 
          'reg04_rd' => {
8243 
            'attributes' => {
8244 
              'bin_pt' => 0,
8245 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
8246 
              'is_floating_block' => 1,
8247 
              'is_gateway_port' => 1,
8248 
              'must_be_hdl_vector' => 1,
8249 
              'period' => 1,
8250 
              'port_id' => 0,
8251 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
8252 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
8253 
              'timingConstraint' => 'none',
8254 
              'type' => 'UFix_32_0',
8255 
            },
8256 
            'direction' => 'out',
8257 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8258 
            'width' => 32,
8259 
          },
8260 
          'reg04_rv' => {
8261 
            'attributes' => {
8262 
              'bin_pt' => 0,
8263 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
8264 
              'is_floating_block' => 1,
8265 
              'is_gateway_port' => 1,
8266 
              'must_be_hdl_vector' => 1,
8267 
              'period' => 1,
8268 
              'port_id' => 0,
8269 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
8270 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
8271 
              'timingConstraint' => 'none',
8272 
              'type' => 'UFix_1_0',
8273 
            },
8274 
            'direction' => 'out',
8275 
            'hdlType' => 'std_logic',
8276 
            'width' => 1,
8277 
          },
8278 
          'reg04_td' => {
8279 
            'attributes' => {
8280 
              'bin_pt' => 0,
8281 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
8282 
              'is_floating_block' => 1,
8283 
              'is_gateway_port' => 1,
8284 
              'must_be_hdl_vector' => 1,
8285 
              'period' => 1,
8286 
              'port_id' => 0,
8287 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
8288 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
8289 
              'timingConstraint' => 'none',
8290 
              'type' => 'UFix_32_0',
8291 
            },
8292 
            'direction' => 'in',
8293 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8294 
            'width' => 32,
8295 
          },
8296 
          'reg04_tv' => {
8297 
            'attributes' => {
8298 
              'bin_pt' => 0,
8299 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
8300 
              'is_floating_block' => 1,
8301 
              'is_gateway_port' => 1,
8302 
              'must_be_hdl_vector' => 1,
8303 
              'period' => 1,
8304 
              'port_id' => 0,
8305 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
8306 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
8307 
              'timingConstraint' => 'none',
8308 
              'type' => 'Bool',
8309 
            },
8310 
            'direction' => 'in',
8311 
            'hdlType' => 'std_logic',
8312 
            'width' => 1,
8313 
          },
8314 
          'reg05_rd' => {
8315 
            'attributes' => {
8316 
              'bin_pt' => 0,
8317 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
8318 
              'is_floating_block' => 1,
8319 
              'is_gateway_port' => 1,
8320 
              'must_be_hdl_vector' => 1,
8321 
              'period' => 1,
8322 
              'port_id' => 0,
8323 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
8324 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
8325 
              'timingConstraint' => 'none',
8326 
              'type' => 'UFix_32_0',
8327 
            },
8328 
            'direction' => 'out',
8329 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8330 
            'width' => 32,
8331 
          },
8332 
          'reg05_rv' => {
8333 
            'attributes' => {
8334 
              'bin_pt' => 0,
8335 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
8336 
              'is_floating_block' => 1,
8337 
              'is_gateway_port' => 1,
8338 
              'must_be_hdl_vector' => 1,
8339 
              'period' => 1,
8340 
              'port_id' => 0,
8341 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
8342 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
8343 
              'timingConstraint' => 'none',
8344 
              'type' => 'UFix_1_0',
8345 
            },
8346 
            'direction' => 'out',
8347 
            'hdlType' => 'std_logic',
8348 
            'width' => 1,
8349 
          },
8350 
          'reg05_td' => {
8351 
            'attributes' => {
8352 
              'bin_pt' => 0,
8353 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
8354 
              'is_floating_block' => 1,
8355 
              'is_gateway_port' => 1,
8356 
              'must_be_hdl_vector' => 1,
8357 
              'period' => 1,
8358 
              'port_id' => 0,
8359 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
8360 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
8361 
              'timingConstraint' => 'none',
8362 
              'type' => 'UFix_32_0',
8363 
            },
8364 
            'direction' => 'in',
8365 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8366 
            'width' => 32,
8367 
          },
8368 
          'reg05_tv' => {
8369 
            'attributes' => {
8370 
              'bin_pt' => 0,
8371 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
8372 
              'is_floating_block' => 1,
8373 
              'is_gateway_port' => 1,
8374 
              'must_be_hdl_vector' => 1,
8375 
              'period' => 1,
8376 
              'port_id' => 0,
8377 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
8378 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
8379 
              'timingConstraint' => 'none',
8380 
              'type' => 'Bool',
8381 
            },
8382 
            'direction' => 'in',
8383 
            'hdlType' => 'std_logic',
8384 
            'width' => 1,
8385 
          },
8386 
          'reg06_rd' => {
8387 
            'attributes' => {
8388 
              'bin_pt' => 0,
8389 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
8390 
              'is_floating_block' => 1,
8391 
              'is_gateway_port' => 1,
8392 
              'must_be_hdl_vector' => 1,
8393 
              'period' => 1,
8394 
              'port_id' => 0,
8395 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
8396 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
8397 
              'timingConstraint' => 'none',
8398 
              'type' => 'UFix_32_0',
8399 
            },
8400 
            'direction' => 'out',
8401 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8402 
            'width' => 32,
8403 
          },
8404 
          'reg06_rv' => {
8405 
            'attributes' => {
8406 
              'bin_pt' => 0,
8407 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
8408 
              'is_floating_block' => 1,
8409 
              'is_gateway_port' => 1,
8410 
              'must_be_hdl_vector' => 1,
8411 
              'period' => 1,
8412 
              'port_id' => 0,
8413 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
8414 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
8415 
              'timingConstraint' => 'none',
8416 
              'type' => 'UFix_1_0',
8417 
            },
8418 
            'direction' => 'out',
8419 
            'hdlType' => 'std_logic',
8420 
            'width' => 1,
8421 
          },
8422 
          'reg06_td' => {
8423 
            'attributes' => {
8424 
              'bin_pt' => 0,
8425 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
8426 
              'is_floating_block' => 1,
8427 
              'is_gateway_port' => 1,
8428 
              'must_be_hdl_vector' => 1,
8429 
              'period' => 1,
8430 
              'port_id' => 0,
8431 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
8432 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
8433 
              'timingConstraint' => 'none',
8434 
              'type' => 'UFix_32_0',
8435 
            },
8436 
            'direction' => 'in',
8437 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8438 
            'width' => 32,
8439 
          },
8440 
          'reg06_tv' => {
8441 
            'attributes' => {
8442 
              'bin_pt' => 0,
8443 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
8444 
              'is_floating_block' => 1,
8445 
              'is_gateway_port' => 1,
8446 
              'must_be_hdl_vector' => 1,
8447 
              'period' => 1,
8448 
              'port_id' => 0,
8449 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
8450 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
8451 
              'timingConstraint' => 'none',
8452 
              'type' => 'Bool',
8453 
            },
8454 
            'direction' => 'in',
8455 
            'hdlType' => 'std_logic',
8456 
            'width' => 1,
8457 
          },
8458 
          'reg07_rd' => {
8459 
            'attributes' => {
8460 
              'bin_pt' => 0,
8461 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
8462 
              'is_floating_block' => 1,
8463 
              'is_gateway_port' => 1,
8464 
              'must_be_hdl_vector' => 1,
8465 
              'period' => 1,
8466 
              'port_id' => 0,
8467 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
8468 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
8469 
              'timingConstraint' => 'none',
8470 
              'type' => 'UFix_32_0',
8471 
            },
8472 
            'direction' => 'out',
8473 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8474 
            'width' => 32,
8475 
          },
8476 
          'reg07_rv' => {
8477 
            'attributes' => {
8478 
              'bin_pt' => 0,
8479 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
8480 
              'is_floating_block' => 1,
8481 
              'is_gateway_port' => 1,
8482 
              'must_be_hdl_vector' => 1,
8483 
              'period' => 1,
8484 
              'port_id' => 0,
8485 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
8486 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
8487 
              'timingConstraint' => 'none',
8488 
              'type' => 'UFix_1_0',
8489 
            },
8490 
            'direction' => 'out',
8491 
            'hdlType' => 'std_logic',
8492 
            'width' => 1,
8493 
          },
8494 
          'reg07_td' => {
8495 
            'attributes' => {
8496 
              'bin_pt' => 0,
8497 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
8498 
              'is_floating_block' => 1,
8499 
              'is_gateway_port' => 1,
8500 
              'must_be_hdl_vector' => 1,
8501 
              'period' => 1,
8502 
              'port_id' => 0,
8503 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
8504 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
8505 
              'timingConstraint' => 'none',
8506 
              'type' => 'UFix_32_0',
8507 
            },
8508 
            'direction' => 'in',
8509 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8510 
            'width' => 32,
8511 
          },
8512 
          'reg07_tv' => {
8513 
            'attributes' => {
8514 
              'bin_pt' => 0,
8515 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
8516 
              'is_floating_block' => 1,
8517 
              'is_gateway_port' => 1,
8518 
              'must_be_hdl_vector' => 1,
8519 
              'period' => 1,
8520 
              'port_id' => 0,
8521 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
8522 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
8523 
              'timingConstraint' => 'none',
8524 
              'type' => 'Bool',
8525 
            },
8526 
            'direction' => 'in',
8527 
            'hdlType' => 'std_logic',
8528 
            'width' => 1,
8529 
          },
8530 
          'reg08_rd' => {
8531 
            'attributes' => {
8532 
              'bin_pt' => 0,
8533 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
8534 
              'is_floating_block' => 1,
8535 
              'is_gateway_port' => 1,
8536 
              'must_be_hdl_vector' => 1,
8537 
              'period' => 1,
8538 
              'port_id' => 0,
8539 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
8540 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
8541 
              'timingConstraint' => 'none',
8542 
              'type' => 'UFix_32_0',
8543 
            },
8544 
            'direction' => 'out',
8545 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8546 
            'width' => 32,
8547 
          },
8548 
          'reg08_rv' => {
8549 
            'attributes' => {
8550 
              'bin_pt' => 0,
8551 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
8552 
              'is_floating_block' => 1,
8553 
              'is_gateway_port' => 1,
8554 
              'must_be_hdl_vector' => 1,
8555 
              'period' => 1,
8556 
              'port_id' => 0,
8557 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
8558 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
8559 
              'timingConstraint' => 'none',
8560 
              'type' => 'UFix_1_0',
8561 
            },
8562 
            'direction' => 'out',
8563 
            'hdlType' => 'std_logic',
8564 
            'width' => 1,
8565 
          },
8566 
          'reg08_td' => {
8567 
            'attributes' => {
8568 
              'bin_pt' => 0,
8569 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
8570 
              'is_floating_block' => 1,
8571 
              'is_gateway_port' => 1,
8572 
              'must_be_hdl_vector' => 1,
8573 
              'period' => 1,
8574 
              'port_id' => 0,
8575 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
8576 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
8577 
              'timingConstraint' => 'none',
8578 
              'type' => 'UFix_32_0',
8579 
            },
8580 
            'direction' => 'in',
8581 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8582 
            'width' => 32,
8583 
          },
8584 
          'reg08_tv' => {
8585 
            'attributes' => {
8586 
              'bin_pt' => 0,
8587 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
8588 
              'is_floating_block' => 1,
8589 
              'is_gateway_port' => 1,
8590 
              'must_be_hdl_vector' => 1,
8591 
              'period' => 1,
8592 
              'port_id' => 0,
8593 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
8594 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
8595 
              'timingConstraint' => 'none',
8596 
              'type' => 'Bool',
8597 
            },
8598 
            'direction' => 'in',
8599 
            'hdlType' => 'std_logic',
8600 
            'width' => 1,
8601 
          },
8602 
          'reg09_rd' => {
8603 
            'attributes' => {
8604 
              'bin_pt' => 0,
8605 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
8606 
              'is_floating_block' => 1,
8607 
              'is_gateway_port' => 1,
8608 
              'must_be_hdl_vector' => 1,
8609 
              'period' => 1,
8610 
              'port_id' => 0,
8611 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
8612 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
8613 
              'timingConstraint' => 'none',
8614 
              'type' => 'UFix_32_0',
8615 
            },
8616 
            'direction' => 'out',
8617 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8618 
            'width' => 32,
8619 
          },
8620 
          'reg09_rv' => {
8621 
            'attributes' => {
8622 
              'bin_pt' => 0,
8623 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
8624 
              'is_floating_block' => 1,
8625 
              'is_gateway_port' => 1,
8626 
              'must_be_hdl_vector' => 1,
8627 
              'period' => 1,
8628 
              'port_id' => 0,
8629 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
8630 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
8631 
              'timingConstraint' => 'none',
8632 
              'type' => 'UFix_1_0',
8633 
            },
8634 
            'direction' => 'out',
8635 
            'hdlType' => 'std_logic',
8636 
            'width' => 1,
8637 
          },
8638 
          'reg09_td' => {
8639 
            'attributes' => {
8640 
              'bin_pt' => 0,
8641 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
8642 
              'is_floating_block' => 1,
8643 
              'is_gateway_port' => 1,
8644 
              'must_be_hdl_vector' => 1,
8645 
              'period' => 1,
8646 
              'port_id' => 0,
8647 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
8648 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
8649 
              'timingConstraint' => 'none',
8650 
              'type' => 'UFix_32_0',
8651 
            },
8652 
            'direction' => 'in',
8653 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8654 
            'width' => 32,
8655 
          },
8656 
          'reg09_tv' => {
8657 
            'attributes' => {
8658 
              'bin_pt' => 0,
8659 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
8660 
              'is_floating_block' => 1,
8661 
              'is_gateway_port' => 1,
8662 
              'must_be_hdl_vector' => 1,
8663 
              'period' => 1,
8664 
              'port_id' => 0,
8665 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
8666 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
8667 
              'timingConstraint' => 'none',
8668 
              'type' => 'Bool',
8669 
            },
8670 
            'direction' => 'in',
8671 
            'hdlType' => 'std_logic',
8672 
            'width' => 1,
8673 
          },
8674 
          'reg10_rd' => {
8675 
            'attributes' => {
8676 
              'bin_pt' => 0,
8677 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
8678 
              'is_floating_block' => 1,
8679 
              'is_gateway_port' => 1,
8680 
              'must_be_hdl_vector' => 1,
8681 
              'period' => 1,
8682 
              'port_id' => 0,
8683 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
8684 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
8685 
              'timingConstraint' => 'none',
8686 
              'type' => 'UFix_32_0',
8687 
            },
8688 
            'direction' => 'out',
8689 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8690 
            'width' => 32,
8691 
          },
8692 
          'reg10_rv' => {
8693 
            'attributes' => {
8694 
              'bin_pt' => 0,
8695 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
8696 
              'is_floating_block' => 1,
8697 
              'is_gateway_port' => 1,
8698 
              'must_be_hdl_vector' => 1,
8699 
              'period' => 1,
8700 
              'port_id' => 0,
8701 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
8702 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
8703 
              'timingConstraint' => 'none',
8704 
              'type' => 'UFix_1_0',
8705 
            },
8706 
            'direction' => 'out',
8707 
            'hdlType' => 'std_logic',
8708 
            'width' => 1,
8709 
          },
8710 
          'reg10_td' => {
8711 
            'attributes' => {
8712 
              'bin_pt' => 0,
8713 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
8714 
              'is_floating_block' => 1,
8715 
              'is_gateway_port' => 1,
8716 
              'must_be_hdl_vector' => 1,
8717 
              'period' => 1,
8718 
              'port_id' => 0,
8719 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
8720 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
8721 
              'timingConstraint' => 'none',
8722 
              'type' => 'UFix_32_0',
8723 
            },
8724 
            'direction' => 'in',
8725 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8726 
            'width' => 32,
8727 
          },
8728 
          'reg10_tv' => {
8729 
            'attributes' => {
8730 
              'bin_pt' => 0,
8731 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
8732 
              'is_floating_block' => 1,
8733 
              'is_gateway_port' => 1,
8734 
              'must_be_hdl_vector' => 1,
8735 
              'period' => 1,
8736 
              'port_id' => 0,
8737 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
8738 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
8739 
              'timingConstraint' => 'none',
8740 
              'type' => 'Bool',
8741 
            },
8742 
            'direction' => 'in',
8743 
            'hdlType' => 'std_logic',
8744 
            'width' => 1,
8745 
          },
8746 
          'reg11_rd' => {
8747 
            'attributes' => {
8748 
              'bin_pt' => 0,
8749 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
8750 
              'is_floating_block' => 1,
8751 
              'is_gateway_port' => 1,
8752 
              'must_be_hdl_vector' => 1,
8753 
              'period' => 1,
8754 
              'port_id' => 0,
8755 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
8756 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
8757 
              'timingConstraint' => 'none',
8758 
              'type' => 'UFix_32_0',
8759 
            },
8760 
            'direction' => 'out',
8761 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8762 
            'width' => 32,
8763 
          },
8764 
          'reg11_rv' => {
8765 
            'attributes' => {
8766 
              'bin_pt' => 0,
8767 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
8768 
              'is_floating_block' => 1,
8769 
              'is_gateway_port' => 1,
8770 
              'must_be_hdl_vector' => 1,
8771 
              'period' => 1,
8772 
              'port_id' => 0,
8773 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
8774 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
8775 
              'timingConstraint' => 'none',
8776 
              'type' => 'UFix_1_0',
8777 
            },
8778 
            'direction' => 'out',
8779 
            'hdlType' => 'std_logic',
8780 
            'width' => 1,
8781 
          },
8782 
          'reg11_td' => {
8783 
            'attributes' => {
8784 
              'bin_pt' => 0,
8785 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
8786 
              'is_floating_block' => 1,
8787 
              'is_gateway_port' => 1,
8788 
              'must_be_hdl_vector' => 1,
8789 
              'period' => 1,
8790 
              'port_id' => 0,
8791 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
8792 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
8793 
              'timingConstraint' => 'none',
8794 
              'type' => 'UFix_32_0',
8795 
            },
8796 
            'direction' => 'in',
8797 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8798 
            'width' => 32,
8799 
          },
8800 
          'reg11_tv' => {
8801 
            'attributes' => {
8802 
              'bin_pt' => 0,
8803 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
8804 
              'is_floating_block' => 1,
8805 
              'is_gateway_port' => 1,
8806 
              'must_be_hdl_vector' => 1,
8807 
              'period' => 1,
8808 
              'port_id' => 0,
8809 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
8810 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
8811 
              'timingConstraint' => 'none',
8812 
              'type' => 'Bool',
8813 
            },
8814 
            'direction' => 'in',
8815 
            'hdlType' => 'std_logic',
8816 
            'width' => 1,
8817 
          },
8818 
          'reg12_rd' => {
8819 
            'attributes' => {
8820 
              'bin_pt' => 0,
8821 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
8822 
              'is_floating_block' => 1,
8823 
              'is_gateway_port' => 1,
8824 
              'must_be_hdl_vector' => 1,
8825 
              'period' => 1,
8826 
              'port_id' => 0,
8827 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
8828 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
8829 
              'timingConstraint' => 'none',
8830 
              'type' => 'UFix_32_0',
8831 
            },
8832 
            'direction' => 'out',
8833 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8834 
            'width' => 32,
8835 
          },
8836 
          'reg12_rv' => {
8837 
            'attributes' => {
8838 
              'bin_pt' => 0,
8839 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
8840 
              'is_floating_block' => 1,
8841 
              'is_gateway_port' => 1,
8842 
              'must_be_hdl_vector' => 1,
8843 
              'period' => 1,
8844 
              'port_id' => 0,
8845 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
8846 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
8847 
              'timingConstraint' => 'none',
8848 
              'type' => 'UFix_1_0',
8849 
            },
8850 
            'direction' => 'out',
8851 
            'hdlType' => 'std_logic',
8852 
            'width' => 1,
8853 
          },
8854 
          'reg12_td' => {
8855 
            'attributes' => {
8856 
              'bin_pt' => 0,
8857 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
8858 
              'is_floating_block' => 1,
8859 
              'is_gateway_port' => 1,
8860 
              'must_be_hdl_vector' => 1,
8861 
              'period' => 1,
8862 
              'port_id' => 0,
8863 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
8864 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
8865 
              'timingConstraint' => 'none',
8866 
              'type' => 'UFix_32_0',
8867 
            },
8868 
            'direction' => 'in',
8869 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8870 
            'width' => 32,
8871 
          },
8872 
          'reg12_tv' => {
8873 
            'attributes' => {
8874 
              'bin_pt' => 0,
8875 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
8876 
              'is_floating_block' => 1,
8877 
              'is_gateway_port' => 1,
8878 
              'must_be_hdl_vector' => 1,
8879 
              'period' => 1,
8880 
              'port_id' => 0,
8881 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
8882 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
8883 
              'timingConstraint' => 'none',
8884 
              'type' => 'Bool',
8885 
            },
8886 
            'direction' => 'in',
8887 
            'hdlType' => 'std_logic',
8888 
            'width' => 1,
8889 
          },
8890 
          'reg13_rd' => {
8891 
            'attributes' => {
8892 
              'bin_pt' => 0,
8893 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
8894 
              'is_floating_block' => 1,
8895 
              'is_gateway_port' => 1,
8896 
              'must_be_hdl_vector' => 1,
8897 
              'period' => 1,
8898 
              'port_id' => 0,
8899 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
8900 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
8901 
              'timingConstraint' => 'none',
8902 
              'type' => 'UFix_32_0',
8903 
            },
8904 
            'direction' => 'out',
8905 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8906 
            'width' => 32,
8907 
          },
8908 
          'reg13_rv' => {
8909 
            'attributes' => {
8910 
              'bin_pt' => 0,
8911 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
8912 
              'is_floating_block' => 1,
8913 
              'is_gateway_port' => 1,
8914 
              'must_be_hdl_vector' => 1,
8915 
              'period' => 1,
8916 
              'port_id' => 0,
8917 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
8918 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
8919 
              'timingConstraint' => 'none',
8920 
              'type' => 'UFix_1_0',
8921 
            },
8922 
            'direction' => 'out',
8923 
            'hdlType' => 'std_logic',
8924 
            'width' => 1,
8925 
          },
8926 
          'reg13_td' => {
8927 
            'attributes' => {
8928 
              'bin_pt' => 0,
8929 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
8930 
              'is_floating_block' => 1,
8931 
              'is_gateway_port' => 1,
8932 
              'must_be_hdl_vector' => 1,
8933 
              'period' => 1,
8934 
              'port_id' => 0,
8935 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
8936 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
8937 
              'timingConstraint' => 'none',
8938 
              'type' => 'UFix_32_0',
8939 
            },
8940 
            'direction' => 'in',
8941 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8942 
            'width' => 32,
8943 
          },
8944 
          'reg13_tv' => {
8945 
            'attributes' => {
8946 
              'bin_pt' => 0,
8947 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
8948 
              'is_floating_block' => 1,
8949 
              'is_gateway_port' => 1,
8950 
              'must_be_hdl_vector' => 1,
8951 
              'period' => 1,
8952 
              'port_id' => 0,
8953 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
8954 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
8955 
              'timingConstraint' => 'none',
8956 
              'type' => 'Bool',
8957 
            },
8958 
            'direction' => 'in',
8959 
            'hdlType' => 'std_logic',
8960 
            'width' => 1,
8961 
          },
8962 
          'reg14_rd' => {
8963 
            'attributes' => {
8964 
              'bin_pt' => 0,
8965 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
8966 
              'is_floating_block' => 1,
8967 
              'is_gateway_port' => 1,
8968 
              'must_be_hdl_vector' => 1,
8969 
              'period' => 1,
8970 
              'port_id' => 0,
8971 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
8972 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
8973 
              'timingConstraint' => 'none',
8974 
              'type' => 'UFix_32_0',
8975 
            },
8976 
            'direction' => 'out',
8977 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8978 
            'width' => 32,
8979 
          },
8980 
          'reg14_rv' => {
8981 
            'attributes' => {
8982 
              'bin_pt' => 0,
8983 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
8984 
              'is_floating_block' => 1,
8985 
              'is_gateway_port' => 1,
8986 
              'must_be_hdl_vector' => 1,
8987 
              'period' => 1,
8988 
              'port_id' => 0,
8989 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
8990 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
8991 
              'timingConstraint' => 'none',
8992 
              'type' => 'UFix_1_0',
8993 
            },
8994 
            'direction' => 'out',
8995 
            'hdlType' => 'std_logic',
8996 
            'width' => 1,
8997 
          },
8998 
          'reg14_td' => {
8999 
            'attributes' => {
9000 
              'bin_pt' => 0,
9001 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
9002 
              'is_floating_block' => 1,
9003 
              'is_gateway_port' => 1,
9004 
              'must_be_hdl_vector' => 1,
9005 
              'period' => 1,
9006 
              'port_id' => 0,
9007 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
9008 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
9009 
              'timingConstraint' => 'none',
9010 
              'type' => 'UFix_32_0',
9011 
            },
9012 
            'direction' => 'in',
9013 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9014 
            'width' => 32,
9015 
          },
9016 
          'reg14_tv' => {
9017 
            'attributes' => {
9018 
              'bin_pt' => 0,
9019 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
9020 
              'is_floating_block' => 1,
9021 
              'is_gateway_port' => 1,
9022 
              'must_be_hdl_vector' => 1,
9023 
              'period' => 1,
9024 
              'port_id' => 0,
9025 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
9026 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
9027 
              'timingConstraint' => 'none',
9028 
              'type' => 'Bool',
9029 
            },
9030 
            'direction' => 'in',
9031 
            'hdlType' => 'std_logic',
9032 
            'width' => 1,
9033 
          },
9034 
          'to_register10_ce' => {
9035 
            'attributes' => {
9036 
              'domain' => '',
9037 
              'group' => 1,
9038 
              'isCe' => 1,
9039 
              'is_floating_block' => 1,
9040 
              'period' => 1,
9041 
              'type' => 'logic',
9042 
            },
9043 
            'direction' => 'out',
9044 
            'hdlType' => 'std_logic',
9045 
            'width' => 1,
9046 
          },
9047 
          'to_register10_clk' => {
9048 
            'attributes' => {
9049 
              'domain' => '',
9050 
              'group' => 1,
9051 
              'isClk' => 1,
9052 
              'is_floating_block' => 1,
9053 
              'period' => 1,
9054 
              'type' => 'logic',
9055 
            },
9056 
            'direction' => 'out',
9057 
            'hdlType' => 'std_logic',
9058 
            'width' => 1,
9059 
          },
9060 
          'to_register10_clr' => {
9061 
            'attributes' => {
9062 
              'domain' => '',
9063 
              'group' => 1,
9064 
              'isClr' => 1,
9065 
              'is_floating_block' => 1,
9066 
              'period' => 1,
9067 
              'type' => 'logic',
9068 
              'valid_bit_used' => 0,
9069 
            },
9070 
            'direction' => 'out',
9071 
            'hdlType' => 'std_logic',
9072 
            'width' => 1,
9073 
          },
9074 
          'to_register10_data_in' => {
9075 
            'attributes' => {
9076 
              'bin_pt' => 0,
9077 
              'is_floating_block' => 1,
9078 
              'must_be_hdl_vector' => 1,
9079 
              'period' => 1,
9080 
              'port_id' => 0,
9081 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
9082 
              'type' => 'Bool',
9083 
            },
9084 
            'direction' => 'out',
9085 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9086 
            'width' => 1,
9087 
          },
9088 
          'to_register10_dout' => {
9089 
            'attributes' => {
9090 
              'bin_pt' => 0,
9091 
              'is_floating_block' => 1,
9092 
              'must_be_hdl_vector' => 1,
9093 
              'period' => 1,
9094 
              'port_id' => 0,
9095 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
9096 
              'type' => 'Bool',
9097 
            },
9098 
            'direction' => 'in',
9099 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9100 
            'width' => 1,
9101 
          },
9102 
          'to_register10_en' => {
9103 
            'attributes' => {
9104 
              'bin_pt' => 0,
9105 
              'is_floating_block' => 1,
9106 
              'must_be_hdl_vector' => 1,
9107 
              'period' => 1,
9108 
              'port_id' => 1,
9109 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
9110 
              'type' => 'Bool',
9111 
            },
9112 
            'direction' => 'out',
9113 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9114 
            'width' => 1,
9115 
          },
9116 
          'to_register11_ce' => {
9117 
            'attributes' => {
9118 
              'domain' => '',
9119 
              'group' => 1,
9120 
              'isCe' => 1,
9121 
              'is_floating_block' => 1,
9122 
              'period' => 1,
9123 
              'type' => 'logic',
9124 
            },
9125 
            'direction' => 'out',
9126 
            'hdlType' => 'std_logic',
9127 
            'width' => 1,
9128 
          },
9129 
          'to_register11_clk' => {
9130 
            'attributes' => {
9131 
              'domain' => '',
9132 
              'group' => 1,
9133 
              'isClk' => 1,
9134 
              'is_floating_block' => 1,
9135 
              'period' => 1,
9136 
              'type' => 'logic',
9137 
            },
9138 
            'direction' => 'out',
9139 
            'hdlType' => 'std_logic',
9140 
            'width' => 1,
9141 
          },
9142 
          'to_register11_clr' => {
9143 
            'attributes' => {
9144 
              'domain' => '',
9145 
              'group' => 1,
9146 
              'isClr' => 1,
9147 
              'is_floating_block' => 1,
9148 
              'period' => 1,
9149 
              'type' => 'logic',
9150 
              'valid_bit_used' => 0,
9151 
            },
9152 
            'direction' => 'out',
9153 
            'hdlType' => 'std_logic',
9154 
            'width' => 1,
9155 
          },
9156 
          'to_register11_data_in' => {
9157 
            'attributes' => {
9158 
              'bin_pt' => 0,
9159 
              'is_floating_block' => 1,
9160 
              'must_be_hdl_vector' => 1,
9161 
              'period' => 1,
9162 
              'port_id' => 0,
9163 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
9164 
              'type' => 'UFix_32_0',
9165 
            },
9166 
            'direction' => 'out',
9167 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9168 
            'width' => 32,
9169 
          },
9170 
          'to_register11_dout' => {
9171 
            'attributes' => {
9172 
              'bin_pt' => 0,
9173 
              'is_floating_block' => 1,
9174 
              'must_be_hdl_vector' => 1,
9175 
              'period' => 1,
9176 
              'port_id' => 0,
9177 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
9178 
              'type' => 'UFix_32_0',
9179 
            },
9180 
            'direction' => 'in',
9181 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9182 
            'width' => 32,
9183 
          },
9184 
          'to_register11_en' => {
9185 
            'attributes' => {
9186 
              'bin_pt' => 0,
9187 
              'is_floating_block' => 1,
9188 
              'must_be_hdl_vector' => 1,
9189 
              'period' => 1,
9190 
              'port_id' => 1,
9191 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
9192 
              'type' => 'Bool',
9193 
            },
9194 
            'direction' => 'out',
9195 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9196 
            'width' => 1,
9197 
          },
9198 
          'to_register12_ce' => {
9199 
            'attributes' => {
9200 
              'domain' => '',
9201 
              'group' => 1,
9202 
              'isCe' => 1,
9203 
              'is_floating_block' => 1,
9204 
              'period' => 1,
9205 
              'type' => 'logic',
9206 
            },
9207 
            'direction' => 'out',
9208 
            'hdlType' => 'std_logic',
9209 
            'width' => 1,
9210 
          },
9211 
          'to_register12_clk' => {
9212 
            'attributes' => {
9213 
              'domain' => '',
9214 
              'group' => 1,
9215 
              'isClk' => 1,
9216 
              'is_floating_block' => 1,
9217 
              'period' => 1,
9218 
              'type' => 'logic',
9219 
            },
9220 
            'direction' => 'out',
9221 
            'hdlType' => 'std_logic',
9222 
            'width' => 1,
9223 
          },
9224 
          'to_register12_clr' => {
9225 
            'attributes' => {
9226 
              'domain' => '',
9227 
              'group' => 1,
9228 
              'isClr' => 1,
9229 
              'is_floating_block' => 1,
9230 
              'period' => 1,
9231 
              'type' => 'logic',
9232 
              'valid_bit_used' => 0,
9233 
            },
9234 
            'direction' => 'out',
9235 
            'hdlType' => 'std_logic',
9236 
            'width' => 1,
9237 
          },
9238 
          'to_register12_data_in' => {
9239 
            'attributes' => {
9240 
              'bin_pt' => 0,
9241 
              'is_floating_block' => 1,
9242 
              'must_be_hdl_vector' => 1,
9243 
              'period' => 1,
9244 
              'port_id' => 0,
9245 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
9246 
              'type' => 'Bool',
9247 
            },
9248 
            'direction' => 'out',
9249 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9250 
            'width' => 1,
9251 
          },
9252 
          'to_register12_dout' => {
9253 
            'attributes' => {
9254 
              'bin_pt' => 0,
9255 
              'is_floating_block' => 1,
9256 
              'must_be_hdl_vector' => 1,
9257 
              'period' => 1,
9258 
              'port_id' => 0,
9259 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
9260 
              'type' => 'Bool',
9261 
            },
9262 
            'direction' => 'in',
9263 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9264 
            'width' => 1,
9265 
          },
9266 
          'to_register12_en' => {
9267 
            'attributes' => {
9268 
              'bin_pt' => 0,
9269 
              'is_floating_block' => 1,
9270 
              'must_be_hdl_vector' => 1,
9271 
              'period' => 1,
9272 
              'port_id' => 1,
9273 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
9274 
              'type' => 'Bool',
9275 
            },
9276 
            'direction' => 'out',
9277 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9278 
            'width' => 1,
9279 
          },
9280 
          'to_register13_ce' => {
9281 
            'attributes' => {
9282 
              'domain' => '',
9283 
              'group' => 1,
9284 
              'isCe' => 1,
9285 
              'is_floating_block' => 1,
9286 
              'period' => 1,
9287 
              'type' => 'logic',
9288 
            },
9289 
            'direction' => 'out',
9290 
            'hdlType' => 'std_logic',
9291 
            'width' => 1,
9292 
          },
9293 
          'to_register13_clk' => {
9294 
            'attributes' => {
9295 
              'domain' => '',
9296 
              'group' => 1,
9297 
              'isClk' => 1,
9298 
              'is_floating_block' => 1,
9299 
              'period' => 1,
9300 
              'type' => 'logic',
9301 
            },
9302 
            'direction' => 'out',
9303 
            'hdlType' => 'std_logic',
9304 
            'width' => 1,
9305 
          },
9306 
          'to_register13_clr' => {
9307 
            'attributes' => {
9308 
              'domain' => '',
9309 
              'group' => 1,
9310 
              'isClr' => 1,
9311 
              'is_floating_block' => 1,
9312 
              'period' => 1,
9313 
              'type' => 'logic',
9314 
              'valid_bit_used' => 0,
9315 
            },
9316 
            'direction' => 'out',
9317 
            'hdlType' => 'std_logic',
9318 
            'width' => 1,
9319 
          },
9320 
          'to_register13_data_in' => {
9321 
            'attributes' => {
9322 
              'bin_pt' => 0,
9323 
              'is_floating_block' => 1,
9324 
              'must_be_hdl_vector' => 1,
9325 
              'period' => 1,
9326 
              'port_id' => 0,
9327 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
9328 
              'type' => 'UFix_32_0',
9329 
            },
9330 
            'direction' => 'out',
9331 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9332 
            'width' => 32,
9333 
          },
9334 
          'to_register13_dout' => {
9335 
            'attributes' => {
9336 
              'bin_pt' => 0,
9337 
              'is_floating_block' => 1,
9338 
              'must_be_hdl_vector' => 1,
9339 
              'period' => 1,
9340 
              'port_id' => 0,
9341 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
9342 
              'type' => 'UFix_32_0',
9343 
            },
9344 
            'direction' => 'in',
9345 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9346 
            'width' => 32,
9347 
          },
9348 
          'to_register13_en' => {
9349 
            'attributes' => {
9350 
              'bin_pt' => 0,
9351 
              'is_floating_block' => 1,
9352 
              'must_be_hdl_vector' => 1,
9353 
              'period' => 1,
9354 
              'port_id' => 1,
9355 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
9356 
              'type' => 'Bool',
9357 
            },
9358 
            'direction' => 'out',
9359 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9360 
            'width' => 1,
9361 
          },
9362 
          'to_register14_ce' => {
9363 
            'attributes' => {
9364 
              'domain' => '',
9365 
              'group' => 1,
9366 
              'isCe' => 1,
9367 
              'is_floating_block' => 1,
9368 
              'period' => 1,
9369 
              'type' => 'logic',
9370 
            },
9371 
            'direction' => 'out',
9372 
            'hdlType' => 'std_logic',
9373 
            'width' => 1,
9374 
          },
9375 
          'to_register14_clk' => {
9376 
            'attributes' => {
9377 
              'domain' => '',
9378 
              'group' => 1,
9379 
              'isClk' => 1,
9380 
              'is_floating_block' => 1,
9381 
              'period' => 1,
9382 
              'type' => 'logic',
9383 
            },
9384 
            'direction' => 'out',
9385 
            'hdlType' => 'std_logic',
9386 
            'width' => 1,
9387 
          },
9388 
          'to_register14_clr' => {
9389 
            'attributes' => {
9390 
              'domain' => '',
9391 
              'group' => 1,
9392 
              'isClr' => 1,
9393 
              'is_floating_block' => 1,
9394 
              'period' => 1,
9395 
              'type' => 'logic',
9396 
              'valid_bit_used' => 0,
9397 
            },
9398 
            'direction' => 'out',
9399 
            'hdlType' => 'std_logic',
9400 
            'width' => 1,
9401 
          },
9402 
          'to_register14_data_in' => {
9403 
            'attributes' => {
9404 
              'bin_pt' => 0,
9405 
              'is_floating_block' => 1,
9406 
              'must_be_hdl_vector' => 1,
9407 
              'period' => 1,
9408 
              'port_id' => 0,
9409 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
9410 
              'type' => 'Bool',
9411 
            },
9412 
            'direction' => 'out',
9413 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9414 
            'width' => 1,
9415 
          },
9416 
          'to_register14_dout' => {
9417 
            'attributes' => {
9418 
              'bin_pt' => 0,
9419 
              'is_floating_block' => 1,
9420 
              'must_be_hdl_vector' => 1,
9421 
              'period' => 1,
9422 
              'port_id' => 0,
9423 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
9424 
              'type' => 'Bool',
9425 
            },
9426 
            'direction' => 'in',
9427 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9428 
            'width' => 1,
9429 
          },
9430 
          'to_register14_en' => {
9431 
            'attributes' => {
9432 
              'bin_pt' => 0,
9433 
              'is_floating_block' => 1,
9434 
              'must_be_hdl_vector' => 1,
9435 
              'period' => 1,
9436 
              'port_id' => 1,
9437 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
9438 
              'type' => 'Bool',
9439 
            },
9440 
            'direction' => 'out',
9441 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9442 
            'width' => 1,
9443 
          },
9444 
          'to_register15_ce' => {
9445 
            'attributes' => {
9446 
              'domain' => '',
9447 
              'group' => 1,
9448 
              'isCe' => 1,
9449 
              'is_floating_block' => 1,
9450 
              'period' => 1,
9451 
              'type' => 'logic',
9452 
            },
9453 
            'direction' => 'out',
9454 
            'hdlType' => 'std_logic',
9455 
            'width' => 1,
9456 
          },
9457 
          'to_register15_clk' => {
9458 
            'attributes' => {
9459 
              'domain' => '',
9460 
              'group' => 1,
9461 
              'isClk' => 1,
9462 
              'is_floating_block' => 1,
9463 
              'period' => 1,
9464 
              'type' => 'logic',
9465 
            },
9466 
            'direction' => 'out',
9467 
            'hdlType' => 'std_logic',
9468 
            'width' => 1,
9469 
          },
9470 
          'to_register15_clr' => {
9471 
            'attributes' => {
9472 
              'domain' => '',
9473 
              'group' => 1,
9474 
              'isClr' => 1,
9475 
              'is_floating_block' => 1,
9476 
              'period' => 1,
9477 
              'type' => 'logic',
9478 
              'valid_bit_used' => 0,
9479 
            },
9480 
            'direction' => 'out',
9481 
            'hdlType' => 'std_logic',
9482 
            'width' => 1,
9483 
          },
9484 
          'to_register15_data_in' => {
9485 
            'attributes' => {
9486 
              'bin_pt' => 0,
9487 
              'is_floating_block' => 1,
9488 
              'must_be_hdl_vector' => 1,
9489 
              'period' => 1,
9490 
              'port_id' => 0,
9491 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
9492 
              'type' => 'UFix_32_0',
9493 
            },
9494 
            'direction' => 'out',
9495 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9496 
            'width' => 32,
9497 
          },
9498 
          'to_register15_dout' => {
9499 
            'attributes' => {
9500 
              'bin_pt' => 0,
9501 
              'is_floating_block' => 1,
9502 
              'must_be_hdl_vector' => 1,
9503 
              'period' => 1,
9504 
              'port_id' => 0,
9505 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
9506 
              'type' => 'UFix_32_0',
9507 
            },
9508 
            'direction' => 'in',
9509 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9510 
            'width' => 32,
9511 
          },
9512 
          'to_register15_en' => {
9513 
            'attributes' => {
9514 
              'bin_pt' => 0,
9515 
              'is_floating_block' => 1,
9516 
              'must_be_hdl_vector' => 1,
9517 
              'period' => 1,
9518 
              'port_id' => 1,
9519 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
9520 
              'type' => 'Bool',
9521 
            },
9522 
            'direction' => 'out',
9523 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9524 
            'width' => 1,
9525 
          },
9526 
          'to_register16_ce' => {
9527 
            'attributes' => {
9528 
              'domain' => '',
9529 
              'group' => 1,
9530 
              'isCe' => 1,
9531 
              'is_floating_block' => 1,
9532 
              'period' => 1,
9533 
              'type' => 'logic',
9534 
            },
9535 
            'direction' => 'out',
9536 
            'hdlType' => 'std_logic',
9537 
            'width' => 1,
9538 
          },
9539 
          'to_register16_clk' => {
9540 
            'attributes' => {
9541 
              'domain' => '',
9542 
              'group' => 1,
9543 
              'isClk' => 1,
9544 
              'is_floating_block' => 1,
9545 
              'period' => 1,
9546 
              'type' => 'logic',
9547 
            },
9548 
            'direction' => 'out',
9549 
            'hdlType' => 'std_logic',
9550 
            'width' => 1,
9551 
          },
9552 
          'to_register16_clr' => {
9553 
            'attributes' => {
9554 
              'domain' => '',
9555 
              'group' => 1,
9556 
              'isClr' => 1,
9557 
              'is_floating_block' => 1,
9558 
              'period' => 1,
9559 
              'type' => 'logic',
9560 
              'valid_bit_used' => 0,
9561 
            },
9562 
            'direction' => 'out',
9563 
            'hdlType' => 'std_logic',
9564 
            'width' => 1,
9565 
          },
9566 
          'to_register16_data_in' => {
9567 
            'attributes' => {
9568 
              'bin_pt' => 0,
9569 
              'is_floating_block' => 1,
9570 
              'must_be_hdl_vector' => 1,
9571 
              'period' => 1,
9572 
              'port_id' => 0,
9573 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
9574 
              'type' => 'Bool',
9575 
            },
9576 
            'direction' => 'out',
9577 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9578 
            'width' => 1,
9579 
          },
9580 
          'to_register16_dout' => {
9581 
            'attributes' => {
9582 
              'bin_pt' => 0,
9583 
              'is_floating_block' => 1,
9584 
              'must_be_hdl_vector' => 1,
9585 
              'period' => 1,
9586 
              'port_id' => 0,
9587 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
9588 
              'type' => 'Bool',
9589 
            },
9590 
            'direction' => 'in',
9591 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9592 
            'width' => 1,
9593 
          },
9594 
          'to_register16_en' => {
9595 
            'attributes' => {
9596 
              'bin_pt' => 0,
9597 
              'is_floating_block' => 1,
9598 
              'must_be_hdl_vector' => 1,
9599 
              'period' => 1,
9600 
              'port_id' => 1,
9601 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
9602 
              'type' => 'Bool',
9603 
            },
9604 
            'direction' => 'out',
9605 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9606 
            'width' => 1,
9607 
          },
9608 
          'to_register17_ce' => {
9609 
            'attributes' => {
9610 
              'domain' => '',
9611 
              'group' => 1,
9612 
              'isCe' => 1,
9613 
              'is_floating_block' => 1,
9614 
              'period' => 1,
9615 
              'type' => 'logic',
9616 
            },
9617 
            'direction' => 'out',
9618 
            'hdlType' => 'std_logic',
9619 
            'width' => 1,
9620 
          },
9621 
          'to_register17_clk' => {
9622 
            'attributes' => {
9623 
              'domain' => '',
9624 
              'group' => 1,
9625 
              'isClk' => 1,
9626 
              'is_floating_block' => 1,
9627 
              'period' => 1,
9628 
              'type' => 'logic',
9629 
            },
9630 
            'direction' => 'out',
9631 
            'hdlType' => 'std_logic',
9632 
            'width' => 1,
9633 
          },
9634 
          'to_register17_clr' => {
9635 
            'attributes' => {
9636 
              'domain' => '',
9637 
              'group' => 1,
9638 
              'isClr' => 1,
9639 
              'is_floating_block' => 1,
9640 
              'period' => 1,
9641 
              'type' => 'logic',
9642 
              'valid_bit_used' => 0,
9643 
            },
9644 
            'direction' => 'out',
9645 
            'hdlType' => 'std_logic',
9646 
            'width' => 1,
9647 
          },
9648 
          'to_register17_data_in' => {
9649 
            'attributes' => {
9650 
              'bin_pt' => 0,
9651 
              'is_floating_block' => 1,
9652 
              'must_be_hdl_vector' => 1,
9653 
              'period' => 1,
9654 
              'port_id' => 0,
9655 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
9656 
              'type' => 'UFix_32_0',
9657 
            },
9658 
            'direction' => 'out',
9659 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9660 
            'width' => 32,
9661 
          },
9662 
          'to_register17_dout' => {
9663 
            'attributes' => {
9664 
              'bin_pt' => 0,
9665 
              'is_floating_block' => 1,
9666 
              'must_be_hdl_vector' => 1,
9667 
              'period' => 1,
9668 
              'port_id' => 0,
9669 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
9670 
              'type' => 'UFix_32_0',
9671 
            },
9672 
            'direction' => 'in',
9673 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9674 
            'width' => 32,
9675 
          },
9676 
          'to_register17_en' => {
9677 
            'attributes' => {
9678 
              'bin_pt' => 0,
9679 
              'is_floating_block' => 1,
9680 
              'must_be_hdl_vector' => 1,
9681 
              'period' => 1,
9682 
              'port_id' => 1,
9683 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
9684 
              'type' => 'Bool',
9685 
            },
9686 
            'direction' => 'out',
9687 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9688 
            'width' => 1,
9689 
          },
9690 
          'to_register18_ce' => {
9691 
            'attributes' => {
9692 
              'domain' => '',
9693 
              'group' => 1,
9694 
              'isCe' => 1,
9695 
              'is_floating_block' => 1,
9696 
              'period' => 1,
9697 
              'type' => 'logic',
9698 
            },
9699 
            'direction' => 'out',
9700 
            'hdlType' => 'std_logic',
9701 
            'width' => 1,
9702 
          },
9703 
          'to_register18_clk' => {
9704 
            'attributes' => {
9705 
              'domain' => '',
9706 
              'group' => 1,
9707 
              'isClk' => 1,
9708 
              'is_floating_block' => 1,
9709 
              'period' => 1,
9710 
              'type' => 'logic',
9711 
            },
9712 
            'direction' => 'out',
9713 
            'hdlType' => 'std_logic',
9714 
            'width' => 1,
9715 
          },
9716 
          'to_register18_clr' => {
9717 
            'attributes' => {
9718 
              'domain' => '',
9719 
              'group' => 1,
9720 
              'isClr' => 1,
9721 
              'is_floating_block' => 1,
9722 
              'period' => 1,
9723 
              'type' => 'logic',
9724 
              'valid_bit_used' => 0,
9725 
            },
9726 
            'direction' => 'out',
9727 
            'hdlType' => 'std_logic',
9728 
            'width' => 1,
9729 
          },
9730 
          'to_register18_data_in' => {
9731 
            'attributes' => {
9732 
              'bin_pt' => 0,
9733 
              'is_floating_block' => 1,
9734 
              'must_be_hdl_vector' => 1,
9735 
              'period' => 1,
9736 
              'port_id' => 0,
9737 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
9738 
              'type' => 'UFix_1_0',
9739 
            },
9740 
            'direction' => 'out',
9741 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9742 
            'width' => 1,
9743 
          },
9744 
          'to_register18_dout' => {
9745 
            'attributes' => {
9746 
              'bin_pt' => 0,
9747 
              'is_floating_block' => 1,
9748 
              'must_be_hdl_vector' => 1,
9749 
              'period' => 1,
9750 
              'port_id' => 0,
9751 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
9752 
              'type' => 'UFix_1_0',
9753 
            },
9754 
            'direction' => 'in',
9755 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9756 
            'width' => 1,
9757 
          },
9758 
          'to_register18_en' => {
9759 
            'attributes' => {
9760 
              'bin_pt' => 0,
9761 
              'is_floating_block' => 1,
9762 
              'must_be_hdl_vector' => 1,
9763 
              'period' => 1,
9764 
              'port_id' => 1,
9765 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
9766 
              'type' => 'Bool',
9767 
            },
9768 
            'direction' => 'out',
9769 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9770 
            'width' => 1,
9771 
          },
9772 
          'to_register19_ce' => {
9773 
            'attributes' => {
9774 
              'domain' => '',
9775 
              'group' => 1,
9776 
              'isCe' => 1,
9777 
              'is_floating_block' => 1,
9778 
              'period' => 1,
9779 
              'type' => 'logic',
9780 
            },
9781 
            'direction' => 'out',
9782 
            'hdlType' => 'std_logic',
9783 
            'width' => 1,
9784 
          },
9785 
          'to_register19_clk' => {
9786 
            'attributes' => {
9787 
              'domain' => '',
9788 
              'group' => 1,
9789 
              'isClk' => 1,
9790 
              'is_floating_block' => 1,
9791 
              'period' => 1,
9792 
              'type' => 'logic',
9793 
            },
9794 
            'direction' => 'out',
9795 
            'hdlType' => 'std_logic',
9796 
            'width' => 1,
9797 
          },
9798 
          'to_register19_clr' => {
9799 
            'attributes' => {
9800 
              'domain' => '',
9801 
              'group' => 1,
9802 
              'isClr' => 1,
9803 
              'is_floating_block' => 1,
9804 
              'period' => 1,
9805 
              'type' => 'logic',
9806 
              'valid_bit_used' => 0,
9807 
            },
9808 
            'direction' => 'out',
9809 
            'hdlType' => 'std_logic',
9810 
            'width' => 1,
9811 
          },
9812 
          'to_register19_data_in' => {
9813 
            'attributes' => {
9814 
              'bin_pt' => 0,
9815 
              'is_floating_block' => 1,
9816 
              'must_be_hdl_vector' => 1,
9817 
              'period' => 1,
9818 
              'port_id' => 0,
9819 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
9820 
              'type' => 'UFix_1_0',
9821 
            },
9822 
            'direction' => 'out',
9823 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9824 
            'width' => 1,
9825 
          },
9826 
          'to_register19_dout' => {
9827 
            'attributes' => {
9828 
              'bin_pt' => 0,
9829 
              'is_floating_block' => 1,
9830 
              'must_be_hdl_vector' => 1,
9831 
              'period' => 1,
9832 
              'port_id' => 0,
9833 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
9834 
              'type' => 'UFix_1_0',
9835 
            },
9836 
            'direction' => 'in',
9837 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9838 
            'width' => 1,
9839 
          },
9840 
          'to_register19_en' => {
9841 
            'attributes' => {
9842 
              'bin_pt' => 0,
9843 
              'is_floating_block' => 1,
9844 
              'must_be_hdl_vector' => 1,
9845 
              'period' => 1,
9846 
              'port_id' => 1,
9847 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
9848 
              'type' => 'Bool',
9849 
            },
9850 
            'direction' => 'out',
9851 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9852 
            'width' => 1,
9853 
          },
9854 
          'to_register1_ce' => {
9855 
            'attributes' => {
9856 
              'domain' => '',
9857 
              'group' => 1,
9858 
              'isCe' => 1,
9859 
              'is_floating_block' => 1,
9860 
              'period' => 1,
9861 
              'type' => 'logic',
9862 
            },
9863 
            'direction' => 'out',
9864 
            'hdlType' => 'std_logic',
9865 
            'width' => 1,
9866 
          },
9867 
          'to_register1_clk' => {
9868 
            'attributes' => {
9869 
              'domain' => '',
9870 
              'group' => 1,
9871 
              'isClk' => 1,
9872 
              'is_floating_block' => 1,
9873 
              'period' => 1,
9874 
              'type' => 'logic',
9875 
            },
9876 
            'direction' => 'out',
9877 
            'hdlType' => 'std_logic',
9878 
            'width' => 1,
9879 
          },
9880 
          'to_register1_clr' => {
9881 
            'attributes' => {
9882 
              'domain' => '',
9883 
              'group' => 1,
9884 
              'isClr' => 1,
9885 
              'is_floating_block' => 1,
9886 
              'period' => 1,
9887 
              'type' => 'logic',
9888 
              'valid_bit_used' => 0,
9889 
            },
9890 
            'direction' => 'out',
9891 
            'hdlType' => 'std_logic',
9892 
            'width' => 1,
9893 
          },
9894 
          'to_register1_data_in' => {
9895 
            'attributes' => {
9896 
              'bin_pt' => 0,
9897 
              'is_floating_block' => 1,
9898 
              'must_be_hdl_vector' => 1,
9899 
              'period' => 1,
9900 
              'port_id' => 0,
9901 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
9902 
              'type' => 'UFix_32_0',
9903 
            },
9904 
            'direction' => 'out',
9905 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9906 
            'width' => 32,
9907 
          },
9908 
          'to_register1_dout' => {
9909 
            'attributes' => {
9910 
              'bin_pt' => 0,
9911 
              'is_floating_block' => 1,
9912 
              'must_be_hdl_vector' => 1,
9913 
              'period' => 1,
9914 
              'port_id' => 0,
9915 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
9916 
              'type' => 'UFix_32_0',
9917 
            },
9918 
            'direction' => 'in',
9919 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9920 
            'width' => 32,
9921 
          },
9922 
          'to_register1_en' => {
9923 
            'attributes' => {
9924 
              'bin_pt' => 0,
9925 
              'is_floating_block' => 1,
9926 
              'must_be_hdl_vector' => 1,
9927 
              'period' => 1,
9928 
              'port_id' => 1,
9929 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
9930 
              'type' => 'Bool',
9931 
            },
9932 
            'direction' => 'out',
9933 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9934 
            'width' => 1,
9935 
          },
9936 
          'to_register20_ce' => {
9937 
            'attributes' => {
9938 
              'domain' => '',
9939 
              'group' => 1,
9940 
              'isCe' => 1,
9941 
              'is_floating_block' => 1,
9942 
              'period' => 1,
9943 
              'type' => 'logic',
9944 
            },
9945 
            'direction' => 'out',
9946 
            'hdlType' => 'std_logic',
9947 
            'width' => 1,
9948 
          },
9949 
          'to_register20_clk' => {
9950 
            'attributes' => {
9951 
              'domain' => '',
9952 
              'group' => 1,
9953 
              'isClk' => 1,
9954 
              'is_floating_block' => 1,
9955 
              'period' => 1,
9956 
              'type' => 'logic',
9957 
            },
9958 
            'direction' => 'out',
9959 
            'hdlType' => 'std_logic',
9960 
            'width' => 1,
9961 
          },
9962 
          'to_register20_clr' => {
9963 
            'attributes' => {
9964 
              'domain' => '',
9965 
              'group' => 1,
9966 
              'isClr' => 1,
9967 
              'is_floating_block' => 1,
9968 
              'period' => 1,
9969 
              'type' => 'logic',
9970 
              'valid_bit_used' => 0,
9971 
            },
9972 
            'direction' => 'out',
9973 
            'hdlType' => 'std_logic',
9974 
            'width' => 1,
9975 
          },
9976 
          'to_register20_data_in' => {
9977 
            'attributes' => {
9978 
              'bin_pt' => 0,
9979 
              'is_floating_block' => 1,
9980 
              'must_be_hdl_vector' => 1,
9981 
              'period' => 1,
9982 
              'port_id' => 0,
9983 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
9984 
              'type' => 'UFix_32_0',
9985 
            },
9986 
            'direction' => 'out',
9987 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9988 
            'width' => 32,
9989 
          },
9990 
          'to_register20_dout' => {
9991 
            'attributes' => {
9992 
              'bin_pt' => 0,
9993 
              'is_floating_block' => 1,
9994 
              'must_be_hdl_vector' => 1,
9995 
              'period' => 1,
9996 
              'port_id' => 0,
9997 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
9998 
              'type' => 'UFix_32_0',
9999 
            },
10000 
            'direction' => 'in',
10001 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10002 
            'width' => 32,
10003 
          },
10004 
          'to_register20_en' => {
10005 
            'attributes' => {
10006 
              'bin_pt' => 0,
10007 
              'is_floating_block' => 1,
10008 
              'must_be_hdl_vector' => 1,
10009 
              'period' => 1,
10010 
              'port_id' => 1,
10011 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
10012 
              'type' => 'Bool',
10013 
            },
10014 
            'direction' => 'out',
10015 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10016 
            'width' => 1,
10017 
          },
10018 
          'to_register21_ce' => {
10019 
            'attributes' => {
10020 
              'domain' => '',
10021 
              'group' => 1,
10022 
              'isCe' => 1,
10023 
              'is_floating_block' => 1,
10024 
              'period' => 1,
10025 
              'type' => 'logic',
10026 
            },
10027 
            'direction' => 'out',
10028 
            'hdlType' => 'std_logic',
10029 
            'width' => 1,
10030 
          },
10031 
          'to_register21_clk' => {
10032 
            'attributes' => {
10033 
              'domain' => '',
10034 
              'group' => 1,
10035 
              'isClk' => 1,
10036 
              'is_floating_block' => 1,
10037 
              'period' => 1,
10038 
              'type' => 'logic',
10039 
            },
10040 
            'direction' => 'out',
10041 
            'hdlType' => 'std_logic',
10042 
            'width' => 1,
10043 
          },
10044 
          'to_register21_clr' => {
10045 
            'attributes' => {
10046 
              'domain' => '',
10047 
              'group' => 1,
10048 
              'isClr' => 1,
10049 
              'is_floating_block' => 1,
10050 
              'period' => 1,
10051 
              'type' => 'logic',
10052 
              'valid_bit_used' => 0,
10053 
            },
10054 
            'direction' => 'out',
10055 
            'hdlType' => 'std_logic',
10056 
            'width' => 1,
10057 
          },
10058 
          'to_register21_data_in' => {
10059 
            'attributes' => {
10060 
              'bin_pt' => 0,
10061 
              'is_floating_block' => 1,
10062 
              'must_be_hdl_vector' => 1,
10063 
              'period' => 1,
10064 
              'port_id' => 0,
10065 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
10066 
              'type' => 'Bool',
10067 
            },
10068 
            'direction' => 'out',
10069 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10070 
            'width' => 1,
10071 
          },
10072 
          'to_register21_dout' => {
10073 
            'attributes' => {
10074 
              'bin_pt' => 0,
10075 
              'is_floating_block' => 1,
10076 
              'must_be_hdl_vector' => 1,
10077 
              'period' => 1,
10078 
              'port_id' => 0,
10079 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
10080 
              'type' => 'Bool',
10081 
            },
10082 
            'direction' => 'in',
10083 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10084 
            'width' => 1,
10085 
          },
10086 
          'to_register21_en' => {
10087 
            'attributes' => {
10088 
              'bin_pt' => 0,
10089 
              'is_floating_block' => 1,
10090 
              'must_be_hdl_vector' => 1,
10091 
              'period' => 1,
10092 
              'port_id' => 1,
10093 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
10094 
              'type' => 'Bool',
10095 
            },
10096 
            'direction' => 'out',
10097 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10098 
            'width' => 1,
10099 
          },
10100 
          'to_register22_ce' => {
10101 
            'attributes' => {
10102 
              'domain' => '',
10103 
              'group' => 1,
10104 
              'isCe' => 1,
10105 
              'is_floating_block' => 1,
10106 
              'period' => 1,
10107 
              'type' => 'logic',
10108 
            },
10109 
            'direction' => 'out',
10110 
            'hdlType' => 'std_logic',
10111 
            'width' => 1,
10112 
          },
10113 
          'to_register22_clk' => {
10114 
            'attributes' => {
10115 
              'domain' => '',
10116 
              'group' => 1,
10117 
              'isClk' => 1,
10118 
              'is_floating_block' => 1,
10119 
              'period' => 1,
10120 
              'type' => 'logic',
10121 
            },
10122 
            'direction' => 'out',
10123 
            'hdlType' => 'std_logic',
10124 
            'width' => 1,
10125 
          },
10126 
          'to_register22_clr' => {
10127 
            'attributes' => {
10128 
              'domain' => '',
10129 
              'group' => 1,
10130 
              'isClr' => 1,
10131 
              'is_floating_block' => 1,
10132 
              'period' => 1,
10133 
              'type' => 'logic',
10134 
              'valid_bit_used' => 0,
10135 
            },
10136 
            'direction' => 'out',
10137 
            'hdlType' => 'std_logic',
10138 
            'width' => 1,
10139 
          },
10140 
          'to_register22_data_in' => {
10141 
            'attributes' => {
10142 
              'bin_pt' => 0,
10143 
              'is_floating_block' => 1,
10144 
              'must_be_hdl_vector' => 1,
10145 
              'period' => 1,
10146 
              'port_id' => 0,
10147 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
10148 
              'type' => 'UFix_32_0',
10149 
            },
10150 
            'direction' => 'out',
10151 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10152 
            'width' => 32,
10153 
          },
10154 
          'to_register22_dout' => {
10155 
            'attributes' => {
10156 
              'bin_pt' => 0,
10157 
              'is_floating_block' => 1,
10158 
              'must_be_hdl_vector' => 1,
10159 
              'period' => 1,
10160 
              'port_id' => 0,
10161 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
10162 
              'type' => 'UFix_32_0',
10163 
            },
10164 
            'direction' => 'in',
10165 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10166 
            'width' => 32,
10167 
          },
10168 
          'to_register22_en' => {
10169 
            'attributes' => {
10170 
              'bin_pt' => 0,
10171 
              'is_floating_block' => 1,
10172 
              'must_be_hdl_vector' => 1,
10173 
              'period' => 1,
10174 
              'port_id' => 1,
10175 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
10176 
              'type' => 'Bool',
10177 
            },
10178 
            'direction' => 'out',
10179 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10180 
            'width' => 1,
10181 
          },
10182 
          'to_register23_ce' => {
10183 
            'attributes' => {
10184 
              'domain' => '',
10185 
              'group' => 1,
10186 
              'isCe' => 1,
10187 
              'is_floating_block' => 1,
10188 
              'period' => 1,
10189 
              'type' => 'logic',
10190 
            },
10191 
            'direction' => 'out',
10192 
            'hdlType' => 'std_logic',
10193 
            'width' => 1,
10194 
          },
10195 
          'to_register23_clk' => {
10196 
            'attributes' => {
10197 
              'domain' => '',
10198 
              'group' => 1,
10199 
              'isClk' => 1,
10200 
              'is_floating_block' => 1,
10201 
              'period' => 1,
10202 
              'type' => 'logic',
10203 
            },
10204 
            'direction' => 'out',
10205 
            'hdlType' => 'std_logic',
10206 
            'width' => 1,
10207 
          },
10208 
          'to_register23_clr' => {
10209 
            'attributes' => {
10210 
              'domain' => '',
10211 
              'group' => 1,
10212 
              'isClr' => 1,
10213 
              'is_floating_block' => 1,
10214 
              'period' => 1,
10215 
              'type' => 'logic',
10216 
              'valid_bit_used' => 0,
10217 
            },
10218 
            'direction' => 'out',
10219 
            'hdlType' => 'std_logic',
10220 
            'width' => 1,
10221 
          },
10222 
          'to_register23_data_in' => {
10223 
            'attributes' => {
10224 
              'bin_pt' => 0,
10225 
              'is_floating_block' => 1,
10226 
              'must_be_hdl_vector' => 1,
10227 
              'period' => 1,
10228 
              'port_id' => 0,
10229 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
10230 
              'type' => 'Bool',
10231 
            },
10232 
            'direction' => 'out',
10233 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10234 
            'width' => 1,
10235 
          },
10236 
          'to_register23_dout' => {
10237 
            'attributes' => {
10238 
              'bin_pt' => 0,
10239 
              'is_floating_block' => 1,
10240 
              'must_be_hdl_vector' => 1,
10241 
              'period' => 1,
10242 
              'port_id' => 0,
10243 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
10244 
              'type' => 'Bool',
10245 
            },
10246 
            'direction' => 'in',
10247 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10248 
            'width' => 1,
10249 
          },
10250 
          'to_register23_en' => {
10251 
            'attributes' => {
10252 
              'bin_pt' => 0,
10253 
              'is_floating_block' => 1,
10254 
              'must_be_hdl_vector' => 1,
10255 
              'period' => 1,
10256 
              'port_id' => 1,
10257 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
10258 
              'type' => 'Bool',
10259 
            },
10260 
            'direction' => 'out',
10261 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10262 
            'width' => 1,
10263 
          },
10264 
          'to_register24_ce' => {
10265 
            'attributes' => {
10266 
              'domain' => '',
10267 
              'group' => 1,
10268 
              'isCe' => 1,
10269 
              'is_floating_block' => 1,
10270 
              'period' => 1,
10271 
              'type' => 'logic',
10272 
            },
10273 
            'direction' => 'out',
10274 
            'hdlType' => 'std_logic',
10275 
            'width' => 1,
10276 
          },
10277 
          'to_register24_clk' => {
10278 
            'attributes' => {
10279 
              'domain' => '',
10280 
              'group' => 1,
10281 
              'isClk' => 1,
10282 
              'is_floating_block' => 1,
10283 
              'period' => 1,
10284 
              'type' => 'logic',
10285 
            },
10286 
            'direction' => 'out',
10287 
            'hdlType' => 'std_logic',
10288 
            'width' => 1,
10289 
          },
10290 
          'to_register24_clr' => {
10291 
            'attributes' => {
10292 
              'domain' => '',
10293 
              'group' => 1,
10294 
              'isClr' => 1,
10295 
              'is_floating_block' => 1,
10296 
              'period' => 1,
10297 
              'type' => 'logic',
10298 
              'valid_bit_used' => 0,
10299 
            },
10300 
            'direction' => 'out',
10301 
            'hdlType' => 'std_logic',
10302 
            'width' => 1,
10303 
          },
10304 
          'to_register24_data_in' => {
10305 
            'attributes' => {
10306 
              'bin_pt' => 0,
10307 
              'is_floating_block' => 1,
10308 
              'must_be_hdl_vector' => 1,
10309 
              'period' => 1,
10310 
              'port_id' => 0,
10311 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
10312 
              'type' => 'UFix_32_0',
10313 
            },
10314 
            'direction' => 'out',
10315 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10316 
            'width' => 32,
10317 
          },
10318 
          'to_register24_dout' => {
10319 
            'attributes' => {
10320 
              'bin_pt' => 0,
10321 
              'is_floating_block' => 1,
10322 
              'must_be_hdl_vector' => 1,
10323 
              'period' => 1,
10324 
              'port_id' => 0,
10325 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
10326 
              'type' => 'UFix_32_0',
10327 
            },
10328 
            'direction' => 'in',
10329 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10330 
            'width' => 32,
10331 
          },
10332 
          'to_register24_en' => {
10333 
            'attributes' => {
10334 
              'bin_pt' => 0,
10335 
              'is_floating_block' => 1,
10336 
              'must_be_hdl_vector' => 1,
10337 
              'period' => 1,
10338 
              'port_id' => 1,
10339 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
10340 
              'type' => 'Bool',
10341 
            },
10342 
            'direction' => 'out',
10343 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10344 
            'width' => 1,
10345 
          },
10346 
          'to_register25_ce' => {
10347 
            'attributes' => {
10348 
              'domain' => '',
10349 
              'group' => 1,
10350 
              'isCe' => 1,
10351 
              'is_floating_block' => 1,
10352 
              'period' => 1,
10353 
              'type' => 'logic',
10354 
            },
10355 
            'direction' => 'out',
10356 
            'hdlType' => 'std_logic',
10357 
            'width' => 1,
10358 
          },
10359 
          'to_register25_clk' => {
10360 
            'attributes' => {
10361 
              'domain' => '',
10362 
              'group' => 1,
10363 
              'isClk' => 1,
10364 
              'is_floating_block' => 1,
10365 
              'period' => 1,
10366 
              'type' => 'logic',
10367 
            },
10368 
            'direction' => 'out',
10369 
            'hdlType' => 'std_logic',
10370 
            'width' => 1,
10371 
          },
10372 
          'to_register25_clr' => {
10373 
            'attributes' => {
10374 
              'domain' => '',
10375 
              'group' => 1,
10376 
              'isClr' => 1,
10377 
              'is_floating_block' => 1,
10378 
              'period' => 1,
10379 
              'type' => 'logic',
10380 
              'valid_bit_used' => 0,
10381 
            },
10382 
            'direction' => 'out',
10383 
            'hdlType' => 'std_logic',
10384 
            'width' => 1,
10385 
          },
10386 
          'to_register25_data_in' => {
10387 
            'attributes' => {
10388 
              'bin_pt' => 0,
10389 
              'is_floating_block' => 1,
10390 
              'must_be_hdl_vector' => 1,
10391 
              'period' => 1,
10392 
              'port_id' => 0,
10393 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
10394 
              'type' => 'Bool',
10395 
            },
10396 
            'direction' => 'out',
10397 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10398 
            'width' => 1,
10399 
          },
10400 
          'to_register25_dout' => {
10401 
            'attributes' => {
10402 
              'bin_pt' => 0,
10403 
              'is_floating_block' => 1,
10404 
              'must_be_hdl_vector' => 1,
10405 
              'period' => 1,
10406 
              'port_id' => 0,
10407 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
10408 
              'type' => 'Bool',
10409 
            },
10410 
            'direction' => 'in',
10411 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10412 
            'width' => 1,
10413 
          },
10414 
          'to_register25_en' => {
10415 
            'attributes' => {
10416 
              'bin_pt' => 0,
10417 
              'is_floating_block' => 1,
10418 
              'must_be_hdl_vector' => 1,
10419 
              'period' => 1,
10420 
              'port_id' => 1,
10421 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
10422 
              'type' => 'Bool',
10423 
            },
10424 
            'direction' => 'out',
10425 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10426 
            'width' => 1,
10427 
          },
10428 
          'to_register26_ce' => {
10429 
            'attributes' => {
10430 
              'domain' => '',
10431 
              'group' => 1,
10432 
              'isCe' => 1,
10433 
              'is_floating_block' => 1,
10434 
              'period' => 1,
10435 
              'type' => 'logic',
10436 
            },
10437 
            'direction' => 'out',
10438 
            'hdlType' => 'std_logic',
10439 
            'width' => 1,
10440 
          },
10441 
          'to_register26_clk' => {
10442 
            'attributes' => {
10443 
              'domain' => '',
10444 
              'group' => 1,
10445 
              'isClk' => 1,
10446 
              'is_floating_block' => 1,
10447 
              'period' => 1,
10448 
              'type' => 'logic',
10449 
            },
10450 
            'direction' => 'out',
10451 
            'hdlType' => 'std_logic',
10452 
            'width' => 1,
10453 
          },
10454 
          'to_register26_clr' => {
10455 
            'attributes' => {
10456 
              'domain' => '',
10457 
              'group' => 1,
10458 
              'isClr' => 1,
10459 
              'is_floating_block' => 1,
10460 
              'period' => 1,
10461 
              'type' => 'logic',
10462 
              'valid_bit_used' => 0,
10463 
            },
10464 
            'direction' => 'out',
10465 
            'hdlType' => 'std_logic',
10466 
            'width' => 1,
10467 
          },
10468 
          'to_register26_data_in' => {
10469 
            'attributes' => {
10470 
              'bin_pt' => 0,
10471 
              'is_floating_block' => 1,
10472 
              'must_be_hdl_vector' => 1,
10473 
              'period' => 1,
10474 
              'port_id' => 0,
10475 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
10476 
              'type' => 'UFix_32_0',
10477 
            },
10478 
            'direction' => 'out',
10479 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10480 
            'width' => 32,
10481 
          },
10482 
          'to_register26_dout' => {
10483 
            'attributes' => {
10484 
              'bin_pt' => 0,
10485 
              'is_floating_block' => 1,
10486 
              'must_be_hdl_vector' => 1,
10487 
              'period' => 1,
10488 
              'port_id' => 0,
10489 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
10490 
              'type' => 'UFix_32_0',
10491 
            },
10492 
            'direction' => 'in',
10493 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10494 
            'width' => 32,
10495 
          },
10496 
          'to_register26_en' => {
10497 
            'attributes' => {
10498 
              'bin_pt' => 0,
10499 
              'is_floating_block' => 1,
10500 
              'must_be_hdl_vector' => 1,
10501 
              'period' => 1,
10502 
              'port_id' => 1,
10503 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
10504 
              'type' => 'Bool',
10505 
            },
10506 
            'direction' => 'out',
10507 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10508 
            'width' => 1,
10509 
          },
10510 
          'to_register27_ce' => {
10511 
            'attributes' => {
10512 
              'domain' => '',
10513 
              'group' => 1,
10514 
              'isCe' => 1,
10515 
              'is_floating_block' => 1,
10516 
              'period' => 1,
10517 
              'type' => 'logic',
10518 
            },
10519 
            'direction' => 'out',
10520 
            'hdlType' => 'std_logic',
10521 
            'width' => 1,
10522 
          },
10523 
          'to_register27_clk' => {
10524 
            'attributes' => {
10525 
              'domain' => '',
10526 
              'group' => 1,
10527 
              'isClk' => 1,
10528 
              'is_floating_block' => 1,
10529 
              'period' => 1,
10530 
              'type' => 'logic',
10531 
            },
10532 
            'direction' => 'out',
10533 
            'hdlType' => 'std_logic',
10534 
            'width' => 1,
10535 
          },
10536 
          'to_register27_clr' => {
10537 
            'attributes' => {
10538 
              'domain' => '',
10539 
              'group' => 1,
10540 
              'isClr' => 1,
10541 
              'is_floating_block' => 1,
10542 
              'period' => 1,
10543 
              'type' => 'logic',
10544 
              'valid_bit_used' => 0,
10545 
            },
10546 
            'direction' => 'out',
10547 
            'hdlType' => 'std_logic',
10548 
            'width' => 1,
10549 
          },
10550 
          'to_register27_data_in' => {
10551 
            'attributes' => {
10552 
              'bin_pt' => 0,
10553 
              'is_floating_block' => 1,
10554 
              'must_be_hdl_vector' => 1,
10555 
              'period' => 1,
10556 
              'port_id' => 0,
10557 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
10558 
              'type' => 'Bool',
10559 
            },
10560 
            'direction' => 'out',
10561 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10562 
            'width' => 1,
10563 
          },
10564 
          'to_register27_dout' => {
10565 
            'attributes' => {
10566 
              'bin_pt' => 0,
10567 
              'is_floating_block' => 1,
10568 
              'must_be_hdl_vector' => 1,
10569 
              'period' => 1,
10570 
              'port_id' => 0,
10571 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
10572 
              'type' => 'Bool',
10573 
            },
10574 
            'direction' => 'in',
10575 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10576 
            'width' => 1,
10577 
          },
10578 
          'to_register27_en' => {
10579 
            'attributes' => {
10580 
              'bin_pt' => 0,
10581 
              'is_floating_block' => 1,
10582 
              'must_be_hdl_vector' => 1,
10583 
              'period' => 1,
10584 
              'port_id' => 1,
10585 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
10586 
              'type' => 'Bool',
10587 
            },
10588 
            'direction' => 'out',
10589 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10590 
            'width' => 1,
10591 
          },
10592 
          'to_register28_ce' => {
10593 
            'attributes' => {
10594 
              'domain' => '',
10595 
              'group' => 1,
10596 
              'isCe' => 1,
10597 
              'is_floating_block' => 1,
10598 
              'period' => 1,
10599 
              'type' => 'logic',
10600 
            },
10601 
            'direction' => 'out',
10602 
            'hdlType' => 'std_logic',
10603 
            'width' => 1,
10604 
          },
10605 
          'to_register28_clk' => {
10606 
            'attributes' => {
10607 
              'domain' => '',
10608 
              'group' => 1,
10609 
              'isClk' => 1,
10610 
              'is_floating_block' => 1,
10611 
              'period' => 1,
10612 
              'type' => 'logic',
10613 
            },
10614 
            'direction' => 'out',
10615 
            'hdlType' => 'std_logic',
10616 
            'width' => 1,
10617 
          },
10618 
          'to_register28_clr' => {
10619 
            'attributes' => {
10620 
              'domain' => '',
10621 
              'group' => 1,
10622 
              'isClr' => 1,
10623 
              'is_floating_block' => 1,
10624 
              'period' => 1,
10625 
              'type' => 'logic',
10626 
              'valid_bit_used' => 0,
10627 
            },
10628 
            'direction' => 'out',
10629 
            'hdlType' => 'std_logic',
10630 
            'width' => 1,
10631 
          },
10632 
          'to_register28_data_in' => {
10633 
            'attributes' => {
10634 
              'bin_pt' => 0,
10635 
              'is_floating_block' => 1,
10636 
              'must_be_hdl_vector' => 1,
10637 
              'period' => 1,
10638 
              'port_id' => 0,
10639 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
10640 
              'type' => 'UFix_32_0',
10641 
            },
10642 
            'direction' => 'out',
10643 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10644 
            'width' => 32,
10645 
          },
10646 
          'to_register28_dout' => {
10647 
            'attributes' => {
10648 
              'bin_pt' => 0,
10649 
              'is_floating_block' => 1,
10650 
              'must_be_hdl_vector' => 1,
10651 
              'period' => 1,
10652 
              'port_id' => 0,
10653 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
10654 
              'type' => 'UFix_32_0',
10655 
            },
10656 
            'direction' => 'in',
10657 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10658 
            'width' => 32,
10659 
          },
10660 
          'to_register28_en' => {
10661 
            'attributes' => {
10662 
              'bin_pt' => 0,
10663 
              'is_floating_block' => 1,
10664 
              'must_be_hdl_vector' => 1,
10665 
              'period' => 1,
10666 
              'port_id' => 1,
10667 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
10668 
              'type' => 'Bool',
10669 
            },
10670 
            'direction' => 'out',
10671 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10672 
            'width' => 1,
10673 
          },
10674 
          'to_register29_ce' => {
10675 
            'attributes' => {
10676 
              'domain' => '',
10677 
              'group' => 1,
10678 
              'isCe' => 1,
10679 
              'is_floating_block' => 1,
10680 
              'period' => 1,
10681 
              'type' => 'logic',
10682 
            },
10683 
            'direction' => 'out',
10684 
            'hdlType' => 'std_logic',
10685 
            'width' => 1,
10686 
          },
10687 
          'to_register29_clk' => {
10688 
            'attributes' => {
10689 
              'domain' => '',
10690 
              'group' => 1,
10691 
              'isClk' => 1,
10692 
              'is_floating_block' => 1,
10693 
              'period' => 1,
10694 
              'type' => 'logic',
10695 
            },
10696 
            'direction' => 'out',
10697 
            'hdlType' => 'std_logic',
10698 
            'width' => 1,
10699 
          },
10700 
          'to_register29_clr' => {
10701 
            'attributes' => {
10702 
              'domain' => '',
10703 
              'group' => 1,
10704 
              'isClr' => 1,
10705 
              'is_floating_block' => 1,
10706 
              'period' => 1,
10707 
              'type' => 'logic',
10708 
              'valid_bit_used' => 0,
10709 
            },
10710 
            'direction' => 'out',
10711 
            'hdlType' => 'std_logic',
10712 
            'width' => 1,
10713 
          },
10714 
          'to_register29_data_in' => {
10715 
            'attributes' => {
10716 
              'bin_pt' => 0,
10717 
              'is_floating_block' => 1,
10718 
              'must_be_hdl_vector' => 1,
10719 
              'period' => 1,
10720 
              'port_id' => 0,
10721 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
10722 
              'type' => 'Bool',
10723 
            },
10724 
            'direction' => 'out',
10725 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10726 
            'width' => 1,
10727 
          },
10728 
          'to_register29_dout' => {
10729 
            'attributes' => {
10730 
              'bin_pt' => 0,
10731 
              'is_floating_block' => 1,
10732 
              'must_be_hdl_vector' => 1,
10733 
              'period' => 1,
10734 
              'port_id' => 0,
10735 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
10736 
              'type' => 'Bool',
10737 
            },
10738 
            'direction' => 'in',
10739 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10740 
            'width' => 1,
10741 
          },
10742 
          'to_register29_en' => {
10743 
            'attributes' => {
10744 
              'bin_pt' => 0,
10745 
              'is_floating_block' => 1,
10746 
              'must_be_hdl_vector' => 1,
10747 
              'period' => 1,
10748 
              'port_id' => 1,
10749 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
10750 
              'type' => 'Bool',
10751 
            },
10752 
            'direction' => 'out',
10753 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10754 
            'width' => 1,
10755 
          },
10756 
          'to_register2_ce' => {
10757 
            'attributes' => {
10758 
              'domain' => '',
10759 
              'group' => 1,
10760 
              'isCe' => 1,
10761 
              'is_floating_block' => 1,
10762 
              'period' => 1,
10763 
              'type' => 'logic',
10764 
            },
10765 
            'direction' => 'out',
10766 
            'hdlType' => 'std_logic',
10767 
            'width' => 1,
10768 
          },
10769 
          'to_register2_clk' => {
10770 
            'attributes' => {
10771 
              'domain' => '',
10772 
              'group' => 1,
10773 
              'isClk' => 1,
10774 
              'is_floating_block' => 1,
10775 
              'period' => 1,
10776 
              'type' => 'logic',
10777 
            },
10778 
            'direction' => 'out',
10779 
            'hdlType' => 'std_logic',
10780 
            'width' => 1,
10781 
          },
10782 
          'to_register2_clr' => {
10783 
            'attributes' => {
10784 
              'domain' => '',
10785 
              'group' => 1,
10786 
              'isClr' => 1,
10787 
              'is_floating_block' => 1,
10788 
              'period' => 1,
10789 
              'type' => 'logic',
10790 
              'valid_bit_used' => 0,
10791 
            },
10792 
            'direction' => 'out',
10793 
            'hdlType' => 'std_logic',
10794 
            'width' => 1,
10795 
          },
10796 
          'to_register2_data_in' => {
10797 
            'attributes' => {
10798 
              'bin_pt' => 0,
10799 
              'is_floating_block' => 1,
10800 
              'must_be_hdl_vector' => 1,
10801 
              'period' => 1,
10802 
              'port_id' => 0,
10803 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
10804 
              'type' => 'UFix_32_0',
10805 
            },
10806 
            'direction' => 'out',
10807 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10808 
            'width' => 32,
10809 
          },
10810 
          'to_register2_dout' => {
10811 
            'attributes' => {
10812 
              'bin_pt' => 0,
10813 
              'is_floating_block' => 1,
10814 
              'must_be_hdl_vector' => 1,
10815 
              'period' => 1,
10816 
              'port_id' => 0,
10817 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
10818 
              'type' => 'UFix_32_0',
10819 
            },
10820 
            'direction' => 'in',
10821 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10822 
            'width' => 32,
10823 
          },
10824 
          'to_register2_en' => {
10825 
            'attributes' => {
10826 
              'bin_pt' => 0,
10827 
              'is_floating_block' => 1,
10828 
              'must_be_hdl_vector' => 1,
10829 
              'period' => 1,
10830 
              'port_id' => 1,
10831 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
10832 
              'type' => 'Bool',
10833 
            },
10834 
            'direction' => 'out',
10835 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10836 
            'width' => 1,
10837 
          },
10838 
          'to_register30_ce' => {
10839 
            'attributes' => {
10840 
              'domain' => '',
10841 
              'group' => 1,
10842 
              'isCe' => 1,
10843 
              'is_floating_block' => 1,
10844 
              'period' => 1,
10845 
              'type' => 'logic',
10846 
            },
10847 
            'direction' => 'out',
10848 
            'hdlType' => 'std_logic',
10849 
            'width' => 1,
10850 
          },
10851 
          'to_register30_clk' => {
10852 
            'attributes' => {
10853 
              'domain' => '',
10854 
              'group' => 1,
10855 
              'isClk' => 1,
10856 
              'is_floating_block' => 1,
10857 
              'period' => 1,
10858 
              'type' => 'logic',
10859 
            },
10860 
            'direction' => 'out',
10861 
            'hdlType' => 'std_logic',
10862 
            'width' => 1,
10863 
          },
10864 
          'to_register30_clr' => {
10865 
            'attributes' => {
10866 
              'domain' => '',
10867 
              'group' => 1,
10868 
              'isClr' => 1,
10869 
              'is_floating_block' => 1,
10870 
              'period' => 1,
10871 
              'type' => 'logic',
10872 
              'valid_bit_used' => 0,
10873 
            },
10874 
            'direction' => 'out',
10875 
            'hdlType' => 'std_logic',
10876 
            'width' => 1,
10877 
          },
10878 
          'to_register30_data_in' => {
10879 
            'attributes' => {
10880 
              'bin_pt' => 0,
10881 
              'is_floating_block' => 1,
10882 
              'must_be_hdl_vector' => 1,
10883 
              'period' => 1,
10884 
              'port_id' => 0,
10885 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
10886 
              'type' => 'UFix_32_0',
10887 
            },
10888 
            'direction' => 'out',
10889 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10890 
            'width' => 32,
10891 
          },
10892 
          'to_register30_dout' => {
10893 
            'attributes' => {
10894 
              'bin_pt' => 0,
10895 
              'is_floating_block' => 1,
10896 
              'must_be_hdl_vector' => 1,
10897 
              'period' => 1,
10898 
              'port_id' => 0,
10899 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
10900 
              'type' => 'UFix_32_0',
10901 
            },
10902 
            'direction' => 'in',
10903 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10904 
            'width' => 32,
10905 
          },
10906 
          'to_register30_en' => {
10907 
            'attributes' => {
10908 
              'bin_pt' => 0,
10909 
              'is_floating_block' => 1,
10910 
              'must_be_hdl_vector' => 1,
10911 
              'period' => 1,
10912 
              'port_id' => 1,
10913 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
10914 
              'type' => 'Bool',
10915 
            },
10916 
            'direction' => 'out',
10917 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10918 
            'width' => 1,
10919 
          },
10920 
          'to_register31_ce' => {
10921 
            'attributes' => {
10922 
              'domain' => '',
10923 
              'group' => 1,
10924 
              'isCe' => 1,
10925 
              'is_floating_block' => 1,
10926 
              'period' => 1,
10927 
              'type' => 'logic',
10928 
            },
10929 
            'direction' => 'out',
10930 
            'hdlType' => 'std_logic',
10931 
            'width' => 1,
10932 
          },
10933 
          'to_register31_clk' => {
10934 
            'attributes' => {
10935 
              'domain' => '',
10936 
              'group' => 1,
10937 
              'isClk' => 1,
10938 
              'is_floating_block' => 1,
10939 
              'period' => 1,
10940 
              'type' => 'logic',
10941 
            },
10942 
            'direction' => 'out',
10943 
            'hdlType' => 'std_logic',
10944 
            'width' => 1,
10945 
          },
10946 
          'to_register31_clr' => {
10947 
            'attributes' => {
10948 
              'domain' => '',
10949 
              'group' => 1,
10950 
              'isClr' => 1,
10951 
              'is_floating_block' => 1,
10952 
              'period' => 1,
10953 
              'type' => 'logic',
10954 
              'valid_bit_used' => 0,
10955 
            },
10956 
            'direction' => 'out',
10957 
            'hdlType' => 'std_logic',
10958 
            'width' => 1,
10959 
          },
10960 
          'to_register31_data_in' => {
10961 
            'attributes' => {
10962 
              'bin_pt' => 0,
10963 
              'is_floating_block' => 1,
10964 
              'must_be_hdl_vector' => 1,
10965 
              'period' => 1,
10966 
              'port_id' => 0,
10967 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
10968 
              'type' => 'Bool',
10969 
            },
10970 
            'direction' => 'out',
10971 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10972 
            'width' => 1,
10973 
          },
10974 
          'to_register31_dout' => {
10975 
            'attributes' => {
10976 
              'bin_pt' => 0,
10977 
              'is_floating_block' => 1,
10978 
              'must_be_hdl_vector' => 1,
10979 
              'period' => 1,
10980 
              'port_id' => 0,
10981 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
10982 
              'type' => 'Bool',
10983 
            },
10984 
            'direction' => 'in',
10985 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10986 
            'width' => 1,
10987 
          },
10988 
          'to_register31_en' => {
10989 
            'attributes' => {
10990 
              'bin_pt' => 0,
10991 
              'is_floating_block' => 1,
10992 
              'must_be_hdl_vector' => 1,
10993 
              'period' => 1,
10994 
              'port_id' => 1,
10995 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
10996 
              'type' => 'Bool',
10997 
            },
10998 
            'direction' => 'out',
10999 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11000 
            'width' => 1,
11001 
          },
11002 
          'to_register32_ce' => {
11003 
            'attributes' => {
11004 
              'domain' => '',
11005 
              'group' => 1,
11006 
              'isCe' => 1,
11007 
              'is_floating_block' => 1,
11008 
              'period' => 1,
11009 
              'type' => 'logic',
11010 
            },
11011 
            'direction' => 'out',
11012 
            'hdlType' => 'std_logic',
11013 
            'width' => 1,
11014 
          },
11015 
          'to_register32_clk' => {
11016 
            'attributes' => {
11017 
              'domain' => '',
11018 
              'group' => 1,
11019 
              'isClk' => 1,
11020 
              'is_floating_block' => 1,
11021 
              'period' => 1,
11022 
              'type' => 'logic',
11023 
            },
11024 
            'direction' => 'out',
11025 
            'hdlType' => 'std_logic',
11026 
            'width' => 1,
11027 
          },
11028 
          'to_register32_clr' => {
11029 
            'attributes' => {
11030 
              'domain' => '',
11031 
              'group' => 1,
11032 
              'isClr' => 1,
11033 
              'is_floating_block' => 1,
11034 
              'period' => 1,
11035 
              'type' => 'logic',
11036 
              'valid_bit_used' => 0,
11037 
            },
11038 
            'direction' => 'out',
11039 
            'hdlType' => 'std_logic',
11040 
            'width' => 1,
11041 
          },
11042 
          'to_register32_data_in' => {
11043 
            'attributes' => {
11044 
              'bin_pt' => 0,
11045 
              'is_floating_block' => 1,
11046 
              'must_be_hdl_vector' => 1,
11047 
              'period' => 1,
11048 
              'port_id' => 0,
11049 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
11050 
              'type' => 'UFix_32_0',
11051 
            },
11052 
            'direction' => 'out',
11053 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11054 
            'width' => 32,
11055 
          },
11056 
          'to_register32_dout' => {
11057 
            'attributes' => {
11058 
              'bin_pt' => 0,
11059 
              'is_floating_block' => 1,
11060 
              'must_be_hdl_vector' => 1,
11061 
              'period' => 1,
11062 
              'port_id' => 0,
11063 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
11064 
              'type' => 'UFix_32_0',
11065 
            },
11066 
            'direction' => 'in',
11067 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11068 
            'width' => 32,
11069 
          },
11070 
          'to_register32_en' => {
11071 
            'attributes' => {
11072 
              'bin_pt' => 0,
11073 
              'is_floating_block' => 1,
11074 
              'must_be_hdl_vector' => 1,
11075 
              'period' => 1,
11076 
              'port_id' => 1,
11077 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
11078 
              'type' => 'Bool',
11079 
            },
11080 
            'direction' => 'out',
11081 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11082 
            'width' => 1,
11083 
          },
11084 
          'to_register33_ce' => {
11085 
            'attributes' => {
11086 
              'domain' => '',
11087 
              'group' => 1,
11088 
              'isCe' => 1,
11089 
              'is_floating_block' => 1,
11090 
              'period' => 1,
11091 
              'type' => 'logic',
11092 
            },
11093 
            'direction' => 'out',
11094 
            'hdlType' => 'std_logic',
11095 
            'width' => 1,
11096 
          },
11097 
          'to_register33_clk' => {
11098 
            'attributes' => {
11099 
              'domain' => '',
11100 
              'group' => 1,
11101 
              'isClk' => 1,
11102 
              'is_floating_block' => 1,
11103 
              'period' => 1,
11104 
              'type' => 'logic',
11105 
            },
11106 
            'direction' => 'out',
11107 
            'hdlType' => 'std_logic',
11108 
            'width' => 1,
11109 
          },
11110 
          'to_register33_clr' => {
11111 
            'attributes' => {
11112 
              'domain' => '',
11113 
              'group' => 1,
11114 
              'isClr' => 1,
11115 
              'is_floating_block' => 1,
11116 
              'period' => 1,
11117 
              'type' => 'logic',
11118 
              'valid_bit_used' => 0,
11119 
            },
11120 
            'direction' => 'out',
11121 
            'hdlType' => 'std_logic',
11122 
            'width' => 1,
11123 
          },
11124 
          'to_register33_data_in' => {
11125 
            'attributes' => {
11126 
              'bin_pt' => 0,
11127 
              'is_floating_block' => 1,
11128 
              'must_be_hdl_vector' => 1,
11129 
              'period' => 1,
11130 
              'port_id' => 0,
11131 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
11132 
              'type' => 'Bool',
11133 
            },
11134 
            'direction' => 'out',
11135 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11136 
            'width' => 1,
11137 
          },
11138 
          'to_register33_dout' => {
11139 
            'attributes' => {
11140 
              'bin_pt' => 0,
11141 
              'is_floating_block' => 1,
11142 
              'must_be_hdl_vector' => 1,
11143 
              'period' => 1,
11144 
              'port_id' => 0,
11145 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
11146 
              'type' => 'Bool',
11147 
            },
11148 
            'direction' => 'in',
11149 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11150 
            'width' => 1,
11151 
          },
11152 
          'to_register33_en' => {
11153 
            'attributes' => {
11154 
              'bin_pt' => 0,
11155 
              'is_floating_block' => 1,
11156 
              'must_be_hdl_vector' => 1,
11157 
              'period' => 1,
11158 
              'port_id' => 1,
11159 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
11160 
              'type' => 'Bool',
11161 
            },
11162 
            'direction' => 'out',
11163 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11164 
            'width' => 1,
11165 
          },
11166 
          'to_register34_ce' => {
11167 
            'attributes' => {
11168 
              'domain' => '',
11169 
              'group' => 1,
11170 
              'isCe' => 1,
11171 
              'is_floating_block' => 1,
11172 
              'period' => 1,
11173 
              'type' => 'logic',
11174 
            },
11175 
            'direction' => 'out',
11176 
            'hdlType' => 'std_logic',
11177 
            'width' => 1,
11178 
          },
11179 
          'to_register34_clk' => {
11180 
            'attributes' => {
11181 
              'domain' => '',
11182 
              'group' => 1,
11183 
              'isClk' => 1,
11184 
              'is_floating_block' => 1,
11185 
              'period' => 1,
11186 
              'type' => 'logic',
11187 
            },
11188 
            'direction' => 'out',
11189 
            'hdlType' => 'std_logic',
11190 
            'width' => 1,
11191 
          },
11192 
          'to_register34_clr' => {
11193 
            'attributes' => {
11194 
              'domain' => '',
11195 
              'group' => 1,
11196 
              'isClr' => 1,
11197 
              'is_floating_block' => 1,
11198 
              'period' => 1,
11199 
              'type' => 'logic',
11200 
              'valid_bit_used' => 0,
11201 
            },
11202 
            'direction' => 'out',
11203 
            'hdlType' => 'std_logic',
11204 
            'width' => 1,
11205 
          },
11206 
          'to_register34_data_in' => {
11207 
            'attributes' => {
11208 
              'bin_pt' => 0,
11209 
              'is_floating_block' => 1,
11210 
              'must_be_hdl_vector' => 1,
11211 
              'period' => 1,
11212 
              'port_id' => 0,
11213 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
11214 
              'type' => 'UFix_32_0',
11215 
            },
11216 
            'direction' => 'out',
11217 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11218 
            'width' => 32,
11219 
          },
11220 
          'to_register34_dout' => {
11221 
            'attributes' => {
11222 
              'bin_pt' => 0,
11223 
              'is_floating_block' => 1,
11224 
              'must_be_hdl_vector' => 1,
11225 
              'period' => 1,
11226 
              'port_id' => 0,
11227 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
11228 
              'type' => 'UFix_32_0',
11229 
            },
11230 
            'direction' => 'in',
11231 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11232 
            'width' => 32,
11233 
          },
11234 
          'to_register34_en' => {
11235 
            'attributes' => {
11236 
              'bin_pt' => 0,
11237 
              'is_floating_block' => 1,
11238 
              'must_be_hdl_vector' => 1,
11239 
              'period' => 1,
11240 
              'port_id' => 1,
11241 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
11242 
              'type' => 'Bool',
11243 
            },
11244 
            'direction' => 'out',
11245 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11246 
            'width' => 1,
11247 
          },
11248 
          'to_register3_ce' => {
11249 
            'attributes' => {
11250 
              'domain' => '',
11251 
              'group' => 1,
11252 
              'isCe' => 1,
11253 
              'is_floating_block' => 1,
11254 
              'period' => 1,
11255 
              'type' => 'logic',
11256 
            },
11257 
            'direction' => 'out',
11258 
            'hdlType' => 'std_logic',
11259 
            'width' => 1,
11260 
          },
11261 
          'to_register3_clk' => {
11262 
            'attributes' => {
11263 
              'domain' => '',
11264 
              'group' => 1,
11265 
              'isClk' => 1,
11266 
              'is_floating_block' => 1,
11267 
              'period' => 1,
11268 
              'type' => 'logic',
11269 
            },
11270 
            'direction' => 'out',
11271 
            'hdlType' => 'std_logic',
11272 
            'width' => 1,
11273 
          },
11274 
          'to_register3_clr' => {
11275 
            'attributes' => {
11276 
              'domain' => '',
11277 
              'group' => 1,
11278 
              'isClr' => 1,
11279 
              'is_floating_block' => 1,
11280 
              'period' => 1,
11281 
              'type' => 'logic',
11282 
              'valid_bit_used' => 0,
11283 
            },
11284 
            'direction' => 'out',
11285 
            'hdlType' => 'std_logic',
11286 
            'width' => 1,
11287 
          },
11288 
          'to_register3_data_in' => {
11289 
            'attributes' => {
11290 
              'bin_pt' => 0,
11291 
              'is_floating_block' => 1,
11292 
              'must_be_hdl_vector' => 1,
11293 
              'period' => 1,
11294 
              'port_id' => 0,
11295 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
11296 
              'type' => 'Bool',
11297 
            },
11298 
            'direction' => 'out',
11299 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11300 
            'width' => 1,
11301 
          },
11302 
          'to_register3_dout' => {
11303 
            'attributes' => {
11304 
              'bin_pt' => 0,
11305 
              'is_floating_block' => 1,
11306 
              'must_be_hdl_vector' => 1,
11307 
              'period' => 1,
11308 
              'port_id' => 0,
11309 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
11310 
              'type' => 'Bool',
11311 
            },
11312 
            'direction' => 'in',
11313 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11314 
            'width' => 1,
11315 
          },
11316 
          'to_register3_en' => {
11317 
            'attributes' => {
11318 
              'bin_pt' => 0,
11319 
              'is_floating_block' => 1,
11320 
              'must_be_hdl_vector' => 1,
11321 
              'period' => 1,
11322 
              'port_id' => 1,
11323 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
11324 
              'type' => 'Bool',
11325 
            },
11326 
            'direction' => 'out',
11327 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11328 
            'width' => 1,
11329 
          },
11330 
          'to_register4_ce' => {
11331 
            'attributes' => {
11332 
              'domain' => '',
11333 
              'group' => 1,
11334 
              'isCe' => 1,
11335 
              'is_floating_block' => 1,
11336 
              'period' => 1,
11337 
              'type' => 'logic',
11338 
            },
11339 
            'direction' => 'out',
11340 
            'hdlType' => 'std_logic',
11341 
            'width' => 1,
11342 
          },
11343 
          'to_register4_clk' => {
11344 
            'attributes' => {
11345 
              'domain' => '',
11346 
              'group' => 1,
11347 
              'isClk' => 1,
11348 
              'is_floating_block' => 1,
11349 
              'period' => 1,
11350 
              'type' => 'logic',
11351 
            },
11352 
            'direction' => 'out',
11353 
            'hdlType' => 'std_logic',
11354 
            'width' => 1,
11355 
          },
11356 
          'to_register4_clr' => {
11357 
            'attributes' => {
11358 
              'domain' => '',
11359 
              'group' => 1,
11360 
              'isClr' => 1,
11361 
              'is_floating_block' => 1,
11362 
              'period' => 1,
11363 
              'type' => 'logic',
11364 
              'valid_bit_used' => 0,
11365 
            },
11366 
            'direction' => 'out',
11367 
            'hdlType' => 'std_logic',
11368 
            'width' => 1,
11369 
          },
11370 
          'to_register4_data_in' => {
11371 
            'attributes' => {
11372 
              'bin_pt' => 0,
11373 
              'is_floating_block' => 1,
11374 
              'must_be_hdl_vector' => 1,
11375 
              'period' => 1,
11376 
              'port_id' => 0,
11377 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
11378 
              'type' => 'Bool',
11379 
            },
11380 
            'direction' => 'out',
11381 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11382 
            'width' => 1,
11383 
          },
11384 
          'to_register4_dout' => {
11385 
            'attributes' => {
11386 
              'bin_pt' => 0,
11387 
              'is_floating_block' => 1,
11388 
              'must_be_hdl_vector' => 1,
11389 
              'period' => 1,
11390 
              'port_id' => 0,
11391 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
11392 
              'type' => 'Bool',
11393 
            },
11394 
            'direction' => 'in',
11395 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11396 
            'width' => 1,
11397 
          },
11398 
          'to_register4_en' => {
11399 
            'attributes' => {
11400 
              'bin_pt' => 0,
11401 
              'is_floating_block' => 1,
11402 
              'must_be_hdl_vector' => 1,
11403 
              'period' => 1,
11404 
              'port_id' => 1,
11405 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
11406 
              'type' => 'Bool',
11407 
            },
11408 
            'direction' => 'out',
11409 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11410 
            'width' => 1,
11411 
          },
11412 
          'to_register5_ce' => {
11413 
            'attributes' => {
11414 
              'domain' => '',
11415 
              'group' => 1,
11416 
              'isCe' => 1,
11417 
              'is_floating_block' => 1,
11418 
              'period' => 1,
11419 
              'type' => 'logic',
11420 
            },
11421 
            'direction' => 'out',
11422 
            'hdlType' => 'std_logic',
11423 
            'width' => 1,
11424 
          },
11425 
          'to_register5_clk' => {
11426 
            'attributes' => {
11427 
              'domain' => '',
11428 
              'group' => 1,
11429 
              'isClk' => 1,
11430 
              'is_floating_block' => 1,
11431 
              'period' => 1,
11432 
              'type' => 'logic',
11433 
            },
11434 
            'direction' => 'out',
11435 
            'hdlType' => 'std_logic',
11436 
            'width' => 1,
11437 
          },
11438 
          'to_register5_clr' => {
11439 
            'attributes' => {
11440 
              'domain' => '',
11441 
              'group' => 1,
11442 
              'isClr' => 1,
11443 
              'is_floating_block' => 1,
11444 
              'period' => 1,
11445 
              'type' => 'logic',
11446 
              'valid_bit_used' => 0,
11447 
            },
11448 
            'direction' => 'out',
11449 
            'hdlType' => 'std_logic',
11450 
            'width' => 1,
11451 
          },
11452 
          'to_register5_data_in' => {
11453 
            'attributes' => {
11454 
              'bin_pt' => 0,
11455 
              'is_floating_block' => 1,
11456 
              'must_be_hdl_vector' => 1,
11457 
              'period' => 1,
11458 
              'port_id' => 0,
11459 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
11460 
              'type' => 'UFix_32_0',
11461 
            },
11462 
            'direction' => 'out',
11463 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11464 
            'width' => 32,
11465 
          },
11466 
          'to_register5_dout' => {
11467 
            'attributes' => {
11468 
              'bin_pt' => 0,
11469 
              'is_floating_block' => 1,
11470 
              'must_be_hdl_vector' => 1,
11471 
              'period' => 1,
11472 
              'port_id' => 0,
11473 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
11474 
              'type' => 'UFix_32_0',
11475 
            },
11476 
            'direction' => 'in',
11477 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11478 
            'width' => 32,
11479 
          },
11480 
          'to_register5_en' => {
11481 
            'attributes' => {
11482 
              'bin_pt' => 0,
11483 
              'is_floating_block' => 1,
11484 
              'must_be_hdl_vector' => 1,
11485 
              'period' => 1,
11486 
              'port_id' => 1,
11487 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11488 
              'type' => 'Bool',
11489 
            },
11490 
            'direction' => 'out',
11491 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11492 
            'width' => 1,
11493 
          },
11494 
          'to_register6_ce' => {
11495 
            'attributes' => {
11496 
              'domain' => '',
11497 
              'group' => 1,
11498 
              'isCe' => 1,
11499 
              'is_floating_block' => 1,
11500 
              'period' => 1,
11501 
              'type' => 'logic',
11502 
            },
11503 
            'direction' => 'out',
11504 
            'hdlType' => 'std_logic',
11505 
            'width' => 1,
11506 
          },
11507 
          'to_register6_clk' => {
11508 
            'attributes' => {
11509 
              'domain' => '',
11510 
              'group' => 1,
11511 
              'isClk' => 1,
11512 
              'is_floating_block' => 1,
11513 
              'period' => 1,
11514 
              'type' => 'logic',
11515 
            },
11516 
            'direction' => 'out',
11517 
            'hdlType' => 'std_logic',
11518 
            'width' => 1,
11519 
          },
11520 
          'to_register6_clr' => {
11521 
            'attributes' => {
11522 
              'domain' => '',
11523 
              'group' => 1,
11524 
              'isClr' => 1,
11525 
              'is_floating_block' => 1,
11526 
              'period' => 1,
11527 
              'type' => 'logic',
11528 
              'valid_bit_used' => 0,
11529 
            },
11530 
            'direction' => 'out',
11531 
            'hdlType' => 'std_logic',
11532 
            'width' => 1,
11533 
          },
11534 
          'to_register6_data_in' => {
11535 
            'attributes' => {
11536 
              'bin_pt' => 0,
11537 
              'is_floating_block' => 1,
11538 
              'must_be_hdl_vector' => 1,
11539 
              'period' => 1,
11540 
              'port_id' => 0,
11541 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
11542 
              'type' => 'UFix_32_0',
11543 
            },
11544 
            'direction' => 'out',
11545 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11546 
            'width' => 32,
11547 
          },
11548 
          'to_register6_dout' => {
11549 
            'attributes' => {
11550 
              'bin_pt' => 0,
11551 
              'is_floating_block' => 1,
11552 
              'must_be_hdl_vector' => 1,
11553 
              'period' => 1,
11554 
              'port_id' => 0,
11555 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
11556 
              'type' => 'UFix_32_0',
11557 
            },
11558 
            'direction' => 'in',
11559 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11560 
            'width' => 32,
11561 
          },
11562 
          'to_register6_en' => {
11563 
            'attributes' => {
11564 
              'bin_pt' => 0,
11565 
              'is_floating_block' => 1,
11566 
              'must_be_hdl_vector' => 1,
11567 
              'period' => 1,
11568 
              'port_id' => 1,
11569 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
11570 
              'type' => 'Bool',
11571 
            },
11572 
            'direction' => 'out',
11573 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11574 
            'width' => 1,
11575 
          },
11576 
          'to_register7_ce' => {
11577 
            'attributes' => {
11578 
              'domain' => '',
11579 
              'group' => 1,
11580 
              'isCe' => 1,
11581 
              'is_floating_block' => 1,
11582 
              'period' => 1,
11583 
              'type' => 'logic',
11584 
            },
11585 
            'direction' => 'out',
11586 
            'hdlType' => 'std_logic',
11587 
            'width' => 1,
11588 
          },
11589 
          'to_register7_clk' => {
11590 
            'attributes' => {
11591 
              'domain' => '',
11592 
              'group' => 1,
11593 
              'isClk' => 1,
11594 
              'is_floating_block' => 1,
11595 
              'period' => 1,
11596 
              'type' => 'logic',
11597 
            },
11598 
            'direction' => 'out',
11599 
            'hdlType' => 'std_logic',
11600 
            'width' => 1,
11601 
          },
11602 
          'to_register7_clr' => {
11603 
            'attributes' => {
11604 
              'domain' => '',
11605 
              'group' => 1,
11606 
              'isClr' => 1,
11607 
              'is_floating_block' => 1,
11608 
              'period' => 1,
11609 
              'type' => 'logic',
11610 
              'valid_bit_used' => 0,
11611 
            },
11612 
            'direction' => 'out',
11613 
            'hdlType' => 'std_logic',
11614 
            'width' => 1,
11615 
          },
11616 
          'to_register7_data_in' => {
11617 
            'attributes' => {
11618 
              'bin_pt' => 0,
11619 
              'is_floating_block' => 1,
11620 
              'must_be_hdl_vector' => 1,
11621 
              'period' => 1,
11622 
              'port_id' => 0,
11623 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
11624 
              'type' => 'UFix_32_0',
11625 
            },
11626 
            'direction' => 'out',
11627 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11628 
            'width' => 32,
11629 
          },
11630 
          'to_register7_dout' => {
11631 
            'attributes' => {
11632 
              'bin_pt' => 0,
11633 
              'is_floating_block' => 1,
11634 
              'must_be_hdl_vector' => 1,
11635 
              'period' => 1,
11636 
              'port_id' => 0,
11637 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
11638 
              'type' => 'UFix_32_0',
11639 
            },
11640 
            'direction' => 'in',
11641 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11642 
            'width' => 32,
11643 
          },
11644 
          'to_register7_en' => {
11645 
            'attributes' => {
11646 
              'bin_pt' => 0,
11647 
              'is_floating_block' => 1,
11648 
              'must_be_hdl_vector' => 1,
11649 
              'period' => 1,
11650 
              'port_id' => 1,
11651 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11652 
              'type' => 'Bool',
11653 
            },
11654 
            'direction' => 'out',
11655 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11656 
            'width' => 1,
11657 
          },
11658 
          'to_register8_ce' => {
11659 
            'attributes' => {
11660 
              'domain' => '',
11661 
              'group' => 1,
11662 
              'isCe' => 1,
11663 
              'is_floating_block' => 1,
11664 
              'period' => 1,
11665 
              'type' => 'logic',
11666 
            },
11667 
            'direction' => 'out',
11668 
            'hdlType' => 'std_logic',
11669 
            'width' => 1,
11670 
          },
11671 
          'to_register8_clk' => {
11672 
            'attributes' => {
11673 
              'domain' => '',
11674 
              'group' => 1,
11675 
              'isClk' => 1,
11676 
              'is_floating_block' => 1,
11677 
              'period' => 1,
11678 
              'type' => 'logic',
11679 
            },
11680 
            'direction' => 'out',
11681 
            'hdlType' => 'std_logic',
11682 
            'width' => 1,
11683 
          },
11684 
          'to_register8_clr' => {
11685 
            'attributes' => {
11686 
              'domain' => '',
11687 
              'group' => 1,
11688 
              'isClr' => 1,
11689 
              'is_floating_block' => 1,
11690 
              'period' => 1,
11691 
              'type' => 'logic',
11692 
              'valid_bit_used' => 0,
11693 
            },
11694 
            'direction' => 'out',
11695 
            'hdlType' => 'std_logic',
11696 
            'width' => 1,
11697 
          },
11698 
          'to_register8_data_in' => {
11699 
            'attributes' => {
11700 
              'bin_pt' => 0,
11701 
              'is_floating_block' => 1,
11702 
              'must_be_hdl_vector' => 1,
11703 
              'period' => 1,
11704 
              'port_id' => 0,
11705 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11706 
              'type' => 'Bool',
11707 
            },
11708 
            'direction' => 'out',
11709 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11710 
            'width' => 1,
11711 
          },
11712 
          'to_register8_dout' => {
11713 
            'attributes' => {
11714 
              'bin_pt' => 0,
11715 
              'is_floating_block' => 1,
11716 
              'must_be_hdl_vector' => 1,
11717 
              'period' => 1,
11718 
              'port_id' => 0,
11719 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11720 
              'type' => 'Bool',
11721 
            },
11722 
            'direction' => 'in',
11723 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11724 
            'width' => 1,
11725 
          },
11726 
          'to_register8_en' => {
11727 
            'attributes' => {
11728 
              'bin_pt' => 0,
11729 
              'is_floating_block' => 1,
11730 
              'must_be_hdl_vector' => 1,
11731 
              'period' => 1,
11732 
              'port_id' => 1,
11733 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11734 
              'type' => 'Bool',
11735 
            },
11736 
            'direction' => 'out',
11737 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11738 
            'width' => 1,
11739 
          },
11740 
          'to_register9_ce' => {
11741 
            'attributes' => {
11742 
              'domain' => '',
11743 
              'group' => 1,
11744 
              'isCe' => 1,
11745 
              'is_floating_block' => 1,
11746 
              'period' => 1,
11747 
              'type' => 'logic',
11748 
            },
11749 
            'direction' => 'out',
11750 
            'hdlType' => 'std_logic',
11751 
            'width' => 1,
11752 
          },
11753 
          'to_register9_clk' => {
11754 
            'attributes' => {
11755 
              'domain' => '',
11756 
              'group' => 1,
11757 
              'isClk' => 1,
11758 
              'is_floating_block' => 1,
11759 
              'period' => 1,
11760 
              'type' => 'logic',
11761 
            },
11762 
            'direction' => 'out',
11763 
            'hdlType' => 'std_logic',
11764 
            'width' => 1,
11765 
          },
11766 
          'to_register9_clr' => {
11767 
            'attributes' => {
11768 
              'domain' => '',
11769 
              'group' => 1,
11770 
              'isClr' => 1,
11771 
              'is_floating_block' => 1,
11772 
              'period' => 1,
11773 
              'type' => 'logic',
11774 
              'valid_bit_used' => 0,
11775 
            },
11776 
            'direction' => 'out',
11777 
            'hdlType' => 'std_logic',
11778 
            'width' => 1,
11779 
          },
11780 
          'to_register9_data_in' => {
11781 
            'attributes' => {
11782 
              'bin_pt' => 0,
11783 
              'is_floating_block' => 1,
11784 
              'must_be_hdl_vector' => 1,
11785 
              'period' => 1,
11786 
              'port_id' => 0,
11787 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11788 
              'type' => 'UFix_32_0',
11789 
            },
11790 
            'direction' => 'out',
11791 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11792 
            'width' => 32,
11793 
          },
11794 
          'to_register9_dout' => {
11795 
            'attributes' => {
11796 
              'bin_pt' => 0,
11797 
              'is_floating_block' => 1,
11798 
              'must_be_hdl_vector' => 1,
11799 
              'period' => 1,
11800 
              'port_id' => 0,
11801 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11802 
              'type' => 'UFix_32_0',
11803 
            },
11804 
            'direction' => 'in',
11805 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11806 
            'width' => 32,
11807 
          },
11808 
          'to_register9_en' => {
11809 
            'attributes' => {
11810 
              'bin_pt' => 0,
11811 
              'is_floating_block' => 1,
11812 
              'must_be_hdl_vector' => 1,
11813 
              'period' => 1,
11814 
              'port_id' => 1,
11815 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11816 
              'type' => 'Bool',
11817 
            },
11818 
            'direction' => 'out',
11819 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11820 
            'width' => 1,
11821 
          },
11822 
        },
11823 
        'subblocks' => {
11824 
          'default_clock_driver_x0' => {
11825 
            'connections' => {
11826 
              'ce_1' => 'ce_1_sg',
11827 
              'clk_1' => 'clk_1_sg',
11828 
              'sysce' => [
11829 
                'constant',
11830 
                '\'1\'',
11831 
              ],
11832 
              'sysce_clr' => [
11833 
                'constant',
11834 
                '\'0\'',
11835 
              ],
11836 
              'sysclk' => 'clkNet',
11837 
            },
11838 
            'entity' => {
11839 
              'attributes' => {
11840 
                'domain' => 'default',
11841 
                'hdlArchAttributes' => [
11842 
                  [
11843 
                    'syn_noprune',
11844 
                    'boolean',
11845 
                    'true',
11846 
                  ],
11847 
                  [
11848 
                    'optimize_primitives',
11849 
                    'boolean',
11850 
                    'false',
11851 
                  ],
11852 
                  [
11853 
                    'dont_touch',
11854 
                    'boolean',
11855 
                    'true',
11856 
                  ],
11857 
                ],
11858 
                'hdlEntityAttributes' => [
11859 
                ],
11860 
                'isClkDriver' => 1,
11861 
              },
11862 
              'entityName' => 'default_clock_driver',
11863 
              'ports' => {
11864 
                'ce_1' => {
11865 
                  'attributes' => {
11866 
                    'domain' => 'default',
11867 
                    'group' => 1,
11868 
                    'isCe' => 1,
11869 
                    'period' => 1,
11870 
                    'type' => 'logic',
11871 
                  },
11872 
                  'direction' => 'out',
11873 
                  'hdlType' => 'std_logic',
11874 
                  'width' => 1,
11875 
                },
11876 
                'clk_1' => {
11877 
                  'attributes' => {
11878 
                    'domain' => 'default',
11879 
                    'group' => 1,
11880 
                    'isClk' => 1,
11881 
                    'period' => 1,
11882 
                    'type' => 'logic',
11883 
                  },
11884 
                  'direction' => 'out',
11885 
                  'hdlType' => 'std_logic',
11886 
                  'width' => 1,
11887 
                },
11888 
                'sysce' => {
11889 
                  'attributes' => {
11890 
                    'group' => 4,
11891 
                    'isCe' => 1,
11892 
                    'period' => 1,
11893 
                  },
11894 
                  'direction' => 'in',
11895 
                  'hdlType' => 'std_logic',
11896 
                  'width' => 1,
11897 
                },
11898 
                'sysce_clr' => {
11899 
                  'attributes' => {
11900 
                    'group' => 4,
11901 
                    'isClr' => 1,
11902 
                    'period' => 1,
11903 
                  },
11904 
                  'direction' => 'in',
11905 
                  'hdlType' => 'std_logic',
11906 
                  'width' => 1,
11907 
                },
11908 
                'sysclk' => {
11909 
                  'attributes' => {
11910 
                    'group' => 4,
11911 
                    'isClk' => 1,
11912 
                    'period' => 1,
11913 
                  },
11914 
                  'direction' => 'in',
11915 
                  'hdlType' => 'std_logic',
11916 
                  'width' => 1,
11917 
                },
11918 
              },
11919 
            },
11920 
            'entityName' => 'default_clock_driver',
11921 
          },
11922 
          'inout_logic_x0' => {
11923 
            'connections' => {
11924 
              'data_in' => 'debug_in_2i_net_x0',
11925 
              'data_in_x0' => 'reg04_tv_net_x0',
11926 
              'data_in_x1' => 'reg04_td_net_x0',
11927 
              'data_in_x10' => 'debug_in_3i_net_x0',
11928 
              'data_in_x11' => 'debug_in_4i_net_x0',
11929 
              'data_in_x12' => 'reg09_tv_net_x0',
11930 
              'data_in_x13' => 'reg09_td_net_x0',
11931 
              'data_in_x14' => 'reg10_tv_net_x0',
11932 
              'data_in_x15' => 'reg10_td_net_x0',
11933 
              'data_in_x16' => 'reg08_tv_net_x0',
11934 
              'data_in_x17' => 'reg08_td_net_x0',
11935 
              'data_in_x18' => 'reg11_tv_net_x0',
11936 
              'data_in_x19' => 'reg11_td_net_x0',
11937 
              'data_in_x2' => 'reg05_tv_net_x0',
11938 
              'data_in_x20' => 'reg12_tv_net_x0',
11939 
              'data_in_x21' => 'reg01_tv_net_x0',
11940 
              'data_in_x22' => 'reg12_td_net_x0',
11941 
              'data_in_x23' => 'reg13_tv_net_x0',
11942 
              'data_in_x24' => 'reg13_td_net_x0',
11943 
              'data_in_x25' => 'reg14_tv_net_x0',
11944 
              'data_in_x26' => 'reg14_td_net_x0',
11945 
              'data_in_x27' => 'reg02_tv_net_x0',
11946 
              'data_in_x28' => 'reg02_td_net_x0',
11947 
              'data_in_x29' => 'debug_in_1i_net_x0',
11948 
              'data_in_x3' => 'reg05_td_net_x0',
11949 
              'data_in_x30' => 'reg01_td_net_x0',
11950 
              'data_in_x31' => 'reg03_tv_net_x0',
11951 
              'data_in_x32' => 'reg03_td_net_x0',
11952 
              'data_in_x4' => 'reg06_tv_net_x0',
11953 
              'data_in_x5' => 'reg06_td_net_x0',
11954 
              'data_in_x6' => 'reg07_tv_net_x0',
11955 
              'data_in_x7' => 'reg07_td_net_x0',
11956 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
11957 
              'data_in_x9' => 'dma_host2board_done_net_x0',
11958 
              'data_out' => 'from_register1_data_out_net',
11959 
              'data_out_x0' => 'from_register10_data_out_net',
11960 
              'data_out_x1' => 'from_register11_data_out_net',
11961 
              'data_out_x10' => 'from_register2_data_out_net',
11962 
              'data_out_x11' => 'from_register20_data_out_net',
11963 
              'data_out_x12' => 'from_register21_data_out_net',
11964 
              'data_out_x13' => 'from_register22_data_out_net',
11965 
              'data_out_x14' => 'from_register23_data_out_net',
11966 
              'data_out_x15' => 'from_register24_data_out_net',
11967 
              'data_out_x16' => 'from_register25_data_out_net',
11968 
              'data_out_x17' => 'from_register26_data_out_net',
11969 
              'data_out_x18' => 'from_register27_data_out_net',
11970 
              'data_out_x19' => 'from_register28_data_out_net',
11971 
              'data_out_x2' => 'from_register12_data_out_net',
11972 
              'data_out_x20' => 'from_register3_data_out_net',
11973 
              'data_out_x21' => 'from_register4_data_out_net',
11974 
              'data_out_x22' => 'from_register5_data_out_net',
11975 
              'data_out_x23' => 'from_register6_data_out_net',
11976 
              'data_out_x24' => 'from_register7_data_out_net',
11977 
              'data_out_x25' => 'from_register8_data_out_net',
11978 
              'data_out_x26' => 'from_register9_data_out_net',
11979 
              'data_out_x3' => 'from_register13_data_out_net',
11980 
              'data_out_x4' => 'from_register14_data_out_net',
11981 
              'data_out_x5' => 'from_register15_data_out_net',
11982 
              'data_out_x6' => 'from_register16_data_out_net',
11983 
              'data_out_x7' => 'from_register17_data_out_net',
11984 
              'data_out_x8' => 'from_register18_data_out_net',
11985 
              'data_out_x9' => 'from_register19_data_out_net',
11986 
              'debug_in_1i' => 'debug_in_1i_net',
11987 
              'debug_in_2i' => 'debug_in_2i_net',
11988 
              'debug_in_3i' => 'debug_in_3i_net',
11989 
              'debug_in_4i' => 'debug_in_4i_net',
11990 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
11991 
              'dma_host2board_done' => 'dma_host2board_done_net',
11992 
              'en' => 'constant5_op_net_x0',
11993 
              'en_x0' => 'constant5_op_net_x1',
11994 
              'en_x1' => 'constant5_op_net_x2',
11995 
              'en_x10' => 'constant5_op_net_x11',
11996 
              'en_x11' => 'constant5_op_net_x12',
11997 
              'en_x12' => 'constant1_op_net_x0',
11998 
              'en_x13' => 'constant1_op_net_x1',
11999 
              'en_x14' => 'constant1_op_net_x2',
12000 
              'en_x15' => 'constant1_op_net_x3',
12001 
              'en_x16' => 'constant1_op_net_x4',
12002 
              'en_x17' => 'constant1_op_net_x5',
12003 
              'en_x18' => 'constant1_op_net_x6',
12004 
              'en_x19' => 'constant1_op_net_x7',
12005 
              'en_x2' => 'constant5_op_net_x3',
12006 
              'en_x20' => 'constant1_op_net_x8',
12007 
              'en_x21' => 'constant5_op_net_x13',
12008 
              'en_x22' => 'constant1_op_net_x9',
12009 
              'en_x23' => 'constant1_op_net_x10',
12010 
              'en_x24' => 'constant1_op_net_x11',
12011 
              'en_x25' => 'constant1_op_net_x12',
12012 
              'en_x26' => 'constant1_op_net_x13',
12013 
              'en_x27' => 'constant5_op_net_x14',
12014 
              'en_x28' => 'constant5_op_net_x15',
12015 
              'en_x29' => 'constant5_op_net_x16',
12016 
              'en_x3' => 'constant5_op_net_x4',
12017 
              'en_x30' => 'constant5_op_net_x17',
12018 
              'en_x31' => 'constant5_op_net_x18',
12019 
              'en_x32' => 'constant5_op_net_x19',
12020 
              'en_x4' => 'constant5_op_net_x5',
12021 
              'en_x5' => 'constant5_op_net_x6',
12022 
              'en_x6' => 'constant5_op_net_x7',
12023 
              'en_x7' => 'constant5_op_net_x8',
12024 
              'en_x8' => 'constant5_op_net_x9',
12025 
              'en_x9' => 'constant5_op_net_x10',
12026 
              'reg01_rd' => 'from_register3_data_out_net_x0',
12027 
              'reg01_rv' => 'from_register1_data_out_net_x0',
12028 
              'reg01_td' => 'reg01_td_net',
12029 
              'reg01_tv' => 'reg01_tv_net',
12030 
              'reg02_rd' => 'from_register5_data_out_net_x0',
12031 
              'reg02_rv' => 'from_register2_data_out_net_x0',
12032 
              'reg02_td' => 'reg02_td_net',
12033 
              'reg02_tv' => 'reg02_tv_net',
12034 
              'reg03_rd' => 'from_register7_data_out_net_x0',
12035 
              'reg03_rv' => 'from_register6_data_out_net_x0',
12036 
              'reg03_td' => 'reg03_td_net',
12037 
              'reg03_tv' => 'reg03_tv_net',
12038 
              'reg04_rd' => 'from_register8_data_out_net_x0',
12039 
              'reg04_rv' => 'from_register4_data_out_net_x0',
12040 
              'reg04_td' => 'reg04_td_net',
12041 
              'reg04_tv' => 'reg04_tv_net',
12042 
              'reg05_rd' => 'from_register10_data_out_net_x0',
12043 
              'reg05_rv' => 'from_register9_data_out_net_x0',
12044 
              'reg05_td' => 'reg05_td_net',
12045 
              'reg05_tv' => 'reg05_tv_net',
12046 
              'reg06_rd' => 'from_register11_data_out_net_x0',
12047 
              'reg06_rv' => 'from_register12_data_out_net_x0',
12048 
              'reg06_td' => 'reg06_td_net',
12049 
              'reg06_tv' => 'reg06_tv_net',
12050 
              'reg07_rd' => 'from_register13_data_out_net_x0',
12051 
              'reg07_rv' => 'from_register14_data_out_net_x0',
12052 
              'reg07_td' => 'reg07_td_net',
12053 
              'reg07_tv' => 'reg07_tv_net',
12054 
              'reg08_rd' => 'from_register15_data_out_net_x0',
12055 
              'reg08_rv' => 'from_register16_data_out_net_x0',
12056 
              'reg08_td' => 'reg08_td_net',
12057 
              'reg08_tv' => 'reg08_tv_net',
12058 
              'reg09_rd' => 'from_register17_data_out_net_x0',
12059 
              'reg09_rv' => 'from_register18_data_out_net_x0',
12060 
              'reg09_td' => 'reg09_td_net',
12061 
              'reg09_tv' => 'reg09_tv_net',
12062 
              'reg10_rd' => 'from_register19_data_out_net_x0',
12063 
              'reg10_rv' => 'from_register20_data_out_net_x0',
12064 
              'reg10_td' => 'reg10_td_net',
12065 
              'reg10_tv' => 'reg10_tv_net',
12066 
              'reg11_rd' => 'from_register21_data_out_net_x0',
12067 
              'reg11_rv' => 'from_register22_data_out_net_x0',
12068 
              'reg11_td' => 'reg11_td_net',
12069 
              'reg11_tv' => 'reg11_tv_net',
12070 
              'reg12_rd' => 'from_register23_data_out_net_x0',
12071 
              'reg12_rv' => 'from_register24_data_out_net_x0',
12072 
              'reg12_td' => 'reg12_td_net',
12073 
              'reg12_tv' => 'reg12_tv_net',
12074 
              'reg13_rd' => 'from_register25_data_out_net_x0',
12075 
              'reg13_rv' => 'from_register26_data_out_net_x0',
12076 
              'reg13_td' => 'reg13_td_net',
12077 
              'reg13_tv' => 'reg13_tv_net',
12078 
              'reg14_rd' => 'from_register27_data_out_net_x0',
12079 
              'reg14_rv' => 'from_register28_data_out_net_x0',
12080 
              'reg14_td' => 'reg14_td_net',
12081 
              'reg14_tv' => 'reg14_tv_net',
12082 
            },
12083 
            'entity' => {
12084 
              'attributes' => {
12085 
                'entityAlreadyNetlisted' => 1,
12086 
                'hdlKind' => 'vhdl',
12087 
                'isDesign' => 1,
12088 
                'simulinkName' => 'INOUT_LOGIC',
12089 
              },
12090 
              'entityName' => 'inout_logic',
12091 
              'ports' => {
12092 
                'data_in' => {
12093 
                  'attributes' => {
12094 
                    'bin_pt' => 0,
12095 
                    'is_floating_block' => 1,
12096 
                    'must_be_hdl_vector' => 1,
12097 
                    'period' => 1,
12098 
                    'port_id' => 0,
12099 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12100 
                    'type' => 'UFix_32_0',
12101 
                  },
12102 
                  'direction' => 'out',
12103 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12104 
                  'width' => 32,
12105 
                },
12106 
                'data_in_x0' => {
12107 
                  'attributes' => {
12108 
                    'bin_pt' => 0,
12109 
                    'is_floating_block' => 1,
12110 
                    'must_be_hdl_vector' => 1,
12111 
                    'period' => 1,
12112 
                    'port_id' => 0,
12113 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12114 
                    'type' => 'Bool',
12115 
                  },
12116 
                  'direction' => 'out',
12117 
                  'hdlType' => 'std_logic',
12118 
                  'width' => 1,
12119 
                },
12120 
                'data_in_x1' => {
12121 
                  'attributes' => {
12122 
                    'bin_pt' => 0,
12123 
                    'is_floating_block' => 1,
12124 
                    'must_be_hdl_vector' => 1,
12125 
                    'period' => 1,
12126 
                    'port_id' => 0,
12127 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12128 
                    'type' => 'UFix_32_0',
12129 
                  },
12130 
                  'direction' => 'out',
12131 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12132 
                  'width' => 32,
12133 
                },
12134 
                'data_in_x10' => {
12135 
                  'attributes' => {
12136 
                    'bin_pt' => 0,
12137 
                    'is_floating_block' => 1,
12138 
                    'must_be_hdl_vector' => 1,
12139 
                    'period' => 1,
12140 
                    'port_id' => 0,
12141 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12142 
                    'type' => 'UFix_32_0',
12143 
                  },
12144 
                  'direction' => 'out',
12145 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12146 
                  'width' => 32,
12147 
                },
12148 
                'data_in_x11' => {
12149 
                  'attributes' => {
12150 
                    'bin_pt' => 0,
12151 
                    'is_floating_block' => 1,
12152 
                    'must_be_hdl_vector' => 1,
12153 
                    'period' => 1,
12154 
                    'port_id' => 0,
12155 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12156 
                    'type' => 'UFix_32_0',
12157 
                  },
12158 
                  'direction' => 'out',
12159 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12160 
                  'width' => 32,
12161 
                },
12162 
                'data_in_x12' => {
12163 
                  'attributes' => {
12164 
                    'bin_pt' => 0,
12165 
                    'is_floating_block' => 1,
12166 
                    'must_be_hdl_vector' => 1,
12167 
                    'period' => 1,
12168 
                    'port_id' => 0,
12169 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12170 
                    'type' => 'Bool',
12171 
                  },
12172 
                  'direction' => 'out',
12173 
                  'hdlType' => 'std_logic',
12174 
                  'width' => 1,
12175 
                },
12176 
                'data_in_x13' => {
12177 
                  'attributes' => {
12178 
                    'bin_pt' => 0,
12179 
                    'is_floating_block' => 1,
12180 
                    'must_be_hdl_vector' => 1,
12181 
                    'period' => 1,
12182 
                    'port_id' => 0,
12183 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12184 
                    'type' => 'UFix_32_0',
12185 
                  },
12186 
                  'direction' => 'out',
12187 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12188 
                  'width' => 32,
12189 
                },
12190 
                'data_in_x14' => {
12191 
                  'attributes' => {
12192 
                    'bin_pt' => 0,
12193 
                    'is_floating_block' => 1,
12194 
                    'must_be_hdl_vector' => 1,
12195 
                    'period' => 1,
12196 
                    'port_id' => 0,
12197 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12198 
                    'type' => 'Bool',
12199 
                  },
12200 
                  'direction' => 'out',
12201 
                  'hdlType' => 'std_logic',
12202 
                  'width' => 1,
12203 
                },
12204 
                'data_in_x15' => {
12205 
                  'attributes' => {
12206 
                    'bin_pt' => 0,
12207 
                    'is_floating_block' => 1,
12208 
                    'must_be_hdl_vector' => 1,
12209 
                    'period' => 1,
12210 
                    'port_id' => 0,
12211 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12212 
                    'type' => 'UFix_32_0',
12213 
                  },
12214 
                  'direction' => 'out',
12215 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12216 
                  'width' => 32,
12217 
                },
12218 
                'data_in_x16' => {
12219 
                  'attributes' => {
12220 
                    'bin_pt' => 0,
12221 
                    'is_floating_block' => 1,
12222 
                    'must_be_hdl_vector' => 1,
12223 
                    'period' => 1,
12224 
                    'port_id' => 0,
12225 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12226 
                    'type' => 'Bool',
12227 
                  },
12228 
                  'direction' => 'out',
12229 
                  'hdlType' => 'std_logic',
12230 
                  'width' => 1,
12231 
                },
12232 
                'data_in_x17' => {
12233 
                  'attributes' => {
12234 
                    'bin_pt' => 0,
12235 
                    'is_floating_block' => 1,
12236 
                    'must_be_hdl_vector' => 1,
12237 
                    'period' => 1,
12238 
                    'port_id' => 0,
12239 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12240 
                    'type' => 'UFix_32_0',
12241 
                  },
12242 
                  'direction' => 'out',
12243 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12244 
                  'width' => 32,
12245 
                },
12246 
                'data_in_x18' => {
12247 
                  'attributes' => {
12248 
                    'bin_pt' => 0,
12249 
                    'is_floating_block' => 1,
12250 
                    'must_be_hdl_vector' => 1,
12251 
                    'period' => 1,
12252 
                    'port_id' => 0,
12253 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12254 
                    'type' => 'Bool',
12255 
                  },
12256 
                  'direction' => 'out',
12257 
                  'hdlType' => 'std_logic',
12258 
                  'width' => 1,
12259 
                },
12260 
                'data_in_x19' => {
12261 
                  'attributes' => {
12262 
                    'bin_pt' => 0,
12263 
                    'is_floating_block' => 1,
12264 
                    'must_be_hdl_vector' => 1,
12265 
                    'period' => 1,
12266 
                    'port_id' => 0,
12267 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12268 
                    'type' => 'UFix_32_0',
12269 
                  },
12270 
                  'direction' => 'out',
12271 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12272 
                  'width' => 32,
12273 
                },
12274 
                'data_in_x2' => {
12275 
                  'attributes' => {
12276 
                    'bin_pt' => 0,
12277 
                    'is_floating_block' => 1,
12278 
                    'must_be_hdl_vector' => 1,
12279 
                    'period' => 1,
12280 
                    'port_id' => 0,
12281 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12282 
                    'type' => 'Bool',
12283 
                  },
12284 
                  'direction' => 'out',
12285 
                  'hdlType' => 'std_logic',
12286 
                  'width' => 1,
12287 
                },
12288 
                'data_in_x20' => {
12289 
                  'attributes' => {
12290 
                    'bin_pt' => 0,
12291 
                    'is_floating_block' => 1,
12292 
                    'must_be_hdl_vector' => 1,
12293 
                    'period' => 1,
12294 
                    'port_id' => 0,
12295 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12296 
                    'type' => 'Bool',
12297 
                  },
12298 
                  'direction' => 'out',
12299 
                  'hdlType' => 'std_logic',
12300 
                  'width' => 1,
12301 
                },
12302 
                'data_in_x21' => {
12303 
                  'attributes' => {
12304 
                    'bin_pt' => 0,
12305 
                    'is_floating_block' => 1,
12306 
                    'must_be_hdl_vector' => 1,
12307 
                    'period' => 1,
12308 
                    'port_id' => 0,
12309 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12310 
                    'type' => 'Bool',
12311 
                  },
12312 
                  'direction' => 'out',
12313 
                  'hdlType' => 'std_logic',
12314 
                  'width' => 1,
12315 
                },
12316 
                'data_in_x22' => {
12317 
                  'attributes' => {
12318 
                    'bin_pt' => 0,
12319 
                    'is_floating_block' => 1,
12320 
                    'must_be_hdl_vector' => 1,
12321 
                    'period' => 1,
12322 
                    'port_id' => 0,
12323 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12324 
                    'type' => 'UFix_32_0',
12325 
                  },
12326 
                  'direction' => 'out',
12327 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12328 
                  'width' => 32,
12329 
                },
12330 
                'data_in_x23' => {
12331 
                  'attributes' => {
12332 
                    'bin_pt' => 0,
12333 
                    'is_floating_block' => 1,
12334 
                    'must_be_hdl_vector' => 1,
12335 
                    'period' => 1,
12336 
                    'port_id' => 0,
12337 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12338 
                    'type' => 'Bool',
12339 
                  },
12340 
                  'direction' => 'out',
12341 
                  'hdlType' => 'std_logic',
12342 
                  'width' => 1,
12343 
                },
12344 
                'data_in_x24' => {
12345 
                  'attributes' => {
12346 
                    'bin_pt' => 0,
12347 
                    'is_floating_block' => 1,
12348 
                    'must_be_hdl_vector' => 1,
12349 
                    'period' => 1,
12350 
                    'port_id' => 0,
12351 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12352 
                    'type' => 'UFix_32_0',
12353 
                  },
12354 
                  'direction' => 'out',
12355 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12356 
                  'width' => 32,
12357 
                },
12358 
                'data_in_x25' => {
12359 
                  'attributes' => {
12360 
                    'bin_pt' => 0,
12361 
                    'is_floating_block' => 1,
12362 
                    'must_be_hdl_vector' => 1,
12363 
                    'period' => 1,
12364 
                    'port_id' => 0,
12365 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12366 
                    'type' => 'Bool',
12367 
                  },
12368 
                  'direction' => 'out',
12369 
                  'hdlType' => 'std_logic',
12370 
                  'width' => 1,
12371 
                },
12372 
                'data_in_x26' => {
12373 
                  'attributes' => {
12374 
                    'bin_pt' => 0,
12375 
                    'is_floating_block' => 1,
12376 
                    'must_be_hdl_vector' => 1,
12377 
                    'period' => 1,
12378 
                    'port_id' => 0,
12379 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12380 
                    'type' => 'UFix_32_0',
12381 
                  },
12382 
                  'direction' => 'out',
12383 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12384 
                  'width' => 32,
12385 
                },
12386 
                'data_in_x27' => {
12387 
                  'attributes' => {
12388 
                    'bin_pt' => 0,
12389 
                    'is_floating_block' => 1,
12390 
                    'must_be_hdl_vector' => 1,
12391 
                    'period' => 1,
12392 
                    'port_id' => 0,
12393 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12394 
                    'type' => 'Bool',
12395 
                  },
12396 
                  'direction' => 'out',
12397 
                  'hdlType' => 'std_logic',
12398 
                  'width' => 1,
12399 
                },
12400 
                'data_in_x28' => {
12401 
                  'attributes' => {
12402 
                    'bin_pt' => 0,
12403 
                    'is_floating_block' => 1,
12404 
                    'must_be_hdl_vector' => 1,
12405 
                    'period' => 1,
12406 
                    'port_id' => 0,
12407 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12408 
                    'type' => 'UFix_32_0',
12409 
                  },
12410 
                  'direction' => 'out',
12411 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12412 
                  'width' => 32,
12413 
                },
12414 
                'data_in_x29' => {
12415 
                  'attributes' => {
12416 
                    'bin_pt' => 0,
12417 
                    'is_floating_block' => 1,
12418 
                    'must_be_hdl_vector' => 1,
12419 
                    'period' => 1,
12420 
                    'port_id' => 0,
12421 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12422 
                    'type' => 'UFix_32_0',
12423 
                  },
12424 
                  'direction' => 'out',
12425 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12426 
                  'width' => 32,
12427 
                },
12428 
                'data_in_x3' => {
12429 
                  'attributes' => {
12430 
                    'bin_pt' => 0,
12431 
                    'is_floating_block' => 1,
12432 
                    'must_be_hdl_vector' => 1,
12433 
                    'period' => 1,
12434 
                    'port_id' => 0,
12435 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12436 
                    'type' => 'UFix_32_0',
12437 
                  },
12438 
                  'direction' => 'out',
12439 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12440 
                  'width' => 32,
12441 
                },
12442 
                'data_in_x30' => {
12443 
                  'attributes' => {
12444 
                    'bin_pt' => 0,
12445 
                    'is_floating_block' => 1,
12446 
                    'must_be_hdl_vector' => 1,
12447 
                    'period' => 1,
12448 
                    'port_id' => 0,
12449 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12450 
                    'type' => 'UFix_32_0',
12451 
                  },
12452 
                  'direction' => 'out',
12453 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12454 
                  'width' => 32,
12455 
                },
12456 
                'data_in_x31' => {
12457 
                  'attributes' => {
12458 
                    'bin_pt' => 0,
12459 
                    'is_floating_block' => 1,
12460 
                    'must_be_hdl_vector' => 1,
12461 
                    'period' => 1,
12462 
                    'port_id' => 0,
12463 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12464 
                    'type' => 'Bool',
12465 
                  },
12466 
                  'direction' => 'out',
12467 
                  'hdlType' => 'std_logic',
12468 
                  'width' => 1,
12469 
                },
12470 
                'data_in_x32' => {
12471 
                  'attributes' => {
12472 
                    'bin_pt' => 0,
12473 
                    'is_floating_block' => 1,
12474 
                    'must_be_hdl_vector' => 1,
12475 
                    'period' => 1,
12476 
                    'port_id' => 0,
12477 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12478 
                    'type' => 'UFix_32_0',
12479 
                  },
12480 
                  'direction' => 'out',
12481 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12482 
                  'width' => 32,
12483 
                },
12484 
                'data_in_x4' => {
12485 
                  'attributes' => {
12486 
                    'bin_pt' => 0,
12487 
                    'is_floating_block' => 1,
12488 
                    'must_be_hdl_vector' => 1,
12489 
                    'period' => 1,
12490 
                    'port_id' => 0,
12491 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12492 
                    'type' => 'Bool',
12493 
                  },
12494 
                  'direction' => 'out',
12495 
                  'hdlType' => 'std_logic',
12496 
                  'width' => 1,
12497 
                },
12498 
                'data_in_x5' => {
12499 
                  'attributes' => {
12500 
                    'bin_pt' => 0,
12501 
                    'is_floating_block' => 1,
12502 
                    'must_be_hdl_vector' => 1,
12503 
                    'period' => 1,
12504 
                    'port_id' => 0,
12505 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12506 
                    'type' => 'UFix_32_0',
12507 
                  },
12508 
                  'direction' => 'out',
12509 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12510 
                  'width' => 32,
12511 
                },
12512 
                'data_in_x6' => {
12513 
                  'attributes' => {
12514 
                    'bin_pt' => 0,
12515 
                    'is_floating_block' => 1,
12516 
                    'must_be_hdl_vector' => 1,
12517 
                    'period' => 1,
12518 
                    'port_id' => 0,
12519 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12520 
                    'type' => 'Bool',
12521 
                  },
12522 
                  'direction' => 'out',
12523 
                  'hdlType' => 'std_logic',
12524 
                  'width' => 1,
12525 
                },
12526 
                'data_in_x7' => {
12527 
                  'attributes' => {
12528 
                    'bin_pt' => 0,
12529 
                    'is_floating_block' => 1,
12530 
                    'must_be_hdl_vector' => 1,
12531 
                    'period' => 1,
12532 
                    'port_id' => 0,
12533 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12534 
                    'type' => 'UFix_32_0',
12535 
                  },
12536 
                  'direction' => 'out',
12537 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12538 
                  'width' => 32,
12539 
                },
12540 
                'data_in_x8' => {
12541 
                  'attributes' => {
12542 
                    'bin_pt' => 0,
12543 
                    'is_floating_block' => 1,
12544 
                    'must_be_hdl_vector' => 1,
12545 
                    'period' => 1,
12546 
                    'port_id' => 0,
12547 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12548 
                    'type' => 'UFix_1_0',
12549 
                  },
12550 
                  'direction' => 'out',
12551 
                  'hdlType' => 'std_logic',
12552 
                  'width' => 1,
12553 
                },
12554 
                'data_in_x9' => {
12555 
                  'attributes' => {
12556 
                    'bin_pt' => 0,
12557 
                    'is_floating_block' => 1,
12558 
                    'must_be_hdl_vector' => 1,
12559 
                    'period' => 1,
12560 
                    'port_id' => 0,
12561 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12562 
                    'type' => 'UFix_1_0',
12563 
                  },
12564 
                  'direction' => 'out',
12565 
                  'hdlType' => 'std_logic',
12566 
                  'width' => 1,
12567 
                },
12568 
                'data_out' => {
12569 
                  'attributes' => {
12570 
                    'bin_pt' => 0,
12571 
                    'is_floating_block' => 1,
12572 
                    'must_be_hdl_vector' => 1,
12573 
                    'period' => 1,
12574 
                    'port_id' => 0,
12575 
                    'simulinkName' => 'INOUT_LOGIC/From Register1',
12576 
                    'type' => 'UFix_1_0',
12577 
                  },
12578 
                  'direction' => 'in',
12579 
                  'hdlType' => 'std_logic',
12580 
                  'width' => 1,
12581 
                },
12582 
                'data_out_x0' => {
12583 
                  'attributes' => {
12584 
                    'bin_pt' => 0,
12585 
                    'is_floating_block' => 1,
12586 
                    'must_be_hdl_vector' => 1,
12587 
                    'period' => 1,
12588 
                    'port_id' => 0,
12589 
                    'simulinkName' => 'INOUT_LOGIC/From Register10',
12590 
                    'type' => 'UFix_32_0',
12591 
                  },
12592 
                  'direction' => 'in',
12593 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12594 
                  'width' => 32,
12595 
                },
12596 
                'data_out_x1' => {
12597 
                  'attributes' => {
12598 
                    'bin_pt' => 0,
12599 
                    'is_floating_block' => 1,
12600 
                    'must_be_hdl_vector' => 1,
12601 
                    'period' => 1,
12602 
                    'port_id' => 0,
12603 
                    'simulinkName' => 'INOUT_LOGIC/From Register11',
12604 
                    'type' => 'UFix_32_0',
12605 
                  },
12606 
                  'direction' => 'in',
12607 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12608 
                  'width' => 32,
12609 
                },
12610 
                'data_out_x10' => {
12611 
                  'attributes' => {
12612 
                    'bin_pt' => 0,
12613 
                    'is_floating_block' => 1,
12614 
                    'must_be_hdl_vector' => 1,
12615 
                    'period' => 1,
12616 
                    'port_id' => 0,
12617 
                    'simulinkName' => 'INOUT_LOGIC/From Register2',
12618 
                    'type' => 'UFix_1_0',
12619 
                  },
12620 
                  'direction' => 'in',
12621 
                  'hdlType' => 'std_logic',
12622 
                  'width' => 1,
12623 
                },
12624 
                'data_out_x11' => {
12625 
                  'attributes' => {
12626 
                    'bin_pt' => 0,
12627 
                    'is_floating_block' => 1,
12628 
                    'must_be_hdl_vector' => 1,
12629 
                    'period' => 1,
12630 
                    'port_id' => 0,
12631 
                    'simulinkName' => 'INOUT_LOGIC/From Register20',
12632 
                    'type' => 'UFix_1_0',
12633 
                  },
12634 
                  'direction' => 'in',
12635 
                  'hdlType' => 'std_logic',
12636 
                  'width' => 1,
12637 
                },
12638 
                'data_out_x12' => {
12639 
                  'attributes' => {
12640 
                    'bin_pt' => 0,
12641 
                    'is_floating_block' => 1,
12642 
                    'must_be_hdl_vector' => 1,
12643 
                    'period' => 1,
12644 
                    'port_id' => 0,
12645 
                    'simulinkName' => 'INOUT_LOGIC/From Register21',
12646 
                    'type' => 'UFix_32_0',
12647 
                  },
12648 
                  'direction' => 'in',
12649 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12650 
                  'width' => 32,
12651 
                },
12652 
                'data_out_x13' => {
12653 
                  'attributes' => {
12654 
                    'bin_pt' => 0,
12655 
                    'is_floating_block' => 1,
12656 
                    'must_be_hdl_vector' => 1,
12657 
                    'period' => 1,
12658 
                    'port_id' => 0,
12659 
                    'simulinkName' => 'INOUT_LOGIC/From Register22',
12660 
                    'type' => 'UFix_1_0',
12661 
                  },
12662 
                  'direction' => 'in',
12663 
                  'hdlType' => 'std_logic',
12664 
                  'width' => 1,
12665 
                },
12666 
                'data_out_x14' => {
12667 
                  'attributes' => {
12668 
                    'bin_pt' => 0,
12669 
                    'is_floating_block' => 1,
12670 
                    'must_be_hdl_vector' => 1,
12671 
                    'period' => 1,
12672 
                    'port_id' => 0,
12673 
                    'simulinkName' => 'INOUT_LOGIC/From Register23',
12674 
                    'type' => 'UFix_32_0',
12675 
                  },
12676 
                  'direction' => 'in',
12677 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12678 
                  'width' => 32,
12679 
                },
12680 
                'data_out_x15' => {
12681 
                  'attributes' => {
12682 
                    'bin_pt' => 0,
12683 
                    'is_floating_block' => 1,
12684 
                    'must_be_hdl_vector' => 1,
12685 
                    'period' => 1,
12686 
                    'port_id' => 0,
12687 
                    'simulinkName' => 'INOUT_LOGIC/From Register24',
12688 
                    'type' => 'UFix_1_0',
12689 
                  },
12690 
                  'direction' => 'in',
12691 
                  'hdlType' => 'std_logic',
12692 
                  'width' => 1,
12693 
                },
12694 
                'data_out_x16' => {
12695 
                  'attributes' => {
12696 
                    'bin_pt' => 0,
12697 
                    'is_floating_block' => 1,
12698 
                    'must_be_hdl_vector' => 1,
12699 
                    'period' => 1,
12700 
                    'port_id' => 0,
12701 
                    'simulinkName' => 'INOUT_LOGIC/From Register25',
12702 
                    'type' => 'UFix_32_0',
12703 
                  },
12704 
                  'direction' => 'in',
12705 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12706 
                  'width' => 32,
12707 
                },
12708 
                'data_out_x17' => {
12709 
                  'attributes' => {
12710 
                    'bin_pt' => 0,
12711 
                    'is_floating_block' => 1,
12712 
                    'must_be_hdl_vector' => 1,
12713 
                    'period' => 1,
12714 
                    'port_id' => 0,
12715 
                    'simulinkName' => 'INOUT_LOGIC/From Register26',
12716 
                    'type' => 'UFix_1_0',
12717 
                  },
12718 
                  'direction' => 'in',
12719 
                  'hdlType' => 'std_logic',
12720 
                  'width' => 1,
12721 
                },
12722 
                'data_out_x18' => {
12723 
                  'attributes' => {
12724 
                    'bin_pt' => 0,
12725 
                    'is_floating_block' => 1,
12726 
                    'must_be_hdl_vector' => 1,
12727 
                    'period' => 1,
12728 
                    'port_id' => 0,
12729 
                    'simulinkName' => 'INOUT_LOGIC/From Register27',
12730 
                    'type' => 'UFix_32_0',
12731 
                  },
12732 
                  'direction' => 'in',
12733 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12734 
                  'width' => 32,
12735 
                },
12736 
                'data_out_x19' => {
12737 
                  'attributes' => {
12738 
                    'bin_pt' => 0,
12739 
                    'is_floating_block' => 1,
12740 
                    'must_be_hdl_vector' => 1,
12741 
                    'period' => 1,
12742 
                    'port_id' => 0,
12743 
                    'simulinkName' => 'INOUT_LOGIC/From Register28',
12744 
                    'type' => 'UFix_1_0',
12745 
                  },
12746 
                  'direction' => 'in',
12747 
                  'hdlType' => 'std_logic',
12748 
                  'width' => 1,
12749 
                },
12750 
                'data_out_x2' => {
12751 
                  'attributes' => {
12752 
                    'bin_pt' => 0,
12753 
                    'is_floating_block' => 1,
12754 
                    'must_be_hdl_vector' => 1,
12755 
                    'period' => 1,
12756 
                    'port_id' => 0,
12757 
                    'simulinkName' => 'INOUT_LOGIC/From Register12',
12758 
                    'type' => 'UFix_1_0',
12759 
                  },
12760 
                  'direction' => 'in',
12761 
                  'hdlType' => 'std_logic',
12762 
                  'width' => 1,
12763 
                },
12764 
                'data_out_x20' => {
12765 
                  'attributes' => {
12766 
                    'bin_pt' => 0,
12767 
                    'is_floating_block' => 1,
12768 
                    'must_be_hdl_vector' => 1,
12769 
                    'period' => 1,
12770 
                    'port_id' => 0,
12771 
                    'simulinkName' => 'INOUT_LOGIC/From Register3',
12772 
                    'type' => 'UFix_32_0',
12773 
                  },
12774 
                  'direction' => 'in',
12775 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12776 
                  'width' => 32,
12777 
                },
12778 
                'data_out_x21' => {
12779 
                  'attributes' => {
12780 
                    'bin_pt' => 0,
12781 
                    'is_floating_block' => 1,
12782 
                    'must_be_hdl_vector' => 1,
12783 
                    'period' => 1,
12784 
                    'port_id' => 0,
12785 
                    'simulinkName' => 'INOUT_LOGIC/From Register4',
12786 
                    'type' => 'UFix_1_0',
12787 
                  },
12788 
                  'direction' => 'in',
12789 
                  'hdlType' => 'std_logic',
12790 
                  'width' => 1,
12791 
                },
12792 
                'data_out_x22' => {
12793 
                  'attributes' => {
12794 
                    'bin_pt' => 0,
12795 
                    'is_floating_block' => 1,
12796 
                    'must_be_hdl_vector' => 1,
12797 
                    'period' => 1,
12798 
                    'port_id' => 0,
12799 
                    'simulinkName' => 'INOUT_LOGIC/From Register5',
12800 
                    'type' => 'UFix_32_0',
12801 
                  },
12802 
                  'direction' => 'in',
12803 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12804 
                  'width' => 32,
12805 
                },
12806 
                'data_out_x23' => {
12807 
                  'attributes' => {
12808 
                    'bin_pt' => 0,
12809 
                    'is_floating_block' => 1,
12810 
                    'must_be_hdl_vector' => 1,
12811 
                    'period' => 1,
12812 
                    'port_id' => 0,
12813 
                    'simulinkName' => 'INOUT_LOGIC/From Register6',
12814 
                    'type' => 'UFix_1_0',
12815 
                  },
12816 
                  'direction' => 'in',
12817 
                  'hdlType' => 'std_logic',
12818 
                  'width' => 1,
12819 
                },
12820 
                'data_out_x24' => {
12821 
                  'attributes' => {
12822 
                    'bin_pt' => 0,
12823 
                    'is_floating_block' => 1,
12824 
                    'must_be_hdl_vector' => 1,
12825 
                    'period' => 1,
12826 
                    'port_id' => 0,
12827 
                    'simulinkName' => 'INOUT_LOGIC/From Register7',
12828 
                    'type' => 'UFix_32_0',
12829 
                  },
12830 
                  'direction' => 'in',
12831 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12832 
                  'width' => 32,
12833 
                },
12834 
                'data_out_x25' => {
12835 
                  'attributes' => {
12836 
                    'bin_pt' => 0,
12837 
                    'is_floating_block' => 1,
12838 
                    'must_be_hdl_vector' => 1,
12839 
                    'period' => 1,
12840 
                    'port_id' => 0,
12841 
                    'simulinkName' => 'INOUT_LOGIC/From Register8',
12842 
                    'type' => 'UFix_32_0',
12843 
                  },
12844 
                  'direction' => 'in',
12845 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12846 
                  'width' => 32,
12847 
                },
12848 
                'data_out_x26' => {
12849 
                  'attributes' => {
12850 
                    'bin_pt' => 0,
12851 
                    'is_floating_block' => 1,
12852 
                    'must_be_hdl_vector' => 1,
12853 
                    'period' => 1,
12854 
                    'port_id' => 0,
12855 
                    'simulinkName' => 'INOUT_LOGIC/From Register9',
12856 
                    'type' => 'UFix_1_0',
12857 
                  },
12858 
                  'direction' => 'in',
12859 
                  'hdlType' => 'std_logic',
12860 
                  'width' => 1,
12861 
                },
12862 
                'data_out_x3' => {
12863 
                  'attributes' => {
12864 
                    'bin_pt' => 0,
12865 
                    'is_floating_block' => 1,
12866 
                    'must_be_hdl_vector' => 1,
12867 
                    'period' => 1,
12868 
                    'port_id' => 0,
12869 
                    'simulinkName' => 'INOUT_LOGIC/From Register13',
12870 
                    'type' => 'UFix_32_0',
12871 
                  },
12872 
                  'direction' => 'in',
12873 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12874 
                  'width' => 32,
12875 
                },
12876 
                'data_out_x4' => {
12877 
                  'attributes' => {
12878 
                    'bin_pt' => 0,
12879 
                    'is_floating_block' => 1,
12880 
                    'must_be_hdl_vector' => 1,
12881 
                    'period' => 1,
12882 
                    'port_id' => 0,
12883 
                    'simulinkName' => 'INOUT_LOGIC/From Register14',
12884 
                    'type' => 'UFix_1_0',
12885 
                  },
12886 
                  'direction' => 'in',
12887 
                  'hdlType' => 'std_logic',
12888 
                  'width' => 1,
12889 
                },
12890 
                'data_out_x5' => {
12891 
                  'attributes' => {
12892 
                    'bin_pt' => 0,
12893 
                    'is_floating_block' => 1,
12894 
                    'must_be_hdl_vector' => 1,
12895 
                    'period' => 1,
12896 
                    'port_id' => 0,
12897 
                    'simulinkName' => 'INOUT_LOGIC/From Register15',
12898 
                    'type' => 'UFix_32_0',
12899 
                  },
12900 
                  'direction' => 'in',
12901 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12902 
                  'width' => 32,
12903 
                },
12904 
                'data_out_x6' => {
12905 
                  'attributes' => {
12906 
                    'bin_pt' => 0,
12907 
                    'is_floating_block' => 1,
12908 
                    'must_be_hdl_vector' => 1,
12909 
                    'period' => 1,
12910 
                    'port_id' => 0,
12911 
                    'simulinkName' => 'INOUT_LOGIC/From Register16',
12912 
                    'type' => 'UFix_1_0',
12913 
                  },
12914 
                  'direction' => 'in',
12915 
                  'hdlType' => 'std_logic',
12916 
                  'width' => 1,
12917 
                },
12918 
                'data_out_x7' => {
12919 
                  'attributes' => {
12920 
                    'bin_pt' => 0,
12921 
                    'is_floating_block' => 1,
12922 
                    'must_be_hdl_vector' => 1,
12923 
                    'period' => 1,
12924 
                    'port_id' => 0,
12925 
                    'simulinkName' => 'INOUT_LOGIC/From Register17',
12926 
                    'type' => 'UFix_32_0',
12927 
                  },
12928 
                  'direction' => 'in',
12929 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12930 
                  'width' => 32,
12931 
                },
12932 
                'data_out_x8' => {
12933 
                  'attributes' => {
12934 
                    'bin_pt' => 0,
12935 
                    'is_floating_block' => 1,
12936 
                    'must_be_hdl_vector' => 1,
12937 
                    'period' => 1,
12938 
                    'port_id' => 0,
12939 
                    'simulinkName' => 'INOUT_LOGIC/From Register18',
12940 
                    'type' => 'UFix_1_0',
12941 
                  },
12942 
                  'direction' => 'in',
12943 
                  'hdlType' => 'std_logic',
12944 
                  'width' => 1,
12945 
                },
12946 
                'data_out_x9' => {
12947 
                  'attributes' => {
12948 
                    'bin_pt' => 0,
12949 
                    'is_floating_block' => 1,
12950 
                    'must_be_hdl_vector' => 1,
12951 
                    'period' => 1,
12952 
                    'port_id' => 0,
12953 
                    'simulinkName' => 'INOUT_LOGIC/From Register19',
12954 
                    'type' => 'UFix_32_0',
12955 
                  },
12956 
                  'direction' => 'in',
12957 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12958 
                  'width' => 32,
12959 
                },
12960 
                'debug_in_1i' => {
12961 
                  'attributes' => {
12962 
                    'bin_pt' => 0,
12963 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
12964 
                    'is_floating_block' => 1,
12965 
                    'is_gateway_port' => 1,
12966 
                    'must_be_hdl_vector' => 1,
12967 
                    'period' => 1,
12968 
                    'port_id' => 0,
12969 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_1i',
12970 
                    'source_block' => 'INOUT_LOGIC',
12971 
                    'timingConstraint' => 'none',
12972 
                    'type' => 'UFix_32_0',
12973 
                  },
12974 
                  'direction' => 'in',
12975 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12976 
                  'width' => 32,
12977 
                },
12978 
                'debug_in_2i' => {
12979 
                  'attributes' => {
12980 
                    'bin_pt' => 0,
12981 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
12982 
                    'is_floating_block' => 1,
12983 
                    'is_gateway_port' => 1,
12984 
                    'must_be_hdl_vector' => 1,
12985 
                    'period' => 1,
12986 
                    'port_id' => 0,
12987 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_2i',
12988 
                    'source_block' => 'INOUT_LOGIC',
12989 
                    'timingConstraint' => 'none',
12990 
                    'type' => 'UFix_32_0',
12991 
                  },
12992 
                  'direction' => 'in',
12993 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12994 
                  'width' => 32,
12995 
                },
12996 
                'debug_in_3i' => {
12997 
                  'attributes' => {
12998 
                    'bin_pt' => 0,
12999 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
13000 
                    'is_floating_block' => 1,
13001 
                    'is_gateway_port' => 1,
13002 
                    'must_be_hdl_vector' => 1,
13003 
                    'period' => 1,
13004 
                    'port_id' => 0,
13005 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_3i',
13006 
                    'source_block' => 'INOUT_LOGIC',
13007 
                    'timingConstraint' => 'none',
13008 
                    'type' => 'UFix_32_0',
13009 
                  },
13010 
                  'direction' => 'in',
13011 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13012 
                  'width' => 32,
13013 
                },
13014 
                'debug_in_4i' => {
13015 
                  'attributes' => {
13016 
                    'bin_pt' => 0,
13017 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
13018 
                    'is_floating_block' => 1,
13019 
                    'is_gateway_port' => 1,
13020 
                    'must_be_hdl_vector' => 1,
13021 
                    'period' => 1,
13022 
                    'port_id' => 0,
13023 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_4i',
13024 
                    'source_block' => 'INOUT_LOGIC',
13025 
                    'timingConstraint' => 'none',
13026 
                    'type' => 'UFix_32_0',
13027 
                  },
13028 
                  'direction' => 'in',
13029 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13030 
                  'width' => 32,
13031 
                },
13032 
                'dma_host2board_busy' => {
13033 
                  'attributes' => {
13034 
                    'bin_pt' => 0,
13035 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
13036 
                    'is_floating_block' => 1,
13037 
                    'is_gateway_port' => 1,
13038 
                    'must_be_hdl_vector' => 1,
13039 
                    'period' => 1,
13040 
                    'port_id' => 0,
13041 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Busy',
13042 
                    'source_block' => 'INOUT_LOGIC',
13043 
                    'timingConstraint' => 'none',
13044 
                    'type' => 'UFix_1_0',
13045 
                  },
13046 
                  'direction' => 'in',
13047 
                  'hdlType' => 'std_logic',
13048 
                  'width' => 1,
13049 
                },
13050 
                'dma_host2board_done' => {
13051 
                  'attributes' => {
13052 
                    'bin_pt' => 0,
13053 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
13054 
                    'is_floating_block' => 1,
13055 
                    'is_gateway_port' => 1,
13056 
                    'must_be_hdl_vector' => 1,
13057 
                    'period' => 1,
13058 
                    'port_id' => 0,
13059 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Done',
13060 
                    'source_block' => 'INOUT_LOGIC',
13061 
                    'timingConstraint' => 'none',
13062 
                    'type' => 'UFix_1_0',
13063 
                  },
13064 
                  'direction' => 'in',
13065 
                  'hdlType' => 'std_logic',
13066 
                  'width' => 1,
13067 
                },
13068 
                'en' => {
13069 
                  'attributes' => {
13070 
                    'bin_pt' => 0,
13071 
                    'is_floating_block' => 1,
13072 
                    'must_be_hdl_vector' => 1,
13073 
                    'period' => 1,
13074 
                    'port_id' => 0,
13075 
                    'simulinkName' => 'INOUT_LOGIC/en',
13076 
                    'type' => 'Bool',
13077 
                  },
13078 
                  'direction' => 'out',
13079 
                  'hdlType' => 'std_logic',
13080 
                  'width' => 1,
13081 
                },
13082 
                'en_x0' => {
13083 
                  'attributes' => {
13084 
                    'bin_pt' => 0,
13085 
                    'is_floating_block' => 1,
13086 
                    'must_be_hdl_vector' => 1,
13087 
                    'period' => 1,
13088 
                    'port_id' => 0,
13089 
                    'simulinkName' => 'INOUT_LOGIC/en',
13090 
                    'type' => 'Bool',
13091 
                  },
13092 
                  'direction' => 'out',
13093 
                  'hdlType' => 'std_logic',
13094 
                  'width' => 1,
13095 
                },
13096 
                'en_x1' => {
13097 
                  'attributes' => {
13098 
                    'bin_pt' => 0,
13099 
                    'is_floating_block' => 1,
13100 
                    'must_be_hdl_vector' => 1,
13101 
                    'period' => 1,
13102 
                    'port_id' => 0,
13103 
                    'simulinkName' => 'INOUT_LOGIC/en',
13104 
                    'type' => 'Bool',
13105 
                  },
13106 
                  'direction' => 'out',
13107 
                  'hdlType' => 'std_logic',
13108 
                  'width' => 1,
13109 
                },
13110 
                'en_x10' => {
13111 
                  'attributes' => {
13112 
                    'bin_pt' => 0,
13113 
                    'is_floating_block' => 1,
13114 
                    'must_be_hdl_vector' => 1,
13115 
                    'period' => 1,
13116 
                    'port_id' => 0,
13117 
                    'simulinkName' => 'INOUT_LOGIC/en',
13118 
                    'type' => 'Bool',
13119 
                  },
13120 
                  'direction' => 'out',
13121 
                  'hdlType' => 'std_logic',
13122 
                  'width' => 1,
13123 
                },
13124 
                'en_x11' => {
13125 
                  'attributes' => {
13126 
                    'bin_pt' => 0,
13127 
                    'is_floating_block' => 1,
13128 
                    'must_be_hdl_vector' => 1,
13129 
                    'period' => 1,
13130 
                    'port_id' => 0,
13131 
                    'simulinkName' => 'INOUT_LOGIC/en',
13132 
                    'type' => 'Bool',
13133 
                  },
13134 
                  'direction' => 'out',
13135 
                  'hdlType' => 'std_logic',
13136 
                  'width' => 1,
13137 
                },
13138 
                'en_x12' => {
13139 
                  'attributes' => {
13140 
                    'bin_pt' => 0,
13141 
                    'is_floating_block' => 1,
13142 
                    'must_be_hdl_vector' => 1,
13143 
                    'period' => 1,
13144 
                    'port_id' => 0,
13145 
                    'simulinkName' => 'INOUT_LOGIC/en',
13146 
                    'type' => 'Bool',
13147 
                  },
13148 
                  'direction' => 'out',
13149 
                  'hdlType' => 'std_logic',
13150 
                  'width' => 1,
13151 
                },
13152 
                'en_x13' => {
13153 
                  'attributes' => {
13154 
                    'bin_pt' => 0,
13155 
                    'is_floating_block' => 1,
13156 
                    'must_be_hdl_vector' => 1,
13157 
                    'period' => 1,
13158 
                    'port_id' => 0,
13159 
                    'simulinkName' => 'INOUT_LOGIC/en',
13160 
                    'type' => 'Bool',
13161 
                  },
13162 
                  'direction' => 'out',
13163 
                  'hdlType' => 'std_logic',
13164 
                  'width' => 1,
13165 
                },
13166 
                'en_x14' => {
13167 
                  'attributes' => {
13168 
                    'bin_pt' => 0,
13169 
                    'is_floating_block' => 1,
13170 
                    'must_be_hdl_vector' => 1,
13171 
                    'period' => 1,
13172 
                    'port_id' => 0,
13173 
                    'simulinkName' => 'INOUT_LOGIC/en',
13174 
                    'type' => 'Bool',
13175 
                  },
13176 
                  'direction' => 'out',
13177 
                  'hdlType' => 'std_logic',
13178 
                  'width' => 1,
13179 
                },
13180 
                'en_x15' => {
13181 
                  'attributes' => {
13182 
                    'bin_pt' => 0,
13183 
                    'is_floating_block' => 1,
13184 
                    'must_be_hdl_vector' => 1,
13185 
                    'period' => 1,
13186 
                    'port_id' => 0,
13187 
                    'simulinkName' => 'INOUT_LOGIC/en',
13188 
                    'type' => 'Bool',
13189 
                  },
13190 
                  'direction' => 'out',
13191 
                  'hdlType' => 'std_logic',
13192 
                  'width' => 1,
13193 
                },
13194 
                'en_x16' => {
13195 
                  'attributes' => {
13196 
                    'bin_pt' => 0,
13197 
                    'is_floating_block' => 1,
13198 
                    'must_be_hdl_vector' => 1,
13199 
                    'period' => 1,
13200 
                    'port_id' => 0,
13201 
                    'simulinkName' => 'INOUT_LOGIC/en',
13202 
                    'type' => 'Bool',
13203 
                  },
13204 
                  'direction' => 'out',
13205 
                  'hdlType' => 'std_logic',
13206 
                  'width' => 1,
13207 
                },
13208 
                'en_x17' => {
13209 
                  'attributes' => {
13210 
                    'bin_pt' => 0,
13211 
                    'is_floating_block' => 1,
13212 
                    'must_be_hdl_vector' => 1,
13213 
                    'period' => 1,
13214 
                    'port_id' => 0,
13215 
                    'simulinkName' => 'INOUT_LOGIC/en',
13216 
                    'type' => 'Bool',
13217 
                  },
13218 
                  'direction' => 'out',
13219 
                  'hdlType' => 'std_logic',
13220 
                  'width' => 1,
13221 
                },
13222 
                'en_x18' => {
13223 
                  'attributes' => {
13224 
                    'bin_pt' => 0,
13225 
                    'is_floating_block' => 1,
13226 
                    'must_be_hdl_vector' => 1,
13227 
                    'period' => 1,
13228 
                    'port_id' => 0,
13229 
                    'simulinkName' => 'INOUT_LOGIC/en',
13230 
                    'type' => 'Bool',
13231 
                  },
13232 
                  'direction' => 'out',
13233 
                  'hdlType' => 'std_logic',
13234 
                  'width' => 1,
13235 
                },
13236 
                'en_x19' => {
13237 
                  'attributes' => {
13238 
                    'bin_pt' => 0,
13239 
                    'is_floating_block' => 1,
13240 
                    'must_be_hdl_vector' => 1,
13241 
                    'period' => 1,
13242 
                    'port_id' => 0,
13243 
                    'simulinkName' => 'INOUT_LOGIC/en',
13244 
                    'type' => 'Bool',
13245 
                  },
13246 
                  'direction' => 'out',
13247 
                  'hdlType' => 'std_logic',
13248 
                  'width' => 1,
13249 
                },
13250 
                'en_x2' => {
13251 
                  'attributes' => {
13252 
                    'bin_pt' => 0,
13253 
                    'is_floating_block' => 1,
13254 
                    'must_be_hdl_vector' => 1,
13255 
                    'period' => 1,
13256 
                    'port_id' => 0,
13257 
                    'simulinkName' => 'INOUT_LOGIC/en',
13258 
                    'type' => 'Bool',
13259 
                  },
13260 
                  'direction' => 'out',
13261 
                  'hdlType' => 'std_logic',
13262 
                  'width' => 1,
13263 
                },
13264 
                'en_x20' => {
13265 
                  'attributes' => {
13266 
                    'bin_pt' => 0,
13267 
                    'is_floating_block' => 1,
13268 
                    'must_be_hdl_vector' => 1,
13269 
                    'period' => 1,
13270 
                    'port_id' => 0,
13271 
                    'simulinkName' => 'INOUT_LOGIC/en',
13272 
                    'type' => 'Bool',
13273 
                  },
13274 
                  'direction' => 'out',
13275 
                  'hdlType' => 'std_logic',
13276 
                  'width' => 1,
13277 
                },
13278 
                'en_x21' => {
13279 
                  'attributes' => {
13280 
                    'bin_pt' => 0,
13281 
                    'is_floating_block' => 1,
13282 
                    'must_be_hdl_vector' => 1,
13283 
                    'period' => 1,
13284 
                    'port_id' => 0,
13285 
                    'simulinkName' => 'INOUT_LOGIC/en',
13286 
                    'type' => 'Bool',
13287 
                  },
13288 
                  'direction' => 'out',
13289 
                  'hdlType' => 'std_logic',
13290 
                  'width' => 1,
13291 
                },
13292 
                'en_x22' => {
13293 
                  'attributes' => {
13294 
                    'bin_pt' => 0,
13295 
                    'is_floating_block' => 1,
13296 
                    'must_be_hdl_vector' => 1,
13297 
                    'period' => 1,
13298 
                    'port_id' => 0,
13299 
                    'simulinkName' => 'INOUT_LOGIC/en',
13300 
                    'type' => 'Bool',
13301 
                  },
13302 
                  'direction' => 'out',
13303 
                  'hdlType' => 'std_logic',
13304 
                  'width' => 1,
13305 
                },
13306 
                'en_x23' => {
13307 
                  'attributes' => {
13308 
                    'bin_pt' => 0,
13309 
                    'is_floating_block' => 1,
13310 
                    'must_be_hdl_vector' => 1,
13311 
                    'period' => 1,
13312 
                    'port_id' => 0,
13313 
                    'simulinkName' => 'INOUT_LOGIC/en',
13314 
                    'type' => 'Bool',
13315 
                  },
13316 
                  'direction' => 'out',
13317 
                  'hdlType' => 'std_logic',
13318 
                  'width' => 1,
13319 
                },
13320 
                'en_x24' => {
13321 
                  'attributes' => {
13322 
                    'bin_pt' => 0,
13323 
                    'is_floating_block' => 1,
13324 
                    'must_be_hdl_vector' => 1,
13325 
                    'period' => 1,
13326 
                    'port_id' => 0,
13327 
                    'simulinkName' => 'INOUT_LOGIC/en',
13328 
                    'type' => 'Bool',
13329 
                  },
13330 
                  'direction' => 'out',
13331 
                  'hdlType' => 'std_logic',
13332 
                  'width' => 1,
13333 
                },
13334 
                'en_x25' => {
13335 
                  'attributes' => {
13336 
                    'bin_pt' => 0,
13337 
                    'is_floating_block' => 1,
13338 
                    'must_be_hdl_vector' => 1,
13339 
                    'period' => 1,
13340 
                    'port_id' => 0,
13341 
                    'simulinkName' => 'INOUT_LOGIC/en',
13342 
                    'type' => 'Bool',
13343 
                  },
13344 
                  'direction' => 'out',
13345 
                  'hdlType' => 'std_logic',
13346 
                  'width' => 1,
13347 
                },
13348 
                'en_x26' => {
13349 
                  'attributes' => {
13350 
                    'bin_pt' => 0,
13351 
                    'is_floating_block' => 1,
13352 
                    'must_be_hdl_vector' => 1,
13353 
                    'period' => 1,
13354 
                    'port_id' => 0,
13355 
                    'simulinkName' => 'INOUT_LOGIC/en',
13356 
                    'type' => 'Bool',
13357 
                  },
13358 
                  'direction' => 'out',
13359 
                  'hdlType' => 'std_logic',
13360 
                  'width' => 1,
13361 
                },
13362 
                'en_x27' => {
13363 
                  'attributes' => {
13364 
                    'bin_pt' => 0,
13365 
                    'is_floating_block' => 1,
13366 
                    'must_be_hdl_vector' => 1,
13367 
                    'period' => 1,
13368 
                    'port_id' => 0,
13369 
                    'simulinkName' => 'INOUT_LOGIC/en',
13370 
                    'type' => 'Bool',
13371 
                  },
13372 
                  'direction' => 'out',
13373 
                  'hdlType' => 'std_logic',
13374 
                  'width' => 1,
13375 
                },
13376 
                'en_x28' => {
13377 
                  'attributes' => {
13378 
                    'bin_pt' => 0,
13379 
                    'is_floating_block' => 1,
13380 
                    'must_be_hdl_vector' => 1,
13381 
                    'period' => 1,
13382 
                    'port_id' => 0,
13383 
                    'simulinkName' => 'INOUT_LOGIC/en',
13384 
                    'type' => 'Bool',
13385 
                  },
13386 
                  'direction' => 'out',
13387 
                  'hdlType' => 'std_logic',
13388 
                  'width' => 1,
13389 
                },
13390 
                'en_x29' => {
13391 
                  'attributes' => {
13392 
                    'bin_pt' => 0,
13393 
                    'is_floating_block' => 1,
13394 
                    'must_be_hdl_vector' => 1,
13395 
                    'period' => 1,
13396 
                    'port_id' => 0,
13397 
                    'simulinkName' => 'INOUT_LOGIC/en',
13398 
                    'type' => 'Bool',
13399 
                  },
13400 
                  'direction' => 'out',
13401 
                  'hdlType' => 'std_logic',
13402 
                  'width' => 1,
13403 
                },
13404 
                'en_x3' => {
13405 
                  'attributes' => {
13406 
                    'bin_pt' => 0,
13407 
                    'is_floating_block' => 1,
13408 
                    'must_be_hdl_vector' => 1,
13409 
                    'period' => 1,
13410 
                    'port_id' => 0,
13411 
                    'simulinkName' => 'INOUT_LOGIC/en',
13412 
                    'type' => 'Bool',
13413 
                  },
13414 
                  'direction' => 'out',
13415 
                  'hdlType' => 'std_logic',
13416 
                  'width' => 1,
13417 
                },
13418 
                'en_x30' => {
13419 
                  'attributes' => {
13420 
                    'bin_pt' => 0,
13421 
                    'is_floating_block' => 1,
13422 
                    'must_be_hdl_vector' => 1,
13423 
                    'period' => 1,
13424 
                    'port_id' => 0,
13425 
                    'simulinkName' => 'INOUT_LOGIC/en',
13426 
                    'type' => 'Bool',
13427 
                  },
13428 
                  'direction' => 'out',
13429 
                  'hdlType' => 'std_logic',
13430 
                  'width' => 1,
13431 
                },
13432 
                'en_x31' => {
13433 
                  'attributes' => {
13434 
                    'bin_pt' => 0,
13435 
                    'is_floating_block' => 1,
13436 
                    'must_be_hdl_vector' => 1,
13437 
                    'period' => 1,
13438 
                    'port_id' => 0,
13439 
                    'simulinkName' => 'INOUT_LOGIC/en',
13440 
                    'type' => 'Bool',
13441 
                  },
13442 
                  'direction' => 'out',
13443 
                  'hdlType' => 'std_logic',
13444 
                  'width' => 1,
13445 
                },
13446 
                'en_x32' => {
13447 
                  'attributes' => {
13448 
                    'bin_pt' => 0,
13449 
                    'is_floating_block' => 1,
13450 
                    'must_be_hdl_vector' => 1,
13451 
                    'period' => 1,
13452 
                    'port_id' => 0,
13453 
                    'simulinkName' => 'INOUT_LOGIC/en',
13454 
                    'type' => 'Bool',
13455 
                  },
13456 
                  'direction' => 'out',
13457 
                  'hdlType' => 'std_logic',
13458 
                  'width' => 1,
13459 
                },
13460 
                'en_x4' => {
13461 
                  'attributes' => {
13462 
                    'bin_pt' => 0,
13463 
                    'is_floating_block' => 1,
13464 
                    'must_be_hdl_vector' => 1,
13465 
                    'period' => 1,
13466 
                    'port_id' => 0,
13467 
                    'simulinkName' => 'INOUT_LOGIC/en',
13468 
                    'type' => 'Bool',
13469 
                  },
13470 
                  'direction' => 'out',
13471 
                  'hdlType' => 'std_logic',
13472 
                  'width' => 1,
13473 
                },
13474 
                'en_x5' => {
13475 
                  'attributes' => {
13476 
                    'bin_pt' => 0,
13477 
                    'is_floating_block' => 1,
13478 
                    'must_be_hdl_vector' => 1,
13479 
                    'period' => 1,
13480 
                    'port_id' => 0,
13481 
                    'simulinkName' => 'INOUT_LOGIC/en',
13482 
                    'type' => 'Bool',
13483 
                  },
13484 
                  'direction' => 'out',
13485 
                  'hdlType' => 'std_logic',
13486 
                  'width' => 1,
13487 
                },
13488 
                'en_x6' => {
13489 
                  'attributes' => {
13490 
                    'bin_pt' => 0,
13491 
                    'is_floating_block' => 1,
13492 
                    'must_be_hdl_vector' => 1,
13493 
                    'period' => 1,
13494 
                    'port_id' => 0,
13495 
                    'simulinkName' => 'INOUT_LOGIC/en',
13496 
                    'type' => 'Bool',
13497 
                  },
13498 
                  'direction' => 'out',
13499 
                  'hdlType' => 'std_logic',
13500 
                  'width' => 1,
13501 
                },
13502 
                'en_x7' => {
13503 
                  'attributes' => {
13504 
                    'bin_pt' => 0,
13505 
                    'is_floating_block' => 1,
13506 
                    'must_be_hdl_vector' => 1,
13507 
                    'period' => 1,
13508 
                    'port_id' => 0,
13509 
                    'simulinkName' => 'INOUT_LOGIC/en',
13510 
                    'type' => 'Bool',
13511 
                  },
13512 
                  'direction' => 'out',
13513 
                  'hdlType' => 'std_logic',
13514 
                  'width' => 1,
13515 
                },
13516 
                'en_x8' => {
13517 
                  'attributes' => {
13518 
                    'bin_pt' => 0,
13519 
                    'is_floating_block' => 1,
13520 
                    'must_be_hdl_vector' => 1,
13521 
                    'period' => 1,
13522 
                    'port_id' => 0,
13523 
                    'simulinkName' => 'INOUT_LOGIC/en',
13524 
                    'type' => 'Bool',
13525 
                  },
13526 
                  'direction' => 'out',
13527 
                  'hdlType' => 'std_logic',
13528 
                  'width' => 1,
13529 
                },
13530 
                'en_x9' => {
13531 
                  'attributes' => {
13532 
                    'bin_pt' => 0,
13533 
                    'is_floating_block' => 1,
13534 
                    'must_be_hdl_vector' => 1,
13535 
                    'period' => 1,
13536 
                    'port_id' => 0,
13537 
                    'simulinkName' => 'INOUT_LOGIC/en',
13538 
                    'type' => 'Bool',
13539 
                  },
13540 
                  'direction' => 'out',
13541 
                  'hdlType' => 'std_logic',
13542 
                  'width' => 1,
13543 
                },
13544 
                'reg01_rd' => {
13545 
                  'attributes' => {
13546 
                    'bin_pt' => 0,
13547 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
13548 
                    'is_floating_block' => 1,
13549 
                    'is_gateway_port' => 1,
13550 
                    'must_be_hdl_vector' => 1,
13551 
                    'period' => 1,
13552 
                    'port_id' => 0,
13553 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rd',
13554 
                    'source_block' => 'INOUT_LOGIC',
13555 
                    'timingConstraint' => 'none',
13556 
                    'type' => 'UFix_32_0',
13557 
                  },
13558 
                  'direction' => 'out',
13559 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13560 
                  'width' => 32,
13561 
                },
13562 
                'reg01_rv' => {
13563 
                  'attributes' => {
13564 
                    'bin_pt' => 0,
13565 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
13566 
                    'is_floating_block' => 1,
13567 
                    'is_gateway_port' => 1,
13568 
                    'must_be_hdl_vector' => 1,
13569 
                    'period' => 1,
13570 
                    'port_id' => 0,
13571 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rv',
13572 
                    'source_block' => 'INOUT_LOGIC',
13573 
                    'timingConstraint' => 'none',
13574 
                    'type' => 'UFix_1_0',
13575 
                  },
13576 
                  'direction' => 'out',
13577 
                  'hdlType' => 'std_logic',
13578 
                  'width' => 1,
13579 
                },
13580 
                'reg01_td' => {
13581 
                  'attributes' => {
13582 
                    'bin_pt' => 0,
13583 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
13584 
                    'is_floating_block' => 1,
13585 
                    'is_gateway_port' => 1,
13586 
                    'must_be_hdl_vector' => 1,
13587 
                    'period' => 1,
13588 
                    'port_id' => 0,
13589 
                    'simulinkName' => 'INOUT_LOGIC/reg01_td',
13590 
                    'source_block' => 'INOUT_LOGIC',
13591 
                    'timingConstraint' => 'none',
13592 
                    'type' => 'UFix_32_0',
13593 
                  },
13594 
                  'direction' => 'in',
13595 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13596 
                  'width' => 32,
13597 
                },
13598 
                'reg01_tv' => {
13599 
                  'attributes' => {
13600 
                    'bin_pt' => 0,
13601 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
13602 
                    'is_floating_block' => 1,
13603 
                    'is_gateway_port' => 1,
13604 
                    'must_be_hdl_vector' => 1,
13605 
                    'period' => 1,
13606 
                    'port_id' => 0,
13607 
                    'simulinkName' => 'INOUT_LOGIC/reg01_tv',
13608 
                    'source_block' => 'INOUT_LOGIC',
13609 
                    'timingConstraint' => 'none',
13610 
                    'type' => 'Bool',
13611 
                  },
13612 
                  'direction' => 'in',
13613 
                  'hdlType' => 'std_logic',
13614 
                  'width' => 1,
13615 
                },
13616 
                'reg02_rd' => {
13617 
                  'attributes' => {
13618 
                    'bin_pt' => 0,
13619 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
13620 
                    'is_floating_block' => 1,
13621 
                    'is_gateway_port' => 1,
13622 
                    'must_be_hdl_vector' => 1,
13623 
                    'period' => 1,
13624 
                    'port_id' => 0,
13625 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rd',
13626 
                    'source_block' => 'INOUT_LOGIC',
13627 
                    'timingConstraint' => 'none',
13628 
                    'type' => 'UFix_32_0',
13629 
                  },
13630 
                  'direction' => 'out',
13631 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13632 
                  'width' => 32,
13633 
                },
13634 
                'reg02_rv' => {
13635 
                  'attributes' => {
13636 
                    'bin_pt' => 0,
13637 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
13638 
                    'is_floating_block' => 1,
13639 
                    'is_gateway_port' => 1,
13640 
                    'must_be_hdl_vector' => 1,
13641 
                    'period' => 1,
13642 
                    'port_id' => 0,
13643 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rv',
13644 
                    'source_block' => 'INOUT_LOGIC',
13645 
                    'timingConstraint' => 'none',
13646 
                    'type' => 'UFix_1_0',
13647 
                  },
13648 
                  'direction' => 'out',
13649 
                  'hdlType' => 'std_logic',
13650 
                  'width' => 1,
13651 
                },
13652 
                'reg02_td' => {
13653 
                  'attributes' => {
13654 
                    'bin_pt' => 0,
13655 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
13656 
                    'is_floating_block' => 1,
13657 
                    'is_gateway_port' => 1,
13658 
                    'must_be_hdl_vector' => 1,
13659 
                    'period' => 1,
13660 
                    'port_id' => 0,
13661 
                    'simulinkName' => 'INOUT_LOGIC/reg02_td',
13662 
                    'source_block' => 'INOUT_LOGIC',
13663 
                    'timingConstraint' => 'none',
13664 
                    'type' => 'UFix_32_0',
13665 
                  },
13666 
                  'direction' => 'in',
13667 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13668 
                  'width' => 32,
13669 
                },
13670 
                'reg02_tv' => {
13671 
                  'attributes' => {
13672 
                    'bin_pt' => 0,
13673 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
13674 
                    'is_floating_block' => 1,
13675 
                    'is_gateway_port' => 1,
13676 
                    'must_be_hdl_vector' => 1,
13677 
                    'period' => 1,
13678 
                    'port_id' => 0,
13679 
                    'simulinkName' => 'INOUT_LOGIC/reg02_tv',
13680 
                    'source_block' => 'INOUT_LOGIC',
13681 
                    'timingConstraint' => 'none',
13682 
                    'type' => 'Bool',
13683 
                  },
13684 
                  'direction' => 'in',
13685 
                  'hdlType' => 'std_logic',
13686 
                  'width' => 1,
13687 
                },
13688 
                'reg03_rd' => {
13689 
                  'attributes' => {
13690 
                    'bin_pt' => 0,
13691 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
13692 
                    'is_floating_block' => 1,
13693 
                    'is_gateway_port' => 1,
13694 
                    'must_be_hdl_vector' => 1,
13695 
                    'period' => 1,
13696 
                    'port_id' => 0,
13697 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rd',
13698 
                    'source_block' => 'INOUT_LOGIC',
13699 
                    'timingConstraint' => 'none',
13700 
                    'type' => 'UFix_32_0',
13701 
                  },
13702 
                  'direction' => 'out',
13703 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13704 
                  'width' => 32,
13705 
                },
13706 
                'reg03_rv' => {
13707 
                  'attributes' => {
13708 
                    'bin_pt' => 0,
13709 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
13710 
                    'is_floating_block' => 1,
13711 
                    'is_gateway_port' => 1,
13712 
                    'must_be_hdl_vector' => 1,
13713 
                    'period' => 1,
13714 
                    'port_id' => 0,
13715 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rv',
13716 
                    'source_block' => 'INOUT_LOGIC',
13717 
                    'timingConstraint' => 'none',
13718 
                    'type' => 'UFix_1_0',
13719 
                  },
13720 
                  'direction' => 'out',
13721 
                  'hdlType' => 'std_logic',
13722 
                  'width' => 1,
13723 
                },
13724 
                'reg03_td' => {
13725 
                  'attributes' => {
13726 
                    'bin_pt' => 0,
13727 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
13728 
                    'is_floating_block' => 1,
13729 
                    'is_gateway_port' => 1,
13730 
                    'must_be_hdl_vector' => 1,
13731 
                    'period' => 1,
13732 
                    'port_id' => 0,
13733 
                    'simulinkName' => 'INOUT_LOGIC/reg03_td',
13734 
                    'source_block' => 'INOUT_LOGIC',
13735 
                    'timingConstraint' => 'none',
13736 
                    'type' => 'UFix_32_0',
13737 
                  },
13738 
                  'direction' => 'in',
13739 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13740 
                  'width' => 32,
13741 
                },
13742 
                'reg03_tv' => {
13743 
                  'attributes' => {
13744 
                    'bin_pt' => 0,
13745 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
13746 
                    'is_floating_block' => 1,
13747 
                    'is_gateway_port' => 1,
13748 
                    'must_be_hdl_vector' => 1,
13749 
                    'period' => 1,
13750 
                    'port_id' => 0,
13751 
                    'simulinkName' => 'INOUT_LOGIC/reg03_tv',
13752 
                    'source_block' => 'INOUT_LOGIC',
13753 
                    'timingConstraint' => 'none',
13754 
                    'type' => 'Bool',
13755 
                  },
13756 
                  'direction' => 'in',
13757 
                  'hdlType' => 'std_logic',
13758 
                  'width' => 1,
13759 
                },
13760 
                'reg04_rd' => {
13761 
                  'attributes' => {
13762 
                    'bin_pt' => 0,
13763 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
13764 
                    'is_floating_block' => 1,
13765 
                    'is_gateway_port' => 1,
13766 
                    'must_be_hdl_vector' => 1,
13767 
                    'period' => 1,
13768 
                    'port_id' => 0,
13769 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rd',
13770 
                    'source_block' => 'INOUT_LOGIC',
13771 
                    'timingConstraint' => 'none',
13772 
                    'type' => 'UFix_32_0',
13773 
                  },
13774 
                  'direction' => 'out',
13775 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13776 
                  'width' => 32,
13777 
                },
13778 
                'reg04_rv' => {
13779 
                  'attributes' => {
13780 
                    'bin_pt' => 0,
13781 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
13782 
                    'is_floating_block' => 1,
13783 
                    'is_gateway_port' => 1,
13784 
                    'must_be_hdl_vector' => 1,
13785 
                    'period' => 1,
13786 
                    'port_id' => 0,
13787 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rv',
13788 
                    'source_block' => 'INOUT_LOGIC',
13789 
                    'timingConstraint' => 'none',
13790 
                    'type' => 'UFix_1_0',
13791 
                  },
13792 
                  'direction' => 'out',
13793 
                  'hdlType' => 'std_logic',
13794 
                  'width' => 1,
13795 
                },
13796 
                'reg04_td' => {
13797 
                  'attributes' => {
13798 
                    'bin_pt' => 0,
13799 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
13800 
                    'is_floating_block' => 1,
13801 
                    'is_gateway_port' => 1,
13802 
                    'must_be_hdl_vector' => 1,
13803 
                    'period' => 1,
13804 
                    'port_id' => 0,
13805 
                    'simulinkName' => 'INOUT_LOGIC/reg04_td',
13806 
                    'source_block' => 'INOUT_LOGIC',
13807 
                    'timingConstraint' => 'none',
13808 
                    'type' => 'UFix_32_0',
13809 
                  },
13810 
                  'direction' => 'in',
13811 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13812 
                  'width' => 32,
13813 
                },
13814 
                'reg04_tv' => {
13815 
                  'attributes' => {
13816 
                    'bin_pt' => 0,
13817 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
13818 
                    'is_floating_block' => 1,
13819 
                    'is_gateway_port' => 1,
13820 
                    'must_be_hdl_vector' => 1,
13821 
                    'period' => 1,
13822 
                    'port_id' => 0,
13823 
                    'simulinkName' => 'INOUT_LOGIC/reg04_tv',
13824 
                    'source_block' => 'INOUT_LOGIC',
13825 
                    'timingConstraint' => 'none',
13826 
                    'type' => 'Bool',
13827 
                  },
13828 
                  'direction' => 'in',
13829 
                  'hdlType' => 'std_logic',
13830 
                  'width' => 1,
13831 
                },
13832 
                'reg05_rd' => {
13833 
                  'attributes' => {
13834 
                    'bin_pt' => 0,
13835 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
13836 
                    'is_floating_block' => 1,
13837 
                    'is_gateway_port' => 1,
13838 
                    'must_be_hdl_vector' => 1,
13839 
                    'period' => 1,
13840 
                    'port_id' => 0,
13841 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rd',
13842 
                    'source_block' => 'INOUT_LOGIC',
13843 
                    'timingConstraint' => 'none',
13844 
                    'type' => 'UFix_32_0',
13845 
                  },
13846 
                  'direction' => 'out',
13847 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13848 
                  'width' => 32,
13849 
                },
13850 
                'reg05_rv' => {
13851 
                  'attributes' => {
13852 
                    'bin_pt' => 0,
13853 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
13854 
                    'is_floating_block' => 1,
13855 
                    'is_gateway_port' => 1,
13856 
                    'must_be_hdl_vector' => 1,
13857 
                    'period' => 1,
13858 
                    'port_id' => 0,
13859 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rv',
13860 
                    'source_block' => 'INOUT_LOGIC',
13861 
                    'timingConstraint' => 'none',
13862 
                    'type' => 'UFix_1_0',
13863 
                  },
13864 
                  'direction' => 'out',
13865 
                  'hdlType' => 'std_logic',
13866 
                  'width' => 1,
13867 
                },
13868 
                'reg05_td' => {
13869 
                  'attributes' => {
13870 
                    'bin_pt' => 0,
13871 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
13872 
                    'is_floating_block' => 1,
13873 
                    'is_gateway_port' => 1,
13874 
                    'must_be_hdl_vector' => 1,
13875 
                    'period' => 1,
13876 
                    'port_id' => 0,
13877 
                    'simulinkName' => 'INOUT_LOGIC/reg05_td',
13878 
                    'source_block' => 'INOUT_LOGIC',
13879 
                    'timingConstraint' => 'none',
13880 
                    'type' => 'UFix_32_0',
13881 
                  },
13882 
                  'direction' => 'in',
13883 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13884 
                  'width' => 32,
13885 
                },
13886 
                'reg05_tv' => {
13887 
                  'attributes' => {
13888 
                    'bin_pt' => 0,
13889 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
13890 
                    'is_floating_block' => 1,
13891 
                    'is_gateway_port' => 1,
13892 
                    'must_be_hdl_vector' => 1,
13893 
                    'period' => 1,
13894 
                    'port_id' => 0,
13895 
                    'simulinkName' => 'INOUT_LOGIC/reg05_tv',
13896 
                    'source_block' => 'INOUT_LOGIC',
13897 
                    'timingConstraint' => 'none',
13898 
                    'type' => 'Bool',
13899 
                  },
13900 
                  'direction' => 'in',
13901 
                  'hdlType' => 'std_logic',
13902 
                  'width' => 1,
13903 
                },
13904 
                'reg06_rd' => {
13905 
                  'attributes' => {
13906 
                    'bin_pt' => 0,
13907 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
13908 
                    'is_floating_block' => 1,
13909 
                    'is_gateway_port' => 1,
13910 
                    'must_be_hdl_vector' => 1,
13911 
                    'period' => 1,
13912 
                    'port_id' => 0,
13913 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rd',
13914 
                    'source_block' => 'INOUT_LOGIC',
13915 
                    'timingConstraint' => 'none',
13916 
                    'type' => 'UFix_32_0',
13917 
                  },
13918 
                  'direction' => 'out',
13919 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13920 
                  'width' => 32,
13921 
                },
13922 
                'reg06_rv' => {
13923 
                  'attributes' => {
13924 
                    'bin_pt' => 0,
13925 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
13926 
                    'is_floating_block' => 1,
13927 
                    'is_gateway_port' => 1,
13928 
                    'must_be_hdl_vector' => 1,
13929 
                    'period' => 1,
13930 
                    'port_id' => 0,
13931 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rv',
13932 
                    'source_block' => 'INOUT_LOGIC',
13933 
                    'timingConstraint' => 'none',
13934 
                    'type' => 'UFix_1_0',
13935 
                  },
13936 
                  'direction' => 'out',
13937 
                  'hdlType' => 'std_logic',
13938 
                  'width' => 1,
13939 
                },
13940 
                'reg06_td' => {
13941 
                  'attributes' => {
13942 
                    'bin_pt' => 0,
13943 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
13944 
                    'is_floating_block' => 1,
13945 
                    'is_gateway_port' => 1,
13946 
                    'must_be_hdl_vector' => 1,
13947 
                    'period' => 1,
13948 
                    'port_id' => 0,
13949 
                    'simulinkName' => 'INOUT_LOGIC/reg06_td',
13950 
                    'source_block' => 'INOUT_LOGIC',
13951 
                    'timingConstraint' => 'none',
13952 
                    'type' => 'UFix_32_0',
13953 
                  },
13954 
                  'direction' => 'in',
13955 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13956 
                  'width' => 32,
13957 
                },
13958 
                'reg06_tv' => {
13959 
                  'attributes' => {
13960 
                    'bin_pt' => 0,
13961 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
13962 
                    'is_floating_block' => 1,
13963 
                    'is_gateway_port' => 1,
13964 
                    'must_be_hdl_vector' => 1,
13965 
                    'period' => 1,
13966 
                    'port_id' => 0,
13967 
                    'simulinkName' => 'INOUT_LOGIC/reg06_tv',
13968 
                    'source_block' => 'INOUT_LOGIC',
13969 
                    'timingConstraint' => 'none',
13970 
                    'type' => 'Bool',
13971 
                  },
13972 
                  'direction' => 'in',
13973 
                  'hdlType' => 'std_logic',
13974 
                  'width' => 1,
13975 
                },
13976 
                'reg07_rd' => {
13977 
                  'attributes' => {
13978 
                    'bin_pt' => 0,
13979 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
13980 
                    'is_floating_block' => 1,
13981 
                    'is_gateway_port' => 1,
13982 
                    'must_be_hdl_vector' => 1,
13983 
                    'period' => 1,
13984 
                    'port_id' => 0,
13985 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rd',
13986 
                    'source_block' => 'INOUT_LOGIC',
13987 
                    'timingConstraint' => 'none',
13988 
                    'type' => 'UFix_32_0',
13989 
                  },
13990 
                  'direction' => 'out',
13991 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13992 
                  'width' => 32,
13993 
                },
13994 
                'reg07_rv' => {
13995 
                  'attributes' => {
13996 
                    'bin_pt' => 0,
13997 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
13998 
                    'is_floating_block' => 1,
13999 
                    'is_gateway_port' => 1,
14000 
                    'must_be_hdl_vector' => 1,
14001 
                    'period' => 1,
14002 
                    'port_id' => 0,
14003 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rv',
14004 
                    'source_block' => 'INOUT_LOGIC',
14005 
                    'timingConstraint' => 'none',
14006 
                    'type' => 'UFix_1_0',
14007 
                  },
14008 
                  'direction' => 'out',
14009 
                  'hdlType' => 'std_logic',
14010 
                  'width' => 1,
14011 
                },
14012 
                'reg07_td' => {
14013 
                  'attributes' => {
14014 
                    'bin_pt' => 0,
14015 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
14016 
                    'is_floating_block' => 1,
14017 
                    'is_gateway_port' => 1,
14018 
                    'must_be_hdl_vector' => 1,
14019 
                    'period' => 1,
14020 
                    'port_id' => 0,
14021 
                    'simulinkName' => 'INOUT_LOGIC/reg07_td',
14022 
                    'source_block' => 'INOUT_LOGIC',
14023 
                    'timingConstraint' => 'none',
14024 
                    'type' => 'UFix_32_0',
14025 
                  },
14026 
                  'direction' => 'in',
14027 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14028 
                  'width' => 32,
14029 
                },
14030 
                'reg07_tv' => {
14031 
                  'attributes' => {
14032 
                    'bin_pt' => 0,
14033 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
14034 
                    'is_floating_block' => 1,
14035 
                    'is_gateway_port' => 1,
14036 
                    'must_be_hdl_vector' => 1,
14037 
                    'period' => 1,
14038 
                    'port_id' => 0,
14039 
                    'simulinkName' => 'INOUT_LOGIC/reg07_tv',
14040 
                    'source_block' => 'INOUT_LOGIC',
14041 
                    'timingConstraint' => 'none',
14042 
                    'type' => 'Bool',
14043 
                  },
14044 
                  'direction' => 'in',
14045 
                  'hdlType' => 'std_logic',
14046 
                  'width' => 1,
14047 
                },
14048 
                'reg08_rd' => {
14049 
                  'attributes' => {
14050 
                    'bin_pt' => 0,
14051 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
14052 
                    'is_floating_block' => 1,
14053 
                    'is_gateway_port' => 1,
14054 
                    'must_be_hdl_vector' => 1,
14055 
                    'period' => 1,
14056 
                    'port_id' => 0,
14057 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rd',
14058 
                    'source_block' => 'INOUT_LOGIC',
14059 
                    'timingConstraint' => 'none',
14060 
                    'type' => 'UFix_32_0',
14061 
                  },
14062 
                  'direction' => 'out',
14063 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14064 
                  'width' => 32,
14065 
                },
14066 
                'reg08_rv' => {
14067 
                  'attributes' => {
14068 
                    'bin_pt' => 0,
14069 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
14070 
                    'is_floating_block' => 1,
14071 
                    'is_gateway_port' => 1,
14072 
                    'must_be_hdl_vector' => 1,
14073 
                    'period' => 1,
14074 
                    'port_id' => 0,
14075 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rv',
14076 
                    'source_block' => 'INOUT_LOGIC',
14077 
                    'timingConstraint' => 'none',
14078 
                    'type' => 'UFix_1_0',
14079 
                  },
14080 
                  'direction' => 'out',
14081 
                  'hdlType' => 'std_logic',
14082 
                  'width' => 1,
14083 
                },
14084 
                'reg08_td' => {
14085 
                  'attributes' => {
14086 
                    'bin_pt' => 0,
14087 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
14088 
                    'is_floating_block' => 1,
14089 
                    'is_gateway_port' => 1,
14090 
                    'must_be_hdl_vector' => 1,
14091 
                    'period' => 1,
14092 
                    'port_id' => 0,
14093 
                    'simulinkName' => 'INOUT_LOGIC/reg08_td',
14094 
                    'source_block' => 'INOUT_LOGIC',
14095 
                    'timingConstraint' => 'none',
14096 
                    'type' => 'UFix_32_0',
14097 
                  },
14098 
                  'direction' => 'in',
14099 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14100 
                  'width' => 32,
14101 
                },
14102 
                'reg08_tv' => {
14103 
                  'attributes' => {
14104 
                    'bin_pt' => 0,
14105 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
14106 
                    'is_floating_block' => 1,
14107 
                    'is_gateway_port' => 1,
14108 
                    'must_be_hdl_vector' => 1,
14109 
                    'period' => 1,
14110 
                    'port_id' => 0,
14111 
                    'simulinkName' => 'INOUT_LOGIC/reg08_tv',
14112 
                    'source_block' => 'INOUT_LOGIC',
14113 
                    'timingConstraint' => 'none',
14114 
                    'type' => 'Bool',
14115 
                  },
14116 
                  'direction' => 'in',
14117 
                  'hdlType' => 'std_logic',
14118 
                  'width' => 1,
14119 
                },
14120 
                'reg09_rd' => {
14121 
                  'attributes' => {
14122 
                    'bin_pt' => 0,
14123 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
14124 
                    'is_floating_block' => 1,
14125 
                    'is_gateway_port' => 1,
14126 
                    'must_be_hdl_vector' => 1,
14127 
                    'period' => 1,
14128 
                    'port_id' => 0,
14129 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rd',
14130 
                    'source_block' => 'INOUT_LOGIC',
14131 
                    'timingConstraint' => 'none',
14132 
                    'type' => 'UFix_32_0',
14133 
                  },
14134 
                  'direction' => 'out',
14135 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14136 
                  'width' => 32,
14137 
                },
14138 
                'reg09_rv' => {
14139 
                  'attributes' => {
14140 
                    'bin_pt' => 0,
14141 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
14142 
                    'is_floating_block' => 1,
14143 
                    'is_gateway_port' => 1,
14144 
                    'must_be_hdl_vector' => 1,
14145 
                    'period' => 1,
14146 
                    'port_id' => 0,
14147 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rv',
14148 
                    'source_block' => 'INOUT_LOGIC',
14149 
                    'timingConstraint' => 'none',
14150 
                    'type' => 'UFix_1_0',
14151 
                  },
14152 
                  'direction' => 'out',
14153 
                  'hdlType' => 'std_logic',
14154 
                  'width' => 1,
14155 
                },
14156 
                'reg09_td' => {
14157 
                  'attributes' => {
14158 
                    'bin_pt' => 0,
14159 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
14160 
                    'is_floating_block' => 1,
14161 
                    'is_gateway_port' => 1,
14162 
                    'must_be_hdl_vector' => 1,
14163 
                    'period' => 1,
14164 
                    'port_id' => 0,
14165 
                    'simulinkName' => 'INOUT_LOGIC/reg09_td',
14166 
                    'source_block' => 'INOUT_LOGIC',
14167 
                    'timingConstraint' => 'none',
14168 
                    'type' => 'UFix_32_0',
14169 
                  },
14170 
                  'direction' => 'in',
14171 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14172 
                  'width' => 32,
14173 
                },
14174 
                'reg09_tv' => {
14175 
                  'attributes' => {
14176 
                    'bin_pt' => 0,
14177 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
14178 
                    'is_floating_block' => 1,
14179 
                    'is_gateway_port' => 1,
14180 
                    'must_be_hdl_vector' => 1,
14181 
                    'period' => 1,
14182 
                    'port_id' => 0,
14183 
                    'simulinkName' => 'INOUT_LOGIC/reg09_tv',
14184 
                    'source_block' => 'INOUT_LOGIC',
14185 
                    'timingConstraint' => 'none',
14186 
                    'type' => 'Bool',
14187 
                  },
14188 
                  'direction' => 'in',
14189 
                  'hdlType' => 'std_logic',
14190 
                  'width' => 1,
14191 
                },
14192 
                'reg10_rd' => {
14193 
                  'attributes' => {
14194 
                    'bin_pt' => 0,
14195 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
14196 
                    'is_floating_block' => 1,
14197 
                    'is_gateway_port' => 1,
14198 
                    'must_be_hdl_vector' => 1,
14199 
                    'period' => 1,
14200 
                    'port_id' => 0,
14201 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rd',
14202 
                    'source_block' => 'INOUT_LOGIC',
14203 
                    'timingConstraint' => 'none',
14204 
                    'type' => 'UFix_32_0',
14205 
                  },
14206 
                  'direction' => 'out',
14207 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14208 
                  'width' => 32,
14209 
                },
14210 
                'reg10_rv' => {
14211 
                  'attributes' => {
14212 
                    'bin_pt' => 0,
14213 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
14214 
                    'is_floating_block' => 1,
14215 
                    'is_gateway_port' => 1,
14216 
                    'must_be_hdl_vector' => 1,
14217 
                    'period' => 1,
14218 
                    'port_id' => 0,
14219 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rv',
14220 
                    'source_block' => 'INOUT_LOGIC',
14221 
                    'timingConstraint' => 'none',
14222 
                    'type' => 'UFix_1_0',
14223 
                  },
14224 
                  'direction' => 'out',
14225 
                  'hdlType' => 'std_logic',
14226 
                  'width' => 1,
14227 
                },
14228 
                'reg10_td' => {
14229 
                  'attributes' => {
14230 
                    'bin_pt' => 0,
14231 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
14232 
                    'is_floating_block' => 1,
14233 
                    'is_gateway_port' => 1,
14234 
                    'must_be_hdl_vector' => 1,
14235 
                    'period' => 1,
14236 
                    'port_id' => 0,
14237 
                    'simulinkName' => 'INOUT_LOGIC/reg10_td',
14238 
                    'source_block' => 'INOUT_LOGIC',
14239 
                    'timingConstraint' => 'none',
14240 
                    'type' => 'UFix_32_0',
14241 
                  },
14242 
                  'direction' => 'in',
14243 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14244 
                  'width' => 32,
14245 
                },
14246 
                'reg10_tv' => {
14247 
                  'attributes' => {
14248 
                    'bin_pt' => 0,
14249 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
14250 
                    'is_floating_block' => 1,
14251 
                    'is_gateway_port' => 1,
14252 
                    'must_be_hdl_vector' => 1,
14253 
                    'period' => 1,
14254 
                    'port_id' => 0,
14255 
                    'simulinkName' => 'INOUT_LOGIC/reg10_tv',
14256 
                    'source_block' => 'INOUT_LOGIC',
14257 
                    'timingConstraint' => 'none',
14258 
                    'type' => 'Bool',
14259 
                  },
14260 
                  'direction' => 'in',
14261 
                  'hdlType' => 'std_logic',
14262 
                  'width' => 1,
14263 
                },
14264 
                'reg11_rd' => {
14265 
                  'attributes' => {
14266 
                    'bin_pt' => 0,
14267 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
14268 
                    'is_floating_block' => 1,
14269 
                    'is_gateway_port' => 1,
14270 
                    'must_be_hdl_vector' => 1,
14271 
                    'period' => 1,
14272 
                    'port_id' => 0,
14273 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rd',
14274 
                    'source_block' => 'INOUT_LOGIC',
14275 
                    'timingConstraint' => 'none',
14276 
                    'type' => 'UFix_32_0',
14277 
                  },
14278 
                  'direction' => 'out',
14279 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14280 
                  'width' => 32,
14281 
                },
14282 
                'reg11_rv' => {
14283 
                  'attributes' => {
14284 
                    'bin_pt' => 0,
14285 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
14286 
                    'is_floating_block' => 1,
14287 
                    'is_gateway_port' => 1,
14288 
                    'must_be_hdl_vector' => 1,
14289 
                    'period' => 1,
14290 
                    'port_id' => 0,
14291 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rv',
14292 
                    'source_block' => 'INOUT_LOGIC',
14293 
                    'timingConstraint' => 'none',
14294 
                    'type' => 'UFix_1_0',
14295 
                  },
14296 
                  'direction' => 'out',
14297 
                  'hdlType' => 'std_logic',
14298 
                  'width' => 1,
14299 
                },
14300 
                'reg11_td' => {
14301 
                  'attributes' => {
14302 
                    'bin_pt' => 0,
14303 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
14304 
                    'is_floating_block' => 1,
14305 
                    'is_gateway_port' => 1,
14306 
                    'must_be_hdl_vector' => 1,
14307 
                    'period' => 1,
14308 
                    'port_id' => 0,
14309 
                    'simulinkName' => 'INOUT_LOGIC/reg11_td',
14310 
                    'source_block' => 'INOUT_LOGIC',
14311 
                    'timingConstraint' => 'none',
14312 
                    'type' => 'UFix_32_0',
14313 
                  },
14314 
                  'direction' => 'in',
14315 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14316 
                  'width' => 32,
14317 
                },
14318 
                'reg11_tv' => {
14319 
                  'attributes' => {
14320 
                    'bin_pt' => 0,
14321 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
14322 
                    'is_floating_block' => 1,
14323 
                    'is_gateway_port' => 1,
14324 
                    'must_be_hdl_vector' => 1,
14325 
                    'period' => 1,
14326 
                    'port_id' => 0,
14327 
                    'simulinkName' => 'INOUT_LOGIC/reg11_tv',
14328 
                    'source_block' => 'INOUT_LOGIC',
14329 
                    'timingConstraint' => 'none',
14330 
                    'type' => 'Bool',
14331 
                  },
14332 
                  'direction' => 'in',
14333 
                  'hdlType' => 'std_logic',
14334 
                  'width' => 1,
14335 
                },
14336 
                'reg12_rd' => {
14337 
                  'attributes' => {
14338 
                    'bin_pt' => 0,
14339 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
14340 
                    'is_floating_block' => 1,
14341 
                    'is_gateway_port' => 1,
14342 
                    'must_be_hdl_vector' => 1,
14343 
                    'period' => 1,
14344 
                    'port_id' => 0,
14345 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rd',
14346 
                    'source_block' => 'INOUT_LOGIC',
14347 
                    'timingConstraint' => 'none',
14348 
                    'type' => 'UFix_32_0',
14349 
                  },
14350 
                  'direction' => 'out',
14351 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14352 
                  'width' => 32,
14353 
                },
14354 
                'reg12_rv' => {
14355 
                  'attributes' => {
14356 
                    'bin_pt' => 0,
14357 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
14358 
                    'is_floating_block' => 1,
14359 
                    'is_gateway_port' => 1,
14360 
                    'must_be_hdl_vector' => 1,
14361 
                    'period' => 1,
14362 
                    'port_id' => 0,
14363 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rv',
14364 
                    'source_block' => 'INOUT_LOGIC',
14365 
                    'timingConstraint' => 'none',
14366 
                    'type' => 'UFix_1_0',
14367 
                  },
14368 
                  'direction' => 'out',
14369 
                  'hdlType' => 'std_logic',
14370 
                  'width' => 1,
14371 
                },
14372 
                'reg12_td' => {
14373 
                  'attributes' => {
14374 
                    'bin_pt' => 0,
14375 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
14376 
                    'is_floating_block' => 1,
14377 
                    'is_gateway_port' => 1,
14378 
                    'must_be_hdl_vector' => 1,
14379 
                    'period' => 1,
14380 
                    'port_id' => 0,
14381 
                    'simulinkName' => 'INOUT_LOGIC/reg12_td',
14382 
                    'source_block' => 'INOUT_LOGIC',
14383 
                    'timingConstraint' => 'none',
14384 
                    'type' => 'UFix_32_0',
14385 
                  },
14386 
                  'direction' => 'in',
14387 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14388 
                  'width' => 32,
14389 
                },
14390 
                'reg12_tv' => {
14391 
                  'attributes' => {
14392 
                    'bin_pt' => 0,
14393 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
14394 
                    'is_floating_block' => 1,
14395 
                    'is_gateway_port' => 1,
14396 
                    'must_be_hdl_vector' => 1,
14397 
                    'period' => 1,
14398 
                    'port_id' => 0,
14399 
                    'simulinkName' => 'INOUT_LOGIC/reg12_tv',
14400 
                    'source_block' => 'INOUT_LOGIC',
14401 
                    'timingConstraint' => 'none',
14402 
                    'type' => 'Bool',
14403 
                  },
14404 
                  'direction' => 'in',
14405 
                  'hdlType' => 'std_logic',
14406 
                  'width' => 1,
14407 
                },
14408 
                'reg13_rd' => {
14409 
                  'attributes' => {
14410 
                    'bin_pt' => 0,
14411 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
14412 
                    'is_floating_block' => 1,
14413 
                    'is_gateway_port' => 1,
14414 
                    'must_be_hdl_vector' => 1,
14415 
                    'period' => 1,
14416 
                    'port_id' => 0,
14417 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rd',
14418 
                    'source_block' => 'INOUT_LOGIC',
14419 
                    'timingConstraint' => 'none',
14420 
                    'type' => 'UFix_32_0',
14421 
                  },
14422 
                  'direction' => 'out',
14423 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14424 
                  'width' => 32,
14425 
                },
14426 
                'reg13_rv' => {
14427 
                  'attributes' => {
14428 
                    'bin_pt' => 0,
14429 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
14430 
                    'is_floating_block' => 1,
14431 
                    'is_gateway_port' => 1,
14432 
                    'must_be_hdl_vector' => 1,
14433 
                    'period' => 1,
14434 
                    'port_id' => 0,
14435 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rv',
14436 
                    'source_block' => 'INOUT_LOGIC',
14437 
                    'timingConstraint' => 'none',
14438 
                    'type' => 'UFix_1_0',
14439 
                  },
14440 
                  'direction' => 'out',
14441 
                  'hdlType' => 'std_logic',
14442 
                  'width' => 1,
14443 
                },
14444 
                'reg13_td' => {
14445 
                  'attributes' => {
14446 
                    'bin_pt' => 0,
14447 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
14448 
                    'is_floating_block' => 1,
14449 
                    'is_gateway_port' => 1,
14450 
                    'must_be_hdl_vector' => 1,
14451 
                    'period' => 1,
14452 
                    'port_id' => 0,
14453 
                    'simulinkName' => 'INOUT_LOGIC/reg13_td',
14454 
                    'source_block' => 'INOUT_LOGIC',
14455 
                    'timingConstraint' => 'none',
14456 
                    'type' => 'UFix_32_0',
14457 
                  },
14458 
                  'direction' => 'in',
14459 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14460 
                  'width' => 32,
14461 
                },
14462 
                'reg13_tv' => {
14463 
                  'attributes' => {
14464 
                    'bin_pt' => 0,
14465 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
14466 
                    'is_floating_block' => 1,
14467 
                    'is_gateway_port' => 1,
14468 
                    'must_be_hdl_vector' => 1,
14469 
                    'period' => 1,
14470 
                    'port_id' => 0,
14471 
                    'simulinkName' => 'INOUT_LOGIC/reg13_tv',
14472 
                    'source_block' => 'INOUT_LOGIC',
14473 
                    'timingConstraint' => 'none',
14474 
                    'type' => 'Bool',
14475 
                  },
14476 
                  'direction' => 'in',
14477 
                  'hdlType' => 'std_logic',
14478 
                  'width' => 1,
14479 
                },
14480 
                'reg14_rd' => {
14481 
                  'attributes' => {
14482 
                    'bin_pt' => 0,
14483 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
14484 
                    'is_floating_block' => 1,
14485 
                    'is_gateway_port' => 1,
14486 
                    'must_be_hdl_vector' => 1,
14487 
                    'period' => 1,
14488 
                    'port_id' => 0,
14489 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rd',
14490 
                    'source_block' => 'INOUT_LOGIC',
14491 
                    'timingConstraint' => 'none',
14492 
                    'type' => 'UFix_32_0',
14493 
                  },
14494 
                  'direction' => 'out',
14495 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14496 
                  'width' => 32,
14497 
                },
14498 
                'reg14_rv' => {
14499 
                  'attributes' => {
14500 
                    'bin_pt' => 0,
14501 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
14502 
                    'is_floating_block' => 1,
14503 
                    'is_gateway_port' => 1,
14504 
                    'must_be_hdl_vector' => 1,
14505 
                    'period' => 1,
14506 
                    'port_id' => 0,
14507 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rv',
14508 
                    'source_block' => 'INOUT_LOGIC',
14509 
                    'timingConstraint' => 'none',
14510 
                    'type' => 'UFix_1_0',
14511 
                  },
14512 
                  'direction' => 'out',
14513 
                  'hdlType' => 'std_logic',
14514 
                  'width' => 1,
14515 
                },
14516 
                'reg14_td' => {
14517 
                  'attributes' => {
14518 
                    'bin_pt' => 0,
14519 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
14520 
                    'is_floating_block' => 1,
14521 
                    'is_gateway_port' => 1,
14522 
                    'must_be_hdl_vector' => 1,
14523 
                    'period' => 1,
14524 
                    'port_id' => 0,
14525 
                    'simulinkName' => 'INOUT_LOGIC/reg14_td',
14526 
                    'source_block' => 'INOUT_LOGIC',
14527 
                    'timingConstraint' => 'none',
14528 
                    'type' => 'UFix_32_0',
14529 
                  },
14530 
                  'direction' => 'in',
14531 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14532 
                  'width' => 32,
14533 
                },
14534 
                'reg14_tv' => {
14535 
                  'attributes' => {
14536 
                    'bin_pt' => 0,
14537 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
14538 
                    'is_floating_block' => 1,
14539 
                    'is_gateway_port' => 1,
14540 
                    'must_be_hdl_vector' => 1,
14541 
                    'period' => 1,
14542 
                    'port_id' => 0,
14543 
                    'simulinkName' => 'INOUT_LOGIC/reg14_tv',
14544 
                    'source_block' => 'INOUT_LOGIC',
14545 
                    'timingConstraint' => 'none',
14546 
                    'type' => 'Bool',
14547 
                  },
14548 
                  'direction' => 'in',
14549 
                  'hdlType' => 'std_logic',
14550 
                  'width' => 1,
14551 
                },
14552 
              },
14553 
            },
14554 
            'entityName' => 'inout_logic',
14555 
          },
14556 
          'persistentdff_inst' => {
14557 
            'connections' => {
14558 
              'clk' => 'clkNet',
14559 
              'd' => 'persistentdff_inst_q',
14560 
              'q' => 'persistentdff_inst_q',
14561 
            },
14562 
            'entity' => {
14563 
              'attributes' => {
14564 
                'entityAlreadyNetlisted' => 1,
14565 
                'hdlCompAttributes' => [
14566 
                  [
14567 
                    'syn_black_box',
14568 
                    'boolean',
14569 
                    'true',
14570 
                  ],
14571 
                  [
14572 
                    'box_type',
14573 
                    'string',
14574 
                    '"black_box"',
14575 
                  ],
14576 
                ],
14577 
                'is_persistent_dff' => 1,
14578 
                'needsComponentDeclaration' => 1,
14579 
              },
14580 
              'entityName' => 'xlpersistentdff',
14581 
              'ports' => {
14582 
                'clk' => {
14583 
                  'direction' => 'in',
14584 
                  'hdlType' => 'std_logic',
14585 
                  'width' => 1,
14586 
                },
14587 
                'd' => {
14588 
                  'direction' => 'in',
14589 
                  'hdlType' => 'std_logic',
14590 
                  'width' => 1,
14591 
                },
14592 
                'q' => {
14593 
                  'direction' => 'out',
14594 
                  'hdlType' => 'std_logic',
14595 
                  'width' => 1,
14596 
                },
14597 
              },
14598 
            },
14599 
            'entityName' => 'xlpersistentdff',
14600 
          },
14601 
        },
14602 
      },
14603 
      'entityName' => 'inout_logic_cw',
14604 
    },
14605 
    'sysgen_gw_clk' => {
14606 
      'connections' => {
14607 
        'clk' => '.clk',
14608 
      },
14609 
      'entity' => {
14610 
        'attributes' => {
14611 
          'entityAlreadyNetlisted' => 1,
14612 
          'isClk' => 1,
14613 
          'isGateway' => 1,
14614 
          'is_floating_block' => 1,
14615 
        },
14616 
        'entityName' => 'sysgen_gw_clk',
14617 
        'ports' => {
14618 
          'clk' => {
14619 
            'attributes' => {
14620 
              'isClk' => 1,
14621 
            },
14622 
            'direction' => 'out',
14623 
            'hdlType' => 'std_logic',
14624 
            'width' => 1,
14625 
          },
14626 
        },
14627 
      },
14628 
      'entityName' => 'sysgen_gw_clk',
14629 
    },
14630 
    'to_register1' => {
14631 
      'connections' => {
14632 
        'ce' => 'sysgen_dut.to_register1_ce',
14633 
        'clk' => 'sysgen_dut.to_register1_clk',
14634 
        'clr' => 'sysgen_dut.to_register1_clr',
14635 
        'data_in' => 'sysgen_dut.to_register1_data_in',
14636 
        'dout' => 'to_register1.dout',
14637 
        'en' => 'sysgen_dut.to_register1_en',
14638 
      },
14639 
      'entity' => {
14640 
        'attributes' => {
14641 
          'entityAlreadyNetlisted' => 1,
14642 
          'generics' => [
14643 
          ],
14644 
          'is_floating_block' => 1,
14645 
          'mask' => {
14646 
            'Block_Handle' => 38.0009765625,
14647 
            'Block_handle' => 38.0009765625,
14648 
            'MDL_Handle' => 3.0009765625,
14649 
            'MDL_handle' => 3.0009765625,
14650 
            'arith_type' => 1,
14651 
            'bin_pt' => 14,
14652 
            'block_config' => 'sysgen_blockset:toreg_config',
14653 
            'block_handle' => 38.0009765625,
14654 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14655 
            'block_type' => 'toreg',
14656 
            'dbl_ovrd' => 0,
14657 
            'explicit_data_type' => 0,
14658 
            'init' => 0,
14659 
            'init_bit_vector' => '00000000000000000000000000000000b',
14660 
            'mdl_handle' => 3.0009765625,
14661 
            'model_handle' => 3.0009765625,
14662 
            'n_bits' => 16,
14663 
            'ownership' => 1,
14664 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14665 
            'shared_memory_name' => 'debug2i',
14666 
          },
14667 
          'needs_vhdl_wrapper' => 0,
14668 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14669 
        },
14670 
        'entityName' => 'x',
14671 
        'ports' => {
14672 
          'ce' => {
14673 
            'attributes' => {
14674 
              'domain' => '',
14675 
              'group' => 1,
14676 
              'isCe' => 1,
14677 
              'is_floating_block' => 1,
14678 
              'period' => 1,
14679 
              'type' => 'logic',
14680 
            },
14681 
            'direction' => 'in',
14682 
            'hdlType' => 'std_logic',
14683 
            'width' => 1,
14684 
          },
14685 
          'clk' => {
14686 
            'attributes' => {
14687 
              'domain' => '',
14688 
              'group' => 1,
14689 
              'isClk' => 1,
14690 
              'is_floating_block' => 1,
14691 
              'period' => 1,
14692 
              'type' => 'logic',
14693 
            },
14694 
            'direction' => 'in',
14695 
            'hdlType' => 'std_logic',
14696 
            'width' => 1,
14697 
          },
14698 
          'clr' => {
14699 
            'attributes' => {
14700 
              'domain' => '',
14701 
              'group' => 1,
14702 
              'isClr' => 1,
14703 
              'is_floating_block' => 1,
14704 
              'period' => 1,
14705 
              'type' => 'logic',
14706 
              'valid_bit_used' => 0,
14707 
            },
14708 
            'direction' => 'in',
14709 
            'hdlType' => 'std_logic',
14710 
            'width' => 1,
14711 
          },
14712 
          'data_in' => {
14713 
            'attributes' => {
14714 
              'bin_pt' => 0,
14715 
              'is_floating_block' => 1,
14716 
              'must_be_hdl_vector' => 1,
14717 
              'period' => 1,
14718 
              'port_id' => 0,
14719 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
14720 
              'type' => 'UFix_32_0',
14721 
            },
14722 
            'direction' => 'in',
14723 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14724 
            'width' => 32,
14725 
          },
14726 
          'dout' => {
14727 
            'attributes' => {
14728 
              'bin_pt' => 0,
14729 
              'is_floating_block' => 1,
14730 
              'must_be_hdl_vector' => 1,
14731 
              'period' => 1,
14732 
              'port_id' => 0,
14733 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
14734 
              'type' => 'UFix_32_0',
14735 
            },
14736 
            'direction' => 'out',
14737 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14738 
            'width' => 32,
14739 
          },
14740 
          'en' => {
14741 
            'attributes' => {
14742 
              'bin_pt' => 0,
14743 
              'is_floating_block' => 1,
14744 
              'must_be_hdl_vector' => 1,
14745 
              'period' => 1,
14746 
              'port_id' => 1,
14747 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
14748 
              'type' => 'Bool',
14749 
            },
14750 
            'direction' => 'in',
14751 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14752 
            'width' => 1,
14753 
          },
14754 
        },
14755 
      },
14756 
      'entityName' => 'x',
14757 
    },
14758 
    'to_register10' => {
14759 
      'connections' => {
14760 
        'ce' => 'sysgen_dut.to_register10_ce',
14761 
        'clk' => 'sysgen_dut.to_register10_clk',
14762 
        'clr' => 'sysgen_dut.to_register10_clr',
14763 
        'data_in' => 'sysgen_dut.to_register10_data_in',
14764 
        'dout' => 'to_register10.dout',
14765 
        'en' => 'sysgen_dut.to_register10_en',
14766 
      },
14767 
      'entity' => {
14768 
        'attributes' => {
14769 
          'entityAlreadyNetlisted' => 1,
14770 
          'generics' => [
14771 
          ],
14772 
          'is_floating_block' => 1,
14773 
          'mask' => {
14774 
            'Block_Handle' => 39.0009765625,
14775 
            'Block_handle' => 39.0009765625,
14776 
            'MDL_Handle' => 3.0009765625,
14777 
            'MDL_handle' => 3.0009765625,
14778 
            'arith_type' => 1,
14779 
            'bin_pt' => 14,
14780 
            'block_config' => 'sysgen_blockset:toreg_config',
14781 
            'block_handle' => 39.0009765625,
14782 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14783 
            'block_type' => 'toreg',
14784 
            'dbl_ovrd' => 0,
14785 
            'explicit_data_type' => 0,
14786 
            'init' => 0,
14787 
            'init_bit_vector' => '0b',
14788 
            'mdl_handle' => 3.0009765625,
14789 
            'model_handle' => 3.0009765625,
14790 
            'n_bits' => 16,
14791 
            'ownership' => 1,
14792 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14793 
            'shared_memory_name' => 'register04tv',
14794 
          },
14795 
          'needs_vhdl_wrapper' => 0,
14796 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14797 
        },
14798 
        'entityName' => 'x_x0',
14799 
        'ports' => {
14800 
          'ce' => {
14801 
            'attributes' => {
14802 
              'domain' => '',
14803 
              'group' => 1,
14804 
              'isCe' => 1,
14805 
              'is_floating_block' => 1,
14806 
              'period' => 1,
14807 
              'type' => 'logic',
14808 
            },
14809 
            'direction' => 'in',
14810 
            'hdlType' => 'std_logic',
14811 
            'width' => 1,
14812 
          },
14813 
          'clk' => {
14814 
            'attributes' => {
14815 
              'domain' => '',
14816 
              'group' => 1,
14817 
              'isClk' => 1,
14818 
              'is_floating_block' => 1,
14819 
              'period' => 1,
14820 
              'type' => 'logic',
14821 
            },
14822 
            'direction' => 'in',
14823 
            'hdlType' => 'std_logic',
14824 
            'width' => 1,
14825 
          },
14826 
          'clr' => {
14827 
            'attributes' => {
14828 
              'domain' => '',
14829 
              'group' => 1,
14830 
              'isClr' => 1,
14831 
              'is_floating_block' => 1,
14832 
              'period' => 1,
14833 
              'type' => 'logic',
14834 
              'valid_bit_used' => 0,
14835 
            },
14836 
            'direction' => 'in',
14837 
            'hdlType' => 'std_logic',
14838 
            'width' => 1,
14839 
          },
14840 
          'data_in' => {
14841 
            'attributes' => {
14842 
              'bin_pt' => 0,
14843 
              'is_floating_block' => 1,
14844 
              'must_be_hdl_vector' => 1,
14845 
              'period' => 1,
14846 
              'port_id' => 0,
14847 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
14848 
              'type' => 'Bool',
14849 
            },
14850 
            'direction' => 'in',
14851 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14852 
            'width' => 1,
14853 
          },
14854 
          'dout' => {
14855 
            'attributes' => {
14856 
              'bin_pt' => 0,
14857 
              'is_floating_block' => 1,
14858 
              'must_be_hdl_vector' => 1,
14859 
              'period' => 1,
14860 
              'port_id' => 0,
14861 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
14862 
              'type' => 'Bool',
14863 
            },
14864 
            'direction' => 'out',
14865 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14866 
            'width' => 1,
14867 
          },
14868 
          'en' => {
14869 
            'attributes' => {
14870 
              'bin_pt' => 0,
14871 
              'is_floating_block' => 1,
14872 
              'must_be_hdl_vector' => 1,
14873 
              'period' => 1,
14874 
              'port_id' => 1,
14875 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
14876 
              'type' => 'Bool',
14877 
            },
14878 
            'direction' => 'in',
14879 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14880 
            'width' => 1,
14881 
          },
14882 
        },
14883 
      },
14884 
      'entityName' => 'x_x0',
14885 
    },
14886 
    'to_register11' => {
14887 
      'connections' => {
14888 
        'ce' => 'sysgen_dut.to_register11_ce',
14889 
        'clk' => 'sysgen_dut.to_register11_clk',
14890 
        'clr' => 'sysgen_dut.to_register11_clr',
14891 
        'data_in' => 'sysgen_dut.to_register11_data_in',
14892 
        'dout' => 'to_register11.dout',
14893 
        'en' => 'sysgen_dut.to_register11_en',
14894 
      },
14895 
      'entity' => {
14896 
        'attributes' => {
14897 
          'entityAlreadyNetlisted' => 1,
14898 
          'generics' => [
14899 
          ],
14900 
          'is_floating_block' => 1,
14901 
          'mask' => {
14902 
            'Block_Handle' => 40.0009765625,
14903 
            'Block_handle' => 40.0009765625,
14904 
            'MDL_Handle' => 3.0009765625,
14905 
            'MDL_handle' => 3.0009765625,
14906 
            'arith_type' => 1,
14907 
            'bin_pt' => 14,
14908 
            'block_config' => 'sysgen_blockset:toreg_config',
14909 
            'block_handle' => 40.0009765625,
14910 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14911 
            'block_type' => 'toreg',
14912 
            'dbl_ovrd' => 0,
14913 
            'explicit_data_type' => 0,
14914 
            'init' => 0,
14915 
            'init_bit_vector' => '00000000000000000000000000000000b',
14916 
            'mdl_handle' => 3.0009765625,
14917 
            'model_handle' => 3.0009765625,
14918 
            'n_bits' => 16,
14919 
            'ownership' => 1,
14920 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14921 
            'shared_memory_name' => 'register04td',
14922 
          },
14923 
          'needs_vhdl_wrapper' => 0,
14924 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14925 
        },
14926 
        'entityName' => 'x_x1',
14927 
        'ports' => {
14928 
          'ce' => {
14929 
            'attributes' => {
14930 
              'domain' => '',
14931 
              'group' => 1,
14932 
              'isCe' => 1,
14933 
              'is_floating_block' => 1,
14934 
              'period' => 1,
14935 
              'type' => 'logic',
14936 
            },
14937 
            'direction' => 'in',
14938 
            'hdlType' => 'std_logic',
14939 
            'width' => 1,
14940 
          },
14941 
          'clk' => {
14942 
            'attributes' => {
14943 
              'domain' => '',
14944 
              'group' => 1,
14945 
              'isClk' => 1,
14946 
              'is_floating_block' => 1,
14947 
              'period' => 1,
14948 
              'type' => 'logic',
14949 
            },
14950 
            'direction' => 'in',
14951 
            'hdlType' => 'std_logic',
14952 
            'width' => 1,
14953 
          },
14954 
          'clr' => {
14955 
            'attributes' => {
14956 
              'domain' => '',
14957 
              'group' => 1,
14958 
              'isClr' => 1,
14959 
              'is_floating_block' => 1,
14960 
              'period' => 1,
14961 
              'type' => 'logic',
14962 
              'valid_bit_used' => 0,
14963 
            },
14964 
            'direction' => 'in',
14965 
            'hdlType' => 'std_logic',
14966 
            'width' => 1,
14967 
          },
14968 
          'data_in' => {
14969 
            'attributes' => {
14970 
              'bin_pt' => 0,
14971 
              'is_floating_block' => 1,
14972 
              'must_be_hdl_vector' => 1,
14973 
              'period' => 1,
14974 
              'port_id' => 0,
14975 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
14976 
              'type' => 'UFix_32_0',
14977 
            },
14978 
            'direction' => 'in',
14979 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14980 
            'width' => 32,
14981 
          },
14982 
          'dout' => {
14983 
            'attributes' => {
14984 
              'bin_pt' => 0,
14985 
              'is_floating_block' => 1,
14986 
              'must_be_hdl_vector' => 1,
14987 
              'period' => 1,
14988 
              'port_id' => 0,
14989 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
14990 
              'type' => 'UFix_32_0',
14991 
            },
14992 
            'direction' => 'out',
14993 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14994 
            'width' => 32,
14995 
          },
14996 
          'en' => {
14997 
            'attributes' => {
14998 
              'bin_pt' => 0,
14999 
              'is_floating_block' => 1,
15000 
              'must_be_hdl_vector' => 1,
15001 
              'period' => 1,
15002 
              'port_id' => 1,
15003 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
15004 
              'type' => 'Bool',
15005 
            },
15006 
            'direction' => 'in',
15007 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15008 
            'width' => 1,
15009 
          },
15010 
        },
15011 
      },
15012 
      'entityName' => 'x_x1',
15013 
    },
15014 
    'to_register12' => {
15015 
      'connections' => {
15016 
        'ce' => 'sysgen_dut.to_register12_ce',
15017 
        'clk' => 'sysgen_dut.to_register12_clk',
15018 
        'clr' => 'sysgen_dut.to_register12_clr',
15019 
        'data_in' => 'sysgen_dut.to_register12_data_in',
15020 
        'dout' => 'to_register12.dout',
15021 
        'en' => 'sysgen_dut.to_register12_en',
15022 
      },
15023 
      'entity' => {
15024 
        'attributes' => {
15025 
          'entityAlreadyNetlisted' => 1,
15026 
          'generics' => [
15027 
          ],
15028 
          'is_floating_block' => 1,
15029 
          'mask' => {
15030 
            'Block_Handle' => 41.0009765625,
15031 
            'Block_handle' => 41.0009765625,
15032 
            'MDL_Handle' => 3.0009765625,
15033 
            'MDL_handle' => 3.0009765625,
15034 
            'arith_type' => 1,
15035 
            'bin_pt' => 14,
15036 
            'block_config' => 'sysgen_blockset:toreg_config',
15037 
            'block_handle' => 41.0009765625,
15038 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
15039 
            'block_type' => 'toreg',
15040 
            'dbl_ovrd' => 0,
15041 
            'explicit_data_type' => 0,
15042 
            'init' => 0,
15043 
            'init_bit_vector' => '0b',
15044 
            'mdl_handle' => 3.0009765625,
15045 
            'model_handle' => 3.0009765625,
15046 
            'n_bits' => 16,
15047 
            'ownership' => 1,
15048 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15049 
            'shared_memory_name' => 'register05tv',
15050 
          },
15051 
          'needs_vhdl_wrapper' => 0,
15052 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
15053 
        },
15054 
        'entityName' => 'x_x2',
15055 
        'ports' => {
15056 
          'ce' => {
15057 
            'attributes' => {
15058 
              'domain' => '',
15059 
              'group' => 1,
15060 
              'isCe' => 1,
15061 
              'is_floating_block' => 1,
15062 
              'period' => 1,
15063 
              'type' => 'logic',
15064 
            },
15065 
            'direction' => 'in',
15066 
            'hdlType' => 'std_logic',
15067 
            'width' => 1,
15068 
          },
15069 
          'clk' => {
15070 
            'attributes' => {
15071 
              'domain' => '',
15072 
              'group' => 1,
15073 
              'isClk' => 1,
15074 
              'is_floating_block' => 1,
15075 
              'period' => 1,
15076 
              'type' => 'logic',
15077 
            },
15078 
            'direction' => 'in',
15079 
            'hdlType' => 'std_logic',
15080 
            'width' => 1,
15081 
          },
15082 
          'clr' => {
15083 
            'attributes' => {
15084 
              'domain' => '',
15085 
              'group' => 1,
15086 
              'isClr' => 1,
15087 
              'is_floating_block' => 1,
15088 
              'period' => 1,
15089 
              'type' => 'logic',
15090 
              'valid_bit_used' => 0,
15091 
            },
15092 
            'direction' => 'in',
15093 
            'hdlType' => 'std_logic',
15094 
            'width' => 1,
15095 
          },
15096 
          'data_in' => {
15097 
            'attributes' => {
15098 
              'bin_pt' => 0,
15099 
              'is_floating_block' => 1,
15100 
              'must_be_hdl_vector' => 1,
15101 
              'period' => 1,
15102 
              'port_id' => 0,
15103 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
15104 
              'type' => 'Bool',
15105 
            },
15106 
            'direction' => 'in',
15107 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15108 
            'width' => 1,
15109 
          },
15110 
          'dout' => {
15111 
            'attributes' => {
15112 
              'bin_pt' => 0,
15113 
              'is_floating_block' => 1,
15114 
              'must_be_hdl_vector' => 1,
15115 
              'period' => 1,
15116 
              'port_id' => 0,
15117 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
15118 
              'type' => 'Bool',
15119 
            },
15120 
            'direction' => 'out',
15121 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15122 
            'width' => 1,
15123 
          },
15124 
          'en' => {
15125 
            'attributes' => {
15126 
              'bin_pt' => 0,
15127 
              'is_floating_block' => 1,
15128 
              'must_be_hdl_vector' => 1,
15129 
              'period' => 1,
15130 
              'port_id' => 1,
15131 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
15132 
              'type' => 'Bool',
15133 
            },
15134 
            'direction' => 'in',
15135 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15136 
            'width' => 1,
15137 
          },
15138 
        },
15139 
      },
15140 
      'entityName' => 'x_x2',
15141 
    },
15142 
    'to_register13' => {
15143 
      'connections' => {
15144 
        'ce' => 'sysgen_dut.to_register13_ce',
15145 
        'clk' => 'sysgen_dut.to_register13_clk',
15146 
        'clr' => 'sysgen_dut.to_register13_clr',
15147 
        'data_in' => 'sysgen_dut.to_register13_data_in',
15148 
        'dout' => 'to_register13.dout',
15149 
        'en' => 'sysgen_dut.to_register13_en',
15150 
      },
15151 
      'entity' => {
15152 
        'attributes' => {
15153 
          'entityAlreadyNetlisted' => 1,
15154 
          'generics' => [
15155 
          ],
15156 
          'is_floating_block' => 1,
15157 
          'mask' => {
15158 
            'Block_Handle' => 42.0009765625,
15159 
            'Block_handle' => 42.0009765625,
15160 
            'MDL_Handle' => 3.0009765625,
15161 
            'MDL_handle' => 3.0009765625,
15162 
            'arith_type' => 1,
15163 
            'bin_pt' => 14,
15164 
            'block_config' => 'sysgen_blockset:toreg_config',
15165 
            'block_handle' => 42.0009765625,
15166 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
15167 
            'block_type' => 'toreg',
15168 
            'dbl_ovrd' => 0,
15169 
            'explicit_data_type' => 0,
15170 
            'init' => 0,
15171 
            'init_bit_vector' => '00000000000000000000000000000000b',
15172 
            'mdl_handle' => 3.0009765625,
15173 
            'model_handle' => 3.0009765625,
15174 
            'n_bits' => 16,
15175 
            'ownership' => 1,
15176 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15177 
            'shared_memory_name' => 'register05td',
15178 
          },
15179 
          'needs_vhdl_wrapper' => 0,
15180 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
15181 
        },
15182 
        'entityName' => 'x_x3',
15183 
        'ports' => {
15184 
          'ce' => {
15185 
            'attributes' => {
15186 
              'domain' => '',
15187 
              'group' => 1,
15188 
              'isCe' => 1,
15189 
              'is_floating_block' => 1,
15190 
              'period' => 1,
15191 
              'type' => 'logic',
15192 
            },
15193 
            'direction' => 'in',
15194 
            'hdlType' => 'std_logic',
15195 
            'width' => 1,
15196 
          },
15197 
          'clk' => {
15198 
            'attributes' => {
15199 
              'domain' => '',
15200 
              'group' => 1,
15201 
              'isClk' => 1,
15202 
              'is_floating_block' => 1,
15203 
              'period' => 1,
15204 
              'type' => 'logic',
15205 
            },
15206 
            'direction' => 'in',
15207 
            'hdlType' => 'std_logic',
15208 
            'width' => 1,
15209 
          },
15210 
          'clr' => {
15211 
            'attributes' => {
15212 
              'domain' => '',
15213 
              'group' => 1,
15214 
              'isClr' => 1,
15215 
              'is_floating_block' => 1,
15216 
              'period' => 1,
15217 
              'type' => 'logic',
15218 
              'valid_bit_used' => 0,
15219 
            },
15220 
            'direction' => 'in',
15221 
            'hdlType' => 'std_logic',
15222 
            'width' => 1,
15223 
          },
15224 
          'data_in' => {
15225 
            'attributes' => {
15226 
              'bin_pt' => 0,
15227 
              'is_floating_block' => 1,
15228 
              'must_be_hdl_vector' => 1,
15229 
              'period' => 1,
15230 
              'port_id' => 0,
15231 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
15232 
              'type' => 'UFix_32_0',
15233 
            },
15234 
            'direction' => 'in',
15235 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15236 
            'width' => 32,
15237 
          },
15238 
          'dout' => {
15239 
            'attributes' => {
15240 
              'bin_pt' => 0,
15241 
              'is_floating_block' => 1,
15242 
              'must_be_hdl_vector' => 1,
15243 
              'period' => 1,
15244 
              'port_id' => 0,
15245 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
15246 
              'type' => 'UFix_32_0',
15247 
            },
15248 
            'direction' => 'out',
15249 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15250 
            'width' => 32,
15251 
          },
15252 
          'en' => {
15253 
            'attributes' => {
15254 
              'bin_pt' => 0,
15255 
              'is_floating_block' => 1,
15256 
              'must_be_hdl_vector' => 1,
15257 
              'period' => 1,
15258 
              'port_id' => 1,
15259 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
15260 
              'type' => 'Bool',
15261 
            },
15262 
            'direction' => 'in',
15263 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15264 
            'width' => 1,
15265 
          },
15266 
        },
15267 
      },
15268 
      'entityName' => 'x_x3',
15269 
    },
15270 
    'to_register14' => {
15271 
      'connections' => {
15272 
        'ce' => 'sysgen_dut.to_register14_ce',
15273 
        'clk' => 'sysgen_dut.to_register14_clk',
15274 
        'clr' => 'sysgen_dut.to_register14_clr',
15275 
        'data_in' => 'sysgen_dut.to_register14_data_in',
15276 
        'dout' => 'to_register14.dout',
15277 
        'en' => 'sysgen_dut.to_register14_en',
15278 
      },
15279 
      'entity' => {
15280 
        'attributes' => {
15281 
          'entityAlreadyNetlisted' => 1,
15282 
          'generics' => [
15283 
          ],
15284 
          'is_floating_block' => 1,
15285 
          'mask' => {
15286 
            'Block_Handle' => 43.0009765625,
15287 
            'Block_handle' => 43.0009765625,
15288 
            'MDL_Handle' => 3.0009765625,
15289 
            'MDL_handle' => 3.0009765625,
15290 
            'arith_type' => 1,
15291 
            'bin_pt' => 14,
15292 
            'block_config' => 'sysgen_blockset:toreg_config',
15293 
            'block_handle' => 43.0009765625,
15294 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
15295 
            'block_type' => 'toreg',
15296 
            'dbl_ovrd' => 0,
15297 
            'explicit_data_type' => 0,
15298 
            'init' => 0,
15299 
            'init_bit_vector' => '0b',
15300 
            'mdl_handle' => 3.0009765625,
15301 
            'model_handle' => 3.0009765625,
15302 
            'n_bits' => 16,
15303 
            'ownership' => 1,
15304 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15305 
            'shared_memory_name' => 'register06tv',
15306 
          },
15307 
          'needs_vhdl_wrapper' => 0,
15308 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
15309 
        },
15310 
        'entityName' => 'x_x4',
15311 
        'ports' => {
15312 
          'ce' => {
15313 
            'attributes' => {
15314 
              'domain' => '',
15315 
              'group' => 1,
15316 
              'isCe' => 1,
15317 
              'is_floating_block' => 1,
15318 
              'period' => 1,
15319 
              'type' => 'logic',
15320 
            },
15321 
            'direction' => 'in',
15322 
            'hdlType' => 'std_logic',
15323 
            'width' => 1,
15324 
          },
15325 
          'clk' => {
15326 
            'attributes' => {
15327 
              'domain' => '',
15328 
              'group' => 1,
15329 
              'isClk' => 1,
15330 
              'is_floating_block' => 1,
15331 
              'period' => 1,
15332 
              'type' => 'logic',
15333 
            },
15334 
            'direction' => 'in',
15335 
            'hdlType' => 'std_logic',
15336 
            'width' => 1,
15337 
          },
15338 
          'clr' => {
15339 
            'attributes' => {
15340 
              'domain' => '',
15341 
              'group' => 1,
15342 
              'isClr' => 1,
15343 
              'is_floating_block' => 1,
15344 
              'period' => 1,
15345 
              'type' => 'logic',
15346 
              'valid_bit_used' => 0,
15347 
            },
15348 
            'direction' => 'in',
15349 
            'hdlType' => 'std_logic',
15350 
            'width' => 1,
15351 
          },
15352 
          'data_in' => {
15353 
            'attributes' => {
15354 
              'bin_pt' => 0,
15355 
              'is_floating_block' => 1,
15356 
              'must_be_hdl_vector' => 1,
15357 
              'period' => 1,
15358 
              'port_id' => 0,
15359 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
15360 
              'type' => 'Bool',
15361 
            },
15362 
            'direction' => 'in',
15363 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15364 
            'width' => 1,
15365 
          },
15366 
          'dout' => {
15367 
            'attributes' => {
15368 
              'bin_pt' => 0,
15369 
              'is_floating_block' => 1,
15370 
              'must_be_hdl_vector' => 1,
15371 
              'period' => 1,
15372 
              'port_id' => 0,
15373 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
15374 
              'type' => 'Bool',
15375 
            },
15376 
            'direction' => 'out',
15377 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15378 
            'width' => 1,
15379 
          },
15380 
          'en' => {
15381 
            'attributes' => {
15382 
              'bin_pt' => 0,
15383 
              'is_floating_block' => 1,
15384 
              'must_be_hdl_vector' => 1,
15385 
              'period' => 1,
15386 
              'port_id' => 1,
15387 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
15388 
              'type' => 'Bool',
15389 
            },
15390 
            'direction' => 'in',
15391 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15392 
            'width' => 1,
15393 
          },
15394 
        },
15395 
      },
15396 
      'entityName' => 'x_x4',
15397 
    },
15398 
    'to_register15' => {
15399 
      'connections' => {
15400 
        'ce' => 'sysgen_dut.to_register15_ce',
15401 
        'clk' => 'sysgen_dut.to_register15_clk',
15402 
        'clr' => 'sysgen_dut.to_register15_clr',
15403 
        'data_in' => 'sysgen_dut.to_register15_data_in',
15404 
        'dout' => 'to_register15.dout',
15405 
        'en' => 'sysgen_dut.to_register15_en',
15406 
      },
15407 
      'entity' => {
15408 
        'attributes' => {
15409 
          'entityAlreadyNetlisted' => 1,
15410 
          'generics' => [
15411 
          ],
15412 
          'is_floating_block' => 1,
15413 
          'mask' => {
15414 
            'Block_Handle' => 44.0009765625,
15415 
            'Block_handle' => 44.0009765625,
15416 
            'MDL_Handle' => 3.0009765625,
15417 
            'MDL_handle' => 3.0009765625,
15418 
            'arith_type' => 1,
15419 
            'bin_pt' => 14,
15420 
            'block_config' => 'sysgen_blockset:toreg_config',
15421 
            'block_handle' => 44.0009765625,
15422 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
15423 
            'block_type' => 'toreg',
15424 
            'dbl_ovrd' => 0,
15425 
            'explicit_data_type' => 0,
15426 
            'init' => 0,
15427 
            'init_bit_vector' => '00000000000000000000000000000000b',
15428 
            'mdl_handle' => 3.0009765625,
15429 
            'model_handle' => 3.0009765625,
15430 
            'n_bits' => 16,
15431 
            'ownership' => 1,
15432 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15433 
            'shared_memory_name' => 'register06td',
15434 
          },
15435 
          'needs_vhdl_wrapper' => 0,
15436 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
15437 
        },
15438 
        'entityName' => 'x_x5',
15439 
        'ports' => {
15440 
          'ce' => {
15441 
            'attributes' => {
15442 
              'domain' => '',
15443 
              'group' => 1,
15444 
              'isCe' => 1,
15445 
              'is_floating_block' => 1,
15446 
              'period' => 1,
15447 
              'type' => 'logic',
15448 
            },
15449 
            'direction' => 'in',
15450 
            'hdlType' => 'std_logic',
15451 
            'width' => 1,
15452 
          },
15453 
          'clk' => {
15454 
            'attributes' => {
15455 
              'domain' => '',
15456 
              'group' => 1,
15457 
              'isClk' => 1,
15458 
              'is_floating_block' => 1,
15459 
              'period' => 1,
15460 
              'type' => 'logic',
15461 
            },
15462 
            'direction' => 'in',
15463 
            'hdlType' => 'std_logic',
15464 
            'width' => 1,
15465 
          },
15466 
          'clr' => {
15467 
            'attributes' => {
15468 
              'domain' => '',
15469 
              'group' => 1,
15470 
              'isClr' => 1,
15471 
              'is_floating_block' => 1,
15472 
              'period' => 1,
15473 
              'type' => 'logic',
15474 
              'valid_bit_used' => 0,
15475 
            },
15476 
            'direction' => 'in',
15477 
            'hdlType' => 'std_logic',
15478 
            'width' => 1,
15479 
          },
15480 
          'data_in' => {
15481 
            'attributes' => {
15482 
              'bin_pt' => 0,
15483 
              'is_floating_block' => 1,
15484 
              'must_be_hdl_vector' => 1,
15485 
              'period' => 1,
15486 
              'port_id' => 0,
15487 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
15488 
              'type' => 'UFix_32_0',
15489 
            },
15490 
            'direction' => 'in',
15491 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15492 
            'width' => 32,
15493 
          },
15494 
          'dout' => {
15495 
            'attributes' => {
15496 
              'bin_pt' => 0,
15497 
              'is_floating_block' => 1,
15498 
              'must_be_hdl_vector' => 1,
15499 
              'period' => 1,
15500 
              'port_id' => 0,
15501 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
15502 
              'type' => 'UFix_32_0',
15503 
            },
15504 
            'direction' => 'out',
15505 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15506 
            'width' => 32,
15507 
          },
15508 
          'en' => {
15509 
            'attributes' => {
15510 
              'bin_pt' => 0,
15511 
              'is_floating_block' => 1,
15512 
              'must_be_hdl_vector' => 1,
15513 
              'period' => 1,
15514 
              'port_id' => 1,
15515 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
15516 
              'type' => 'Bool',
15517 
            },
15518 
            'direction' => 'in',
15519 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15520 
            'width' => 1,
15521 
          },
15522 
        },
15523 
      },
15524 
      'entityName' => 'x_x5',
15525 
    },
15526 
    'to_register16' => {
15527 
      'connections' => {
15528 
        'ce' => 'sysgen_dut.to_register16_ce',
15529 
        'clk' => 'sysgen_dut.to_register16_clk',
15530 
        'clr' => 'sysgen_dut.to_register16_clr',
15531 
        'data_in' => 'sysgen_dut.to_register16_data_in',
15532 
        'dout' => 'to_register16.dout',
15533 
        'en' => 'sysgen_dut.to_register16_en',
15534 
      },
15535 
      'entity' => {
15536 
        'attributes' => {
15537 
          'entityAlreadyNetlisted' => 1,
15538 
          'generics' => [
15539 
          ],
15540 
          'is_floating_block' => 1,
15541 
          'mask' => {
15542 
            'Block_Handle' => 45.0009765625,
15543 
            'Block_handle' => 45.0009765625,
15544 
            'MDL_Handle' => 3.0009765625,
15545 
            'MDL_handle' => 3.0009765625,
15546 
            'arith_type' => 1,
15547 
            'bin_pt' => 14,
15548 
            'block_config' => 'sysgen_blockset:toreg_config',
15549 
            'block_handle' => 45.0009765625,
15550 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15551 
            'block_type' => 'toreg',
15552 
            'dbl_ovrd' => 0,
15553 
            'explicit_data_type' => 0,
15554 
            'init' => 0,
15555 
            'init_bit_vector' => '0b',
15556 
            'mdl_handle' => 3.0009765625,
15557 
            'model_handle' => 3.0009765625,
15558 
            'n_bits' => 16,
15559 
            'ownership' => 1,
15560 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15561 
            'shared_memory_name' => 'register07tv',
15562 
          },
15563 
          'needs_vhdl_wrapper' => 0,
15564 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15565 
        },
15566 
        'entityName' => 'x_x6',
15567 
        'ports' => {
15568 
          'ce' => {
15569 
            'attributes' => {
15570 
              'domain' => '',
15571 
              'group' => 1,
15572 
              'isCe' => 1,
15573 
              'is_floating_block' => 1,
15574 
              'period' => 1,
15575 
              'type' => 'logic',
15576 
            },
15577 
            'direction' => 'in',
15578 
            'hdlType' => 'std_logic',
15579 
            'width' => 1,
15580 
          },
15581 
          'clk' => {
15582 
            'attributes' => {
15583 
              'domain' => '',
15584 
              'group' => 1,
15585 
              'isClk' => 1,
15586 
              'is_floating_block' => 1,
15587 
              'period' => 1,
15588 
              'type' => 'logic',
15589 
            },
15590 
            'direction' => 'in',
15591 
            'hdlType' => 'std_logic',
15592 
            'width' => 1,
15593 
          },
15594 
          'clr' => {
15595 
            'attributes' => {
15596 
              'domain' => '',
15597 
              'group' => 1,
15598 
              'isClr' => 1,
15599 
              'is_floating_block' => 1,
15600 
              'period' => 1,
15601 
              'type' => 'logic',
15602 
              'valid_bit_used' => 0,
15603 
            },
15604 
            'direction' => 'in',
15605 
            'hdlType' => 'std_logic',
15606 
            'width' => 1,
15607 
          },
15608 
          'data_in' => {
15609 
            'attributes' => {
15610 
              'bin_pt' => 0,
15611 
              'is_floating_block' => 1,
15612 
              'must_be_hdl_vector' => 1,
15613 
              'period' => 1,
15614 
              'port_id' => 0,
15615 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
15616 
              'type' => 'Bool',
15617 
            },
15618 
            'direction' => 'in',
15619 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15620 
            'width' => 1,
15621 
          },
15622 
          'dout' => {
15623 
            'attributes' => {
15624 
              'bin_pt' => 0,
15625 
              'is_floating_block' => 1,
15626 
              'must_be_hdl_vector' => 1,
15627 
              'period' => 1,
15628 
              'port_id' => 0,
15629 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
15630 
              'type' => 'Bool',
15631 
            },
15632 
            'direction' => 'out',
15633 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15634 
            'width' => 1,
15635 
          },
15636 
          'en' => {
15637 
            'attributes' => {
15638 
              'bin_pt' => 0,
15639 
              'is_floating_block' => 1,
15640 
              'must_be_hdl_vector' => 1,
15641 
              'period' => 1,
15642 
              'port_id' => 1,
15643 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
15644 
              'type' => 'Bool',
15645 
            },
15646 
            'direction' => 'in',
15647 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15648 
            'width' => 1,
15649 
          },
15650 
        },
15651 
      },
15652 
      'entityName' => 'x_x6',
15653 
    },
15654 
    'to_register17' => {
15655 
      'connections' => {
15656 
        'ce' => 'sysgen_dut.to_register17_ce',
15657 
        'clk' => 'sysgen_dut.to_register17_clk',
15658 
        'clr' => 'sysgen_dut.to_register17_clr',
15659 
        'data_in' => 'sysgen_dut.to_register17_data_in',
15660 
        'dout' => 'to_register17.dout',
15661 
        'en' => 'sysgen_dut.to_register17_en',
15662 
      },
15663 
      'entity' => {
15664 
        'attributes' => {
15665 
          'entityAlreadyNetlisted' => 1,
15666 
          'generics' => [
15667 
          ],
15668 
          'is_floating_block' => 1,
15669 
          'mask' => {
15670 
            'Block_Handle' => 46.0009765625,
15671 
            'Block_handle' => 46.0009765625,
15672 
            'MDL_Handle' => 3.0009765625,
15673 
            'MDL_handle' => 3.0009765625,
15674 
            'arith_type' => 1,
15675 
            'bin_pt' => 14,
15676 
            'block_config' => 'sysgen_blockset:toreg_config',
15677 
            'block_handle' => 46.0009765625,
15678 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15679 
            'block_type' => 'toreg',
15680 
            'dbl_ovrd' => 0,
15681 
            'explicit_data_type' => 0,
15682 
            'init' => 0,
15683 
            'init_bit_vector' => '00000000000000000000000000000000b',
15684 
            'mdl_handle' => 3.0009765625,
15685 
            'model_handle' => 3.0009765625,
15686 
            'n_bits' => 16,
15687 
            'ownership' => 1,
15688 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15689 
            'shared_memory_name' => 'register07td',
15690 
          },
15691 
          'needs_vhdl_wrapper' => 0,
15692 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15693 
        },
15694 
        'entityName' => 'x_x7',
15695 
        'ports' => {
15696 
          'ce' => {
15697 
            'attributes' => {
15698 
              'domain' => '',
15699 
              'group' => 1,
15700 
              'isCe' => 1,
15701 
              'is_floating_block' => 1,
15702 
              'period' => 1,
15703 
              'type' => 'logic',
15704 
            },
15705 
            'direction' => 'in',
15706 
            'hdlType' => 'std_logic',
15707 
            'width' => 1,
15708 
          },
15709 
          'clk' => {
15710 
            'attributes' => {
15711 
              'domain' => '',
15712 
              'group' => 1,
15713 
              'isClk' => 1,
15714 
              'is_floating_block' => 1,
15715 
              'period' => 1,
15716 
              'type' => 'logic',
15717 
            },
15718 
            'direction' => 'in',
15719 
            'hdlType' => 'std_logic',
15720 
            'width' => 1,
15721 
          },
15722 
          'clr' => {
15723 
            'attributes' => {
15724 
              'domain' => '',
15725 
              'group' => 1,
15726 
              'isClr' => 1,
15727 
              'is_floating_block' => 1,
15728 
              'period' => 1,
15729 
              'type' => 'logic',
15730 
              'valid_bit_used' => 0,
15731 
            },
15732 
            'direction' => 'in',
15733 
            'hdlType' => 'std_logic',
15734 
            'width' => 1,
15735 
          },
15736 
          'data_in' => {
15737 
            'attributes' => {
15738 
              'bin_pt' => 0,
15739 
              'is_floating_block' => 1,
15740 
              'must_be_hdl_vector' => 1,
15741 
              'period' => 1,
15742 
              'port_id' => 0,
15743 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
15744 
              'type' => 'UFix_32_0',
15745 
            },
15746 
            'direction' => 'in',
15747 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15748 
            'width' => 32,
15749 
          },
15750 
          'dout' => {
15751 
            'attributes' => {
15752 
              'bin_pt' => 0,
15753 
              'is_floating_block' => 1,
15754 
              'must_be_hdl_vector' => 1,
15755 
              'period' => 1,
15756 
              'port_id' => 0,
15757 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
15758 
              'type' => 'UFix_32_0',
15759 
            },
15760 
            'direction' => 'out',
15761 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15762 
            'width' => 32,
15763 
          },
15764 
          'en' => {
15765 
            'attributes' => {
15766 
              'bin_pt' => 0,
15767 
              'is_floating_block' => 1,
15768 
              'must_be_hdl_vector' => 1,
15769 
              'period' => 1,
15770 
              'port_id' => 1,
15771 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
15772 
              'type' => 'Bool',
15773 
            },
15774 
            'direction' => 'in',
15775 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15776 
            'width' => 1,
15777 
          },
15778 
        },
15779 
      },
15780 
      'entityName' => 'x_x7',
15781 
    },
15782 
    'to_register18' => {
15783 
      'connections' => {
15784 
        'ce' => 'sysgen_dut.to_register18_ce',
15785 
        'clk' => 'sysgen_dut.to_register18_clk',
15786 
        'clr' => 'sysgen_dut.to_register18_clr',
15787 
        'data_in' => 'sysgen_dut.to_register18_data_in',
15788 
        'dout' => 'to_register18.dout',
15789 
        'en' => 'sysgen_dut.to_register18_en',
15790 
      },
15791 
      'entity' => {
15792 
        'attributes' => {
15793 
          'entityAlreadyNetlisted' => 1,
15794 
          'generics' => [
15795 
          ],
15796 
          'is_floating_block' => 1,
15797 
          'mask' => {
15798 
            'Block_Handle' => 47.0009765625,
15799 
            'Block_handle' => 47.0009765625,
15800 
            'MDL_Handle' => 3.0009765625,
15801 
            'MDL_handle' => 3.0009765625,
15802 
            'arith_type' => 1,
15803 
            'bin_pt' => 14,
15804 
            'block_config' => 'sysgen_blockset:toreg_config',
15805 
            'block_handle' => 47.0009765625,
15806 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15807 
            'block_type' => 'toreg',
15808 
            'dbl_ovrd' => 0,
15809 
            'explicit_data_type' => 0,
15810 
            'init' => 0,
15811 
            'init_bit_vector' => '0b',
15812 
            'mdl_handle' => 3.0009765625,
15813 
            'model_handle' => 3.0009765625,
15814 
            'n_bits' => 16,
15815 
            'ownership' => 1,
15816 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15817 
            'shared_memory_name' => 'DMA_Host2Board_Busy',
15818 
          },
15819 
          'needs_vhdl_wrapper' => 0,
15820 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15821 
        },
15822 
        'entityName' => 'x_x8',
15823 
        'ports' => {
15824 
          'ce' => {
15825 
            'attributes' => {
15826 
              'domain' => '',
15827 
              'group' => 1,
15828 
              'isCe' => 1,
15829 
              'is_floating_block' => 1,
15830 
              'period' => 1,
15831 
              'type' => 'logic',
15832 
            },
15833 
            'direction' => 'in',
15834 
            'hdlType' => 'std_logic',
15835 
            'width' => 1,
15836 
          },
15837 
          'clk' => {
15838 
            'attributes' => {
15839 
              'domain' => '',
15840 
              'group' => 1,
15841 
              'isClk' => 1,
15842 
              'is_floating_block' => 1,
15843 
              'period' => 1,
15844 
              'type' => 'logic',
15845 
            },
15846 
            'direction' => 'in',
15847 
            'hdlType' => 'std_logic',
15848 
            'width' => 1,
15849 
          },
15850 
          'clr' => {
15851 
            'attributes' => {
15852 
              'domain' => '',
15853 
              'group' => 1,
15854 
              'isClr' => 1,
15855 
              'is_floating_block' => 1,
15856 
              'period' => 1,
15857 
              'type' => 'logic',
15858 
              'valid_bit_used' => 0,
15859 
            },
15860 
            'direction' => 'in',
15861 
            'hdlType' => 'std_logic',
15862 
            'width' => 1,
15863 
          },
15864 
          'data_in' => {
15865 
            'attributes' => {
15866 
              'bin_pt' => 0,
15867 
              'is_floating_block' => 1,
15868 
              'must_be_hdl_vector' => 1,
15869 
              'period' => 1,
15870 
              'port_id' => 0,
15871 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
15872 
              'type' => 'UFix_1_0',
15873 
            },
15874 
            'direction' => 'in',
15875 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15876 
            'width' => 1,
15877 
          },
15878 
          'dout' => {
15879 
            'attributes' => {
15880 
              'bin_pt' => 0,
15881 
              'is_floating_block' => 1,
15882 
              'must_be_hdl_vector' => 1,
15883 
              'period' => 1,
15884 
              'port_id' => 0,
15885 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
15886 
              'type' => 'UFix_1_0',
15887 
            },
15888 
            'direction' => 'out',
15889 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15890 
            'width' => 1,
15891 
          },
15892 
          'en' => {
15893 
            'attributes' => {
15894 
              'bin_pt' => 0,
15895 
              'is_floating_block' => 1,
15896 
              'must_be_hdl_vector' => 1,
15897 
              'period' => 1,
15898 
              'port_id' => 1,
15899 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
15900 
              'type' => 'Bool',
15901 
            },
15902 
            'direction' => 'in',
15903 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15904 
            'width' => 1,
15905 
          },
15906 
        },
15907 
      },
15908 
      'entityName' => 'x_x8',
15909 
    },
15910 
    'to_register19' => {
15911 
      'connections' => {
15912 
        'ce' => 'sysgen_dut.to_register19_ce',
15913 
        'clk' => 'sysgen_dut.to_register19_clk',
15914 
        'clr' => 'sysgen_dut.to_register19_clr',
15915 
        'data_in' => 'sysgen_dut.to_register19_data_in',
15916 
        'dout' => 'to_register19.dout',
15917 
        'en' => 'sysgen_dut.to_register19_en',
15918 
      },
15919 
      'entity' => {
15920 
        'attributes' => {
15921 
          'entityAlreadyNetlisted' => 1,
15922 
          'generics' => [
15923 
          ],
15924 
          'is_floating_block' => 1,
15925 
          'mask' => {
15926 
            'Block_Handle' => 48.0009765625,
15927 
            'Block_handle' => 48.0009765625,
15928 
            'MDL_Handle' => 3.0009765625,
15929 
            'MDL_handle' => 3.0009765625,
15930 
            'arith_type' => 1,
15931 
            'bin_pt' => 14,
15932 
            'block_config' => 'sysgen_blockset:toreg_config',
15933 
            'block_handle' => 48.0009765625,
15934 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
15935 
            'block_type' => 'toreg',
15936 
            'dbl_ovrd' => 0,
15937 
            'explicit_data_type' => 0,
15938 
            'init' => 0,
15939 
            'init_bit_vector' => '0b',
15940 
            'mdl_handle' => 3.0009765625,
15941 
            'model_handle' => 3.0009765625,
15942 
            'n_bits' => 16,
15943 
            'ownership' => 1,
15944 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15945 
            'shared_memory_name' => 'DMA_Host2Board_Done',
15946 
          },
15947 
          'needs_vhdl_wrapper' => 0,
15948 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
15949 
        },
15950 
        'entityName' => 'x_x9',
15951 
        'ports' => {
15952 
          'ce' => {
15953 
            'attributes' => {
15954 
              'domain' => '',
15955 
              'group' => 1,
15956 
              'isCe' => 1,
15957 
              'is_floating_block' => 1,
15958 
              'period' => 1,
15959 
              'type' => 'logic',
15960 
            },
15961 
            'direction' => 'in',
15962 
            'hdlType' => 'std_logic',
15963 
            'width' => 1,
15964 
          },
15965 
          'clk' => {
15966 
            'attributes' => {
15967 
              'domain' => '',
15968 
              'group' => 1,
15969 
              'isClk' => 1,
15970 
              'is_floating_block' => 1,
15971 
              'period' => 1,
15972 
              'type' => 'logic',
15973 
            },
15974 
            'direction' => 'in',
15975 
            'hdlType' => 'std_logic',
15976 
            'width' => 1,
15977 
          },
15978 
          'clr' => {
15979 
            'attributes' => {
15980 
              'domain' => '',
15981 
              'group' => 1,
15982 
              'isClr' => 1,
15983 
              'is_floating_block' => 1,
15984 
              'period' => 1,
15985 
              'type' => 'logic',
15986 
              'valid_bit_used' => 0,
15987 
            },
15988 
            'direction' => 'in',
15989 
            'hdlType' => 'std_logic',
15990 
            'width' => 1,
15991 
          },
15992 
          'data_in' => {
15993 
            'attributes' => {
15994 
              'bin_pt' => 0,
15995 
              'is_floating_block' => 1,
15996 
              'must_be_hdl_vector' => 1,
15997 
              'period' => 1,
15998 
              'port_id' => 0,
15999 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
16000 
              'type' => 'UFix_1_0',
16001 
            },
16002 
            'direction' => 'in',
16003 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16004 
            'width' => 1,
16005 
          },
16006 
          'dout' => {
16007 
            'attributes' => {
16008 
              'bin_pt' => 0,
16009 
              'is_floating_block' => 1,
16010 
              'must_be_hdl_vector' => 1,
16011 
              'period' => 1,
16012 
              'port_id' => 0,
16013 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
16014 
              'type' => 'UFix_1_0',
16015 
            },
16016 
            'direction' => 'out',
16017 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16018 
            'width' => 1,
16019 
          },
16020 
          'en' => {
16021 
            'attributes' => {
16022 
              'bin_pt' => 0,
16023 
              'is_floating_block' => 1,
16024 
              'must_be_hdl_vector' => 1,
16025 
              'period' => 1,
16026 
              'port_id' => 1,
16027 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
16028 
              'type' => 'Bool',
16029 
            },
16030 
            'direction' => 'in',
16031 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16032 
            'width' => 1,
16033 
          },
16034 
        },
16035 
      },
16036 
      'entityName' => 'x_x9',
16037 
    },
16038 
    'to_register2' => {
16039 
      'connections' => {
16040 
        'ce' => 'sysgen_dut.to_register2_ce',
16041 
        'clk' => 'sysgen_dut.to_register2_clk',
16042 
        'clr' => 'sysgen_dut.to_register2_clr',
16043 
        'data_in' => 'sysgen_dut.to_register2_data_in',
16044 
        'dout' => 'to_register2.dout',
16045 
        'en' => 'sysgen_dut.to_register2_en',
16046 
      },
16047 
      'entity' => {
16048 
        'attributes' => {
16049 
          'entityAlreadyNetlisted' => 1,
16050 
          'generics' => [
16051 
          ],
16052 
          'is_floating_block' => 1,
16053 
          'mask' => {
16054 
            'Block_Handle' => 49.0009765625,
16055 
            'Block_handle' => 49.0009765625,
16056 
            'MDL_Handle' => 3.0009765625,
16057 
            'MDL_handle' => 3.0009765625,
16058 
            'arith_type' => 1,
16059 
            'bin_pt' => 14,
16060 
            'block_config' => 'sysgen_blockset:toreg_config',
16061 
            'block_handle' => 49.0009765625,
16062 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
16063 
            'block_type' => 'toreg',
16064 
            'dbl_ovrd' => 0,
16065 
            'explicit_data_type' => 0,
16066 
            'init' => 0,
16067 
            'init_bit_vector' => '00000000000000000000000000000000b',
16068 
            'mdl_handle' => 3.0009765625,
16069 
            'model_handle' => 3.0009765625,
16070 
            'n_bits' => 16,
16071 
            'ownership' => 1,
16072 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16073 
            'shared_memory_name' => 'debug3i',
16074 
          },
16075 
          'needs_vhdl_wrapper' => 0,
16076 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
16077 
        },
16078 
        'entityName' => 'x_x10',
16079 
        'ports' => {
16080 
          'ce' => {
16081 
            'attributes' => {
16082 
              'domain' => '',
16083 
              'group' => 1,
16084 
              'isCe' => 1,
16085 
              'is_floating_block' => 1,
16086 
              'period' => 1,
16087 
              'type' => 'logic',
16088 
            },
16089 
            'direction' => 'in',
16090 
            'hdlType' => 'std_logic',
16091 
            'width' => 1,
16092 
          },
16093 
          'clk' => {
16094 
            'attributes' => {
16095 
              'domain' => '',
16096 
              'group' => 1,
16097 
              'isClk' => 1,
16098 
              'is_floating_block' => 1,
16099 
              'period' => 1,
16100 
              'type' => 'logic',
16101 
            },
16102 
            'direction' => 'in',
16103 
            'hdlType' => 'std_logic',
16104 
            'width' => 1,
16105 
          },
16106 
          'clr' => {
16107 
            'attributes' => {
16108 
              'domain' => '',
16109 
              'group' => 1,
16110 
              'isClr' => 1,
16111 
              'is_floating_block' => 1,
16112 
              'period' => 1,
16113 
              'type' => 'logic',
16114 
              'valid_bit_used' => 0,
16115 
            },
16116 
            'direction' => 'in',
16117 
            'hdlType' => 'std_logic',
16118 
            'width' => 1,
16119 
          },
16120 
          'data_in' => {
16121 
            'attributes' => {
16122 
              'bin_pt' => 0,
16123 
              'is_floating_block' => 1,
16124 
              'must_be_hdl_vector' => 1,
16125 
              'period' => 1,
16126 
              'port_id' => 0,
16127 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
16128 
              'type' => 'UFix_32_0',
16129 
            },
16130 
            'direction' => 'in',
16131 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16132 
            'width' => 32,
16133 
          },
16134 
          'dout' => {
16135 
            'attributes' => {
16136 
              'bin_pt' => 0,
16137 
              'is_floating_block' => 1,
16138 
              'must_be_hdl_vector' => 1,
16139 
              'period' => 1,
16140 
              'port_id' => 0,
16141 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
16142 
              'type' => 'UFix_32_0',
16143 
            },
16144 
            'direction' => 'out',
16145 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16146 
            'width' => 32,
16147 
          },
16148 
          'en' => {
16149 
            'attributes' => {
16150 
              'bin_pt' => 0,
16151 
              'is_floating_block' => 1,
16152 
              'must_be_hdl_vector' => 1,
16153 
              'period' => 1,
16154 
              'port_id' => 1,
16155 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
16156 
              'type' => 'Bool',
16157 
            },
16158 
            'direction' => 'in',
16159 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16160 
            'width' => 1,
16161 
          },
16162 
        },
16163 
      },
16164 
      'entityName' => 'x_x10',
16165 
    },
16166 
    'to_register20' => {
16167 
      'connections' => {
16168 
        'ce' => 'sysgen_dut.to_register20_ce',
16169 
        'clk' => 'sysgen_dut.to_register20_clk',
16170 
        'clr' => 'sysgen_dut.to_register20_clr',
16171 
        'data_in' => 'sysgen_dut.to_register20_data_in',
16172 
        'dout' => 'to_register20.dout',
16173 
        'en' => 'sysgen_dut.to_register20_en',
16174 
      },
16175 
      'entity' => {
16176 
        'attributes' => {
16177 
          'entityAlreadyNetlisted' => 1,
16178 
          'generics' => [
16179 
          ],
16180 
          'is_floating_block' => 1,
16181 
          'mask' => {
16182 
            'Block_Handle' => 50.0009765625,
16183 
            'Block_handle' => 50.0009765625,
16184 
            'MDL_Handle' => 3.0009765625,
16185 
            'MDL_handle' => 3.0009765625,
16186 
            'arith_type' => 1,
16187 
            'bin_pt' => 14,
16188 
            'block_config' => 'sysgen_blockset:toreg_config',
16189 
            'block_handle' => 50.0009765625,
16190 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
16191 
            'block_type' => 'toreg',
16192 
            'dbl_ovrd' => 0,
16193 
            'explicit_data_type' => 0,
16194 
            'init' => 0,
16195 
            'init_bit_vector' => '00000000000000000000000000000000b',
16196 
            'mdl_handle' => 3.0009765625,
16197 
            'model_handle' => 3.0009765625,
16198 
            'n_bits' => 16,
16199 
            'ownership' => 1,
16200 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16201 
            'shared_memory_name' => 'debug4i',
16202 
          },
16203 
          'needs_vhdl_wrapper' => 0,
16204 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
16205 
        },
16206 
        'entityName' => 'x_x11',
16207 
        'ports' => {
16208 
          'ce' => {
16209 
            'attributes' => {
16210 
              'domain' => '',
16211 
              'group' => 1,
16212 
              'isCe' => 1,
16213 
              'is_floating_block' => 1,
16214 
              'period' => 1,
16215 
              'type' => 'logic',
16216 
            },
16217 
            'direction' => 'in',
16218 
            'hdlType' => 'std_logic',
16219 
            'width' => 1,
16220 
          },
16221 
          'clk' => {
16222 
            'attributes' => {
16223 
              'domain' => '',
16224 
              'group' => 1,
16225 
              'isClk' => 1,
16226 
              'is_floating_block' => 1,
16227 
              'period' => 1,
16228 
              'type' => 'logic',
16229 
            },
16230 
            'direction' => 'in',
16231 
            'hdlType' => 'std_logic',
16232 
            'width' => 1,
16233 
          },
16234 
          'clr' => {
16235 
            'attributes' => {
16236 
              'domain' => '',
16237 
              'group' => 1,
16238 
              'isClr' => 1,
16239 
              'is_floating_block' => 1,
16240 
              'period' => 1,
16241 
              'type' => 'logic',
16242 
              'valid_bit_used' => 0,
16243 
            },
16244 
            'direction' => 'in',
16245 
            'hdlType' => 'std_logic',
16246 
            'width' => 1,
16247 
          },
16248 
          'data_in' => {
16249 
            'attributes' => {
16250 
              'bin_pt' => 0,
16251 
              'is_floating_block' => 1,
16252 
              'must_be_hdl_vector' => 1,
16253 
              'period' => 1,
16254 
              'port_id' => 0,
16255 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
16256 
              'type' => 'UFix_32_0',
16257 
            },
16258 
            'direction' => 'in',
16259 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16260 
            'width' => 32,
16261 
          },
16262 
          'dout' => {
16263 
            'attributes' => {
16264 
              'bin_pt' => 0,
16265 
              'is_floating_block' => 1,
16266 
              'must_be_hdl_vector' => 1,
16267 
              'period' => 1,
16268 
              'port_id' => 0,
16269 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
16270 
              'type' => 'UFix_32_0',
16271 
            },
16272 
            'direction' => 'out',
16273 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16274 
            'width' => 32,
16275 
          },
16276 
          'en' => {
16277 
            'attributes' => {
16278 
              'bin_pt' => 0,
16279 
              'is_floating_block' => 1,
16280 
              'must_be_hdl_vector' => 1,
16281 
              'period' => 1,
16282 
              'port_id' => 1,
16283 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
16284 
              'type' => 'Bool',
16285 
            },
16286 
            'direction' => 'in',
16287 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16288 
            'width' => 1,
16289 
          },
16290 
        },
16291 
      },
16292 
      'entityName' => 'x_x11',
16293 
    },
16294 
    'to_register21' => {
16295 
      'connections' => {
16296 
        'ce' => 'sysgen_dut.to_register21_ce',
16297 
        'clk' => 'sysgen_dut.to_register21_clk',
16298 
        'clr' => 'sysgen_dut.to_register21_clr',
16299 
        'data_in' => 'sysgen_dut.to_register21_data_in',
16300 
        'dout' => 'to_register21.dout',
16301 
        'en' => 'sysgen_dut.to_register21_en',
16302 
      },
16303 
      'entity' => {
16304 
        'attributes' => {
16305 
          'entityAlreadyNetlisted' => 1,
16306 
          'generics' => [
16307 
          ],
16308 
          'is_floating_block' => 1,
16309 
          'mask' => {
16310 
            'Block_Handle' => 51.0009765625,
16311 
            'Block_handle' => 51.0009765625,
16312 
            'MDL_Handle' => 3.0009765625,
16313 
            'MDL_handle' => 3.0009765625,
16314 
            'arith_type' => 1,
16315 
            'bin_pt' => 14,
16316 
            'block_config' => 'sysgen_blockset:toreg_config',
16317 
            'block_handle' => 51.0009765625,
16318 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
16319 
            'block_type' => 'toreg',
16320 
            'dbl_ovrd' => 0,
16321 
            'explicit_data_type' => 0,
16322 
            'init' => 0,
16323 
            'init_bit_vector' => '0b',
16324 
            'mdl_handle' => 3.0009765625,
16325 
            'model_handle' => 3.0009765625,
16326 
            'n_bits' => 16,
16327 
            'ownership' => 1,
16328 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16329 
            'shared_memory_name' => 'register09tv',
16330 
          },
16331 
          'needs_vhdl_wrapper' => 0,
16332 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
16333 
        },
16334 
        'entityName' => 'x_x12',
16335 
        'ports' => {
16336 
          'ce' => {
16337 
            'attributes' => {
16338 
              'domain' => '',
16339 
              'group' => 1,
16340 
              'isCe' => 1,
16341 
              'is_floating_block' => 1,
16342 
              'period' => 1,
16343 
              'type' => 'logic',
16344 
            },
16345 
            'direction' => 'in',
16346 
            'hdlType' => 'std_logic',
16347 
            'width' => 1,
16348 
          },
16349 
          'clk' => {
16350 
            'attributes' => {
16351 
              'domain' => '',
16352 
              'group' => 1,
16353 
              'isClk' => 1,
16354 
              'is_floating_block' => 1,
16355 
              'period' => 1,
16356 
              'type' => 'logic',
16357 
            },
16358 
            'direction' => 'in',
16359 
            'hdlType' => 'std_logic',
16360 
            'width' => 1,
16361 
          },
16362 
          'clr' => {
16363 
            'attributes' => {
16364 
              'domain' => '',
16365 
              'group' => 1,
16366 
              'isClr' => 1,
16367 
              'is_floating_block' => 1,
16368 
              'period' => 1,
16369 
              'type' => 'logic',
16370 
              'valid_bit_used' => 0,
16371 
            },
16372 
            'direction' => 'in',
16373 
            'hdlType' => 'std_logic',
16374 
            'width' => 1,
16375 
          },
16376 
          'data_in' => {
16377 
            'attributes' => {
16378 
              'bin_pt' => 0,
16379 
              'is_floating_block' => 1,
16380 
              'must_be_hdl_vector' => 1,
16381 
              'period' => 1,
16382 
              'port_id' => 0,
16383 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
16384 
              'type' => 'Bool',
16385 
            },
16386 
            'direction' => 'in',
16387 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16388 
            'width' => 1,
16389 
          },
16390 
          'dout' => {
16391 
            'attributes' => {
16392 
              'bin_pt' => 0,
16393 
              'is_floating_block' => 1,
16394 
              'must_be_hdl_vector' => 1,
16395 
              'period' => 1,
16396 
              'port_id' => 0,
16397 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
16398 
              'type' => 'Bool',
16399 
            },
16400 
            'direction' => 'out',
16401 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16402 
            'width' => 1,
16403 
          },
16404 
          'en' => {
16405 
            'attributes' => {
16406 
              'bin_pt' => 0,
16407 
              'is_floating_block' => 1,
16408 
              'must_be_hdl_vector' => 1,
16409 
              'period' => 1,
16410 
              'port_id' => 1,
16411 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
16412 
              'type' => 'Bool',
16413 
            },
16414 
            'direction' => 'in',
16415 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16416 
            'width' => 1,
16417 
          },
16418 
        },
16419 
      },
16420 
      'entityName' => 'x_x12',
16421 
    },
16422 
    'to_register22' => {
16423 
      'connections' => {
16424 
        'ce' => 'sysgen_dut.to_register22_ce',
16425 
        'clk' => 'sysgen_dut.to_register22_clk',
16426 
        'clr' => 'sysgen_dut.to_register22_clr',
16427 
        'data_in' => 'sysgen_dut.to_register22_data_in',
16428 
        'dout' => 'to_register22.dout',
16429 
        'en' => 'sysgen_dut.to_register22_en',
16430 
      },
16431 
      'entity' => {
16432 
        'attributes' => {
16433 
          'entityAlreadyNetlisted' => 1,
16434 
          'generics' => [
16435 
          ],
16436 
          'is_floating_block' => 1,
16437 
          'mask' => {
16438 
            'Block_Handle' => 52.0009765625,
16439 
            'Block_handle' => 52.0009765625,
16440 
            'MDL_Handle' => 3.0009765625,
16441 
            'MDL_handle' => 3.0009765625,
16442 
            'arith_type' => 1,
16443 
            'bin_pt' => 14,
16444 
            'block_config' => 'sysgen_blockset:toreg_config',
16445 
            'block_handle' => 52.0009765625,
16446 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16447 
            'block_type' => 'toreg',
16448 
            'dbl_ovrd' => 0,
16449 
            'explicit_data_type' => 0,
16450 
            'init' => 0,
16451 
            'init_bit_vector' => '00000000000000000000000000000000b',
16452 
            'mdl_handle' => 3.0009765625,
16453 
            'model_handle' => 3.0009765625,
16454 
            'n_bits' => 16,
16455 
            'ownership' => 1,
16456 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16457 
            'shared_memory_name' => 'register09td',
16458 
          },
16459 
          'needs_vhdl_wrapper' => 0,
16460 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16461 
        },
16462 
        'entityName' => 'x_x13',
16463 
        'ports' => {
16464 
          'ce' => {
16465 
            'attributes' => {
16466 
              'domain' => '',
16467 
              'group' => 1,
16468 
              'isCe' => 1,
16469 
              'is_floating_block' => 1,
16470 
              'period' => 1,
16471 
              'type' => 'logic',
16472 
            },
16473 
            'direction' => 'in',
16474 
            'hdlType' => 'std_logic',
16475 
            'width' => 1,
16476 
          },
16477 
          'clk' => {
16478 
            'attributes' => {
16479 
              'domain' => '',
16480 
              'group' => 1,
16481 
              'isClk' => 1,
16482 
              'is_floating_block' => 1,
16483 
              'period' => 1,
16484 
              'type' => 'logic',
16485 
            },
16486 
            'direction' => 'in',
16487 
            'hdlType' => 'std_logic',
16488 
            'width' => 1,
16489 
          },
16490 
          'clr' => {
16491 
            'attributes' => {
16492 
              'domain' => '',
16493 
              'group' => 1,
16494 
              'isClr' => 1,
16495 
              'is_floating_block' => 1,
16496 
              'period' => 1,
16497 
              'type' => 'logic',
16498 
              'valid_bit_used' => 0,
16499 
            },
16500 
            'direction' => 'in',
16501 
            'hdlType' => 'std_logic',
16502 
            'width' => 1,
16503 
          },
16504 
          'data_in' => {
16505 
            'attributes' => {
16506 
              'bin_pt' => 0,
16507 
              'is_floating_block' => 1,
16508 
              'must_be_hdl_vector' => 1,
16509 
              'period' => 1,
16510 
              'port_id' => 0,
16511 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
16512 
              'type' => 'UFix_32_0',
16513 
            },
16514 
            'direction' => 'in',
16515 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16516 
            'width' => 32,
16517 
          },
16518 
          'dout' => {
16519 
            'attributes' => {
16520 
              'bin_pt' => 0,
16521 
              'is_floating_block' => 1,
16522 
              'must_be_hdl_vector' => 1,
16523 
              'period' => 1,
16524 
              'port_id' => 0,
16525 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
16526 
              'type' => 'UFix_32_0',
16527 
            },
16528 
            'direction' => 'out',
16529 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16530 
            'width' => 32,
16531 
          },
16532 
          'en' => {
16533 
            'attributes' => {
16534 
              'bin_pt' => 0,
16535 
              'is_floating_block' => 1,
16536 
              'must_be_hdl_vector' => 1,
16537 
              'period' => 1,
16538 
              'port_id' => 1,
16539 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
16540 
              'type' => 'Bool',
16541 
            },
16542 
            'direction' => 'in',
16543 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16544 
            'width' => 1,
16545 
          },
16546 
        },
16547 
      },
16548 
      'entityName' => 'x_x13',
16549 
    },
16550 
    'to_register23' => {
16551 
      'connections' => {
16552 
        'ce' => 'sysgen_dut.to_register23_ce',
16553 
        'clk' => 'sysgen_dut.to_register23_clk',
16554 
        'clr' => 'sysgen_dut.to_register23_clr',
16555 
        'data_in' => 'sysgen_dut.to_register23_data_in',
16556 
        'dout' => 'to_register23.dout',
16557 
        'en' => 'sysgen_dut.to_register23_en',
16558 
      },
16559 
      'entity' => {
16560 
        'attributes' => {
16561 
          'entityAlreadyNetlisted' => 1,
16562 
          'generics' => [
16563 
          ],
16564 
          'is_floating_block' => 1,
16565 
          'mask' => {
16566 
            'Block_Handle' => 53.0009765625,
16567 
            'Block_handle' => 53.0009765625,
16568 
            'MDL_Handle' => 3.0009765625,
16569 
            'MDL_handle' => 3.0009765625,
16570 
            'arith_type' => 1,
16571 
            'bin_pt' => 14,
16572 
            'block_config' => 'sysgen_blockset:toreg_config',
16573 
            'block_handle' => 53.0009765625,
16574 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16575 
            'block_type' => 'toreg',
16576 
            'dbl_ovrd' => 0,
16577 
            'explicit_data_type' => 0,
16578 
            'init' => 0,
16579 
            'init_bit_vector' => '0b',
16580 
            'mdl_handle' => 3.0009765625,
16581 
            'model_handle' => 3.0009765625,
16582 
            'n_bits' => 16,
16583 
            'ownership' => 1,
16584 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16585 
            'shared_memory_name' => 'register10tv',
16586 
          },
16587 
          'needs_vhdl_wrapper' => 0,
16588 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16589 
        },
16590 
        'entityName' => 'x_x14',
16591 
        'ports' => {
16592 
          'ce' => {
16593 
            'attributes' => {
16594 
              'domain' => '',
16595 
              'group' => 1,
16596 
              'isCe' => 1,
16597 
              'is_floating_block' => 1,
16598 
              'period' => 1,
16599 
              'type' => 'logic',
16600 
            },
16601 
            'direction' => 'in',
16602 
            'hdlType' => 'std_logic',
16603 
            'width' => 1,
16604 
          },
16605 
          'clk' => {
16606 
            'attributes' => {
16607 
              'domain' => '',
16608 
              'group' => 1,
16609 
              'isClk' => 1,
16610 
              'is_floating_block' => 1,
16611 
              'period' => 1,
16612 
              'type' => 'logic',
16613 
            },
16614 
            'direction' => 'in',
16615 
            'hdlType' => 'std_logic',
16616 
            'width' => 1,
16617 
          },
16618 
          'clr' => {
16619 
            'attributes' => {
16620 
              'domain' => '',
16621 
              'group' => 1,
16622 
              'isClr' => 1,
16623 
              'is_floating_block' => 1,
16624 
              'period' => 1,
16625 
              'type' => 'logic',
16626 
              'valid_bit_used' => 0,
16627 
            },
16628 
            'direction' => 'in',
16629 
            'hdlType' => 'std_logic',
16630 
            'width' => 1,
16631 
          },
16632 
          'data_in' => {
16633 
            'attributes' => {
16634 
              'bin_pt' => 0,
16635 
              'is_floating_block' => 1,
16636 
              'must_be_hdl_vector' => 1,
16637 
              'period' => 1,
16638 
              'port_id' => 0,
16639 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
16640 
              'type' => 'Bool',
16641 
            },
16642 
            'direction' => 'in',
16643 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16644 
            'width' => 1,
16645 
          },
16646 
          'dout' => {
16647 
            'attributes' => {
16648 
              'bin_pt' => 0,
16649 
              'is_floating_block' => 1,
16650 
              'must_be_hdl_vector' => 1,
16651 
              'period' => 1,
16652 
              'port_id' => 0,
16653 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
16654 
              'type' => 'Bool',
16655 
            },
16656 
            'direction' => 'out',
16657 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16658 
            'width' => 1,
16659 
          },
16660 
          'en' => {
16661 
            'attributes' => {
16662 
              'bin_pt' => 0,
16663 
              'is_floating_block' => 1,
16664 
              'must_be_hdl_vector' => 1,
16665 
              'period' => 1,
16666 
              'port_id' => 1,
16667 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
16668 
              'type' => 'Bool',
16669 
            },
16670 
            'direction' => 'in',
16671 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16672 
            'width' => 1,
16673 
          },
16674 
        },
16675 
      },
16676 
      'entityName' => 'x_x14',
16677 
    },
16678 
    'to_register24' => {
16679 
      'connections' => {
16680 
        'ce' => 'sysgen_dut.to_register24_ce',
16681 
        'clk' => 'sysgen_dut.to_register24_clk',
16682 
        'clr' => 'sysgen_dut.to_register24_clr',
16683 
        'data_in' => 'sysgen_dut.to_register24_data_in',
16684 
        'dout' => 'to_register24.dout',
16685 
        'en' => 'sysgen_dut.to_register24_en',
16686 
      },
16687 
      'entity' => {
16688 
        'attributes' => {
16689 
          'entityAlreadyNetlisted' => 1,
16690 
          'generics' => [
16691 
          ],
16692 
          'is_floating_block' => 1,
16693 
          'mask' => {
16694 
            'Block_Handle' => 54.0009765625,
16695 
            'Block_handle' => 54.0009765625,
16696 
            'MDL_Handle' => 3.0009765625,
16697 
            'MDL_handle' => 3.0009765625,
16698 
            'arith_type' => 1,
16699 
            'bin_pt' => 14,
16700 
            'block_config' => 'sysgen_blockset:toreg_config',
16701 
            'block_handle' => 54.0009765625,
16702 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16703 
            'block_type' => 'toreg',
16704 
            'dbl_ovrd' => 0,
16705 
            'explicit_data_type' => 0,
16706 
            'init' => 0,
16707 
            'init_bit_vector' => '00000000000000000000000000000000b',
16708 
            'mdl_handle' => 3.0009765625,
16709 
            'model_handle' => 3.0009765625,
16710 
            'n_bits' => 16,
16711 
            'ownership' => 1,
16712 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16713 
            'shared_memory_name' => 'register10td',
16714 
          },
16715 
          'needs_vhdl_wrapper' => 0,
16716 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16717 
        },
16718 
        'entityName' => 'x_x15',
16719 
        'ports' => {
16720 
          'ce' => {
16721 
            'attributes' => {
16722 
              'domain' => '',
16723 
              'group' => 1,
16724 
              'isCe' => 1,
16725 
              'is_floating_block' => 1,
16726 
              'period' => 1,
16727 
              'type' => 'logic',
16728 
            },
16729 
            'direction' => 'in',
16730 
            'hdlType' => 'std_logic',
16731 
            'width' => 1,
16732 
          },
16733 
          'clk' => {
16734 
            'attributes' => {
16735 
              'domain' => '',
16736 
              'group' => 1,
16737 
              'isClk' => 1,
16738 
              'is_floating_block' => 1,
16739 
              'period' => 1,
16740 
              'type' => 'logic',
16741 
            },
16742 
            'direction' => 'in',
16743 
            'hdlType' => 'std_logic',
16744 
            'width' => 1,
16745 
          },
16746 
          'clr' => {
16747 
            'attributes' => {
16748 
              'domain' => '',
16749 
              'group' => 1,
16750 
              'isClr' => 1,
16751 
              'is_floating_block' => 1,
16752 
              'period' => 1,
16753 
              'type' => 'logic',
16754 
              'valid_bit_used' => 0,
16755 
            },
16756 
            'direction' => 'in',
16757 
            'hdlType' => 'std_logic',
16758 
            'width' => 1,
16759 
          },
16760 
          'data_in' => {
16761 
            'attributes' => {
16762 
              'bin_pt' => 0,
16763 
              'is_floating_block' => 1,
16764 
              'must_be_hdl_vector' => 1,
16765 
              'period' => 1,
16766 
              'port_id' => 0,
16767 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
16768 
              'type' => 'UFix_32_0',
16769 
            },
16770 
            'direction' => 'in',
16771 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16772 
            'width' => 32,
16773 
          },
16774 
          'dout' => {
16775 
            'attributes' => {
16776 
              'bin_pt' => 0,
16777 
              'is_floating_block' => 1,
16778 
              'must_be_hdl_vector' => 1,
16779 
              'period' => 1,
16780 
              'port_id' => 0,
16781 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
16782 
              'type' => 'UFix_32_0',
16783 
            },
16784 
            'direction' => 'out',
16785 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16786 
            'width' => 32,
16787 
          },
16788 
          'en' => {
16789 
            'attributes' => {
16790 
              'bin_pt' => 0,
16791 
              'is_floating_block' => 1,
16792 
              'must_be_hdl_vector' => 1,
16793 
              'period' => 1,
16794 
              'port_id' => 1,
16795 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
16796 
              'type' => 'Bool',
16797 
            },
16798 
            'direction' => 'in',
16799 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16800 
            'width' => 1,
16801 
          },
16802 
        },
16803 
      },
16804 
      'entityName' => 'x_x15',
16805 
    },
16806 
    'to_register25' => {
16807 
      'connections' => {
16808 
        'ce' => 'sysgen_dut.to_register25_ce',
16809 
        'clk' => 'sysgen_dut.to_register25_clk',
16810 
        'clr' => 'sysgen_dut.to_register25_clr',
16811 
        'data_in' => 'sysgen_dut.to_register25_data_in',
16812 
        'dout' => 'to_register25.dout',
16813 
        'en' => 'sysgen_dut.to_register25_en',
16814 
      },
16815 
      'entity' => {
16816 
        'attributes' => {
16817 
          'entityAlreadyNetlisted' => 1,
16818 
          'generics' => [
16819 
          ],
16820 
          'is_floating_block' => 1,
16821 
          'mask' => {
16822 
            'Block_Handle' => 55.0009765625,
16823 
            'Block_handle' => 55.0009765625,
16824 
            'MDL_Handle' => 3.0009765625,
16825 
            'MDL_handle' => 3.0009765625,
16826 
            'arith_type' => 1,
16827 
            'bin_pt' => 14,
16828 
            'block_config' => 'sysgen_blockset:toreg_config',
16829 
            'block_handle' => 55.0009765625,
16830 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16831 
            'block_type' => 'toreg',
16832 
            'dbl_ovrd' => 0,
16833 
            'explicit_data_type' => 0,
16834 
            'init' => 0,
16835 
            'init_bit_vector' => '0b',
16836 
            'mdl_handle' => 3.0009765625,
16837 
            'model_handle' => 3.0009765625,
16838 
            'n_bits' => 16,
16839 
            'ownership' => 1,
16840 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16841 
            'shared_memory_name' => 'register08tv',
16842 
          },
16843 
          'needs_vhdl_wrapper' => 0,
16844 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16845 
        },
16846 
        'entityName' => 'x_x16',
16847 
        'ports' => {
16848 
          'ce' => {
16849 
            'attributes' => {
16850 
              'domain' => '',
16851 
              'group' => 1,
16852 
              'isCe' => 1,
16853 
              'is_floating_block' => 1,
16854 
              'period' => 1,
16855 
              'type' => 'logic',
16856 
            },
16857 
            'direction' => 'in',
16858 
            'hdlType' => 'std_logic',
16859 
            'width' => 1,
16860 
          },
16861 
          'clk' => {
16862 
            'attributes' => {
16863 
              'domain' => '',
16864 
              'group' => 1,
16865 
              'isClk' => 1,
16866 
              'is_floating_block' => 1,
16867 
              'period' => 1,
16868 
              'type' => 'logic',
16869 
            },
16870 
            'direction' => 'in',
16871 
            'hdlType' => 'std_logic',
16872 
            'width' => 1,
16873 
          },
16874 
          'clr' => {
16875 
            'attributes' => {
16876 
              'domain' => '',
16877 
              'group' => 1,
16878 
              'isClr' => 1,
16879 
              'is_floating_block' => 1,
16880 
              'period' => 1,
16881 
              'type' => 'logic',
16882 
              'valid_bit_used' => 0,
16883 
            },
16884 
            'direction' => 'in',
16885 
            'hdlType' => 'std_logic',
16886 
            'width' => 1,
16887 
          },
16888 
          'data_in' => {
16889 
            'attributes' => {
16890 
              'bin_pt' => 0,
16891 
              'is_floating_block' => 1,
16892 
              'must_be_hdl_vector' => 1,
16893 
              'period' => 1,
16894 
              'port_id' => 0,
16895 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
16896 
              'type' => 'Bool',
16897 
            },
16898 
            'direction' => 'in',
16899 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16900 
            'width' => 1,
16901 
          },
16902 
          'dout' => {
16903 
            'attributes' => {
16904 
              'bin_pt' => 0,
16905 
              'is_floating_block' => 1,
16906 
              'must_be_hdl_vector' => 1,
16907 
              'period' => 1,
16908 
              'port_id' => 0,
16909 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
16910 
              'type' => 'Bool',
16911 
            },
16912 
            'direction' => 'out',
16913 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16914 
            'width' => 1,
16915 
          },
16916 
          'en' => {
16917 
            'attributes' => {
16918 
              'bin_pt' => 0,
16919 
              'is_floating_block' => 1,
16920 
              'must_be_hdl_vector' => 1,
16921 
              'period' => 1,
16922 
              'port_id' => 1,
16923 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
16924 
              'type' => 'Bool',
16925 
            },
16926 
            'direction' => 'in',
16927 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16928 
            'width' => 1,
16929 
          },
16930 
        },
16931 
      },
16932 
      'entityName' => 'x_x16',
16933 
    },
16934 
    'to_register26' => {
16935 
      'connections' => {
16936 
        'ce' => 'sysgen_dut.to_register26_ce',
16937 
        'clk' => 'sysgen_dut.to_register26_clk',
16938 
        'clr' => 'sysgen_dut.to_register26_clr',
16939 
        'data_in' => 'sysgen_dut.to_register26_data_in',
16940 
        'dout' => 'to_register26.dout',
16941 
        'en' => 'sysgen_dut.to_register26_en',
16942 
      },
16943 
      'entity' => {
16944 
        'attributes' => {
16945 
          'entityAlreadyNetlisted' => 1,
16946 
          'generics' => [
16947 
          ],
16948 
          'is_floating_block' => 1,
16949 
          'mask' => {
16950 
            'Block_Handle' => 56.0009765625,
16951 
            'Block_handle' => 56.0009765625,
16952 
            'MDL_Handle' => 3.0009765625,
16953 
            'MDL_handle' => 3.0009765625,
16954 
            'arith_type' => 1,
16955 
            'bin_pt' => 14,
16956 
            'block_config' => 'sysgen_blockset:toreg_config',
16957 
            'block_handle' => 56.0009765625,
16958 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
16959 
            'block_type' => 'toreg',
16960 
            'dbl_ovrd' => 0,
16961 
            'explicit_data_type' => 0,
16962 
            'init' => 0,
16963 
            'init_bit_vector' => '00000000000000000000000000000000b',
16964 
            'mdl_handle' => 3.0009765625,
16965 
            'model_handle' => 3.0009765625,
16966 
            'n_bits' => 16,
16967 
            'ownership' => 1,
16968 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16969 
            'shared_memory_name' => 'register08td',
16970 
          },
16971 
          'needs_vhdl_wrapper' => 0,
16972 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
16973 
        },
16974 
        'entityName' => 'x_x17',
16975 
        'ports' => {
16976 
          'ce' => {
16977 
            'attributes' => {
16978 
              'domain' => '',
16979 
              'group' => 1,
16980 
              'isCe' => 1,
16981 
              'is_floating_block' => 1,
16982 
              'period' => 1,
16983 
              'type' => 'logic',
16984 
            },
16985 
            'direction' => 'in',
16986 
            'hdlType' => 'std_logic',
16987 
            'width' => 1,
16988 
          },
16989 
          'clk' => {
16990 
            'attributes' => {
16991 
              'domain' => '',
16992 
              'group' => 1,
16993 
              'isClk' => 1,
16994 
              'is_floating_block' => 1,
16995 
              'period' => 1,
16996 
              'type' => 'logic',
16997 
            },
16998 
            'direction' => 'in',
16999 
            'hdlType' => 'std_logic',
17000 
            'width' => 1,
17001 
          },
17002 
          'clr' => {
17003 
            'attributes' => {
17004 
              'domain' => '',
17005 
              'group' => 1,
17006 
              'isClr' => 1,
17007 
              'is_floating_block' => 1,
17008 
              'period' => 1,
17009 
              'type' => 'logic',
17010 
              'valid_bit_used' => 0,
17011 
            },
17012 
            'direction' => 'in',
17013 
            'hdlType' => 'std_logic',
17014 
            'width' => 1,
17015 
          },
17016 
          'data_in' => {
17017 
            'attributes' => {
17018 
              'bin_pt' => 0,
17019 
              'is_floating_block' => 1,
17020 
              'must_be_hdl_vector' => 1,
17021 
              'period' => 1,
17022 
              'port_id' => 0,
17023 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
17024 
              'type' => 'UFix_32_0',
17025 
            },
17026 
            'direction' => 'in',
17027 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17028 
            'width' => 32,
17029 
          },
17030 
          'dout' => {
17031 
            'attributes' => {
17032 
              'bin_pt' => 0,
17033 
              'is_floating_block' => 1,
17034 
              'must_be_hdl_vector' => 1,
17035 
              'period' => 1,
17036 
              'port_id' => 0,
17037 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
17038 
              'type' => 'UFix_32_0',
17039 
            },
17040 
            'direction' => 'out',
17041 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17042 
            'width' => 32,
17043 
          },
17044 
          'en' => {
17045 
            'attributes' => {
17046 
              'bin_pt' => 0,
17047 
              'is_floating_block' => 1,
17048 
              'must_be_hdl_vector' => 1,
17049 
              'period' => 1,
17050 
              'port_id' => 1,
17051 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
17052 
              'type' => 'Bool',
17053 
            },
17054 
            'direction' => 'in',
17055 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17056 
            'width' => 1,
17057 
          },
17058 
        },
17059 
      },
17060 
      'entityName' => 'x_x17',
17061 
    },
17062 
    'to_register27' => {
17063 
      'connections' => {
17064 
        'ce' => 'sysgen_dut.to_register27_ce',
17065 
        'clk' => 'sysgen_dut.to_register27_clk',
17066 
        'clr' => 'sysgen_dut.to_register27_clr',
17067 
        'data_in' => 'sysgen_dut.to_register27_data_in',
17068 
        'dout' => 'to_register27.dout',
17069 
        'en' => 'sysgen_dut.to_register27_en',
17070 
      },
17071 
      'entity' => {
17072 
        'attributes' => {
17073 
          'entityAlreadyNetlisted' => 1,
17074 
          'generics' => [
17075 
          ],
17076 
          'is_floating_block' => 1,
17077 
          'mask' => {
17078 
            'Block_Handle' => 57.0009765625,
17079 
            'Block_handle' => 57.0009765625,
17080 
            'MDL_Handle' => 3.0009765625,
17081 
            'MDL_handle' => 3.0009765625,
17082 
            'arith_type' => 1,
17083 
            'bin_pt' => 14,
17084 
            'block_config' => 'sysgen_blockset:toreg_config',
17085 
            'block_handle' => 57.0009765625,
17086 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
17087 
            'block_type' => 'toreg',
17088 
            'dbl_ovrd' => 0,
17089 
            'explicit_data_type' => 0,
17090 
            'init' => 0,
17091 
            'init_bit_vector' => '0b',
17092 
            'mdl_handle' => 3.0009765625,
17093 
            'model_handle' => 3.0009765625,
17094 
            'n_bits' => 16,
17095 
            'ownership' => 1,
17096 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17097 
            'shared_memory_name' => 'register11tv',
17098 
          },
17099 
          'needs_vhdl_wrapper' => 0,
17100 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
17101 
        },
17102 
        'entityName' => 'x_x18',
17103 
        'ports' => {
17104 
          'ce' => {
17105 
            'attributes' => {
17106 
              'domain' => '',
17107 
              'group' => 1,
17108 
              'isCe' => 1,
17109 
              'is_floating_block' => 1,
17110 
              'period' => 1,
17111 
              'type' => 'logic',
17112 
            },
17113 
            'direction' => 'in',
17114 
            'hdlType' => 'std_logic',
17115 
            'width' => 1,
17116 
          },
17117 
          'clk' => {
17118 
            'attributes' => {
17119 
              'domain' => '',
17120 
              'group' => 1,
17121 
              'isClk' => 1,
17122 
              'is_floating_block' => 1,
17123 
              'period' => 1,
17124 
              'type' => 'logic',
17125 
            },
17126 
            'direction' => 'in',
17127 
            'hdlType' => 'std_logic',
17128 
            'width' => 1,
17129 
          },
17130 
          'clr' => {
17131 
            'attributes' => {
17132 
              'domain' => '',
17133 
              'group' => 1,
17134 
              'isClr' => 1,
17135 
              'is_floating_block' => 1,
17136 
              'period' => 1,
17137 
              'type' => 'logic',
17138 
              'valid_bit_used' => 0,
17139 
            },
17140 
            'direction' => 'in',
17141 
            'hdlType' => 'std_logic',
17142 
            'width' => 1,
17143 
          },
17144 
          'data_in' => {
17145 
            'attributes' => {
17146 
              'bin_pt' => 0,
17147 
              'is_floating_block' => 1,
17148 
              'must_be_hdl_vector' => 1,
17149 
              'period' => 1,
17150 
              'port_id' => 0,
17151 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
17152 
              'type' => 'Bool',
17153 
            },
17154 
            'direction' => 'in',
17155 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17156 
            'width' => 1,
17157 
          },
17158 
          'dout' => {
17159 
            'attributes' => {
17160 
              'bin_pt' => 0,
17161 
              'is_floating_block' => 1,
17162 
              'must_be_hdl_vector' => 1,
17163 
              'period' => 1,
17164 
              'port_id' => 0,
17165 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
17166 
              'type' => 'Bool',
17167 
            },
17168 
            'direction' => 'out',
17169 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17170 
            'width' => 1,
17171 
          },
17172 
          'en' => {
17173 
            'attributes' => {
17174 
              'bin_pt' => 0,
17175 
              'is_floating_block' => 1,
17176 
              'must_be_hdl_vector' => 1,
17177 
              'period' => 1,
17178 
              'port_id' => 1,
17179 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
17180 
              'type' => 'Bool',
17181 
            },
17182 
            'direction' => 'in',
17183 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17184 
            'width' => 1,
17185 
          },
17186 
        },
17187 
      },
17188 
      'entityName' => 'x_x18',
17189 
    },
17190 
    'to_register28' => {
17191 
      'connections' => {
17192 
        'ce' => 'sysgen_dut.to_register28_ce',
17193 
        'clk' => 'sysgen_dut.to_register28_clk',
17194 
        'clr' => 'sysgen_dut.to_register28_clr',
17195 
        'data_in' => 'sysgen_dut.to_register28_data_in',
17196 
        'dout' => 'to_register28.dout',
17197 
        'en' => 'sysgen_dut.to_register28_en',
17198 
      },
17199 
      'entity' => {
17200 
        'attributes' => {
17201 
          'entityAlreadyNetlisted' => 1,
17202 
          'generics' => [
17203 
          ],
17204 
          'is_floating_block' => 1,
17205 
          'mask' => {
17206 
            'Block_Handle' => 58.0009765625,
17207 
            'Block_handle' => 58.0009765625,
17208 
            'MDL_Handle' => 3.0009765625,
17209 
            'MDL_handle' => 3.0009765625,
17210 
            'arith_type' => 1,
17211 
            'bin_pt' => 14,
17212 
            'block_config' => 'sysgen_blockset:toreg_config',
17213 
            'block_handle' => 58.0009765625,
17214 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
17215 
            'block_type' => 'toreg',
17216 
            'dbl_ovrd' => 0,
17217 
            'explicit_data_type' => 0,
17218 
            'init' => 0,
17219 
            'init_bit_vector' => '00000000000000000000000000000000b',
17220 
            'mdl_handle' => 3.0009765625,
17221 
            'model_handle' => 3.0009765625,
17222 
            'n_bits' => 16,
17223 
            'ownership' => 1,
17224 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17225 
            'shared_memory_name' => 'register11td',
17226 
          },
17227 
          'needs_vhdl_wrapper' => 0,
17228 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
17229 
        },
17230 
        'entityName' => 'x_x19',
17231 
        'ports' => {
17232 
          'ce' => {
17233 
            'attributes' => {
17234 
              'domain' => '',
17235 
              'group' => 1,
17236 
              'isCe' => 1,
17237 
              'is_floating_block' => 1,
17238 
              'period' => 1,
17239 
              'type' => 'logic',
17240 
            },
17241 
            'direction' => 'in',
17242 
            'hdlType' => 'std_logic',
17243 
            'width' => 1,
17244 
          },
17245 
          'clk' => {
17246 
            'attributes' => {
17247 
              'domain' => '',
17248 
              'group' => 1,
17249 
              'isClk' => 1,
17250 
              'is_floating_block' => 1,
17251 
              'period' => 1,
17252 
              'type' => 'logic',
17253 
            },
17254 
            'direction' => 'in',
17255 
            'hdlType' => 'std_logic',
17256 
            'width' => 1,
17257 
          },
17258 
          'clr' => {
17259 
            'attributes' => {
17260 
              'domain' => '',
17261 
              'group' => 1,
17262 
              'isClr' => 1,
17263 
              'is_floating_block' => 1,
17264 
              'period' => 1,
17265 
              'type' => 'logic',
17266 
              'valid_bit_used' => 0,
17267 
            },
17268 
            'direction' => 'in',
17269 
            'hdlType' => 'std_logic',
17270 
            'width' => 1,
17271 
          },
17272 
          'data_in' => {
17273 
            'attributes' => {
17274 
              'bin_pt' => 0,
17275 
              'is_floating_block' => 1,
17276 
              'must_be_hdl_vector' => 1,
17277 
              'period' => 1,
17278 
              'port_id' => 0,
17279 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
17280 
              'type' => 'UFix_32_0',
17281 
            },
17282 
            'direction' => 'in',
17283 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17284 
            'width' => 32,
17285 
          },
17286 
          'dout' => {
17287 
            'attributes' => {
17288 
              'bin_pt' => 0,
17289 
              'is_floating_block' => 1,
17290 
              'must_be_hdl_vector' => 1,
17291 
              'period' => 1,
17292 
              'port_id' => 0,
17293 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
17294 
              'type' => 'UFix_32_0',
17295 
            },
17296 
            'direction' => 'out',
17297 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17298 
            'width' => 32,
17299 
          },
17300 
          'en' => {
17301 
            'attributes' => {
17302 
              'bin_pt' => 0,
17303 
              'is_floating_block' => 1,
17304 
              'must_be_hdl_vector' => 1,
17305 
              'period' => 1,
17306 
              'port_id' => 1,
17307 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
17308 
              'type' => 'Bool',
17309 
            },
17310 
            'direction' => 'in',
17311 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17312 
            'width' => 1,
17313 
          },
17314 
        },
17315 
      },
17316 
      'entityName' => 'x_x19',
17317 
    },
17318 
    'to_register29' => {
17319 
      'connections' => {
17320 
        'ce' => 'sysgen_dut.to_register29_ce',
17321 
        'clk' => 'sysgen_dut.to_register29_clk',
17322 
        'clr' => 'sysgen_dut.to_register29_clr',
17323 
        'data_in' => 'sysgen_dut.to_register29_data_in',
17324 
        'dout' => 'to_register29.dout',
17325 
        'en' => 'sysgen_dut.to_register29_en',
17326 
      },
17327 
      'entity' => {
17328 
        'attributes' => {
17329 
          'entityAlreadyNetlisted' => 1,
17330 
          'generics' => [
17331 
          ],
17332 
          'is_floating_block' => 1,
17333 
          'mask' => {
17334 
            'Block_Handle' => 59.0009765625,
17335 
            'Block_handle' => 59.0009765625,
17336 
            'MDL_Handle' => 3.0009765625,
17337 
            'MDL_handle' => 3.0009765625,
17338 
            'arith_type' => 1,
17339 
            'bin_pt' => 14,
17340 
            'block_config' => 'sysgen_blockset:toreg_config',
17341 
            'block_handle' => 59.0009765625,
17342 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
17343 
            'block_type' => 'toreg',
17344 
            'dbl_ovrd' => 0,
17345 
            'explicit_data_type' => 0,
17346 
            'init' => 0,
17347 
            'init_bit_vector' => '0b',
17348 
            'mdl_handle' => 3.0009765625,
17349 
            'model_handle' => 3.0009765625,
17350 
            'n_bits' => 16,
17351 
            'ownership' => 1,
17352 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17353 
            'shared_memory_name' => 'register12tv',
17354 
          },
17355 
          'needs_vhdl_wrapper' => 0,
17356 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
17357 
        },
17358 
        'entityName' => 'x_x20',
17359 
        'ports' => {
17360 
          'ce' => {
17361 
            'attributes' => {
17362 
              'domain' => '',
17363 
              'group' => 1,
17364 
              'isCe' => 1,
17365 
              'is_floating_block' => 1,
17366 
              'period' => 1,
17367 
              'type' => 'logic',
17368 
            },
17369 
            'direction' => 'in',
17370 
            'hdlType' => 'std_logic',
17371 
            'width' => 1,
17372 
          },
17373 
          'clk' => {
17374 
            'attributes' => {
17375 
              'domain' => '',
17376 
              'group' => 1,
17377 
              'isClk' => 1,
17378 
              'is_floating_block' => 1,
17379 
              'period' => 1,
17380 
              'type' => 'logic',
17381 
            },
17382 
            'direction' => 'in',
17383 
            'hdlType' => 'std_logic',
17384 
            'width' => 1,
17385 
          },
17386 
          'clr' => {
17387 
            'attributes' => {
17388 
              'domain' => '',
17389 
              'group' => 1,
17390 
              'isClr' => 1,
17391 
              'is_floating_block' => 1,
17392 
              'period' => 1,
17393 
              'type' => 'logic',
17394 
              'valid_bit_used' => 0,
17395 
            },
17396 
            'direction' => 'in',
17397 
            'hdlType' => 'std_logic',
17398 
            'width' => 1,
17399 
          },
17400 
          'data_in' => {
17401 
            'attributes' => {
17402 
              'bin_pt' => 0,
17403 
              'is_floating_block' => 1,
17404 
              'must_be_hdl_vector' => 1,
17405 
              'period' => 1,
17406 
              'port_id' => 0,
17407 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
17408 
              'type' => 'Bool',
17409 
            },
17410 
            'direction' => 'in',
17411 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17412 
            'width' => 1,
17413 
          },
17414 
          'dout' => {
17415 
            'attributes' => {
17416 
              'bin_pt' => 0,
17417 
              'is_floating_block' => 1,
17418 
              'must_be_hdl_vector' => 1,
17419 
              'period' => 1,
17420 
              'port_id' => 0,
17421 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
17422 
              'type' => 'Bool',
17423 
            },
17424 
            'direction' => 'out',
17425 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17426 
            'width' => 1,
17427 
          },
17428 
          'en' => {
17429 
            'attributes' => {
17430 
              'bin_pt' => 0,
17431 
              'is_floating_block' => 1,
17432 
              'must_be_hdl_vector' => 1,
17433 
              'period' => 1,
17434 
              'port_id' => 1,
17435 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
17436 
              'type' => 'Bool',
17437 
            },
17438 
            'direction' => 'in',
17439 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17440 
            'width' => 1,
17441 
          },
17442 
        },
17443 
      },
17444 
      'entityName' => 'x_x20',
17445 
    },
17446 
    'to_register3' => {
17447 
      'connections' => {
17448 
        'ce' => 'sysgen_dut.to_register3_ce',
17449 
        'clk' => 'sysgen_dut.to_register3_clk',
17450 
        'clr' => 'sysgen_dut.to_register3_clr',
17451 
        'data_in' => 'sysgen_dut.to_register3_data_in',
17452 
        'dout' => 'to_register3.dout',
17453 
        'en' => 'sysgen_dut.to_register3_en',
17454 
      },
17455 
      'entity' => {
17456 
        'attributes' => {
17457 
          'entityAlreadyNetlisted' => 1,
17458 
          'generics' => [
17459 
          ],
17460 
          'is_floating_block' => 1,
17461 
          'mask' => {
17462 
            'Block_Handle' => 60.0009765625,
17463 
            'Block_handle' => 60.0009765625,
17464 
            'MDL_Handle' => 3.0009765625,
17465 
            'MDL_handle' => 3.0009765625,
17466 
            'arith_type' => 1,
17467 
            'bin_pt' => 14,
17468 
            'block_config' => 'sysgen_blockset:toreg_config',
17469 
            'block_handle' => 60.0009765625,
17470 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17471 
            'block_type' => 'toreg',
17472 
            'dbl_ovrd' => 0,
17473 
            'explicit_data_type' => 0,
17474 
            'init' => 0,
17475 
            'init_bit_vector' => '0b',
17476 
            'mdl_handle' => 3.0009765625,
17477 
            'model_handle' => 3.0009765625,
17478 
            'n_bits' => 16,
17479 
            'ownership' => 1,
17480 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17481 
            'shared_memory_name' => 'register01tv',
17482 
          },
17483 
          'needs_vhdl_wrapper' => 0,
17484 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17485 
        },
17486 
        'entityName' => 'x_x21',
17487 
        'ports' => {
17488 
          'ce' => {
17489 
            'attributes' => {
17490 
              'domain' => '',
17491 
              'group' => 1,
17492 
              'isCe' => 1,
17493 
              'is_floating_block' => 1,
17494 
              'period' => 1,
17495 
              'type' => 'logic',
17496 
            },
17497 
            'direction' => 'in',
17498 
            'hdlType' => 'std_logic',
17499 
            'width' => 1,
17500 
          },
17501 
          'clk' => {
17502 
            'attributes' => {
17503 
              'domain' => '',
17504 
              'group' => 1,
17505 
              'isClk' => 1,
17506 
              'is_floating_block' => 1,
17507 
              'period' => 1,
17508 
              'type' => 'logic',
17509 
            },
17510 
            'direction' => 'in',
17511 
            'hdlType' => 'std_logic',
17512 
            'width' => 1,
17513 
          },
17514 
          'clr' => {
17515 
            'attributes' => {
17516 
              'domain' => '',
17517 
              'group' => 1,
17518 
              'isClr' => 1,
17519 
              'is_floating_block' => 1,
17520 
              'period' => 1,
17521 
              'type' => 'logic',
17522 
              'valid_bit_used' => 0,
17523 
            },
17524 
            'direction' => 'in',
17525 
            'hdlType' => 'std_logic',
17526 
            'width' => 1,
17527 
          },
17528 
          'data_in' => {
17529 
            'attributes' => {
17530 
              'bin_pt' => 0,
17531 
              'is_floating_block' => 1,
17532 
              'must_be_hdl_vector' => 1,
17533 
              'period' => 1,
17534 
              'port_id' => 0,
17535 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
17536 
              'type' => 'Bool',
17537 
            },
17538 
            'direction' => 'in',
17539 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17540 
            'width' => 1,
17541 
          },
17542 
          'dout' => {
17543 
            'attributes' => {
17544 
              'bin_pt' => 0,
17545 
              'is_floating_block' => 1,
17546 
              'must_be_hdl_vector' => 1,
17547 
              'period' => 1,
17548 
              'port_id' => 0,
17549 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
17550 
              'type' => 'Bool',
17551 
            },
17552 
            'direction' => 'out',
17553 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17554 
            'width' => 1,
17555 
          },
17556 
          'en' => {
17557 
            'attributes' => {
17558 
              'bin_pt' => 0,
17559 
              'is_floating_block' => 1,
17560 
              'must_be_hdl_vector' => 1,
17561 
              'period' => 1,
17562 
              'port_id' => 1,
17563 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
17564 
              'type' => 'Bool',
17565 
            },
17566 
            'direction' => 'in',
17567 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17568 
            'width' => 1,
17569 
          },
17570 
        },
17571 
      },
17572 
      'entityName' => 'x_x21',
17573 
    },
17574 
    'to_register30' => {
17575 
      'connections' => {
17576 
        'ce' => 'sysgen_dut.to_register30_ce',
17577 
        'clk' => 'sysgen_dut.to_register30_clk',
17578 
        'clr' => 'sysgen_dut.to_register30_clr',
17579 
        'data_in' => 'sysgen_dut.to_register30_data_in',
17580 
        'dout' => 'to_register30.dout',
17581 
        'en' => 'sysgen_dut.to_register30_en',
17582 
      },
17583 
      'entity' => {
17584 
        'attributes' => {
17585 
          'entityAlreadyNetlisted' => 1,
17586 
          'generics' => [
17587 
          ],
17588 
          'is_floating_block' => 1,
17589 
          'mask' => {
17590 
            'Block_Handle' => 61.0009765625,
17591 
            'Block_handle' => 61.0009765625,
17592 
            'MDL_Handle' => 3.0009765625,
17593 
            'MDL_handle' => 3.0009765625,
17594 
            'arith_type' => 1,
17595 
            'bin_pt' => 14,
17596 
            'block_config' => 'sysgen_blockset:toreg_config',
17597 
            'block_handle' => 61.0009765625,
17598 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17599 
            'block_type' => 'toreg',
17600 
            'dbl_ovrd' => 0,
17601 
            'explicit_data_type' => 0,
17602 
            'init' => 0,
17603 
            'init_bit_vector' => '00000000000000000000000000000000b',
17604 
            'mdl_handle' => 3.0009765625,
17605 
            'model_handle' => 3.0009765625,
17606 
            'n_bits' => 16,
17607 
            'ownership' => 1,
17608 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17609 
            'shared_memory_name' => 'register12td',
17610 
          },
17611 
          'needs_vhdl_wrapper' => 0,
17612 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17613 
        },
17614 
        'entityName' => 'x_x22',
17615 
        'ports' => {
17616 
          'ce' => {
17617 
            'attributes' => {
17618 
              'domain' => '',
17619 
              'group' => 1,
17620 
              'isCe' => 1,
17621 
              'is_floating_block' => 1,
17622 
              'period' => 1,
17623 
              'type' => 'logic',
17624 
            },
17625 
            'direction' => 'in',
17626 
            'hdlType' => 'std_logic',
17627 
            'width' => 1,
17628 
          },
17629 
          'clk' => {
17630 
            'attributes' => {
17631 
              'domain' => '',
17632 
              'group' => 1,
17633 
              'isClk' => 1,
17634 
              'is_floating_block' => 1,
17635 
              'period' => 1,
17636 
              'type' => 'logic',
17637 
            },
17638 
            'direction' => 'in',
17639 
            'hdlType' => 'std_logic',
17640 
            'width' => 1,
17641 
          },
17642 
          'clr' => {
17643 
            'attributes' => {
17644 
              'domain' => '',
17645 
              'group' => 1,
17646 
              'isClr' => 1,
17647 
              'is_floating_block' => 1,
17648 
              'period' => 1,
17649 
              'type' => 'logic',
17650 
              'valid_bit_used' => 0,
17651 
            },
17652 
            'direction' => 'in',
17653 
            'hdlType' => 'std_logic',
17654 
            'width' => 1,
17655 
          },
17656 
          'data_in' => {
17657 
            'attributes' => {
17658 
              'bin_pt' => 0,
17659 
              'is_floating_block' => 1,
17660 
              'must_be_hdl_vector' => 1,
17661 
              'period' => 1,
17662 
              'port_id' => 0,
17663 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
17664 
              'type' => 'UFix_32_0',
17665 
            },
17666 
            'direction' => 'in',
17667 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17668 
            'width' => 32,
17669 
          },
17670 
          'dout' => {
17671 
            'attributes' => {
17672 
              'bin_pt' => 0,
17673 
              'is_floating_block' => 1,
17674 
              'must_be_hdl_vector' => 1,
17675 
              'period' => 1,
17676 
              'port_id' => 0,
17677 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
17678 
              'type' => 'UFix_32_0',
17679 
            },
17680 
            'direction' => 'out',
17681 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17682 
            'width' => 32,
17683 
          },
17684 
          'en' => {
17685 
            'attributes' => {
17686 
              'bin_pt' => 0,
17687 
              'is_floating_block' => 1,
17688 
              'must_be_hdl_vector' => 1,
17689 
              'period' => 1,
17690 
              'port_id' => 1,
17691 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
17692 
              'type' => 'Bool',
17693 
            },
17694 
            'direction' => 'in',
17695 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17696 
            'width' => 1,
17697 
          },
17698 
        },
17699 
      },
17700 
      'entityName' => 'x_x22',
17701 
    },
17702 
    'to_register31' => {
17703 
      'connections' => {
17704 
        'ce' => 'sysgen_dut.to_register31_ce',
17705 
        'clk' => 'sysgen_dut.to_register31_clk',
17706 
        'clr' => 'sysgen_dut.to_register31_clr',
17707 
        'data_in' => 'sysgen_dut.to_register31_data_in',
17708 
        'dout' => 'to_register31.dout',
17709 
        'en' => 'sysgen_dut.to_register31_en',
17710 
      },
17711 
      'entity' => {
17712 
        'attributes' => {
17713 
          'entityAlreadyNetlisted' => 1,
17714 
          'generics' => [
17715 
          ],
17716 
          'is_floating_block' => 1,
17717 
          'mask' => {
17718 
            'Block_Handle' => 62.0009765625,
17719 
            'Block_handle' => 62.0009765625,
17720 
            'MDL_Handle' => 3.0009765625,
17721 
            'MDL_handle' => 3.0009765625,
17722 
            'arith_type' => 1,
17723 
            'bin_pt' => 14,
17724 
            'block_config' => 'sysgen_blockset:toreg_config',
17725 
            'block_handle' => 62.0009765625,
17726 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17727 
            'block_type' => 'toreg',
17728 
            'dbl_ovrd' => 0,
17729 
            'explicit_data_type' => 0,
17730 
            'init' => 0,
17731 
            'init_bit_vector' => '0b',
17732 
            'mdl_handle' => 3.0009765625,
17733 
            'model_handle' => 3.0009765625,
17734 
            'n_bits' => 16,
17735 
            'ownership' => 1,
17736 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17737 
            'shared_memory_name' => 'register13tv',
17738 
          },
17739 
          'needs_vhdl_wrapper' => 0,
17740 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17741 
        },
17742 
        'entityName' => 'x_x23',
17743 
        'ports' => {
17744 
          'ce' => {
17745 
            'attributes' => {
17746 
              'domain' => '',
17747 
              'group' => 1,
17748 
              'isCe' => 1,
17749 
              'is_floating_block' => 1,
17750 
              'period' => 1,
17751 
              'type' => 'logic',
17752 
            },
17753 
            'direction' => 'in',
17754 
            'hdlType' => 'std_logic',
17755 
            'width' => 1,
17756 
          },
17757 
          'clk' => {
17758 
            'attributes' => {
17759 
              'domain' => '',
17760 
              'group' => 1,
17761 
              'isClk' => 1,
17762 
              'is_floating_block' => 1,
17763 
              'period' => 1,
17764 
              'type' => 'logic',
17765 
            },
17766 
            'direction' => 'in',
17767 
            'hdlType' => 'std_logic',
17768 
            'width' => 1,
17769 
          },
17770 
          'clr' => {
17771 
            'attributes' => {
17772 
              'domain' => '',
17773 
              'group' => 1,
17774 
              'isClr' => 1,
17775 
              'is_floating_block' => 1,
17776 
              'period' => 1,
17777 
              'type' => 'logic',
17778 
              'valid_bit_used' => 0,
17779 
            },
17780 
            'direction' => 'in',
17781 
            'hdlType' => 'std_logic',
17782 
            'width' => 1,
17783 
          },
17784 
          'data_in' => {
17785 
            'attributes' => {
17786 
              'bin_pt' => 0,
17787 
              'is_floating_block' => 1,
17788 
              'must_be_hdl_vector' => 1,
17789 
              'period' => 1,
17790 
              'port_id' => 0,
17791 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
17792 
              'type' => 'Bool',
17793 
            },
17794 
            'direction' => 'in',
17795 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17796 
            'width' => 1,
17797 
          },
17798 
          'dout' => {
17799 
            'attributes' => {
17800 
              'bin_pt' => 0,
17801 
              'is_floating_block' => 1,
17802 
              'must_be_hdl_vector' => 1,
17803 
              'period' => 1,
17804 
              'port_id' => 0,
17805 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
17806 
              'type' => 'Bool',
17807 
            },
17808 
            'direction' => 'out',
17809 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17810 
            'width' => 1,
17811 
          },
17812 
          'en' => {
17813 
            'attributes' => {
17814 
              'bin_pt' => 0,
17815 
              'is_floating_block' => 1,
17816 
              'must_be_hdl_vector' => 1,
17817 
              'period' => 1,
17818 
              'port_id' => 1,
17819 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
17820 
              'type' => 'Bool',
17821 
            },
17822 
            'direction' => 'in',
17823 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17824 
            'width' => 1,
17825 
          },
17826 
        },
17827 
      },
17828 
      'entityName' => 'x_x23',
17829 
    },
17830 
    'to_register32' => {
17831 
      'connections' => {
17832 
        'ce' => 'sysgen_dut.to_register32_ce',
17833 
        'clk' => 'sysgen_dut.to_register32_clk',
17834 
        'clr' => 'sysgen_dut.to_register32_clr',
17835 
        'data_in' => 'sysgen_dut.to_register32_data_in',
17836 
        'dout' => 'to_register32.dout',
17837 
        'en' => 'sysgen_dut.to_register32_en',
17838 
      },
17839 
      'entity' => {
17840 
        'attributes' => {
17841 
          'entityAlreadyNetlisted' => 1,
17842 
          'generics' => [
17843 
          ],
17844 
          'is_floating_block' => 1,
17845 
          'mask' => {
17846 
            'Block_Handle' => 63.0009765625,
17847 
            'Block_handle' => 63.0009765625,
17848 
            'MDL_Handle' => 3.0009765625,
17849 
            'MDL_handle' => 3.0009765625,
17850 
            'arith_type' => 1,
17851 
            'bin_pt' => 14,
17852 
            'block_config' => 'sysgen_blockset:toreg_config',
17853 
            'block_handle' => 63.0009765625,
17854 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17855 
            'block_type' => 'toreg',
17856 
            'dbl_ovrd' => 0,
17857 
            'explicit_data_type' => 0,
17858 
            'init' => 0,
17859 
            'init_bit_vector' => '00000000000000000000000000000000b',
17860 
            'mdl_handle' => 3.0009765625,
17861 
            'model_handle' => 3.0009765625,
17862 
            'n_bits' => 16,
17863 
            'ownership' => 1,
17864 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17865 
            'shared_memory_name' => 'register13td',
17866 
          },
17867 
          'needs_vhdl_wrapper' => 0,
17868 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17869 
        },
17870 
        'entityName' => 'x_x24',
17871 
        'ports' => {
17872 
          'ce' => {
17873 
            'attributes' => {
17874 
              'domain' => '',
17875 
              'group' => 1,
17876 
              'isCe' => 1,
17877 
              'is_floating_block' => 1,
17878 
              'period' => 1,
17879 
              'type' => 'logic',
17880 
            },
17881 
            'direction' => 'in',
17882 
            'hdlType' => 'std_logic',
17883 
            'width' => 1,
17884 
          },
17885 
          'clk' => {
17886 
            'attributes' => {
17887 
              'domain' => '',
17888 
              'group' => 1,
17889 
              'isClk' => 1,
17890 
              'is_floating_block' => 1,
17891 
              'period' => 1,
17892 
              'type' => 'logic',
17893 
            },
17894 
            'direction' => 'in',
17895 
            'hdlType' => 'std_logic',
17896 
            'width' => 1,
17897 
          },
17898 
          'clr' => {
17899 
            'attributes' => {
17900 
              'domain' => '',
17901 
              'group' => 1,
17902 
              'isClr' => 1,
17903 
              'is_floating_block' => 1,
17904 
              'period' => 1,
17905 
              'type' => 'logic',
17906 
              'valid_bit_used' => 0,
17907 
            },
17908 
            'direction' => 'in',
17909 
            'hdlType' => 'std_logic',
17910 
            'width' => 1,
17911 
          },
17912 
          'data_in' => {
17913 
            'attributes' => {
17914 
              'bin_pt' => 0,
17915 
              'is_floating_block' => 1,
17916 
              'must_be_hdl_vector' => 1,
17917 
              'period' => 1,
17918 
              'port_id' => 0,
17919 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
17920 
              'type' => 'UFix_32_0',
17921 
            },
17922 
            'direction' => 'in',
17923 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17924 
            'width' => 32,
17925 
          },
17926 
          'dout' => {
17927 
            'attributes' => {
17928 
              'bin_pt' => 0,
17929 
              'is_floating_block' => 1,
17930 
              'must_be_hdl_vector' => 1,
17931 
              'period' => 1,
17932 
              'port_id' => 0,
17933 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
17934 
              'type' => 'UFix_32_0',
17935 
            },
17936 
            'direction' => 'out',
17937 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17938 
            'width' => 32,
17939 
          },
17940 
          'en' => {
17941 
            'attributes' => {
17942 
              'bin_pt' => 0,
17943 
              'is_floating_block' => 1,
17944 
              'must_be_hdl_vector' => 1,
17945 
              'period' => 1,
17946 
              'port_id' => 1,
17947 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
17948 
              'type' => 'Bool',
17949 
            },
17950 
            'direction' => 'in',
17951 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17952 
            'width' => 1,
17953 
          },
17954 
        },
17955 
      },
17956 
      'entityName' => 'x_x24',
17957 
    },
17958 
    'to_register33' => {
17959 
      'connections' => {
17960 
        'ce' => 'sysgen_dut.to_register33_ce',
17961 
        'clk' => 'sysgen_dut.to_register33_clk',
17962 
        'clr' => 'sysgen_dut.to_register33_clr',
17963 
        'data_in' => 'sysgen_dut.to_register33_data_in',
17964 
        'dout' => 'to_register33.dout',
17965 
        'en' => 'sysgen_dut.to_register33_en',
17966 
      },
17967 
      'entity' => {
17968 
        'attributes' => {
17969 
          'entityAlreadyNetlisted' => 1,
17970 
          'generics' => [
17971 
          ],
17972 
          'is_floating_block' => 1,
17973 
          'mask' => {
17974 
            'Block_Handle' => 64.0009765625,
17975 
            'Block_handle' => 64.0009765625,
17976 
            'MDL_Handle' => 3.0009765625,
17977 
            'MDL_handle' => 3.0009765625,
17978 
            'arith_type' => 1,
17979 
            'bin_pt' => 14,
17980 
            'block_config' => 'sysgen_blockset:toreg_config',
17981 
            'block_handle' => 64.0009765625,
17982 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
17983 
            'block_type' => 'toreg',
17984 
            'dbl_ovrd' => 0,
17985 
            'explicit_data_type' => 0,
17986 
            'init' => 0,
17987 
            'init_bit_vector' => '0b',
17988 
            'mdl_handle' => 3.0009765625,
17989 
            'model_handle' => 3.0009765625,
17990 
            'n_bits' => 16,
17991 
            'ownership' => 1,
17992 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17993 
            'shared_memory_name' => 'register14tv',
17994 
          },
17995 
          'needs_vhdl_wrapper' => 0,
17996 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
17997 
        },
17998 
        'entityName' => 'x_x25',
17999 
        'ports' => {
18000 
          'ce' => {
18001 
            'attributes' => {
18002 
              'domain' => '',
18003 
              'group' => 1,
18004 
              'isCe' => 1,
18005 
              'is_floating_block' => 1,
18006 
              'period' => 1,
18007 
              'type' => 'logic',
18008 
            },
18009 
            'direction' => 'in',
18010 
            'hdlType' => 'std_logic',
18011 
            'width' => 1,
18012 
          },
18013 
          'clk' => {
18014 
            'attributes' => {
18015 
              'domain' => '',
18016 
              'group' => 1,
18017 
              'isClk' => 1,
18018 
              'is_floating_block' => 1,
18019 
              'period' => 1,
18020 
              'type' => 'logic',
18021 
            },
18022 
            'direction' => 'in',
18023 
            'hdlType' => 'std_logic',
18024 
            'width' => 1,
18025 
          },
18026 
          'clr' => {
18027 
            'attributes' => {
18028 
              'domain' => '',
18029 
              'group' => 1,
18030 
              'isClr' => 1,
18031 
              'is_floating_block' => 1,
18032 
              'period' => 1,
18033 
              'type' => 'logic',
18034 
              'valid_bit_used' => 0,
18035 
            },
18036 
            'direction' => 'in',
18037 
            'hdlType' => 'std_logic',
18038 
            'width' => 1,
18039 
          },
18040 
          'data_in' => {
18041 
            'attributes' => {
18042 
              'bin_pt' => 0,
18043 
              'is_floating_block' => 1,
18044 
              'must_be_hdl_vector' => 1,
18045 
              'period' => 1,
18046 
              'port_id' => 0,
18047 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
18048 
              'type' => 'Bool',
18049 
            },
18050 
            'direction' => 'in',
18051 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18052 
            'width' => 1,
18053 
          },
18054 
          'dout' => {
18055 
            'attributes' => {
18056 
              'bin_pt' => 0,
18057 
              'is_floating_block' => 1,
18058 
              'must_be_hdl_vector' => 1,
18059 
              'period' => 1,
18060 
              'port_id' => 0,
18061 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
18062 
              'type' => 'Bool',
18063 
            },
18064 
            'direction' => 'out',
18065 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18066 
            'width' => 1,
18067 
          },
18068 
          'en' => {
18069 
            'attributes' => {
18070 
              'bin_pt' => 0,
18071 
              'is_floating_block' => 1,
18072 
              'must_be_hdl_vector' => 1,
18073 
              'period' => 1,
18074 
              'port_id' => 1,
18075 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
18076 
              'type' => 'Bool',
18077 
            },
18078 
            'direction' => 'in',
18079 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18080 
            'width' => 1,
18081 
          },
18082 
        },
18083 
      },
18084 
      'entityName' => 'x_x25',
18085 
    },
18086 
    'to_register34' => {
18087 
      'connections' => {
18088 
        'ce' => 'sysgen_dut.to_register34_ce',
18089 
        'clk' => 'sysgen_dut.to_register34_clk',
18090 
        'clr' => 'sysgen_dut.to_register34_clr',
18091 
        'data_in' => 'sysgen_dut.to_register34_data_in',
18092 
        'dout' => 'to_register34.dout',
18093 
        'en' => 'sysgen_dut.to_register34_en',
18094 
      },
18095 
      'entity' => {
18096 
        'attributes' => {
18097 
          'entityAlreadyNetlisted' => 1,
18098 
          'generics' => [
18099 
          ],
18100 
          'is_floating_block' => 1,
18101 
          'mask' => {
18102 
            'Block_Handle' => 65.0009765625,
18103 
            'Block_handle' => 65.0009765625,
18104 
            'MDL_Handle' => 3.0009765625,
18105 
            'MDL_handle' => 3.0009765625,
18106 
            'arith_type' => 1,
18107 
            'bin_pt' => 14,
18108 
            'block_config' => 'sysgen_blockset:toreg_config',
18109 
            'block_handle' => 65.0009765625,
18110 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
18111 
            'block_type' => 'toreg',
18112 
            'dbl_ovrd' => 0,
18113 
            'explicit_data_type' => 0,
18114 
            'init' => 0,
18115 
            'init_bit_vector' => '00000000000000000000000000000000b',
18116 
            'mdl_handle' => 3.0009765625,
18117 
            'model_handle' => 3.0009765625,
18118 
            'n_bits' => 16,
18119 
            'ownership' => 1,
18120 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18121 
            'shared_memory_name' => 'register14td',
18122 
          },
18123 
          'needs_vhdl_wrapper' => 0,
18124 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
18125 
        },
18126 
        'entityName' => 'x_x26',
18127 
        'ports' => {
18128 
          'ce' => {
18129 
            'attributes' => {
18130 
              'domain' => '',
18131 
              'group' => 1,
18132 
              'isCe' => 1,
18133 
              'is_floating_block' => 1,
18134 
              'period' => 1,
18135 
              'type' => 'logic',
18136 
            },
18137 
            'direction' => 'in',
18138 
            'hdlType' => 'std_logic',
18139 
            'width' => 1,
18140 
          },
18141 
          'clk' => {
18142 
            'attributes' => {
18143 
              'domain' => '',
18144 
              'group' => 1,
18145 
              'isClk' => 1,
18146 
              'is_floating_block' => 1,
18147 
              'period' => 1,
18148 
              'type' => 'logic',
18149 
            },
18150 
            'direction' => 'in',
18151 
            'hdlType' => 'std_logic',
18152 
            'width' => 1,
18153 
          },
18154 
          'clr' => {
18155 
            'attributes' => {
18156 
              'domain' => '',
18157 
              'group' => 1,
18158 
              'isClr' => 1,
18159 
              'is_floating_block' => 1,
18160 
              'period' => 1,
18161 
              'type' => 'logic',
18162 
              'valid_bit_used' => 0,
18163 
            },
18164 
            'direction' => 'in',
18165 
            'hdlType' => 'std_logic',
18166 
            'width' => 1,
18167 
          },
18168 
          'data_in' => {
18169 
            'attributes' => {
18170 
              'bin_pt' => 0,
18171 
              'is_floating_block' => 1,
18172 
              'must_be_hdl_vector' => 1,
18173 
              'period' => 1,
18174 
              'port_id' => 0,
18175 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
18176 
              'type' => 'UFix_32_0',
18177 
            },
18178 
            'direction' => 'in',
18179 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18180 
            'width' => 32,
18181 
          },
18182 
          'dout' => {
18183 
            'attributes' => {
18184 
              'bin_pt' => 0,
18185 
              'is_floating_block' => 1,
18186 
              'must_be_hdl_vector' => 1,
18187 
              'period' => 1,
18188 
              'port_id' => 0,
18189 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
18190 
              'type' => 'UFix_32_0',
18191 
            },
18192 
            'direction' => 'out',
18193 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18194 
            'width' => 32,
18195 
          },
18196 
          'en' => {
18197 
            'attributes' => {
18198 
              'bin_pt' => 0,
18199 
              'is_floating_block' => 1,
18200 
              'must_be_hdl_vector' => 1,
18201 
              'period' => 1,
18202 
              'port_id' => 1,
18203 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
18204 
              'type' => 'Bool',
18205 
            },
18206 
            'direction' => 'in',
18207 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18208 
            'width' => 1,
18209 
          },
18210 
        },
18211 
      },
18212 
      'entityName' => 'x_x26',
18213 
    },
18214 
    'to_register4' => {
18215 
      'connections' => {
18216 
        'ce' => 'sysgen_dut.to_register4_ce',
18217 
        'clk' => 'sysgen_dut.to_register4_clk',
18218 
        'clr' => 'sysgen_dut.to_register4_clr',
18219 
        'data_in' => 'sysgen_dut.to_register4_data_in',
18220 
        'dout' => 'to_register4.dout',
18221 
        'en' => 'sysgen_dut.to_register4_en',
18222 
      },
18223 
      'entity' => {
18224 
        'attributes' => {
18225 
          'entityAlreadyNetlisted' => 1,
18226 
          'generics' => [
18227 
          ],
18228 
          'is_floating_block' => 1,
18229 
          'mask' => {
18230 
            'Block_Handle' => 66.0009765625,
18231 
            'Block_handle' => 66.0009765625,
18232 
            'MDL_Handle' => 3.0009765625,
18233 
            'MDL_handle' => 3.0009765625,
18234 
            'arith_type' => 1,
18235 
            'bin_pt' => 14,
18236 
            'block_config' => 'sysgen_blockset:toreg_config',
18237 
            'block_handle' => 66.0009765625,
18238 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
18239 
            'block_type' => 'toreg',
18240 
            'dbl_ovrd' => 0,
18241 
            'explicit_data_type' => 0,
18242 
            'init' => 0,
18243 
            'init_bit_vector' => '0b',
18244 
            'mdl_handle' => 3.0009765625,
18245 
            'model_handle' => 3.0009765625,
18246 
            'n_bits' => 16,
18247 
            'ownership' => 1,
18248 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18249 
            'shared_memory_name' => 'register02tv',
18250 
          },
18251 
          'needs_vhdl_wrapper' => 0,
18252 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
18253 
        },
18254 
        'entityName' => 'x_x27',
18255 
        'ports' => {
18256 
          'ce' => {
18257 
            'attributes' => {
18258 
              'domain' => '',
18259 
              'group' => 1,
18260 
              'isCe' => 1,
18261 
              'is_floating_block' => 1,
18262 
              'period' => 1,
18263 
              'type' => 'logic',
18264 
            },
18265 
            'direction' => 'in',
18266 
            'hdlType' => 'std_logic',
18267 
            'width' => 1,
18268 
          },
18269 
          'clk' => {
18270 
            'attributes' => {
18271 
              'domain' => '',
18272 
              'group' => 1,
18273 
              'isClk' => 1,
18274 
              'is_floating_block' => 1,
18275 
              'period' => 1,
18276 
              'type' => 'logic',
18277 
            },
18278 
            'direction' => 'in',
18279 
            'hdlType' => 'std_logic',
18280 
            'width' => 1,
18281 
          },
18282 
          'clr' => {
18283 
            'attributes' => {
18284 
              'domain' => '',
18285 
              'group' => 1,
18286 
              'isClr' => 1,
18287 
              'is_floating_block' => 1,
18288 
              'period' => 1,
18289 
              'type' => 'logic',
18290 
              'valid_bit_used' => 0,
18291 
            },
18292 
            'direction' => 'in',
18293 
            'hdlType' => 'std_logic',
18294 
            'width' => 1,
18295 
          },
18296 
          'data_in' => {
18297 
            'attributes' => {
18298 
              'bin_pt' => 0,
18299 
              'is_floating_block' => 1,
18300 
              'must_be_hdl_vector' => 1,
18301 
              'period' => 1,
18302 
              'port_id' => 0,
18303 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
18304 
              'type' => 'Bool',
18305 
            },
18306 
            'direction' => 'in',
18307 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18308 
            'width' => 1,
18309 
          },
18310 
          'dout' => {
18311 
            'attributes' => {
18312 
              'bin_pt' => 0,
18313 
              'is_floating_block' => 1,
18314 
              'must_be_hdl_vector' => 1,
18315 
              'period' => 1,
18316 
              'port_id' => 0,
18317 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
18318 
              'type' => 'Bool',
18319 
            },
18320 
            'direction' => 'out',
18321 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18322 
            'width' => 1,
18323 
          },
18324 
          'en' => {
18325 
            'attributes' => {
18326 
              'bin_pt' => 0,
18327 
              'is_floating_block' => 1,
18328 
              'must_be_hdl_vector' => 1,
18329 
              'period' => 1,
18330 
              'port_id' => 1,
18331 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
18332 
              'type' => 'Bool',
18333 
            },
18334 
            'direction' => 'in',
18335 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18336 
            'width' => 1,
18337 
          },
18338 
        },
18339 
      },
18340 
      'entityName' => 'x_x27',
18341 
    },
18342 
    'to_register5' => {
18343 
      'connections' => {
18344 
        'ce' => 'sysgen_dut.to_register5_ce',
18345 
        'clk' => 'sysgen_dut.to_register5_clk',
18346 
        'clr' => 'sysgen_dut.to_register5_clr',
18347 
        'data_in' => 'sysgen_dut.to_register5_data_in',
18348 
        'dout' => 'to_register5.dout',
18349 
        'en' => 'sysgen_dut.to_register5_en',
18350 
      },
18351 
      'entity' => {
18352 
        'attributes' => {
18353 
          'entityAlreadyNetlisted' => 1,
18354 
          'generics' => [
18355 
          ],
18356 
          'is_floating_block' => 1,
18357 
          'mask' => {
18358 
            'Block_Handle' => 67.0009765625,
18359 
            'Block_handle' => 67.0009765625,
18360 
            'MDL_Handle' => 3.0009765625,
18361 
            'MDL_handle' => 3.0009765625,
18362 
            'arith_type' => 1,
18363 
            'bin_pt' => 14,
18364 
            'block_config' => 'sysgen_blockset:toreg_config',
18365 
            'block_handle' => 67.0009765625,
18366 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
18367 
            'block_type' => 'toreg',
18368 
            'dbl_ovrd' => 0,
18369 
            'explicit_data_type' => 0,
18370 
            'init' => 0,
18371 
            'init_bit_vector' => '00000000000000000000000000000000b',
18372 
            'mdl_handle' => 3.0009765625,
18373 
            'model_handle' => 3.0009765625,
18374 
            'n_bits' => 16,
18375 
            'ownership' => 1,
18376 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18377 
            'shared_memory_name' => 'register02td',
18378 
          },
18379 
          'needs_vhdl_wrapper' => 0,
18380 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
18381 
        },
18382 
        'entityName' => 'x_x28',
18383 
        'ports' => {
18384 
          'ce' => {
18385 
            'attributes' => {
18386 
              'domain' => '',
18387 
              'group' => 1,
18388 
              'isCe' => 1,
18389 
              'is_floating_block' => 1,
18390 
              'period' => 1,
18391 
              'type' => 'logic',
18392 
            },
18393 
            'direction' => 'in',
18394 
            'hdlType' => 'std_logic',
18395 
            'width' => 1,
18396 
          },
18397 
          'clk' => {
18398 
            'attributes' => {
18399 
              'domain' => '',
18400 
              'group' => 1,
18401 
              'isClk' => 1,
18402 
              'is_floating_block' => 1,
18403 
              'period' => 1,
18404 
              'type' => 'logic',
18405 
            },
18406 
            'direction' => 'in',
18407 
            'hdlType' => 'std_logic',
18408 
            'width' => 1,
18409 
          },
18410 
          'clr' => {
18411 
            'attributes' => {
18412 
              'domain' => '',
18413 
              'group' => 1,
18414 
              'isClr' => 1,
18415 
              'is_floating_block' => 1,
18416 
              'period' => 1,
18417 
              'type' => 'logic',
18418 
              'valid_bit_used' => 0,
18419 
            },
18420 
            'direction' => 'in',
18421 
            'hdlType' => 'std_logic',
18422 
            'width' => 1,
18423 
          },
18424 
          'data_in' => {
18425 
            'attributes' => {
18426 
              'bin_pt' => 0,
18427 
              'is_floating_block' => 1,
18428 
              'must_be_hdl_vector' => 1,
18429 
              'period' => 1,
18430 
              'port_id' => 0,
18431 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
18432 
              'type' => 'UFix_32_0',
18433 
            },
18434 
            'direction' => 'in',
18435 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18436 
            'width' => 32,
18437 
          },
18438 
          'dout' => {
18439 
            'attributes' => {
18440 
              'bin_pt' => 0,
18441 
              'is_floating_block' => 1,
18442 
              'must_be_hdl_vector' => 1,
18443 
              'period' => 1,
18444 
              'port_id' => 0,
18445 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
18446 
              'type' => 'UFix_32_0',
18447 
            },
18448 
            'direction' => 'out',
18449 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18450 
            'width' => 32,
18451 
          },
18452 
          'en' => {
18453 
            'attributes' => {
18454 
              'bin_pt' => 0,
18455 
              'is_floating_block' => 1,
18456 
              'must_be_hdl_vector' => 1,
18457 
              'period' => 1,
18458 
              'port_id' => 1,
18459 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
18460 
              'type' => 'Bool',
18461 
            },
18462 
            'direction' => 'in',
18463 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18464 
            'width' => 1,
18465 
          },
18466 
        },
18467 
      },
18468 
      'entityName' => 'x_x28',
18469 
    },
18470 
    'to_register6' => {
18471 
      'connections' => {
18472 
        'ce' => 'sysgen_dut.to_register6_ce',
18473 
        'clk' => 'sysgen_dut.to_register6_clk',
18474 
        'clr' => 'sysgen_dut.to_register6_clr',
18475 
        'data_in' => 'sysgen_dut.to_register6_data_in',
18476 
        'dout' => 'to_register6.dout',
18477 
        'en' => 'sysgen_dut.to_register6_en',
18478 
      },
18479 
      'entity' => {
18480 
        'attributes' => {
18481 
          'entityAlreadyNetlisted' => 1,
18482 
          'generics' => [
18483 
          ],
18484 
          'is_floating_block' => 1,
18485 
          'mask' => {
18486 
            'Block_Handle' => 68.0009765625,
18487 
            'Block_handle' => 68.0009765625,
18488 
            'MDL_Handle' => 3.0009765625,
18489 
            'MDL_handle' => 3.0009765625,
18490 
            'arith_type' => 1,
18491 
            'bin_pt' => 14,
18492 
            'block_config' => 'sysgen_blockset:toreg_config',
18493 
            'block_handle' => 68.0009765625,
18494 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18495 
            'block_type' => 'toreg',
18496 
            'dbl_ovrd' => 0,
18497 
            'explicit_data_type' => 0,
18498 
            'init' => 0,
18499 
            'init_bit_vector' => '00000000000000000000000000000000b',
18500 
            'mdl_handle' => 3.0009765625,
18501 
            'model_handle' => 3.0009765625,
18502 
            'n_bits' => 16,
18503 
            'ownership' => 1,
18504 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18505 
            'shared_memory_name' => 'debug1i',
18506 
          },
18507 
          'needs_vhdl_wrapper' => 0,
18508 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18509 
        },
18510 
        'entityName' => 'x_x29',
18511 
        'ports' => {
18512 
          'ce' => {
18513 
            'attributes' => {
18514 
              'domain' => '',
18515 
              'group' => 1,
18516 
              'isCe' => 1,
18517 
              'is_floating_block' => 1,
18518 
              'period' => 1,
18519 
              'type' => 'logic',
18520 
            },
18521 
            'direction' => 'in',
18522 
            'hdlType' => 'std_logic',
18523 
            'width' => 1,
18524 
          },
18525 
          'clk' => {
18526 
            'attributes' => {
18527 
              'domain' => '',
18528 
              'group' => 1,
18529 
              'isClk' => 1,
18530 
              'is_floating_block' => 1,
18531 
              'period' => 1,
18532 
              'type' => 'logic',
18533 
            },
18534 
            'direction' => 'in',
18535 
            'hdlType' => 'std_logic',
18536 
            'width' => 1,
18537 
          },
18538 
          'clr' => {
18539 
            'attributes' => {
18540 
              'domain' => '',
18541 
              'group' => 1,
18542 
              'isClr' => 1,
18543 
              'is_floating_block' => 1,
18544 
              'period' => 1,
18545 
              'type' => 'logic',
18546 
              'valid_bit_used' => 0,
18547 
            },
18548 
            'direction' => 'in',
18549 
            'hdlType' => 'std_logic',
18550 
            'width' => 1,
18551 
          },
18552 
          'data_in' => {
18553 
            'attributes' => {
18554 
              'bin_pt' => 0,
18555 
              'is_floating_block' => 1,
18556 
              'must_be_hdl_vector' => 1,
18557 
              'period' => 1,
18558 
              'port_id' => 0,
18559 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
18560 
              'type' => 'UFix_32_0',
18561 
            },
18562 
            'direction' => 'in',
18563 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18564 
            'width' => 32,
18565 
          },
18566 
          'dout' => {
18567 
            'attributes' => {
18568 
              'bin_pt' => 0,
18569 
              'is_floating_block' => 1,
18570 
              'must_be_hdl_vector' => 1,
18571 
              'period' => 1,
18572 
              'port_id' => 0,
18573 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
18574 
              'type' => 'UFix_32_0',
18575 
            },
18576 
            'direction' => 'out',
18577 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18578 
            'width' => 32,
18579 
          },
18580 
          'en' => {
18581 
            'attributes' => {
18582 
              'bin_pt' => 0,
18583 
              'is_floating_block' => 1,
18584 
              'must_be_hdl_vector' => 1,
18585 
              'period' => 1,
18586 
              'port_id' => 1,
18587 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
18588 
              'type' => 'Bool',
18589 
            },
18590 
            'direction' => 'in',
18591 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18592 
            'width' => 1,
18593 
          },
18594 
        },
18595 
      },
18596 
      'entityName' => 'x_x29',
18597 
    },
18598 
    'to_register7' => {
18599 
      'connections' => {
18600 
        'ce' => 'sysgen_dut.to_register7_ce',
18601 
        'clk' => 'sysgen_dut.to_register7_clk',
18602 
        'clr' => 'sysgen_dut.to_register7_clr',
18603 
        'data_in' => 'sysgen_dut.to_register7_data_in',
18604 
        'dout' => 'to_register7.dout',
18605 
        'en' => 'sysgen_dut.to_register7_en',
18606 
      },
18607 
      'entity' => {
18608 
        'attributes' => {
18609 
          'entityAlreadyNetlisted' => 1,
18610 
          'generics' => [
18611 
          ],
18612 
          'is_floating_block' => 1,
18613 
          'mask' => {
18614 
            'Block_Handle' => 69.0009765625,
18615 
            'Block_handle' => 69.0009765625,
18616 
            'MDL_Handle' => 3.0009765625,
18617 
            'MDL_handle' => 3.0009765625,
18618 
            'arith_type' => 1,
18619 
            'bin_pt' => 14,
18620 
            'block_config' => 'sysgen_blockset:toreg_config',
18621 
            'block_handle' => 69.0009765625,
18622 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18623 
            'block_type' => 'toreg',
18624 
            'dbl_ovrd' => 0,
18625 
            'explicit_data_type' => 0,
18626 
            'init' => 0,
18627 
            'init_bit_vector' => '00000000000000000000000000000000b',
18628 
            'mdl_handle' => 3.0009765625,
18629 
            'model_handle' => 3.0009765625,
18630 
            'n_bits' => 16,
18631 
            'ownership' => 1,
18632 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18633 
            'shared_memory_name' => 'register01td',
18634 
          },
18635 
          'needs_vhdl_wrapper' => 0,
18636 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18637 
        },
18638 
        'entityName' => 'x_x30',
18639 
        'ports' => {
18640 
          'ce' => {
18641 
            'attributes' => {
18642 
              'domain' => '',
18643 
              'group' => 1,
18644 
              'isCe' => 1,
18645 
              'is_floating_block' => 1,
18646 
              'period' => 1,
18647 
              'type' => 'logic',
18648 
            },
18649 
            'direction' => 'in',
18650 
            'hdlType' => 'std_logic',
18651 
            'width' => 1,
18652 
          },
18653 
          'clk' => {
18654 
            'attributes' => {
18655 
              'domain' => '',
18656 
              'group' => 1,
18657 
              'isClk' => 1,
18658 
              'is_floating_block' => 1,
18659 
              'period' => 1,
18660 
              'type' => 'logic',
18661 
            },
18662 
            'direction' => 'in',
18663 
            'hdlType' => 'std_logic',
18664 
            'width' => 1,
18665 
          },
18666 
          'clr' => {
18667 
            'attributes' => {
18668 
              'domain' => '',
18669 
              'group' => 1,
18670 
              'isClr' => 1,
18671 
              'is_floating_block' => 1,
18672 
              'period' => 1,
18673 
              'type' => 'logic',
18674 
              'valid_bit_used' => 0,
18675 
            },
18676 
            'direction' => 'in',
18677 
            'hdlType' => 'std_logic',
18678 
            'width' => 1,
18679 
          },
18680 
          'data_in' => {
18681 
            'attributes' => {
18682 
              'bin_pt' => 0,
18683 
              'is_floating_block' => 1,
18684 
              'must_be_hdl_vector' => 1,
18685 
              'period' => 1,
18686 
              'port_id' => 0,
18687 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
18688 
              'type' => 'UFix_32_0',
18689 
            },
18690 
            'direction' => 'in',
18691 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18692 
            'width' => 32,
18693 
          },
18694 
          'dout' => {
18695 
            'attributes' => {
18696 
              'bin_pt' => 0,
18697 
              'is_floating_block' => 1,
18698 
              'must_be_hdl_vector' => 1,
18699 
              'period' => 1,
18700 
              'port_id' => 0,
18701 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
18702 
              'type' => 'UFix_32_0',
18703 
            },
18704 
            'direction' => 'out',
18705 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18706 
            'width' => 32,
18707 
          },
18708 
          'en' => {
18709 
            'attributes' => {
18710 
              'bin_pt' => 0,
18711 
              'is_floating_block' => 1,
18712 
              'must_be_hdl_vector' => 1,
18713 
              'period' => 1,
18714 
              'port_id' => 1,
18715 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
18716 
              'type' => 'Bool',
18717 
            },
18718 
            'direction' => 'in',
18719 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18720 
            'width' => 1,
18721 
          },
18722 
        },
18723 
      },
18724 
      'entityName' => 'x_x30',
18725 
    },
18726 
    'to_register8' => {
18727 
      'connections' => {
18728 
        'ce' => 'sysgen_dut.to_register8_ce',
18729 
        'clk' => 'sysgen_dut.to_register8_clk',
18730 
        'clr' => 'sysgen_dut.to_register8_clr',
18731 
        'data_in' => 'sysgen_dut.to_register8_data_in',
18732 
        'dout' => 'to_register8.dout',
18733 
        'en' => 'sysgen_dut.to_register8_en',
18734 
      },
18735 
      'entity' => {
18736 
        'attributes' => {
18737 
          'entityAlreadyNetlisted' => 1,
18738 
          'generics' => [
18739 
          ],
18740 
          'is_floating_block' => 1,
18741 
          'mask' => {
18742 
            'Block_Handle' => 70.0009765625,
18743 
            'Block_handle' => 70.0009765625,
18744 
            'MDL_Handle' => 3.0009765625,
18745 
            'MDL_handle' => 3.0009765625,
18746 
            'arith_type' => 1,
18747 
            'bin_pt' => 14,
18748 
            'block_config' => 'sysgen_blockset:toreg_config',
18749 
            'block_handle' => 70.0009765625,
18750 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18751 
            'block_type' => 'toreg',
18752 
            'dbl_ovrd' => 0,
18753 
            'explicit_data_type' => 0,
18754 
            'init' => 0,
18755 
            'init_bit_vector' => '0b',
18756 
            'mdl_handle' => 3.0009765625,
18757 
            'model_handle' => 3.0009765625,
18758 
            'n_bits' => 16,
18759 
            'ownership' => 1,
18760 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18761 
            'shared_memory_name' => 'register03tv',
18762 
          },
18763 
          'needs_vhdl_wrapper' => 0,
18764 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18765 
        },
18766 
        'entityName' => 'x_x31',
18767 
        'ports' => {
18768 
          'ce' => {
18769 
            'attributes' => {
18770 
              'domain' => '',
18771 
              'group' => 1,
18772 
              'isCe' => 1,
18773 
              'is_floating_block' => 1,
18774 
              'period' => 1,
18775 
              'type' => 'logic',
18776 
            },
18777 
            'direction' => 'in',
18778 
            'hdlType' => 'std_logic',
18779 
            'width' => 1,
18780 
          },
18781 
          'clk' => {
18782 
            'attributes' => {
18783 
              'domain' => '',
18784 
              'group' => 1,
18785 
              'isClk' => 1,
18786 
              'is_floating_block' => 1,
18787 
              'period' => 1,
18788 
              'type' => 'logic',
18789 
            },
18790 
            'direction' => 'in',
18791 
            'hdlType' => 'std_logic',
18792 
            'width' => 1,
18793 
          },
18794 
          'clr' => {
18795 
            'attributes' => {
18796 
              'domain' => '',
18797 
              'group' => 1,
18798 
              'isClr' => 1,
18799 
              'is_floating_block' => 1,
18800 
              'period' => 1,
18801 
              'type' => 'logic',
18802 
              'valid_bit_used' => 0,
18803 
            },
18804 
            'direction' => 'in',
18805 
            'hdlType' => 'std_logic',
18806 
            'width' => 1,
18807 
          },
18808 
          'data_in' => {
18809 
            'attributes' => {
18810 
              'bin_pt' => 0,
18811 
              'is_floating_block' => 1,
18812 
              'must_be_hdl_vector' => 1,
18813 
              'period' => 1,
18814 
              'port_id' => 0,
18815 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
18816 
              'type' => 'Bool',
18817 
            },
18818 
            'direction' => 'in',
18819 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18820 
            'width' => 1,
18821 
          },
18822 
          'dout' => {
18823 
            'attributes' => {
18824 
              'bin_pt' => 0,
18825 
              'is_floating_block' => 1,
18826 
              'must_be_hdl_vector' => 1,
18827 
              'period' => 1,
18828 
              'port_id' => 0,
18829 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
18830 
              'type' => 'Bool',
18831 
            },
18832 
            'direction' => 'out',
18833 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18834 
            'width' => 1,
18835 
          },
18836 
          'en' => {
18837 
            'attributes' => {
18838 
              'bin_pt' => 0,
18839 
              'is_floating_block' => 1,
18840 
              'must_be_hdl_vector' => 1,
18841 
              'period' => 1,
18842 
              'port_id' => 1,
18843 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
18844 
              'type' => 'Bool',
18845 
            },
18846 
            'direction' => 'in',
18847 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18848 
            'width' => 1,
18849 
          },
18850 
        },
18851 
      },
18852 
      'entityName' => 'x_x31',
18853 
    },
18854 
    'to_register9' => {
18855 
      'connections' => {
18856 
        'ce' => 'sysgen_dut.to_register9_ce',
18857 
        'clk' => 'sysgen_dut.to_register9_clk',
18858 
        'clr' => 'sysgen_dut.to_register9_clr',
18859 
        'data_in' => 'sysgen_dut.to_register9_data_in',
18860 
        'dout' => 'to_register9.dout',
18861 
        'en' => 'sysgen_dut.to_register9_en',
18862 
      },
18863 
      'entity' => {
18864 
        'attributes' => {
18865 
          'entityAlreadyNetlisted' => 1,
18866 
          'generics' => [
18867 
          ],
18868 
          'is_floating_block' => 1,
18869 
          'mask' => {
18870 
            'Block_Handle' => 71.0009765625,
18871 
            'Block_handle' => 71.0009765625,
18872 
            'MDL_Handle' => 3.0009765625,
18873 
            'MDL_handle' => 3.0009765625,
18874 
            'arith_type' => 1,
18875 
            'bin_pt' => 14,
18876 
            'block_config' => 'sysgen_blockset:toreg_config',
18877 
            'block_handle' => 71.0009765625,
18878 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
18879 
            'block_type' => 'toreg',
18880 
            'dbl_ovrd' => 0,
18881 
            'explicit_data_type' => 0,
18882 
            'init' => 0,
18883 
            'init_bit_vector' => '00000000000000000000000000000000b',
18884 
            'mdl_handle' => 3.0009765625,
18885 
            'model_handle' => 3.0009765625,
18886 
            'n_bits' => 16,
18887 
            'ownership' => 1,
18888 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18889 
            'shared_memory_name' => 'register03td',
18890 
          },
18891 
          'needs_vhdl_wrapper' => 0,
18892 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
18893 
        },
18894 
        'entityName' => 'x_x32',
18895 
        'ports' => {
18896 
          'ce' => {
18897 
            'attributes' => {
18898 
              'domain' => '',
18899 
              'group' => 1,
18900 
              'isCe' => 1,
18901 
              'is_floating_block' => 1,
18902 
              'period' => 1,
18903 
              'type' => 'logic',
18904 
            },
18905 
            'direction' => 'in',
18906 
            'hdlType' => 'std_logic',
18907 
            'width' => 1,
18908 
          },
18909 
          'clk' => {
18910 
            'attributes' => {
18911 
              'domain' => '',
18912 
              'group' => 1,
18913 
              'isClk' => 1,
18914 
              'is_floating_block' => 1,
18915 
              'period' => 1,
18916 
              'type' => 'logic',
18917 
            },
18918 
            'direction' => 'in',
18919 
            'hdlType' => 'std_logic',
18920 
            'width' => 1,
18921 
          },
18922 
          'clr' => {
18923 
            'attributes' => {
18924 
              'domain' => '',
18925 
              'group' => 1,
18926 
              'isClr' => 1,
18927 
              'is_floating_block' => 1,
18928 
              'period' => 1,
18929 
              'type' => 'logic',
18930 
              'valid_bit_used' => 0,
18931 
            },
18932 
            'direction' => 'in',
18933 
            'hdlType' => 'std_logic',
18934 
            'width' => 1,
18935 
          },
18936 
          'data_in' => {
18937 
            'attributes' => {
18938 
              'bin_pt' => 0,
18939 
              'is_floating_block' => 1,
18940 
              'must_be_hdl_vector' => 1,
18941 
              'period' => 1,
18942 
              'port_id' => 0,
18943 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
18944 
              'type' => 'UFix_32_0',
18945 
            },
18946 
            'direction' => 'in',
18947 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18948 
            'width' => 32,
18949 
          },
18950 
          'dout' => {
18951 
            'attributes' => {
18952 
              'bin_pt' => 0,
18953 
              'is_floating_block' => 1,
18954 
              'must_be_hdl_vector' => 1,
18955 
              'period' => 1,
18956 
              'port_id' => 0,
18957 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
18958 
              'type' => 'UFix_32_0',
18959 
            },
18960 
            'direction' => 'out',
18961 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18962 
            'width' => 32,
18963 
          },
18964 
          'en' => {
18965 
            'attributes' => {
18966 
              'bin_pt' => 0,
18967 
              'is_floating_block' => 1,
18968 
              'must_be_hdl_vector' => 1,
18969 
              'period' => 1,
18970 
              'port_id' => 1,
18971 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
18972 
              'type' => 'Bool',
18973 
            },
18974 
            'direction' => 'in',
18975 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18976 
            'width' => 1,
18977 
          },
18978 
        },
18979 
      },
18980 
      'entityName' => 'x_x32',
18981 
    },
18982 
  },
18983 
}

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