OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis.1] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
{
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fprintf(\'\',\'COMMENT: end icon graphics\');
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    },
462 
    'constant5_op_net_x2' => {
463 
      'hdlType' => 'std_logic',
464 
      'width' => 1,
465 
    },
466 
    'constant5_op_net_x3' => {
467 
      'hdlType' => 'std_logic',
468 
      'width' => 1,
469 
    },
470 
    'constant5_op_net_x4' => {
471 
      'hdlType' => 'std_logic',
472 
      'width' => 1,
473 
    },
474 
    'constant5_op_net_x5' => {
475 
      'hdlType' => 'std_logic',
476 
      'width' => 1,
477 
    },
478 
    'constant5_op_net_x6' => {
479 
      'hdlType' => 'std_logic',
480 
      'width' => 1,
481 
    },
482 
    'constant5_op_net_x7' => {
483 
      'hdlType' => 'std_logic',
484 
      'width' => 1,
485 
    },
486 
    'constant5_op_net_x8' => {
487 
      'hdlType' => 'std_logic',
488 
      'width' => 1,
489 
    },
490 
    'constant5_op_net_x9' => {
491 
      'hdlType' => 'std_logic',
492 
      'width' => 1,
493 
    },
494 
    'debug_in_1i_net' => {
495 
      'hdlType' => 'std_logic_vector(31 downto 0)',
496 
      'width' => 32,
497 
    },
498 
    'debug_in_1i_net_x0' => {
499 
      'hdlType' => 'std_logic_vector(31 downto 0)',
500 
      'width' => 32,
501 
    },
502 
    'debug_in_2i_net' => {
503 
      'hdlType' => 'std_logic_vector(31 downto 0)',
504 
      'width' => 32,
505 
    },
506 
    'debug_in_2i_net_x0' => {
507 
      'hdlType' => 'std_logic_vector(31 downto 0)',
508 
      'width' => 32,
509 
    },
510 
    'debug_in_3i_net' => {
511 
      'hdlType' => 'std_logic_vector(31 downto 0)',
512 
      'width' => 32,
513 
    },
514 
    'debug_in_3i_net_x0' => {
515 
      'hdlType' => 'std_logic_vector(31 downto 0)',
516 
      'width' => 32,
517 
    },
518 
    'debug_in_4i_net' => {
519 
      'hdlType' => 'std_logic_vector(31 downto 0)',
520 
      'width' => 32,
521 
    },
522 
    'debug_in_4i_net_x0' => {
523 
      'hdlType' => 'std_logic_vector(31 downto 0)',
524 
      'width' => 32,
525 
    },
526 
    'dma_host2board_busy_net' => {
527 
      'hdlType' => 'std_logic',
528 
      'width' => 1,
529 
    },
530 
    'dma_host2board_busy_net_x0' => {
531 
      'hdlType' => 'std_logic',
532 
      'width' => 1,
533 
    },
534 
    'dma_host2board_done_net' => {
535 
      'hdlType' => 'std_logic',
536 
      'width' => 1,
537 
    },
538 
    'dma_host2board_done_net_x0' => {
539 
      'hdlType' => 'std_logic',
540 
      'width' => 1,
541 
    },
542 
    'from_register10_data_out_net' => {
543 
      'hdlType' => 'std_logic_vector(31 downto 0)',
544 
      'width' => 32,
545 
    },
546 
    'from_register10_data_out_net_x0' => {
547 
      'hdlType' => 'std_logic_vector(31 downto 0)',
548 
      'width' => 32,
549 
    },
550 
    'from_register11_data_out_net' => {
551 
      'hdlType' => 'std_logic_vector(31 downto 0)',
552 
      'width' => 32,
553 
    },
554 
    'from_register11_data_out_net_x0' => {
555 
      'hdlType' => 'std_logic_vector(31 downto 0)',
556 
      'width' => 32,
557 
    },
558 
    'from_register12_data_out_net' => {
559 
      'hdlType' => 'std_logic',
560 
      'width' => 1,
561 
    },
562 
    'from_register12_data_out_net_x0' => {
563 
      'hdlType' => 'std_logic',
564 
      'width' => 1,
565 
    },
566 
    'from_register13_data_out_net' => {
567 
      'hdlType' => 'std_logic_vector(31 downto 0)',
568 
      'width' => 32,
569 
    },
570 
    'from_register13_data_out_net_x0' => {
571 
      'hdlType' => 'std_logic_vector(31 downto 0)',
572 
      'width' => 32,
573 
    },
574 
    'from_register14_data_out_net' => {
575 
      'hdlType' => 'std_logic',
576 
      'width' => 1,
577 
    },
578 
    'from_register14_data_out_net_x0' => {
579 
      'hdlType' => 'std_logic',
580 
      'width' => 1,
581 
    },
582 
    'from_register15_data_out_net' => {
583 
      'hdlType' => 'std_logic_vector(31 downto 0)',
584 
      'width' => 32,
585 
    },
586 
    'from_register15_data_out_net_x0' => {
587 
      'hdlType' => 'std_logic_vector(31 downto 0)',
588 
      'width' => 32,
589 
    },
590 
    'from_register16_data_out_net' => {
591 
      'hdlType' => 'std_logic',
592 
      'width' => 1,
593 
    },
594 
    'from_register16_data_out_net_x0' => {
595 
      'hdlType' => 'std_logic',
596 
      'width' => 1,
597 
    },
598 
    'from_register17_data_out_net' => {
599 
      'hdlType' => 'std_logic_vector(31 downto 0)',
600 
      'width' => 32,
601 
    },
602 
    'from_register17_data_out_net_x0' => {
603 
      'hdlType' => 'std_logic_vector(31 downto 0)',
604 
      'width' => 32,
605 
    },
606 
    'from_register18_data_out_net' => {
607 
      'hdlType' => 'std_logic',
608 
      'width' => 1,
609 
    },
610 
    'from_register18_data_out_net_x0' => {
611 
      'hdlType' => 'std_logic',
612 
      'width' => 1,
613 
    },
614 
    'from_register19_data_out_net' => {
615 
      'hdlType' => 'std_logic_vector(31 downto 0)',
616 
      'width' => 32,
617 
    },
618 
    'from_register19_data_out_net_x0' => {
619 
      'hdlType' => 'std_logic_vector(31 downto 0)',
620 
      'width' => 32,
621 
    },
622 
    'from_register1_data_out_net' => {
623 
      'hdlType' => 'std_logic',
624 
      'width' => 1,
625 
    },
626 
    'from_register1_data_out_net_x0' => {
627 
      'hdlType' => 'std_logic',
628 
      'width' => 1,
629 
    },
630 
    'from_register20_data_out_net' => {
631 
      'hdlType' => 'std_logic',
632 
      'width' => 1,
633 
    },
634 
    'from_register20_data_out_net_x0' => {
635 
      'hdlType' => 'std_logic',
636 
      'width' => 1,
637 
    },
638 
    'from_register21_data_out_net' => {
639 
      'hdlType' => 'std_logic_vector(31 downto 0)',
640 
      'width' => 32,
641 
    },
642 
    'from_register21_data_out_net_x0' => {
643 
      'hdlType' => 'std_logic_vector(31 downto 0)',
644 
      'width' => 32,
645 
    },
646 
    'from_register22_data_out_net' => {
647 
      'hdlType' => 'std_logic',
648 
      'width' => 1,
649 
    },
650 
    'from_register22_data_out_net_x0' => {
651 
      'hdlType' => 'std_logic',
652 
      'width' => 1,
653 
    },
654 
    'from_register23_data_out_net' => {
655 
      'hdlType' => 'std_logic_vector(31 downto 0)',
656 
      'width' => 32,
657 
    },
658 
    'from_register23_data_out_net_x0' => {
659 
      'hdlType' => 'std_logic_vector(31 downto 0)',
660 
      'width' => 32,
661 
    },
662 
    'from_register24_data_out_net' => {
663 
      'hdlType' => 'std_logic',
664 
      'width' => 1,
665 
    },
666 
    'from_register24_data_out_net_x0' => {
667 
      'hdlType' => 'std_logic',
668 
      'width' => 1,
669 
    },
670 
    'from_register25_data_out_net' => {
671 
      'hdlType' => 'std_logic_vector(31 downto 0)',
672 
      'width' => 32,
673 
    },
674 
    'from_register25_data_out_net_x0' => {
675 
      'hdlType' => 'std_logic_vector(31 downto 0)',
676 
      'width' => 32,
677 
    },
678 
    'from_register26_data_out_net' => {
679 
      'hdlType' => 'std_logic',
680 
      'width' => 1,
681 
    },
682 
    'from_register26_data_out_net_x0' => {
683 
      'hdlType' => 'std_logic',
684 
      'width' => 1,
685 
    },
686 
    'from_register27_data_out_net' => {
687 
      'hdlType' => 'std_logic_vector(31 downto 0)',
688 
      'width' => 32,
689 
    },
690 
    'from_register27_data_out_net_x0' => {
691 
      'hdlType' => 'std_logic_vector(31 downto 0)',
692 
      'width' => 32,
693 
    },
694 
    'from_register28_data_out_net' => {
695 
      'hdlType' => 'std_logic',
696 
      'width' => 1,
697 
    },
698 
    'from_register28_data_out_net_x0' => {
699 
      'hdlType' => 'std_logic',
700 
      'width' => 1,
701 
    },
702 
    'from_register2_data_out_net' => {
703 
      'hdlType' => 'std_logic',
704 
      'width' => 1,
705 
    },
706 
    'from_register2_data_out_net_x0' => {
707 
      'hdlType' => 'std_logic',
708 
      'width' => 1,
709 
    },
710 
    'from_register3_data_out_net' => {
711 
      'hdlType' => 'std_logic_vector(31 downto 0)',
712 
      'width' => 32,
713 
    },
714 
    'from_register3_data_out_net_x0' => {
715 
      'hdlType' => 'std_logic_vector(31 downto 0)',
716 
      'width' => 32,
717 
    },
718 
    'from_register4_data_out_net' => {
719 
      'hdlType' => 'std_logic',
720 
      'width' => 1,
721 
    },
722 
    'from_register4_data_out_net_x0' => {
723 
      'hdlType' => 'std_logic',
724 
      'width' => 1,
725 
    },
726 
    'from_register5_data_out_net' => {
727 
      'hdlType' => 'std_logic_vector(31 downto 0)',
728 
      'width' => 32,
729 
    },
730 
    'from_register5_data_out_net_x0' => {
731 
      'hdlType' => 'std_logic_vector(31 downto 0)',
732 
      'width' => 32,
733 
    },
734 
    'from_register6_data_out_net' => {
735 
      'hdlType' => 'std_logic',
736 
      'width' => 1,
737 
    },
738 
    'from_register6_data_out_net_x0' => {
739 
      'hdlType' => 'std_logic',
740 
      'width' => 1,
741 
    },
742 
    'from_register7_data_out_net' => {
743 
      'hdlType' => 'std_logic_vector(31 downto 0)',
744 
      'width' => 32,
745 
    },
746 
    'from_register7_data_out_net_x0' => {
747 
      'hdlType' => 'std_logic_vector(31 downto 0)',
748 
      'width' => 32,
749 
    },
750 
    'from_register8_data_out_net' => {
751 
      'hdlType' => 'std_logic_vector(31 downto 0)',
752 
      'width' => 32,
753 
    },
754 
    'from_register8_data_out_net_x0' => {
755 
      'hdlType' => 'std_logic_vector(31 downto 0)',
756 
      'width' => 32,
757 
    },
758 
    'from_register9_data_out_net' => {
759 
      'hdlType' => 'std_logic',
760 
      'width' => 1,
761 
    },
762 
    'from_register9_data_out_net_x0' => {
763 
      'hdlType' => 'std_logic',
764 
      'width' => 1,
765 
    },
766 
    'reg01_td_net' => {
767 
      'hdlType' => 'std_logic_vector(31 downto 0)',
768 
      'width' => 32,
769 
    },
770 
    'reg01_td_net_x0' => {
771 
      'hdlType' => 'std_logic_vector(31 downto 0)',
772 
      'width' => 32,
773 
    },
774 
    'reg01_tv_net' => {
775 
      'hdlType' => 'std_logic',
776 
      'width' => 1,
777 
    },
778 
    'reg01_tv_net_x0' => {
779 
      'hdlType' => 'std_logic',
780 
      'width' => 1,
781 
    },
782 
    'reg02_td_net' => {
783 
      'hdlType' => 'std_logic_vector(31 downto 0)',
784 
      'width' => 32,
785 
    },
786 
    'reg02_td_net_x0' => {
787 
      'hdlType' => 'std_logic_vector(31 downto 0)',
788 
      'width' => 32,
789 
    },
790 
    'reg02_tv_net' => {
791 
      'hdlType' => 'std_logic',
792 
      'width' => 1,
793 
    },
794 
    'reg02_tv_net_x0' => {
795 
      'hdlType' => 'std_logic',
796 
      'width' => 1,
797 
    },
798 
    'reg03_td_net' => {
799 
      'hdlType' => 'std_logic_vector(31 downto 0)',
800 
      'width' => 32,
801 
    },
802 
    'reg03_td_net_x0' => {
803 
      'hdlType' => 'std_logic_vector(31 downto 0)',
804 
      'width' => 32,
805 
    },
806 
    'reg03_tv_net' => {
807 
      'hdlType' => 'std_logic',
808 
      'width' => 1,
809 
    },
810 
    'reg03_tv_net_x0' => {
811 
      'hdlType' => 'std_logic',
812 
      'width' => 1,
813 
    },
814 
    'reg04_td_net' => {
815 
      'hdlType' => 'std_logic_vector(31 downto 0)',
816 
      'width' => 32,
817 
    },
818 
    'reg04_td_net_x0' => {
819 
      'hdlType' => 'std_logic_vector(31 downto 0)',
820 
      'width' => 32,
821 
    },
822 
    'reg04_tv_net' => {
823 
      'hdlType' => 'std_logic',
824 
      'width' => 1,
825 
    },
826 
    'reg04_tv_net_x0' => {
827 
      'hdlType' => 'std_logic',
828 
      'width' => 1,
829 
    },
830 
    'reg05_td_net' => {
831 
      'hdlType' => 'std_logic_vector(31 downto 0)',
832 
      'width' => 32,
833 
    },
834 
    'reg05_td_net_x0' => {
835 
      'hdlType' => 'std_logic_vector(31 downto 0)',
836 
      'width' => 32,
837 
    },
838 
    'reg05_tv_net' => {
839 
      'hdlType' => 'std_logic',
840 
      'width' => 1,
841 
    },
842 
    'reg05_tv_net_x0' => {
843 
      'hdlType' => 'std_logic',
844 
      'width' => 1,
845 
    },
846 
    'reg06_td_net' => {
847 
      'hdlType' => 'std_logic_vector(31 downto 0)',
848 
      'width' => 32,
849 
    },
850 
    'reg06_td_net_x0' => {
851 
      'hdlType' => 'std_logic_vector(31 downto 0)',
852 
      'width' => 32,
853 
    },
854 
    'reg06_tv_net' => {
855 
      'hdlType' => 'std_logic',
856 
      'width' => 1,
857 
    },
858 
    'reg06_tv_net_x0' => {
859 
      'hdlType' => 'std_logic',
860 
      'width' => 1,
861 
    },
862 
    'reg07_td_net' => {
863 
      'hdlType' => 'std_logic_vector(31 downto 0)',
864 
      'width' => 32,
865 
    },
866 
    'reg07_td_net_x0' => {
867 
      'hdlType' => 'std_logic_vector(31 downto 0)',
868 
      'width' => 32,
869 
    },
870 
    'reg07_tv_net' => {
871 
      'hdlType' => 'std_logic',
872 
      'width' => 1,
873 
    },
874 
    'reg07_tv_net_x0' => {
875 
      'hdlType' => 'std_logic',
876 
      'width' => 1,
877 
    },
878 
    'reg08_td_net' => {
879 
      'hdlType' => 'std_logic_vector(31 downto 0)',
880 
      'width' => 32,
881 
    },
882 
    'reg08_td_net_x0' => {
883 
      'hdlType' => 'std_logic_vector(31 downto 0)',
884 
      'width' => 32,
885 
    },
886 
    'reg08_tv_net' => {
887 
      'hdlType' => 'std_logic',
888 
      'width' => 1,
889 
    },
890 
    'reg08_tv_net_x0' => {
891 
      'hdlType' => 'std_logic',
892 
      'width' => 1,
893 
    },
894 
    'reg09_td_net' => {
895 
      'hdlType' => 'std_logic_vector(31 downto 0)',
896 
      'width' => 32,
897 
    },
898 
    'reg09_td_net_x0' => {
899 
      'hdlType' => 'std_logic_vector(31 downto 0)',
900 
      'width' => 32,
901 
    },
902 
    'reg09_tv_net' => {
903 
      'hdlType' => 'std_logic',
904 
      'width' => 1,
905 
    },
906 
    'reg09_tv_net_x0' => {
907 
      'hdlType' => 'std_logic',
908 
      'width' => 1,
909 
    },
910 
    'reg10_td_net' => {
911 
      'hdlType' => 'std_logic_vector(31 downto 0)',
912 
      'width' => 32,
913 
    },
914 
    'reg10_td_net_x0' => {
915 
      'hdlType' => 'std_logic_vector(31 downto 0)',
916 
      'width' => 32,
917 
    },
918 
    'reg10_tv_net' => {
919 
      'hdlType' => 'std_logic',
920 
      'width' => 1,
921 
    },
922 
    'reg10_tv_net_x0' => {
923 
      'hdlType' => 'std_logic',
924 
      'width' => 1,
925 
    },
926 
    'reg11_td_net' => {
927 
      'hdlType' => 'std_logic_vector(31 downto 0)',
928 
      'width' => 32,
929 
    },
930 
    'reg11_td_net_x0' => {
931 
      'hdlType' => 'std_logic_vector(31 downto 0)',
932 
      'width' => 32,
933 
    },
934 
    'reg11_tv_net' => {
935 
      'hdlType' => 'std_logic',
936 
      'width' => 1,
937 
    },
938 
    'reg11_tv_net_x0' => {
939 
      'hdlType' => 'std_logic',
940 
      'width' => 1,
941 
    },
942 
    'reg12_td_net' => {
943 
      'hdlType' => 'std_logic_vector(31 downto 0)',
944 
      'width' => 32,
945 
    },
946 
    'reg12_td_net_x0' => {
947 
      'hdlType' => 'std_logic_vector(31 downto 0)',
948 
      'width' => 32,
949 
    },
950 
    'reg12_tv_net' => {
951 
      'hdlType' => 'std_logic',
952 
      'width' => 1,
953 
    },
954 
    'reg12_tv_net_x0' => {
955 
      'hdlType' => 'std_logic',
956 
      'width' => 1,
957 
    },
958 
    'reg13_td_net' => {
959 
      'hdlType' => 'std_logic_vector(31 downto 0)',
960 
      'width' => 32,
961 
    },
962 
    'reg13_td_net_x0' => {
963 
      'hdlType' => 'std_logic_vector(31 downto 0)',
964 
      'width' => 32,
965 
    },
966 
    'reg13_tv_net' => {
967 
      'hdlType' => 'std_logic',
968 
      'width' => 1,
969 
    },
970 
    'reg13_tv_net_x0' => {
971 
      'hdlType' => 'std_logic',
972 
      'width' => 1,
973 
    },
974 
    'reg14_td_net' => {
975 
      'hdlType' => 'std_logic_vector(31 downto 0)',
976 
      'width' => 32,
977 
    },
978 
    'reg14_td_net_x0' => {
979 
      'hdlType' => 'std_logic_vector(31 downto 0)',
980 
      'width' => 32,
981 
    },
982 
    'reg14_tv_net' => {
983 
      'hdlType' => 'std_logic',
984 
      'width' => 1,
985 
    },
986 
    'reg14_tv_net_x0' => {
987 
      'hdlType' => 'std_logic',
988 
      'width' => 1,
989 
    },
990 
    'to_register10_dout_net' => {
991 
      'hdlType' => 'std_logic',
992 
      'width' => 1,
993 
    },
994 
    'to_register11_dout_net' => {
995 
      'hdlType' => 'std_logic_vector(31 downto 0)',
996 
      'width' => 32,
997 
    },
998 
    'to_register12_dout_net' => {
999 
      'hdlType' => 'std_logic',
1000 
      'width' => 1,
1001 
    },
1002 
    'to_register13_dout_net' => {
1003 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1004 
      'width' => 32,
1005 
    },
1006 
    'to_register14_dout_net' => {
1007 
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1008 
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2800 
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2801 
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2802 
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2803 
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2804 
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2805 
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2806 
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2807 
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2816 
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2821 
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2824 
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2825 
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2827 
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2829 
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2830 
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2831 
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2840 
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2843 
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2845 
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2850 
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2851 
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2852 
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2853 
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2854 
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2855 
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2856 
        'en_x11' => 'constant5_op_net_x12',
2857 
        'en_x12' => 'constant1_op_net_x0',
2858 
        'en_x13' => 'constant1_op_net_x1',
2859 
        'en_x14' => 'constant1_op_net_x2',
2860 
        'en_x15' => 'constant1_op_net_x3',
2861 
        'en_x16' => 'constant1_op_net_x4',
2862 
        'en_x17' => 'constant1_op_net_x5',
2863 
        'en_x18' => 'constant1_op_net_x6',
2864 
        'en_x19' => 'constant1_op_net_x7',
2865 
        'en_x2' => 'constant5_op_net_x3',
2866 
        'en_x20' => 'constant1_op_net_x8',
2867 
        'en_x21' => 'constant5_op_net_x13',
2868 
        'en_x22' => 'constant1_op_net_x9',
2869 
        'en_x23' => 'constant1_op_net_x10',
2870 
        'en_x24' => 'constant1_op_net_x11',
2871 
        'en_x25' => 'constant1_op_net_x12',
2872 
        'en_x26' => 'constant1_op_net_x13',
2873 
        'en_x27' => 'constant5_op_net_x14',
2874 
        'en_x28' => 'constant5_op_net_x15',
2875 
        'en_x29' => 'constant5_op_net_x16',
2876 
        'en_x3' => 'constant5_op_net_x4',
2877 
        'en_x30' => 'constant5_op_net_x17',
2878 
        'en_x31' => 'constant5_op_net_x18',
2879 
        'en_x32' => 'constant5_op_net_x19',
2880 
        'en_x4' => 'constant5_op_net_x5',
2881 
        'en_x5' => 'constant5_op_net_x6',
2882 
        'en_x6' => 'constant5_op_net_x7',
2883 
        'en_x7' => 'constant5_op_net_x8',
2884 
        'en_x8' => 'constant5_op_net_x9',
2885 
        'en_x9' => 'constant5_op_net_x10',
2886 
        'reg01_rd' => 'from_register3_data_out_net_x0',
2887 
        'reg01_rv' => 'from_register1_data_out_net_x0',
2888 
        'reg01_td' => 'reg01_td_net',
2889 
        'reg01_tv' => 'reg01_tv_net',
2890 
        'reg02_rd' => 'from_register5_data_out_net_x0',
2891 
        'reg02_rv' => 'from_register2_data_out_net_x0',
2892 
        'reg02_td' => 'reg02_td_net',
2893 
        'reg02_tv' => 'reg02_tv_net',
2894 
        'reg03_rd' => 'from_register7_data_out_net_x0',
2895 
        'reg03_rv' => 'from_register6_data_out_net_x0',
2896 
        'reg03_td' => 'reg03_td_net',
2897 
        'reg03_tv' => 'reg03_tv_net',
2898 
        'reg04_rd' => 'from_register8_data_out_net_x0',
2899 
        'reg04_rv' => 'from_register4_data_out_net_x0',
2900 
        'reg04_td' => 'reg04_td_net',
2901 
        'reg04_tv' => 'reg04_tv_net',
2902 
        'reg05_rd' => 'from_register10_data_out_net_x0',
2903 
        'reg05_rv' => 'from_register9_data_out_net_x0',
2904 
        'reg05_td' => 'reg05_td_net',
2905 
        'reg05_tv' => 'reg05_tv_net',
2906 
        'reg06_rd' => 'from_register11_data_out_net_x0',
2907 
        'reg06_rv' => 'from_register12_data_out_net_x0',
2908 
        'reg06_td' => 'reg06_td_net',
2909 
        'reg06_tv' => 'reg06_tv_net',
2910 
        'reg07_rd' => 'from_register13_data_out_net_x0',
2911 
        'reg07_rv' => 'from_register14_data_out_net_x0',
2912 
        'reg07_td' => 'reg07_td_net',
2913 
        'reg07_tv' => 'reg07_tv_net',
2914 
        'reg08_rd' => 'from_register15_data_out_net_x0',
2915 
        'reg08_rv' => 'from_register16_data_out_net_x0',
2916 
        'reg08_td' => 'reg08_td_net',
2917 
        'reg08_tv' => 'reg08_tv_net',
2918 
        'reg09_rd' => 'from_register17_data_out_net_x0',
2919 
        'reg09_rv' => 'from_register18_data_out_net_x0',
2920 
        'reg09_td' => 'reg09_td_net',
2921 
        'reg09_tv' => 'reg09_tv_net',
2922 
        'reg10_rd' => 'from_register19_data_out_net_x0',
2923 
        'reg10_rv' => 'from_register20_data_out_net_x0',
2924 
        'reg10_td' => 'reg10_td_net',
2925 
        'reg10_tv' => 'reg10_tv_net',
2926 
        'reg11_rd' => 'from_register21_data_out_net_x0',
2927 
        'reg11_rv' => 'from_register22_data_out_net_x0',
2928 
        'reg11_td' => 'reg11_td_net',
2929 
        'reg11_tv' => 'reg11_tv_net',
2930 
        'reg12_rd' => 'from_register23_data_out_net_x0',
2931 
        'reg12_rv' => 'from_register24_data_out_net_x0',
2932 
        'reg12_td' => 'reg12_td_net',
2933 
        'reg12_tv' => 'reg12_tv_net',
2934 
        'reg13_rd' => 'from_register25_data_out_net_x0',
2935 
        'reg13_rv' => 'from_register26_data_out_net_x0',
2936 
        'reg13_td' => 'reg13_td_net',
2937 
        'reg13_tv' => 'reg13_tv_net',
2938 
        'reg14_rd' => 'from_register27_data_out_net_x0',
2939 
        'reg14_rv' => 'from_register28_data_out_net_x0',
2940 
        'reg14_td' => 'reg14_td_net',
2941 
        'reg14_tv' => 'reg14_tv_net',
2942 
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2943 
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2944 
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11468 
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11469 
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11470 
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11471 
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11472 
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11473 
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11474 
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11475 
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11476 
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11477 
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11478 
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11479 
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11480 
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11481 
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11482 
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11483 
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11484 
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11485 
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11486 
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11487 
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11488 
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11489 
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11490 
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11491 
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11492 
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11493 
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11494 
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11495 
              'is_floating_block' => 1,
11496 
              'must_be_hdl_vector' => 1,
11497 
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11498 
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11499 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11500 
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11501 
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11502 
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11503 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11504 
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11505 
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11506 
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11507 
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11508 
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11509 
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11510 
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11511 
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11512 
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11513 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11514 
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11515 
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11516 
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11517 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11518 
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11519 
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11520 
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11521 
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11522 
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11523 
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11524 
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11525 
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11526 
              'port_id' => '1',
11527 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11528 
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11529 
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11530 
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11531 
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11532 
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11533 
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11534 
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11535 
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11536 
      'entityName' => 'x_x32',
11537 
    },
11538 
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11539 
}

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