OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis_com.xilinx.sysgen.netlister.CfWriter] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0,
4 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
5 
    'Impl_file' => 'ISE Defaults',
6 
    'Impl_file_sgadvanced' => '',
7 
    'Synth_file' => 'XST Defaults',
8 
    'Synth_file_sgadvanced' => '',
9 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
10 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
11 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
12 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
13 
    'base_system_period_hardware' => 5,
14 
    'base_system_period_simulink' => '8e-009',
15 
    'block_icon_display' => 'Default',
16 
    'block_type' => 'sysgen',
17 
    'block_version' => '',
18 
    'ce_clr' => 0,
19 
    'clkWrapper' => 'inout_logic_cw',
20 
    'clkWrapperFile' => 'inout_logic_cw.vhd',
21 
    'clock_loc' => '',
22 
    'clock_wrapper' => 'Clock Enables',
23 
    'clock_wrapper_sgadvanced' => '',
24 
    'compilation' => 'NGC Netlist',
25 
    'compilation_lut' => {
26 
      'keys' => [
27 
        'HDL Netlist',
28 
        'Bitstream',
29 
        'NGC Netlist',
30 
      ],
31 
      'values' => [
32 
        'target1',
33 
        'target2',
34 
        'target3',
35 
      ],
36 
    },
37 
    'compilation_target' => 'NGC Netlist',
38 
    'core_generation' => 1,
39 
    'core_generation_sgadvanced' => '',
40 
    'core_is_deployed' => 0,
41 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c00613f6911dfdaa6',
42 
    'coregen_part_family' => 'virtex6',
43 
    'createTestbench' => 0,
44 
    'create_interface_document' => 'off',
45 
    'dbl_ovrd' => -1,
46 
    'dbl_ovrd_sgadvanced' => '',
47 
    'dcm_info' => {},
48 
    'dcm_input_clock_period' => 5,
49 
    'deprecated_control' => 'off',
50 
    'deprecated_control_sgadvanced' => '',
51 
    'design' => 'inout_logic',
52 
    'designFile' => 'inout_logic.vhd',
53 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\pcie-v6-ml605_ISE12_OpenCores\\MySysGen\\PCIe_UserLogic_00.mdl',
54 
    'device' => 'xc6vlx240t-3ff784',
55 
    'device_speed' => -3,
56 
    'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
57 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
58 
    'entityNamingInstrs' => {
59 
      'nameMap' => undef,
60 
      'namesAlreadyUsed' => {
61 
        'default_clock_driver' => 1,
62 
        'inout_logic_cw' => 1,
63 
      },
64 
    },
65 
    'eval_field' => 0,
66 
    'fileAttributes' => {
67 
      'nonleaf_results.vhd' => { 'producer' => 'nonleafNetlister', },
68 
    },
69 
    'files' => [
70 
      'xlpersistentdff.ngc',
71 
      'synopsis',
72 
      'inout_logic.vhd',
73 
      'xlpersistentdff.ngc',
74 
      'inout_logic_cw.vhd',
75 
      'inout_logic_cw.ucf',
76 
      'inout_logic_cw.xcf',
77 
      'inout_logic_cw.sdc',
78 
    ],
79 
    'fxdptinstalled' => 1,
80 
    'generateUsing71FrontEnd' => 1,
81 
    'generating_island_subsystem_handle' => 4.0009765625,
82 
    'generating_subsystem_handle' => 4.0009765625,
83 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
84 
    'has_advanced_control' => 0,
85 
    'hdlDir' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl',
86 
    'hdlKind' => 'vhdl',
87 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
88 
    'impl_file' => 'ISE Defaults*',
89 
    'incr_netlist' => 'off',
90 
    'incr_netlist_sgadvanced' => '',
91 
    'infoedit' => ' System Generator',
92 
    'isCombinatorial' => 1,
93 
    'isdeployed' => 0,
94 
    'ise_version' => '12.3i',
95 
    'master_sysgen_token_handle' => 5.0009765625,
96 
    'matlab' => 'C:/Programmi/MATLAB/R2010a',
97 
    'matlab_fixedpoint' => 1,
98 
    'mdlHandle' => 3.0009765625,
99 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
100 
    'modelDiagnostics' => [
101 
      {
102 
        'count' => 339,
103 
        'isMask' => 0,
104 
        'type' => 'PCIe_UserLogic_00 Total blocks',
105 
      },
106 
      {
107 
        'count' => 4,
108 
        'isMask' => 0,
109 
        'type' => 'DiscretePulseGenerator',
110 
      },
111 
      {
112 
        'count' => 327,
113 
        'isMask' => 0,
114 
        'type' => 'S-Function',
115 
      },
116 
      {
117 
        'count' => 4,
118 
        'isMask' => 0,
119 
        'type' => 'SubSystem',
120 
      },
121 
      {
122 
        'count' => 4,
123 
        'isMask' => 0,
124 
        'type' => 'Terminator',
125 
      },
126 
      {
127 
        'count' => 23,
128 
        'isMask' => 1,
129 
        'type' => 'Xilinx Constant Block Block',
130 
      },
131 
      {
132 
        'count' => 1,
133 
        'isMask' => 1,
134 
        'type' => 'Xilinx Counter Block',
135 
      },
136 
      {
137 
        'count' => 44,
138 
        'isMask' => 1,
139 
        'type' => 'Xilinx Gateway In Block',
140 
      },
141 
      {
142 
        'count' => 39,
143 
        'isMask' => 1,
144 
        'type' => 'Xilinx Gateway Out Block',
145 
      },
146 
      {
147 
        'count' => 2,
148 
        'isMask' => 1,
149 
        'type' => 'Xilinx Inverter Block',
150 
      },
151 
      {
152 
        'count' => 1,
153 
        'isMask' => 1,
154 
        'type' => 'Xilinx Logical Block Block',
155 
      },
156 
      {
157 
        'count' => 78,
158 
        'isMask' => 1,
159 
        'type' => 'Xilinx Register Block',
160 
      },
161 
      {
162 
        'count' => 62,
163 
        'isMask' => 1,
164 
        'type' => 'Xilinx Shared Memory Based From Register Block',
165 
      },
166 
      {
167 
        'count' => 62,
168 
        'isMask' => 1,
169 
        'type' => 'Xilinx Shared Memory Based To Register Block',
170 
      },
171 
      {
172 
        'count' => 1,
173 
        'isMask' => 1,
174 
        'type' => 'Xilinx Subsystem Generator Block',
175 
      },
176 
      {
177 
        'count' => 2,
178 
        'isMask' => 1,
179 
        'type' => 'Xilinx System Generator Block',
180 
      },
181 
      {
182 
        'count' => 14,
183 
        'isMask' => 1,
184 
        'type' => 'Xilinx Type Converter Block',
185 
      },
186 
    ],
187 
    'model_globals_initialized' => 1,
188 
    'model_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
189 
    'myxilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
190 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
191 
    'ngc_config' => {
192 
      'include_cf' => 1,
193 
      'include_clockwrapper' => 1,
194 
    },
195 
    'ngc_files' => [ 'xlpersistentdff.ngc', ],
196 
    'num_sim_cycles' => 1250000000,
197 
    'package' => 'ff784',
198 
    'part' => 'xc6vlx240t',
199 
    'partFamily' => 'virtex6',
200 
    'port_data_types_enabled' => 1,
201 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
202 
    'preserve_hierarchy' => 0,
203 
    'proj_type' => 'Project Navigator',
204 
    'proj_type_sgadvanced' => '',
205 
    'run_coregen' => 'off',
206 
    'run_coregen_sgadvanced' => '',
207 
    'sample_time_colors_enabled' => 1,
208 
    'sampletimecolors' => 1,
209 
    'sdcFile' => 'inout_logic_cw.sdc',
210 
    'settings_fcn' => 'xlngcsettings',
211 
    'sg_blockgui_xml' => '',
212 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
213 
    'sg_list_contents' => '',
214 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
215 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
216 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
217 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
218 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
219 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
220 
fprintf(\'\',\'COMMENT: end icon graphics\');
221 
fprintf(\'\',\'COMMENT: begin icon text\');
222 
fprintf(\'\',\'COMMENT: end icon text\');',
223 
    'sg_version' => '',
224 
    'sggui_pos' => '-1,-1,-1,-1',
225 
    'simulation_island_subsystem_handle' => 4.0009765625,
226 
    'simulinkName' => 'parking_lot',
227 
    'simulink_accelerator_running' => 0,
228 
    'simulink_debugger_running' => 0,
229 
    'simulink_period' => '8e-009',
230 
    'speed' => -3,
231 
    'synth_file' => 'XST Defaults*',
232 
    'synthesisTool' => 'XST',
233 
    'synthesis_language' => 'vhdl',
234 
    'synthesis_tool' => 'XST',
235 
    'synthesis_tool_sgadvanced' => '',
236 
    'sysclk_period' => 5,
237 
    'sysgen' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
238 
    'sysgenRoot' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
239 
    'sysgenTokenSettings' => {
240 
      'Impl_file' => 'ISE Defaults',
241 
      'Impl_file_sgadvanced' => '',
242 
      'Synth_file' => 'XST Defaults',
243 
      'Synth_file_sgadvanced' => '',
244 
      'base_system_period_hardware' => 5,
245 
      'base_system_period_simulink' => '8e-009',
246 
      'block_icon_display' => 'Default',
247 
      'block_type' => 'sysgen',
248 
      'block_version' => '',
249 
      'ce_clr' => 0,
250 
      'clock_loc' => '',
251 
      'clock_wrapper' => 'Clock Enables',
252 
      'clock_wrapper_sgadvanced' => '',
253 
      'compilation' => 'NGC Netlist',
254 
      'compilation_lut' => {
255 
        'keys' => [
256 
          'HDL Netlist',
257 
          'Bitstream',
258 
          'NGC Netlist',
259 
        ],
260 
        'values' => [
261 
          'target1',
262 
          'target2',
263 
          'target3',
264 
        ],
265 
      },
266 
      'core_generation' => 1,
267 
      'core_generation_sgadvanced' => '',
268 
      'coregen_part_family' => 'virtex6',
269 
      'create_interface_document' => 'off',
270 
      'dbl_ovrd' => -1,
271 
      'dbl_ovrd_sgadvanced' => '',
272 
      'dcm_input_clock_period' => 5,
273 
      'deprecated_control' => 'off',
274 
      'deprecated_control_sgadvanced' => '',
275 
      'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
276 
      'eval_field' => 0,
277 
      'has_advanced_control' => 0,
278 
      'impl_file' => 'ISE Defaults*',
279 
      'incr_netlist' => 'off',
280 
      'incr_netlist_sgadvanced' => '',
281 
      'infoedit' => ' System Generator',
282 
      'master_sysgen_token_handle' => 5.0009765625,
283 
      'ngc_config' => {
284 
        'include_cf' => 1,
285 
        'include_clockwrapper' => 1,
286 
      },
287 
      'package' => 'ff784',
288 
      'part' => 'xc6vlx240t',
289 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
290 
      'preserve_hierarchy' => 0,
291 
      'proj_type' => 'Project Navigator',
292 
      'proj_type_sgadvanced' => '',
293 
      'run_coregen' => 'off',
294 
      'run_coregen_sgadvanced' => '',
295 
      'settings_fcn' => 'xlngcsettings',
296 
      'sg_blockgui_xml' => '',
297 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
298 
      'sg_list_contents' => '',
299 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
300 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
301 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
302 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
303 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
304 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
305 
fprintf(\'\',\'COMMENT: end icon graphics\');
306 
fprintf(\'\',\'COMMENT: begin icon text\');
307 
fprintf(\'\',\'COMMENT: end icon text\');',
308 
      'sggui_pos' => '-1,-1,-1,-1',
309 
      'simulation_island_subsystem_handle' => 4.0009765625,
310 
      'simulink_period' => '8e-009',
311 
      'speed' => -3,
312 
      'synth_file' => 'XST Defaults*',
313 
      'synthesis_language' => 'vhdl',
314 
      'synthesis_tool' => 'XST',
315 
      'synthesis_tool_sgadvanced' => '',
316 
      'sysclk_period' => 5,
317 
      'testbench' => 0,
318 
      'testbench_sgadvanced' => '',
319 
      'trim_vbits' => 1,
320 
      'trim_vbits_sgadvanced' => '',
321 
      'xilinx_device' => 'xc6vlx240t-3ff784',
322 
      'xilinxfamily' => 'virtex6',
323 
    },
324 
    'sysgen_Root' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
325 
    'systemClockPeriod' => 5,
326 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
327 
    'testbench' => 0,
328 
    'testbench_sgadvanced' => '',
329 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/sysgen',
330 
    'trim_vbits' => 1,
331 
    'trim_vbits_sgadvanced' => '',
332 
    'ucfFile' => 'inout_logic_cw.ucf',
333 
    'use_ce_syn_keep' => 1,
334 
    'use_strict_names' => 1,
335 
    'user_tips_enabled' => 0,
336 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
337 
    'using71Netlister' => 1,
338 
    'verilog_files' => [
339 
      'conv_pkg.v',
340 
      'synth_reg.v',
341 
      'synth_reg_w_init.v',
342 
      'convert_type.v',
343 
    ],
344 
    'version' => '',
345 
    'vhdl_files' => [
346 
      'conv_pkg.vhd',
347 
      'synth_reg.vhd',
348 
      'synth_reg_w_init.vhd',
349 
    ],
350 
    'vsimtime' => '6875000275.000000 ns',
351 
    'xcfFile' => 'inout_logic_cw.xcf',
352 
    'xilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
353 
    'xilinx_device' => 'xc6vlx240t-3ff784',
354 
    'xilinx_family' => 'virtex6',
355 
    'xilinx_package' => 'ff784',
356 
    'xilinx_part' => 'xc6vlx240t',
357 
    'xilinxdevice' => 'xc6vlx240t-3ff784',
358 
    'xilinxfamily' => 'virtex6',
359 
    'xilinxpart' => 'xc6vlx240t',
360 
  },
361 
  'entityName' => '',
362 
  'nets' => {
363 
    '.clk' => {
364 
      'hdlType' => 'std_logic',
365 
      'width' => 1,
366 
    },
367 
    '.debug_in_1i' => {
368 
      'hdlType' => 'std_logic_vector(31 downto 0)',
369 
      'width' => 32,
370 
    },
371 
    '.debug_in_2i' => {
372 
      'hdlType' => 'std_logic_vector(31 downto 0)',
373 
      'width' => 32,
374 
    },
375 
    '.debug_in_3i' => {
376 
      'hdlType' => 'std_logic_vector(31 downto 0)',
377 
      'width' => 32,
378 
    },
379 
    '.debug_in_4i' => {
380 
      'hdlType' => 'std_logic_vector(31 downto 0)',
381 
      'width' => 32,
382 
    },
383 
    '.dma_host2board_busy' => {
384 
      'hdlType' => 'std_logic',
385 
      'width' => 1,
386 
    },
387 
    '.dma_host2board_done' => {
388 
      'hdlType' => 'std_logic',
389 
      'width' => 1,
390 
    },
391 
    '.reg01_td' => {
392 
      'hdlType' => 'std_logic_vector(31 downto 0)',
393 
      'width' => 32,
394 
    },
395 
    '.reg01_tv' => {
396 
      'hdlType' => 'std_logic',
397 
      'width' => 1,
398 
    },
399 
    '.reg02_td' => {
400 
      'hdlType' => 'std_logic_vector(31 downto 0)',
401 
      'width' => 32,
402 
    },
403 
    '.reg02_tv' => {
404 
      'hdlType' => 'std_logic',
405 
      'width' => 1,
406 
    },
407 
    '.reg03_td' => {
408 
      'hdlType' => 'std_logic_vector(31 downto 0)',
409 
      'width' => 32,
410 
    },
411 
    '.reg03_tv' => {
412 
      'hdlType' => 'std_logic',
413 
      'width' => 1,
414 
    },
415 
    '.reg04_td' => {
416 
      'hdlType' => 'std_logic_vector(31 downto 0)',
417 
      'width' => 32,
418 
    },
419 
    '.reg04_tv' => {
420 
      'hdlType' => 'std_logic',
421 
      'width' => 1,
422 
    },
423 
    '.reg05_td' => {
424 
      'hdlType' => 'std_logic_vector(31 downto 0)',
425 
      'width' => 32,
426 
    },
427 
    '.reg05_tv' => {
428 
      'hdlType' => 'std_logic',
429 
      'width' => 1,
430 
    },
431 
    '.reg06_td' => {
432 
      'hdlType' => 'std_logic_vector(31 downto 0)',
433 
      'width' => 32,
434 
    },
435 
    '.reg06_tv' => {
436 
      'hdlType' => 'std_logic',
437 
      'width' => 1,
438 
    },
439 
    '.reg07_td' => {
440 
      'hdlType' => 'std_logic_vector(31 downto 0)',
441 
      'width' => 32,
442 
    },
443 
    '.reg07_tv' => {
444 
      'hdlType' => 'std_logic',
445 
      'width' => 1,
446 
    },
447 
    '.reg08_td' => {
448 
      'hdlType' => 'std_logic_vector(31 downto 0)',
449 
      'width' => 32,
450 
    },
451 
    '.reg08_tv' => {
452 
      'hdlType' => 'std_logic',
453 
      'width' => 1,
454 
    },
455 
    '.reg09_td' => {
456 
      'hdlType' => 'std_logic_vector(31 downto 0)',
457 
      'width' => 32,
458 
    },
459 
    '.reg09_tv' => {
460 
      'hdlType' => 'std_logic',
461 
      'width' => 1,
462 
    },
463 
    '.reg10_td' => {
464 
      'hdlType' => 'std_logic_vector(31 downto 0)',
465 
      'width' => 32,
466 
    },
467 
    '.reg10_tv' => {
468 
      'hdlType' => 'std_logic',
469 
      'width' => 1,
470 
    },
471 
    '.reg11_td' => {
472 
      'hdlType' => 'std_logic_vector(31 downto 0)',
473 
      'width' => 32,
474 
    },
475 
    '.reg11_tv' => {
476 
      'hdlType' => 'std_logic',
477 
      'width' => 1,
478 
    },
479 
    '.reg12_td' => {
480 
      'hdlType' => 'std_logic_vector(31 downto 0)',
481 
      'width' => 32,
482 
    },
483 
    '.reg12_tv' => {
484 
      'hdlType' => 'std_logic',
485 
      'width' => 1,
486 
    },
487 
    '.reg13_td' => {
488 
      'hdlType' => 'std_logic_vector(31 downto 0)',
489 
      'width' => 32,
490 
    },
491 
    '.reg13_tv' => {
492 
      'hdlType' => 'std_logic',
493 
      'width' => 1,
494 
    },
495 
    '.reg14_td' => {
496 
      'hdlType' => 'std_logic_vector(31 downto 0)',
497 
      'width' => 32,
498 
    },
499 
    '.reg14_tv' => {
500 
      'hdlType' => 'std_logic',
501 
      'width' => 1,
502 
    },
503 
    'from_register1.data_out' => {
504 
      'hdlType' => 'std_logic',
505 
      'width' => 1,
506 
    },
507 
    'from_register10.data_out' => {
508 
      'hdlType' => 'std_logic_vector(31 downto 0)',
509 
      'width' => 32,
510 
    },
511 
    'from_register11.data_out' => {
512 
      'hdlType' => 'std_logic_vector(31 downto 0)',
513 
      'width' => 32,
514 
    },
515 
    'from_register12.data_out' => {
516 
      'hdlType' => 'std_logic',
517 
      'width' => 1,
518 
    },
519 
    'from_register13.data_out' => {
520 
      'hdlType' => 'std_logic_vector(31 downto 0)',
521 
      'width' => 32,
522 
    },
523 
    'from_register14.data_out' => {
524 
      'hdlType' => 'std_logic',
525 
      'width' => 1,
526 
    },
527 
    'from_register15.data_out' => {
528 
      'hdlType' => 'std_logic_vector(31 downto 0)',
529 
      'width' => 32,
530 
    },
531 
    'from_register16.data_out' => {
532 
      'hdlType' => 'std_logic',
533 
      'width' => 1,
534 
    },
535 
    'from_register17.data_out' => {
536 
      'hdlType' => 'std_logic_vector(31 downto 0)',
537 
      'width' => 32,
538 
    },
539 
    'from_register18.data_out' => {
540 
      'hdlType' => 'std_logic',
541 
      'width' => 1,
542 
    },
543 
    'from_register19.data_out' => {
544 
      'hdlType' => 'std_logic_vector(31 downto 0)',
545 
      'width' => 32,
546 
    },
547 
    'from_register2.data_out' => {
548 
      'hdlType' => 'std_logic',
549 
      'width' => 1,
550 
    },
551 
    'from_register20.data_out' => {
552 
      'hdlType' => 'std_logic',
553 
      'width' => 1,
554 
    },
555 
    'from_register21.data_out' => {
556 
      'hdlType' => 'std_logic_vector(31 downto 0)',
557 
      'width' => 32,
558 
    },
559 
    'from_register22.data_out' => {
560 
      'hdlType' => 'std_logic',
561 
      'width' => 1,
562 
    },
563 
    'from_register23.data_out' => {
564 
      'hdlType' => 'std_logic_vector(31 downto 0)',
565 
      'width' => 32,
566 
    },
567 
    'from_register24.data_out' => {
568 
      'hdlType' => 'std_logic',
569 
      'width' => 1,
570 
    },
571 
    'from_register25.data_out' => {
572 
      'hdlType' => 'std_logic_vector(31 downto 0)',
573 
      'width' => 32,
574 
    },
575 
    'from_register26.data_out' => {
576 
      'hdlType' => 'std_logic',
577 
      'width' => 1,
578 
    },
579 
    'from_register27.data_out' => {
580 
      'hdlType' => 'std_logic_vector(31 downto 0)',
581 
      'width' => 32,
582 
    },
583 
    'from_register28.data_out' => {
584 
      'hdlType' => 'std_logic',
585 
      'width' => 1,
586 
    },
587 
    'from_register3.data_out' => {
588 
      'hdlType' => 'std_logic_vector(31 downto 0)',
589 
      'width' => 32,
590 
    },
591 
    'from_register4.data_out' => {
592 
      'hdlType' => 'std_logic',
593 
      'width' => 1,
594 
    },
595 
    'from_register5.data_out' => {
596 
      'hdlType' => 'std_logic_vector(31 downto 0)',
597 
      'width' => 32,
598 
    },
599 
    'from_register6.data_out' => {
600 
      'hdlType' => 'std_logic',
601 
      'width' => 1,
602 
    },
603 
    'from_register7.data_out' => {
604 
      'hdlType' => 'std_logic_vector(31 downto 0)',
605 
      'width' => 32,
606 
    },
607 
    'from_register8.data_out' => {
608 
      'hdlType' => 'std_logic_vector(31 downto 0)',
609 
      'width' => 32,
610 
    },
611 
    'from_register9.data_out' => {
612 
      'hdlType' => 'std_logic',
613 
      'width' => 1,
614 
    },
615 
    'sysgen_dut.reg01_rd' => {
616 
      'hdlType' => 'std_logic_vector(31 downto 0)',
617 
      'width' => 32,
618 
    },
619 
    'sysgen_dut.reg01_rv' => {
620 
      'hdlType' => 'std_logic',
621 
      'width' => 1,
622 
    },
623 
    'sysgen_dut.reg02_rd' => {
624 
      'hdlType' => 'std_logic_vector(31 downto 0)',
625 
      'width' => 32,
626 
    },
627 
    'sysgen_dut.reg02_rv' => {
628 
      'hdlType' => 'std_logic',
629 
      'width' => 1,
630 
    },
631 
    'sysgen_dut.reg03_rd' => {
632 
      'hdlType' => 'std_logic_vector(31 downto 0)',
633 
      'width' => 32,
634 
    },
635 
    'sysgen_dut.reg03_rv' => {
636 
      'hdlType' => 'std_logic',
637 
      'width' => 1,
638 
    },
639 
    'sysgen_dut.reg04_rd' => {
640 
      'hdlType' => 'std_logic_vector(31 downto 0)',
641 
      'width' => 32,
642 
    },
643 
    'sysgen_dut.reg04_rv' => {
644 
      'hdlType' => 'std_logic',
645 
      'width' => 1,
646 
    },
647 
    'sysgen_dut.reg05_rd' => {
648 
      'hdlType' => 'std_logic_vector(31 downto 0)',
649 
      'width' => 32,
650 
    },
651 
    'sysgen_dut.reg05_rv' => {
652 
      'hdlType' => 'std_logic',
653 
      'width' => 1,
654 
    },
655 
    'sysgen_dut.reg06_rd' => {
656 
      'hdlType' => 'std_logic_vector(31 downto 0)',
657 
      'width' => 32,
658 
    },
659 
    'sysgen_dut.reg06_rv' => {
660 
      'hdlType' => 'std_logic',
661 
      'width' => 1,
662 
    },
663 
    'sysgen_dut.reg07_rd' => {
664 
      'hdlType' => 'std_logic_vector(31 downto 0)',
665 
      'width' => 32,
666 
    },
667 
    'sysgen_dut.reg07_rv' => {
668 
      'hdlType' => 'std_logic',
669 
      'width' => 1,
670 
    },
671 
    'sysgen_dut.reg08_rd' => {
672 
      'hdlType' => 'std_logic_vector(31 downto 0)',
673 
      'width' => 32,
674 
    },
675 
    'sysgen_dut.reg08_rv' => {
676 
      'hdlType' => 'std_logic',
677 
      'width' => 1,
678 
    },
679 
    'sysgen_dut.reg09_rd' => {
680 
      'hdlType' => 'std_logic_vector(31 downto 0)',
681 
      'width' => 32,
682 
    },
683 
    'sysgen_dut.reg09_rv' => {
684 
      'hdlType' => 'std_logic',
685 
      'width' => 1,
686 
    },
687 
    'sysgen_dut.reg10_rd' => {
688 
      'hdlType' => 'std_logic_vector(31 downto 0)',
689 
      'width' => 32,
690 
    },
691 
    'sysgen_dut.reg10_rv' => {
692 
      'hdlType' => 'std_logic',
693 
      'width' => 1,
694 
    },
695 
    'sysgen_dut.reg11_rd' => {
696 
      'hdlType' => 'std_logic_vector(31 downto 0)',
697 
      'width' => 32,
698 
    },
699 
    'sysgen_dut.reg11_rv' => {
700 
      'hdlType' => 'std_logic',
701 
      'width' => 1,
702 
    },
703 
    'sysgen_dut.reg12_rd' => {
704 
      'hdlType' => 'std_logic_vector(31 downto 0)',
705 
      'width' => 32,
706 
    },
707 
    'sysgen_dut.reg12_rv' => {
708 
      'hdlType' => 'std_logic',
709 
      'width' => 1,
710 
    },
711 
    'sysgen_dut.reg13_rd' => {
712 
      'hdlType' => 'std_logic_vector(31 downto 0)',
713 
      'width' => 32,
714 
    },
715 
    'sysgen_dut.reg13_rv' => {
716 
      'hdlType' => 'std_logic',
717 
      'width' => 1,
718 
    },
719 
    'sysgen_dut.reg14_rd' => {
720 
      'hdlType' => 'std_logic_vector(31 downto 0)',
721 
      'width' => 32,
722 
    },
723 
    'sysgen_dut.reg14_rv' => {
724 
      'hdlType' => 'std_logic',
725 
      'width' => 1,
726 
    },
727 
    'sysgen_dut.to_register10_ce' => {
728 
      'hdlType' => 'std_logic',
729 
      'width' => 1,
730 
    },
731 
    'sysgen_dut.to_register10_clk' => {
732 
      'hdlType' => 'std_logic',
733 
      'width' => 1,
734 
    },
735 
    'sysgen_dut.to_register10_clr' => {
736 
      'hdlType' => 'std_logic',
737 
      'width' => 1,
738 
    },
739 
    'sysgen_dut.to_register10_data_in' => {
740 
      'hdlType' => 'std_logic',
741 
      'width' => 1,
742 
    },
743 
    'sysgen_dut.to_register10_en' => {
744 
      'hdlType' => 'std_logic',
745 
      'width' => 1,
746 
    },
747 
    'sysgen_dut.to_register11_ce' => {
748 
      'hdlType' => 'std_logic',
749 
      'width' => 1,
750 
    },
751 
    'sysgen_dut.to_register11_clk' => {
752 
      'hdlType' => 'std_logic',
753 
      'width' => 1,
754 
    },
755 
    'sysgen_dut.to_register11_clr' => {
756 
      'hdlType' => 'std_logic',
757 
      'width' => 1,
758 
    },
759 
    'sysgen_dut.to_register11_data_in' => {
760 
      'hdlType' => 'std_logic_vector(31 downto 0)',
761 
      'width' => 32,
762 
    },
763 
    'sysgen_dut.to_register11_en' => {
764 
      'hdlType' => 'std_logic',
765 
      'width' => 1,
766 
    },
767 
    'sysgen_dut.to_register12_ce' => {
768 
      'hdlType' => 'std_logic',
769 
      'width' => 1,
770 
    },
771 
    'sysgen_dut.to_register12_clk' => {
772 
      'hdlType' => 'std_logic',
773 
      'width' => 1,
774 
    },
775 
    'sysgen_dut.to_register12_clr' => {
776 
      'hdlType' => 'std_logic',
777 
      'width' => 1,
778 
    },
779 
    'sysgen_dut.to_register12_data_in' => {
780 
      'hdlType' => 'std_logic',
781 
      'width' => 1,
782 
    },
783 
    'sysgen_dut.to_register12_en' => {
784 
      'hdlType' => 'std_logic',
785 
      'width' => 1,
786 
    },
787 
    'sysgen_dut.to_register13_ce' => {
788 
      'hdlType' => 'std_logic',
789 
      'width' => 1,
790 
    },
791 
    'sysgen_dut.to_register13_clk' => {
792 
      'hdlType' => 'std_logic',
793 
      'width' => 1,
794 
    },
795 
    'sysgen_dut.to_register13_clr' => {
796 
      'hdlType' => 'std_logic',
797 
      'width' => 1,
798 
    },
799 
    'sysgen_dut.to_register13_data_in' => {
800 
      'hdlType' => 'std_logic_vector(31 downto 0)',
801 
      'width' => 32,
802 
    },
803 
    'sysgen_dut.to_register13_en' => {
804 
      'hdlType' => 'std_logic',
805 
      'width' => 1,
806 
    },
807 
    'sysgen_dut.to_register14_ce' => {
808 
      'hdlType' => 'std_logic',
809 
      'width' => 1,
810 
    },
811 
    'sysgen_dut.to_register14_clk' => {
812 
      'hdlType' => 'std_logic',
813 
      'width' => 1,
814 
    },
815 
    'sysgen_dut.to_register14_clr' => {
816 
      'hdlType' => 'std_logic',
817 
      'width' => 1,
818 
    },
819 
    'sysgen_dut.to_register14_data_in' => {
820 
      'hdlType' => 'std_logic',
821 
      'width' => 1,
822 
    },
823 
    'sysgen_dut.to_register14_en' => {
824 
      'hdlType' => 'std_logic',
825 
      'width' => 1,
826 
    },
827 
    'sysgen_dut.to_register15_ce' => {
828 
      'hdlType' => 'std_logic',
829 
      'width' => 1,
830 
    },
831 
    'sysgen_dut.to_register15_clk' => {
832 
      'hdlType' => 'std_logic',
833 
      'width' => 1,
834 
    },
835 
    'sysgen_dut.to_register15_clr' => {
836 
      'hdlType' => 'std_logic',
837 
      'width' => 1,
838 
    },
839 
    'sysgen_dut.to_register15_data_in' => {
840 
      'hdlType' => 'std_logic_vector(31 downto 0)',
841 
      'width' => 32,
842 
    },
843 
    'sysgen_dut.to_register15_en' => {
844 
      'hdlType' => 'std_logic',
845 
      'width' => 1,
846 
    },
847 
    'sysgen_dut.to_register16_ce' => {
848 
      'hdlType' => 'std_logic',
849 
      'width' => 1,
850 
    },
851 
    'sysgen_dut.to_register16_clk' => {
852 
      'hdlType' => 'std_logic',
853 
      'width' => 1,
854 
    },
855 
    'sysgen_dut.to_register16_clr' => {
856 
      'hdlType' => 'std_logic',
857 
      'width' => 1,
858 
    },
859 
    'sysgen_dut.to_register16_data_in' => {
860 
      'hdlType' => 'std_logic',
861 
      'width' => 1,
862 
    },
863 
    'sysgen_dut.to_register16_en' => {
864 
      'hdlType' => 'std_logic',
865 
      'width' => 1,
866 
    },
867 
    'sysgen_dut.to_register17_ce' => {
868 
      'hdlType' => 'std_logic',
869 
      'width' => 1,
870 
    },
871 
    'sysgen_dut.to_register17_clk' => {
872 
      'hdlType' => 'std_logic',
873 
      'width' => 1,
874 
    },
875 
    'sysgen_dut.to_register17_clr' => {
876 
      'hdlType' => 'std_logic',
877 
      'width' => 1,
878 
    },
879 
    'sysgen_dut.to_register17_data_in' => {
880 
      'hdlType' => 'std_logic_vector(31 downto 0)',
881 
      'width' => 32,
882 
    },
883 
    'sysgen_dut.to_register17_en' => {
884 
      'hdlType' => 'std_logic',
885 
      'width' => 1,
886 
    },
887 
    'sysgen_dut.to_register18_ce' => {
888 
      'hdlType' => 'std_logic',
889 
      'width' => 1,
890 
    },
891 
    'sysgen_dut.to_register18_clk' => {
892 
      'hdlType' => 'std_logic',
893 
      'width' => 1,
894 
    },
895 
    'sysgen_dut.to_register18_clr' => {
896 
      'hdlType' => 'std_logic',
897 
      'width' => 1,
898 
    },
899 
    'sysgen_dut.to_register18_data_in' => {
900 
      'hdlType' => 'std_logic',
901 
      'width' => 1,
902 
    },
903 
    'sysgen_dut.to_register18_en' => {
904 
      'hdlType' => 'std_logic',
905 
      'width' => 1,
906 
    },
907 
    'sysgen_dut.to_register19_ce' => {
908 
      'hdlType' => 'std_logic',
909 
      'width' => 1,
910 
    },
911 
    'sysgen_dut.to_register19_clk' => {
912 
      'hdlType' => 'std_logic',
913 
      'width' => 1,
914 
    },
915 
    'sysgen_dut.to_register19_clr' => {
916 
      'hdlType' => 'std_logic',
917 
      'width' => 1,
918 
    },
919 
    'sysgen_dut.to_register19_data_in' => {
920 
      'hdlType' => 'std_logic',
921 
      'width' => 1,
922 
    },
923 
    'sysgen_dut.to_register19_en' => {
924 
      'hdlType' => 'std_logic',
925 
      'width' => 1,
926 
    },
927 
    'sysgen_dut.to_register1_ce' => {
928 
      'hdlType' => 'std_logic',
929 
      'width' => 1,
930 
    },
931 
    'sysgen_dut.to_register1_clk' => {
932 
      'hdlType' => 'std_logic',
933 
      'width' => 1,
934 
    },
935 
    'sysgen_dut.to_register1_clr' => {
936 
      'hdlType' => 'std_logic',
937 
      'width' => 1,
938 
    },
939 
    'sysgen_dut.to_register1_data_in' => {
940 
      'hdlType' => 'std_logic_vector(31 downto 0)',
941 
      'width' => 32,
942 
    },
943 
    'sysgen_dut.to_register1_en' => {
944 
      'hdlType' => 'std_logic',
945 
      'width' => 1,
946 
    },
947 
    'sysgen_dut.to_register20_ce' => {
948 
      'hdlType' => 'std_logic',
949 
      'width' => 1,
950 
    },
951 
    'sysgen_dut.to_register20_clk' => {
952 
      'hdlType' => 'std_logic',
953 
      'width' => 1,
954 
    },
955 
    'sysgen_dut.to_register20_clr' => {
956 
      'hdlType' => 'std_logic',
957 
      'width' => 1,
958 
    },
959 
    'sysgen_dut.to_register20_data_in' => {
960 
      'hdlType' => 'std_logic_vector(31 downto 0)',
961 
      'width' => 32,
962 
    },
963 
    'sysgen_dut.to_register20_en' => {
964 
      'hdlType' => 'std_logic',
965 
      'width' => 1,
966 
    },
967 
    'sysgen_dut.to_register21_ce' => {
968 
      'hdlType' => 'std_logic',
969 
      'width' => 1,
970 
    },
971 
    'sysgen_dut.to_register21_clk' => {
972 
      'hdlType' => 'std_logic',
973 
      'width' => 1,
974 
    },
975 
    'sysgen_dut.to_register21_clr' => {
976 
      'hdlType' => 'std_logic',
977 
      'width' => 1,
978 
    },
979 
    'sysgen_dut.to_register21_data_in' => {
980 
      'hdlType' => 'std_logic',
981 
      'width' => 1,
982 
    },
983 
    'sysgen_dut.to_register21_en' => {
984 
      'hdlType' => 'std_logic',
985 
      'width' => 1,
986 
    },
987 
    'sysgen_dut.to_register22_ce' => {
988 
      'hdlType' => 'std_logic',
989 
      'width' => 1,
990 
    },
991 
    'sysgen_dut.to_register22_clk' => {
992 
      'hdlType' => 'std_logic',
993 
      'width' => 1,
994 
    },
995 
    'sysgen_dut.to_register22_clr' => {
996 
      'hdlType' => 'std_logic',
997 
      'width' => 1,
998 
    },
999 
    'sysgen_dut.to_register22_data_in' => {
1000 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1001 
      'width' => 32,
1002 
    },
1003 
    'sysgen_dut.to_register22_en' => {
1004 
      'hdlType' => 'std_logic',
1005 
      'width' => 1,
1006 
    },
1007 
    'sysgen_dut.to_register23_ce' => {
1008 
      'hdlType' => 'std_logic',
1009 
      'width' => 1,
1010 
    },
1011 
    'sysgen_dut.to_register23_clk' => {
1012 
      'hdlType' => 'std_logic',
1013 
      'width' => 1,
1014 
    },
1015 
    'sysgen_dut.to_register23_clr' => {
1016 
      'hdlType' => 'std_logic',
1017 
      'width' => 1,
1018 
    },
1019 
    'sysgen_dut.to_register23_data_in' => {
1020 
      'hdlType' => 'std_logic',
1021 
      'width' => 1,
1022 
    },
1023 
    'sysgen_dut.to_register23_en' => {
1024 
      'hdlType' => 'std_logic',
1025 
      'width' => 1,
1026 
    },
1027 
    'sysgen_dut.to_register24_ce' => {
1028 
      'hdlType' => 'std_logic',
1029 
      'width' => 1,
1030 
    },
1031 
    'sysgen_dut.to_register24_clk' => {
1032 
      'hdlType' => 'std_logic',
1033 
      'width' => 1,
1034 
    },
1035 
    'sysgen_dut.to_register24_clr' => {
1036 
      'hdlType' => 'std_logic',
1037 
      'width' => 1,
1038 
    },
1039 
    'sysgen_dut.to_register24_data_in' => {
1040 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1041 
      'width' => 32,
1042 
    },
1043 
    'sysgen_dut.to_register24_en' => {
1044 
      'hdlType' => 'std_logic',
1045 
      'width' => 1,
1046 
    },
1047 
    'sysgen_dut.to_register25_ce' => {
1048 
      'hdlType' => 'std_logic',
1049 
      'width' => 1,
1050 
    },
1051 
    'sysgen_dut.to_register25_clk' => {
1052 
      'hdlType' => 'std_logic',
1053 
      'width' => 1,
1054 
    },
1055 
    'sysgen_dut.to_register25_clr' => {
1056 
      'hdlType' => 'std_logic',
1057 
      'width' => 1,
1058 
    },
1059 
    'sysgen_dut.to_register25_data_in' => {
1060 
      'hdlType' => 'std_logic',
1061 
      'width' => 1,
1062 
    },
1063 
    'sysgen_dut.to_register25_en' => {
1064 
      'hdlType' => 'std_logic',
1065 
      'width' => 1,
1066 
    },
1067 
    'sysgen_dut.to_register26_ce' => {
1068 
      'hdlType' => 'std_logic',
1069 
      'width' => 1,
1070 
    },
1071 
    'sysgen_dut.to_register26_clk' => {
1072 
      'hdlType' => 'std_logic',
1073 
      'width' => 1,
1074 
    },
1075 
    'sysgen_dut.to_register26_clr' => {
1076 
      'hdlType' => 'std_logic',
1077 
      'width' => 1,
1078 
    },
1079 
    'sysgen_dut.to_register26_data_in' => {
1080 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1081 
      'width' => 32,
1082 
    },
1083 
    'sysgen_dut.to_register26_en' => {
1084 
      'hdlType' => 'std_logic',
1085 
      'width' => 1,
1086 
    },
1087 
    'sysgen_dut.to_register27_ce' => {
1088 
      'hdlType' => 'std_logic',
1089 
      'width' => 1,
1090 
    },
1091 
    'sysgen_dut.to_register27_clk' => {
1092 
      'hdlType' => 'std_logic',
1093 
      'width' => 1,
1094 
    },
1095 
    'sysgen_dut.to_register27_clr' => {
1096 
      'hdlType' => 'std_logic',
1097 
      'width' => 1,
1098 
    },
1099 
    'sysgen_dut.to_register27_data_in' => {
1100 
      'hdlType' => 'std_logic',
1101 
      'width' => 1,
1102 
    },
1103 
    'sysgen_dut.to_register27_en' => {
1104 
      'hdlType' => 'std_logic',
1105 
      'width' => 1,
1106 
    },
1107 
    'sysgen_dut.to_register28_ce' => {
1108 
      'hdlType' => 'std_logic',
1109 
      'width' => 1,
1110 
    },
1111 
    'sysgen_dut.to_register28_clk' => {
1112 
      'hdlType' => 'std_logic',
1113 
      'width' => 1,
1114 
    },
1115 
    'sysgen_dut.to_register28_clr' => {
1116 
      'hdlType' => 'std_logic',
1117 
      'width' => 1,
1118 
    },
1119 
    'sysgen_dut.to_register28_data_in' => {
1120 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1121 
      'width' => 32,
1122 
    },
1123 
    'sysgen_dut.to_register28_en' => {
1124 
      'hdlType' => 'std_logic',
1125 
      'width' => 1,
1126 
    },
1127 
    'sysgen_dut.to_register29_ce' => {
1128 
      'hdlType' => 'std_logic',
1129 
      'width' => 1,
1130 
    },
1131 
    'sysgen_dut.to_register29_clk' => {
1132 
      'hdlType' => 'std_logic',
1133 
      'width' => 1,
1134 
    },
1135 
    'sysgen_dut.to_register29_clr' => {
1136 
      'hdlType' => 'std_logic',
1137 
      'width' => 1,
1138 
    },
1139 
    'sysgen_dut.to_register29_data_in' => {
1140 
      'hdlType' => 'std_logic',
1141 
      'width' => 1,
1142 
    },
1143 
    'sysgen_dut.to_register29_en' => {
1144 
      'hdlType' => 'std_logic',
1145 
      'width' => 1,
1146 
    },
1147 
    'sysgen_dut.to_register2_ce' => {
1148 
      'hdlType' => 'std_logic',
1149 
      'width' => 1,
1150 
    },
1151 
    'sysgen_dut.to_register2_clk' => {
1152 
      'hdlType' => 'std_logic',
1153 
      'width' => 1,
1154 
    },
1155 
    'sysgen_dut.to_register2_clr' => {
1156 
      'hdlType' => 'std_logic',
1157 
      'width' => 1,
1158 
    },
1159 
    'sysgen_dut.to_register2_data_in' => {
1160 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1161 
      'width' => 32,
1162 
    },
1163 
    'sysgen_dut.to_register2_en' => {
1164 
      'hdlType' => 'std_logic',
1165 
      'width' => 1,
1166 
    },
1167 
    'sysgen_dut.to_register30_ce' => {
1168 
      'hdlType' => 'std_logic',
1169 
      'width' => 1,
1170 
    },
1171 
    'sysgen_dut.to_register30_clk' => {
1172 
      'hdlType' => 'std_logic',
1173 
      'width' => 1,
1174 
    },
1175 
    'sysgen_dut.to_register30_clr' => {
1176 
      'hdlType' => 'std_logic',
1177 
      'width' => 1,
1178 
    },
1179 
    'sysgen_dut.to_register30_data_in' => {
1180 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1181 
      'width' => 32,
1182 
    },
1183 
    'sysgen_dut.to_register30_en' => {
1184 
      'hdlType' => 'std_logic',
1185 
      'width' => 1,
1186 
    },
1187 
    'sysgen_dut.to_register31_ce' => {
1188 
      'hdlType' => 'std_logic',
1189 
      'width' => 1,
1190 
    },
1191 
    'sysgen_dut.to_register31_clk' => {
1192 
      'hdlType' => 'std_logic',
1193 
      'width' => 1,
1194 
    },
1195 
    'sysgen_dut.to_register31_clr' => {
1196 
      'hdlType' => 'std_logic',
1197 
      'width' => 1,
1198 
    },
1199 
    'sysgen_dut.to_register31_data_in' => {
1200 
      'hdlType' => 'std_logic',
1201 
      'width' => 1,
1202 
    },
1203 
    'sysgen_dut.to_register31_en' => {
1204 
      'hdlType' => 'std_logic',
1205 
      'width' => 1,
1206 
    },
1207 
    'sysgen_dut.to_register32_ce' => {
1208 
      'hdlType' => 'std_logic',
1209 
      'width' => 1,
1210 
    },
1211 
    'sysgen_dut.to_register32_clk' => {
1212 
      'hdlType' => 'std_logic',
1213 
      'width' => 1,
1214 
    },
1215 
    'sysgen_dut.to_register32_clr' => {
1216 
      'hdlType' => 'std_logic',
1217 
      'width' => 1,
1218 
    },
1219 
    'sysgen_dut.to_register32_data_in' => {
1220 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1221 
      'width' => 32,
1222 
    },
1223 
    'sysgen_dut.to_register32_en' => {
1224 
      'hdlType' => 'std_logic',
1225 
      'width' => 1,
1226 
    },
1227 
    'sysgen_dut.to_register33_ce' => {
1228 
      'hdlType' => 'std_logic',
1229 
      'width' => 1,
1230 
    },
1231 
    'sysgen_dut.to_register33_clk' => {
1232 
      'hdlType' => 'std_logic',
1233 
      'width' => 1,
1234 
    },
1235 
    'sysgen_dut.to_register33_clr' => {
1236 
      'hdlType' => 'std_logic',
1237 
      'width' => 1,
1238 
    },
1239 
    'sysgen_dut.to_register33_data_in' => {
1240 
      'hdlType' => 'std_logic',
1241 
      'width' => 1,
1242 
    },
1243 
    'sysgen_dut.to_register33_en' => {
1244 
      'hdlType' => 'std_logic',
1245 
      'width' => 1,
1246 
    },
1247 
    'sysgen_dut.to_register34_ce' => {
1248 
      'hdlType' => 'std_logic',
1249 
      'width' => 1,
1250 
    },
1251 
    'sysgen_dut.to_register34_clk' => {
1252 
      'hdlType' => 'std_logic',
1253 
      'width' => 1,
1254 
    },
1255 
    'sysgen_dut.to_register34_clr' => {
1256 
      'hdlType' => 'std_logic',
1257 
      'width' => 1,
1258 
    },
1259 
    'sysgen_dut.to_register34_data_in' => {
1260 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1261 
      'width' => 32,
1262 
    },
1263 
    'sysgen_dut.to_register34_en' => {
1264 
      'hdlType' => 'std_logic',
1265 
      'width' => 1,
1266 
    },
1267 
    'sysgen_dut.to_register3_ce' => {
1268 
      'hdlType' => 'std_logic',
1269 
      'width' => 1,
1270 
    },
1271 
    'sysgen_dut.to_register3_clk' => {
1272 
      'hdlType' => 'std_logic',
1273 
      'width' => 1,
1274 
    },
1275 
    'sysgen_dut.to_register3_clr' => {
1276 
      'hdlType' => 'std_logic',
1277 
      'width' => 1,
1278 
    },
1279 
    'sysgen_dut.to_register3_data_in' => {
1280 
      'hdlType' => 'std_logic',
1281 
      'width' => 1,
1282 
    },
1283 
    'sysgen_dut.to_register3_en' => {
1284 
      'hdlType' => 'std_logic',
1285 
      'width' => 1,
1286 
    },
1287 
    'sysgen_dut.to_register4_ce' => {
1288 
      'hdlType' => 'std_logic',
1289 
      'width' => 1,
1290 
    },
1291 
    'sysgen_dut.to_register4_clk' => {
1292 
      'hdlType' => 'std_logic',
1293 
      'width' => 1,
1294 
    },
1295 
    'sysgen_dut.to_register4_clr' => {
1296 
      'hdlType' => 'std_logic',
1297 
      'width' => 1,
1298 
    },
1299 
    'sysgen_dut.to_register4_data_in' => {
1300 
      'hdlType' => 'std_logic',
1301 
      'width' => 1,
1302 
    },
1303 
    'sysgen_dut.to_register4_en' => {
1304 
      'hdlType' => 'std_logic',
1305 
      'width' => 1,
1306 
    },
1307 
    'sysgen_dut.to_register5_ce' => {
1308 
      'hdlType' => 'std_logic',
1309 
      'width' => 1,
1310 
    },
1311 
    'sysgen_dut.to_register5_clk' => {
1312 
      'hdlType' => 'std_logic',
1313 
      'width' => 1,
1314 
    },
1315 
    'sysgen_dut.to_register5_clr' => {
1316 
      'hdlType' => 'std_logic',
1317 
      'width' => 1,
1318 
    },
1319 
    'sysgen_dut.to_register5_data_in' => {
1320 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1321 
      'width' => 32,
1322 
    },
1323 
    'sysgen_dut.to_register5_en' => {
1324 
      'hdlType' => 'std_logic',
1325 
      'width' => 1,
1326 
    },
1327 
    'sysgen_dut.to_register6_ce' => {
1328 
      'hdlType' => 'std_logic',
1329 
      'width' => 1,
1330 
    },
1331 
    'sysgen_dut.to_register6_clk' => {
1332 
      'hdlType' => 'std_logic',
1333 
      'width' => 1,
1334 
    },
1335 
    'sysgen_dut.to_register6_clr' => {
1336 
      'hdlType' => 'std_logic',
1337 
      'width' => 1,
1338 
    },
1339 
    'sysgen_dut.to_register6_data_in' => {
1340 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1341 
      'width' => 32,
1342 
    },
1343 
    'sysgen_dut.to_register6_en' => {
1344 
      'hdlType' => 'std_logic',
1345 
      'width' => 1,
1346 
    },
1347 
    'sysgen_dut.to_register7_ce' => {
1348 
      'hdlType' => 'std_logic',
1349 
      'width' => 1,
1350 
    },
1351 
    'sysgen_dut.to_register7_clk' => {
1352 
      'hdlType' => 'std_logic',
1353 
      'width' => 1,
1354 
    },
1355 
    'sysgen_dut.to_register7_clr' => {
1356 
      'hdlType' => 'std_logic',
1357 
      'width' => 1,
1358 
    },
1359 
    'sysgen_dut.to_register7_data_in' => {
1360 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1361 
      'width' => 32,
1362 
    },
1363 
    'sysgen_dut.to_register7_en' => {
1364 
      'hdlType' => 'std_logic',
1365 
      'width' => 1,
1366 
    },
1367 
    'sysgen_dut.to_register8_ce' => {
1368 
      'hdlType' => 'std_logic',
1369 
      'width' => 1,
1370 
    },
1371 
    'sysgen_dut.to_register8_clk' => {
1372 
      'hdlType' => 'std_logic',
1373 
      'width' => 1,
1374 
    },
1375 
    'sysgen_dut.to_register8_clr' => {
1376 
      'hdlType' => 'std_logic',
1377 
      'width' => 1,
1378 
    },
1379 
    'sysgen_dut.to_register8_data_in' => {
1380 
      'hdlType' => 'std_logic',
1381 
      'width' => 1,
1382 
    },
1383 
    'sysgen_dut.to_register8_en' => {
1384 
      'hdlType' => 'std_logic',
1385 
      'width' => 1,
1386 
    },
1387 
    'sysgen_dut.to_register9_ce' => {
1388 
      'hdlType' => 'std_logic',
1389 
      'width' => 1,
1390 
    },
1391 
    'sysgen_dut.to_register9_clk' => {
1392 
      'hdlType' => 'std_logic',
1393 
      'width' => 1,
1394 
    },
1395 
    'sysgen_dut.to_register9_clr' => {
1396 
      'hdlType' => 'std_logic',
1397 
      'width' => 1,
1398 
    },
1399 
    'sysgen_dut.to_register9_data_in' => {
1400 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1401 
      'width' => 32,
1402 
    },
1403 
    'sysgen_dut.to_register9_en' => {
1404 
      'hdlType' => 'std_logic',
1405 
      'width' => 1,
1406 
    },
1407 
    'to_register1.dout' => {
1408 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1409 
      'width' => 32,
1410 
    },
1411 
    'to_register10.dout' => {
1412 
      'hdlType' => 'std_logic',
1413 
      'width' => 1,
1414 
    },
1415 
    'to_register11.dout' => {
1416 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1417 
      'width' => 32,
1418 
    },
1419 
    'to_register12.dout' => {
1420 
      'hdlType' => 'std_logic',
1421 
      'width' => 1,
1422 
    },
1423 
    'to_register13.dout' => {
1424 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1425 
      'width' => 32,
1426 
    },
1427 
    'to_register14.dout' => {
1428 
      'hdlType' => 'std_logic',
1429 
      'width' => 1,
1430 
    },
1431 
    'to_register15.dout' => {
1432 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1433 
      'width' => 32,
1434 
    },
1435 
    'to_register16.dout' => {
1436 
      'hdlType' => 'std_logic',
1437 
      'width' => 1,
1438 
    },
1439 
    'to_register17.dout' => {
1440 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1441 
      'width' => 32,
1442 
    },
1443 
    'to_register18.dout' => {
1444 
      'hdlType' => 'std_logic',
1445 
      'width' => 1,
1446 
    },
1447 
    'to_register19.dout' => {
1448 
      'hdlType' => 'std_logic',
1449 
      'width' => 1,
1450 
    },
1451 
    'to_register2.dout' => {
1452 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1453 
      'width' => 32,
1454 
    },
1455 
    'to_register20.dout' => {
1456 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1457 
      'width' => 32,
1458 
    },
1459 
    'to_register21.dout' => {
1460 
      'hdlType' => 'std_logic',
1461 
      'width' => 1,
1462 
    },
1463 
    'to_register22.dout' => {
1464 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1465 
      'width' => 32,
1466 
    },
1467 
    'to_register23.dout' => {
1468 
      'hdlType' => 'std_logic',
1469 
      'width' => 1,
1470 
    },
1471 
    'to_register24.dout' => {
1472 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1473 
      'width' => 32,
1474 
    },
1475 
    'to_register25.dout' => {
1476 
      'hdlType' => 'std_logic',
1477 
      'width' => 1,
1478 
    },
1479 
    'to_register26.dout' => {
1480 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1481 
      'width' => 32,
1482 
    },
1483 
    'to_register27.dout' => {
1484 
      'hdlType' => 'std_logic',
1485 
      'width' => 1,
1486 
    },
1487 
    'to_register28.dout' => {
1488 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1489 
      'width' => 32,
1490 
    },
1491 
    'to_register29.dout' => {
1492 
      'hdlType' => 'std_logic',
1493 
      'width' => 1,
1494 
    },
1495 
    'to_register3.dout' => {
1496 
      'hdlType' => 'std_logic',
1497 
      'width' => 1,
1498 
    },
1499 
    'to_register30.dout' => {
1500 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1501 
      'width' => 32,
1502 
    },
1503 
    'to_register31.dout' => {
1504 
      'hdlType' => 'std_logic',
1505 
      'width' => 1,
1506 
    },
1507 
    'to_register32.dout' => {
1508 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1509 
      'width' => 32,
1510 
    },
1511 
    'to_register33.dout' => {
1512 
      'hdlType' => 'std_logic',
1513 
      'width' => 1,
1514 
    },
1515 
    'to_register34.dout' => {
1516 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1517 
      'width' => 32,
1518 
    },
1519 
    'to_register4.dout' => {
1520 
      'hdlType' => 'std_logic',
1521 
      'width' => 1,
1522 
    },
1523 
    'to_register5.dout' => {
1524 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1525 
      'width' => 32,
1526 
    },
1527 
    'to_register6.dout' => {
1528 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1529 
      'width' => 32,
1530 
    },
1531 
    'to_register7.dout' => {
1532 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1533 
      'width' => 32,
1534 
    },
1535 
    'to_register8.dout' => {
1536 
      'hdlType' => 'std_logic',
1537 
      'width' => 1,
1538 
    },
1539 
    'to_register9.dout' => {
1540 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1541 
      'width' => 32,
1542 
    },
1543 
  },
1544 
  'subblocks' => {
1545 
    'debug_in_1i' => {
1546 
      'connections' => { 'debug_in_1i' => '.debug_in_1i', },
1547 
      'entity' => {
1548 
        'attributes' => {
1549 
          'entityAlreadyNetlisted' => 1,
1550 
          'isGateway' => 1,
1551 
          'is_floating_block' => 1,
1552 
        },
1553 
        'entityName' => 'debug_in_1i',
1554 
        'ports' => {
1555 
          'debug_in_1i' => {
1556 
            'attributes' => {
1557 
              'bin_pt' => 0,
1558 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
1559 
              'is_floating_block' => 1,
1560 
              'is_gateway_port' => 1,
1561 
              'must_be_hdl_vector' => 1,
1562 
              'period' => 1,
1563 
              'port_id' => 0,
1564 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
1565 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
1566 
              'timingConstraint' => 'none',
1567 
              'type' => 'UFix_32_0',
1568 
            },
1569 
            'direction' => 'out',
1570 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1571 
            'width' => 32,
1572 
          },
1573 
        },
1574 
      },
1575 
      'entityName' => 'debug_in_1i',
1576 
    },
1577 
    'debug_in_2i' => {
1578 
      'connections' => { 'debug_in_2i' => '.debug_in_2i', },
1579 
      'entity' => {
1580 
        'attributes' => {
1581 
          'entityAlreadyNetlisted' => 1,
1582 
          'isGateway' => 1,
1583 
          'is_floating_block' => 1,
1584 
        },
1585 
        'entityName' => 'debug_in_2i',
1586 
        'ports' => {
1587 
          'debug_in_2i' => {
1588 
            'attributes' => {
1589 
              'bin_pt' => 0,
1590 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
1591 
              'is_floating_block' => 1,
1592 
              'is_gateway_port' => 1,
1593 
              'must_be_hdl_vector' => 1,
1594 
              'period' => 1,
1595 
              'port_id' => 0,
1596 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
1597 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
1598 
              'timingConstraint' => 'none',
1599 
              'type' => 'UFix_32_0',
1600 
            },
1601 
            'direction' => 'out',
1602 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1603 
            'width' => 32,
1604 
          },
1605 
        },
1606 
      },
1607 
      'entityName' => 'debug_in_2i',
1608 
    },
1609 
    'debug_in_3i' => {
1610 
      'connections' => { 'debug_in_3i' => '.debug_in_3i', },
1611 
      'entity' => {
1612 
        'attributes' => {
1613 
          'entityAlreadyNetlisted' => 1,
1614 
          'isGateway' => 1,
1615 
          'is_floating_block' => 1,
1616 
        },
1617 
        'entityName' => 'debug_in_3i',
1618 
        'ports' => {
1619 
          'debug_in_3i' => {
1620 
            'attributes' => {
1621 
              'bin_pt' => 0,
1622 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
1623 
              'is_floating_block' => 1,
1624 
              'is_gateway_port' => 1,
1625 
              'must_be_hdl_vector' => 1,
1626 
              'period' => 1,
1627 
              'port_id' => 0,
1628 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
1629 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
1630 
              'timingConstraint' => 'none',
1631 
              'type' => 'UFix_32_0',
1632 
            },
1633 
            'direction' => 'out',
1634 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1635 
            'width' => 32,
1636 
          },
1637 
        },
1638 
      },
1639 
      'entityName' => 'debug_in_3i',
1640 
    },
1641 
    'debug_in_4i' => {
1642 
      'connections' => { 'debug_in_4i' => '.debug_in_4i', },
1643 
      'entity' => {
1644 
        'attributes' => {
1645 
          'entityAlreadyNetlisted' => 1,
1646 
          'isGateway' => 1,
1647 
          'is_floating_block' => 1,
1648 
        },
1649 
        'entityName' => 'debug_in_4i',
1650 
        'ports' => {
1651 
          'debug_in_4i' => {
1652 
            'attributes' => {
1653 
              'bin_pt' => 0,
1654 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
1655 
              'is_floating_block' => 1,
1656 
              'is_gateway_port' => 1,
1657 
              'must_be_hdl_vector' => 1,
1658 
              'period' => 1,
1659 
              'port_id' => 0,
1660 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
1661 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
1662 
              'timingConstraint' => 'none',
1663 
              'type' => 'UFix_32_0',
1664 
            },
1665 
            'direction' => 'out',
1666 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1667 
            'width' => 32,
1668 
          },
1669 
        },
1670 
      },
1671 
      'entityName' => 'debug_in_4i',
1672 
    },
1673 
    'dma_host2board_busy' => {
1674 
      'connections' => { 'dma_host2board_busy' => '.dma_host2board_busy', },
1675 
      'entity' => {
1676 
        'attributes' => {
1677 
          'entityAlreadyNetlisted' => 1,
1678 
          'isGateway' => 1,
1679 
          'is_floating_block' => 1,
1680 
        },
1681 
        'entityName' => 'dma_host2board_busy',
1682 
        'ports' => {
1683 
          'dma_host2board_busy' => {
1684 
            'attributes' => {
1685 
              'bin_pt' => 0,
1686 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
1687 
              'is_floating_block' => 1,
1688 
              'is_gateway_port' => 1,
1689 
              'must_be_hdl_vector' => 1,
1690 
              'period' => 1,
1691 
              'port_id' => 0,
1692 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
1693 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
1694 
              'timingConstraint' => 'none',
1695 
              'type' => 'UFix_1_0',
1696 
            },
1697 
            'direction' => 'out',
1698 
            'hdlType' => 'std_logic',
1699 
            'width' => 1,
1700 
          },
1701 
        },
1702 
      },
1703 
      'entityName' => 'dma_host2board_busy',
1704 
    },
1705 
    'dma_host2board_done' => {
1706 
      'connections' => { 'dma_host2board_done' => '.dma_host2board_done', },
1707 
      'entity' => {
1708 
        'attributes' => {
1709 
          'entityAlreadyNetlisted' => 1,
1710 
          'isGateway' => 1,
1711 
          'is_floating_block' => 1,
1712 
        },
1713 
        'entityName' => 'dma_host2board_done',
1714 
        'ports' => {
1715 
          'dma_host2board_done' => {
1716 
            'attributes' => {
1717 
              'bin_pt' => 0,
1718 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
1719 
              'is_floating_block' => 1,
1720 
              'is_gateway_port' => 1,
1721 
              'must_be_hdl_vector' => 1,
1722 
              'period' => 1,
1723 
              'port_id' => 0,
1724 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
1725 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
1726 
              'timingConstraint' => 'none',
1727 
              'type' => 'UFix_1_0',
1728 
            },
1729 
            'direction' => 'out',
1730 
            'hdlType' => 'std_logic',
1731 
            'width' => 1,
1732 
          },
1733 
        },
1734 
      },
1735 
      'entityName' => 'dma_host2board_done',
1736 
    },
1737 
    'from_register1' => {
1738 
      'connections' => { 'data_out' => 'from_register1.data_out', },
1739 
      'entity' => {
1740 
        'attributes' => {
1741 
          'entityAlreadyNetlisted' => 1,
1742 
          'generics' => [],
1743 
          'is_floating_block' => 1,
1744 
          'mask' => {
1745 
            'Block_Handle' => 10.0009765625,
1746 
            'Block_handle' => 10.0009765625,
1747 
            'MDL_Handle' => 3.0009765625,
1748 
            'MDL_handle' => 3.0009765625,
1749 
            'arith_type' => 2,
1750 
            'bin_pt' => 0,
1751 
            'block_config' => 'sysgen_blockset:fromreg_config',
1752 
            'block_handle' => 10.0009765625,
1753 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1754 
            'block_type' => 'fromreg',
1755 
            'dbl_ovrd' => 0,
1756 
            'init' => 0,
1757 
            'init_bit_vector' => '0b',
1758 
            'mdl_handle' => 3.0009765625,
1759 
            'model_handle' => 3.0009765625,
1760 
            'n_bits' => 1,
1761 
            'ownership' => 2,
1762 
            'period' => '8e-009',
1763 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1764 
            'shared_memory_name' => 'register01rv',
1765 
          },
1766 
          'needs_vhdl_wrapper' => 0,
1767 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1768 
        },
1769 
        'entityName' => 'x_x61',
1770 
        'ports' => {
1771 
          'data_out' => {
1772 
            'attributes' => {
1773 
              'bin_pt' => 0,
1774 
              'is_floating_block' => 1,
1775 
              'must_be_hdl_vector' => 1,
1776 
              'period' => 1,
1777 
              'port_id' => 0,
1778 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
1779 
              'type' => 'UFix_1_0',
1780 
            },
1781 
            'direction' => 'out',
1782 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1783 
            'width' => 1,
1784 
          },
1785 
        },
1786 
      },
1787 
      'entityName' => 'x_x61',
1788 
    },
1789 
    'from_register10' => {
1790 
      'connections' => { 'data_out' => 'from_register10.data_out', },
1791 
      'entity' => {
1792 
        'attributes' => {
1793 
          'entityAlreadyNetlisted' => 1,
1794 
          'generics' => [],
1795 
          'is_floating_block' => 1,
1796 
          'mask' => {
1797 
            'Block_Handle' => 11.0009765625,
1798 
            'Block_handle' => 11.0009765625,
1799 
            'MDL_Handle' => 3.0009765625,
1800 
            'MDL_handle' => 3.0009765625,
1801 
            'arith_type' => 2,
1802 
            'bin_pt' => 0,
1803 
            'block_config' => 'sysgen_blockset:fromreg_config',
1804 
            'block_handle' => 11.0009765625,
1805 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1806 
            'block_type' => 'fromreg',
1807 
            'dbl_ovrd' => 0,
1808 
            'init' => 0,
1809 
            'init_bit_vector' => '00000000000000000000000000000000b',
1810 
            'mdl_handle' => 3.0009765625,
1811 
            'model_handle' => 3.0009765625,
1812 
            'n_bits' => 32,
1813 
            'ownership' => 2,
1814 
            'period' => '8e-009',
1815 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1816 
            'shared_memory_name' => 'register05rd',
1817 
          },
1818 
          'needs_vhdl_wrapper' => 0,
1819 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1820 
        },
1821 
        'entityName' => 'x_x62',
1822 
        'ports' => {
1823 
          'data_out' => {
1824 
            'attributes' => {
1825 
              'bin_pt' => 0,
1826 
              'is_floating_block' => 1,
1827 
              'must_be_hdl_vector' => 1,
1828 
              'period' => 1,
1829 
              'port_id' => 0,
1830 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
1831 
              'type' => 'UFix_32_0',
1832 
            },
1833 
            'direction' => 'out',
1834 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1835 
            'width' => 32,
1836 
          },
1837 
        },
1838 
      },
1839 
      'entityName' => 'x_x62',
1840 
    },
1841 
    'from_register11' => {
1842 
      'connections' => { 'data_out' => 'from_register11.data_out', },
1843 
      'entity' => {
1844 
        'attributes' => {
1845 
          'entityAlreadyNetlisted' => 1,
1846 
          'generics' => [],
1847 
          'is_floating_block' => 1,
1848 
          'mask' => {
1849 
            'Block_Handle' => 12.0009765625,
1850 
            'Block_handle' => 12.0009765625,
1851 
            'MDL_Handle' => 3.0009765625,
1852 
            'MDL_handle' => 3.0009765625,
1853 
            'arith_type' => 2,
1854 
            'bin_pt' => 0,
1855 
            'block_config' => 'sysgen_blockset:fromreg_config',
1856 
            'block_handle' => 12.0009765625,
1857 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1858 
            'block_type' => 'fromreg',
1859 
            'dbl_ovrd' => 0,
1860 
            'init' => 0,
1861 
            'init_bit_vector' => '00000000000000000000000000000000b',
1862 
            'mdl_handle' => 3.0009765625,
1863 
            'model_handle' => 3.0009765625,
1864 
            'n_bits' => 32,
1865 
            'ownership' => 2,
1866 
            'period' => '8e-009',
1867 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1868 
            'shared_memory_name' => 'register06rd',
1869 
          },
1870 
          'needs_vhdl_wrapper' => 0,
1871 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1872 
        },
1873 
        'entityName' => 'x_x63',
1874 
        'ports' => {
1875 
          'data_out' => {
1876 
            'attributes' => {
1877 
              'bin_pt' => 0,
1878 
              'is_floating_block' => 1,
1879 
              'must_be_hdl_vector' => 1,
1880 
              'period' => 1,
1881 
              'port_id' => 0,
1882 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
1883 
              'type' => 'UFix_32_0',
1884 
            },
1885 
            'direction' => 'out',
1886 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1887 
            'width' => 32,
1888 
          },
1889 
        },
1890 
      },
1891 
      'entityName' => 'x_x63',
1892 
    },
1893 
    'from_register12' => {
1894 
      'connections' => { 'data_out' => 'from_register12.data_out', },
1895 
      'entity' => {
1896 
        'attributes' => {
1897 
          'entityAlreadyNetlisted' => 1,
1898 
          'generics' => [],
1899 
          'is_floating_block' => 1,
1900 
          'mask' => {
1901 
            'Block_Handle' => 13.0009765625,
1902 
            'Block_handle' => 13.0009765625,
1903 
            'MDL_Handle' => 3.0009765625,
1904 
            'MDL_handle' => 3.0009765625,
1905 
            'arith_type' => 2,
1906 
            'bin_pt' => 0,
1907 
            'block_config' => 'sysgen_blockset:fromreg_config',
1908 
            'block_handle' => 13.0009765625,
1909 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1910 
            'block_type' => 'fromreg',
1911 
            'dbl_ovrd' => 0,
1912 
            'init' => 0,
1913 
            'init_bit_vector' => '0b',
1914 
            'mdl_handle' => 3.0009765625,
1915 
            'model_handle' => 3.0009765625,
1916 
            'n_bits' => 1,
1917 
            'ownership' => 2,
1918 
            'period' => '8e-009',
1919 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1920 
            'shared_memory_name' => 'register06rv',
1921 
          },
1922 
          'needs_vhdl_wrapper' => 0,
1923 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1924 
        },
1925 
        'entityName' => 'x_x64',
1926 
        'ports' => {
1927 
          'data_out' => {
1928 
            'attributes' => {
1929 
              'bin_pt' => 0,
1930 
              'is_floating_block' => 1,
1931 
              'must_be_hdl_vector' => 1,
1932 
              'period' => 1,
1933 
              'port_id' => 0,
1934 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
1935 
              'type' => 'UFix_1_0',
1936 
            },
1937 
            'direction' => 'out',
1938 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1939 
            'width' => 1,
1940 
          },
1941 
        },
1942 
      },
1943 
      'entityName' => 'x_x64',
1944 
    },
1945 
    'from_register13' => {
1946 
      'connections' => { 'data_out' => 'from_register13.data_out', },
1947 
      'entity' => {
1948 
        'attributes' => {
1949 
          'entityAlreadyNetlisted' => 1,
1950 
          'generics' => [],
1951 
          'is_floating_block' => 1,
1952 
          'mask' => {
1953 
            'Block_Handle' => 14.0009765625,
1954 
            'Block_handle' => 14.0009765625,
1955 
            'MDL_Handle' => 3.0009765625,
1956 
            'MDL_handle' => 3.0009765625,
1957 
            'arith_type' => 2,
1958 
            'bin_pt' => 0,
1959 
            'block_config' => 'sysgen_blockset:fromreg_config',
1960 
            'block_handle' => 14.0009765625,
1961 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
1962 
            'block_type' => 'fromreg',
1963 
            'dbl_ovrd' => 0,
1964 
            'init' => 0,
1965 
            'init_bit_vector' => '00000000000000000000000000000000b',
1966 
            'mdl_handle' => 3.0009765625,
1967 
            'model_handle' => 3.0009765625,
1968 
            'n_bits' => 32,
1969 
            'ownership' => 2,
1970 
            'period' => '8e-009',
1971 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1972 
            'shared_memory_name' => 'register07rd',
1973 
          },
1974 
          'needs_vhdl_wrapper' => 0,
1975 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
1976 
        },
1977 
        'entityName' => 'x_x65',
1978 
        'ports' => {
1979 
          'data_out' => {
1980 
            'attributes' => {
1981 
              'bin_pt' => 0,
1982 
              'is_floating_block' => 1,
1983 
              'must_be_hdl_vector' => 1,
1984 
              'period' => 1,
1985 
              'port_id' => 0,
1986 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
1987 
              'type' => 'UFix_32_0',
1988 
            },
1989 
            'direction' => 'out',
1990 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1991 
            'width' => 32,
1992 
          },
1993 
        },
1994 
      },
1995 
      'entityName' => 'x_x65',
1996 
    },
1997 
    'from_register14' => {
1998 
      'connections' => { 'data_out' => 'from_register14.data_out', },
1999 
      'entity' => {
2000 
        'attributes' => {
2001 
          'entityAlreadyNetlisted' => 1,
2002 
          'generics' => [],
2003 
          'is_floating_block' => 1,
2004 
          'mask' => {
2005 
            'Block_Handle' => 15.0009765625,
2006 
            'Block_handle' => 15.0009765625,
2007 
            'MDL_Handle' => 3.0009765625,
2008 
            'MDL_handle' => 3.0009765625,
2009 
            'arith_type' => 2,
2010 
            'bin_pt' => 0,
2011 
            'block_config' => 'sysgen_blockset:fromreg_config',
2012 
            'block_handle' => 15.0009765625,
2013 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2014 
            'block_type' => 'fromreg',
2015 
            'dbl_ovrd' => 0,
2016 
            'init' => 0,
2017 
            'init_bit_vector' => '0b',
2018 
            'mdl_handle' => 3.0009765625,
2019 
            'model_handle' => 3.0009765625,
2020 
            'n_bits' => 1,
2021 
            'ownership' => 2,
2022 
            'period' => '8e-009',
2023 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2024 
            'shared_memory_name' => 'register07rv',
2025 
          },
2026 
          'needs_vhdl_wrapper' => 0,
2027 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2028 
        },
2029 
        'entityName' => 'x_x66',
2030 
        'ports' => {
2031 
          'data_out' => {
2032 
            'attributes' => {
2033 
              'bin_pt' => 0,
2034 
              'is_floating_block' => 1,
2035 
              'must_be_hdl_vector' => 1,
2036 
              'period' => 1,
2037 
              'port_id' => 0,
2038 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
2039 
              'type' => 'UFix_1_0',
2040 
            },
2041 
            'direction' => 'out',
2042 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2043 
            'width' => 1,
2044 
          },
2045 
        },
2046 
      },
2047 
      'entityName' => 'x_x66',
2048 
    },
2049 
    'from_register15' => {
2050 
      'connections' => { 'data_out' => 'from_register15.data_out', },
2051 
      'entity' => {
2052 
        'attributes' => {
2053 
          'entityAlreadyNetlisted' => 1,
2054 
          'generics' => [],
2055 
          'is_floating_block' => 1,
2056 
          'mask' => {
2057 
            'Block_Handle' => 16.0009765625,
2058 
            'Block_handle' => 16.0009765625,
2059 
            'MDL_Handle' => 3.0009765625,
2060 
            'MDL_handle' => 3.0009765625,
2061 
            'arith_type' => 2,
2062 
            'bin_pt' => 0,
2063 
            'block_config' => 'sysgen_blockset:fromreg_config',
2064 
            'block_handle' => 16.0009765625,
2065 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2066 
            'block_type' => 'fromreg',
2067 
            'dbl_ovrd' => 0,
2068 
            'init' => 0,
2069 
            'init_bit_vector' => '00000000000000000000000000000000b',
2070 
            'mdl_handle' => 3.0009765625,
2071 
            'model_handle' => 3.0009765625,
2072 
            'n_bits' => 32,
2073 
            'ownership' => 2,
2074 
            'period' => '8e-009',
2075 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2076 
            'shared_memory_name' => 'register08rd',
2077 
          },
2078 
          'needs_vhdl_wrapper' => 0,
2079 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2080 
        },
2081 
        'entityName' => 'x_x67',
2082 
        'ports' => {
2083 
          'data_out' => {
2084 
            'attributes' => {
2085 
              'bin_pt' => 0,
2086 
              'is_floating_block' => 1,
2087 
              'must_be_hdl_vector' => 1,
2088 
              'period' => 1,
2089 
              'port_id' => 0,
2090 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
2091 
              'type' => 'UFix_32_0',
2092 
            },
2093 
            'direction' => 'out',
2094 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2095 
            'width' => 32,
2096 
          },
2097 
        },
2098 
      },
2099 
      'entityName' => 'x_x67',
2100 
    },
2101 
    'from_register16' => {
2102 
      'connections' => { 'data_out' => 'from_register16.data_out', },
2103 
      'entity' => {
2104 
        'attributes' => {
2105 
          'entityAlreadyNetlisted' => 1,
2106 
          'generics' => [],
2107 
          'is_floating_block' => 1,
2108 
          'mask' => {
2109 
            'Block_Handle' => 17.0009765625,
2110 
            'Block_handle' => 17.0009765625,
2111 
            'MDL_Handle' => 3.0009765625,
2112 
            'MDL_handle' => 3.0009765625,
2113 
            'arith_type' => 2,
2114 
            'bin_pt' => 0,
2115 
            'block_config' => 'sysgen_blockset:fromreg_config',
2116 
            'block_handle' => 17.0009765625,
2117 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2118 
            'block_type' => 'fromreg',
2119 
            'dbl_ovrd' => 0,
2120 
            'init' => 0,
2121 
            'init_bit_vector' => '0b',
2122 
            'mdl_handle' => 3.0009765625,
2123 
            'model_handle' => 3.0009765625,
2124 
            'n_bits' => 1,
2125 
            'ownership' => 2,
2126 
            'period' => '8e-009',
2127 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2128 
            'shared_memory_name' => 'register08rv',
2129 
          },
2130 
          'needs_vhdl_wrapper' => 0,
2131 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2132 
        },
2133 
        'entityName' => 'x_x68',
2134 
        'ports' => {
2135 
          'data_out' => {
2136 
            'attributes' => {
2137 
              'bin_pt' => 0,
2138 
              'is_floating_block' => 1,
2139 
              'must_be_hdl_vector' => 1,
2140 
              'period' => 1,
2141 
              'port_id' => 0,
2142 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
2143 
              'type' => 'UFix_1_0',
2144 
            },
2145 
            'direction' => 'out',
2146 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2147 
            'width' => 1,
2148 
          },
2149 
        },
2150 
      },
2151 
      'entityName' => 'x_x68',
2152 
    },
2153 
    'from_register17' => {
2154 
      'connections' => { 'data_out' => 'from_register17.data_out', },
2155 
      'entity' => {
2156 
        'attributes' => {
2157 
          'entityAlreadyNetlisted' => 1,
2158 
          'generics' => [],
2159 
          'is_floating_block' => 1,
2160 
          'mask' => {
2161 
            'Block_Handle' => 18.0009765625,
2162 
            'Block_handle' => 18.0009765625,
2163 
            'MDL_Handle' => 3.0009765625,
2164 
            'MDL_handle' => 3.0009765625,
2165 
            'arith_type' => 2,
2166 
            'bin_pt' => 0,
2167 
            'block_config' => 'sysgen_blockset:fromreg_config',
2168 
            'block_handle' => 18.0009765625,
2169 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2170 
            'block_type' => 'fromreg',
2171 
            'dbl_ovrd' => 0,
2172 
            'init' => 0,
2173 
            'init_bit_vector' => '00000000000000000000000000000000b',
2174 
            'mdl_handle' => 3.0009765625,
2175 
            'model_handle' => 3.0009765625,
2176 
            'n_bits' => 32,
2177 
            'ownership' => 2,
2178 
            'period' => '8e-009',
2179 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2180 
            'shared_memory_name' => 'register09rd',
2181 
          },
2182 
          'needs_vhdl_wrapper' => 0,
2183 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2184 
        },
2185 
        'entityName' => 'x_x69',
2186 
        'ports' => {
2187 
          'data_out' => {
2188 
            'attributes' => {
2189 
              'bin_pt' => 0,
2190 
              'is_floating_block' => 1,
2191 
              'must_be_hdl_vector' => 1,
2192 
              'period' => 1,
2193 
              'port_id' => 0,
2194 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
2195 
              'type' => 'UFix_32_0',
2196 
            },
2197 
            'direction' => 'out',
2198 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2199 
            'width' => 32,
2200 
          },
2201 
        },
2202 
      },
2203 
      'entityName' => 'x_x69',
2204 
    },
2205 
    'from_register18' => {
2206 
      'connections' => { 'data_out' => 'from_register18.data_out', },
2207 
      'entity' => {
2208 
        'attributes' => {
2209 
          'entityAlreadyNetlisted' => 1,
2210 
          'generics' => [],
2211 
          'is_floating_block' => 1,
2212 
          'mask' => {
2213 
            'Block_Handle' => 19.0009765625,
2214 
            'Block_handle' => 19.0009765625,
2215 
            'MDL_Handle' => 3.0009765625,
2216 
            'MDL_handle' => 3.0009765625,
2217 
            'arith_type' => 2,
2218 
            'bin_pt' => 0,
2219 
            'block_config' => 'sysgen_blockset:fromreg_config',
2220 
            'block_handle' => 19.0009765625,
2221 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2222 
            'block_type' => 'fromreg',
2223 
            'dbl_ovrd' => 0,
2224 
            'init' => 0,
2225 
            'init_bit_vector' => '0b',
2226 
            'mdl_handle' => 3.0009765625,
2227 
            'model_handle' => 3.0009765625,
2228 
            'n_bits' => 1,
2229 
            'ownership' => 2,
2230 
            'period' => '8e-009',
2231 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2232 
            'shared_memory_name' => 'register09rv',
2233 
          },
2234 
          'needs_vhdl_wrapper' => 0,
2235 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2236 
        },
2237 
        'entityName' => 'x_x70',
2238 
        'ports' => {
2239 
          'data_out' => {
2240 
            'attributes' => {
2241 
              'bin_pt' => 0,
2242 
              'is_floating_block' => 1,
2243 
              'must_be_hdl_vector' => 1,
2244 
              'period' => 1,
2245 
              'port_id' => 0,
2246 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
2247 
              'type' => 'UFix_1_0',
2248 
            },
2249 
            'direction' => 'out',
2250 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2251 
            'width' => 1,
2252 
          },
2253 
        },
2254 
      },
2255 
      'entityName' => 'x_x70',
2256 
    },
2257 
    'from_register19' => {
2258 
      'connections' => { 'data_out' => 'from_register19.data_out', },
2259 
      'entity' => {
2260 
        'attributes' => {
2261 
          'entityAlreadyNetlisted' => 1,
2262 
          'generics' => [],
2263 
          'is_floating_block' => 1,
2264 
          'mask' => {
2265 
            'Block_Handle' => 20.0009765625,
2266 
            'Block_handle' => 20.0009765625,
2267 
            'MDL_Handle' => 3.0009765625,
2268 
            'MDL_handle' => 3.0009765625,
2269 
            'arith_type' => 2,
2270 
            'bin_pt' => 0,
2271 
            'block_config' => 'sysgen_blockset:fromreg_config',
2272 
            'block_handle' => 20.0009765625,
2273 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2274 
            'block_type' => 'fromreg',
2275 
            'dbl_ovrd' => 0,
2276 
            'init' => 0,
2277 
            'init_bit_vector' => '00000000000000000000000000000000b',
2278 
            'mdl_handle' => 3.0009765625,
2279 
            'model_handle' => 3.0009765625,
2280 
            'n_bits' => 32,
2281 
            'ownership' => 2,
2282 
            'period' => '8e-009',
2283 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2284 
            'shared_memory_name' => 'register10rd',
2285 
          },
2286 
          'needs_vhdl_wrapper' => 0,
2287 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2288 
        },
2289 
        'entityName' => 'x_x71',
2290 
        'ports' => {
2291 
          'data_out' => {
2292 
            'attributes' => {
2293 
              'bin_pt' => 0,
2294 
              'is_floating_block' => 1,
2295 
              'must_be_hdl_vector' => 1,
2296 
              'period' => 1,
2297 
              'port_id' => 0,
2298 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
2299 
              'type' => 'UFix_32_0',
2300 
            },
2301 
            'direction' => 'out',
2302 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2303 
            'width' => 32,
2304 
          },
2305 
        },
2306 
      },
2307 
      'entityName' => 'x_x71',
2308 
    },
2309 
    'from_register2' => {
2310 
      'connections' => { 'data_out' => 'from_register2.data_out', },
2311 
      'entity' => {
2312 
        'attributes' => {
2313 
          'entityAlreadyNetlisted' => 1,
2314 
          'generics' => [],
2315 
          'is_floating_block' => 1,
2316 
          'mask' => {
2317 
            'Block_Handle' => 21.0009765625,
2318 
            'Block_handle' => 21.0009765625,
2319 
            'MDL_Handle' => 3.0009765625,
2320 
            'MDL_handle' => 3.0009765625,
2321 
            'arith_type' => 2,
2322 
            'bin_pt' => 0,
2323 
            'block_config' => 'sysgen_blockset:fromreg_config',
2324 
            'block_handle' => 21.0009765625,
2325 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2326 
            'block_type' => 'fromreg',
2327 
            'dbl_ovrd' => 0,
2328 
            'init' => 0,
2329 
            'init_bit_vector' => '0b',
2330 
            'mdl_handle' => 3.0009765625,
2331 
            'model_handle' => 3.0009765625,
2332 
            'n_bits' => 1,
2333 
            'ownership' => 2,
2334 
            'period' => '8e-009',
2335 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2336 
            'shared_memory_name' => 'register02rv',
2337 
          },
2338 
          'needs_vhdl_wrapper' => 0,
2339 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2340 
        },
2341 
        'entityName' => 'x_x72',
2342 
        'ports' => {
2343 
          'data_out' => {
2344 
            'attributes' => {
2345 
              'bin_pt' => 0,
2346 
              'is_floating_block' => 1,
2347 
              'must_be_hdl_vector' => 1,
2348 
              'period' => 1,
2349 
              'port_id' => 0,
2350 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
2351 
              'type' => 'UFix_1_0',
2352 
            },
2353 
            'direction' => 'out',
2354 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2355 
            'width' => 1,
2356 
          },
2357 
        },
2358 
      },
2359 
      'entityName' => 'x_x72',
2360 
    },
2361 
    'from_register20' => {
2362 
      'connections' => { 'data_out' => 'from_register20.data_out', },
2363 
      'entity' => {
2364 
        'attributes' => {
2365 
          'entityAlreadyNetlisted' => 1,
2366 
          'generics' => [],
2367 
          'is_floating_block' => 1,
2368 
          'mask' => {
2369 
            'Block_Handle' => 22.0009765625,
2370 
            'Block_handle' => 22.0009765625,
2371 
            'MDL_Handle' => 3.0009765625,
2372 
            'MDL_handle' => 3.0009765625,
2373 
            'arith_type' => 2,
2374 
            'bin_pt' => 0,
2375 
            'block_config' => 'sysgen_blockset:fromreg_config',
2376 
            'block_handle' => 22.0009765625,
2377 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2378 
            'block_type' => 'fromreg',
2379 
            'dbl_ovrd' => 0,
2380 
            'init' => 0,
2381 
            'init_bit_vector' => '0b',
2382 
            'mdl_handle' => 3.0009765625,
2383 
            'model_handle' => 3.0009765625,
2384 
            'n_bits' => 1,
2385 
            'ownership' => 2,
2386 
            'period' => '8e-009',
2387 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2388 
            'shared_memory_name' => 'register10rv',
2389 
          },
2390 
          'needs_vhdl_wrapper' => 0,
2391 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2392 
        },
2393 
        'entityName' => 'x_x73',
2394 
        'ports' => {
2395 
          'data_out' => {
2396 
            'attributes' => {
2397 
              'bin_pt' => 0,
2398 
              'is_floating_block' => 1,
2399 
              'must_be_hdl_vector' => 1,
2400 
              'period' => 1,
2401 
              'port_id' => 0,
2402 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
2403 
              'type' => 'UFix_1_0',
2404 
            },
2405 
            'direction' => 'out',
2406 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2407 
            'width' => 1,
2408 
          },
2409 
        },
2410 
      },
2411 
      'entityName' => 'x_x73',
2412 
    },
2413 
    'from_register21' => {
2414 
      'connections' => { 'data_out' => 'from_register21.data_out', },
2415 
      'entity' => {
2416 
        'attributes' => {
2417 
          'entityAlreadyNetlisted' => 1,
2418 
          'generics' => [],
2419 
          'is_floating_block' => 1,
2420 
          'mask' => {
2421 
            'Block_Handle' => 23.0009765625,
2422 
            'Block_handle' => 23.0009765625,
2423 
            'MDL_Handle' => 3.0009765625,
2424 
            'MDL_handle' => 3.0009765625,
2425 
            'arith_type' => 2,
2426 
            'bin_pt' => 0,
2427 
            'block_config' => 'sysgen_blockset:fromreg_config',
2428 
            'block_handle' => 23.0009765625,
2429 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2430 
            'block_type' => 'fromreg',
2431 
            'dbl_ovrd' => 0,
2432 
            'init' => 0,
2433 
            'init_bit_vector' => '00000000000000000000000000000000b',
2434 
            'mdl_handle' => 3.0009765625,
2435 
            'model_handle' => 3.0009765625,
2436 
            'n_bits' => 32,
2437 
            'ownership' => 2,
2438 
            'period' => '8e-009',
2439 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2440 
            'shared_memory_name' => 'register11rd',
2441 
          },
2442 
          'needs_vhdl_wrapper' => 0,
2443 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2444 
        },
2445 
        'entityName' => 'x_x74',
2446 
        'ports' => {
2447 
          'data_out' => {
2448 
            'attributes' => {
2449 
              'bin_pt' => 0,
2450 
              'is_floating_block' => 1,
2451 
              'must_be_hdl_vector' => 1,
2452 
              'period' => 1,
2453 
              'port_id' => 0,
2454 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
2455 
              'type' => 'UFix_32_0',
2456 
            },
2457 
            'direction' => 'out',
2458 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2459 
            'width' => 32,
2460 
          },
2461 
        },
2462 
      },
2463 
      'entityName' => 'x_x74',
2464 
    },
2465 
    'from_register22' => {
2466 
      'connections' => { 'data_out' => 'from_register22.data_out', },
2467 
      'entity' => {
2468 
        'attributes' => {
2469 
          'entityAlreadyNetlisted' => 1,
2470 
          'generics' => [],
2471 
          'is_floating_block' => 1,
2472 
          'mask' => {
2473 
            'Block_Handle' => 24.0009765625,
2474 
            'Block_handle' => 24.0009765625,
2475 
            'MDL_Handle' => 3.0009765625,
2476 
            'MDL_handle' => 3.0009765625,
2477 
            'arith_type' => 2,
2478 
            'bin_pt' => 0,
2479 
            'block_config' => 'sysgen_blockset:fromreg_config',
2480 
            'block_handle' => 24.0009765625,
2481 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2482 
            'block_type' => 'fromreg',
2483 
            'dbl_ovrd' => 0,
2484 
            'init' => 0,
2485 
            'init_bit_vector' => '0b',
2486 
            'mdl_handle' => 3.0009765625,
2487 
            'model_handle' => 3.0009765625,
2488 
            'n_bits' => 1,
2489 
            'ownership' => 2,
2490 
            'period' => '8e-009',
2491 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2492 
            'shared_memory_name' => 'register11rv',
2493 
          },
2494 
          'needs_vhdl_wrapper' => 0,
2495 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2496 
        },
2497 
        'entityName' => 'x_x75',
2498 
        'ports' => {
2499 
          'data_out' => {
2500 
            'attributes' => {
2501 
              'bin_pt' => 0,
2502 
              'is_floating_block' => 1,
2503 
              'must_be_hdl_vector' => 1,
2504 
              'period' => 1,
2505 
              'port_id' => 0,
2506 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
2507 
              'type' => 'UFix_1_0',
2508 
            },
2509 
            'direction' => 'out',
2510 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2511 
            'width' => 1,
2512 
          },
2513 
        },
2514 
      },
2515 
      'entityName' => 'x_x75',
2516 
    },
2517 
    'from_register23' => {
2518 
      'connections' => { 'data_out' => 'from_register23.data_out', },
2519 
      'entity' => {
2520 
        'attributes' => {
2521 
          'entityAlreadyNetlisted' => 1,
2522 
          'generics' => [],
2523 
          'is_floating_block' => 1,
2524 
          'mask' => {
2525 
            'Block_Handle' => 25.0009765625,
2526 
            'Block_handle' => 25.0009765625,
2527 
            'MDL_Handle' => 3.0009765625,
2528 
            'MDL_handle' => 3.0009765625,
2529 
            'arith_type' => 2,
2530 
            'bin_pt' => 0,
2531 
            'block_config' => 'sysgen_blockset:fromreg_config',
2532 
            'block_handle' => 25.0009765625,
2533 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2534 
            'block_type' => 'fromreg',
2535 
            'dbl_ovrd' => 0,
2536 
            'init' => 0,
2537 
            'init_bit_vector' => '00000000000000000000000000000000b',
2538 
            'mdl_handle' => 3.0009765625,
2539 
            'model_handle' => 3.0009765625,
2540 
            'n_bits' => 32,
2541 
            'ownership' => 2,
2542 
            'period' => '8e-009',
2543 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2544 
            'shared_memory_name' => 'register12rd',
2545 
          },
2546 
          'needs_vhdl_wrapper' => 0,
2547 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2548 
        },
2549 
        'entityName' => 'x_x76',
2550 
        'ports' => {
2551 
          'data_out' => {
2552 
            'attributes' => {
2553 
              'bin_pt' => 0,
2554 
              'is_floating_block' => 1,
2555 
              'must_be_hdl_vector' => 1,
2556 
              'period' => 1,
2557 
              'port_id' => 0,
2558 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
2559 
              'type' => 'UFix_32_0',
2560 
            },
2561 
            'direction' => 'out',
2562 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2563 
            'width' => 32,
2564 
          },
2565 
        },
2566 
      },
2567 
      'entityName' => 'x_x76',
2568 
    },
2569 
    'from_register24' => {
2570 
      'connections' => { 'data_out' => 'from_register24.data_out', },
2571 
      'entity' => {
2572 
        'attributes' => {
2573 
          'entityAlreadyNetlisted' => 1,
2574 
          'generics' => [],
2575 
          'is_floating_block' => 1,
2576 
          'mask' => {
2577 
            'Block_Handle' => 26.0009765625,
2578 
            'Block_handle' => 26.0009765625,
2579 
            'MDL_Handle' => 3.0009765625,
2580 
            'MDL_handle' => 3.0009765625,
2581 
            'arith_type' => 2,
2582 
            'bin_pt' => 0,
2583 
            'block_config' => 'sysgen_blockset:fromreg_config',
2584 
            'block_handle' => 26.0009765625,
2585 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2586 
            'block_type' => 'fromreg',
2587 
            'dbl_ovrd' => 0,
2588 
            'init' => 0,
2589 
            'init_bit_vector' => '0b',
2590 
            'mdl_handle' => 3.0009765625,
2591 
            'model_handle' => 3.0009765625,
2592 
            'n_bits' => 1,
2593 
            'ownership' => 2,
2594 
            'period' => '8e-009',
2595 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2596 
            'shared_memory_name' => 'register12rv',
2597 
          },
2598 
          'needs_vhdl_wrapper' => 0,
2599 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2600 
        },
2601 
        'entityName' => 'x_x77',
2602 
        'ports' => {
2603 
          'data_out' => {
2604 
            'attributes' => {
2605 
              'bin_pt' => 0,
2606 
              'is_floating_block' => 1,
2607 
              'must_be_hdl_vector' => 1,
2608 
              'period' => 1,
2609 
              'port_id' => 0,
2610 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
2611 
              'type' => 'UFix_1_0',
2612 
            },
2613 
            'direction' => 'out',
2614 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2615 
            'width' => 1,
2616 
          },
2617 
        },
2618 
      },
2619 
      'entityName' => 'x_x77',
2620 
    },
2621 
    'from_register25' => {
2622 
      'connections' => { 'data_out' => 'from_register25.data_out', },
2623 
      'entity' => {
2624 
        'attributes' => {
2625 
          'entityAlreadyNetlisted' => 1,
2626 
          'generics' => [],
2627 
          'is_floating_block' => 1,
2628 
          'mask' => {
2629 
            'Block_Handle' => 27.0009765625,
2630 
            'Block_handle' => 27.0009765625,
2631 
            'MDL_Handle' => 3.0009765625,
2632 
            'MDL_handle' => 3.0009765625,
2633 
            'arith_type' => 2,
2634 
            'bin_pt' => 0,
2635 
            'block_config' => 'sysgen_blockset:fromreg_config',
2636 
            'block_handle' => 27.0009765625,
2637 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2638 
            'block_type' => 'fromreg',
2639 
            'dbl_ovrd' => 0,
2640 
            'init' => 0,
2641 
            'init_bit_vector' => '00000000000000000000000000000000b',
2642 
            'mdl_handle' => 3.0009765625,
2643 
            'model_handle' => 3.0009765625,
2644 
            'n_bits' => 32,
2645 
            'ownership' => 2,
2646 
            'period' => '8e-009',
2647 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2648 
            'shared_memory_name' => 'register13rd',
2649 
          },
2650 
          'needs_vhdl_wrapper' => 0,
2651 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2652 
        },
2653 
        'entityName' => 'x_x78',
2654 
        'ports' => {
2655 
          'data_out' => {
2656 
            'attributes' => {
2657 
              'bin_pt' => 0,
2658 
              'is_floating_block' => 1,
2659 
              'must_be_hdl_vector' => 1,
2660 
              'period' => 1,
2661 
              'port_id' => 0,
2662 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
2663 
              'type' => 'UFix_32_0',
2664 
            },
2665 
            'direction' => 'out',
2666 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2667 
            'width' => 32,
2668 
          },
2669 
        },
2670 
      },
2671 
      'entityName' => 'x_x78',
2672 
    },
2673 
    'from_register26' => {
2674 
      'connections' => { 'data_out' => 'from_register26.data_out', },
2675 
      'entity' => {
2676 
        'attributes' => {
2677 
          'entityAlreadyNetlisted' => 1,
2678 
          'generics' => [],
2679 
          'is_floating_block' => 1,
2680 
          'mask' => {
2681 
            'Block_Handle' => 28.0009765625,
2682 
            'Block_handle' => 28.0009765625,
2683 
            'MDL_Handle' => 3.0009765625,
2684 
            'MDL_handle' => 3.0009765625,
2685 
            'arith_type' => 2,
2686 
            'bin_pt' => 0,
2687 
            'block_config' => 'sysgen_blockset:fromreg_config',
2688 
            'block_handle' => 28.0009765625,
2689 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2690 
            'block_type' => 'fromreg',
2691 
            'dbl_ovrd' => 0,
2692 
            'init' => 0,
2693 
            'init_bit_vector' => '0b',
2694 
            'mdl_handle' => 3.0009765625,
2695 
            'model_handle' => 3.0009765625,
2696 
            'n_bits' => 1,
2697 
            'ownership' => 2,
2698 
            'period' => '8e-009',
2699 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2700 
            'shared_memory_name' => 'register13rv',
2701 
          },
2702 
          'needs_vhdl_wrapper' => 0,
2703 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2704 
        },
2705 
        'entityName' => 'x_x79',
2706 
        'ports' => {
2707 
          'data_out' => {
2708 
            'attributes' => {
2709 
              'bin_pt' => 0,
2710 
              'is_floating_block' => 1,
2711 
              'must_be_hdl_vector' => 1,
2712 
              'period' => 1,
2713 
              'port_id' => 0,
2714 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
2715 
              'type' => 'UFix_1_0',
2716 
            },
2717 
            'direction' => 'out',
2718 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2719 
            'width' => 1,
2720 
          },
2721 
        },
2722 
      },
2723 
      'entityName' => 'x_x79',
2724 
    },
2725 
    'from_register27' => {
2726 
      'connections' => { 'data_out' => 'from_register27.data_out', },
2727 
      'entity' => {
2728 
        'attributes' => {
2729 
          'entityAlreadyNetlisted' => 1,
2730 
          'generics' => [],
2731 
          'is_floating_block' => 1,
2732 
          'mask' => {
2733 
            'Block_Handle' => 29.0009765625,
2734 
            'Block_handle' => 29.0009765625,
2735 
            'MDL_Handle' => 3.0009765625,
2736 
            'MDL_handle' => 3.0009765625,
2737 
            'arith_type' => 2,
2738 
            'bin_pt' => 0,
2739 
            'block_config' => 'sysgen_blockset:fromreg_config',
2740 
            'block_handle' => 29.0009765625,
2741 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2742 
            'block_type' => 'fromreg',
2743 
            'dbl_ovrd' => 0,
2744 
            'init' => 0,
2745 
            'init_bit_vector' => '00000000000000000000000000000000b',
2746 
            'mdl_handle' => 3.0009765625,
2747 
            'model_handle' => 3.0009765625,
2748 
            'n_bits' => 32,
2749 
            'ownership' => 2,
2750 
            'period' => '8e-009',
2751 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2752 
            'shared_memory_name' => 'register14rd',
2753 
          },
2754 
          'needs_vhdl_wrapper' => 0,
2755 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2756 
        },
2757 
        'entityName' => 'x_x80',
2758 
        'ports' => {
2759 
          'data_out' => {
2760 
            'attributes' => {
2761 
              'bin_pt' => 0,
2762 
              'is_floating_block' => 1,
2763 
              'must_be_hdl_vector' => 1,
2764 
              'period' => 1,
2765 
              'port_id' => 0,
2766 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
2767 
              'type' => 'UFix_32_0',
2768 
            },
2769 
            'direction' => 'out',
2770 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2771 
            'width' => 32,
2772 
          },
2773 
        },
2774 
      },
2775 
      'entityName' => 'x_x80',
2776 
    },
2777 
    'from_register28' => {
2778 
      'connections' => { 'data_out' => 'from_register28.data_out', },
2779 
      'entity' => {
2780 
        'attributes' => {
2781 
          'entityAlreadyNetlisted' => 1,
2782 
          'generics' => [],
2783 
          'is_floating_block' => 1,
2784 
          'mask' => {
2785 
            'Block_Handle' => 30.0009765625,
2786 
            'Block_handle' => 30.0009765625,
2787 
            'MDL_Handle' => 3.0009765625,
2788 
            'MDL_handle' => 3.0009765625,
2789 
            'arith_type' => 2,
2790 
            'bin_pt' => 0,
2791 
            'block_config' => 'sysgen_blockset:fromreg_config',
2792 
            'block_handle' => 30.0009765625,
2793 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2794 
            'block_type' => 'fromreg',
2795 
            'dbl_ovrd' => 0,
2796 
            'init' => 0,
2797 
            'init_bit_vector' => '0b',
2798 
            'mdl_handle' => 3.0009765625,
2799 
            'model_handle' => 3.0009765625,
2800 
            'n_bits' => 1,
2801 
            'ownership' => 2,
2802 
            'period' => '8e-009',
2803 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2804 
            'shared_memory_name' => 'register14rv',
2805 
          },
2806 
          'needs_vhdl_wrapper' => 0,
2807 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2808 
        },
2809 
        'entityName' => 'x_x81',
2810 
        'ports' => {
2811 
          'data_out' => {
2812 
            'attributes' => {
2813 
              'bin_pt' => 0,
2814 
              'is_floating_block' => 1,
2815 
              'must_be_hdl_vector' => 1,
2816 
              'period' => 1,
2817 
              'port_id' => 0,
2818 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
2819 
              'type' => 'UFix_1_0',
2820 
            },
2821 
            'direction' => 'out',
2822 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2823 
            'width' => 1,
2824 
          },
2825 
        },
2826 
      },
2827 
      'entityName' => 'x_x81',
2828 
    },
2829 
    'from_register3' => {
2830 
      'connections' => { 'data_out' => 'from_register3.data_out', },
2831 
      'entity' => {
2832 
        'attributes' => {
2833 
          'entityAlreadyNetlisted' => 1,
2834 
          'generics' => [],
2835 
          'is_floating_block' => 1,
2836 
          'mask' => {
2837 
            'Block_Handle' => 31.0009765625,
2838 
            'Block_handle' => 31.0009765625,
2839 
            'MDL_Handle' => 3.0009765625,
2840 
            'MDL_handle' => 3.0009765625,
2841 
            'arith_type' => 2,
2842 
            'bin_pt' => 0,
2843 
            'block_config' => 'sysgen_blockset:fromreg_config',
2844 
            'block_handle' => 31.0009765625,
2845 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2846 
            'block_type' => 'fromreg',
2847 
            'dbl_ovrd' => 0,
2848 
            'init' => 0,
2849 
            'init_bit_vector' => '00000000000000000000000000000000b',
2850 
            'mdl_handle' => 3.0009765625,
2851 
            'model_handle' => 3.0009765625,
2852 
            'n_bits' => 32,
2853 
            'ownership' => 2,
2854 
            'period' => '8e-009',
2855 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2856 
            'shared_memory_name' => 'register01rd',
2857 
          },
2858 
          'needs_vhdl_wrapper' => 0,
2859 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2860 
        },
2861 
        'entityName' => 'x_x82',
2862 
        'ports' => {
2863 
          'data_out' => {
2864 
            'attributes' => {
2865 
              'bin_pt' => 0,
2866 
              'is_floating_block' => 1,
2867 
              'must_be_hdl_vector' => 1,
2868 
              'period' => 1,
2869 
              'port_id' => 0,
2870 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
2871 
              'type' => 'UFix_32_0',
2872 
            },
2873 
            'direction' => 'out',
2874 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2875 
            'width' => 32,
2876 
          },
2877 
        },
2878 
      },
2879 
      'entityName' => 'x_x82',
2880 
    },
2881 
    'from_register4' => {
2882 
      'connections' => { 'data_out' => 'from_register4.data_out', },
2883 
      'entity' => {
2884 
        'attributes' => {
2885 
          'entityAlreadyNetlisted' => 1,
2886 
          'generics' => [],
2887 
          'is_floating_block' => 1,
2888 
          'mask' => {
2889 
            'Block_Handle' => 32.0009765625,
2890 
            'Block_handle' => 32.0009765625,
2891 
            'MDL_Handle' => 3.0009765625,
2892 
            'MDL_handle' => 3.0009765625,
2893 
            'arith_type' => 2,
2894 
            'bin_pt' => 0,
2895 
            'block_config' => 'sysgen_blockset:fromreg_config',
2896 
            'block_handle' => 32.0009765625,
2897 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
2898 
            'block_type' => 'fromreg',
2899 
            'dbl_ovrd' => 0,
2900 
            'init' => 0,
2901 
            'init_bit_vector' => '0b',
2902 
            'mdl_handle' => 3.0009765625,
2903 
            'model_handle' => 3.0009765625,
2904 
            'n_bits' => 1,
2905 
            'ownership' => 2,
2906 
            'period' => '8e-009',
2907 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2908 
            'shared_memory_name' => 'register04rv',
2909 
          },
2910 
          'needs_vhdl_wrapper' => 0,
2911 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
2912 
        },
2913 
        'entityName' => 'x_x83',
2914 
        'ports' => {
2915 
          'data_out' => {
2916 
            'attributes' => {
2917 
              'bin_pt' => 0,
2918 
              'is_floating_block' => 1,
2919 
              'must_be_hdl_vector' => 1,
2920 
              'period' => 1,
2921 
              'port_id' => 0,
2922 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
2923 
              'type' => 'UFix_1_0',
2924 
            },
2925 
            'direction' => 'out',
2926 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2927 
            'width' => 1,
2928 
          },
2929 
        },
2930 
      },
2931 
      'entityName' => 'x_x83',
2932 
    },
2933 
    'from_register5' => {
2934 
      'connections' => { 'data_out' => 'from_register5.data_out', },
2935 
      'entity' => {
2936 
        'attributes' => {
2937 
          'entityAlreadyNetlisted' => 1,
2938 
          'generics' => [],
2939 
          'is_floating_block' => 1,
2940 
          'mask' => {
2941 
            'Block_Handle' => 33.0009765625,
2942 
            'Block_handle' => 33.0009765625,
2943 
            'MDL_Handle' => 3.0009765625,
2944 
            'MDL_handle' => 3.0009765625,
2945 
            'arith_type' => 2,
2946 
            'bin_pt' => 0,
2947 
            'block_config' => 'sysgen_blockset:fromreg_config',
2948 
            'block_handle' => 33.0009765625,
2949 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
2950 
            'block_type' => 'fromreg',
2951 
            'dbl_ovrd' => 0,
2952 
            'init' => 0,
2953 
            'init_bit_vector' => '00000000000000000000000000000000b',
2954 
            'mdl_handle' => 3.0009765625,
2955 
            'model_handle' => 3.0009765625,
2956 
            'n_bits' => 32,
2957 
            'ownership' => 2,
2958 
            'period' => '8e-009',
2959 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2960 
            'shared_memory_name' => 'register02rd',
2961 
          },
2962 
          'needs_vhdl_wrapper' => 0,
2963 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
2964 
        },
2965 
        'entityName' => 'x_x84',
2966 
        'ports' => {
2967 
          'data_out' => {
2968 
            'attributes' => {
2969 
              'bin_pt' => 0,
2970 
              'is_floating_block' => 1,
2971 
              'must_be_hdl_vector' => 1,
2972 
              'period' => 1,
2973 
              'port_id' => 0,
2974 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
2975 
              'type' => 'UFix_32_0',
2976 
            },
2977 
            'direction' => 'out',
2978 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2979 
            'width' => 32,
2980 
          },
2981 
        },
2982 
      },
2983 
      'entityName' => 'x_x84',
2984 
    },
2985 
    'from_register6' => {
2986 
      'connections' => { 'data_out' => 'from_register6.data_out', },
2987 
      'entity' => {
2988 
        'attributes' => {
2989 
          'entityAlreadyNetlisted' => 1,
2990 
          'generics' => [],
2991 
          'is_floating_block' => 1,
2992 
          'mask' => {
2993 
            'Block_Handle' => 34.0009765625,
2994 
            'Block_handle' => 34.0009765625,
2995 
            'MDL_Handle' => 3.0009765625,
2996 
            'MDL_handle' => 3.0009765625,
2997 
            'arith_type' => 2,
2998 
            'bin_pt' => 0,
2999 
            'block_config' => 'sysgen_blockset:fromreg_config',
3000 
            'block_handle' => 34.0009765625,
3001 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3002 
            'block_type' => 'fromreg',
3003 
            'dbl_ovrd' => 0,
3004 
            'init' => 0,
3005 
            'init_bit_vector' => '0b',
3006 
            'mdl_handle' => 3.0009765625,
3007 
            'model_handle' => 3.0009765625,
3008 
            'n_bits' => 1,
3009 
            'ownership' => 2,
3010 
            'period' => '8e-009',
3011 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3012 
            'shared_memory_name' => 'register03rv',
3013 
          },
3014 
          'needs_vhdl_wrapper' => 0,
3015 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3016 
        },
3017 
        'entityName' => 'x_x85',
3018 
        'ports' => {
3019 
          'data_out' => {
3020 
            'attributes' => {
3021 
              'bin_pt' => 0,
3022 
              'is_floating_block' => 1,
3023 
              'must_be_hdl_vector' => 1,
3024 
              'period' => 1,
3025 
              'port_id' => 0,
3026 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
3027 
              'type' => 'UFix_1_0',
3028 
            },
3029 
            'direction' => 'out',
3030 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3031 
            'width' => 1,
3032 
          },
3033 
        },
3034 
      },
3035 
      'entityName' => 'x_x85',
3036 
    },
3037 
    'from_register7' => {
3038 
      'connections' => { 'data_out' => 'from_register7.data_out', },
3039 
      'entity' => {
3040 
        'attributes' => {
3041 
          'entityAlreadyNetlisted' => 1,
3042 
          'generics' => [],
3043 
          'is_floating_block' => 1,
3044 
          'mask' => {
3045 
            'Block_Handle' => 35.0009765625,
3046 
            'Block_handle' => 35.0009765625,
3047 
            'MDL_Handle' => 3.0009765625,
3048 
            'MDL_handle' => 3.0009765625,
3049 
            'arith_type' => 2,
3050 
            'bin_pt' => 0,
3051 
            'block_config' => 'sysgen_blockset:fromreg_config',
3052 
            'block_handle' => 35.0009765625,
3053 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3054 
            'block_type' => 'fromreg',
3055 
            'dbl_ovrd' => 0,
3056 
            'init' => 0,
3057 
            'init_bit_vector' => '00000000000000000000000000000000b',
3058 
            'mdl_handle' => 3.0009765625,
3059 
            'model_handle' => 3.0009765625,
3060 
            'n_bits' => 32,
3061 
            'ownership' => 2,
3062 
            'period' => '8e-009',
3063 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3064 
            'shared_memory_name' => 'register03rd',
3065 
          },
3066 
          'needs_vhdl_wrapper' => 0,
3067 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3068 
        },
3069 
        'entityName' => 'x_x86',
3070 
        'ports' => {
3071 
          'data_out' => {
3072 
            'attributes' => {
3073 
              'bin_pt' => 0,
3074 
              'is_floating_block' => 1,
3075 
              'must_be_hdl_vector' => 1,
3076 
              'period' => 1,
3077 
              'port_id' => 0,
3078 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
3079 
              'type' => 'UFix_32_0',
3080 
            },
3081 
            'direction' => 'out',
3082 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3083 
            'width' => 32,
3084 
          },
3085 
        },
3086 
      },
3087 
      'entityName' => 'x_x86',
3088 
    },
3089 
    'from_register8' => {
3090 
      'connections' => { 'data_out' => 'from_register8.data_out', },
3091 
      'entity' => {
3092 
        'attributes' => {
3093 
          'entityAlreadyNetlisted' => 1,
3094 
          'generics' => [],
3095 
          'is_floating_block' => 1,
3096 
          'mask' => {
3097 
            'Block_Handle' => 36.0009765625,
3098 
            'Block_handle' => 36.0009765625,
3099 
            'MDL_Handle' => 3.0009765625,
3100 
            'MDL_handle' => 3.0009765625,
3101 
            'arith_type' => 2,
3102 
            'bin_pt' => 0,
3103 
            'block_config' => 'sysgen_blockset:fromreg_config',
3104 
            'block_handle' => 36.0009765625,
3105 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3106 
            'block_type' => 'fromreg',
3107 
            'dbl_ovrd' => 0,
3108 
            'init' => 0,
3109 
            'init_bit_vector' => '00000000000000000000000000000000b',
3110 
            'mdl_handle' => 3.0009765625,
3111 
            'model_handle' => 3.0009765625,
3112 
            'n_bits' => 32,
3113 
            'ownership' => 2,
3114 
            'period' => '8e-009',
3115 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3116 
            'shared_memory_name' => 'register04rd',
3117 
          },
3118 
          'needs_vhdl_wrapper' => 0,
3119 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3120 
        },
3121 
        'entityName' => 'x_x87',
3122 
        'ports' => {
3123 
          'data_out' => {
3124 
            'attributes' => {
3125 
              'bin_pt' => 0,
3126 
              'is_floating_block' => 1,
3127 
              'must_be_hdl_vector' => 1,
3128 
              'period' => 1,
3129 
              'port_id' => 0,
3130 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
3131 
              'type' => 'UFix_32_0',
3132 
            },
3133 
            'direction' => 'out',
3134 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3135 
            'width' => 32,
3136 
          },
3137 
        },
3138 
      },
3139 
      'entityName' => 'x_x87',
3140 
    },
3141 
    'from_register9' => {
3142 
      'connections' => { 'data_out' => 'from_register9.data_out', },
3143 
      'entity' => {
3144 
        'attributes' => {
3145 
          'entityAlreadyNetlisted' => 1,
3146 
          'generics' => [],
3147 
          'is_floating_block' => 1,
3148 
          'mask' => {
3149 
            'Block_Handle' => 37.0009765625,
3150 
            'Block_handle' => 37.0009765625,
3151 
            'MDL_Handle' => 3.0009765625,
3152 
            'MDL_handle' => 3.0009765625,
3153 
            'arith_type' => 2,
3154 
            'bin_pt' => 0,
3155 
            'block_config' => 'sysgen_blockset:fromreg_config',
3156 
            'block_handle' => 37.0009765625,
3157 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3158 
            'block_type' => 'fromreg',
3159 
            'dbl_ovrd' => 0,
3160 
            'init' => 0,
3161 
            'init_bit_vector' => '0b',
3162 
            'mdl_handle' => 3.0009765625,
3163 
            'model_handle' => 3.0009765625,
3164 
            'n_bits' => 1,
3165 
            'ownership' => 2,
3166 
            'period' => '8e-009',
3167 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3168 
            'shared_memory_name' => 'register05rv',
3169 
          },
3170 
          'needs_vhdl_wrapper' => 0,
3171 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3172 
        },
3173 
        'entityName' => 'x_x88',
3174 
        'ports' => {
3175 
          'data_out' => {
3176 
            'attributes' => {
3177 
              'bin_pt' => 0,
3178 
              'is_floating_block' => 1,
3179 
              'must_be_hdl_vector' => 1,
3180 
              'period' => 1,
3181 
              'port_id' => 0,
3182 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
3183 
              'type' => 'UFix_1_0',
3184 
            },
3185 
            'direction' => 'out',
3186 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3187 
            'width' => 1,
3188 
          },
3189 
        },
3190 
      },
3191 
      'entityName' => 'x_x88',
3192 
    },
3193 
    'reg01_rd' => {
3194 
      'connections' => { 'reg01_rd' => 'sysgen_dut.reg01_rd', },
3195 
      'entity' => {
3196 
        'attributes' => {
3197 
          'entityAlreadyNetlisted' => 1,
3198 
          'isGateway' => 1,
3199 
          'is_floating_block' => 1,
3200 
        },
3201 
        'entityName' => 'reg01_rd',
3202 
        'ports' => {
3203 
          'reg01_rd' => {
3204 
            'attributes' => {
3205 
              'bin_pt' => 0,
3206 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
3207 
              'is_floating_block' => 1,
3208 
              'is_gateway_port' => 1,
3209 
              'must_be_hdl_vector' => 1,
3210 
              'period' => 1,
3211 
              'port_id' => 0,
3212 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
3213 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
3214 
              'timingConstraint' => 'none',
3215 
              'type' => 'UFix_32_0',
3216 
            },
3217 
            'direction' => 'in',
3218 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3219 
            'width' => 32,
3220 
          },
3221 
        },
3222 
      },
3223 
      'entityName' => 'reg01_rd',
3224 
    },
3225 
    'reg01_rv' => {
3226 
      'connections' => { 'reg01_rv' => 'sysgen_dut.reg01_rv', },
3227 
      'entity' => {
3228 
        'attributes' => {
3229 
          'entityAlreadyNetlisted' => 1,
3230 
          'isGateway' => 1,
3231 
          'is_floating_block' => 1,
3232 
        },
3233 
        'entityName' => 'reg01_rv',
3234 
        'ports' => {
3235 
          'reg01_rv' => {
3236 
            'attributes' => {
3237 
              'bin_pt' => 0,
3238 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
3239 
              'is_floating_block' => 1,
3240 
              'is_gateway_port' => 1,
3241 
              'must_be_hdl_vector' => 1,
3242 
              'period' => 1,
3243 
              'port_id' => 0,
3244 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
3245 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
3246 
              'timingConstraint' => 'none',
3247 
              'type' => 'UFix_1_0',
3248 
            },
3249 
            'direction' => 'in',
3250 
            'hdlType' => 'std_logic',
3251 
            'width' => 1,
3252 
          },
3253 
        },
3254 
      },
3255 
      'entityName' => 'reg01_rv',
3256 
    },
3257 
    'reg01_td' => {
3258 
      'connections' => { 'reg01_td' => '.reg01_td', },
3259 
      'entity' => {
3260 
        'attributes' => {
3261 
          'entityAlreadyNetlisted' => 1,
3262 
          'isGateway' => 1,
3263 
          'is_floating_block' => 1,
3264 
        },
3265 
        'entityName' => 'reg01_td',
3266 
        'ports' => {
3267 
          'reg01_td' => {
3268 
            'attributes' => {
3269 
              'bin_pt' => 0,
3270 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
3271 
              'is_floating_block' => 1,
3272 
              'is_gateway_port' => 1,
3273 
              'must_be_hdl_vector' => 1,
3274 
              'period' => 1,
3275 
              'port_id' => 0,
3276 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
3277 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
3278 
              'timingConstraint' => 'none',
3279 
              'type' => 'UFix_32_0',
3280 
            },
3281 
            'direction' => 'out',
3282 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3283 
            'width' => 32,
3284 
          },
3285 
        },
3286 
      },
3287 
      'entityName' => 'reg01_td',
3288 
    },
3289 
    'reg01_tv' => {
3290 
      'connections' => { 'reg01_tv' => '.reg01_tv', },
3291 
      'entity' => {
3292 
        'attributes' => {
3293 
          'entityAlreadyNetlisted' => 1,
3294 
          'isGateway' => 1,
3295 
          'is_floating_block' => 1,
3296 
        },
3297 
        'entityName' => 'reg01_tv',
3298 
        'ports' => {
3299 
          'reg01_tv' => {
3300 
            'attributes' => {
3301 
              'bin_pt' => 0,
3302 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
3303 
              'is_floating_block' => 1,
3304 
              'is_gateway_port' => 1,
3305 
              'must_be_hdl_vector' => 1,
3306 
              'period' => 1,
3307 
              'port_id' => 0,
3308 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
3309 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
3310 
              'timingConstraint' => 'none',
3311 
              'type' => 'Bool',
3312 
            },
3313 
            'direction' => 'out',
3314 
            'hdlType' => 'std_logic',
3315 
            'width' => 1,
3316 
          },
3317 
        },
3318 
      },
3319 
      'entityName' => 'reg01_tv',
3320 
    },
3321 
    'reg02_rd' => {
3322 
      'connections' => { 'reg02_rd' => 'sysgen_dut.reg02_rd', },
3323 
      'entity' => {
3324 
        'attributes' => {
3325 
          'entityAlreadyNetlisted' => 1,
3326 
          'isGateway' => 1,
3327 
          'is_floating_block' => 1,
3328 
        },
3329 
        'entityName' => 'reg02_rd',
3330 
        'ports' => {
3331 
          'reg02_rd' => {
3332 
            'attributes' => {
3333 
              'bin_pt' => 0,
3334 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
3335 
              'is_floating_block' => 1,
3336 
              'is_gateway_port' => 1,
3337 
              'must_be_hdl_vector' => 1,
3338 
              'period' => 1,
3339 
              'port_id' => 0,
3340 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
3341 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
3342 
              'timingConstraint' => 'none',
3343 
              'type' => 'UFix_32_0',
3344 
            },
3345 
            'direction' => 'in',
3346 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3347 
            'width' => 32,
3348 
          },
3349 
        },
3350 
      },
3351 
      'entityName' => 'reg02_rd',
3352 
    },
3353 
    'reg02_rv' => {
3354 
      'connections' => { 'reg02_rv' => 'sysgen_dut.reg02_rv', },
3355 
      'entity' => {
3356 
        'attributes' => {
3357 
          'entityAlreadyNetlisted' => 1,
3358 
          'isGateway' => 1,
3359 
          'is_floating_block' => 1,
3360 
        },
3361 
        'entityName' => 'reg02_rv',
3362 
        'ports' => {
3363 
          'reg02_rv' => {
3364 
            'attributes' => {
3365 
              'bin_pt' => 0,
3366 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
3367 
              'is_floating_block' => 1,
3368 
              'is_gateway_port' => 1,
3369 
              'must_be_hdl_vector' => 1,
3370 
              'period' => 1,
3371 
              'port_id' => 0,
3372 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
3373 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
3374 
              'timingConstraint' => 'none',
3375 
              'type' => 'UFix_1_0',
3376 
            },
3377 
            'direction' => 'in',
3378 
            'hdlType' => 'std_logic',
3379 
            'width' => 1,
3380 
          },
3381 
        },
3382 
      },
3383 
      'entityName' => 'reg02_rv',
3384 
    },
3385 
    'reg02_td' => {
3386 
      'connections' => { 'reg02_td' => '.reg02_td', },
3387 
      'entity' => {
3388 
        'attributes' => {
3389 
          'entityAlreadyNetlisted' => 1,
3390 
          'isGateway' => 1,
3391 
          'is_floating_block' => 1,
3392 
        },
3393 
        'entityName' => 'reg02_td',
3394 
        'ports' => {
3395 
          'reg02_td' => {
3396 
            'attributes' => {
3397 
              'bin_pt' => 0,
3398 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
3399 
              'is_floating_block' => 1,
3400 
              'is_gateway_port' => 1,
3401 
              'must_be_hdl_vector' => 1,
3402 
              'period' => 1,
3403 
              'port_id' => 0,
3404 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
3405 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
3406 
              'timingConstraint' => 'none',
3407 
              'type' => 'UFix_32_0',
3408 
            },
3409 
            'direction' => 'out',
3410 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3411 
            'width' => 32,
3412 
          },
3413 
        },
3414 
      },
3415 
      'entityName' => 'reg02_td',
3416 
    },
3417 
    'reg02_tv' => {
3418 
      'connections' => { 'reg02_tv' => '.reg02_tv', },
3419 
      'entity' => {
3420 
        'attributes' => {
3421 
          'entityAlreadyNetlisted' => 1,
3422 
          'isGateway' => 1,
3423 
          'is_floating_block' => 1,
3424 
        },
3425 
        'entityName' => 'reg02_tv',
3426 
        'ports' => {
3427 
          'reg02_tv' => {
3428 
            'attributes' => {
3429 
              'bin_pt' => 0,
3430 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
3431 
              'is_floating_block' => 1,
3432 
              'is_gateway_port' => 1,
3433 
              'must_be_hdl_vector' => 1,
3434 
              'period' => 1,
3435 
              'port_id' => 0,
3436 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
3437 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
3438 
              'timingConstraint' => 'none',
3439 
              'type' => 'Bool',
3440 
            },
3441 
            'direction' => 'out',
3442 
            'hdlType' => 'std_logic',
3443 
            'width' => 1,
3444 
          },
3445 
        },
3446 
      },
3447 
      'entityName' => 'reg02_tv',
3448 
    },
3449 
    'reg03_rd' => {
3450 
      'connections' => { 'reg03_rd' => 'sysgen_dut.reg03_rd', },
3451 
      'entity' => {
3452 
        'attributes' => {
3453 
          'entityAlreadyNetlisted' => 1,
3454 
          'isGateway' => 1,
3455 
          'is_floating_block' => 1,
3456 
        },
3457 
        'entityName' => 'reg03_rd',
3458 
        'ports' => {
3459 
          'reg03_rd' => {
3460 
            'attributes' => {
3461 
              'bin_pt' => 0,
3462 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
3463 
              'is_floating_block' => 1,
3464 
              'is_gateway_port' => 1,
3465 
              'must_be_hdl_vector' => 1,
3466 
              'period' => 1,
3467 
              'port_id' => 0,
3468 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
3469 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
3470 
              'timingConstraint' => 'none',
3471 
              'type' => 'UFix_32_0',
3472 
            },
3473 
            'direction' => 'in',
3474 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3475 
            'width' => 32,
3476 
          },
3477 
        },
3478 
      },
3479 
      'entityName' => 'reg03_rd',
3480 
    },
3481 
    'reg03_rv' => {
3482 
      'connections' => { 'reg03_rv' => 'sysgen_dut.reg03_rv', },
3483 
      'entity' => {
3484 
        'attributes' => {
3485 
          'entityAlreadyNetlisted' => 1,
3486 
          'isGateway' => 1,
3487 
          'is_floating_block' => 1,
3488 
        },
3489 
        'entityName' => 'reg03_rv',
3490 
        'ports' => {
3491 
          'reg03_rv' => {
3492 
            'attributes' => {
3493 
              'bin_pt' => 0,
3494 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
3495 
              'is_floating_block' => 1,
3496 
              'is_gateway_port' => 1,
3497 
              'must_be_hdl_vector' => 1,
3498 
              'period' => 1,
3499 
              'port_id' => 0,
3500 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
3501 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
3502 
              'timingConstraint' => 'none',
3503 
              'type' => 'UFix_1_0',
3504 
            },
3505 
            'direction' => 'in',
3506 
            'hdlType' => 'std_logic',
3507 
            'width' => 1,
3508 
          },
3509 
        },
3510 
      },
3511 
      'entityName' => 'reg03_rv',
3512 
    },
3513 
    'reg03_td' => {
3514 
      'connections' => { 'reg03_td' => '.reg03_td', },
3515 
      'entity' => {
3516 
        'attributes' => {
3517 
          'entityAlreadyNetlisted' => 1,
3518 
          'isGateway' => 1,
3519 
          'is_floating_block' => 1,
3520 
        },
3521 
        'entityName' => 'reg03_td',
3522 
        'ports' => {
3523 
          'reg03_td' => {
3524 
            'attributes' => {
3525 
              'bin_pt' => 0,
3526 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
3527 
              'is_floating_block' => 1,
3528 
              'is_gateway_port' => 1,
3529 
              'must_be_hdl_vector' => 1,
3530 
              'period' => 1,
3531 
              'port_id' => 0,
3532 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
3533 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
3534 
              'timingConstraint' => 'none',
3535 
              'type' => 'UFix_32_0',
3536 
            },
3537 
            'direction' => 'out',
3538 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3539 
            'width' => 32,
3540 
          },
3541 
        },
3542 
      },
3543 
      'entityName' => 'reg03_td',
3544 
    },
3545 
    'reg03_tv' => {
3546 
      'connections' => { 'reg03_tv' => '.reg03_tv', },
3547 
      'entity' => {
3548 
        'attributes' => {
3549 
          'entityAlreadyNetlisted' => 1,
3550 
          'isGateway' => 1,
3551 
          'is_floating_block' => 1,
3552 
        },
3553 
        'entityName' => 'reg03_tv',
3554 
        'ports' => {
3555 
          'reg03_tv' => {
3556 
            'attributes' => {
3557 
              'bin_pt' => 0,
3558 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
3559 
              'is_floating_block' => 1,
3560 
              'is_gateway_port' => 1,
3561 
              'must_be_hdl_vector' => 1,
3562 
              'period' => 1,
3563 
              'port_id' => 0,
3564 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
3565 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
3566 
              'timingConstraint' => 'none',
3567 
              'type' => 'Bool',
3568 
            },
3569 
            'direction' => 'out',
3570 
            'hdlType' => 'std_logic',
3571 
            'width' => 1,
3572 
          },
3573 
        },
3574 
      },
3575 
      'entityName' => 'reg03_tv',
3576 
    },
3577 
    'reg04_rd' => {
3578 
      'connections' => { 'reg04_rd' => 'sysgen_dut.reg04_rd', },
3579 
      'entity' => {
3580 
        'attributes' => {
3581 
          'entityAlreadyNetlisted' => 1,
3582 
          'isGateway' => 1,
3583 
          'is_floating_block' => 1,
3584 
        },
3585 
        'entityName' => 'reg04_rd',
3586 
        'ports' => {
3587 
          'reg04_rd' => {
3588 
            'attributes' => {
3589 
              'bin_pt' => 0,
3590 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
3591 
              'is_floating_block' => 1,
3592 
              'is_gateway_port' => 1,
3593 
              'must_be_hdl_vector' => 1,
3594 
              'period' => 1,
3595 
              'port_id' => 0,
3596 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
3597 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
3598 
              'timingConstraint' => 'none',
3599 
              'type' => 'UFix_32_0',
3600 
            },
3601 
            'direction' => 'in',
3602 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3603 
            'width' => 32,
3604 
          },
3605 
        },
3606 
      },
3607 
      'entityName' => 'reg04_rd',
3608 
    },
3609 
    'reg04_rv' => {
3610 
      'connections' => { 'reg04_rv' => 'sysgen_dut.reg04_rv', },
3611 
      'entity' => {
3612 
        'attributes' => {
3613 
          'entityAlreadyNetlisted' => 1,
3614 
          'isGateway' => 1,
3615 
          'is_floating_block' => 1,
3616 
        },
3617 
        'entityName' => 'reg04_rv',
3618 
        'ports' => {
3619 
          'reg04_rv' => {
3620 
            'attributes' => {
3621 
              'bin_pt' => 0,
3622 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
3623 
              'is_floating_block' => 1,
3624 
              'is_gateway_port' => 1,
3625 
              'must_be_hdl_vector' => 1,
3626 
              'period' => 1,
3627 
              'port_id' => 0,
3628 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
3629 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
3630 
              'timingConstraint' => 'none',
3631 
              'type' => 'UFix_1_0',
3632 
            },
3633 
            'direction' => 'in',
3634 
            'hdlType' => 'std_logic',
3635 
            'width' => 1,
3636 
          },
3637 
        },
3638 
      },
3639 
      'entityName' => 'reg04_rv',
3640 
    },
3641 
    'reg04_td' => {
3642 
      'connections' => { 'reg04_td' => '.reg04_td', },
3643 
      'entity' => {
3644 
        'attributes' => {
3645 
          'entityAlreadyNetlisted' => 1,
3646 
          'isGateway' => 1,
3647 
          'is_floating_block' => 1,
3648 
        },
3649 
        'entityName' => 'reg04_td',
3650 
        'ports' => {
3651 
          'reg04_td' => {
3652 
            'attributes' => {
3653 
              'bin_pt' => 0,
3654 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
3655 
              'is_floating_block' => 1,
3656 
              'is_gateway_port' => 1,
3657 
              'must_be_hdl_vector' => 1,
3658 
              'period' => 1,
3659 
              'port_id' => 0,
3660 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
3661 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
3662 
              'timingConstraint' => 'none',
3663 
              'type' => 'UFix_32_0',
3664 
            },
3665 
            'direction' => 'out',
3666 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3667 
            'width' => 32,
3668 
          },
3669 
        },
3670 
      },
3671 
      'entityName' => 'reg04_td',
3672 
    },
3673 
    'reg04_tv' => {
3674 
      'connections' => { 'reg04_tv' => '.reg04_tv', },
3675 
      'entity' => {
3676 
        'attributes' => {
3677 
          'entityAlreadyNetlisted' => 1,
3678 
          'isGateway' => 1,
3679 
          'is_floating_block' => 1,
3680 
        },
3681 
        'entityName' => 'reg04_tv',
3682 
        'ports' => {
3683 
          'reg04_tv' => {
3684 
            'attributes' => {
3685 
              'bin_pt' => 0,
3686 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
3687 
              'is_floating_block' => 1,
3688 
              'is_gateway_port' => 1,
3689 
              'must_be_hdl_vector' => 1,
3690 
              'period' => 1,
3691 
              'port_id' => 0,
3692 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
3693 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
3694 
              'timingConstraint' => 'none',
3695 
              'type' => 'Bool',
3696 
            },
3697 
            'direction' => 'out',
3698 
            'hdlType' => 'std_logic',
3699 
            'width' => 1,
3700 
          },
3701 
        },
3702 
      },
3703 
      'entityName' => 'reg04_tv',
3704 
    },
3705 
    'reg05_rd' => {
3706 
      'connections' => { 'reg05_rd' => 'sysgen_dut.reg05_rd', },
3707 
      'entity' => {
3708 
        'attributes' => {
3709 
          'entityAlreadyNetlisted' => 1,
3710 
          'isGateway' => 1,
3711 
          'is_floating_block' => 1,
3712 
        },
3713 
        'entityName' => 'reg05_rd',
3714 
        'ports' => {
3715 
          'reg05_rd' => {
3716 
            'attributes' => {
3717 
              'bin_pt' => 0,
3718 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
3719 
              'is_floating_block' => 1,
3720 
              'is_gateway_port' => 1,
3721 
              'must_be_hdl_vector' => 1,
3722 
              'period' => 1,
3723 
              'port_id' => 0,
3724 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
3725 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
3726 
              'timingConstraint' => 'none',
3727 
              'type' => 'UFix_32_0',
3728 
            },
3729 
            'direction' => 'in',
3730 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3731 
            'width' => 32,
3732 
          },
3733 
        },
3734 
      },
3735 
      'entityName' => 'reg05_rd',
3736 
    },
3737 
    'reg05_rv' => {
3738 
      'connections' => { 'reg05_rv' => 'sysgen_dut.reg05_rv', },
3739 
      'entity' => {
3740 
        'attributes' => {
3741 
          'entityAlreadyNetlisted' => 1,
3742 
          'isGateway' => 1,
3743 
          'is_floating_block' => 1,
3744 
        },
3745 
        'entityName' => 'reg05_rv',
3746 
        'ports' => {
3747 
          'reg05_rv' => {
3748 
            'attributes' => {
3749 
              'bin_pt' => 0,
3750 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
3751 
              'is_floating_block' => 1,
3752 
              'is_gateway_port' => 1,
3753 
              'must_be_hdl_vector' => 1,
3754 
              'period' => 1,
3755 
              'port_id' => 0,
3756 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
3757 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
3758 
              'timingConstraint' => 'none',
3759 
              'type' => 'UFix_1_0',
3760 
            },
3761 
            'direction' => 'in',
3762 
            'hdlType' => 'std_logic',
3763 
            'width' => 1,
3764 
          },
3765 
        },
3766 
      },
3767 
      'entityName' => 'reg05_rv',
3768 
    },
3769 
    'reg05_td' => {
3770 
      'connections' => { 'reg05_td' => '.reg05_td', },
3771 
      'entity' => {
3772 
        'attributes' => {
3773 
          'entityAlreadyNetlisted' => 1,
3774 
          'isGateway' => 1,
3775 
          'is_floating_block' => 1,
3776 
        },
3777 
        'entityName' => 'reg05_td',
3778 
        'ports' => {
3779 
          'reg05_td' => {
3780 
            'attributes' => {
3781 
              'bin_pt' => 0,
3782 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
3783 
              'is_floating_block' => 1,
3784 
              'is_gateway_port' => 1,
3785 
              'must_be_hdl_vector' => 1,
3786 
              'period' => 1,
3787 
              'port_id' => 0,
3788 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
3789 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
3790 
              'timingConstraint' => 'none',
3791 
              'type' => 'UFix_32_0',
3792 
            },
3793 
            'direction' => 'out',
3794 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3795 
            'width' => 32,
3796 
          },
3797 
        },
3798 
      },
3799 
      'entityName' => 'reg05_td',
3800 
    },
3801 
    'reg05_tv' => {
3802 
      'connections' => { 'reg05_tv' => '.reg05_tv', },
3803 
      'entity' => {
3804 
        'attributes' => {
3805 
          'entityAlreadyNetlisted' => 1,
3806 
          'isGateway' => 1,
3807 
          'is_floating_block' => 1,
3808 
        },
3809 
        'entityName' => 'reg05_tv',
3810 
        'ports' => {
3811 
          'reg05_tv' => {
3812 
            'attributes' => {
3813 
              'bin_pt' => 0,
3814 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
3815 
              'is_floating_block' => 1,
3816 
              'is_gateway_port' => 1,
3817 
              'must_be_hdl_vector' => 1,
3818 
              'period' => 1,
3819 
              'port_id' => 0,
3820 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
3821 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
3822 
              'timingConstraint' => 'none',
3823 
              'type' => 'Bool',
3824 
            },
3825 
            'direction' => 'out',
3826 
            'hdlType' => 'std_logic',
3827 
            'width' => 1,
3828 
          },
3829 
        },
3830 
      },
3831 
      'entityName' => 'reg05_tv',
3832 
    },
3833 
    'reg06_rd' => {
3834 
      'connections' => { 'reg06_rd' => 'sysgen_dut.reg06_rd', },
3835 
      'entity' => {
3836 
        'attributes' => {
3837 
          'entityAlreadyNetlisted' => 1,
3838 
          'isGateway' => 1,
3839 
          'is_floating_block' => 1,
3840 
        },
3841 
        'entityName' => 'reg06_rd',
3842 
        'ports' => {
3843 
          'reg06_rd' => {
3844 
            'attributes' => {
3845 
              'bin_pt' => 0,
3846 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
3847 
              'is_floating_block' => 1,
3848 
              'is_gateway_port' => 1,
3849 
              'must_be_hdl_vector' => 1,
3850 
              'period' => 1,
3851 
              'port_id' => 0,
3852 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
3853 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
3854 
              'timingConstraint' => 'none',
3855 
              'type' => 'UFix_32_0',
3856 
            },
3857 
            'direction' => 'in',
3858 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3859 
            'width' => 32,
3860 
          },
3861 
        },
3862 
      },
3863 
      'entityName' => 'reg06_rd',
3864 
    },
3865 
    'reg06_rv' => {
3866 
      'connections' => { 'reg06_rv' => 'sysgen_dut.reg06_rv', },
3867 
      'entity' => {
3868 
        'attributes' => {
3869 
          'entityAlreadyNetlisted' => 1,
3870 
          'isGateway' => 1,
3871 
          'is_floating_block' => 1,
3872 
        },
3873 
        'entityName' => 'reg06_rv',
3874 
        'ports' => {
3875 
          'reg06_rv' => {
3876 
            'attributes' => {
3877 
              'bin_pt' => 0,
3878 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
3879 
              'is_floating_block' => 1,
3880 
              'is_gateway_port' => 1,
3881 
              'must_be_hdl_vector' => 1,
3882 
              'period' => 1,
3883 
              'port_id' => 0,
3884 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
3885 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
3886 
              'timingConstraint' => 'none',
3887 
              'type' => 'UFix_1_0',
3888 
            },
3889 
            'direction' => 'in',
3890 
            'hdlType' => 'std_logic',
3891 
            'width' => 1,
3892 
          },
3893 
        },
3894 
      },
3895 
      'entityName' => 'reg06_rv',
3896 
    },
3897 
    'reg06_td' => {
3898 
      'connections' => { 'reg06_td' => '.reg06_td', },
3899 
      'entity' => {
3900 
        'attributes' => {
3901 
          'entityAlreadyNetlisted' => 1,
3902 
          'isGateway' => 1,
3903 
          'is_floating_block' => 1,
3904 
        },
3905 
        'entityName' => 'reg06_td',
3906 
        'ports' => {
3907 
          'reg06_td' => {
3908 
            'attributes' => {
3909 
              'bin_pt' => 0,
3910 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
3911 
              'is_floating_block' => 1,
3912 
              'is_gateway_port' => 1,
3913 
              'must_be_hdl_vector' => 1,
3914 
              'period' => 1,
3915 
              'port_id' => 0,
3916 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
3917 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
3918 
              'timingConstraint' => 'none',
3919 
              'type' => 'UFix_32_0',
3920 
            },
3921 
            'direction' => 'out',
3922 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3923 
            'width' => 32,
3924 
          },
3925 
        },
3926 
      },
3927 
      'entityName' => 'reg06_td',
3928 
    },
3929 
    'reg06_tv' => {
3930 
      'connections' => { 'reg06_tv' => '.reg06_tv', },
3931 
      'entity' => {
3932 
        'attributes' => {
3933 
          'entityAlreadyNetlisted' => 1,
3934 
          'isGateway' => 1,
3935 
          'is_floating_block' => 1,
3936 
        },
3937 
        'entityName' => 'reg06_tv',
3938 
        'ports' => {
3939 
          'reg06_tv' => {
3940 
            'attributes' => {
3941 
              'bin_pt' => 0,
3942 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
3943 
              'is_floating_block' => 1,
3944 
              'is_gateway_port' => 1,
3945 
              'must_be_hdl_vector' => 1,
3946 
              'period' => 1,
3947 
              'port_id' => 0,
3948 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
3949 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
3950 
              'timingConstraint' => 'none',
3951 
              'type' => 'Bool',
3952 
            },
3953 
            'direction' => 'out',
3954 
            'hdlType' => 'std_logic',
3955 
            'width' => 1,
3956 
          },
3957 
        },
3958 
      },
3959 
      'entityName' => 'reg06_tv',
3960 
    },
3961 
    'reg07_rd' => {
3962 
      'connections' => { 'reg07_rd' => 'sysgen_dut.reg07_rd', },
3963 
      'entity' => {
3964 
        'attributes' => {
3965 
          'entityAlreadyNetlisted' => 1,
3966 
          'isGateway' => 1,
3967 
          'is_floating_block' => 1,
3968 
        },
3969 
        'entityName' => 'reg07_rd',
3970 
        'ports' => {
3971 
          'reg07_rd' => {
3972 
            'attributes' => {
3973 
              'bin_pt' => 0,
3974 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
3975 
              'is_floating_block' => 1,
3976 
              'is_gateway_port' => 1,
3977 
              'must_be_hdl_vector' => 1,
3978 
              'period' => 1,
3979 
              'port_id' => 0,
3980 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
3981 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
3982 
              'timingConstraint' => 'none',
3983 
              'type' => 'UFix_32_0',
3984 
            },
3985 
            'direction' => 'in',
3986 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3987 
            'width' => 32,
3988 
          },
3989 
        },
3990 
      },
3991 
      'entityName' => 'reg07_rd',
3992 
    },
3993 
    'reg07_rv' => {
3994 
      'connections' => { 'reg07_rv' => 'sysgen_dut.reg07_rv', },
3995 
      'entity' => {
3996 
        'attributes' => {
3997 
          'entityAlreadyNetlisted' => 1,
3998 
          'isGateway' => 1,
3999 
          'is_floating_block' => 1,
4000 
        },
4001 
        'entityName' => 'reg07_rv',
4002 
        'ports' => {
4003 
          'reg07_rv' => {
4004 
            'attributes' => {
4005 
              'bin_pt' => 0,
4006 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
4007 
              'is_floating_block' => 1,
4008 
              'is_gateway_port' => 1,
4009 
              'must_be_hdl_vector' => 1,
4010 
              'period' => 1,
4011 
              'port_id' => 0,
4012 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
4013 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
4014 
              'timingConstraint' => 'none',
4015 
              'type' => 'UFix_1_0',
4016 
            },
4017 
            'direction' => 'in',
4018 
            'hdlType' => 'std_logic',
4019 
            'width' => 1,
4020 
          },
4021 
        },
4022 
      },
4023 
      'entityName' => 'reg07_rv',
4024 
    },
4025 
    'reg07_td' => {
4026 
      'connections' => { 'reg07_td' => '.reg07_td', },
4027 
      'entity' => {
4028 
        'attributes' => {
4029 
          'entityAlreadyNetlisted' => 1,
4030 
          'isGateway' => 1,
4031 
          'is_floating_block' => 1,
4032 
        },
4033 
        'entityName' => 'reg07_td',
4034 
        'ports' => {
4035 
          'reg07_td' => {
4036 
            'attributes' => {
4037 
              'bin_pt' => 0,
4038 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
4039 
              'is_floating_block' => 1,
4040 
              'is_gateway_port' => 1,
4041 
              'must_be_hdl_vector' => 1,
4042 
              'period' => 1,
4043 
              'port_id' => 0,
4044 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
4045 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
4046 
              'timingConstraint' => 'none',
4047 
              'type' => 'UFix_32_0',
4048 
            },
4049 
            'direction' => 'out',
4050 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4051 
            'width' => 32,
4052 
          },
4053 
        },
4054 
      },
4055 
      'entityName' => 'reg07_td',
4056 
    },
4057 
    'reg07_tv' => {
4058 
      'connections' => { 'reg07_tv' => '.reg07_tv', },
4059 
      'entity' => {
4060 
        'attributes' => {
4061 
          'entityAlreadyNetlisted' => 1,
4062 
          'isGateway' => 1,
4063 
          'is_floating_block' => 1,
4064 
        },
4065 
        'entityName' => 'reg07_tv',
4066 
        'ports' => {
4067 
          'reg07_tv' => {
4068 
            'attributes' => {
4069 
              'bin_pt' => 0,
4070 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
4071 
              'is_floating_block' => 1,
4072 
              'is_gateway_port' => 1,
4073 
              'must_be_hdl_vector' => 1,
4074 
              'period' => 1,
4075 
              'port_id' => 0,
4076 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
4077 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
4078 
              'timingConstraint' => 'none',
4079 
              'type' => 'Bool',
4080 
            },
4081 
            'direction' => 'out',
4082 
            'hdlType' => 'std_logic',
4083 
            'width' => 1,
4084 
          },
4085 
        },
4086 
      },
4087 
      'entityName' => 'reg07_tv',
4088 
    },
4089 
    'reg08_rd' => {
4090 
      'connections' => { 'reg08_rd' => 'sysgen_dut.reg08_rd', },
4091 
      'entity' => {
4092 
        'attributes' => {
4093 
          'entityAlreadyNetlisted' => 1,
4094 
          'isGateway' => 1,
4095 
          'is_floating_block' => 1,
4096 
        },
4097 
        'entityName' => 'reg08_rd',
4098 
        'ports' => {
4099 
          'reg08_rd' => {
4100 
            'attributes' => {
4101 
              'bin_pt' => 0,
4102 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
4103 
              'is_floating_block' => 1,
4104 
              'is_gateway_port' => 1,
4105 
              'must_be_hdl_vector' => 1,
4106 
              'period' => 1,
4107 
              'port_id' => 0,
4108 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
4109 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
4110 
              'timingConstraint' => 'none',
4111 
              'type' => 'UFix_32_0',
4112 
            },
4113 
            'direction' => 'in',
4114 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4115 
            'width' => 32,
4116 
          },
4117 
        },
4118 
      },
4119 
      'entityName' => 'reg08_rd',
4120 
    },
4121 
    'reg08_rv' => {
4122 
      'connections' => { 'reg08_rv' => 'sysgen_dut.reg08_rv', },
4123 
      'entity' => {
4124 
        'attributes' => {
4125 
          'entityAlreadyNetlisted' => 1,
4126 
          'isGateway' => 1,
4127 
          'is_floating_block' => 1,
4128 
        },
4129 
        'entityName' => 'reg08_rv',
4130 
        'ports' => {
4131 
          'reg08_rv' => {
4132 
            'attributes' => {
4133 
              'bin_pt' => 0,
4134 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
4135 
              'is_floating_block' => 1,
4136 
              'is_gateway_port' => 1,
4137 
              'must_be_hdl_vector' => 1,
4138 
              'period' => 1,
4139 
              'port_id' => 0,
4140 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
4141 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
4142 
              'timingConstraint' => 'none',
4143 
              'type' => 'UFix_1_0',
4144 
            },
4145 
            'direction' => 'in',
4146 
            'hdlType' => 'std_logic',
4147 
            'width' => 1,
4148 
          },
4149 
        },
4150 
      },
4151 
      'entityName' => 'reg08_rv',
4152 
    },
4153 
    'reg08_td' => {
4154 
      'connections' => { 'reg08_td' => '.reg08_td', },
4155 
      'entity' => {
4156 
        'attributes' => {
4157 
          'entityAlreadyNetlisted' => 1,
4158 
          'isGateway' => 1,
4159 
          'is_floating_block' => 1,
4160 
        },
4161 
        'entityName' => 'reg08_td',
4162 
        'ports' => {
4163 
          'reg08_td' => {
4164 
            'attributes' => {
4165 
              'bin_pt' => 0,
4166 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
4167 
              'is_floating_block' => 1,
4168 
              'is_gateway_port' => 1,
4169 
              'must_be_hdl_vector' => 1,
4170 
              'period' => 1,
4171 
              'port_id' => 0,
4172 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
4173 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
4174 
              'timingConstraint' => 'none',
4175 
              'type' => 'UFix_32_0',
4176 
            },
4177 
            'direction' => 'out',
4178 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4179 
            'width' => 32,
4180 
          },
4181 
        },
4182 
      },
4183 
      'entityName' => 'reg08_td',
4184 
    },
4185 
    'reg08_tv' => {
4186 
      'connections' => { 'reg08_tv' => '.reg08_tv', },
4187 
      'entity' => {
4188 
        'attributes' => {
4189 
          'entityAlreadyNetlisted' => 1,
4190 
          'isGateway' => 1,
4191 
          'is_floating_block' => 1,
4192 
        },
4193 
        'entityName' => 'reg08_tv',
4194 
        'ports' => {
4195 
          'reg08_tv' => {
4196 
            'attributes' => {
4197 
              'bin_pt' => 0,
4198 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
4199 
              'is_floating_block' => 1,
4200 
              'is_gateway_port' => 1,
4201 
              'must_be_hdl_vector' => 1,
4202 
              'period' => 1,
4203 
              'port_id' => 0,
4204 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
4205 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
4206 
              'timingConstraint' => 'none',
4207 
              'type' => 'Bool',
4208 
            },
4209 
            'direction' => 'out',
4210 
            'hdlType' => 'std_logic',
4211 
            'width' => 1,
4212 
          },
4213 
        },
4214 
      },
4215 
      'entityName' => 'reg08_tv',
4216 
    },
4217 
    'reg09_rd' => {
4218 
      'connections' => { 'reg09_rd' => 'sysgen_dut.reg09_rd', },
4219 
      'entity' => {
4220 
        'attributes' => {
4221 
          'entityAlreadyNetlisted' => 1,
4222 
          'isGateway' => 1,
4223 
          'is_floating_block' => 1,
4224 
        },
4225 
        'entityName' => 'reg09_rd',
4226 
        'ports' => {
4227 
          'reg09_rd' => {
4228 
            'attributes' => {
4229 
              'bin_pt' => 0,
4230 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
4231 
              'is_floating_block' => 1,
4232 
              'is_gateway_port' => 1,
4233 
              'must_be_hdl_vector' => 1,
4234 
              'period' => 1,
4235 
              'port_id' => 0,
4236 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
4237 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
4238 
              'timingConstraint' => 'none',
4239 
              'type' => 'UFix_32_0',
4240 
            },
4241 
            'direction' => 'in',
4242 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4243 
            'width' => 32,
4244 
          },
4245 
        },
4246 
      },
4247 
      'entityName' => 'reg09_rd',
4248 
    },
4249 
    'reg09_rv' => {
4250 
      'connections' => { 'reg09_rv' => 'sysgen_dut.reg09_rv', },
4251 
      'entity' => {
4252 
        'attributes' => {
4253 
          'entityAlreadyNetlisted' => 1,
4254 
          'isGateway' => 1,
4255 
          'is_floating_block' => 1,
4256 
        },
4257 
        'entityName' => 'reg09_rv',
4258 
        'ports' => {
4259 
          'reg09_rv' => {
4260 
            'attributes' => {
4261 
              'bin_pt' => 0,
4262 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
4263 
              'is_floating_block' => 1,
4264 
              'is_gateway_port' => 1,
4265 
              'must_be_hdl_vector' => 1,
4266 
              'period' => 1,
4267 
              'port_id' => 0,
4268 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
4269 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
4270 
              'timingConstraint' => 'none',
4271 
              'type' => 'UFix_1_0',
4272 
            },
4273 
            'direction' => 'in',
4274 
            'hdlType' => 'std_logic',
4275 
            'width' => 1,
4276 
          },
4277 
        },
4278 
      },
4279 
      'entityName' => 'reg09_rv',
4280 
    },
4281 
    'reg09_td' => {
4282 
      'connections' => { 'reg09_td' => '.reg09_td', },
4283 
      'entity' => {
4284 
        'attributes' => {
4285 
          'entityAlreadyNetlisted' => 1,
4286 
          'isGateway' => 1,
4287 
          'is_floating_block' => 1,
4288 
        },
4289 
        'entityName' => 'reg09_td',
4290 
        'ports' => {
4291 
          'reg09_td' => {
4292 
            'attributes' => {
4293 
              'bin_pt' => 0,
4294 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
4295 
              'is_floating_block' => 1,
4296 
              'is_gateway_port' => 1,
4297 
              'must_be_hdl_vector' => 1,
4298 
              'period' => 1,
4299 
              'port_id' => 0,
4300 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
4301 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
4302 
              'timingConstraint' => 'none',
4303 
              'type' => 'UFix_32_0',
4304 
            },
4305 
            'direction' => 'out',
4306 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4307 
            'width' => 32,
4308 
          },
4309 
        },
4310 
      },
4311 
      'entityName' => 'reg09_td',
4312 
    },
4313 
    'reg09_tv' => {
4314 
      'connections' => { 'reg09_tv' => '.reg09_tv', },
4315 
      'entity' => {
4316 
        'attributes' => {
4317 
          'entityAlreadyNetlisted' => 1,
4318 
          'isGateway' => 1,
4319 
          'is_floating_block' => 1,
4320 
        },
4321 
        'entityName' => 'reg09_tv',
4322 
        'ports' => {
4323 
          'reg09_tv' => {
4324 
            'attributes' => {
4325 
              'bin_pt' => 0,
4326 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
4327 
              'is_floating_block' => 1,
4328 
              'is_gateway_port' => 1,
4329 
              'must_be_hdl_vector' => 1,
4330 
              'period' => 1,
4331 
              'port_id' => 0,
4332 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
4333 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
4334 
              'timingConstraint' => 'none',
4335 
              'type' => 'Bool',
4336 
            },
4337 
            'direction' => 'out',
4338 
            'hdlType' => 'std_logic',
4339 
            'width' => 1,
4340 
          },
4341 
        },
4342 
      },
4343 
      'entityName' => 'reg09_tv',
4344 
    },
4345 
    'reg10_rd' => {
4346 
      'connections' => { 'reg10_rd' => 'sysgen_dut.reg10_rd', },
4347 
      'entity' => {
4348 
        'attributes' => {
4349 
          'entityAlreadyNetlisted' => 1,
4350 
          'isGateway' => 1,
4351 
          'is_floating_block' => 1,
4352 
        },
4353 
        'entityName' => 'reg10_rd',
4354 
        'ports' => {
4355 
          'reg10_rd' => {
4356 
            'attributes' => {
4357 
              'bin_pt' => 0,
4358 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
4359 
              'is_floating_block' => 1,
4360 
              'is_gateway_port' => 1,
4361 
              'must_be_hdl_vector' => 1,
4362 
              'period' => 1,
4363 
              'port_id' => 0,
4364 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
4365 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
4366 
              'timingConstraint' => 'none',
4367 
              'type' => 'UFix_32_0',
4368 
            },
4369 
            'direction' => 'in',
4370 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4371 
            'width' => 32,
4372 
          },
4373 
        },
4374 
      },
4375 
      'entityName' => 'reg10_rd',
4376 
    },
4377 
    'reg10_rv' => {
4378 
      'connections' => { 'reg10_rv' => 'sysgen_dut.reg10_rv', },
4379 
      'entity' => {
4380 
        'attributes' => {
4381 
          'entityAlreadyNetlisted' => 1,
4382 
          'isGateway' => 1,
4383 
          'is_floating_block' => 1,
4384 
        },
4385 
        'entityName' => 'reg10_rv',
4386 
        'ports' => {
4387 
          'reg10_rv' => {
4388 
            'attributes' => {
4389 
              'bin_pt' => 0,
4390 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
4391 
              'is_floating_block' => 1,
4392 
              'is_gateway_port' => 1,
4393 
              'must_be_hdl_vector' => 1,
4394 
              'period' => 1,
4395 
              'port_id' => 0,
4396 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
4397 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
4398 
              'timingConstraint' => 'none',
4399 
              'type' => 'UFix_1_0',
4400 
            },
4401 
            'direction' => 'in',
4402 
            'hdlType' => 'std_logic',
4403 
            'width' => 1,
4404 
          },
4405 
        },
4406 
      },
4407 
      'entityName' => 'reg10_rv',
4408 
    },
4409 
    'reg10_td' => {
4410 
      'connections' => { 'reg10_td' => '.reg10_td', },
4411 
      'entity' => {
4412 
        'attributes' => {
4413 
          'entityAlreadyNetlisted' => 1,
4414 
          'isGateway' => 1,
4415 
          'is_floating_block' => 1,
4416 
        },
4417 
        'entityName' => 'reg10_td',
4418 
        'ports' => {
4419 
          'reg10_td' => {
4420 
            'attributes' => {
4421 
              'bin_pt' => 0,
4422 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
4423 
              'is_floating_block' => 1,
4424 
              'is_gateway_port' => 1,
4425 
              'must_be_hdl_vector' => 1,
4426 
              'period' => 1,
4427 
              'port_id' => 0,
4428 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
4429 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
4430 
              'timingConstraint' => 'none',
4431 
              'type' => 'UFix_32_0',
4432 
            },
4433 
            'direction' => 'out',
4434 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4435 
            'width' => 32,
4436 
          },
4437 
        },
4438 
      },
4439 
      'entityName' => 'reg10_td',
4440 
    },
4441 
    'reg10_tv' => {
4442 
      'connections' => { 'reg10_tv' => '.reg10_tv', },
4443 
      'entity' => {
4444 
        'attributes' => {
4445 
          'entityAlreadyNetlisted' => 1,
4446 
          'isGateway' => 1,
4447 
          'is_floating_block' => 1,
4448 
        },
4449 
        'entityName' => 'reg10_tv',
4450 
        'ports' => {
4451 
          'reg10_tv' => {
4452 
            'attributes' => {
4453 
              'bin_pt' => 0,
4454 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
4455 
              'is_floating_block' => 1,
4456 
              'is_gateway_port' => 1,
4457 
              'must_be_hdl_vector' => 1,
4458 
              'period' => 1,
4459 
              'port_id' => 0,
4460 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
4461 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
4462 
              'timingConstraint' => 'none',
4463 
              'type' => 'Bool',
4464 
            },
4465 
            'direction' => 'out',
4466 
            'hdlType' => 'std_logic',
4467 
            'width' => 1,
4468 
          },
4469 
        },
4470 
      },
4471 
      'entityName' => 'reg10_tv',
4472 
    },
4473 
    'reg11_rd' => {
4474 
      'connections' => { 'reg11_rd' => 'sysgen_dut.reg11_rd', },
4475 
      'entity' => {
4476 
        'attributes' => {
4477 
          'entityAlreadyNetlisted' => 1,
4478 
          'isGateway' => 1,
4479 
          'is_floating_block' => 1,
4480 
        },
4481 
        'entityName' => 'reg11_rd',
4482 
        'ports' => {
4483 
          'reg11_rd' => {
4484 
            'attributes' => {
4485 
              'bin_pt' => 0,
4486 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
4487 
              'is_floating_block' => 1,
4488 
              'is_gateway_port' => 1,
4489 
              'must_be_hdl_vector' => 1,
4490 
              'period' => 1,
4491 
              'port_id' => 0,
4492 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
4493 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
4494 
              'timingConstraint' => 'none',
4495 
              'type' => 'UFix_32_0',
4496 
            },
4497 
            'direction' => 'in',
4498 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4499 
            'width' => 32,
4500 
          },
4501 
        },
4502 
      },
4503 
      'entityName' => 'reg11_rd',
4504 
    },
4505 
    'reg11_rv' => {
4506 
      'connections' => { 'reg11_rv' => 'sysgen_dut.reg11_rv', },
4507 
      'entity' => {
4508 
        'attributes' => {
4509 
          'entityAlreadyNetlisted' => 1,
4510 
          'isGateway' => 1,
4511 
          'is_floating_block' => 1,
4512 
        },
4513 
        'entityName' => 'reg11_rv',
4514 
        'ports' => {
4515 
          'reg11_rv' => {
4516 
            'attributes' => {
4517 
              'bin_pt' => 0,
4518 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
4519 
              'is_floating_block' => 1,
4520 
              'is_gateway_port' => 1,
4521 
              'must_be_hdl_vector' => 1,
4522 
              'period' => 1,
4523 
              'port_id' => 0,
4524 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
4525 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
4526 
              'timingConstraint' => 'none',
4527 
              'type' => 'UFix_1_0',
4528 
            },
4529 
            'direction' => 'in',
4530 
            'hdlType' => 'std_logic',
4531 
            'width' => 1,
4532 
          },
4533 
        },
4534 
      },
4535 
      'entityName' => 'reg11_rv',
4536 
    },
4537 
    'reg11_td' => {
4538 
      'connections' => { 'reg11_td' => '.reg11_td', },
4539 
      'entity' => {
4540 
        'attributes' => {
4541 
          'entityAlreadyNetlisted' => 1,
4542 
          'isGateway' => 1,
4543 
          'is_floating_block' => 1,
4544 
        },
4545 
        'entityName' => 'reg11_td',
4546 
        'ports' => {
4547 
          'reg11_td' => {
4548 
            'attributes' => {
4549 
              'bin_pt' => 0,
4550 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
4551 
              'is_floating_block' => 1,
4552 
              'is_gateway_port' => 1,
4553 
              'must_be_hdl_vector' => 1,
4554 
              'period' => 1,
4555 
              'port_id' => 0,
4556 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
4557 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
4558 
              'timingConstraint' => 'none',
4559 
              'type' => 'UFix_32_0',
4560 
            },
4561 
            'direction' => 'out',
4562 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4563 
            'width' => 32,
4564 
          },
4565 
        },
4566 
      },
4567 
      'entityName' => 'reg11_td',
4568 
    },
4569 
    'reg11_tv' => {
4570 
      'connections' => { 'reg11_tv' => '.reg11_tv', },
4571 
      'entity' => {
4572 
        'attributes' => {
4573 
          'entityAlreadyNetlisted' => 1,
4574 
          'isGateway' => 1,
4575 
          'is_floating_block' => 1,
4576 
        },
4577 
        'entityName' => 'reg11_tv',
4578 
        'ports' => {
4579 
          'reg11_tv' => {
4580 
            'attributes' => {
4581 
              'bin_pt' => 0,
4582 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
4583 
              'is_floating_block' => 1,
4584 
              'is_gateway_port' => 1,
4585 
              'must_be_hdl_vector' => 1,
4586 
              'period' => 1,
4587 
              'port_id' => 0,
4588 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
4589 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
4590 
              'timingConstraint' => 'none',
4591 
              'type' => 'Bool',
4592 
            },
4593 
            'direction' => 'out',
4594 
            'hdlType' => 'std_logic',
4595 
            'width' => 1,
4596 
          },
4597 
        },
4598 
      },
4599 
      'entityName' => 'reg11_tv',
4600 
    },
4601 
    'reg12_rd' => {
4602 
      'connections' => { 'reg12_rd' => 'sysgen_dut.reg12_rd', },
4603 
      'entity' => {
4604 
        'attributes' => {
4605 
          'entityAlreadyNetlisted' => 1,
4606 
          'isGateway' => 1,
4607 
          'is_floating_block' => 1,
4608 
        },
4609 
        'entityName' => 'reg12_rd',
4610 
        'ports' => {
4611 
          'reg12_rd' => {
4612 
            'attributes' => {
4613 
              'bin_pt' => 0,
4614 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
4615 
              'is_floating_block' => 1,
4616 
              'is_gateway_port' => 1,
4617 
              'must_be_hdl_vector' => 1,
4618 
              'period' => 1,
4619 
              'port_id' => 0,
4620 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
4621 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
4622 
              'timingConstraint' => 'none',
4623 
              'type' => 'UFix_32_0',
4624 
            },
4625 
            'direction' => 'in',
4626 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4627 
            'width' => 32,
4628 
          },
4629 
        },
4630 
      },
4631 
      'entityName' => 'reg12_rd',
4632 
    },
4633 
    'reg12_rv' => {
4634 
      'connections' => { 'reg12_rv' => 'sysgen_dut.reg12_rv', },
4635 
      'entity' => {
4636 
        'attributes' => {
4637 
          'entityAlreadyNetlisted' => 1,
4638 
          'isGateway' => 1,
4639 
          'is_floating_block' => 1,
4640 
        },
4641 
        'entityName' => 'reg12_rv',
4642 
        'ports' => {
4643 
          'reg12_rv' => {
4644 
            'attributes' => {
4645 
              'bin_pt' => 0,
4646 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
4647 
              'is_floating_block' => 1,
4648 
              'is_gateway_port' => 1,
4649 
              'must_be_hdl_vector' => 1,
4650 
              'period' => 1,
4651 
              'port_id' => 0,
4652 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
4653 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
4654 
              'timingConstraint' => 'none',
4655 
              'type' => 'UFix_1_0',
4656 
            },
4657 
            'direction' => 'in',
4658 
            'hdlType' => 'std_logic',
4659 
            'width' => 1,
4660 
          },
4661 
        },
4662 
      },
4663 
      'entityName' => 'reg12_rv',
4664 
    },
4665 
    'reg12_td' => {
4666 
      'connections' => { 'reg12_td' => '.reg12_td', },
4667 
      'entity' => {
4668 
        'attributes' => {
4669 
          'entityAlreadyNetlisted' => 1,
4670 
          'isGateway' => 1,
4671 
          'is_floating_block' => 1,
4672 
        },
4673 
        'entityName' => 'reg12_td',
4674 
        'ports' => {
4675 
          'reg12_td' => {
4676 
            'attributes' => {
4677 
              'bin_pt' => 0,
4678 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
4679 
              'is_floating_block' => 1,
4680 
              'is_gateway_port' => 1,
4681 
              'must_be_hdl_vector' => 1,
4682 
              'period' => 1,
4683 
              'port_id' => 0,
4684 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
4685 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
4686 
              'timingConstraint' => 'none',
4687 
              'type' => 'UFix_32_0',
4688 
            },
4689 
            'direction' => 'out',
4690 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4691 
            'width' => 32,
4692 
          },
4693 
        },
4694 
      },
4695 
      'entityName' => 'reg12_td',
4696 
    },
4697 
    'reg12_tv' => {
4698 
      'connections' => { 'reg12_tv' => '.reg12_tv', },
4699 
      'entity' => {
4700 
        'attributes' => {
4701 
          'entityAlreadyNetlisted' => 1,
4702 
          'isGateway' => 1,
4703 
          'is_floating_block' => 1,
4704 
        },
4705 
        'entityName' => 'reg12_tv',
4706 
        'ports' => {
4707 
          'reg12_tv' => {
4708 
            'attributes' => {
4709 
              'bin_pt' => 0,
4710 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
4711 
              'is_floating_block' => 1,
4712 
              'is_gateway_port' => 1,
4713 
              'must_be_hdl_vector' => 1,
4714 
              'period' => 1,
4715 
              'port_id' => 0,
4716 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
4717 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
4718 
              'timingConstraint' => 'none',
4719 
              'type' => 'Bool',
4720 
            },
4721 
            'direction' => 'out',
4722 
            'hdlType' => 'std_logic',
4723 
            'width' => 1,
4724 
          },
4725 
        },
4726 
      },
4727 
      'entityName' => 'reg12_tv',
4728 
    },
4729 
    'reg13_rd' => {
4730 
      'connections' => { 'reg13_rd' => 'sysgen_dut.reg13_rd', },
4731 
      'entity' => {
4732 
        'attributes' => {
4733 
          'entityAlreadyNetlisted' => 1,
4734 
          'isGateway' => 1,
4735 
          'is_floating_block' => 1,
4736 
        },
4737 
        'entityName' => 'reg13_rd',
4738 
        'ports' => {
4739 
          'reg13_rd' => {
4740 
            'attributes' => {
4741 
              'bin_pt' => 0,
4742 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
4743 
              'is_floating_block' => 1,
4744 
              'is_gateway_port' => 1,
4745 
              'must_be_hdl_vector' => 1,
4746 
              'period' => 1,
4747 
              'port_id' => 0,
4748 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
4749 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
4750 
              'timingConstraint' => 'none',
4751 
              'type' => 'UFix_32_0',
4752 
            },
4753 
            'direction' => 'in',
4754 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4755 
            'width' => 32,
4756 
          },
4757 
        },
4758 
      },
4759 
      'entityName' => 'reg13_rd',
4760 
    },
4761 
    'reg13_rv' => {
4762 
      'connections' => { 'reg13_rv' => 'sysgen_dut.reg13_rv', },
4763 
      'entity' => {
4764 
        'attributes' => {
4765 
          'entityAlreadyNetlisted' => 1,
4766 
          'isGateway' => 1,
4767 
          'is_floating_block' => 1,
4768 
        },
4769 
        'entityName' => 'reg13_rv',
4770 
        'ports' => {
4771 
          'reg13_rv' => {
4772 
            'attributes' => {
4773 
              'bin_pt' => 0,
4774 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
4775 
              'is_floating_block' => 1,
4776 
              'is_gateway_port' => 1,
4777 
              'must_be_hdl_vector' => 1,
4778 
              'period' => 1,
4779 
              'port_id' => 0,
4780 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
4781 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
4782 
              'timingConstraint' => 'none',
4783 
              'type' => 'UFix_1_0',
4784 
            },
4785 
            'direction' => 'in',
4786 
            'hdlType' => 'std_logic',
4787 
            'width' => 1,
4788 
          },
4789 
        },
4790 
      },
4791 
      'entityName' => 'reg13_rv',
4792 
    },
4793 
    'reg13_td' => {
4794 
      'connections' => { 'reg13_td' => '.reg13_td', },
4795 
      'entity' => {
4796 
        'attributes' => {
4797 
          'entityAlreadyNetlisted' => 1,
4798 
          'isGateway' => 1,
4799 
          'is_floating_block' => 1,
4800 
        },
4801 
        'entityName' => 'reg13_td',
4802 
        'ports' => {
4803 
          'reg13_td' => {
4804 
            'attributes' => {
4805 
              'bin_pt' => 0,
4806 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
4807 
              'is_floating_block' => 1,
4808 
              'is_gateway_port' => 1,
4809 
              'must_be_hdl_vector' => 1,
4810 
              'period' => 1,
4811 
              'port_id' => 0,
4812 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
4813 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
4814 
              'timingConstraint' => 'none',
4815 
              'type' => 'UFix_32_0',
4816 
            },
4817 
            'direction' => 'out',
4818 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4819 
            'width' => 32,
4820 
          },
4821 
        },
4822 
      },
4823 
      'entityName' => 'reg13_td',
4824 
    },
4825 
    'reg13_tv' => {
4826 
      'connections' => { 'reg13_tv' => '.reg13_tv', },
4827 
      'entity' => {
4828 
        'attributes' => {
4829 
          'entityAlreadyNetlisted' => 1,
4830 
          'isGateway' => 1,
4831 
          'is_floating_block' => 1,
4832 
        },
4833 
        'entityName' => 'reg13_tv',
4834 
        'ports' => {
4835 
          'reg13_tv' => {
4836 
            'attributes' => {
4837 
              'bin_pt' => 0,
4838 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
4839 
              'is_floating_block' => 1,
4840 
              'is_gateway_port' => 1,
4841 
              'must_be_hdl_vector' => 1,
4842 
              'period' => 1,
4843 
              'port_id' => 0,
4844 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
4845 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
4846 
              'timingConstraint' => 'none',
4847 
              'type' => 'Bool',
4848 
            },
4849 
            'direction' => 'out',
4850 
            'hdlType' => 'std_logic',
4851 
            'width' => 1,
4852 
          },
4853 
        },
4854 
      },
4855 
      'entityName' => 'reg13_tv',
4856 
    },
4857 
    'reg14_rd' => {
4858 
      'connections' => { 'reg14_rd' => 'sysgen_dut.reg14_rd', },
4859 
      'entity' => {
4860 
        'attributes' => {
4861 
          'entityAlreadyNetlisted' => 1,
4862 
          'isGateway' => 1,
4863 
          'is_floating_block' => 1,
4864 
        },
4865 
        'entityName' => 'reg14_rd',
4866 
        'ports' => {
4867 
          'reg14_rd' => {
4868 
            'attributes' => {
4869 
              'bin_pt' => 0,
4870 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
4871 
              'is_floating_block' => 1,
4872 
              'is_gateway_port' => 1,
4873 
              'must_be_hdl_vector' => 1,
4874 
              'period' => 1,
4875 
              'port_id' => 0,
4876 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
4877 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
4878 
              'timingConstraint' => 'none',
4879 
              'type' => 'UFix_32_0',
4880 
            },
4881 
            'direction' => 'in',
4882 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4883 
            'width' => 32,
4884 
          },
4885 
        },
4886 
      },
4887 
      'entityName' => 'reg14_rd',
4888 
    },
4889 
    'reg14_rv' => {
4890 
      'connections' => { 'reg14_rv' => 'sysgen_dut.reg14_rv', },
4891 
      'entity' => {
4892 
        'attributes' => {
4893 
          'entityAlreadyNetlisted' => 1,
4894 
          'isGateway' => 1,
4895 
          'is_floating_block' => 1,
4896 
        },
4897 
        'entityName' => 'reg14_rv',
4898 
        'ports' => {
4899 
          'reg14_rv' => {
4900 
            'attributes' => {
4901 
              'bin_pt' => 0,
4902 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
4903 
              'is_floating_block' => 1,
4904 
              'is_gateway_port' => 1,
4905 
              'must_be_hdl_vector' => 1,
4906 
              'period' => 1,
4907 
              'port_id' => 0,
4908 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
4909 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
4910 
              'timingConstraint' => 'none',
4911 
              'type' => 'UFix_1_0',
4912 
            },
4913 
            'direction' => 'in',
4914 
            'hdlType' => 'std_logic',
4915 
            'width' => 1,
4916 
          },
4917 
        },
4918 
      },
4919 
      'entityName' => 'reg14_rv',
4920 
    },
4921 
    'reg14_td' => {
4922 
      'connections' => { 'reg14_td' => '.reg14_td', },
4923 
      'entity' => {
4924 
        'attributes' => {
4925 
          'entityAlreadyNetlisted' => 1,
4926 
          'isGateway' => 1,
4927 
          'is_floating_block' => 1,
4928 
        },
4929 
        'entityName' => 'reg14_td',
4930 
        'ports' => {
4931 
          'reg14_td' => {
4932 
            'attributes' => {
4933 
              'bin_pt' => 0,
4934 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
4935 
              'is_floating_block' => 1,
4936 
              'is_gateway_port' => 1,
4937 
              'must_be_hdl_vector' => 1,
4938 
              'period' => 1,
4939 
              'port_id' => 0,
4940 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
4941 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
4942 
              'timingConstraint' => 'none',
4943 
              'type' => 'UFix_32_0',
4944 
            },
4945 
            'direction' => 'out',
4946 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4947 
            'width' => 32,
4948 
          },
4949 
        },
4950 
      },
4951 
      'entityName' => 'reg14_td',
4952 
    },
4953 
    'reg14_tv' => {
4954 
      'connections' => { 'reg14_tv' => '.reg14_tv', },
4955 
      'entity' => {
4956 
        'attributes' => {
4957 
          'entityAlreadyNetlisted' => 1,
4958 
          'isGateway' => 1,
4959 
          'is_floating_block' => 1,
4960 
        },
4961 
        'entityName' => 'reg14_tv',
4962 
        'ports' => {
4963 
          'reg14_tv' => {
4964 
            'attributes' => {
4965 
              'bin_pt' => 0,
4966 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
4967 
              'is_floating_block' => 1,
4968 
              'is_gateway_port' => 1,
4969 
              'must_be_hdl_vector' => 1,
4970 
              'period' => 1,
4971 
              'port_id' => 0,
4972 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
4973 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
4974 
              'timingConstraint' => 'none',
4975 
              'type' => 'Bool',
4976 
            },
4977 
            'direction' => 'out',
4978 
            'hdlType' => 'std_logic',
4979 
            'width' => 1,
4980 
          },
4981 
        },
4982 
      },
4983 
      'entityName' => 'reg14_tv',
4984 
    },
4985 
    'sysgen_dut' => {
4986 
      'connections' => {
4987 
        'clk' => '.clk',
4988 
        'debug_in_1i' => '.debug_in_1i',
4989 
        'debug_in_2i' => '.debug_in_2i',
4990 
        'debug_in_3i' => '.debug_in_3i',
4991 
        'debug_in_4i' => '.debug_in_4i',
4992 
        'dma_host2board_busy' => '.dma_host2board_busy',
4993 
        'dma_host2board_done' => '.dma_host2board_done',
4994 
        'from_register10_data_out' => 'from_register10.data_out',
4995 
        'from_register11_data_out' => 'from_register11.data_out',
4996 
        'from_register12_data_out' => 'from_register12.data_out',
4997 
        'from_register13_data_out' => 'from_register13.data_out',
4998 
        'from_register14_data_out' => 'from_register14.data_out',
4999 
        'from_register15_data_out' => 'from_register15.data_out',
5000 
        'from_register16_data_out' => 'from_register16.data_out',
5001 
        'from_register17_data_out' => 'from_register17.data_out',
5002 
        'from_register18_data_out' => 'from_register18.data_out',
5003 
        'from_register19_data_out' => 'from_register19.data_out',
5004 
        'from_register1_data_out' => 'from_register1.data_out',
5005 
        'from_register20_data_out' => 'from_register20.data_out',
5006 
        'from_register21_data_out' => 'from_register21.data_out',
5007 
        'from_register22_data_out' => 'from_register22.data_out',
5008 
        'from_register23_data_out' => 'from_register23.data_out',
5009 
        'from_register24_data_out' => 'from_register24.data_out',
5010 
        'from_register25_data_out' => 'from_register25.data_out',
5011 
        'from_register26_data_out' => 'from_register26.data_out',
5012 
        'from_register27_data_out' => 'from_register27.data_out',
5013 
        'from_register28_data_out' => 'from_register28.data_out',
5014 
        'from_register2_data_out' => 'from_register2.data_out',
5015 
        'from_register3_data_out' => 'from_register3.data_out',
5016 
        'from_register4_data_out' => 'from_register4.data_out',
5017 
        'from_register5_data_out' => 'from_register5.data_out',
5018 
        'from_register6_data_out' => 'from_register6.data_out',
5019 
        'from_register7_data_out' => 'from_register7.data_out',
5020 
        'from_register8_data_out' => 'from_register8.data_out',
5021 
        'from_register9_data_out' => 'from_register9.data_out',
5022 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5023 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5024 
        'reg01_td' => '.reg01_td',
5025 
        'reg01_tv' => '.reg01_tv',
5026 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5027 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5028 
        'reg02_td' => '.reg02_td',
5029 
        'reg02_tv' => '.reg02_tv',
5030 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5031 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5032 
        'reg03_td' => '.reg03_td',
5033 
        'reg03_tv' => '.reg03_tv',
5034 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5035 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5036 
        'reg04_td' => '.reg04_td',
5037 
        'reg04_tv' => '.reg04_tv',
5038 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5039 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5040 
        'reg05_td' => '.reg05_td',
5041 
        'reg05_tv' => '.reg05_tv',
5042 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5043 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5044 
        'reg06_td' => '.reg06_td',
5045 
        'reg06_tv' => '.reg06_tv',
5046 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5047 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5048 
        'reg07_td' => '.reg07_td',
5049 
        'reg07_tv' => '.reg07_tv',
5050 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5051 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5052 
        'reg08_td' => '.reg08_td',
5053 
        'reg08_tv' => '.reg08_tv',
5054 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5055 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5056 
        'reg09_td' => '.reg09_td',
5057 
        'reg09_tv' => '.reg09_tv',
5058 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5059 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5060 
        'reg10_td' => '.reg10_td',
5061 
        'reg10_tv' => '.reg10_tv',
5062 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5063 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5064 
        'reg11_td' => '.reg11_td',
5065 
        'reg11_tv' => '.reg11_tv',
5066 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5067 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5068 
        'reg12_td' => '.reg12_td',
5069 
        'reg12_tv' => '.reg12_tv',
5070 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5071 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5072 
        'reg13_td' => '.reg13_td',
5073 
        'reg13_tv' => '.reg13_tv',
5074 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5075 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5076 
        'reg14_td' => '.reg14_td',
5077 
        'reg14_tv' => '.reg14_tv',
5078 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5079 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5080 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5081 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5082 
        'to_register10_dout' => 'to_register10.dout',
5083 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5084 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5085 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5086 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5087 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5088 
        'to_register11_dout' => 'to_register11.dout',
5089 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5090 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5091 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5092 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5093 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5094 
        'to_register12_dout' => 'to_register12.dout',
5095 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5096 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5097 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5098 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5099 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5100 
        'to_register13_dout' => 'to_register13.dout',
5101 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5102 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5103 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5104 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5105 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5106 
        'to_register14_dout' => 'to_register14.dout',
5107 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5108 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5109 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5110 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5111 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5112 
        'to_register15_dout' => 'to_register15.dout',
5113 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5114 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5115 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5116 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5117 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5118 
        'to_register16_dout' => 'to_register16.dout',
5119 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5120 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5121 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5122 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5123 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5124 
        'to_register17_dout' => 'to_register17.dout',
5125 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5126 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5127 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5128 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5129 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5130 
        'to_register18_dout' => 'to_register18.dout',
5131 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5132 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5133 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5134 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5135 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5136 
        'to_register19_dout' => 'to_register19.dout',
5137 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5138 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5139 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5140 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5141 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5142 
        'to_register1_dout' => 'to_register1.dout',
5143 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5144 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5145 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5146 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5147 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5148 
        'to_register20_dout' => 'to_register20.dout',
5149 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5150 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5151 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5152 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5153 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5154 
        'to_register21_dout' => 'to_register21.dout',
5155 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5156 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5157 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5158 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5159 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5160 
        'to_register22_dout' => 'to_register22.dout',
5161 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5162 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5163 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5164 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5165 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5166 
        'to_register23_dout' => 'to_register23.dout',
5167 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5168 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5169 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5170 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5171 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5172 
        'to_register24_dout' => 'to_register24.dout',
5173 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5174 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5175 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5176 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5177 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5178 
        'to_register25_dout' => 'to_register25.dout',
5179 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5180 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5181 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5182 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5183 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5184 
        'to_register26_dout' => 'to_register26.dout',
5185 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5186 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5187 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5188 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5189 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5190 
        'to_register27_dout' => 'to_register27.dout',
5191 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5192 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5193 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5194 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5195 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5196 
        'to_register28_dout' => 'to_register28.dout',
5197 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5198 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5199 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5200 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5201 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5202 
        'to_register29_dout' => 'to_register29.dout',
5203 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5204 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5205 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5206 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5207 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5208 
        'to_register2_dout' => 'to_register2.dout',
5209 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5210 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5211 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5212 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5213 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5214 
        'to_register30_dout' => 'to_register30.dout',
5215 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5216 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5217 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5218 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5219 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5220 
        'to_register31_dout' => 'to_register31.dout',
5221 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5222 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5223 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5224 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5225 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5226 
        'to_register32_dout' => 'to_register32.dout',
5227 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5228 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5229 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5230 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5231 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5232 
        'to_register33_dout' => 'to_register33.dout',
5233 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5234 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5235 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5236 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5237 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5238 
        'to_register34_dout' => 'to_register34.dout',
5239 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5240 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5241 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5242 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5243 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5244 
        'to_register3_dout' => 'to_register3.dout',
5245 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5246 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5247 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5248 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5249 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5250 
        'to_register4_dout' => 'to_register4.dout',
5251 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5252 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5253 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5254 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5255 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5256 
        'to_register5_dout' => 'to_register5.dout',
5257 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5258 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5259 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5260 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5261 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5262 
        'to_register6_dout' => 'to_register6.dout',
5263 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5264 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5265 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5266 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5267 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5268 
        'to_register7_dout' => 'to_register7.dout',
5269 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5270 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5271 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5272 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5273 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5274 
        'to_register8_dout' => 'to_register8.dout',
5275 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5276 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5277 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5278 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5279 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5280 
        'to_register9_dout' => 'to_register9.dout',
5281 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5282 
      },
5283 
      'entity' => {
5284 
        'attributes' => {
5285 
          'entityAlreadyNetlisted' => 1,
5286 
          'hdlArchAttributes' => [],
5287 
          'hdlEntityAttributes' => [],
5288 
          'isClkWrapper' => 1,
5289 
        },
5290 
        'connections' => {
5291 
          'clk' => 'clkNet',
5292 
          'debug_in_1i' => 'debug_in_1i_net',
5293 
          'debug_in_2i' => 'debug_in_2i_net',
5294 
          'debug_in_3i' => 'debug_in_3i_net',
5295 
          'debug_in_4i' => 'debug_in_4i_net',
5296 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5297 
          'dma_host2board_done' => 'dma_host2board_done_net',
5298 
          'from_register10_data_out' => 'from_register10_data_out_net',
5299 
          'from_register11_data_out' => 'from_register11_data_out_net',
5300 
          'from_register12_data_out' => 'from_register12_data_out_net',
5301 
          'from_register13_data_out' => 'from_register13_data_out_net',
5302 
          'from_register14_data_out' => 'from_register14_data_out_net',
5303 
          'from_register15_data_out' => 'from_register15_data_out_net',
5304 
          'from_register16_data_out' => 'from_register16_data_out_net',
5305 
          'from_register17_data_out' => 'from_register17_data_out_net',
5306 
          'from_register18_data_out' => 'from_register18_data_out_net',
5307 
          'from_register19_data_out' => 'from_register19_data_out_net',
5308 
          'from_register1_data_out' => 'from_register1_data_out_net',
5309 
          'from_register20_data_out' => 'from_register20_data_out_net',
5310 
          'from_register21_data_out' => 'from_register21_data_out_net',
5311 
          'from_register22_data_out' => 'from_register22_data_out_net',
5312 
          'from_register23_data_out' => 'from_register23_data_out_net',
5313 
          'from_register24_data_out' => 'from_register24_data_out_net',
5314 
          'from_register25_data_out' => 'from_register25_data_out_net',
5315 
          'from_register26_data_out' => 'from_register26_data_out_net',
5316 
          'from_register27_data_out' => 'from_register27_data_out_net',
5317 
          'from_register28_data_out' => 'from_register28_data_out_net',
5318 
          'from_register2_data_out' => 'from_register2_data_out_net',
5319 
          'from_register3_data_out' => 'from_register3_data_out_net',
5320 
          'from_register4_data_out' => 'from_register4_data_out_net',
5321 
          'from_register5_data_out' => 'from_register5_data_out_net',
5322 
          'from_register6_data_out' => 'from_register6_data_out_net',
5323 
          'from_register7_data_out' => 'from_register7_data_out_net',
5324 
          'from_register8_data_out' => 'from_register8_data_out_net',
5325 
          'from_register9_data_out' => 'from_register9_data_out_net',
5326 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5327 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5328 
          'reg01_td' => 'reg01_td_net',
5329 
          'reg01_tv' => 'reg01_tv_net',
5330 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5331 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5332 
          'reg02_td' => 'reg02_td_net',
5333 
          'reg02_tv' => 'reg02_tv_net',
5334 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5335 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5336 
          'reg03_td' => 'reg03_td_net',
5337 
          'reg03_tv' => 'reg03_tv_net',
5338 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5339 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5340 
          'reg04_td' => 'reg04_td_net',
5341 
          'reg04_tv' => 'reg04_tv_net',
5342 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5343 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5344 
          'reg05_td' => 'reg05_td_net',
5345 
          'reg05_tv' => 'reg05_tv_net',
5346 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5347 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5348 
          'reg06_td' => 'reg06_td_net',
5349 
          'reg06_tv' => 'reg06_tv_net',
5350 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5351 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5352 
          'reg07_td' => 'reg07_td_net',
5353 
          'reg07_tv' => 'reg07_tv_net',
5354 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5355 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5356 
          'reg08_td' => 'reg08_td_net',
5357 
          'reg08_tv' => 'reg08_tv_net',
5358 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5359 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5360 
          'reg09_td' => 'reg09_td_net',
5361 
          'reg09_tv' => 'reg09_tv_net',
5362 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5363 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5364 
          'reg10_td' => 'reg10_td_net',
5365 
          'reg10_tv' => 'reg10_tv_net',
5366 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5367 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5368 
          'reg11_td' => 'reg11_td_net',
5369 
          'reg11_tv' => 'reg11_tv_net',
5370 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5371 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5372 
          'reg12_td' => 'reg12_td_net',
5373 
          'reg12_tv' => 'reg12_tv_net',
5374 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5375 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5376 
          'reg13_td' => 'reg13_td_net',
5377 
          'reg13_tv' => 'reg13_tv_net',
5378 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5379 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5380 
          'reg14_td' => 'reg14_td_net',
5381 
          'reg14_tv' => 'reg14_tv_net',
5382 
          'to_register10_ce' => 'ce_1_sg',
5383 
          'to_register10_clk' => 'clk_1_sg',
5384 
          'to_register10_clr' => [
5385 
            'constant',
5386 
            '\'0\'',
5387 
          ],
5388 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5389 
          'to_register10_dout' => 'to_register10_dout_net',
5390 
          'to_register10_en' => 'constant5_op_net_x1',
5391 
          'to_register11_ce' => 'ce_1_sg',
5392 
          'to_register11_clk' => 'clk_1_sg',
5393 
          'to_register11_clr' => [
5394 
            'constant',
5395 
            '\'0\'',
5396 
          ],
5397 
          'to_register11_data_in' => 'reg04_td_net_x0',
5398 
          'to_register11_dout' => 'to_register11_dout_net',
5399 
          'to_register11_en' => 'constant5_op_net_x2',
5400 
          'to_register12_ce' => 'ce_1_sg',
5401 
          'to_register12_clk' => 'clk_1_sg',
5402 
          'to_register12_clr' => [
5403 
            'constant',
5404 
            '\'0\'',
5405 
          ],
5406 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5407 
          'to_register12_dout' => 'to_register12_dout_net',
5408 
          'to_register12_en' => 'constant5_op_net_x3',
5409 
          'to_register13_ce' => 'ce_1_sg',
5410 
          'to_register13_clk' => 'clk_1_sg',
5411 
          'to_register13_clr' => [
5412 
            'constant',
5413 
            '\'0\'',
5414 
          ],
5415 
          'to_register13_data_in' => 'reg05_td_net_x0',
5416 
          'to_register13_dout' => 'to_register13_dout_net',
5417 
          'to_register13_en' => 'constant5_op_net_x4',
5418 
          'to_register14_ce' => 'ce_1_sg',
5419 
          'to_register14_clk' => 'clk_1_sg',
5420 
          'to_register14_clr' => [
5421 
            'constant',
5422 
            '\'0\'',
5423 
          ],
5424 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5425 
          'to_register14_dout' => 'to_register14_dout_net',
5426 
          'to_register14_en' => 'constant5_op_net_x5',
5427 
          'to_register15_ce' => 'ce_1_sg',
5428 
          'to_register15_clk' => 'clk_1_sg',
5429 
          'to_register15_clr' => [
5430 
            'constant',
5431 
            '\'0\'',
5432 
          ],
5433 
          'to_register15_data_in' => 'reg06_td_net_x0',
5434 
          'to_register15_dout' => 'to_register15_dout_net',
5435 
          'to_register15_en' => 'constant5_op_net_x6',
5436 
          'to_register16_ce' => 'ce_1_sg',
5437 
          'to_register16_clk' => 'clk_1_sg',
5438 
          'to_register16_clr' => [
5439 
            'constant',
5440 
            '\'0\'',
5441 
          ],
5442 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5443 
          'to_register16_dout' => 'to_register16_dout_net',
5444 
          'to_register16_en' => 'constant5_op_net_x7',
5445 
          'to_register17_ce' => 'ce_1_sg',
5446 
          'to_register17_clk' => 'clk_1_sg',
5447 
          'to_register17_clr' => [
5448 
            'constant',
5449 
            '\'0\'',
5450 
          ],
5451 
          'to_register17_data_in' => 'reg07_td_net_x0',
5452 
          'to_register17_dout' => 'to_register17_dout_net',
5453 
          'to_register17_en' => 'constant5_op_net_x8',
5454 
          'to_register18_ce' => 'ce_1_sg',
5455 
          'to_register18_clk' => 'clk_1_sg',
5456 
          'to_register18_clr' => [
5457 
            'constant',
5458 
            '\'0\'',
5459 
          ],
5460 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5461 
          'to_register18_dout' => 'to_register18_dout_net',
5462 
          'to_register18_en' => 'constant5_op_net_x9',
5463 
          'to_register19_ce' => 'ce_1_sg',
5464 
          'to_register19_clk' => 'clk_1_sg',
5465 
          'to_register19_clr' => [
5466 
            'constant',
5467 
            '\'0\'',
5468 
          ],
5469 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5470 
          'to_register19_dout' => 'to_register19_dout_net',
5471 
          'to_register19_en' => 'constant5_op_net_x10',
5472 
          'to_register1_ce' => 'ce_1_sg',
5473 
          'to_register1_clk' => 'clk_1_sg',
5474 
          'to_register1_clr' => [
5475 
            'constant',
5476 
            '\'0\'',
5477 
          ],
5478 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5479 
          'to_register1_dout' => 'to_register1_dout_net',
5480 
          'to_register1_en' => 'constant5_op_net_x0',
5481 
          'to_register20_ce' => 'ce_1_sg',
5482 
          'to_register20_clk' => 'clk_1_sg',
5483 
          'to_register20_clr' => [
5484 
            'constant',
5485 
            '\'0\'',
5486 
          ],
5487 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5488 
          'to_register20_dout' => 'to_register20_dout_net',
5489 
          'to_register20_en' => 'constant5_op_net_x12',
5490 
          'to_register21_ce' => 'ce_1_sg',
5491 
          'to_register21_clk' => 'clk_1_sg',
5492 
          'to_register21_clr' => [
5493 
            'constant',
5494 
            '\'0\'',
5495 
          ],
5496 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5497 
          'to_register21_dout' => 'to_register21_dout_net',
5498 
          'to_register21_en' => 'constant1_op_net_x0',
5499 
          'to_register22_ce' => 'ce_1_sg',
5500 
          'to_register22_clk' => 'clk_1_sg',
5501 
          'to_register22_clr' => [
5502 
            'constant',
5503 
            '\'0\'',
5504 
          ],
5505 
          'to_register22_data_in' => 'reg09_td_net_x0',
5506 
          'to_register22_dout' => 'to_register22_dout_net',
5507 
          'to_register22_en' => 'constant1_op_net_x1',
5508 
          'to_register23_ce' => 'ce_1_sg',
5509 
          'to_register23_clk' => 'clk_1_sg',
5510 
          'to_register23_clr' => [
5511 
            'constant',
5512 
            '\'0\'',
5513 
          ],
5514 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5515 
          'to_register23_dout' => 'to_register23_dout_net',
5516 
          'to_register23_en' => 'constant1_op_net_x2',
5517 
          'to_register24_ce' => 'ce_1_sg',
5518 
          'to_register24_clk' => 'clk_1_sg',
5519 
          'to_register24_clr' => [
5520 
            'constant',
5521 
            '\'0\'',
5522 
          ],
5523 
          'to_register24_data_in' => 'reg10_td_net_x0',
5524 
          'to_register24_dout' => 'to_register24_dout_net',
5525 
          'to_register24_en' => 'constant1_op_net_x3',
5526 
          'to_register25_ce' => 'ce_1_sg',
5527 
          'to_register25_clk' => 'clk_1_sg',
5528 
          'to_register25_clr' => [
5529 
            'constant',
5530 
            '\'0\'',
5531 
          ],
5532 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5533 
          'to_register25_dout' => 'to_register25_dout_net',
5534 
          'to_register25_en' => 'constant1_op_net_x4',
5535 
          'to_register26_ce' => 'ce_1_sg',
5536 
          'to_register26_clk' => 'clk_1_sg',
5537 
          'to_register26_clr' => [
5538 
            'constant',
5539 
            '\'0\'',
5540 
          ],
5541 
          'to_register26_data_in' => 'reg08_td_net_x0',
5542 
          'to_register26_dout' => 'to_register26_dout_net',
5543 
          'to_register26_en' => 'constant1_op_net_x5',
5544 
          'to_register27_ce' => 'ce_1_sg',
5545 
          'to_register27_clk' => 'clk_1_sg',
5546 
          'to_register27_clr' => [
5547 
            'constant',
5548 
            '\'0\'',
5549 
          ],
5550 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5551 
          'to_register27_dout' => 'to_register27_dout_net',
5552 
          'to_register27_en' => 'constant1_op_net_x6',
5553 
          'to_register28_ce' => 'ce_1_sg',
5554 
          'to_register28_clk' => 'clk_1_sg',
5555 
          'to_register28_clr' => [
5556 
            'constant',
5557 
            '\'0\'',
5558 
          ],
5559 
          'to_register28_data_in' => 'reg11_td_net_x0',
5560 
          'to_register28_dout' => 'to_register28_dout_net',
5561 
          'to_register28_en' => 'constant1_op_net_x7',
5562 
          'to_register29_ce' => 'ce_1_sg',
5563 
          'to_register29_clk' => 'clk_1_sg',
5564 
          'to_register29_clr' => [
5565 
            'constant',
5566 
            '\'0\'',
5567 
          ],
5568 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5569 
          'to_register29_dout' => 'to_register29_dout_net',
5570 
          'to_register29_en' => 'constant1_op_net_x8',
5571 
          'to_register2_ce' => 'ce_1_sg',
5572 
          'to_register2_clk' => 'clk_1_sg',
5573 
          'to_register2_clr' => [
5574 
            'constant',
5575 
            '\'0\'',
5576 
          ],
5577 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5578 
          'to_register2_dout' => 'to_register2_dout_net',
5579 
          'to_register2_en' => 'constant5_op_net_x11',
5580 
          'to_register30_ce' => 'ce_1_sg',
5581 
          'to_register30_clk' => 'clk_1_sg',
5582 
          'to_register30_clr' => [
5583 
            'constant',
5584 
            '\'0\'',
5585 
          ],
5586 
          'to_register30_data_in' => 'reg12_td_net_x0',
5587 
          'to_register30_dout' => 'to_register30_dout_net',
5588 
          'to_register30_en' => 'constant1_op_net_x9',
5589 
          'to_register31_ce' => 'ce_1_sg',
5590 
          'to_register31_clk' => 'clk_1_sg',
5591 
          'to_register31_clr' => [
5592 
            'constant',
5593 
            '\'0\'',
5594 
          ],
5595 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5596 
          'to_register31_dout' => 'to_register31_dout_net',
5597 
          'to_register31_en' => 'constant1_op_net_x10',
5598 
          'to_register32_ce' => 'ce_1_sg',
5599 
          'to_register32_clk' => 'clk_1_sg',
5600 
          'to_register32_clr' => [
5601 
            'constant',
5602 
            '\'0\'',
5603 
          ],
5604 
          'to_register32_data_in' => 'reg13_td_net_x0',
5605 
          'to_register32_dout' => 'to_register32_dout_net',
5606 
          'to_register32_en' => 'constant1_op_net_x11',
5607 
          'to_register33_ce' => 'ce_1_sg',
5608 
          'to_register33_clk' => 'clk_1_sg',
5609 
          'to_register33_clr' => [
5610 
            'constant',
5611 
            '\'0\'',
5612 
          ],
5613 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5614 
          'to_register33_dout' => 'to_register33_dout_net',
5615 
          'to_register33_en' => 'constant1_op_net_x12',
5616 
          'to_register34_ce' => 'ce_1_sg',
5617 
          'to_register34_clk' => 'clk_1_sg',
5618 
          'to_register34_clr' => [
5619 
            'constant',
5620 
            '\'0\'',
5621 
          ],
5622 
          'to_register34_data_in' => 'reg14_td_net_x0',
5623 
          'to_register34_dout' => 'to_register34_dout_net',
5624 
          'to_register34_en' => 'constant1_op_net_x13',
5625 
          'to_register3_ce' => 'ce_1_sg',
5626 
          'to_register3_clk' => 'clk_1_sg',
5627 
          'to_register3_clr' => [
5628 
            'constant',
5629 
            '\'0\'',
5630 
          ],
5631 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5632 
          'to_register3_dout' => 'to_register3_dout_net',
5633 
          'to_register3_en' => 'constant5_op_net_x13',
5634 
          'to_register4_ce' => 'ce_1_sg',
5635 
          'to_register4_clk' => 'clk_1_sg',
5636 
          'to_register4_clr' => [
5637 
            'constant',
5638 
            '\'0\'',
5639 
          ],
5640 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5641 
          'to_register4_dout' => 'to_register4_dout_net',
5642 
          'to_register4_en' => 'constant5_op_net_x14',
5643 
          'to_register5_ce' => 'ce_1_sg',
5644 
          'to_register5_clk' => 'clk_1_sg',
5645 
          'to_register5_clr' => [
5646 
            'constant',
5647 
            '\'0\'',
5648 
          ],
5649 
          'to_register5_data_in' => 'reg02_td_net_x0',
5650 
          'to_register5_dout' => 'to_register5_dout_net',
5651 
          'to_register5_en' => 'constant5_op_net_x15',
5652 
          'to_register6_ce' => 'ce_1_sg',
5653 
          'to_register6_clk' => 'clk_1_sg',
5654 
          'to_register6_clr' => [
5655 
            'constant',
5656 
            '\'0\'',
5657 
          ],
5658 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5659 
          'to_register6_dout' => 'to_register6_dout_net',
5660 
          'to_register6_en' => 'constant5_op_net_x16',
5661 
          'to_register7_ce' => 'ce_1_sg',
5662 
          'to_register7_clk' => 'clk_1_sg',
5663 
          'to_register7_clr' => [
5664 
            'constant',
5665 
            '\'0\'',
5666 
          ],
5667 
          'to_register7_data_in' => 'reg01_td_net_x0',
5668 
          'to_register7_dout' => 'to_register7_dout_net',
5669 
          'to_register7_en' => 'constant5_op_net_x17',
5670 
          'to_register8_ce' => 'ce_1_sg',
5671 
          'to_register8_clk' => 'clk_1_sg',
5672 
          'to_register8_clr' => [
5673 
            'constant',
5674 
            '\'0\'',
5675 
          ],
5676 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5677 
          'to_register8_dout' => 'to_register8_dout_net',
5678 
          'to_register8_en' => 'constant5_op_net_x18',
5679 
          'to_register9_ce' => 'ce_1_sg',
5680 
          'to_register9_clk' => 'clk_1_sg',
5681 
          'to_register9_clr' => [
5682 
            'constant',
5683 
            '\'0\'',
5684 
          ],
5685 
          'to_register9_data_in' => 'reg03_td_net_x0',
5686 
          'to_register9_dout' => 'to_register9_dout_net',
5687 
          'to_register9_en' => 'constant5_op_net_x19',
5688 
        },
5689 
        'entityName' => 'inout_logic_cw',
5690 
        'nets' => {
5691 
          'ce_1_sg' => {
5692 
            'attributes' => {
5693 
              'hdlNetAttributes' => [
5694 
                [
5695 
                  'MAX_FANOUT',
5696 
                  'string',
5697 
                  '"REDUCE"',
5698 
                ],
5699 
              ],
5700 
            },
5701 
            'hdlType' => 'std_logic',
5702 
            'width' => 1,
5703 
          },
5704 
          'clkNet' => {
5705 
            'attributes' => {
5706 
              'hdlNetAttributes' => [],
5707 
            },
5708 
            'hdlType' => 'std_logic',
5709 
            'width' => 1,
5710 
          },
5711 
          'clk_1_sg' => {
5712 
            'attributes' => {
5713 
              'hdlNetAttributes' => [],
5714 
            },
5715 
            'hdlType' => 'std_logic',
5716 
            'width' => 1,
5717 
          },
5718 
          'constant1_op_net_x0' => {
5719 
            'attributes' => {
5720 
              'hdlNetAttributes' => [],
5721 
            },
5722 
            'hdlType' => 'std_logic',
5723 
            'width' => 1,
5724 
          },
5725 
          'constant1_op_net_x1' => {
5726 
            'attributes' => {
5727 
              'hdlNetAttributes' => [],
5728 
            },
5729 
            'hdlType' => 'std_logic',
5730 
            'width' => 1,
5731 
          },
5732 
          'constant1_op_net_x10' => {
5733 
            'attributes' => {
5734 
              'hdlNetAttributes' => [],
5735 
            },
5736 
            'hdlType' => 'std_logic',
5737 
            'width' => 1,
5738 
          },
5739 
          'constant1_op_net_x11' => {
5740 
            'attributes' => {
5741 
              'hdlNetAttributes' => [],
5742 
            },
5743 
            'hdlType' => 'std_logic',
5744 
            'width' => 1,
5745 
          },
5746 
          'constant1_op_net_x12' => {
5747 
            'attributes' => {
5748 
              'hdlNetAttributes' => [],
5749 
            },
5750 
            'hdlType' => 'std_logic',
5751 
            'width' => 1,
5752 
          },
5753 
          'constant1_op_net_x13' => {
5754 
            'attributes' => {
5755 
              'hdlNetAttributes' => [],
5756 
            },
5757 
            'hdlType' => 'std_logic',
5758 
            'width' => 1,
5759 
          },
5760 
          'constant1_op_net_x2' => {
5761 
            'attributes' => {
5762 
              'hdlNetAttributes' => [],
5763 
            },
5764 
            'hdlType' => 'std_logic',
5765 
            'width' => 1,
5766 
          },
5767 
          'constant1_op_net_x3' => {
5768 
            'attributes' => {
5769 
              'hdlNetAttributes' => [],
5770 
            },
5771 
            'hdlType' => 'std_logic',
5772 
            'width' => 1,
5773 
          },
5774 
          'constant1_op_net_x4' => {
5775 
            'attributes' => {
5776 
              'hdlNetAttributes' => [],
5777 
            },
5778 
            'hdlType' => 'std_logic',
5779 
            'width' => 1,
5780 
          },
5781 
          'constant1_op_net_x5' => {
5782 
            'attributes' => {
5783 
              'hdlNetAttributes' => [],
5784 
            },
5785 
            'hdlType' => 'std_logic',
5786 
            'width' => 1,
5787 
          },
5788 
          'constant1_op_net_x6' => {
5789 
            'attributes' => {
5790 
              'hdlNetAttributes' => [],
5791 
            },
5792 
            'hdlType' => 'std_logic',
5793 
            'width' => 1,
5794 
          },
5795 
          'constant1_op_net_x7' => {
5796 
            'attributes' => {
5797 
              'hdlNetAttributes' => [],
5798 
            },
5799 
            'hdlType' => 'std_logic',
5800 
            'width' => 1,
5801 
          },
5802 
          'constant1_op_net_x8' => {
5803 
            'attributes' => {
5804 
              'hdlNetAttributes' => [],
5805 
            },
5806 
            'hdlType' => 'std_logic',
5807 
            'width' => 1,
5808 
          },
5809 
          'constant1_op_net_x9' => {
5810 
            'attributes' => {
5811 
              'hdlNetAttributes' => [],
5812 
            },
5813 
            'hdlType' => 'std_logic',
5814 
            'width' => 1,
5815 
          },
5816 
          'constant5_op_net_x0' => {
5817 
            'attributes' => {
5818 
              'hdlNetAttributes' => [],
5819 
            },
5820 
            'hdlType' => 'std_logic',
5821 
            'width' => 1,
5822 
          },
5823 
          'constant5_op_net_x1' => {
5824 
            'attributes' => {
5825 
              'hdlNetAttributes' => [],
5826 
            },
5827 
            'hdlType' => 'std_logic',
5828 
            'width' => 1,
5829 
          },
5830 
          'constant5_op_net_x10' => {
5831 
            'attributes' => {
5832 
              'hdlNetAttributes' => [],
5833 
            },
5834 
            'hdlType' => 'std_logic',
5835 
            'width' => 1,
5836 
          },
5837 
          'constant5_op_net_x11' => {
5838 
            'attributes' => {
5839 
              'hdlNetAttributes' => [],
5840 
            },
5841 
            'hdlType' => 'std_logic',
5842 
            'width' => 1,
5843 
          },
5844 
          'constant5_op_net_x12' => {
5845 
            'attributes' => {
5846 
              'hdlNetAttributes' => [],
5847 
            },
5848 
            'hdlType' => 'std_logic',
5849 
            'width' => 1,
5850 
          },
5851 
          'constant5_op_net_x13' => {
5852 
            'attributes' => {
5853 
              'hdlNetAttributes' => [],
5854 
            },
5855 
            'hdlType' => 'std_logic',
5856 
            'width' => 1,
5857 
          },
5858 
          'constant5_op_net_x14' => {
5859 
            'attributes' => {
5860 
              'hdlNetAttributes' => [],
5861 
            },
5862 
            'hdlType' => 'std_logic',
5863 
            'width' => 1,
5864 
          },
5865 
          'constant5_op_net_x15' => {
5866 
            'attributes' => {
5867 
              'hdlNetAttributes' => [],
5868 
            },
5869 
            'hdlType' => 'std_logic',
5870 
            'width' => 1,
5871 
          },
5872 
          'constant5_op_net_x16' => {
5873 
            'attributes' => {
5874 
              'hdlNetAttributes' => [],
5875 
            },
5876 
            'hdlType' => 'std_logic',
5877 
            'width' => 1,
5878 
          },
5879 
          'constant5_op_net_x17' => {
5880 
            'attributes' => {
5881 
              'hdlNetAttributes' => [],
5882 
            },
5883 
            'hdlType' => 'std_logic',
5884 
            'width' => 1,
5885 
          },
5886 
          'constant5_op_net_x18' => {
5887 
            'attributes' => {
5888 
              'hdlNetAttributes' => [],
5889 
            },
5890 
            'hdlType' => 'std_logic',
5891 
            'width' => 1,
5892 
          },
5893 
          'constant5_op_net_x19' => {
5894 
            'attributes' => {
5895 
              'hdlNetAttributes' => [],
5896 
            },
5897 
            'hdlType' => 'std_logic',
5898 
            'width' => 1,
5899 
          },
5900 
          'constant5_op_net_x2' => {
5901 
            'attributes' => {
5902 
              'hdlNetAttributes' => [],
5903 
            },
5904 
            'hdlType' => 'std_logic',
5905 
            'width' => 1,
5906 
          },
5907 
          'constant5_op_net_x3' => {
5908 
            'attributes' => {
5909 
              'hdlNetAttributes' => [],
5910 
            },
5911 
            'hdlType' => 'std_logic',
5912 
            'width' => 1,
5913 
          },
5914 
          'constant5_op_net_x4' => {
5915 
            'attributes' => {
5916 
              'hdlNetAttributes' => [],
5917 
            },
5918 
            'hdlType' => 'std_logic',
5919 
            'width' => 1,
5920 
          },
5921 
          'constant5_op_net_x5' => {
5922 
            'attributes' => {
5923 
              'hdlNetAttributes' => [],
5924 
            },
5925 
            'hdlType' => 'std_logic',
5926 
            'width' => 1,
5927 
          },
5928 
          'constant5_op_net_x6' => {
5929 
            'attributes' => {
5930 
              'hdlNetAttributes' => [],
5931 
            },
5932 
            'hdlType' => 'std_logic',
5933 
            'width' => 1,
5934 
          },
5935 
          'constant5_op_net_x7' => {
5936 
            'attributes' => {
5937 
              'hdlNetAttributes' => [],
5938 
            },
5939 
            'hdlType' => 'std_logic',
5940 
            'width' => 1,
5941 
          },
5942 
          'constant5_op_net_x8' => {
5943 
            'attributes' => {
5944 
              'hdlNetAttributes' => [],
5945 
            },
5946 
            'hdlType' => 'std_logic',
5947 
            'width' => 1,
5948 
          },
5949 
          'constant5_op_net_x9' => {
5950 
            'attributes' => {
5951 
              'hdlNetAttributes' => [],
5952 
            },
5953 
            'hdlType' => 'std_logic',
5954 
            'width' => 1,
5955 
          },
5956 
          'debug_in_1i_net' => {
5957 
            'attributes' => {
5958 
              'hdlNetAttributes' => [],
5959 
            },
5960 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5961 
            'width' => 32,
5962 
          },
5963 
          'debug_in_1i_net_x0' => {
5964 
            'attributes' => {
5965 
              'hdlNetAttributes' => [],
5966 
            },
5967 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5968 
            'width' => 32,
5969 
          },
5970 
          'debug_in_2i_net' => {
5971 
            'attributes' => {
5972 
              'hdlNetAttributes' => [],
5973 
            },
5974 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5975 
            'width' => 32,
5976 
          },
5977 
          'debug_in_2i_net_x0' => {
5978 
            'attributes' => {
5979 
              'hdlNetAttributes' => [],
5980 
            },
5981 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5982 
            'width' => 32,
5983 
          },
5984 
          'debug_in_3i_net' => {
5985 
            'attributes' => {
5986 
              'hdlNetAttributes' => [],
5987 
            },
5988 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5989 
            'width' => 32,
5990 
          },
5991 
          'debug_in_3i_net_x0' => {
5992 
            'attributes' => {
5993 
              'hdlNetAttributes' => [],
5994 
            },
5995 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5996 
            'width' => 32,
5997 
          },
5998 
          'debug_in_4i_net' => {
5999 
            'attributes' => {
6000 
              'hdlNetAttributes' => [],
6001 
            },
6002 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6003 
            'width' => 32,
6004 
          },
6005 
          'debug_in_4i_net_x0' => {
6006 
            'attributes' => {
6007 
              'hdlNetAttributes' => [],
6008 
            },
6009 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6010 
            'width' => 32,
6011 
          },
6012 
          'dma_host2board_busy_net' => {
6013 
            'attributes' => {
6014 
              'hdlNetAttributes' => [],
6015 
            },
6016 
            'hdlType' => 'std_logic',
6017 
            'width' => 1,
6018 
          },
6019 
          'dma_host2board_busy_net_x0' => {
6020 
            'attributes' => {
6021 
              'hdlNetAttributes' => [],
6022 
            },
6023 
            'hdlType' => 'std_logic',
6024 
            'width' => 1,
6025 
          },
6026 
          'dma_host2board_done_net' => {
6027 
            'attributes' => {
6028 
              'hdlNetAttributes' => [],
6029 
            },
6030 
            'hdlType' => 'std_logic',
6031 
            'width' => 1,
6032 
          },
6033 
          'dma_host2board_done_net_x0' => {
6034 
            'attributes' => {
6035 
              'hdlNetAttributes' => [],
6036 
            },
6037 
            'hdlType' => 'std_logic',
6038 
            'width' => 1,
6039 
          },
6040 
          'from_register10_data_out_net' => {
6041 
            'attributes' => {
6042 
              'hdlNetAttributes' => [],
6043 
            },
6044 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6045 
            'width' => 32,
6046 
          },
6047 
          'from_register10_data_out_net_x0' => {
6048 
            'attributes' => {
6049 
              'hdlNetAttributes' => [],
6050 
            },
6051 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6052 
            'width' => 32,
6053 
          },
6054 
          'from_register11_data_out_net' => {
6055 
            'attributes' => {
6056 
              'hdlNetAttributes' => [],
6057 
            },
6058 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6059 
            'width' => 32,
6060 
          },
6061 
          'from_register11_data_out_net_x0' => {
6062 
            'attributes' => {
6063 
              'hdlNetAttributes' => [],
6064 
            },
6065 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6066 
            'width' => 32,
6067 
          },
6068 
          'from_register12_data_out_net' => {
6069 
            'attributes' => {
6070 
              'hdlNetAttributes' => [],
6071 
            },
6072 
            'hdlType' => 'std_logic',
6073 
            'width' => 1,
6074 
          },
6075 
          'from_register12_data_out_net_x0' => {
6076 
            'attributes' => {
6077 
              'hdlNetAttributes' => [],
6078 
            },
6079 
            'hdlType' => 'std_logic',
6080 
            'width' => 1,
6081 
          },
6082 
          'from_register13_data_out_net' => {
6083 
            'attributes' => {
6084 
              'hdlNetAttributes' => [],
6085 
            },
6086 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6087 
            'width' => 32,
6088 
          },
6089 
          'from_register13_data_out_net_x0' => {
6090 
            'attributes' => {
6091 
              'hdlNetAttributes' => [],
6092 
            },
6093 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6094 
            'width' => 32,
6095 
          },
6096 
          'from_register14_data_out_net' => {
6097 
            'attributes' => {
6098 
              'hdlNetAttributes' => [],
6099 
            },
6100 
            'hdlType' => 'std_logic',
6101 
            'width' => 1,
6102 
          },
6103 
          'from_register14_data_out_net_x0' => {
6104 
            'attributes' => {
6105 
              'hdlNetAttributes' => [],
6106 
            },
6107 
            'hdlType' => 'std_logic',
6108 
            'width' => 1,
6109 
          },
6110 
          'from_register15_data_out_net' => {
6111 
            'attributes' => {
6112 
              'hdlNetAttributes' => [],
6113 
            },
6114 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6115 
            'width' => 32,
6116 
          },
6117 
          'from_register15_data_out_net_x0' => {
6118 
            'attributes' => {
6119 
              'hdlNetAttributes' => [],
6120 
            },
6121 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6122 
            'width' => 32,
6123 
          },
6124 
          'from_register16_data_out_net' => {
6125 
            'attributes' => {
6126 
              'hdlNetAttributes' => [],
6127 
            },
6128 
            'hdlType' => 'std_logic',
6129 
            'width' => 1,
6130 
          },
6131 
          'from_register16_data_out_net_x0' => {
6132 
            'attributes' => {
6133 
              'hdlNetAttributes' => [],
6134 
            },
6135 
            'hdlType' => 'std_logic',
6136 
            'width' => 1,
6137 
          },
6138 
          'from_register17_data_out_net' => {
6139 
            'attributes' => {
6140 
              'hdlNetAttributes' => [],
6141 
            },
6142 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6143 
            'width' => 32,
6144 
          },
6145 
          'from_register17_data_out_net_x0' => {
6146 
            'attributes' => {
6147 
              'hdlNetAttributes' => [],
6148 
            },
6149 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6150 
            'width' => 32,
6151 
          },
6152 
          'from_register18_data_out_net' => {
6153 
            'attributes' => {
6154 
              'hdlNetAttributes' => [],
6155 
            },
6156 
            'hdlType' => 'std_logic',
6157 
            'width' => 1,
6158 
          },
6159 
          'from_register18_data_out_net_x0' => {
6160 
            'attributes' => {
6161 
              'hdlNetAttributes' => [],
6162 
            },
6163 
            'hdlType' => 'std_logic',
6164 
            'width' => 1,
6165 
          },
6166 
          'from_register19_data_out_net' => {
6167 
            'attributes' => {
6168 
              'hdlNetAttributes' => [],
6169 
            },
6170 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6171 
            'width' => 32,
6172 
          },
6173 
          'from_register19_data_out_net_x0' => {
6174 
            'attributes' => {
6175 
              'hdlNetAttributes' => [],
6176 
            },
6177 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6178 
            'width' => 32,
6179 
          },
6180 
          'from_register1_data_out_net' => {
6181 
            'attributes' => {
6182 
              'hdlNetAttributes' => [],
6183 
            },
6184 
            'hdlType' => 'std_logic',
6185 
            'width' => 1,
6186 
          },
6187 
          'from_register1_data_out_net_x0' => {
6188 
            'attributes' => {
6189 
              'hdlNetAttributes' => [],
6190 
            },
6191 
            'hdlType' => 'std_logic',
6192 
            'width' => 1,
6193 
          },
6194 
          'from_register20_data_out_net' => {
6195 
            'attributes' => {
6196 
              'hdlNetAttributes' => [],
6197 
            },
6198 
            'hdlType' => 'std_logic',
6199 
            'width' => 1,
6200 
          },
6201 
          'from_register20_data_out_net_x0' => {
6202 
            'attributes' => {
6203 
              'hdlNetAttributes' => [],
6204 
            },
6205 
            'hdlType' => 'std_logic',
6206 
            'width' => 1,
6207 
          },
6208 
          'from_register21_data_out_net' => {
6209 
            'attributes' => {
6210 
              'hdlNetAttributes' => [],
6211 
            },
6212 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6213 
            'width' => 32,
6214 
          },
6215 
          'from_register21_data_out_net_x0' => {
6216 
            'attributes' => {
6217 
              'hdlNetAttributes' => [],
6218 
            },
6219 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6220 
            'width' => 32,
6221 
          },
6222 
          'from_register22_data_out_net' => {
6223 
            'attributes' => {
6224 
              'hdlNetAttributes' => [],
6225 
            },
6226 
            'hdlType' => 'std_logic',
6227 
            'width' => 1,
6228 
          },
6229 
          'from_register22_data_out_net_x0' => {
6230 
            'attributes' => {
6231 
              'hdlNetAttributes' => [],
6232 
            },
6233 
            'hdlType' => 'std_logic',
6234 
            'width' => 1,
6235 
          },
6236 
          'from_register23_data_out_net' => {
6237 
            'attributes' => {
6238 
              'hdlNetAttributes' => [],
6239 
            },
6240 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6241 
            'width' => 32,
6242 
          },
6243 
          'from_register23_data_out_net_x0' => {
6244 
            'attributes' => {
6245 
              'hdlNetAttributes' => [],
6246 
            },
6247 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6248 
            'width' => 32,
6249 
          },
6250 
          'from_register24_data_out_net' => {
6251 
            'attributes' => {
6252 
              'hdlNetAttributes' => [],
6253 
            },
6254 
            'hdlType' => 'std_logic',
6255 
            'width' => 1,
6256 
          },
6257 
          'from_register24_data_out_net_x0' => {
6258 
            'attributes' => {
6259 
              'hdlNetAttributes' => [],
6260 
            },
6261 
            'hdlType' => 'std_logic',
6262 
            'width' => 1,
6263 
          },
6264 
          'from_register25_data_out_net' => {
6265 
            'attributes' => {
6266 
              'hdlNetAttributes' => [],
6267 
            },
6268 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6269 
            'width' => 32,
6270 
          },
6271 
          'from_register25_data_out_net_x0' => {
6272 
            'attributes' => {
6273 
              'hdlNetAttributes' => [],
6274 
            },
6275 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6276 
            'width' => 32,
6277 
          },
6278 
          'from_register26_data_out_net' => {
6279 
            'attributes' => {
6280 
              'hdlNetAttributes' => [],
6281 
            },
6282 
            'hdlType' => 'std_logic',
6283 
            'width' => 1,
6284 
          },
6285 
          'from_register26_data_out_net_x0' => {
6286 
            'attributes' => {
6287 
              'hdlNetAttributes' => [],
6288 
            },
6289 
            'hdlType' => 'std_logic',
6290 
            'width' => 1,
6291 
          },
6292 
          'from_register27_data_out_net' => {
6293 
            'attributes' => {
6294 
              'hdlNetAttributes' => [],
6295 
            },
6296 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6297 
            'width' => 32,
6298 
          },
6299 
          'from_register27_data_out_net_x0' => {
6300 
            'attributes' => {
6301 
              'hdlNetAttributes' => [],
6302 
            },
6303 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6304 
            'width' => 32,
6305 
          },
6306 
          'from_register28_data_out_net' => {
6307 
            'attributes' => {
6308 
              'hdlNetAttributes' => [],
6309 
            },
6310 
            'hdlType' => 'std_logic',
6311 
            'width' => 1,
6312 
          },
6313 
          'from_register28_data_out_net_x0' => {
6314 
            'attributes' => {
6315 
              'hdlNetAttributes' => [],
6316 
            },
6317 
            'hdlType' => 'std_logic',
6318 
            'width' => 1,
6319 
          },
6320 
          'from_register2_data_out_net' => {
6321 
            'attributes' => {
6322 
              'hdlNetAttributes' => [],
6323 
            },
6324 
            'hdlType' => 'std_logic',
6325 
            'width' => 1,
6326 
          },
6327 
          'from_register2_data_out_net_x0' => {
6328 
            'attributes' => {
6329 
              'hdlNetAttributes' => [],
6330 
            },
6331 
            'hdlType' => 'std_logic',
6332 
            'width' => 1,
6333 
          },
6334 
          'from_register3_data_out_net' => {
6335 
            'attributes' => {
6336 
              'hdlNetAttributes' => [],
6337 
            },
6338 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6339 
            'width' => 32,
6340 
          },
6341 
          'from_register3_data_out_net_x0' => {
6342 
            'attributes' => {
6343 
              'hdlNetAttributes' => [],
6344 
            },
6345 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6346 
            'width' => 32,
6347 
          },
6348 
          'from_register4_data_out_net' => {
6349 
            'attributes' => {
6350 
              'hdlNetAttributes' => [],
6351 
            },
6352 
            'hdlType' => 'std_logic',
6353 
            'width' => 1,
6354 
          },
6355 
          'from_register4_data_out_net_x0' => {
6356 
            'attributes' => {
6357 
              'hdlNetAttributes' => [],
6358 
            },
6359 
            'hdlType' => 'std_logic',
6360 
            'width' => 1,
6361 
          },
6362 
          'from_register5_data_out_net' => {
6363 
            'attributes' => {
6364 
              'hdlNetAttributes' => [],
6365 
            },
6366 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6367 
            'width' => 32,
6368 
          },
6369 
          'from_register5_data_out_net_x0' => {
6370 
            'attributes' => {
6371 
              'hdlNetAttributes' => [],
6372 
            },
6373 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6374 
            'width' => 32,
6375 
          },
6376 
          'from_register6_data_out_net' => {
6377 
            'attributes' => {
6378 
              'hdlNetAttributes' => [],
6379 
            },
6380 
            'hdlType' => 'std_logic',
6381 
            'width' => 1,
6382 
          },
6383 
          'from_register6_data_out_net_x0' => {
6384 
            'attributes' => {
6385 
              'hdlNetAttributes' => [],
6386 
            },
6387 
            'hdlType' => 'std_logic',
6388 
            'width' => 1,
6389 
          },
6390 
          'from_register7_data_out_net' => {
6391 
            'attributes' => {
6392 
              'hdlNetAttributes' => [],
6393 
            },
6394 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6395 
            'width' => 32,
6396 
          },
6397 
          'from_register7_data_out_net_x0' => {
6398 
            'attributes' => {
6399 
              'hdlNetAttributes' => [],
6400 
            },
6401 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6402 
            'width' => 32,
6403 
          },
6404 
          'from_register8_data_out_net' => {
6405 
            'attributes' => {
6406 
              'hdlNetAttributes' => [],
6407 
            },
6408 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6409 
            'width' => 32,
6410 
          },
6411 
          'from_register8_data_out_net_x0' => {
6412 
            'attributes' => {
6413 
              'hdlNetAttributes' => [],
6414 
            },
6415 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6416 
            'width' => 32,
6417 
          },
6418 
          'from_register9_data_out_net' => {
6419 
            'attributes' => {
6420 
              'hdlNetAttributes' => [],
6421 
            },
6422 
            'hdlType' => 'std_logic',
6423 
            'width' => 1,
6424 
          },
6425 
          'from_register9_data_out_net_x0' => {
6426 
            'attributes' => {
6427 
              'hdlNetAttributes' => [],
6428 
            },
6429 
            'hdlType' => 'std_logic',
6430 
            'width' => 1,
6431 
          },
6432 
          'persistentdff_inst_q' => {
6433 
            'attributes' => {
6434 
              'hdlNetAttributes' => [
6435 
                [
6436 
                  'syn_keep',
6437 
                  'boolean',
6438 
                  'true',
6439 
                ],
6440 
                [
6441 
                  'keep',
6442 
                  'boolean',
6443 
                  'true',
6444 
                ],
6445 
                [
6446 
                  'preserve_signal',
6447 
                  'boolean',
6448 
                  'true',
6449 
                ],
6450 
              ],
6451 
            },
6452 
            'hdlType' => 'std_logic',
6453 
            'width' => 1,
6454 
          },
6455 
          'reg01_td_net' => {
6456 
            'attributes' => {
6457 
              'hdlNetAttributes' => [],
6458 
            },
6459 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6460 
            'width' => 32,
6461 
          },
6462 
          'reg01_td_net_x0' => {
6463 
            'attributes' => {
6464 
              'hdlNetAttributes' => [],
6465 
            },
6466 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6467 
            'width' => 32,
6468 
          },
6469 
          'reg01_tv_net' => {
6470 
            'attributes' => {
6471 
              'hdlNetAttributes' => [],
6472 
            },
6473 
            'hdlType' => 'std_logic',
6474 
            'width' => 1,
6475 
          },
6476 
          'reg01_tv_net_x0' => {
6477 
            'attributes' => {
6478 
              'hdlNetAttributes' => [],
6479 
            },
6480 
            'hdlType' => 'std_logic',
6481 
            'width' => 1,
6482 
          },
6483 
          'reg02_td_net' => {
6484 
            'attributes' => {
6485 
              'hdlNetAttributes' => [],
6486 
            },
6487 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6488 
            'width' => 32,
6489 
          },
6490 
          'reg02_td_net_x0' => {
6491 
            'attributes' => {
6492 
              'hdlNetAttributes' => [],
6493 
            },
6494 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6495 
            'width' => 32,
6496 
          },
6497 
          'reg02_tv_net' => {
6498 
            'attributes' => {
6499 
              'hdlNetAttributes' => [],
6500 
            },
6501 
            'hdlType' => 'std_logic',
6502 
            'width' => 1,
6503 
          },
6504 
          'reg02_tv_net_x0' => {
6505 
            'attributes' => {
6506 
              'hdlNetAttributes' => [],
6507 
            },
6508 
            'hdlType' => 'std_logic',
6509 
            'width' => 1,
6510 
          },
6511 
          'reg03_td_net' => {
6512 
            'attributes' => {
6513 
              'hdlNetAttributes' => [],
6514 
            },
6515 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6516 
            'width' => 32,
6517 
          },
6518 
          'reg03_td_net_x0' => {
6519 
            'attributes' => {
6520 
              'hdlNetAttributes' => [],
6521 
            },
6522 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6523 
            'width' => 32,
6524 
          },
6525 
          'reg03_tv_net' => {
6526 
            'attributes' => {
6527 
              'hdlNetAttributes' => [],
6528 
            },
6529 
            'hdlType' => 'std_logic',
6530 
            'width' => 1,
6531 
          },
6532 
          'reg03_tv_net_x0' => {
6533 
            'attributes' => {
6534 
              'hdlNetAttributes' => [],
6535 
            },
6536 
            'hdlType' => 'std_logic',
6537 
            'width' => 1,
6538 
          },
6539 
          'reg04_td_net' => {
6540 
            'attributes' => {
6541 
              'hdlNetAttributes' => [],
6542 
            },
6543 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6544 
            'width' => 32,
6545 
          },
6546 
          'reg04_td_net_x0' => {
6547 
            'attributes' => {
6548 
              'hdlNetAttributes' => [],
6549 
            },
6550 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6551 
            'width' => 32,
6552 
          },
6553 
          'reg04_tv_net' => {
6554 
            'attributes' => {
6555 
              'hdlNetAttributes' => [],
6556 
            },
6557 
            'hdlType' => 'std_logic',
6558 
            'width' => 1,
6559 
          },
6560 
          'reg04_tv_net_x0' => {
6561 
            'attributes' => {
6562 
              'hdlNetAttributes' => [],
6563 
            },
6564 
            'hdlType' => 'std_logic',
6565 
            'width' => 1,
6566 
          },
6567 
          'reg05_td_net' => {
6568 
            'attributes' => {
6569 
              'hdlNetAttributes' => [],
6570 
            },
6571 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6572 
            'width' => 32,
6573 
          },
6574 
          'reg05_td_net_x0' => {
6575 
            'attributes' => {
6576 
              'hdlNetAttributes' => [],
6577 
            },
6578 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6579 
            'width' => 32,
6580 
          },
6581 
          'reg05_tv_net' => {
6582 
            'attributes' => {
6583 
              'hdlNetAttributes' => [],
6584 
            },
6585 
            'hdlType' => 'std_logic',
6586 
            'width' => 1,
6587 
          },
6588 
          'reg05_tv_net_x0' => {
6589 
            'attributes' => {
6590 
              'hdlNetAttributes' => [],
6591 
            },
6592 
            'hdlType' => 'std_logic',
6593 
            'width' => 1,
6594 
          },
6595 
          'reg06_td_net' => {
6596 
            'attributes' => {
6597 
              'hdlNetAttributes' => [],
6598 
            },
6599 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6600 
            'width' => 32,
6601 
          },
6602 
          'reg06_td_net_x0' => {
6603 
            'attributes' => {
6604 
              'hdlNetAttributes' => [],
6605 
            },
6606 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6607 
            'width' => 32,
6608 
          },
6609 
          'reg06_tv_net' => {
6610 
            'attributes' => {
6611 
              'hdlNetAttributes' => [],
6612 
            },
6613 
            'hdlType' => 'std_logic',
6614 
            'width' => 1,
6615 
          },
6616 
          'reg06_tv_net_x0' => {
6617 
            'attributes' => {
6618 
              'hdlNetAttributes' => [],
6619 
            },
6620 
            'hdlType' => 'std_logic',
6621 
            'width' => 1,
6622 
          },
6623 
          'reg07_td_net' => {
6624 
            'attributes' => {
6625 
              'hdlNetAttributes' => [],
6626 
            },
6627 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6628 
            'width' => 32,
6629 
          },
6630 
          'reg07_td_net_x0' => {
6631 
            'attributes' => {
6632 
              'hdlNetAttributes' => [],
6633 
            },
6634 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6635 
            'width' => 32,
6636 
          },
6637 
          'reg07_tv_net' => {
6638 
            'attributes' => {
6639 
              'hdlNetAttributes' => [],
6640 
            },
6641 
            'hdlType' => 'std_logic',
6642 
            'width' => 1,
6643 
          },
6644 
          'reg07_tv_net_x0' => {
6645 
            'attributes' => {
6646 
              'hdlNetAttributes' => [],
6647 
            },
6648 
            'hdlType' => 'std_logic',
6649 
            'width' => 1,
6650 
          },
6651 
          'reg08_td_net' => {
6652 
            'attributes' => {
6653 
              'hdlNetAttributes' => [],
6654 
            },
6655 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6656 
            'width' => 32,
6657 
          },
6658 
          'reg08_td_net_x0' => {
6659 
            'attributes' => {
6660 
              'hdlNetAttributes' => [],
6661 
            },
6662 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6663 
            'width' => 32,
6664 
          },
6665 
          'reg08_tv_net' => {
6666 
            'attributes' => {
6667 
              'hdlNetAttributes' => [],
6668 
            },
6669 
            'hdlType' => 'std_logic',
6670 
            'width' => 1,
6671 
          },
6672 
          'reg08_tv_net_x0' => {
6673 
            'attributes' => {
6674 
              'hdlNetAttributes' => [],
6675 
            },
6676 
            'hdlType' => 'std_logic',
6677 
            'width' => 1,
6678 
          },
6679 
          'reg09_td_net' => {
6680 
            'attributes' => {
6681 
              'hdlNetAttributes' => [],
6682 
            },
6683 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6684 
            'width' => 32,
6685 
          },
6686 
          'reg09_td_net_x0' => {
6687 
            'attributes' => {
6688 
              'hdlNetAttributes' => [],
6689 
            },
6690 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6691 
            'width' => 32,
6692 
          },
6693 
          'reg09_tv_net' => {
6694 
            'attributes' => {
6695 
              'hdlNetAttributes' => [],
6696 
            },
6697 
            'hdlType' => 'std_logic',
6698 
            'width' => 1,
6699 
          },
6700 
          'reg09_tv_net_x0' => {
6701 
            'attributes' => {
6702 
              'hdlNetAttributes' => [],
6703 
            },
6704 
            'hdlType' => 'std_logic',
6705 
            'width' => 1,
6706 
          },
6707 
          'reg10_td_net' => {
6708 
            'attributes' => {
6709 
              'hdlNetAttributes' => [],
6710 
            },
6711 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6712 
            'width' => 32,
6713 
          },
6714 
          'reg10_td_net_x0' => {
6715 
            'attributes' => {
6716 
              'hdlNetAttributes' => [],
6717 
            },
6718 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6719 
            'width' => 32,
6720 
          },
6721 
          'reg10_tv_net' => {
6722 
            'attributes' => {
6723 
              'hdlNetAttributes' => [],
6724 
            },
6725 
            'hdlType' => 'std_logic',
6726 
            'width' => 1,
6727 
          },
6728 
          'reg10_tv_net_x0' => {
6729 
            'attributes' => {
6730 
              'hdlNetAttributes' => [],
6731 
            },
6732 
            'hdlType' => 'std_logic',
6733 
            'width' => 1,
6734 
          },
6735 
          'reg11_td_net' => {
6736 
            'attributes' => {
6737 
              'hdlNetAttributes' => [],
6738 
            },
6739 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6740 
            'width' => 32,
6741 
          },
6742 
          'reg11_td_net_x0' => {
6743 
            'attributes' => {
6744 
              'hdlNetAttributes' => [],
6745 
            },
6746 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6747 
            'width' => 32,
6748 
          },
6749 
          'reg11_tv_net' => {
6750 
            'attributes' => {
6751 
              'hdlNetAttributes' => [],
6752 
            },
6753 
            'hdlType' => 'std_logic',
6754 
            'width' => 1,
6755 
          },
6756 
          'reg11_tv_net_x0' => {
6757 
            'attributes' => {
6758 
              'hdlNetAttributes' => [],
6759 
            },
6760 
            'hdlType' => 'std_logic',
6761 
            'width' => 1,
6762 
          },
6763 
          'reg12_td_net' => {
6764 
            'attributes' => {
6765 
              'hdlNetAttributes' => [],
6766 
            },
6767 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6768 
            'width' => 32,
6769 
          },
6770 
          'reg12_td_net_x0' => {
6771 
            'attributes' => {
6772 
              'hdlNetAttributes' => [],
6773 
            },
6774 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6775 
            'width' => 32,
6776 
          },
6777 
          'reg12_tv_net' => {
6778 
            'attributes' => {
6779 
              'hdlNetAttributes' => [],
6780 
            },
6781 
            'hdlType' => 'std_logic',
6782 
            'width' => 1,
6783 
          },
6784 
          'reg12_tv_net_x0' => {
6785 
            'attributes' => {
6786 
              'hdlNetAttributes' => [],
6787 
            },
6788 
            'hdlType' => 'std_logic',
6789 
            'width' => 1,
6790 
          },
6791 
          'reg13_td_net' => {
6792 
            'attributes' => {
6793 
              'hdlNetAttributes' => [],
6794 
            },
6795 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6796 
            'width' => 32,
6797 
          },
6798 
          'reg13_td_net_x0' => {
6799 
            'attributes' => {
6800 
              'hdlNetAttributes' => [],
6801 
            },
6802 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6803 
            'width' => 32,
6804 
          },
6805 
          'reg13_tv_net' => {
6806 
            'attributes' => {
6807 
              'hdlNetAttributes' => [],
6808 
            },
6809 
            'hdlType' => 'std_logic',
6810 
            'width' => 1,
6811 
          },
6812 
          'reg13_tv_net_x0' => {
6813 
            'attributes' => {
6814 
              'hdlNetAttributes' => [],
6815 
            },
6816 
            'hdlType' => 'std_logic',
6817 
            'width' => 1,
6818 
          },
6819 
          'reg14_td_net' => {
6820 
            'attributes' => {
6821 
              'hdlNetAttributes' => [],
6822 
            },
6823 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6824 
            'width' => 32,
6825 
          },
6826 
          'reg14_td_net_x0' => {
6827 
            'attributes' => {
6828 
              'hdlNetAttributes' => [],
6829 
            },
6830 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6831 
            'width' => 32,
6832 
          },
6833 
          'reg14_tv_net' => {
6834 
            'attributes' => {
6835 
              'hdlNetAttributes' => [],
6836 
            },
6837 
            'hdlType' => 'std_logic',
6838 
            'width' => 1,
6839 
          },
6840 
          'reg14_tv_net_x0' => {
6841 
            'attributes' => {
6842 
              'hdlNetAttributes' => [],
6843 
            },
6844 
            'hdlType' => 'std_logic',
6845 
            'width' => 1,
6846 
          },
6847 
          'to_register10_dout_net' => {
6848 
            'attributes' => {
6849 
              'hdlNetAttributes' => [],
6850 
            },
6851 
            'hdlType' => 'std_logic',
6852 
            'width' => 1,
6853 
          },
6854 
          'to_register11_dout_net' => {
6855 
            'attributes' => {
6856 
              'hdlNetAttributes' => [],
6857 
            },
6858 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6859 
            'width' => 32,
6860 
          },
6861 
          'to_register12_dout_net' => {
6862 
            'attributes' => {
6863 
              'hdlNetAttributes' => [],
6864 
            },
6865 
            'hdlType' => 'std_logic',
6866 
            'width' => 1,
6867 
          },
6868 
          'to_register13_dout_net' => {
6869 
            'attributes' => {
6870 
              'hdlNetAttributes' => [],
6871 
            },
6872 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6873 
            'width' => 32,
6874 
          },
6875 
          'to_register14_dout_net' => {
6876 
            'attributes' => {
6877 
              'hdlNetAttributes' => [],
6878 
            },
6879 
            'hdlType' => 'std_logic',
6880 
            'width' => 1,
6881 
          },
6882 
          'to_register15_dout_net' => {
6883 
            'attributes' => {
6884 
              'hdlNetAttributes' => [],
6885 
            },
6886 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6887 
            'width' => 32,
6888 
          },
6889 
          'to_register16_dout_net' => {
6890 
            'attributes' => {
6891 
              'hdlNetAttributes' => [],
6892 
            },
6893 
            'hdlType' => 'std_logic',
6894 
            'width' => 1,
6895 
          },
6896 
          'to_register17_dout_net' => {
6897 
            'attributes' => {
6898 
              'hdlNetAttributes' => [],
6899 
            },
6900 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6901 
            'width' => 32,
6902 
          },
6903 
          'to_register18_dout_net' => {
6904 
            'attributes' => {
6905 
              'hdlNetAttributes' => [],
6906 
            },
6907 
            'hdlType' => 'std_logic',
6908 
            'width' => 1,
6909 
          },
6910 
          'to_register19_dout_net' => {
6911 
            'attributes' => {
6912 
              'hdlNetAttributes' => [],
6913 
            },
6914 
            'hdlType' => 'std_logic',
6915 
            'width' => 1,
6916 
          },
6917 
          'to_register1_dout_net' => {
6918 
            'attributes' => {
6919 
              'hdlNetAttributes' => [],
6920 
            },
6921 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6922 
            'width' => 32,
6923 
          },
6924 
          'to_register20_dout_net' => {
6925 
            'attributes' => {
6926 
              'hdlNetAttributes' => [],
6927 
            },
6928 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6929 
            'width' => 32,
6930 
          },
6931 
          'to_register21_dout_net' => {
6932 
            'attributes' => {
6933 
              'hdlNetAttributes' => [],
6934 
            },
6935 
            'hdlType' => 'std_logic',
6936 
            'width' => 1,
6937 
          },
6938 
          'to_register22_dout_net' => {
6939 
            'attributes' => {
6940 
              'hdlNetAttributes' => [],
6941 
            },
6942 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6943 
            'width' => 32,
6944 
          },
6945 
          'to_register23_dout_net' => {
6946 
            'attributes' => {
6947 
              'hdlNetAttributes' => [],
6948 
            },
6949 
            'hdlType' => 'std_logic',
6950 
            'width' => 1,
6951 
          },
6952 
          'to_register24_dout_net' => {
6953 
            'attributes' => {
6954 
              'hdlNetAttributes' => [],
6955 
            },
6956 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6957 
            'width' => 32,
6958 
          },
6959 
          'to_register25_dout_net' => {
6960 
            'attributes' => {
6961 
              'hdlNetAttributes' => [],
6962 
            },
6963 
            'hdlType' => 'std_logic',
6964 
            'width' => 1,
6965 
          },
6966 
          'to_register26_dout_net' => {
6967 
            'attributes' => {
6968 
              'hdlNetAttributes' => [],
6969 
            },
6970 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6971 
            'width' => 32,
6972 
          },
6973 
          'to_register27_dout_net' => {
6974 
            'attributes' => {
6975 
              'hdlNetAttributes' => [],
6976 
            },
6977 
            'hdlType' => 'std_logic',
6978 
            'width' => 1,
6979 
          },
6980 
          'to_register28_dout_net' => {
6981 
            'attributes' => {
6982 
              'hdlNetAttributes' => [],
6983 
            },
6984 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6985 
            'width' => 32,
6986 
          },
6987 
          'to_register29_dout_net' => {
6988 
            'attributes' => {
6989 
              'hdlNetAttributes' => [],
6990 
            },
6991 
            'hdlType' => 'std_logic',
6992 
            'width' => 1,
6993 
          },
6994 
          'to_register2_dout_net' => {
6995 
            'attributes' => {
6996 
              'hdlNetAttributes' => [],
6997 
            },
6998 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6999 
            'width' => 32,
7000 
          },
7001 
          'to_register30_dout_net' => {
7002 
            'attributes' => {
7003 
              'hdlNetAttributes' => [],
7004 
            },
7005 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7006 
            'width' => 32,
7007 
          },
7008 
          'to_register31_dout_net' => {
7009 
            'attributes' => {
7010 
              'hdlNetAttributes' => [],
7011 
            },
7012 
            'hdlType' => 'std_logic',
7013 
            'width' => 1,
7014 
          },
7015 
          'to_register32_dout_net' => {
7016 
            'attributes' => {
7017 
              'hdlNetAttributes' => [],
7018 
            },
7019 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7020 
            'width' => 32,
7021 
          },
7022 
          'to_register33_dout_net' => {
7023 
            'attributes' => {
7024 
              'hdlNetAttributes' => [],
7025 
            },
7026 
            'hdlType' => 'std_logic',
7027 
            'width' => 1,
7028 
          },
7029 
          'to_register34_dout_net' => {
7030 
            'attributes' => {
7031 
              'hdlNetAttributes' => [],
7032 
            },
7033 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7034 
            'width' => 32,
7035 
          },
7036 
          'to_register3_dout_net' => {
7037 
            'attributes' => {
7038 
              'hdlNetAttributes' => [],
7039 
            },
7040 
            'hdlType' => 'std_logic',
7041 
            'width' => 1,
7042 
          },
7043 
          'to_register4_dout_net' => {
7044 
            'attributes' => {
7045 
              'hdlNetAttributes' => [],
7046 
            },
7047 
            'hdlType' => 'std_logic',
7048 
            'width' => 1,
7049 
          },
7050 
          'to_register5_dout_net' => {
7051 
            'attributes' => {
7052 
              'hdlNetAttributes' => [],
7053 
            },
7054 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7055 
            'width' => 32,
7056 
          },
7057 
          'to_register6_dout_net' => {
7058 
            'attributes' => {
7059 
              'hdlNetAttributes' => [],
7060 
            },
7061 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7062 
            'width' => 32,
7063 
          },
7064 
          'to_register7_dout_net' => {
7065 
            'attributes' => {
7066 
              'hdlNetAttributes' => [],
7067 
            },
7068 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7069 
            'width' => 32,
7070 
          },
7071 
          'to_register8_dout_net' => {
7072 
            'attributes' => {
7073 
              'hdlNetAttributes' => [],
7074 
            },
7075 
            'hdlType' => 'std_logic',
7076 
            'width' => 1,
7077 
          },
7078 
          'to_register9_dout_net' => {
7079 
            'attributes' => {
7080 
              'hdlNetAttributes' => [],
7081 
            },
7082 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7083 
            'width' => 32,
7084 
          },
7085 
        },
7086 
        'ports' => {
7087 
          'ce' => {
7088 
            'attributes' => {
7089 
              'defaultHdlValue' => '\'1\'',
7090 
              'domain' => 'default',
7091 
              'group' => 4,
7092 
              'isCe' => 1,
7093 
              'period' => 1,
7094 
            },
7095 
            'direction' => 'in',
7096 
            'hdlType' => 'std_logic',
7097 
            'width' => 1,
7098 
          },
7099 
          'clk' => {
7100 
            'attributes' => {
7101 
              'domain' => 'default',
7102 
              'group' => 4,
7103 
              'isClk' => 1,
7104 
              'period' => 1,
7105 
              'type' => 'logic',
7106 
            },
7107 
            'direction' => 'in',
7108 
            'hdlType' => 'std_logic',
7109 
            'width' => 1,
7110 
          },
7111 
          'debug_in_1i' => {
7112 
            'attributes' => {
7113 
              'bin_pt' => 0,
7114 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
7115 
              'is_floating_block' => 1,
7116 
              'is_gateway_port' => 1,
7117 
              'must_be_hdl_vector' => 1,
7118 
              'period' => 1,
7119 
              'port_id' => 0,
7120 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
7121 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
7122 
              'timingConstraint' => 'none',
7123 
              'type' => 'UFix_32_0',
7124 
            },
7125 
            'direction' => 'in',
7126 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7127 
            'width' => 32,
7128 
          },
7129 
          'debug_in_2i' => {
7130 
            'attributes' => {
7131 
              'bin_pt' => 0,
7132 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
7133 
              'is_floating_block' => 1,
7134 
              'is_gateway_port' => 1,
7135 
              'must_be_hdl_vector' => 1,
7136 
              'period' => 1,
7137 
              'port_id' => 0,
7138 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
7139 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
7140 
              'timingConstraint' => 'none',
7141 
              'type' => 'UFix_32_0',
7142 
            },
7143 
            'direction' => 'in',
7144 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7145 
            'width' => 32,
7146 
          },
7147 
          'debug_in_3i' => {
7148 
            'attributes' => {
7149 
              'bin_pt' => 0,
7150 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
7151 
              'is_floating_block' => 1,
7152 
              'is_gateway_port' => 1,
7153 
              'must_be_hdl_vector' => 1,
7154 
              'period' => 1,
7155 
              'port_id' => 0,
7156 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
7157 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
7158 
              'timingConstraint' => 'none',
7159 
              'type' => 'UFix_32_0',
7160 
            },
7161 
            'direction' => 'in',
7162 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7163 
            'width' => 32,
7164 
          },
7165 
          'debug_in_4i' => {
7166 
            'attributes' => {
7167 
              'bin_pt' => 0,
7168 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
7169 
              'is_floating_block' => 1,
7170 
              'is_gateway_port' => 1,
7171 
              'must_be_hdl_vector' => 1,
7172 
              'period' => 1,
7173 
              'port_id' => 0,
7174 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
7175 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
7176 
              'timingConstraint' => 'none',
7177 
              'type' => 'UFix_32_0',
7178 
            },
7179 
            'direction' => 'in',
7180 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7181 
            'width' => 32,
7182 
          },
7183 
          'dma_host2board_busy' => {
7184 
            'attributes' => {
7185 
              'bin_pt' => 0,
7186 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
7187 
              'is_floating_block' => 1,
7188 
              'is_gateway_port' => 1,
7189 
              'must_be_hdl_vector' => 1,
7190 
              'period' => 1,
7191 
              'port_id' => 0,
7192 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
7193 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
7194 
              'timingConstraint' => 'none',
7195 
              'type' => 'UFix_1_0',
7196 
            },
7197 
            'direction' => 'in',
7198 
            'hdlType' => 'std_logic',
7199 
            'width' => 1,
7200 
          },
7201 
          'dma_host2board_done' => {
7202 
            'attributes' => {
7203 
              'bin_pt' => 0,
7204 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
7205 
              'is_floating_block' => 1,
7206 
              'is_gateway_port' => 1,
7207 
              'must_be_hdl_vector' => 1,
7208 
              'period' => 1,
7209 
              'port_id' => 0,
7210 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
7211 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
7212 
              'timingConstraint' => 'none',
7213 
              'type' => 'UFix_1_0',
7214 
            },
7215 
            'direction' => 'in',
7216 
            'hdlType' => 'std_logic',
7217 
            'width' => 1,
7218 
          },
7219 
          'from_register10_data_out' => {
7220 
            'attributes' => {
7221 
              'bin_pt' => 0,
7222 
              'is_floating_block' => 1,
7223 
              'must_be_hdl_vector' => 1,
7224 
              'period' => 1,
7225 
              'port_id' => 0,
7226 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
7227 
              'type' => 'UFix_32_0',
7228 
            },
7229 
            'direction' => 'in',
7230 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7231 
            'width' => 32,
7232 
          },
7233 
          'from_register11_data_out' => {
7234 
            'attributes' => {
7235 
              'bin_pt' => 0,
7236 
              'is_floating_block' => 1,
7237 
              'must_be_hdl_vector' => 1,
7238 
              'period' => 1,
7239 
              'port_id' => 0,
7240 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
7241 
              'type' => 'UFix_32_0',
7242 
            },
7243 
            'direction' => 'in',
7244 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7245 
            'width' => 32,
7246 
          },
7247 
          'from_register12_data_out' => {
7248 
            'attributes' => {
7249 
              'bin_pt' => 0,
7250 
              'is_floating_block' => 1,
7251 
              'must_be_hdl_vector' => 1,
7252 
              'period' => 1,
7253 
              'port_id' => 0,
7254 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
7255 
              'type' => 'UFix_1_0',
7256 
            },
7257 
            'direction' => 'in',
7258 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7259 
            'width' => 1,
7260 
          },
7261 
          'from_register13_data_out' => {
7262 
            'attributes' => {
7263 
              'bin_pt' => 0,
7264 
              'is_floating_block' => 1,
7265 
              'must_be_hdl_vector' => 1,
7266 
              'period' => 1,
7267 
              'port_id' => 0,
7268 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
7269 
              'type' => 'UFix_32_0',
7270 
            },
7271 
            'direction' => 'in',
7272 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7273 
            'width' => 32,
7274 
          },
7275 
          'from_register14_data_out' => {
7276 
            'attributes' => {
7277 
              'bin_pt' => 0,
7278 
              'is_floating_block' => 1,
7279 
              'must_be_hdl_vector' => 1,
7280 
              'period' => 1,
7281 
              'port_id' => 0,
7282 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
7283 
              'type' => 'UFix_1_0',
7284 
            },
7285 
            'direction' => 'in',
7286 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7287 
            'width' => 1,
7288 
          },
7289 
          'from_register15_data_out' => {
7290 
            'attributes' => {
7291 
              'bin_pt' => 0,
7292 
              'is_floating_block' => 1,
7293 
              'must_be_hdl_vector' => 1,
7294 
              'period' => 1,
7295 
              'port_id' => 0,
7296 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
7297 
              'type' => 'UFix_32_0',
7298 
            },
7299 
            'direction' => 'in',
7300 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7301 
            'width' => 32,
7302 
          },
7303 
          'from_register16_data_out' => {
7304 
            'attributes' => {
7305 
              'bin_pt' => 0,
7306 
              'is_floating_block' => 1,
7307 
              'must_be_hdl_vector' => 1,
7308 
              'period' => 1,
7309 
              'port_id' => 0,
7310 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
7311 
              'type' => 'UFix_1_0',
7312 
            },
7313 
            'direction' => 'in',
7314 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7315 
            'width' => 1,
7316 
          },
7317 
          'from_register17_data_out' => {
7318 
            'attributes' => {
7319 
              'bin_pt' => 0,
7320 
              'is_floating_block' => 1,
7321 
              'must_be_hdl_vector' => 1,
7322 
              'period' => 1,
7323 
              'port_id' => 0,
7324 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
7325 
              'type' => 'UFix_32_0',
7326 
            },
7327 
            'direction' => 'in',
7328 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7329 
            'width' => 32,
7330 
          },
7331 
          'from_register18_data_out' => {
7332 
            'attributes' => {
7333 
              'bin_pt' => 0,
7334 
              'is_floating_block' => 1,
7335 
              'must_be_hdl_vector' => 1,
7336 
              'period' => 1,
7337 
              'port_id' => 0,
7338 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
7339 
              'type' => 'UFix_1_0',
7340 
            },
7341 
            'direction' => 'in',
7342 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7343 
            'width' => 1,
7344 
          },
7345 
          'from_register19_data_out' => {
7346 
            'attributes' => {
7347 
              'bin_pt' => 0,
7348 
              'is_floating_block' => 1,
7349 
              'must_be_hdl_vector' => 1,
7350 
              'period' => 1,
7351 
              'port_id' => 0,
7352 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
7353 
              'type' => 'UFix_32_0',
7354 
            },
7355 
            'direction' => 'in',
7356 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7357 
            'width' => 32,
7358 
          },
7359 
          'from_register1_data_out' => {
7360 
            'attributes' => {
7361 
              'bin_pt' => 0,
7362 
              'is_floating_block' => 1,
7363 
              'must_be_hdl_vector' => 1,
7364 
              'period' => 1,
7365 
              'port_id' => 0,
7366 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
7367 
              'type' => 'UFix_1_0',
7368 
            },
7369 
            'direction' => 'in',
7370 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7371 
            'width' => 1,
7372 
          },
7373 
          'from_register20_data_out' => {
7374 
            'attributes' => {
7375 
              'bin_pt' => 0,
7376 
              'is_floating_block' => 1,
7377 
              'must_be_hdl_vector' => 1,
7378 
              'period' => 1,
7379 
              'port_id' => 0,
7380 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
7381 
              'type' => 'UFix_1_0',
7382 
            },
7383 
            'direction' => 'in',
7384 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7385 
            'width' => 1,
7386 
          },
7387 
          'from_register21_data_out' => {
7388 
            'attributes' => {
7389 
              'bin_pt' => 0,
7390 
              'is_floating_block' => 1,
7391 
              'must_be_hdl_vector' => 1,
7392 
              'period' => 1,
7393 
              'port_id' => 0,
7394 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
7395 
              'type' => 'UFix_32_0',
7396 
            },
7397 
            'direction' => 'in',
7398 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7399 
            'width' => 32,
7400 
          },
7401 
          'from_register22_data_out' => {
7402 
            'attributes' => {
7403 
              'bin_pt' => 0,
7404 
              'is_floating_block' => 1,
7405 
              'must_be_hdl_vector' => 1,
7406 
              'period' => 1,
7407 
              'port_id' => 0,
7408 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
7409 
              'type' => 'UFix_1_0',
7410 
            },
7411 
            'direction' => 'in',
7412 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7413 
            'width' => 1,
7414 
          },
7415 
          'from_register23_data_out' => {
7416 
            'attributes' => {
7417 
              'bin_pt' => 0,
7418 
              'is_floating_block' => 1,
7419 
              'must_be_hdl_vector' => 1,
7420 
              'period' => 1,
7421 
              'port_id' => 0,
7422 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
7423 
              'type' => 'UFix_32_0',
7424 
            },
7425 
            'direction' => 'in',
7426 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7427 
            'width' => 32,
7428 
          },
7429 
          'from_register24_data_out' => {
7430 
            'attributes' => {
7431 
              'bin_pt' => 0,
7432 
              'is_floating_block' => 1,
7433 
              'must_be_hdl_vector' => 1,
7434 
              'period' => 1,
7435 
              'port_id' => 0,
7436 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
7437 
              'type' => 'UFix_1_0',
7438 
            },
7439 
            'direction' => 'in',
7440 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7441 
            'width' => 1,
7442 
          },
7443 
          'from_register25_data_out' => {
7444 
            'attributes' => {
7445 
              'bin_pt' => 0,
7446 
              'is_floating_block' => 1,
7447 
              'must_be_hdl_vector' => 1,
7448 
              'period' => 1,
7449 
              'port_id' => 0,
7450 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
7451 
              'type' => 'UFix_32_0',
7452 
            },
7453 
            'direction' => 'in',
7454 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7455 
            'width' => 32,
7456 
          },
7457 
          'from_register26_data_out' => {
7458 
            'attributes' => {
7459 
              'bin_pt' => 0,
7460 
              'is_floating_block' => 1,
7461 
              'must_be_hdl_vector' => 1,
7462 
              'period' => 1,
7463 
              'port_id' => 0,
7464 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
7465 
              'type' => 'UFix_1_0',
7466 
            },
7467 
            'direction' => 'in',
7468 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7469 
            'width' => 1,
7470 
          },
7471 
          'from_register27_data_out' => {
7472 
            'attributes' => {
7473 
              'bin_pt' => 0,
7474 
              'is_floating_block' => 1,
7475 
              'must_be_hdl_vector' => 1,
7476 
              'period' => 1,
7477 
              'port_id' => 0,
7478 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
7479 
              'type' => 'UFix_32_0',
7480 
            },
7481 
            'direction' => 'in',
7482 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7483 
            'width' => 32,
7484 
          },
7485 
          'from_register28_data_out' => {
7486 
            'attributes' => {
7487 
              'bin_pt' => 0,
7488 
              'is_floating_block' => 1,
7489 
              'must_be_hdl_vector' => 1,
7490 
              'period' => 1,
7491 
              'port_id' => 0,
7492 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
7493 
              'type' => 'UFix_1_0',
7494 
            },
7495 
            'direction' => 'in',
7496 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7497 
            'width' => 1,
7498 
          },
7499 
          'from_register2_data_out' => {
7500 
            'attributes' => {
7501 
              'bin_pt' => 0,
7502 
              'is_floating_block' => 1,
7503 
              'must_be_hdl_vector' => 1,
7504 
              'period' => 1,
7505 
              'port_id' => 0,
7506 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
7507 
              'type' => 'UFix_1_0',
7508 
            },
7509 
            'direction' => 'in',
7510 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7511 
            'width' => 1,
7512 
          },
7513 
          'from_register3_data_out' => {
7514 
            'attributes' => {
7515 
              'bin_pt' => 0,
7516 
              'is_floating_block' => 1,
7517 
              'must_be_hdl_vector' => 1,
7518 
              'period' => 1,
7519 
              'port_id' => 0,
7520 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
7521 
              'type' => 'UFix_32_0',
7522 
            },
7523 
            'direction' => 'in',
7524 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7525 
            'width' => 32,
7526 
          },
7527 
          'from_register4_data_out' => {
7528 
            'attributes' => {
7529 
              'bin_pt' => 0,
7530 
              'is_floating_block' => 1,
7531 
              'must_be_hdl_vector' => 1,
7532 
              'period' => 1,
7533 
              'port_id' => 0,
7534 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
7535 
              'type' => 'UFix_1_0',
7536 
            },
7537 
            'direction' => 'in',
7538 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7539 
            'width' => 1,
7540 
          },
7541 
          'from_register5_data_out' => {
7542 
            'attributes' => {
7543 
              'bin_pt' => 0,
7544 
              'is_floating_block' => 1,
7545 
              'must_be_hdl_vector' => 1,
7546 
              'period' => 1,
7547 
              'port_id' => 0,
7548 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
7549 
              'type' => 'UFix_32_0',
7550 
            },
7551 
            'direction' => 'in',
7552 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7553 
            'width' => 32,
7554 
          },
7555 
          'from_register6_data_out' => {
7556 
            'attributes' => {
7557 
              'bin_pt' => 0,
7558 
              'is_floating_block' => 1,
7559 
              'must_be_hdl_vector' => 1,
7560 
              'period' => 1,
7561 
              'port_id' => 0,
7562 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
7563 
              'type' => 'UFix_1_0',
7564 
            },
7565 
            'direction' => 'in',
7566 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7567 
            'width' => 1,
7568 
          },
7569 
          'from_register7_data_out' => {
7570 
            'attributes' => {
7571 
              'bin_pt' => 0,
7572 
              'is_floating_block' => 1,
7573 
              'must_be_hdl_vector' => 1,
7574 
              'period' => 1,
7575 
              'port_id' => 0,
7576 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
7577 
              'type' => 'UFix_32_0',
7578 
            },
7579 
            'direction' => 'in',
7580 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7581 
            'width' => 32,
7582 
          },
7583 
          'from_register8_data_out' => {
7584 
            'attributes' => {
7585 
              'bin_pt' => 0,
7586 
              'is_floating_block' => 1,
7587 
              'must_be_hdl_vector' => 1,
7588 
              'period' => 1,
7589 
              'port_id' => 0,
7590 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
7591 
              'type' => 'UFix_32_0',
7592 
            },
7593 
            'direction' => 'in',
7594 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7595 
            'width' => 32,
7596 
          },
7597 
          'from_register9_data_out' => {
7598 
            'attributes' => {
7599 
              'bin_pt' => 0,
7600 
              'is_floating_block' => 1,
7601 
              'must_be_hdl_vector' => 1,
7602 
              'period' => 1,
7603 
              'port_id' => 0,
7604 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
7605 
              'type' => 'UFix_1_0',
7606 
            },
7607 
            'direction' => 'in',
7608 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7609 
            'width' => 1,
7610 
          },
7611 
          'reg01_rd' => {
7612 
            'attributes' => {
7613 
              'bin_pt' => 0,
7614 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
7615 
              'is_floating_block' => 1,
7616 
              'is_gateway_port' => 1,
7617 
              'must_be_hdl_vector' => 1,
7618 
              'period' => 1,
7619 
              'port_id' => 0,
7620 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
7621 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
7622 
              'timingConstraint' => 'none',
7623 
              'type' => 'UFix_32_0',
7624 
            },
7625 
            'direction' => 'out',
7626 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7627 
            'width' => 32,
7628 
          },
7629 
          'reg01_rv' => {
7630 
            'attributes' => {
7631 
              'bin_pt' => 0,
7632 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
7633 
              'is_floating_block' => 1,
7634 
              'is_gateway_port' => 1,
7635 
              'must_be_hdl_vector' => 1,
7636 
              'period' => 1,
7637 
              'port_id' => 0,
7638 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
7639 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
7640 
              'timingConstraint' => 'none',
7641 
              'type' => 'UFix_1_0',
7642 
            },
7643 
            'direction' => 'out',
7644 
            'hdlType' => 'std_logic',
7645 
            'width' => 1,
7646 
          },
7647 
          'reg01_td' => {
7648 
            'attributes' => {
7649 
              'bin_pt' => 0,
7650 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
7651 
              'is_floating_block' => 1,
7652 
              'is_gateway_port' => 1,
7653 
              'must_be_hdl_vector' => 1,
7654 
              'period' => 1,
7655 
              'port_id' => 0,
7656 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
7657 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
7658 
              'timingConstraint' => 'none',
7659 
              'type' => 'UFix_32_0',
7660 
            },
7661 
            'direction' => 'in',
7662 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7663 
            'width' => 32,
7664 
          },
7665 
          'reg01_tv' => {
7666 
            'attributes' => {
7667 
              'bin_pt' => 0,
7668 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
7669 
              'is_floating_block' => 1,
7670 
              'is_gateway_port' => 1,
7671 
              'must_be_hdl_vector' => 1,
7672 
              'period' => 1,
7673 
              'port_id' => 0,
7674 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
7675 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
7676 
              'timingConstraint' => 'none',
7677 
              'type' => 'Bool',
7678 
            },
7679 
            'direction' => 'in',
7680 
            'hdlType' => 'std_logic',
7681 
            'width' => 1,
7682 
          },
7683 
          'reg02_rd' => {
7684 
            'attributes' => {
7685 
              'bin_pt' => 0,
7686 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
7687 
              'is_floating_block' => 1,
7688 
              'is_gateway_port' => 1,
7689 
              'must_be_hdl_vector' => 1,
7690 
              'period' => 1,
7691 
              'port_id' => 0,
7692 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
7693 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
7694 
              'timingConstraint' => 'none',
7695 
              'type' => 'UFix_32_0',
7696 
            },
7697 
            'direction' => 'out',
7698 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7699 
            'width' => 32,
7700 
          },
7701 
          'reg02_rv' => {
7702 
            'attributes' => {
7703 
              'bin_pt' => 0,
7704 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
7705 
              'is_floating_block' => 1,
7706 
              'is_gateway_port' => 1,
7707 
              'must_be_hdl_vector' => 1,
7708 
              'period' => 1,
7709 
              'port_id' => 0,
7710 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
7711 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
7712 
              'timingConstraint' => 'none',
7713 
              'type' => 'UFix_1_0',
7714 
            },
7715 
            'direction' => 'out',
7716 
            'hdlType' => 'std_logic',
7717 
            'width' => 1,
7718 
          },
7719 
          'reg02_td' => {
7720 
            'attributes' => {
7721 
              'bin_pt' => 0,
7722 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
7723 
              'is_floating_block' => 1,
7724 
              'is_gateway_port' => 1,
7725 
              'must_be_hdl_vector' => 1,
7726 
              'period' => 1,
7727 
              'port_id' => 0,
7728 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
7729 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
7730 
              'timingConstraint' => 'none',
7731 
              'type' => 'UFix_32_0',
7732 
            },
7733 
            'direction' => 'in',
7734 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7735 
            'width' => 32,
7736 
          },
7737 
          'reg02_tv' => {
7738 
            'attributes' => {
7739 
              'bin_pt' => 0,
7740 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
7741 
              'is_floating_block' => 1,
7742 
              'is_gateway_port' => 1,
7743 
              'must_be_hdl_vector' => 1,
7744 
              'period' => 1,
7745 
              'port_id' => 0,
7746 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
7747 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
7748 
              'timingConstraint' => 'none',
7749 
              'type' => 'Bool',
7750 
            },
7751 
            'direction' => 'in',
7752 
            'hdlType' => 'std_logic',
7753 
            'width' => 1,
7754 
          },
7755 
          'reg03_rd' => {
7756 
            'attributes' => {
7757 
              'bin_pt' => 0,
7758 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
7759 
              'is_floating_block' => 1,
7760 
              'is_gateway_port' => 1,
7761 
              'must_be_hdl_vector' => 1,
7762 
              'period' => 1,
7763 
              'port_id' => 0,
7764 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
7765 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
7766 
              'timingConstraint' => 'none',
7767 
              'type' => 'UFix_32_0',
7768 
            },
7769 
            'direction' => 'out',
7770 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7771 
            'width' => 32,
7772 
          },
7773 
          'reg03_rv' => {
7774 
            'attributes' => {
7775 
              'bin_pt' => 0,
7776 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
7777 
              'is_floating_block' => 1,
7778 
              'is_gateway_port' => 1,
7779 
              'must_be_hdl_vector' => 1,
7780 
              'period' => 1,
7781 
              'port_id' => 0,
7782 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
7783 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
7784 
              'timingConstraint' => 'none',
7785 
              'type' => 'UFix_1_0',
7786 
            },
7787 
            'direction' => 'out',
7788 
            'hdlType' => 'std_logic',
7789 
            'width' => 1,
7790 
          },
7791 
          'reg03_td' => {
7792 
            'attributes' => {
7793 
              'bin_pt' => 0,
7794 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
7795 
              'is_floating_block' => 1,
7796 
              'is_gateway_port' => 1,
7797 
              'must_be_hdl_vector' => 1,
7798 
              'period' => 1,
7799 
              'port_id' => 0,
7800 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
7801 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
7802 
              'timingConstraint' => 'none',
7803 
              'type' => 'UFix_32_0',
7804 
            },
7805 
            'direction' => 'in',
7806 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7807 
            'width' => 32,
7808 
          },
7809 
          'reg03_tv' => {
7810 
            'attributes' => {
7811 
              'bin_pt' => 0,
7812 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
7813 
              'is_floating_block' => 1,
7814 
              'is_gateway_port' => 1,
7815 
              'must_be_hdl_vector' => 1,
7816 
              'period' => 1,
7817 
              'port_id' => 0,
7818 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
7819 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
7820 
              'timingConstraint' => 'none',
7821 
              'type' => 'Bool',
7822 
            },
7823 
            'direction' => 'in',
7824 
            'hdlType' => 'std_logic',
7825 
            'width' => 1,
7826 
          },
7827 
          'reg04_rd' => {
7828 
            'attributes' => {
7829 
              'bin_pt' => 0,
7830 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
7831 
              'is_floating_block' => 1,
7832 
              'is_gateway_port' => 1,
7833 
              'must_be_hdl_vector' => 1,
7834 
              'period' => 1,
7835 
              'port_id' => 0,
7836 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
7837 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
7838 
              'timingConstraint' => 'none',
7839 
              'type' => 'UFix_32_0',
7840 
            },
7841 
            'direction' => 'out',
7842 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7843 
            'width' => 32,
7844 
          },
7845 
          'reg04_rv' => {
7846 
            'attributes' => {
7847 
              'bin_pt' => 0,
7848 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
7849 
              'is_floating_block' => 1,
7850 
              'is_gateway_port' => 1,
7851 
              'must_be_hdl_vector' => 1,
7852 
              'period' => 1,
7853 
              'port_id' => 0,
7854 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
7855 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
7856 
              'timingConstraint' => 'none',
7857 
              'type' => 'UFix_1_0',
7858 
            },
7859 
            'direction' => 'out',
7860 
            'hdlType' => 'std_logic',
7861 
            'width' => 1,
7862 
          },
7863 
          'reg04_td' => {
7864 
            'attributes' => {
7865 
              'bin_pt' => 0,
7866 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
7867 
              'is_floating_block' => 1,
7868 
              'is_gateway_port' => 1,
7869 
              'must_be_hdl_vector' => 1,
7870 
              'period' => 1,
7871 
              'port_id' => 0,
7872 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
7873 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
7874 
              'timingConstraint' => 'none',
7875 
              'type' => 'UFix_32_0',
7876 
            },
7877 
            'direction' => 'in',
7878 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7879 
            'width' => 32,
7880 
          },
7881 
          'reg04_tv' => {
7882 
            'attributes' => {
7883 
              'bin_pt' => 0,
7884 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
7885 
              'is_floating_block' => 1,
7886 
              'is_gateway_port' => 1,
7887 
              'must_be_hdl_vector' => 1,
7888 
              'period' => 1,
7889 
              'port_id' => 0,
7890 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
7891 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
7892 
              'timingConstraint' => 'none',
7893 
              'type' => 'Bool',
7894 
            },
7895 
            'direction' => 'in',
7896 
            'hdlType' => 'std_logic',
7897 
            'width' => 1,
7898 
          },
7899 
          'reg05_rd' => {
7900 
            'attributes' => {
7901 
              'bin_pt' => 0,
7902 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
7903 
              'is_floating_block' => 1,
7904 
              'is_gateway_port' => 1,
7905 
              'must_be_hdl_vector' => 1,
7906 
              'period' => 1,
7907 
              'port_id' => 0,
7908 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
7909 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
7910 
              'timingConstraint' => 'none',
7911 
              'type' => 'UFix_32_0',
7912 
            },
7913 
            'direction' => 'out',
7914 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7915 
            'width' => 32,
7916 
          },
7917 
          'reg05_rv' => {
7918 
            'attributes' => {
7919 
              'bin_pt' => 0,
7920 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
7921 
              'is_floating_block' => 1,
7922 
              'is_gateway_port' => 1,
7923 
              'must_be_hdl_vector' => 1,
7924 
              'period' => 1,
7925 
              'port_id' => 0,
7926 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
7927 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
7928 
              'timingConstraint' => 'none',
7929 
              'type' => 'UFix_1_0',
7930 
            },
7931 
            'direction' => 'out',
7932 
            'hdlType' => 'std_logic',
7933 
            'width' => 1,
7934 
          },
7935 
          'reg05_td' => {
7936 
            'attributes' => {
7937 
              'bin_pt' => 0,
7938 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
7939 
              'is_floating_block' => 1,
7940 
              'is_gateway_port' => 1,
7941 
              'must_be_hdl_vector' => 1,
7942 
              'period' => 1,
7943 
              'port_id' => 0,
7944 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
7945 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
7946 
              'timingConstraint' => 'none',
7947 
              'type' => 'UFix_32_0',
7948 
            },
7949 
            'direction' => 'in',
7950 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7951 
            'width' => 32,
7952 
          },
7953 
          'reg05_tv' => {
7954 
            'attributes' => {
7955 
              'bin_pt' => 0,
7956 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
7957 
              'is_floating_block' => 1,
7958 
              'is_gateway_port' => 1,
7959 
              'must_be_hdl_vector' => 1,
7960 
              'period' => 1,
7961 
              'port_id' => 0,
7962 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
7963 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
7964 
              'timingConstraint' => 'none',
7965 
              'type' => 'Bool',
7966 
            },
7967 
            'direction' => 'in',
7968 
            'hdlType' => 'std_logic',
7969 
            'width' => 1,
7970 
          },
7971 
          'reg06_rd' => {
7972 
            'attributes' => {
7973 
              'bin_pt' => 0,
7974 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
7975 
              'is_floating_block' => 1,
7976 
              'is_gateway_port' => 1,
7977 
              'must_be_hdl_vector' => 1,
7978 
              'period' => 1,
7979 
              'port_id' => 0,
7980 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
7981 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
7982 
              'timingConstraint' => 'none',
7983 
              'type' => 'UFix_32_0',
7984 
            },
7985 
            'direction' => 'out',
7986 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7987 
            'width' => 32,
7988 
          },
7989 
          'reg06_rv' => {
7990 
            'attributes' => {
7991 
              'bin_pt' => 0,
7992 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
7993 
              'is_floating_block' => 1,
7994 
              'is_gateway_port' => 1,
7995 
              'must_be_hdl_vector' => 1,
7996 
              'period' => 1,
7997 
              'port_id' => 0,
7998 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
7999 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
8000 
              'timingConstraint' => 'none',
8001 
              'type' => 'UFix_1_0',
8002 
            },
8003 
            'direction' => 'out',
8004 
            'hdlType' => 'std_logic',
8005 
            'width' => 1,
8006 
          },
8007 
          'reg06_td' => {
8008 
            'attributes' => {
8009 
              'bin_pt' => 0,
8010 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
8011 
              'is_floating_block' => 1,
8012 
              'is_gateway_port' => 1,
8013 
              'must_be_hdl_vector' => 1,
8014 
              'period' => 1,
8015 
              'port_id' => 0,
8016 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
8017 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
8018 
              'timingConstraint' => 'none',
8019 
              'type' => 'UFix_32_0',
8020 
            },
8021 
            'direction' => 'in',
8022 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8023 
            'width' => 32,
8024 
          },
8025 
          'reg06_tv' => {
8026 
            'attributes' => {
8027 
              'bin_pt' => 0,
8028 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
8029 
              'is_floating_block' => 1,
8030 
              'is_gateway_port' => 1,
8031 
              'must_be_hdl_vector' => 1,
8032 
              'period' => 1,
8033 
              'port_id' => 0,
8034 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
8035 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
8036 
              'timingConstraint' => 'none',
8037 
              'type' => 'Bool',
8038 
            },
8039 
            'direction' => 'in',
8040 
            'hdlType' => 'std_logic',
8041 
            'width' => 1,
8042 
          },
8043 
          'reg07_rd' => {
8044 
            'attributes' => {
8045 
              'bin_pt' => 0,
8046 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
8047 
              'is_floating_block' => 1,
8048 
              'is_gateway_port' => 1,
8049 
              'must_be_hdl_vector' => 1,
8050 
              'period' => 1,
8051 
              'port_id' => 0,
8052 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
8053 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
8054 
              'timingConstraint' => 'none',
8055 
              'type' => 'UFix_32_0',
8056 
            },
8057 
            'direction' => 'out',
8058 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8059 
            'width' => 32,
8060 
          },
8061 
          'reg07_rv' => {
8062 
            'attributes' => {
8063 
              'bin_pt' => 0,
8064 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
8065 
              'is_floating_block' => 1,
8066 
              'is_gateway_port' => 1,
8067 
              'must_be_hdl_vector' => 1,
8068 
              'period' => 1,
8069 
              'port_id' => 0,
8070 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
8071 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
8072 
              'timingConstraint' => 'none',
8073 
              'type' => 'UFix_1_0',
8074 
            },
8075 
            'direction' => 'out',
8076 
            'hdlType' => 'std_logic',
8077 
            'width' => 1,
8078 
          },
8079 
          'reg07_td' => {
8080 
            'attributes' => {
8081 
              'bin_pt' => 0,
8082 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
8083 
              'is_floating_block' => 1,
8084 
              'is_gateway_port' => 1,
8085 
              'must_be_hdl_vector' => 1,
8086 
              'period' => 1,
8087 
              'port_id' => 0,
8088 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
8089 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
8090 
              'timingConstraint' => 'none',
8091 
              'type' => 'UFix_32_0',
8092 
            },
8093 
            'direction' => 'in',
8094 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8095 
            'width' => 32,
8096 
          },
8097 
          'reg07_tv' => {
8098 
            'attributes' => {
8099 
              'bin_pt' => 0,
8100 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
8101 
              'is_floating_block' => 1,
8102 
              'is_gateway_port' => 1,
8103 
              'must_be_hdl_vector' => 1,
8104 
              'period' => 1,
8105 
              'port_id' => 0,
8106 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
8107 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
8108 
              'timingConstraint' => 'none',
8109 
              'type' => 'Bool',
8110 
            },
8111 
            'direction' => 'in',
8112 
            'hdlType' => 'std_logic',
8113 
            'width' => 1,
8114 
          },
8115 
          'reg08_rd' => {
8116 
            'attributes' => {
8117 
              'bin_pt' => 0,
8118 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
8119 
              'is_floating_block' => 1,
8120 
              'is_gateway_port' => 1,
8121 
              'must_be_hdl_vector' => 1,
8122 
              'period' => 1,
8123 
              'port_id' => 0,
8124 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
8125 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
8126 
              'timingConstraint' => 'none',
8127 
              'type' => 'UFix_32_0',
8128 
            },
8129 
            'direction' => 'out',
8130 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8131 
            'width' => 32,
8132 
          },
8133 
          'reg08_rv' => {
8134 
            'attributes' => {
8135 
              'bin_pt' => 0,
8136 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
8137 
              'is_floating_block' => 1,
8138 
              'is_gateway_port' => 1,
8139 
              'must_be_hdl_vector' => 1,
8140 
              'period' => 1,
8141 
              'port_id' => 0,
8142 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
8143 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
8144 
              'timingConstraint' => 'none',
8145 
              'type' => 'UFix_1_0',
8146 
            },
8147 
            'direction' => 'out',
8148 
            'hdlType' => 'std_logic',
8149 
            'width' => 1,
8150 
          },
8151 
          'reg08_td' => {
8152 
            'attributes' => {
8153 
              'bin_pt' => 0,
8154 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
8155 
              'is_floating_block' => 1,
8156 
              'is_gateway_port' => 1,
8157 
              'must_be_hdl_vector' => 1,
8158 
              'period' => 1,
8159 
              'port_id' => 0,
8160 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
8161 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
8162 
              'timingConstraint' => 'none',
8163 
              'type' => 'UFix_32_0',
8164 
            },
8165 
            'direction' => 'in',
8166 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8167 
            'width' => 32,
8168 
          },
8169 
          'reg08_tv' => {
8170 
            'attributes' => {
8171 
              'bin_pt' => 0,
8172 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
8173 
              'is_floating_block' => 1,
8174 
              'is_gateway_port' => 1,
8175 
              'must_be_hdl_vector' => 1,
8176 
              'period' => 1,
8177 
              'port_id' => 0,
8178 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
8179 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
8180 
              'timingConstraint' => 'none',
8181 
              'type' => 'Bool',
8182 
            },
8183 
            'direction' => 'in',
8184 
            'hdlType' => 'std_logic',
8185 
            'width' => 1,
8186 
          },
8187 
          'reg09_rd' => {
8188 
            'attributes' => {
8189 
              'bin_pt' => 0,
8190 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
8191 
              'is_floating_block' => 1,
8192 
              'is_gateway_port' => 1,
8193 
              'must_be_hdl_vector' => 1,
8194 
              'period' => 1,
8195 
              'port_id' => 0,
8196 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
8197 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
8198 
              'timingConstraint' => 'none',
8199 
              'type' => 'UFix_32_0',
8200 
            },
8201 
            'direction' => 'out',
8202 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8203 
            'width' => 32,
8204 
          },
8205 
          'reg09_rv' => {
8206 
            'attributes' => {
8207 
              'bin_pt' => 0,
8208 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
8209 
              'is_floating_block' => 1,
8210 
              'is_gateway_port' => 1,
8211 
              'must_be_hdl_vector' => 1,
8212 
              'period' => 1,
8213 
              'port_id' => 0,
8214 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
8215 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
8216 
              'timingConstraint' => 'none',
8217 
              'type' => 'UFix_1_0',
8218 
            },
8219 
            'direction' => 'out',
8220 
            'hdlType' => 'std_logic',
8221 
            'width' => 1,
8222 
          },
8223 
          'reg09_td' => {
8224 
            'attributes' => {
8225 
              'bin_pt' => 0,
8226 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
8227 
              'is_floating_block' => 1,
8228 
              'is_gateway_port' => 1,
8229 
              'must_be_hdl_vector' => 1,
8230 
              'period' => 1,
8231 
              'port_id' => 0,
8232 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
8233 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
8234 
              'timingConstraint' => 'none',
8235 
              'type' => 'UFix_32_0',
8236 
            },
8237 
            'direction' => 'in',
8238 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8239 
            'width' => 32,
8240 
          },
8241 
          'reg09_tv' => {
8242 
            'attributes' => {
8243 
              'bin_pt' => 0,
8244 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
8245 
              'is_floating_block' => 1,
8246 
              'is_gateway_port' => 1,
8247 
              'must_be_hdl_vector' => 1,
8248 
              'period' => 1,
8249 
              'port_id' => 0,
8250 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
8251 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
8252 
              'timingConstraint' => 'none',
8253 
              'type' => 'Bool',
8254 
            },
8255 
            'direction' => 'in',
8256 
            'hdlType' => 'std_logic',
8257 
            'width' => 1,
8258 
          },
8259 
          'reg10_rd' => {
8260 
            'attributes' => {
8261 
              'bin_pt' => 0,
8262 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
8263 
              'is_floating_block' => 1,
8264 
              'is_gateway_port' => 1,
8265 
              'must_be_hdl_vector' => 1,
8266 
              'period' => 1,
8267 
              'port_id' => 0,
8268 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
8269 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
8270 
              'timingConstraint' => 'none',
8271 
              'type' => 'UFix_32_0',
8272 
            },
8273 
            'direction' => 'out',
8274 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8275 
            'width' => 32,
8276 
          },
8277 
          'reg10_rv' => {
8278 
            'attributes' => {
8279 
              'bin_pt' => 0,
8280 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
8281 
              'is_floating_block' => 1,
8282 
              'is_gateway_port' => 1,
8283 
              'must_be_hdl_vector' => 1,
8284 
              'period' => 1,
8285 
              'port_id' => 0,
8286 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
8287 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
8288 
              'timingConstraint' => 'none',
8289 
              'type' => 'UFix_1_0',
8290 
            },
8291 
            'direction' => 'out',
8292 
            'hdlType' => 'std_logic',
8293 
            'width' => 1,
8294 
          },
8295 
          'reg10_td' => {
8296 
            'attributes' => {
8297 
              'bin_pt' => 0,
8298 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
8299 
              'is_floating_block' => 1,
8300 
              'is_gateway_port' => 1,
8301 
              'must_be_hdl_vector' => 1,
8302 
              'period' => 1,
8303 
              'port_id' => 0,
8304 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
8305 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
8306 
              'timingConstraint' => 'none',
8307 
              'type' => 'UFix_32_0',
8308 
            },
8309 
            'direction' => 'in',
8310 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8311 
            'width' => 32,
8312 
          },
8313 
          'reg10_tv' => {
8314 
            'attributes' => {
8315 
              'bin_pt' => 0,
8316 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
8317 
              'is_floating_block' => 1,
8318 
              'is_gateway_port' => 1,
8319 
              'must_be_hdl_vector' => 1,
8320 
              'period' => 1,
8321 
              'port_id' => 0,
8322 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
8323 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
8324 
              'timingConstraint' => 'none',
8325 
              'type' => 'Bool',
8326 
            },
8327 
            'direction' => 'in',
8328 
            'hdlType' => 'std_logic',
8329 
            'width' => 1,
8330 
          },
8331 
          'reg11_rd' => {
8332 
            'attributes' => {
8333 
              'bin_pt' => 0,
8334 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
8335 
              'is_floating_block' => 1,
8336 
              'is_gateway_port' => 1,
8337 
              'must_be_hdl_vector' => 1,
8338 
              'period' => 1,
8339 
              'port_id' => 0,
8340 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
8341 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
8342 
              'timingConstraint' => 'none',
8343 
              'type' => 'UFix_32_0',
8344 
            },
8345 
            'direction' => 'out',
8346 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8347 
            'width' => 32,
8348 
          },
8349 
          'reg11_rv' => {
8350 
            'attributes' => {
8351 
              'bin_pt' => 0,
8352 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
8353 
              'is_floating_block' => 1,
8354 
              'is_gateway_port' => 1,
8355 
              'must_be_hdl_vector' => 1,
8356 
              'period' => 1,
8357 
              'port_id' => 0,
8358 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
8359 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
8360 
              'timingConstraint' => 'none',
8361 
              'type' => 'UFix_1_0',
8362 
            },
8363 
            'direction' => 'out',
8364 
            'hdlType' => 'std_logic',
8365 
            'width' => 1,
8366 
          },
8367 
          'reg11_td' => {
8368 
            'attributes' => {
8369 
              'bin_pt' => 0,
8370 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
8371 
              'is_floating_block' => 1,
8372 
              'is_gateway_port' => 1,
8373 
              'must_be_hdl_vector' => 1,
8374 
              'period' => 1,
8375 
              'port_id' => 0,
8376 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
8377 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
8378 
              'timingConstraint' => 'none',
8379 
              'type' => 'UFix_32_0',
8380 
            },
8381 
            'direction' => 'in',
8382 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8383 
            'width' => 32,
8384 
          },
8385 
          'reg11_tv' => {
8386 
            'attributes' => {
8387 
              'bin_pt' => 0,
8388 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
8389 
              'is_floating_block' => 1,
8390 
              'is_gateway_port' => 1,
8391 
              'must_be_hdl_vector' => 1,
8392 
              'period' => 1,
8393 
              'port_id' => 0,
8394 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
8395 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
8396 
              'timingConstraint' => 'none',
8397 
              'type' => 'Bool',
8398 
            },
8399 
            'direction' => 'in',
8400 
            'hdlType' => 'std_logic',
8401 
            'width' => 1,
8402 
          },
8403 
          'reg12_rd' => {
8404 
            'attributes' => {
8405 
              'bin_pt' => 0,
8406 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
8407 
              'is_floating_block' => 1,
8408 
              'is_gateway_port' => 1,
8409 
              'must_be_hdl_vector' => 1,
8410 
              'period' => 1,
8411 
              'port_id' => 0,
8412 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
8413 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
8414 
              'timingConstraint' => 'none',
8415 
              'type' => 'UFix_32_0',
8416 
            },
8417 
            'direction' => 'out',
8418 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8419 
            'width' => 32,
8420 
          },
8421 
          'reg12_rv' => {
8422 
            'attributes' => {
8423 
              'bin_pt' => 0,
8424 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
8425 
              'is_floating_block' => 1,
8426 
              'is_gateway_port' => 1,
8427 
              'must_be_hdl_vector' => 1,
8428 
              'period' => 1,
8429 
              'port_id' => 0,
8430 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
8431 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
8432 
              'timingConstraint' => 'none',
8433 
              'type' => 'UFix_1_0',
8434 
            },
8435 
            'direction' => 'out',
8436 
            'hdlType' => 'std_logic',
8437 
            'width' => 1,
8438 
          },
8439 
          'reg12_td' => {
8440 
            'attributes' => {
8441 
              'bin_pt' => 0,
8442 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
8443 
              'is_floating_block' => 1,
8444 
              'is_gateway_port' => 1,
8445 
              'must_be_hdl_vector' => 1,
8446 
              'period' => 1,
8447 
              'port_id' => 0,
8448 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
8449 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
8450 
              'timingConstraint' => 'none',
8451 
              'type' => 'UFix_32_0',
8452 
            },
8453 
            'direction' => 'in',
8454 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8455 
            'width' => 32,
8456 
          },
8457 
          'reg12_tv' => {
8458 
            'attributes' => {
8459 
              'bin_pt' => 0,
8460 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
8461 
              'is_floating_block' => 1,
8462 
              'is_gateway_port' => 1,
8463 
              'must_be_hdl_vector' => 1,
8464 
              'period' => 1,
8465 
              'port_id' => 0,
8466 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
8467 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
8468 
              'timingConstraint' => 'none',
8469 
              'type' => 'Bool',
8470 
            },
8471 
            'direction' => 'in',
8472 
            'hdlType' => 'std_logic',
8473 
            'width' => 1,
8474 
          },
8475 
          'reg13_rd' => {
8476 
            'attributes' => {
8477 
              'bin_pt' => 0,
8478 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
8479 
              'is_floating_block' => 1,
8480 
              'is_gateway_port' => 1,
8481 
              'must_be_hdl_vector' => 1,
8482 
              'period' => 1,
8483 
              'port_id' => 0,
8484 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
8485 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
8486 
              'timingConstraint' => 'none',
8487 
              'type' => 'UFix_32_0',
8488 
            },
8489 
            'direction' => 'out',
8490 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8491 
            'width' => 32,
8492 
          },
8493 
          'reg13_rv' => {
8494 
            'attributes' => {
8495 
              'bin_pt' => 0,
8496 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
8497 
              'is_floating_block' => 1,
8498 
              'is_gateway_port' => 1,
8499 
              'must_be_hdl_vector' => 1,
8500 
              'period' => 1,
8501 
              'port_id' => 0,
8502 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
8503 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
8504 
              'timingConstraint' => 'none',
8505 
              'type' => 'UFix_1_0',
8506 
            },
8507 
            'direction' => 'out',
8508 
            'hdlType' => 'std_logic',
8509 
            'width' => 1,
8510 
          },
8511 
          'reg13_td' => {
8512 
            'attributes' => {
8513 
              'bin_pt' => 0,
8514 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
8515 
              'is_floating_block' => 1,
8516 
              'is_gateway_port' => 1,
8517 
              'must_be_hdl_vector' => 1,
8518 
              'period' => 1,
8519 
              'port_id' => 0,
8520 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
8521 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
8522 
              'timingConstraint' => 'none',
8523 
              'type' => 'UFix_32_0',
8524 
            },
8525 
            'direction' => 'in',
8526 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8527 
            'width' => 32,
8528 
          },
8529 
          'reg13_tv' => {
8530 
            'attributes' => {
8531 
              'bin_pt' => 0,
8532 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
8533 
              'is_floating_block' => 1,
8534 
              'is_gateway_port' => 1,
8535 
              'must_be_hdl_vector' => 1,
8536 
              'period' => 1,
8537 
              'port_id' => 0,
8538 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
8539 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
8540 
              'timingConstraint' => 'none',
8541 
              'type' => 'Bool',
8542 
            },
8543 
            'direction' => 'in',
8544 
            'hdlType' => 'std_logic',
8545 
            'width' => 1,
8546 
          },
8547 
          'reg14_rd' => {
8548 
            'attributes' => {
8549 
              'bin_pt' => 0,
8550 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
8551 
              'is_floating_block' => 1,
8552 
              'is_gateway_port' => 1,
8553 
              'must_be_hdl_vector' => 1,
8554 
              'period' => 1,
8555 
              'port_id' => 0,
8556 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
8557 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
8558 
              'timingConstraint' => 'none',
8559 
              'type' => 'UFix_32_0',
8560 
            },
8561 
            'direction' => 'out',
8562 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8563 
            'width' => 32,
8564 
          },
8565 
          'reg14_rv' => {
8566 
            'attributes' => {
8567 
              'bin_pt' => 0,
8568 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
8569 
              'is_floating_block' => 1,
8570 
              'is_gateway_port' => 1,
8571 
              'must_be_hdl_vector' => 1,
8572 
              'period' => 1,
8573 
              'port_id' => 0,
8574 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
8575 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
8576 
              'timingConstraint' => 'none',
8577 
              'type' => 'UFix_1_0',
8578 
            },
8579 
            'direction' => 'out',
8580 
            'hdlType' => 'std_logic',
8581 
            'width' => 1,
8582 
          },
8583 
          'reg14_td' => {
8584 
            'attributes' => {
8585 
              'bin_pt' => 0,
8586 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
8587 
              'is_floating_block' => 1,
8588 
              'is_gateway_port' => 1,
8589 
              'must_be_hdl_vector' => 1,
8590 
              'period' => 1,
8591 
              'port_id' => 0,
8592 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
8593 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
8594 
              'timingConstraint' => 'none',
8595 
              'type' => 'UFix_32_0',
8596 
            },
8597 
            'direction' => 'in',
8598 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8599 
            'width' => 32,
8600 
          },
8601 
          'reg14_tv' => {
8602 
            'attributes' => {
8603 
              'bin_pt' => 0,
8604 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
8605 
              'is_floating_block' => 1,
8606 
              'is_gateway_port' => 1,
8607 
              'must_be_hdl_vector' => 1,
8608 
              'period' => 1,
8609 
              'port_id' => 0,
8610 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
8611 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
8612 
              'timingConstraint' => 'none',
8613 
              'type' => 'Bool',
8614 
            },
8615 
            'direction' => 'in',
8616 
            'hdlType' => 'std_logic',
8617 
            'width' => 1,
8618 
          },
8619 
          'to_register10_ce' => {
8620 
            'attributes' => {
8621 
              'domain' => '',
8622 
              'group' => 1,
8623 
              'isCe' => 1,
8624 
              'is_floating_block' => 1,
8625 
              'period' => 1,
8626 
              'type' => 'logic',
8627 
            },
8628 
            'direction' => 'out',
8629 
            'hdlType' => 'std_logic',
8630 
            'width' => 1,
8631 
          },
8632 
          'to_register10_clk' => {
8633 
            'attributes' => {
8634 
              'domain' => '',
8635 
              'group' => 1,
8636 
              'isClk' => 1,
8637 
              'is_floating_block' => 1,
8638 
              'period' => 1,
8639 
              'type' => 'logic',
8640 
            },
8641 
            'direction' => 'out',
8642 
            'hdlType' => 'std_logic',
8643 
            'width' => 1,
8644 
          },
8645 
          'to_register10_clr' => {
8646 
            'attributes' => {
8647 
              'domain' => '',
8648 
              'group' => 1,
8649 
              'isClr' => 1,
8650 
              'is_floating_block' => 1,
8651 
              'period' => 1,
8652 
              'type' => 'logic',
8653 
              'valid_bit_used' => 0,
8654 
            },
8655 
            'direction' => 'out',
8656 
            'hdlType' => 'std_logic',
8657 
            'width' => 1,
8658 
          },
8659 
          'to_register10_data_in' => {
8660 
            'attributes' => {
8661 
              'bin_pt' => 0,
8662 
              'is_floating_block' => 1,
8663 
              'must_be_hdl_vector' => 1,
8664 
              'period' => 1,
8665 
              'port_id' => 0,
8666 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
8667 
              'type' => 'Bool',
8668 
            },
8669 
            'direction' => 'out',
8670 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8671 
            'width' => 1,
8672 
          },
8673 
          'to_register10_dout' => {
8674 
            'attributes' => {
8675 
              'bin_pt' => 0,
8676 
              'is_floating_block' => 1,
8677 
              'must_be_hdl_vector' => 1,
8678 
              'period' => 1,
8679 
              'port_id' => 0,
8680 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
8681 
              'type' => 'Bool',
8682 
            },
8683 
            'direction' => 'in',
8684 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8685 
            'width' => 1,
8686 
          },
8687 
          'to_register10_en' => {
8688 
            'attributes' => {
8689 
              'bin_pt' => 0,
8690 
              'is_floating_block' => 1,
8691 
              'must_be_hdl_vector' => 1,
8692 
              'period' => 1,
8693 
              'port_id' => 1,
8694 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
8695 
              'type' => 'Bool',
8696 
            },
8697 
            'direction' => 'out',
8698 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8699 
            'width' => 1,
8700 
          },
8701 
          'to_register11_ce' => {
8702 
            'attributes' => {
8703 
              'domain' => '',
8704 
              'group' => 1,
8705 
              'isCe' => 1,
8706 
              'is_floating_block' => 1,
8707 
              'period' => 1,
8708 
              'type' => 'logic',
8709 
            },
8710 
            'direction' => 'out',
8711 
            'hdlType' => 'std_logic',
8712 
            'width' => 1,
8713 
          },
8714 
          'to_register11_clk' => {
8715 
            'attributes' => {
8716 
              'domain' => '',
8717 
              'group' => 1,
8718 
              'isClk' => 1,
8719 
              'is_floating_block' => 1,
8720 
              'period' => 1,
8721 
              'type' => 'logic',
8722 
            },
8723 
            'direction' => 'out',
8724 
            'hdlType' => 'std_logic',
8725 
            'width' => 1,
8726 
          },
8727 
          'to_register11_clr' => {
8728 
            'attributes' => {
8729 
              'domain' => '',
8730 
              'group' => 1,
8731 
              'isClr' => 1,
8732 
              'is_floating_block' => 1,
8733 
              'period' => 1,
8734 
              'type' => 'logic',
8735 
              'valid_bit_used' => 0,
8736 
            },
8737 
            'direction' => 'out',
8738 
            'hdlType' => 'std_logic',
8739 
            'width' => 1,
8740 
          },
8741 
          'to_register11_data_in' => {
8742 
            'attributes' => {
8743 
              'bin_pt' => 0,
8744 
              'is_floating_block' => 1,
8745 
              'must_be_hdl_vector' => 1,
8746 
              'period' => 1,
8747 
              'port_id' => 0,
8748 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
8749 
              'type' => 'UFix_32_0',
8750 
            },
8751 
            'direction' => 'out',
8752 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8753 
            'width' => 32,
8754 
          },
8755 
          'to_register11_dout' => {
8756 
            'attributes' => {
8757 
              'bin_pt' => 0,
8758 
              'is_floating_block' => 1,
8759 
              'must_be_hdl_vector' => 1,
8760 
              'period' => 1,
8761 
              'port_id' => 0,
8762 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
8763 
              'type' => 'UFix_32_0',
8764 
            },
8765 
            'direction' => 'in',
8766 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8767 
            'width' => 32,
8768 
          },
8769 
          'to_register11_en' => {
8770 
            'attributes' => {
8771 
              'bin_pt' => 0,
8772 
              'is_floating_block' => 1,
8773 
              'must_be_hdl_vector' => 1,
8774 
              'period' => 1,
8775 
              'port_id' => 1,
8776 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
8777 
              'type' => 'Bool',
8778 
            },
8779 
            'direction' => 'out',
8780 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8781 
            'width' => 1,
8782 
          },
8783 
          'to_register12_ce' => {
8784 
            'attributes' => {
8785 
              'domain' => '',
8786 
              'group' => 1,
8787 
              'isCe' => 1,
8788 
              'is_floating_block' => 1,
8789 
              'period' => 1,
8790 
              'type' => 'logic',
8791 
            },
8792 
            'direction' => 'out',
8793 
            'hdlType' => 'std_logic',
8794 
            'width' => 1,
8795 
          },
8796 
          'to_register12_clk' => {
8797 
            'attributes' => {
8798 
              'domain' => '',
8799 
              'group' => 1,
8800 
              'isClk' => 1,
8801 
              'is_floating_block' => 1,
8802 
              'period' => 1,
8803 
              'type' => 'logic',
8804 
            },
8805 
            'direction' => 'out',
8806 
            'hdlType' => 'std_logic',
8807 
            'width' => 1,
8808 
          },
8809 
          'to_register12_clr' => {
8810 
            'attributes' => {
8811 
              'domain' => '',
8812 
              'group' => 1,
8813 
              'isClr' => 1,
8814 
              'is_floating_block' => 1,
8815 
              'period' => 1,
8816 
              'type' => 'logic',
8817 
              'valid_bit_used' => 0,
8818 
            },
8819 
            'direction' => 'out',
8820 
            'hdlType' => 'std_logic',
8821 
            'width' => 1,
8822 
          },
8823 
          'to_register12_data_in' => {
8824 
            'attributes' => {
8825 
              'bin_pt' => 0,
8826 
              'is_floating_block' => 1,
8827 
              'must_be_hdl_vector' => 1,
8828 
              'period' => 1,
8829 
              'port_id' => 0,
8830 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
8831 
              'type' => 'Bool',
8832 
            },
8833 
            'direction' => 'out',
8834 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8835 
            'width' => 1,
8836 
          },
8837 
          'to_register12_dout' => {
8838 
            'attributes' => {
8839 
              'bin_pt' => 0,
8840 
              'is_floating_block' => 1,
8841 
              'must_be_hdl_vector' => 1,
8842 
              'period' => 1,
8843 
              'port_id' => 0,
8844 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
8845 
              'type' => 'Bool',
8846 
            },
8847 
            'direction' => 'in',
8848 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8849 
            'width' => 1,
8850 
          },
8851 
          'to_register12_en' => {
8852 
            'attributes' => {
8853 
              'bin_pt' => 0,
8854 
              'is_floating_block' => 1,
8855 
              'must_be_hdl_vector' => 1,
8856 
              'period' => 1,
8857 
              'port_id' => 1,
8858 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
8859 
              'type' => 'Bool',
8860 
            },
8861 
            'direction' => 'out',
8862 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8863 
            'width' => 1,
8864 
          },
8865 
          'to_register13_ce' => {
8866 
            'attributes' => {
8867 
              'domain' => '',
8868 
              'group' => 1,
8869 
              'isCe' => 1,
8870 
              'is_floating_block' => 1,
8871 
              'period' => 1,
8872 
              'type' => 'logic',
8873 
            },
8874 
            'direction' => 'out',
8875 
            'hdlType' => 'std_logic',
8876 
            'width' => 1,
8877 
          },
8878 
          'to_register13_clk' => {
8879 
            'attributes' => {
8880 
              'domain' => '',
8881 
              'group' => 1,
8882 
              'isClk' => 1,
8883 
              'is_floating_block' => 1,
8884 
              'period' => 1,
8885 
              'type' => 'logic',
8886 
            },
8887 
            'direction' => 'out',
8888 
            'hdlType' => 'std_logic',
8889 
            'width' => 1,
8890 
          },
8891 
          'to_register13_clr' => {
8892 
            'attributes' => {
8893 
              'domain' => '',
8894 
              'group' => 1,
8895 
              'isClr' => 1,
8896 
              'is_floating_block' => 1,
8897 
              'period' => 1,
8898 
              'type' => 'logic',
8899 
              'valid_bit_used' => 0,
8900 
            },
8901 
            'direction' => 'out',
8902 
            'hdlType' => 'std_logic',
8903 
            'width' => 1,
8904 
          },
8905 
          'to_register13_data_in' => {
8906 
            'attributes' => {
8907 
              'bin_pt' => 0,
8908 
              'is_floating_block' => 1,
8909 
              'must_be_hdl_vector' => 1,
8910 
              'period' => 1,
8911 
              'port_id' => 0,
8912 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
8913 
              'type' => 'UFix_32_0',
8914 
            },
8915 
            'direction' => 'out',
8916 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8917 
            'width' => 32,
8918 
          },
8919 
          'to_register13_dout' => {
8920 
            'attributes' => {
8921 
              'bin_pt' => 0,
8922 
              'is_floating_block' => 1,
8923 
              'must_be_hdl_vector' => 1,
8924 
              'period' => 1,
8925 
              'port_id' => 0,
8926 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
8927 
              'type' => 'UFix_32_0',
8928 
            },
8929 
            'direction' => 'in',
8930 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8931 
            'width' => 32,
8932 
          },
8933 
          'to_register13_en' => {
8934 
            'attributes' => {
8935 
              'bin_pt' => 0,
8936 
              'is_floating_block' => 1,
8937 
              'must_be_hdl_vector' => 1,
8938 
              'period' => 1,
8939 
              'port_id' => 1,
8940 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
8941 
              'type' => 'Bool',
8942 
            },
8943 
            'direction' => 'out',
8944 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8945 
            'width' => 1,
8946 
          },
8947 
          'to_register14_ce' => {
8948 
            'attributes' => {
8949 
              'domain' => '',
8950 
              'group' => 1,
8951 
              'isCe' => 1,
8952 
              'is_floating_block' => 1,
8953 
              'period' => 1,
8954 
              'type' => 'logic',
8955 
            },
8956 
            'direction' => 'out',
8957 
            'hdlType' => 'std_logic',
8958 
            'width' => 1,
8959 
          },
8960 
          'to_register14_clk' => {
8961 
            'attributes' => {
8962 
              'domain' => '',
8963 
              'group' => 1,
8964 
              'isClk' => 1,
8965 
              'is_floating_block' => 1,
8966 
              'period' => 1,
8967 
              'type' => 'logic',
8968 
            },
8969 
            'direction' => 'out',
8970 
            'hdlType' => 'std_logic',
8971 
            'width' => 1,
8972 
          },
8973 
          'to_register14_clr' => {
8974 
            'attributes' => {
8975 
              'domain' => '',
8976 
              'group' => 1,
8977 
              'isClr' => 1,
8978 
              'is_floating_block' => 1,
8979 
              'period' => 1,
8980 
              'type' => 'logic',
8981 
              'valid_bit_used' => 0,
8982 
            },
8983 
            'direction' => 'out',
8984 
            'hdlType' => 'std_logic',
8985 
            'width' => 1,
8986 
          },
8987 
          'to_register14_data_in' => {
8988 
            'attributes' => {
8989 
              'bin_pt' => 0,
8990 
              'is_floating_block' => 1,
8991 
              'must_be_hdl_vector' => 1,
8992 
              'period' => 1,
8993 
              'port_id' => 0,
8994 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
8995 
              'type' => 'Bool',
8996 
            },
8997 
            'direction' => 'out',
8998 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8999 
            'width' => 1,
9000 
          },
9001 
          'to_register14_dout' => {
9002 
            'attributes' => {
9003 
              'bin_pt' => 0,
9004 
              'is_floating_block' => 1,
9005 
              'must_be_hdl_vector' => 1,
9006 
              'period' => 1,
9007 
              'port_id' => 0,
9008 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
9009 
              'type' => 'Bool',
9010 
            },
9011 
            'direction' => 'in',
9012 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9013 
            'width' => 1,
9014 
          },
9015 
          'to_register14_en' => {
9016 
            'attributes' => {
9017 
              'bin_pt' => 0,
9018 
              'is_floating_block' => 1,
9019 
              'must_be_hdl_vector' => 1,
9020 
              'period' => 1,
9021 
              'port_id' => 1,
9022 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
9023 
              'type' => 'Bool',
9024 
            },
9025 
            'direction' => 'out',
9026 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9027 
            'width' => 1,
9028 
          },
9029 
          'to_register15_ce' => {
9030 
            'attributes' => {
9031 
              'domain' => '',
9032 
              'group' => 1,
9033 
              'isCe' => 1,
9034 
              'is_floating_block' => 1,
9035 
              'period' => 1,
9036 
              'type' => 'logic',
9037 
            },
9038 
            'direction' => 'out',
9039 
            'hdlType' => 'std_logic',
9040 
            'width' => 1,
9041 
          },
9042 
          'to_register15_clk' => {
9043 
            'attributes' => {
9044 
              'domain' => '',
9045 
              'group' => 1,
9046 
              'isClk' => 1,
9047 
              'is_floating_block' => 1,
9048 
              'period' => 1,
9049 
              'type' => 'logic',
9050 
            },
9051 
            'direction' => 'out',
9052 
            'hdlType' => 'std_logic',
9053 
            'width' => 1,
9054 
          },
9055 
          'to_register15_clr' => {
9056 
            'attributes' => {
9057 
              'domain' => '',
9058 
              'group' => 1,
9059 
              'isClr' => 1,
9060 
              'is_floating_block' => 1,
9061 
              'period' => 1,
9062 
              'type' => 'logic',
9063 
              'valid_bit_used' => 0,
9064 
            },
9065 
            'direction' => 'out',
9066 
            'hdlType' => 'std_logic',
9067 
            'width' => 1,
9068 
          },
9069 
          'to_register15_data_in' => {
9070 
            'attributes' => {
9071 
              'bin_pt' => 0,
9072 
              'is_floating_block' => 1,
9073 
              'must_be_hdl_vector' => 1,
9074 
              'period' => 1,
9075 
              'port_id' => 0,
9076 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
9077 
              'type' => 'UFix_32_0',
9078 
            },
9079 
            'direction' => 'out',
9080 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9081 
            'width' => 32,
9082 
          },
9083 
          'to_register15_dout' => {
9084 
            'attributes' => {
9085 
              'bin_pt' => 0,
9086 
              'is_floating_block' => 1,
9087 
              'must_be_hdl_vector' => 1,
9088 
              'period' => 1,
9089 
              'port_id' => 0,
9090 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
9091 
              'type' => 'UFix_32_0',
9092 
            },
9093 
            'direction' => 'in',
9094 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9095 
            'width' => 32,
9096 
          },
9097 
          'to_register15_en' => {
9098 
            'attributes' => {
9099 
              'bin_pt' => 0,
9100 
              'is_floating_block' => 1,
9101 
              'must_be_hdl_vector' => 1,
9102 
              'period' => 1,
9103 
              'port_id' => 1,
9104 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
9105 
              'type' => 'Bool',
9106 
            },
9107 
            'direction' => 'out',
9108 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9109 
            'width' => 1,
9110 
          },
9111 
          'to_register16_ce' => {
9112 
            'attributes' => {
9113 
              'domain' => '',
9114 
              'group' => 1,
9115 
              'isCe' => 1,
9116 
              'is_floating_block' => 1,
9117 
              'period' => 1,
9118 
              'type' => 'logic',
9119 
            },
9120 
            'direction' => 'out',
9121 
            'hdlType' => 'std_logic',
9122 
            'width' => 1,
9123 
          },
9124 
          'to_register16_clk' => {
9125 
            'attributes' => {
9126 
              'domain' => '',
9127 
              'group' => 1,
9128 
              'isClk' => 1,
9129 
              'is_floating_block' => 1,
9130 
              'period' => 1,
9131 
              'type' => 'logic',
9132 
            },
9133 
            'direction' => 'out',
9134 
            'hdlType' => 'std_logic',
9135 
            'width' => 1,
9136 
          },
9137 
          'to_register16_clr' => {
9138 
            'attributes' => {
9139 
              'domain' => '',
9140 
              'group' => 1,
9141 
              'isClr' => 1,
9142 
              'is_floating_block' => 1,
9143 
              'period' => 1,
9144 
              'type' => 'logic',
9145 
              'valid_bit_used' => 0,
9146 
            },
9147 
            'direction' => 'out',
9148 
            'hdlType' => 'std_logic',
9149 
            'width' => 1,
9150 
          },
9151 
          'to_register16_data_in' => {
9152 
            'attributes' => {
9153 
              'bin_pt' => 0,
9154 
              'is_floating_block' => 1,
9155 
              'must_be_hdl_vector' => 1,
9156 
              'period' => 1,
9157 
              'port_id' => 0,
9158 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
9159 
              'type' => 'Bool',
9160 
            },
9161 
            'direction' => 'out',
9162 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9163 
            'width' => 1,
9164 
          },
9165 
          'to_register16_dout' => {
9166 
            'attributes' => {
9167 
              'bin_pt' => 0,
9168 
              'is_floating_block' => 1,
9169 
              'must_be_hdl_vector' => 1,
9170 
              'period' => 1,
9171 
              'port_id' => 0,
9172 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
9173 
              'type' => 'Bool',
9174 
            },
9175 
            'direction' => 'in',
9176 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9177 
            'width' => 1,
9178 
          },
9179 
          'to_register16_en' => {
9180 
            'attributes' => {
9181 
              'bin_pt' => 0,
9182 
              'is_floating_block' => 1,
9183 
              'must_be_hdl_vector' => 1,
9184 
              'period' => 1,
9185 
              'port_id' => 1,
9186 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
9187 
              'type' => 'Bool',
9188 
            },
9189 
            'direction' => 'out',
9190 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9191 
            'width' => 1,
9192 
          },
9193 
          'to_register17_ce' => {
9194 
            'attributes' => {
9195 
              'domain' => '',
9196 
              'group' => 1,
9197 
              'isCe' => 1,
9198 
              'is_floating_block' => 1,
9199 
              'period' => 1,
9200 
              'type' => 'logic',
9201 
            },
9202 
            'direction' => 'out',
9203 
            'hdlType' => 'std_logic',
9204 
            'width' => 1,
9205 
          },
9206 
          'to_register17_clk' => {
9207 
            'attributes' => {
9208 
              'domain' => '',
9209 
              'group' => 1,
9210 
              'isClk' => 1,
9211 
              'is_floating_block' => 1,
9212 
              'period' => 1,
9213 
              'type' => 'logic',
9214 
            },
9215 
            'direction' => 'out',
9216 
            'hdlType' => 'std_logic',
9217 
            'width' => 1,
9218 
          },
9219 
          'to_register17_clr' => {
9220 
            'attributes' => {
9221 
              'domain' => '',
9222 
              'group' => 1,
9223 
              'isClr' => 1,
9224 
              'is_floating_block' => 1,
9225 
              'period' => 1,
9226 
              'type' => 'logic',
9227 
              'valid_bit_used' => 0,
9228 
            },
9229 
            'direction' => 'out',
9230 
            'hdlType' => 'std_logic',
9231 
            'width' => 1,
9232 
          },
9233 
          'to_register17_data_in' => {
9234 
            'attributes' => {
9235 
              'bin_pt' => 0,
9236 
              'is_floating_block' => 1,
9237 
              'must_be_hdl_vector' => 1,
9238 
              'period' => 1,
9239 
              'port_id' => 0,
9240 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
9241 
              'type' => 'UFix_32_0',
9242 
            },
9243 
            'direction' => 'out',
9244 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9245 
            'width' => 32,
9246 
          },
9247 
          'to_register17_dout' => {
9248 
            'attributes' => {
9249 
              'bin_pt' => 0,
9250 
              'is_floating_block' => 1,
9251 
              'must_be_hdl_vector' => 1,
9252 
              'period' => 1,
9253 
              'port_id' => 0,
9254 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
9255 
              'type' => 'UFix_32_0',
9256 
            },
9257 
            'direction' => 'in',
9258 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9259 
            'width' => 32,
9260 
          },
9261 
          'to_register17_en' => {
9262 
            'attributes' => {
9263 
              'bin_pt' => 0,
9264 
              'is_floating_block' => 1,
9265 
              'must_be_hdl_vector' => 1,
9266 
              'period' => 1,
9267 
              'port_id' => 1,
9268 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
9269 
              'type' => 'Bool',
9270 
            },
9271 
            'direction' => 'out',
9272 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9273 
            'width' => 1,
9274 
          },
9275 
          'to_register18_ce' => {
9276 
            'attributes' => {
9277 
              'domain' => '',
9278 
              'group' => 1,
9279 
              'isCe' => 1,
9280 
              'is_floating_block' => 1,
9281 
              'period' => 1,
9282 
              'type' => 'logic',
9283 
            },
9284 
            'direction' => 'out',
9285 
            'hdlType' => 'std_logic',
9286 
            'width' => 1,
9287 
          },
9288 
          'to_register18_clk' => {
9289 
            'attributes' => {
9290 
              'domain' => '',
9291 
              'group' => 1,
9292 
              'isClk' => 1,
9293 
              'is_floating_block' => 1,
9294 
              'period' => 1,
9295 
              'type' => 'logic',
9296 
            },
9297 
            'direction' => 'out',
9298 
            'hdlType' => 'std_logic',
9299 
            'width' => 1,
9300 
          },
9301 
          'to_register18_clr' => {
9302 
            'attributes' => {
9303 
              'domain' => '',
9304 
              'group' => 1,
9305 
              'isClr' => 1,
9306 
              'is_floating_block' => 1,
9307 
              'period' => 1,
9308 
              'type' => 'logic',
9309 
              'valid_bit_used' => 0,
9310 
            },
9311 
            'direction' => 'out',
9312 
            'hdlType' => 'std_logic',
9313 
            'width' => 1,
9314 
          },
9315 
          'to_register18_data_in' => {
9316 
            'attributes' => {
9317 
              'bin_pt' => 0,
9318 
              'is_floating_block' => 1,
9319 
              'must_be_hdl_vector' => 1,
9320 
              'period' => 1,
9321 
              'port_id' => 0,
9322 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
9323 
              'type' => 'UFix_1_0',
9324 
            },
9325 
            'direction' => 'out',
9326 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9327 
            'width' => 1,
9328 
          },
9329 
          'to_register18_dout' => {
9330 
            'attributes' => {
9331 
              'bin_pt' => 0,
9332 
              'is_floating_block' => 1,
9333 
              'must_be_hdl_vector' => 1,
9334 
              'period' => 1,
9335 
              'port_id' => 0,
9336 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
9337 
              'type' => 'UFix_1_0',
9338 
            },
9339 
            'direction' => 'in',
9340 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9341 
            'width' => 1,
9342 
          },
9343 
          'to_register18_en' => {
9344 
            'attributes' => {
9345 
              'bin_pt' => 0,
9346 
              'is_floating_block' => 1,
9347 
              'must_be_hdl_vector' => 1,
9348 
              'period' => 1,
9349 
              'port_id' => 1,
9350 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
9351 
              'type' => 'Bool',
9352 
            },
9353 
            'direction' => 'out',
9354 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9355 
            'width' => 1,
9356 
          },
9357 
          'to_register19_ce' => {
9358 
            'attributes' => {
9359 
              'domain' => '',
9360 
              'group' => 1,
9361 
              'isCe' => 1,
9362 
              'is_floating_block' => 1,
9363 
              'period' => 1,
9364 
              'type' => 'logic',
9365 
            },
9366 
            'direction' => 'out',
9367 
            'hdlType' => 'std_logic',
9368 
            'width' => 1,
9369 
          },
9370 
          'to_register19_clk' => {
9371 
            'attributes' => {
9372 
              'domain' => '',
9373 
              'group' => 1,
9374 
              'isClk' => 1,
9375 
              'is_floating_block' => 1,
9376 
              'period' => 1,
9377 
              'type' => 'logic',
9378 
            },
9379 
            'direction' => 'out',
9380 
            'hdlType' => 'std_logic',
9381 
            'width' => 1,
9382 
          },
9383 
          'to_register19_clr' => {
9384 
            'attributes' => {
9385 
              'domain' => '',
9386 
              'group' => 1,
9387 
              'isClr' => 1,
9388 
              'is_floating_block' => 1,
9389 
              'period' => 1,
9390 
              'type' => 'logic',
9391 
              'valid_bit_used' => 0,
9392 
            },
9393 
            'direction' => 'out',
9394 
            'hdlType' => 'std_logic',
9395 
            'width' => 1,
9396 
          },
9397 
          'to_register19_data_in' => {
9398 
            'attributes' => {
9399 
              'bin_pt' => 0,
9400 
              'is_floating_block' => 1,
9401 
              'must_be_hdl_vector' => 1,
9402 
              'period' => 1,
9403 
              'port_id' => 0,
9404 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
9405 
              'type' => 'UFix_1_0',
9406 
            },
9407 
            'direction' => 'out',
9408 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9409 
            'width' => 1,
9410 
          },
9411 
          'to_register19_dout' => {
9412 
            'attributes' => {
9413 
              'bin_pt' => 0,
9414 
              'is_floating_block' => 1,
9415 
              'must_be_hdl_vector' => 1,
9416 
              'period' => 1,
9417 
              'port_id' => 0,
9418 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
9419 
              'type' => 'UFix_1_0',
9420 
            },
9421 
            'direction' => 'in',
9422 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9423 
            'width' => 1,
9424 
          },
9425 
          'to_register19_en' => {
9426 
            'attributes' => {
9427 
              'bin_pt' => 0,
9428 
              'is_floating_block' => 1,
9429 
              'must_be_hdl_vector' => 1,
9430 
              'period' => 1,
9431 
              'port_id' => 1,
9432 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
9433 
              'type' => 'Bool',
9434 
            },
9435 
            'direction' => 'out',
9436 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9437 
            'width' => 1,
9438 
          },
9439 
          'to_register1_ce' => {
9440 
            'attributes' => {
9441 
              'domain' => '',
9442 
              'group' => 1,
9443 
              'isCe' => 1,
9444 
              'is_floating_block' => 1,
9445 
              'period' => 1,
9446 
              'type' => 'logic',
9447 
            },
9448 
            'direction' => 'out',
9449 
            'hdlType' => 'std_logic',
9450 
            'width' => 1,
9451 
          },
9452 
          'to_register1_clk' => {
9453 
            'attributes' => {
9454 
              'domain' => '',
9455 
              'group' => 1,
9456 
              'isClk' => 1,
9457 
              'is_floating_block' => 1,
9458 
              'period' => 1,
9459 
              'type' => 'logic',
9460 
            },
9461 
            'direction' => 'out',
9462 
            'hdlType' => 'std_logic',
9463 
            'width' => 1,
9464 
          },
9465 
          'to_register1_clr' => {
9466 
            'attributes' => {
9467 
              'domain' => '',
9468 
              'group' => 1,
9469 
              'isClr' => 1,
9470 
              'is_floating_block' => 1,
9471 
              'period' => 1,
9472 
              'type' => 'logic',
9473 
              'valid_bit_used' => 0,
9474 
            },
9475 
            'direction' => 'out',
9476 
            'hdlType' => 'std_logic',
9477 
            'width' => 1,
9478 
          },
9479 
          'to_register1_data_in' => {
9480 
            'attributes' => {
9481 
              'bin_pt' => 0,
9482 
              'is_floating_block' => 1,
9483 
              'must_be_hdl_vector' => 1,
9484 
              'period' => 1,
9485 
              'port_id' => 0,
9486 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
9487 
              'type' => 'UFix_32_0',
9488 
            },
9489 
            'direction' => 'out',
9490 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9491 
            'width' => 32,
9492 
          },
9493 
          'to_register1_dout' => {
9494 
            'attributes' => {
9495 
              'bin_pt' => 0,
9496 
              'is_floating_block' => 1,
9497 
              'must_be_hdl_vector' => 1,
9498 
              'period' => 1,
9499 
              'port_id' => 0,
9500 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
9501 
              'type' => 'UFix_32_0',
9502 
            },
9503 
            'direction' => 'in',
9504 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9505 
            'width' => 32,
9506 
          },
9507 
          'to_register1_en' => {
9508 
            'attributes' => {
9509 
              'bin_pt' => 0,
9510 
              'is_floating_block' => 1,
9511 
              'must_be_hdl_vector' => 1,
9512 
              'period' => 1,
9513 
              'port_id' => 1,
9514 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
9515 
              'type' => 'Bool',
9516 
            },
9517 
            'direction' => 'out',
9518 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9519 
            'width' => 1,
9520 
          },
9521 
          'to_register20_ce' => {
9522 
            'attributes' => {
9523 
              'domain' => '',
9524 
              'group' => 1,
9525 
              'isCe' => 1,
9526 
              'is_floating_block' => 1,
9527 
              'period' => 1,
9528 
              'type' => 'logic',
9529 
            },
9530 
            'direction' => 'out',
9531 
            'hdlType' => 'std_logic',
9532 
            'width' => 1,
9533 
          },
9534 
          'to_register20_clk' => {
9535 
            'attributes' => {
9536 
              'domain' => '',
9537 
              'group' => 1,
9538 
              'isClk' => 1,
9539 
              'is_floating_block' => 1,
9540 
              'period' => 1,
9541 
              'type' => 'logic',
9542 
            },
9543 
            'direction' => 'out',
9544 
            'hdlType' => 'std_logic',
9545 
            'width' => 1,
9546 
          },
9547 
          'to_register20_clr' => {
9548 
            'attributes' => {
9549 
              'domain' => '',
9550 
              'group' => 1,
9551 
              'isClr' => 1,
9552 
              'is_floating_block' => 1,
9553 
              'period' => 1,
9554 
              'type' => 'logic',
9555 
              'valid_bit_used' => 0,
9556 
            },
9557 
            'direction' => 'out',
9558 
            'hdlType' => 'std_logic',
9559 
            'width' => 1,
9560 
          },
9561 
          'to_register20_data_in' => {
9562 
            'attributes' => {
9563 
              'bin_pt' => 0,
9564 
              'is_floating_block' => 1,
9565 
              'must_be_hdl_vector' => 1,
9566 
              'period' => 1,
9567 
              'port_id' => 0,
9568 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
9569 
              'type' => 'UFix_32_0',
9570 
            },
9571 
            'direction' => 'out',
9572 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9573 
            'width' => 32,
9574 
          },
9575 
          'to_register20_dout' => {
9576 
            'attributes' => {
9577 
              'bin_pt' => 0,
9578 
              'is_floating_block' => 1,
9579 
              'must_be_hdl_vector' => 1,
9580 
              'period' => 1,
9581 
              'port_id' => 0,
9582 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
9583 
              'type' => 'UFix_32_0',
9584 
            },
9585 
            'direction' => 'in',
9586 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9587 
            'width' => 32,
9588 
          },
9589 
          'to_register20_en' => {
9590 
            'attributes' => {
9591 
              'bin_pt' => 0,
9592 
              'is_floating_block' => 1,
9593 
              'must_be_hdl_vector' => 1,
9594 
              'period' => 1,
9595 
              'port_id' => 1,
9596 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
9597 
              'type' => 'Bool',
9598 
            },
9599 
            'direction' => 'out',
9600 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9601 
            'width' => 1,
9602 
          },
9603 
          'to_register21_ce' => {
9604 
            'attributes' => {
9605 
              'domain' => '',
9606 
              'group' => 1,
9607 
              'isCe' => 1,
9608 
              'is_floating_block' => 1,
9609 
              'period' => 1,
9610 
              'type' => 'logic',
9611 
            },
9612 
            'direction' => 'out',
9613 
            'hdlType' => 'std_logic',
9614 
            'width' => 1,
9615 
          },
9616 
          'to_register21_clk' => {
9617 
            'attributes' => {
9618 
              'domain' => '',
9619 
              'group' => 1,
9620 
              'isClk' => 1,
9621 
              'is_floating_block' => 1,
9622 
              'period' => 1,
9623 
              'type' => 'logic',
9624 
            },
9625 
            'direction' => 'out',
9626 
            'hdlType' => 'std_logic',
9627 
            'width' => 1,
9628 
          },
9629 
          'to_register21_clr' => {
9630 
            'attributes' => {
9631 
              'domain' => '',
9632 
              'group' => 1,
9633 
              'isClr' => 1,
9634 
              'is_floating_block' => 1,
9635 
              'period' => 1,
9636 
              'type' => 'logic',
9637 
              'valid_bit_used' => 0,
9638 
            },
9639 
            'direction' => 'out',
9640 
            'hdlType' => 'std_logic',
9641 
            'width' => 1,
9642 
          },
9643 
          'to_register21_data_in' => {
9644 
            'attributes' => {
9645 
              'bin_pt' => 0,
9646 
              'is_floating_block' => 1,
9647 
              'must_be_hdl_vector' => 1,
9648 
              'period' => 1,
9649 
              'port_id' => 0,
9650 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
9651 
              'type' => 'Bool',
9652 
            },
9653 
            'direction' => 'out',
9654 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9655 
            'width' => 1,
9656 
          },
9657 
          'to_register21_dout' => {
9658 
            'attributes' => {
9659 
              'bin_pt' => 0,
9660 
              'is_floating_block' => 1,
9661 
              'must_be_hdl_vector' => 1,
9662 
              'period' => 1,
9663 
              'port_id' => 0,
9664 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
9665 
              'type' => 'Bool',
9666 
            },
9667 
            'direction' => 'in',
9668 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9669 
            'width' => 1,
9670 
          },
9671 
          'to_register21_en' => {
9672 
            'attributes' => {
9673 
              'bin_pt' => 0,
9674 
              'is_floating_block' => 1,
9675 
              'must_be_hdl_vector' => 1,
9676 
              'period' => 1,
9677 
              'port_id' => 1,
9678 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
9679 
              'type' => 'Bool',
9680 
            },
9681 
            'direction' => 'out',
9682 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9683 
            'width' => 1,
9684 
          },
9685 
          'to_register22_ce' => {
9686 
            'attributes' => {
9687 
              'domain' => '',
9688 
              'group' => 1,
9689 
              'isCe' => 1,
9690 
              'is_floating_block' => 1,
9691 
              'period' => 1,
9692 
              'type' => 'logic',
9693 
            },
9694 
            'direction' => 'out',
9695 
            'hdlType' => 'std_logic',
9696 
            'width' => 1,
9697 
          },
9698 
          'to_register22_clk' => {
9699 
            'attributes' => {
9700 
              'domain' => '',
9701 
              'group' => 1,
9702 
              'isClk' => 1,
9703 
              'is_floating_block' => 1,
9704 
              'period' => 1,
9705 
              'type' => 'logic',
9706 
            },
9707 
            'direction' => 'out',
9708 
            'hdlType' => 'std_logic',
9709 
            'width' => 1,
9710 
          },
9711 
          'to_register22_clr' => {
9712 
            'attributes' => {
9713 
              'domain' => '',
9714 
              'group' => 1,
9715 
              'isClr' => 1,
9716 
              'is_floating_block' => 1,
9717 
              'period' => 1,
9718 
              'type' => 'logic',
9719 
              'valid_bit_used' => 0,
9720 
            },
9721 
            'direction' => 'out',
9722 
            'hdlType' => 'std_logic',
9723 
            'width' => 1,
9724 
          },
9725 
          'to_register22_data_in' => {
9726 
            'attributes' => {
9727 
              'bin_pt' => 0,
9728 
              'is_floating_block' => 1,
9729 
              'must_be_hdl_vector' => 1,
9730 
              'period' => 1,
9731 
              'port_id' => 0,
9732 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
9733 
              'type' => 'UFix_32_0',
9734 
            },
9735 
            'direction' => 'out',
9736 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9737 
            'width' => 32,
9738 
          },
9739 
          'to_register22_dout' => {
9740 
            'attributes' => {
9741 
              'bin_pt' => 0,
9742 
              'is_floating_block' => 1,
9743 
              'must_be_hdl_vector' => 1,
9744 
              'period' => 1,
9745 
              'port_id' => 0,
9746 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
9747 
              'type' => 'UFix_32_0',
9748 
            },
9749 
            'direction' => 'in',
9750 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9751 
            'width' => 32,
9752 
          },
9753 
          'to_register22_en' => {
9754 
            'attributes' => {
9755 
              'bin_pt' => 0,
9756 
              'is_floating_block' => 1,
9757 
              'must_be_hdl_vector' => 1,
9758 
              'period' => 1,
9759 
              'port_id' => 1,
9760 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
9761 
              'type' => 'Bool',
9762 
            },
9763 
            'direction' => 'out',
9764 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9765 
            'width' => 1,
9766 
          },
9767 
          'to_register23_ce' => {
9768 
            'attributes' => {
9769 
              'domain' => '',
9770 
              'group' => 1,
9771 
              'isCe' => 1,
9772 
              'is_floating_block' => 1,
9773 
              'period' => 1,
9774 
              'type' => 'logic',
9775 
            },
9776 
            'direction' => 'out',
9777 
            'hdlType' => 'std_logic',
9778 
            'width' => 1,
9779 
          },
9780 
          'to_register23_clk' => {
9781 
            'attributes' => {
9782 
              'domain' => '',
9783 
              'group' => 1,
9784 
              'isClk' => 1,
9785 
              'is_floating_block' => 1,
9786 
              'period' => 1,
9787 
              'type' => 'logic',
9788 
            },
9789 
            'direction' => 'out',
9790 
            'hdlType' => 'std_logic',
9791 
            'width' => 1,
9792 
          },
9793 
          'to_register23_clr' => {
9794 
            'attributes' => {
9795 
              'domain' => '',
9796 
              'group' => 1,
9797 
              'isClr' => 1,
9798 
              'is_floating_block' => 1,
9799 
              'period' => 1,
9800 
              'type' => 'logic',
9801 
              'valid_bit_used' => 0,
9802 
            },
9803 
            'direction' => 'out',
9804 
            'hdlType' => 'std_logic',
9805 
            'width' => 1,
9806 
          },
9807 
          'to_register23_data_in' => {
9808 
            'attributes' => {
9809 
              'bin_pt' => 0,
9810 
              'is_floating_block' => 1,
9811 
              'must_be_hdl_vector' => 1,
9812 
              'period' => 1,
9813 
              'port_id' => 0,
9814 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
9815 
              'type' => 'Bool',
9816 
            },
9817 
            'direction' => 'out',
9818 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9819 
            'width' => 1,
9820 
          },
9821 
          'to_register23_dout' => {
9822 
            'attributes' => {
9823 
              'bin_pt' => 0,
9824 
              'is_floating_block' => 1,
9825 
              'must_be_hdl_vector' => 1,
9826 
              'period' => 1,
9827 
              'port_id' => 0,
9828 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
9829 
              'type' => 'Bool',
9830 
            },
9831 
            'direction' => 'in',
9832 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9833 
            'width' => 1,
9834 
          },
9835 
          'to_register23_en' => {
9836 
            'attributes' => {
9837 
              'bin_pt' => 0,
9838 
              'is_floating_block' => 1,
9839 
              'must_be_hdl_vector' => 1,
9840 
              'period' => 1,
9841 
              'port_id' => 1,
9842 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
9843 
              'type' => 'Bool',
9844 
            },
9845 
            'direction' => 'out',
9846 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9847 
            'width' => 1,
9848 
          },
9849 
          'to_register24_ce' => {
9850 
            'attributes' => {
9851 
              'domain' => '',
9852 
              'group' => 1,
9853 
              'isCe' => 1,
9854 
              'is_floating_block' => 1,
9855 
              'period' => 1,
9856 
              'type' => 'logic',
9857 
            },
9858 
            'direction' => 'out',
9859 
            'hdlType' => 'std_logic',
9860 
            'width' => 1,
9861 
          },
9862 
          'to_register24_clk' => {
9863 
            'attributes' => {
9864 
              'domain' => '',
9865 
              'group' => 1,
9866 
              'isClk' => 1,
9867 
              'is_floating_block' => 1,
9868 
              'period' => 1,
9869 
              'type' => 'logic',
9870 
            },
9871 
            'direction' => 'out',
9872 
            'hdlType' => 'std_logic',
9873 
            'width' => 1,
9874 
          },
9875 
          'to_register24_clr' => {
9876 
            'attributes' => {
9877 
              'domain' => '',
9878 
              'group' => 1,
9879 
              'isClr' => 1,
9880 
              'is_floating_block' => 1,
9881 
              'period' => 1,
9882 
              'type' => 'logic',
9883 
              'valid_bit_used' => 0,
9884 
            },
9885 
            'direction' => 'out',
9886 
            'hdlType' => 'std_logic',
9887 
            'width' => 1,
9888 
          },
9889 
          'to_register24_data_in' => {
9890 
            'attributes' => {
9891 
              'bin_pt' => 0,
9892 
              'is_floating_block' => 1,
9893 
              'must_be_hdl_vector' => 1,
9894 
              'period' => 1,
9895 
              'port_id' => 0,
9896 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
9897 
              'type' => 'UFix_32_0',
9898 
            },
9899 
            'direction' => 'out',
9900 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9901 
            'width' => 32,
9902 
          },
9903 
          'to_register24_dout' => {
9904 
            'attributes' => {
9905 
              'bin_pt' => 0,
9906 
              'is_floating_block' => 1,
9907 
              'must_be_hdl_vector' => 1,
9908 
              'period' => 1,
9909 
              'port_id' => 0,
9910 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
9911 
              'type' => 'UFix_32_0',
9912 
            },
9913 
            'direction' => 'in',
9914 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9915 
            'width' => 32,
9916 
          },
9917 
          'to_register24_en' => {
9918 
            'attributes' => {
9919 
              'bin_pt' => 0,
9920 
              'is_floating_block' => 1,
9921 
              'must_be_hdl_vector' => 1,
9922 
              'period' => 1,
9923 
              'port_id' => 1,
9924 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
9925 
              'type' => 'Bool',
9926 
            },
9927 
            'direction' => 'out',
9928 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9929 
            'width' => 1,
9930 
          },
9931 
          'to_register25_ce' => {
9932 
            'attributes' => {
9933 
              'domain' => '',
9934 
              'group' => 1,
9935 
              'isCe' => 1,
9936 
              'is_floating_block' => 1,
9937 
              'period' => 1,
9938 
              'type' => 'logic',
9939 
            },
9940 
            'direction' => 'out',
9941 
            'hdlType' => 'std_logic',
9942 
            'width' => 1,
9943 
          },
9944 
          'to_register25_clk' => {
9945 
            'attributes' => {
9946 
              'domain' => '',
9947 
              'group' => 1,
9948 
              'isClk' => 1,
9949 
              'is_floating_block' => 1,
9950 
              'period' => 1,
9951 
              'type' => 'logic',
9952 
            },
9953 
            'direction' => 'out',
9954 
            'hdlType' => 'std_logic',
9955 
            'width' => 1,
9956 
          },
9957 
          'to_register25_clr' => {
9958 
            'attributes' => {
9959 
              'domain' => '',
9960 
              'group' => 1,
9961 
              'isClr' => 1,
9962 
              'is_floating_block' => 1,
9963 
              'period' => 1,
9964 
              'type' => 'logic',
9965 
              'valid_bit_used' => 0,
9966 
            },
9967 
            'direction' => 'out',
9968 
            'hdlType' => 'std_logic',
9969 
            'width' => 1,
9970 
          },
9971 
          'to_register25_data_in' => {
9972 
            'attributes' => {
9973 
              'bin_pt' => 0,
9974 
              'is_floating_block' => 1,
9975 
              'must_be_hdl_vector' => 1,
9976 
              'period' => 1,
9977 
              'port_id' => 0,
9978 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
9979 
              'type' => 'Bool',
9980 
            },
9981 
            'direction' => 'out',
9982 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9983 
            'width' => 1,
9984 
          },
9985 
          'to_register25_dout' => {
9986 
            'attributes' => {
9987 
              'bin_pt' => 0,
9988 
              'is_floating_block' => 1,
9989 
              'must_be_hdl_vector' => 1,
9990 
              'period' => 1,
9991 
              'port_id' => 0,
9992 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
9993 
              'type' => 'Bool',
9994 
            },
9995 
            'direction' => 'in',
9996 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9997 
            'width' => 1,
9998 
          },
9999 
          'to_register25_en' => {
10000 
            'attributes' => {
10001 
              'bin_pt' => 0,
10002 
              'is_floating_block' => 1,
10003 
              'must_be_hdl_vector' => 1,
10004 
              'period' => 1,
10005 
              'port_id' => 1,
10006 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
10007 
              'type' => 'Bool',
10008 
            },
10009 
            'direction' => 'out',
10010 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10011 
            'width' => 1,
10012 
          },
10013 
          'to_register26_ce' => {
10014 
            'attributes' => {
10015 
              'domain' => '',
10016 
              'group' => 1,
10017 
              'isCe' => 1,
10018 
              'is_floating_block' => 1,
10019 
              'period' => 1,
10020 
              'type' => 'logic',
10021 
            },
10022 
            'direction' => 'out',
10023 
            'hdlType' => 'std_logic',
10024 
            'width' => 1,
10025 
          },
10026 
          'to_register26_clk' => {
10027 
            'attributes' => {
10028 
              'domain' => '',
10029 
              'group' => 1,
10030 
              'isClk' => 1,
10031 
              'is_floating_block' => 1,
10032 
              'period' => 1,
10033 
              'type' => 'logic',
10034 
            },
10035 
            'direction' => 'out',
10036 
            'hdlType' => 'std_logic',
10037 
            'width' => 1,
10038 
          },
10039 
          'to_register26_clr' => {
10040 
            'attributes' => {
10041 
              'domain' => '',
10042 
              'group' => 1,
10043 
              'isClr' => 1,
10044 
              'is_floating_block' => 1,
10045 
              'period' => 1,
10046 
              'type' => 'logic',
10047 
              'valid_bit_used' => 0,
10048 
            },
10049 
            'direction' => 'out',
10050 
            'hdlType' => 'std_logic',
10051 
            'width' => 1,
10052 
          },
10053 
          'to_register26_data_in' => {
10054 
            'attributes' => {
10055 
              'bin_pt' => 0,
10056 
              'is_floating_block' => 1,
10057 
              'must_be_hdl_vector' => 1,
10058 
              'period' => 1,
10059 
              'port_id' => 0,
10060 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
10061 
              'type' => 'UFix_32_0',
10062 
            },
10063 
            'direction' => 'out',
10064 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10065 
            'width' => 32,
10066 
          },
10067 
          'to_register26_dout' => {
10068 
            'attributes' => {
10069 
              'bin_pt' => 0,
10070 
              'is_floating_block' => 1,
10071 
              'must_be_hdl_vector' => 1,
10072 
              'period' => 1,
10073 
              'port_id' => 0,
10074 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
10075 
              'type' => 'UFix_32_0',
10076 
            },
10077 
            'direction' => 'in',
10078 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10079 
            'width' => 32,
10080 
          },
10081 
          'to_register26_en' => {
10082 
            'attributes' => {
10083 
              'bin_pt' => 0,
10084 
              'is_floating_block' => 1,
10085 
              'must_be_hdl_vector' => 1,
10086 
              'period' => 1,
10087 
              'port_id' => 1,
10088 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
10089 
              'type' => 'Bool',
10090 
            },
10091 
            'direction' => 'out',
10092 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10093 
            'width' => 1,
10094 
          },
10095 
          'to_register27_ce' => {
10096 
            'attributes' => {
10097 
              'domain' => '',
10098 
              'group' => 1,
10099 
              'isCe' => 1,
10100 
              'is_floating_block' => 1,
10101 
              'period' => 1,
10102 
              'type' => 'logic',
10103 
            },
10104 
            'direction' => 'out',
10105 
            'hdlType' => 'std_logic',
10106 
            'width' => 1,
10107 
          },
10108 
          'to_register27_clk' => {
10109 
            'attributes' => {
10110 
              'domain' => '',
10111 
              'group' => 1,
10112 
              'isClk' => 1,
10113 
              'is_floating_block' => 1,
10114 
              'period' => 1,
10115 
              'type' => 'logic',
10116 
            },
10117 
            'direction' => 'out',
10118 
            'hdlType' => 'std_logic',
10119 
            'width' => 1,
10120 
          },
10121 
          'to_register27_clr' => {
10122 
            'attributes' => {
10123 
              'domain' => '',
10124 
              'group' => 1,
10125 
              'isClr' => 1,
10126 
              'is_floating_block' => 1,
10127 
              'period' => 1,
10128 
              'type' => 'logic',
10129 
              'valid_bit_used' => 0,
10130 
            },
10131 
            'direction' => 'out',
10132 
            'hdlType' => 'std_logic',
10133 
            'width' => 1,
10134 
          },
10135 
          'to_register27_data_in' => {
10136 
            'attributes' => {
10137 
              'bin_pt' => 0,
10138 
              'is_floating_block' => 1,
10139 
              'must_be_hdl_vector' => 1,
10140 
              'period' => 1,
10141 
              'port_id' => 0,
10142 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
10143 
              'type' => 'Bool',
10144 
            },
10145 
            'direction' => 'out',
10146 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10147 
            'width' => 1,
10148 
          },
10149 
          'to_register27_dout' => {
10150 
            'attributes' => {
10151 
              'bin_pt' => 0,
10152 
              'is_floating_block' => 1,
10153 
              'must_be_hdl_vector' => 1,
10154 
              'period' => 1,
10155 
              'port_id' => 0,
10156 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
10157 
              'type' => 'Bool',
10158 
            },
10159 
            'direction' => 'in',
10160 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10161 
            'width' => 1,
10162 
          },
10163 
          'to_register27_en' => {
10164 
            'attributes' => {
10165 
              'bin_pt' => 0,
10166 
              'is_floating_block' => 1,
10167 
              'must_be_hdl_vector' => 1,
10168 
              'period' => 1,
10169 
              'port_id' => 1,
10170 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
10171 
              'type' => 'Bool',
10172 
            },
10173 
            'direction' => 'out',
10174 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10175 
            'width' => 1,
10176 
          },
10177 
          'to_register28_ce' => {
10178 
            'attributes' => {
10179 
              'domain' => '',
10180 
              'group' => 1,
10181 
              'isCe' => 1,
10182 
              'is_floating_block' => 1,
10183 
              'period' => 1,
10184 
              'type' => 'logic',
10185 
            },
10186 
            'direction' => 'out',
10187 
            'hdlType' => 'std_logic',
10188 
            'width' => 1,
10189 
          },
10190 
          'to_register28_clk' => {
10191 
            'attributes' => {
10192 
              'domain' => '',
10193 
              'group' => 1,
10194 
              'isClk' => 1,
10195 
              'is_floating_block' => 1,
10196 
              'period' => 1,
10197 
              'type' => 'logic',
10198 
            },
10199 
            'direction' => 'out',
10200 
            'hdlType' => 'std_logic',
10201 
            'width' => 1,
10202 
          },
10203 
          'to_register28_clr' => {
10204 
            'attributes' => {
10205 
              'domain' => '',
10206 
              'group' => 1,
10207 
              'isClr' => 1,
10208 
              'is_floating_block' => 1,
10209 
              'period' => 1,
10210 
              'type' => 'logic',
10211 
              'valid_bit_used' => 0,
10212 
            },
10213 
            'direction' => 'out',
10214 
            'hdlType' => 'std_logic',
10215 
            'width' => 1,
10216 
          },
10217 
          'to_register28_data_in' => {
10218 
            'attributes' => {
10219 
              'bin_pt' => 0,
10220 
              'is_floating_block' => 1,
10221 
              'must_be_hdl_vector' => 1,
10222 
              'period' => 1,
10223 
              'port_id' => 0,
10224 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
10225 
              'type' => 'UFix_32_0',
10226 
            },
10227 
            'direction' => 'out',
10228 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10229 
            'width' => 32,
10230 
          },
10231 
          'to_register28_dout' => {
10232 
            'attributes' => {
10233 
              'bin_pt' => 0,
10234 
              'is_floating_block' => 1,
10235 
              'must_be_hdl_vector' => 1,
10236 
              'period' => 1,
10237 
              'port_id' => 0,
10238 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
10239 
              'type' => 'UFix_32_0',
10240 
            },
10241 
            'direction' => 'in',
10242 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10243 
            'width' => 32,
10244 
          },
10245 
          'to_register28_en' => {
10246 
            'attributes' => {
10247 
              'bin_pt' => 0,
10248 
              'is_floating_block' => 1,
10249 
              'must_be_hdl_vector' => 1,
10250 
              'period' => 1,
10251 
              'port_id' => 1,
10252 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
10253 
              'type' => 'Bool',
10254 
            },
10255 
            'direction' => 'out',
10256 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10257 
            'width' => 1,
10258 
          },
10259 
          'to_register29_ce' => {
10260 
            'attributes' => {
10261 
              'domain' => '',
10262 
              'group' => 1,
10263 
              'isCe' => 1,
10264 
              'is_floating_block' => 1,
10265 
              'period' => 1,
10266 
              'type' => 'logic',
10267 
            },
10268 
            'direction' => 'out',
10269 
            'hdlType' => 'std_logic',
10270 
            'width' => 1,
10271 
          },
10272 
          'to_register29_clk' => {
10273 
            'attributes' => {
10274 
              'domain' => '',
10275 
              'group' => 1,
10276 
              'isClk' => 1,
10277 
              'is_floating_block' => 1,
10278 
              'period' => 1,
10279 
              'type' => 'logic',
10280 
            },
10281 
            'direction' => 'out',
10282 
            'hdlType' => 'std_logic',
10283 
            'width' => 1,
10284 
          },
10285 
          'to_register29_clr' => {
10286 
            'attributes' => {
10287 
              'domain' => '',
10288 
              'group' => 1,
10289 
              'isClr' => 1,
10290 
              'is_floating_block' => 1,
10291 
              'period' => 1,
10292 
              'type' => 'logic',
10293 
              'valid_bit_used' => 0,
10294 
            },
10295 
            'direction' => 'out',
10296 
            'hdlType' => 'std_logic',
10297 
            'width' => 1,
10298 
          },
10299 
          'to_register29_data_in' => {
10300 
            'attributes' => {
10301 
              'bin_pt' => 0,
10302 
              'is_floating_block' => 1,
10303 
              'must_be_hdl_vector' => 1,
10304 
              'period' => 1,
10305 
              'port_id' => 0,
10306 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
10307 
              'type' => 'Bool',
10308 
            },
10309 
            'direction' => 'out',
10310 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10311 
            'width' => 1,
10312 
          },
10313 
          'to_register29_dout' => {
10314 
            'attributes' => {
10315 
              'bin_pt' => 0,
10316 
              'is_floating_block' => 1,
10317 
              'must_be_hdl_vector' => 1,
10318 
              'period' => 1,
10319 
              'port_id' => 0,
10320 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
10321 
              'type' => 'Bool',
10322 
            },
10323 
            'direction' => 'in',
10324 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10325 
            'width' => 1,
10326 
          },
10327 
          'to_register29_en' => {
10328 
            'attributes' => {
10329 
              'bin_pt' => 0,
10330 
              'is_floating_block' => 1,
10331 
              'must_be_hdl_vector' => 1,
10332 
              'period' => 1,
10333 
              'port_id' => 1,
10334 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
10335 
              'type' => 'Bool',
10336 
            },
10337 
            'direction' => 'out',
10338 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10339 
            'width' => 1,
10340 
          },
10341 
          'to_register2_ce' => {
10342 
            'attributes' => {
10343 
              'domain' => '',
10344 
              'group' => 1,
10345 
              'isCe' => 1,
10346 
              'is_floating_block' => 1,
10347 
              'period' => 1,
10348 
              'type' => 'logic',
10349 
            },
10350 
            'direction' => 'out',
10351 
            'hdlType' => 'std_logic',
10352 
            'width' => 1,
10353 
          },
10354 
          'to_register2_clk' => {
10355 
            'attributes' => {
10356 
              'domain' => '',
10357 
              'group' => 1,
10358 
              'isClk' => 1,
10359 
              'is_floating_block' => 1,
10360 
              'period' => 1,
10361 
              'type' => 'logic',
10362 
            },
10363 
            'direction' => 'out',
10364 
            'hdlType' => 'std_logic',
10365 
            'width' => 1,
10366 
          },
10367 
          'to_register2_clr' => {
10368 
            'attributes' => {
10369 
              'domain' => '',
10370 
              'group' => 1,
10371 
              'isClr' => 1,
10372 
              'is_floating_block' => 1,
10373 
              'period' => 1,
10374 
              'type' => 'logic',
10375 
              'valid_bit_used' => 0,
10376 
            },
10377 
            'direction' => 'out',
10378 
            'hdlType' => 'std_logic',
10379 
            'width' => 1,
10380 
          },
10381 
          'to_register2_data_in' => {
10382 
            'attributes' => {
10383 
              'bin_pt' => 0,
10384 
              'is_floating_block' => 1,
10385 
              'must_be_hdl_vector' => 1,
10386 
              'period' => 1,
10387 
              'port_id' => 0,
10388 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
10389 
              'type' => 'UFix_32_0',
10390 
            },
10391 
            'direction' => 'out',
10392 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10393 
            'width' => 32,
10394 
          },
10395 
          'to_register2_dout' => {
10396 
            'attributes' => {
10397 
              'bin_pt' => 0,
10398 
              'is_floating_block' => 1,
10399 
              'must_be_hdl_vector' => 1,
10400 
              'period' => 1,
10401 
              'port_id' => 0,
10402 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
10403 
              'type' => 'UFix_32_0',
10404 
            },
10405 
            'direction' => 'in',
10406 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10407 
            'width' => 32,
10408 
          },
10409 
          'to_register2_en' => {
10410 
            'attributes' => {
10411 
              'bin_pt' => 0,
10412 
              'is_floating_block' => 1,
10413 
              'must_be_hdl_vector' => 1,
10414 
              'period' => 1,
10415 
              'port_id' => 1,
10416 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
10417 
              'type' => 'Bool',
10418 
            },
10419 
            'direction' => 'out',
10420 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10421 
            'width' => 1,
10422 
          },
10423 
          'to_register30_ce' => {
10424 
            'attributes' => {
10425 
              'domain' => '',
10426 
              'group' => 1,
10427 
              'isCe' => 1,
10428 
              'is_floating_block' => 1,
10429 
              'period' => 1,
10430 
              'type' => 'logic',
10431 
            },
10432 
            'direction' => 'out',
10433 
            'hdlType' => 'std_logic',
10434 
            'width' => 1,
10435 
          },
10436 
          'to_register30_clk' => {
10437 
            'attributes' => {
10438 
              'domain' => '',
10439 
              'group' => 1,
10440 
              'isClk' => 1,
10441 
              'is_floating_block' => 1,
10442 
              'period' => 1,
10443 
              'type' => 'logic',
10444 
            },
10445 
            'direction' => 'out',
10446 
            'hdlType' => 'std_logic',
10447 
            'width' => 1,
10448 
          },
10449 
          'to_register30_clr' => {
10450 
            'attributes' => {
10451 
              'domain' => '',
10452 
              'group' => 1,
10453 
              'isClr' => 1,
10454 
              'is_floating_block' => 1,
10455 
              'period' => 1,
10456 
              'type' => 'logic',
10457 
              'valid_bit_used' => 0,
10458 
            },
10459 
            'direction' => 'out',
10460 
            'hdlType' => 'std_logic',
10461 
            'width' => 1,
10462 
          },
10463 
          'to_register30_data_in' => {
10464 
            'attributes' => {
10465 
              'bin_pt' => 0,
10466 
              'is_floating_block' => 1,
10467 
              'must_be_hdl_vector' => 1,
10468 
              'period' => 1,
10469 
              'port_id' => 0,
10470 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
10471 
              'type' => 'UFix_32_0',
10472 
            },
10473 
            'direction' => 'out',
10474 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10475 
            'width' => 32,
10476 
          },
10477 
          'to_register30_dout' => {
10478 
            'attributes' => {
10479 
              'bin_pt' => 0,
10480 
              'is_floating_block' => 1,
10481 
              'must_be_hdl_vector' => 1,
10482 
              'period' => 1,
10483 
              'port_id' => 0,
10484 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
10485 
              'type' => 'UFix_32_0',
10486 
            },
10487 
            'direction' => 'in',
10488 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10489 
            'width' => 32,
10490 
          },
10491 
          'to_register30_en' => {
10492 
            'attributes' => {
10493 
              'bin_pt' => 0,
10494 
              'is_floating_block' => 1,
10495 
              'must_be_hdl_vector' => 1,
10496 
              'period' => 1,
10497 
              'port_id' => 1,
10498 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
10499 
              'type' => 'Bool',
10500 
            },
10501 
            'direction' => 'out',
10502 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10503 
            'width' => 1,
10504 
          },
10505 
          'to_register31_ce' => {
10506 
            'attributes' => {
10507 
              'domain' => '',
10508 
              'group' => 1,
10509 
              'isCe' => 1,
10510 
              'is_floating_block' => 1,
10511 
              'period' => 1,
10512 
              'type' => 'logic',
10513 
            },
10514 
            'direction' => 'out',
10515 
            'hdlType' => 'std_logic',
10516 
            'width' => 1,
10517 
          },
10518 
          'to_register31_clk' => {
10519 
            'attributes' => {
10520 
              'domain' => '',
10521 
              'group' => 1,
10522 
              'isClk' => 1,
10523 
              'is_floating_block' => 1,
10524 
              'period' => 1,
10525 
              'type' => 'logic',
10526 
            },
10527 
            'direction' => 'out',
10528 
            'hdlType' => 'std_logic',
10529 
            'width' => 1,
10530 
          },
10531 
          'to_register31_clr' => {
10532 
            'attributes' => {
10533 
              'domain' => '',
10534 
              'group' => 1,
10535 
              'isClr' => 1,
10536 
              'is_floating_block' => 1,
10537 
              'period' => 1,
10538 
              'type' => 'logic',
10539 
              'valid_bit_used' => 0,
10540 
            },
10541 
            'direction' => 'out',
10542 
            'hdlType' => 'std_logic',
10543 
            'width' => 1,
10544 
          },
10545 
          'to_register31_data_in' => {
10546 
            'attributes' => {
10547 
              'bin_pt' => 0,
10548 
              'is_floating_block' => 1,
10549 
              'must_be_hdl_vector' => 1,
10550 
              'period' => 1,
10551 
              'port_id' => 0,
10552 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
10553 
              'type' => 'Bool',
10554 
            },
10555 
            'direction' => 'out',
10556 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10557 
            'width' => 1,
10558 
          },
10559 
          'to_register31_dout' => {
10560 
            'attributes' => {
10561 
              'bin_pt' => 0,
10562 
              'is_floating_block' => 1,
10563 
              'must_be_hdl_vector' => 1,
10564 
              'period' => 1,
10565 
              'port_id' => 0,
10566 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
10567 
              'type' => 'Bool',
10568 
            },
10569 
            'direction' => 'in',
10570 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10571 
            'width' => 1,
10572 
          },
10573 
          'to_register31_en' => {
10574 
            'attributes' => {
10575 
              'bin_pt' => 0,
10576 
              'is_floating_block' => 1,
10577 
              'must_be_hdl_vector' => 1,
10578 
              'period' => 1,
10579 
              'port_id' => 1,
10580 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
10581 
              'type' => 'Bool',
10582 
            },
10583 
            'direction' => 'out',
10584 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10585 
            'width' => 1,
10586 
          },
10587 
          'to_register32_ce' => {
10588 
            'attributes' => {
10589 
              'domain' => '',
10590 
              'group' => 1,
10591 
              'isCe' => 1,
10592 
              'is_floating_block' => 1,
10593 
              'period' => 1,
10594 
              'type' => 'logic',
10595 
            },
10596 
            'direction' => 'out',
10597 
            'hdlType' => 'std_logic',
10598 
            'width' => 1,
10599 
          },
10600 
          'to_register32_clk' => {
10601 
            'attributes' => {
10602 
              'domain' => '',
10603 
              'group' => 1,
10604 
              'isClk' => 1,
10605 
              'is_floating_block' => 1,
10606 
              'period' => 1,
10607 
              'type' => 'logic',
10608 
            },
10609 
            'direction' => 'out',
10610 
            'hdlType' => 'std_logic',
10611 
            'width' => 1,
10612 
          },
10613 
          'to_register32_clr' => {
10614 
            'attributes' => {
10615 
              'domain' => '',
10616 
              'group' => 1,
10617 
              'isClr' => 1,
10618 
              'is_floating_block' => 1,
10619 
              'period' => 1,
10620 
              'type' => 'logic',
10621 
              'valid_bit_used' => 0,
10622 
            },
10623 
            'direction' => 'out',
10624 
            'hdlType' => 'std_logic',
10625 
            'width' => 1,
10626 
          },
10627 
          'to_register32_data_in' => {
10628 
            'attributes' => {
10629 
              'bin_pt' => 0,
10630 
              'is_floating_block' => 1,
10631 
              'must_be_hdl_vector' => 1,
10632 
              'period' => 1,
10633 
              'port_id' => 0,
10634 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
10635 
              'type' => 'UFix_32_0',
10636 
            },
10637 
            'direction' => 'out',
10638 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10639 
            'width' => 32,
10640 
          },
10641 
          'to_register32_dout' => {
10642 
            'attributes' => {
10643 
              'bin_pt' => 0,
10644 
              'is_floating_block' => 1,
10645 
              'must_be_hdl_vector' => 1,
10646 
              'period' => 1,
10647 
              'port_id' => 0,
10648 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
10649 
              'type' => 'UFix_32_0',
10650 
            },
10651 
            'direction' => 'in',
10652 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10653 
            'width' => 32,
10654 
          },
10655 
          'to_register32_en' => {
10656 
            'attributes' => {
10657 
              'bin_pt' => 0,
10658 
              'is_floating_block' => 1,
10659 
              'must_be_hdl_vector' => 1,
10660 
              'period' => 1,
10661 
              'port_id' => 1,
10662 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
10663 
              'type' => 'Bool',
10664 
            },
10665 
            'direction' => 'out',
10666 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10667 
            'width' => 1,
10668 
          },
10669 
          'to_register33_ce' => {
10670 
            'attributes' => {
10671 
              'domain' => '',
10672 
              'group' => 1,
10673 
              'isCe' => 1,
10674 
              'is_floating_block' => 1,
10675 
              'period' => 1,
10676 
              'type' => 'logic',
10677 
            },
10678 
            'direction' => 'out',
10679 
            'hdlType' => 'std_logic',
10680 
            'width' => 1,
10681 
          },
10682 
          'to_register33_clk' => {
10683 
            'attributes' => {
10684 
              'domain' => '',
10685 
              'group' => 1,
10686 
              'isClk' => 1,
10687 
              'is_floating_block' => 1,
10688 
              'period' => 1,
10689 
              'type' => 'logic',
10690 
            },
10691 
            'direction' => 'out',
10692 
            'hdlType' => 'std_logic',
10693 
            'width' => 1,
10694 
          },
10695 
          'to_register33_clr' => {
10696 
            'attributes' => {
10697 
              'domain' => '',
10698 
              'group' => 1,
10699 
              'isClr' => 1,
10700 
              'is_floating_block' => 1,
10701 
              'period' => 1,
10702 
              'type' => 'logic',
10703 
              'valid_bit_used' => 0,
10704 
            },
10705 
            'direction' => 'out',
10706 
            'hdlType' => 'std_logic',
10707 
            'width' => 1,
10708 
          },
10709 
          'to_register33_data_in' => {
10710 
            'attributes' => {
10711 
              'bin_pt' => 0,
10712 
              'is_floating_block' => 1,
10713 
              'must_be_hdl_vector' => 1,
10714 
              'period' => 1,
10715 
              'port_id' => 0,
10716 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
10717 
              'type' => 'Bool',
10718 
            },
10719 
            'direction' => 'out',
10720 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10721 
            'width' => 1,
10722 
          },
10723 
          'to_register33_dout' => {
10724 
            'attributes' => {
10725 
              'bin_pt' => 0,
10726 
              'is_floating_block' => 1,
10727 
              'must_be_hdl_vector' => 1,
10728 
              'period' => 1,
10729 
              'port_id' => 0,
10730 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
10731 
              'type' => 'Bool',
10732 
            },
10733 
            'direction' => 'in',
10734 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10735 
            'width' => 1,
10736 
          },
10737 
          'to_register33_en' => {
10738 
            'attributes' => {
10739 
              'bin_pt' => 0,
10740 
              'is_floating_block' => 1,
10741 
              'must_be_hdl_vector' => 1,
10742 
              'period' => 1,
10743 
              'port_id' => 1,
10744 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
10745 
              'type' => 'Bool',
10746 
            },
10747 
            'direction' => 'out',
10748 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10749 
            'width' => 1,
10750 
          },
10751 
          'to_register34_ce' => {
10752 
            'attributes' => {
10753 
              'domain' => '',
10754 
              'group' => 1,
10755 
              'isCe' => 1,
10756 
              'is_floating_block' => 1,
10757 
              'period' => 1,
10758 
              'type' => 'logic',
10759 
            },
10760 
            'direction' => 'out',
10761 
            'hdlType' => 'std_logic',
10762 
            'width' => 1,
10763 
          },
10764 
          'to_register34_clk' => {
10765 
            'attributes' => {
10766 
              'domain' => '',
10767 
              'group' => 1,
10768 
              'isClk' => 1,
10769 
              'is_floating_block' => 1,
10770 
              'period' => 1,
10771 
              'type' => 'logic',
10772 
            },
10773 
            'direction' => 'out',
10774 
            'hdlType' => 'std_logic',
10775 
            'width' => 1,
10776 
          },
10777 
          'to_register34_clr' => {
10778 
            'attributes' => {
10779 
              'domain' => '',
10780 
              'group' => 1,
10781 
              'isClr' => 1,
10782 
              'is_floating_block' => 1,
10783 
              'period' => 1,
10784 
              'type' => 'logic',
10785 
              'valid_bit_used' => 0,
10786 
            },
10787 
            'direction' => 'out',
10788 
            'hdlType' => 'std_logic',
10789 
            'width' => 1,
10790 
          },
10791 
          'to_register34_data_in' => {
10792 
            'attributes' => {
10793 
              'bin_pt' => 0,
10794 
              'is_floating_block' => 1,
10795 
              'must_be_hdl_vector' => 1,
10796 
              'period' => 1,
10797 
              'port_id' => 0,
10798 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
10799 
              'type' => 'UFix_32_0',
10800 
            },
10801 
            'direction' => 'out',
10802 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10803 
            'width' => 32,
10804 
          },
10805 
          'to_register34_dout' => {
10806 
            'attributes' => {
10807 
              'bin_pt' => 0,
10808 
              'is_floating_block' => 1,
10809 
              'must_be_hdl_vector' => 1,
10810 
              'period' => 1,
10811 
              'port_id' => 0,
10812 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
10813 
              'type' => 'UFix_32_0',
10814 
            },
10815 
            'direction' => 'in',
10816 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10817 
            'width' => 32,
10818 
          },
10819 
          'to_register34_en' => {
10820 
            'attributes' => {
10821 
              'bin_pt' => 0,
10822 
              'is_floating_block' => 1,
10823 
              'must_be_hdl_vector' => 1,
10824 
              'period' => 1,
10825 
              'port_id' => 1,
10826 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
10827 
              'type' => 'Bool',
10828 
            },
10829 
            'direction' => 'out',
10830 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10831 
            'width' => 1,
10832 
          },
10833 
          'to_register3_ce' => {
10834 
            'attributes' => {
10835 
              'domain' => '',
10836 
              'group' => 1,
10837 
              'isCe' => 1,
10838 
              'is_floating_block' => 1,
10839 
              'period' => 1,
10840 
              'type' => 'logic',
10841 
            },
10842 
            'direction' => 'out',
10843 
            'hdlType' => 'std_logic',
10844 
            'width' => 1,
10845 
          },
10846 
          'to_register3_clk' => {
10847 
            'attributes' => {
10848 
              'domain' => '',
10849 
              'group' => 1,
10850 
              'isClk' => 1,
10851 
              'is_floating_block' => 1,
10852 
              'period' => 1,
10853 
              'type' => 'logic',
10854 
            },
10855 
            'direction' => 'out',
10856 
            'hdlType' => 'std_logic',
10857 
            'width' => 1,
10858 
          },
10859 
          'to_register3_clr' => {
10860 
            'attributes' => {
10861 
              'domain' => '',
10862 
              'group' => 1,
10863 
              'isClr' => 1,
10864 
              'is_floating_block' => 1,
10865 
              'period' => 1,
10866 
              'type' => 'logic',
10867 
              'valid_bit_used' => 0,
10868 
            },
10869 
            'direction' => 'out',
10870 
            'hdlType' => 'std_logic',
10871 
            'width' => 1,
10872 
          },
10873 
          'to_register3_data_in' => {
10874 
            'attributes' => {
10875 
              'bin_pt' => 0,
10876 
              'is_floating_block' => 1,
10877 
              'must_be_hdl_vector' => 1,
10878 
              'period' => 1,
10879 
              'port_id' => 0,
10880 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
10881 
              'type' => 'Bool',
10882 
            },
10883 
            'direction' => 'out',
10884 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10885 
            'width' => 1,
10886 
          },
10887 
          'to_register3_dout' => {
10888 
            'attributes' => {
10889 
              'bin_pt' => 0,
10890 
              'is_floating_block' => 1,
10891 
              'must_be_hdl_vector' => 1,
10892 
              'period' => 1,
10893 
              'port_id' => 0,
10894 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
10895 
              'type' => 'Bool',
10896 
            },
10897 
            'direction' => 'in',
10898 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10899 
            'width' => 1,
10900 
          },
10901 
          'to_register3_en' => {
10902 
            'attributes' => {
10903 
              'bin_pt' => 0,
10904 
              'is_floating_block' => 1,
10905 
              'must_be_hdl_vector' => 1,
10906 
              'period' => 1,
10907 
              'port_id' => 1,
10908 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
10909 
              'type' => 'Bool',
10910 
            },
10911 
            'direction' => 'out',
10912 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10913 
            'width' => 1,
10914 
          },
10915 
          'to_register4_ce' => {
10916 
            'attributes' => {
10917 
              'domain' => '',
10918 
              'group' => 1,
10919 
              'isCe' => 1,
10920 
              'is_floating_block' => 1,
10921 
              'period' => 1,
10922 
              'type' => 'logic',
10923 
            },
10924 
            'direction' => 'out',
10925 
            'hdlType' => 'std_logic',
10926 
            'width' => 1,
10927 
          },
10928 
          'to_register4_clk' => {
10929 
            'attributes' => {
10930 
              'domain' => '',
10931 
              'group' => 1,
10932 
              'isClk' => 1,
10933 
              'is_floating_block' => 1,
10934 
              'period' => 1,
10935 
              'type' => 'logic',
10936 
            },
10937 
            'direction' => 'out',
10938 
            'hdlType' => 'std_logic',
10939 
            'width' => 1,
10940 
          },
10941 
          'to_register4_clr' => {
10942 
            'attributes' => {
10943 
              'domain' => '',
10944 
              'group' => 1,
10945 
              'isClr' => 1,
10946 
              'is_floating_block' => 1,
10947 
              'period' => 1,
10948 
              'type' => 'logic',
10949 
              'valid_bit_used' => 0,
10950 
            },
10951 
            'direction' => 'out',
10952 
            'hdlType' => 'std_logic',
10953 
            'width' => 1,
10954 
          },
10955 
          'to_register4_data_in' => {
10956 
            'attributes' => {
10957 
              'bin_pt' => 0,
10958 
              'is_floating_block' => 1,
10959 
              'must_be_hdl_vector' => 1,
10960 
              'period' => 1,
10961 
              'port_id' => 0,
10962 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
10963 
              'type' => 'Bool',
10964 
            },
10965 
            'direction' => 'out',
10966 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10967 
            'width' => 1,
10968 
          },
10969 
          'to_register4_dout' => {
10970 
            'attributes' => {
10971 
              'bin_pt' => 0,
10972 
              'is_floating_block' => 1,
10973 
              'must_be_hdl_vector' => 1,
10974 
              'period' => 1,
10975 
              'port_id' => 0,
10976 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
10977 
              'type' => 'Bool',
10978 
            },
10979 
            'direction' => 'in',
10980 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10981 
            'width' => 1,
10982 
          },
10983 
          'to_register4_en' => {
10984 
            'attributes' => {
10985 
              'bin_pt' => 0,
10986 
              'is_floating_block' => 1,
10987 
              'must_be_hdl_vector' => 1,
10988 
              'period' => 1,
10989 
              'port_id' => 1,
10990 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
10991 
              'type' => 'Bool',
10992 
            },
10993 
            'direction' => 'out',
10994 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10995 
            'width' => 1,
10996 
          },
10997 
          'to_register5_ce' => {
10998 
            'attributes' => {
10999 
              'domain' => '',
11000 
              'group' => 1,
11001 
              'isCe' => 1,
11002 
              'is_floating_block' => 1,
11003 
              'period' => 1,
11004 
              'type' => 'logic',
11005 
            },
11006 
            'direction' => 'out',
11007 
            'hdlType' => 'std_logic',
11008 
            'width' => 1,
11009 
          },
11010 
          'to_register5_clk' => {
11011 
            'attributes' => {
11012 
              'domain' => '',
11013 
              'group' => 1,
11014 
              'isClk' => 1,
11015 
              'is_floating_block' => 1,
11016 
              'period' => 1,
11017 
              'type' => 'logic',
11018 
            },
11019 
            'direction' => 'out',
11020 
            'hdlType' => 'std_logic',
11021 
            'width' => 1,
11022 
          },
11023 
          'to_register5_clr' => {
11024 
            'attributes' => {
11025 
              'domain' => '',
11026 
              'group' => 1,
11027 
              'isClr' => 1,
11028 
              'is_floating_block' => 1,
11029 
              'period' => 1,
11030 
              'type' => 'logic',
11031 
              'valid_bit_used' => 0,
11032 
            },
11033 
            'direction' => 'out',
11034 
            'hdlType' => 'std_logic',
11035 
            'width' => 1,
11036 
          },
11037 
          'to_register5_data_in' => {
11038 
            'attributes' => {
11039 
              'bin_pt' => 0,
11040 
              'is_floating_block' => 1,
11041 
              'must_be_hdl_vector' => 1,
11042 
              'period' => 1,
11043 
              'port_id' => 0,
11044 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
11045 
              'type' => 'UFix_32_0',
11046 
            },
11047 
            'direction' => 'out',
11048 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11049 
            'width' => 32,
11050 
          },
11051 
          'to_register5_dout' => {
11052 
            'attributes' => {
11053 
              'bin_pt' => 0,
11054 
              'is_floating_block' => 1,
11055 
              'must_be_hdl_vector' => 1,
11056 
              'period' => 1,
11057 
              'port_id' => 0,
11058 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
11059 
              'type' => 'UFix_32_0',
11060 
            },
11061 
            'direction' => 'in',
11062 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11063 
            'width' => 32,
11064 
          },
11065 
          'to_register5_en' => {
11066 
            'attributes' => {
11067 
              'bin_pt' => 0,
11068 
              'is_floating_block' => 1,
11069 
              'must_be_hdl_vector' => 1,
11070 
              'period' => 1,
11071 
              'port_id' => 1,
11072 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11073 
              'type' => 'Bool',
11074 
            },
11075 
            'direction' => 'out',
11076 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11077 
            'width' => 1,
11078 
          },
11079 
          'to_register6_ce' => {
11080 
            'attributes' => {
11081 
              'domain' => '',
11082 
              'group' => 1,
11083 
              'isCe' => 1,
11084 
              'is_floating_block' => 1,
11085 
              'period' => 1,
11086 
              'type' => 'logic',
11087 
            },
11088 
            'direction' => 'out',
11089 
            'hdlType' => 'std_logic',
11090 
            'width' => 1,
11091 
          },
11092 
          'to_register6_clk' => {
11093 
            'attributes' => {
11094 
              'domain' => '',
11095 
              'group' => 1,
11096 
              'isClk' => 1,
11097 
              'is_floating_block' => 1,
11098 
              'period' => 1,
11099 
              'type' => 'logic',
11100 
            },
11101 
            'direction' => 'out',
11102 
            'hdlType' => 'std_logic',
11103 
            'width' => 1,
11104 
          },
11105 
          'to_register6_clr' => {
11106 
            'attributes' => {
11107 
              'domain' => '',
11108 
              'group' => 1,
11109 
              'isClr' => 1,
11110 
              'is_floating_block' => 1,
11111 
              'period' => 1,
11112 
              'type' => 'logic',
11113 
              'valid_bit_used' => 0,
11114 
            },
11115 
            'direction' => 'out',
11116 
            'hdlType' => 'std_logic',
11117 
            'width' => 1,
11118 
          },
11119 
          'to_register6_data_in' => {
11120 
            'attributes' => {
11121 
              'bin_pt' => 0,
11122 
              'is_floating_block' => 1,
11123 
              'must_be_hdl_vector' => 1,
11124 
              'period' => 1,
11125 
              'port_id' => 0,
11126 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
11127 
              'type' => 'UFix_32_0',
11128 
            },
11129 
            'direction' => 'out',
11130 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11131 
            'width' => 32,
11132 
          },
11133 
          'to_register6_dout' => {
11134 
            'attributes' => {
11135 
              'bin_pt' => 0,
11136 
              'is_floating_block' => 1,
11137 
              'must_be_hdl_vector' => 1,
11138 
              'period' => 1,
11139 
              'port_id' => 0,
11140 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
11141 
              'type' => 'UFix_32_0',
11142 
            },
11143 
            'direction' => 'in',
11144 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11145 
            'width' => 32,
11146 
          },
11147 
          'to_register6_en' => {
11148 
            'attributes' => {
11149 
              'bin_pt' => 0,
11150 
              'is_floating_block' => 1,
11151 
              'must_be_hdl_vector' => 1,
11152 
              'period' => 1,
11153 
              'port_id' => 1,
11154 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
11155 
              'type' => 'Bool',
11156 
            },
11157 
            'direction' => 'out',
11158 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11159 
            'width' => 1,
11160 
          },
11161 
          'to_register7_ce' => {
11162 
            'attributes' => {
11163 
              'domain' => '',
11164 
              'group' => 1,
11165 
              'isCe' => 1,
11166 
              'is_floating_block' => 1,
11167 
              'period' => 1,
11168 
              'type' => 'logic',
11169 
            },
11170 
            'direction' => 'out',
11171 
            'hdlType' => 'std_logic',
11172 
            'width' => 1,
11173 
          },
11174 
          'to_register7_clk' => {
11175 
            'attributes' => {
11176 
              'domain' => '',
11177 
              'group' => 1,
11178 
              'isClk' => 1,
11179 
              'is_floating_block' => 1,
11180 
              'period' => 1,
11181 
              'type' => 'logic',
11182 
            },
11183 
            'direction' => 'out',
11184 
            'hdlType' => 'std_logic',
11185 
            'width' => 1,
11186 
          },
11187 
          'to_register7_clr' => {
11188 
            'attributes' => {
11189 
              'domain' => '',
11190 
              'group' => 1,
11191 
              'isClr' => 1,
11192 
              'is_floating_block' => 1,
11193 
              'period' => 1,
11194 
              'type' => 'logic',
11195 
              'valid_bit_used' => 0,
11196 
            },
11197 
            'direction' => 'out',
11198 
            'hdlType' => 'std_logic',
11199 
            'width' => 1,
11200 
          },
11201 
          'to_register7_data_in' => {
11202 
            'attributes' => {
11203 
              'bin_pt' => 0,
11204 
              'is_floating_block' => 1,
11205 
              'must_be_hdl_vector' => 1,
11206 
              'period' => 1,
11207 
              'port_id' => 0,
11208 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
11209 
              'type' => 'UFix_32_0',
11210 
            },
11211 
            'direction' => 'out',
11212 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11213 
            'width' => 32,
11214 
          },
11215 
          'to_register7_dout' => {
11216 
            'attributes' => {
11217 
              'bin_pt' => 0,
11218 
              'is_floating_block' => 1,
11219 
              'must_be_hdl_vector' => 1,
11220 
              'period' => 1,
11221 
              'port_id' => 0,
11222 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
11223 
              'type' => 'UFix_32_0',
11224 
            },
11225 
            'direction' => 'in',
11226 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11227 
            'width' => 32,
11228 
          },
11229 
          'to_register7_en' => {
11230 
            'attributes' => {
11231 
              'bin_pt' => 0,
11232 
              'is_floating_block' => 1,
11233 
              'must_be_hdl_vector' => 1,
11234 
              'period' => 1,
11235 
              'port_id' => 1,
11236 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11237 
              'type' => 'Bool',
11238 
            },
11239 
            'direction' => 'out',
11240 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11241 
            'width' => 1,
11242 
          },
11243 
          'to_register8_ce' => {
11244 
            'attributes' => {
11245 
              'domain' => '',
11246 
              'group' => 1,
11247 
              'isCe' => 1,
11248 
              'is_floating_block' => 1,
11249 
              'period' => 1,
11250 
              'type' => 'logic',
11251 
            },
11252 
            'direction' => 'out',
11253 
            'hdlType' => 'std_logic',
11254 
            'width' => 1,
11255 
          },
11256 
          'to_register8_clk' => {
11257 
            'attributes' => {
11258 
              'domain' => '',
11259 
              'group' => 1,
11260 
              'isClk' => 1,
11261 
              'is_floating_block' => 1,
11262 
              'period' => 1,
11263 
              'type' => 'logic',
11264 
            },
11265 
            'direction' => 'out',
11266 
            'hdlType' => 'std_logic',
11267 
            'width' => 1,
11268 
          },
11269 
          'to_register8_clr' => {
11270 
            'attributes' => {
11271 
              'domain' => '',
11272 
              'group' => 1,
11273 
              'isClr' => 1,
11274 
              'is_floating_block' => 1,
11275 
              'period' => 1,
11276 
              'type' => 'logic',
11277 
              'valid_bit_used' => 0,
11278 
            },
11279 
            'direction' => 'out',
11280 
            'hdlType' => 'std_logic',
11281 
            'width' => 1,
11282 
          },
11283 
          'to_register8_data_in' => {
11284 
            'attributes' => {
11285 
              'bin_pt' => 0,
11286 
              'is_floating_block' => 1,
11287 
              'must_be_hdl_vector' => 1,
11288 
              'period' => 1,
11289 
              'port_id' => 0,
11290 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11291 
              'type' => 'Bool',
11292 
            },
11293 
            'direction' => 'out',
11294 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11295 
            'width' => 1,
11296 
          },
11297 
          'to_register8_dout' => {
11298 
            'attributes' => {
11299 
              'bin_pt' => 0,
11300 
              'is_floating_block' => 1,
11301 
              'must_be_hdl_vector' => 1,
11302 
              'period' => 1,
11303 
              'port_id' => 0,
11304 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11305 
              'type' => 'Bool',
11306 
            },
11307 
            'direction' => 'in',
11308 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11309 
            'width' => 1,
11310 
          },
11311 
          'to_register8_en' => {
11312 
            'attributes' => {
11313 
              'bin_pt' => 0,
11314 
              'is_floating_block' => 1,
11315 
              'must_be_hdl_vector' => 1,
11316 
              'period' => 1,
11317 
              'port_id' => 1,
11318 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11319 
              'type' => 'Bool',
11320 
            },
11321 
            'direction' => 'out',
11322 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11323 
            'width' => 1,
11324 
          },
11325 
          'to_register9_ce' => {
11326 
            'attributes' => {
11327 
              'domain' => '',
11328 
              'group' => 1,
11329 
              'isCe' => 1,
11330 
              'is_floating_block' => 1,
11331 
              'period' => 1,
11332 
              'type' => 'logic',
11333 
            },
11334 
            'direction' => 'out',
11335 
            'hdlType' => 'std_logic',
11336 
            'width' => 1,
11337 
          },
11338 
          'to_register9_clk' => {
11339 
            'attributes' => {
11340 
              'domain' => '',
11341 
              'group' => 1,
11342 
              'isClk' => 1,
11343 
              'is_floating_block' => 1,
11344 
              'period' => 1,
11345 
              'type' => 'logic',
11346 
            },
11347 
            'direction' => 'out',
11348 
            'hdlType' => 'std_logic',
11349 
            'width' => 1,
11350 
          },
11351 
          'to_register9_clr' => {
11352 
            'attributes' => {
11353 
              'domain' => '',
11354 
              'group' => 1,
11355 
              'isClr' => 1,
11356 
              'is_floating_block' => 1,
11357 
              'period' => 1,
11358 
              'type' => 'logic',
11359 
              'valid_bit_used' => 0,
11360 
            },
11361 
            'direction' => 'out',
11362 
            'hdlType' => 'std_logic',
11363 
            'width' => 1,
11364 
          },
11365 
          'to_register9_data_in' => {
11366 
            'attributes' => {
11367 
              'bin_pt' => 0,
11368 
              'is_floating_block' => 1,
11369 
              'must_be_hdl_vector' => 1,
11370 
              'period' => 1,
11371 
              'port_id' => 0,
11372 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11373 
              'type' => 'UFix_32_0',
11374 
            },
11375 
            'direction' => 'out',
11376 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11377 
            'width' => 32,
11378 
          },
11379 
          'to_register9_dout' => {
11380 
            'attributes' => {
11381 
              'bin_pt' => 0,
11382 
              'is_floating_block' => 1,
11383 
              'must_be_hdl_vector' => 1,
11384 
              'period' => 1,
11385 
              'port_id' => 0,
11386 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11387 
              'type' => 'UFix_32_0',
11388 
            },
11389 
            'direction' => 'in',
11390 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11391 
            'width' => 32,
11392 
          },
11393 
          'to_register9_en' => {
11394 
            'attributes' => {
11395 
              'bin_pt' => 0,
11396 
              'is_floating_block' => 1,
11397 
              'must_be_hdl_vector' => 1,
11398 
              'period' => 1,
11399 
              'port_id' => 1,
11400 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11401 
              'type' => 'Bool',
11402 
            },
11403 
            'direction' => 'out',
11404 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11405 
            'width' => 1,
11406 
          },
11407 
        },
11408 
        'subblocks' => {
11409 
          'default_clock_driver_x0' => {
11410 
            'connections' => {
11411 
              'ce_1' => 'ce_1_sg',
11412 
              'clk_1' => 'clk_1_sg',
11413 
              'sysce' => [
11414 
                'constant',
11415 
                '\'1\'',
11416 
              ],
11417 
              'sysce_clr' => [
11418 
                'constant',
11419 
                '\'0\'',
11420 
              ],
11421 
              'sysclk' => 'clkNet',
11422 
            },
11423 
            'entity' => {
11424 
              'attributes' => {
11425 
                'domain' => 'default',
11426 
                'hdlArchAttributes' => [
11427 
                  [
11428 
                    'syn_noprune',
11429 
                    'boolean',
11430 
                    'true',
11431 
                  ],
11432 
                  [
11433 
                    'optimize_primitives',
11434 
                    'boolean',
11435 
                    'false',
11436 
                  ],
11437 
                  [
11438 
                    'dont_touch',
11439 
                    'boolean',
11440 
                    'true',
11441 
                  ],
11442 
                ],
11443 
                'hdlEntityAttributes' => [],
11444 
                'isClkDriver' => 1,
11445 
              },
11446 
              'entityName' => 'default_clock_driver',
11447 
              'ports' => {
11448 
                'ce_1' => {
11449 
                  'attributes' => {
11450 
                    'domain' => 'default',
11451 
                    'group' => 1,
11452 
                    'isCe' => 1,
11453 
                    'period' => 1,
11454 
                    'type' => 'logic',
11455 
                  },
11456 
                  'direction' => 'out',
11457 
                  'hdlType' => 'std_logic',
11458 
                  'width' => 1,
11459 
                },
11460 
                'clk_1' => {
11461 
                  'attributes' => {
11462 
                    'domain' => 'default',
11463 
                    'group' => 1,
11464 
                    'isClk' => 1,
11465 
                    'period' => 1,
11466 
                    'type' => 'logic',
11467 
                  },
11468 
                  'direction' => 'out',
11469 
                  'hdlType' => 'std_logic',
11470 
                  'width' => 1,
11471 
                },
11472 
                'sysce' => {
11473 
                  'attributes' => {
11474 
                    'group' => 4,
11475 
                    'isCe' => 1,
11476 
                    'period' => 1,
11477 
                  },
11478 
                  'direction' => 'in',
11479 
                  'hdlType' => 'std_logic',
11480 
                  'width' => 1,
11481 
                },
11482 
                'sysce_clr' => {
11483 
                  'attributes' => {
11484 
                    'group' => 4,
11485 
                    'isClr' => 1,
11486 
                    'period' => 1,
11487 
                  },
11488 
                  'direction' => 'in',
11489 
                  'hdlType' => 'std_logic',
11490 
                  'width' => 1,
11491 
                },
11492 
                'sysclk' => {
11493 
                  'attributes' => {
11494 
                    'group' => 4,
11495 
                    'isClk' => 1,
11496 
                    'period' => 1,
11497 
                  },
11498 
                  'direction' => 'in',
11499 
                  'hdlType' => 'std_logic',
11500 
                  'width' => 1,
11501 
                },
11502 
              },
11503 
            },
11504 
            'entityName' => 'default_clock_driver',
11505 
          },
11506 
          'inout_logic_x0' => {
11507 
            'connections' => {
11508 
              'data_in' => 'debug_in_2i_net_x0',
11509 
              'data_in_x0' => 'reg04_tv_net_x0',
11510 
              'data_in_x1' => 'reg04_td_net_x0',
11511 
              'data_in_x10' => 'debug_in_3i_net_x0',
11512 
              'data_in_x11' => 'debug_in_4i_net_x0',
11513 
              'data_in_x12' => 'reg09_tv_net_x0',
11514 
              'data_in_x13' => 'reg09_td_net_x0',
11515 
              'data_in_x14' => 'reg10_tv_net_x0',
11516 
              'data_in_x15' => 'reg10_td_net_x0',
11517 
              'data_in_x16' => 'reg08_tv_net_x0',
11518 
              'data_in_x17' => 'reg08_td_net_x0',
11519 
              'data_in_x18' => 'reg11_tv_net_x0',
11520 
              'data_in_x19' => 'reg11_td_net_x0',
11521 
              'data_in_x2' => 'reg05_tv_net_x0',
11522 
              'data_in_x20' => 'reg12_tv_net_x0',
11523 
              'data_in_x21' => 'reg01_tv_net_x0',
11524 
              'data_in_x22' => 'reg12_td_net_x0',
11525 
              'data_in_x23' => 'reg13_tv_net_x0',
11526 
              'data_in_x24' => 'reg13_td_net_x0',
11527 
              'data_in_x25' => 'reg14_tv_net_x0',
11528 
              'data_in_x26' => 'reg14_td_net_x0',
11529 
              'data_in_x27' => 'reg02_tv_net_x0',
11530 
              'data_in_x28' => 'reg02_td_net_x0',
11531 
              'data_in_x29' => 'debug_in_1i_net_x0',
11532 
              'data_in_x3' => 'reg05_td_net_x0',
11533 
              'data_in_x30' => 'reg01_td_net_x0',
11534 
              'data_in_x31' => 'reg03_tv_net_x0',
11535 
              'data_in_x32' => 'reg03_td_net_x0',
11536 
              'data_in_x4' => 'reg06_tv_net_x0',
11537 
              'data_in_x5' => 'reg06_td_net_x0',
11538 
              'data_in_x6' => 'reg07_tv_net_x0',
11539 
              'data_in_x7' => 'reg07_td_net_x0',
11540 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
11541 
              'data_in_x9' => 'dma_host2board_done_net_x0',
11542 
              'data_out' => 'from_register1_data_out_net',
11543 
              'data_out_x0' => 'from_register10_data_out_net',
11544 
              'data_out_x1' => 'from_register11_data_out_net',
11545 
              'data_out_x10' => 'from_register2_data_out_net',
11546 
              'data_out_x11' => 'from_register20_data_out_net',
11547 
              'data_out_x12' => 'from_register21_data_out_net',
11548 
              'data_out_x13' => 'from_register22_data_out_net',
11549 
              'data_out_x14' => 'from_register23_data_out_net',
11550 
              'data_out_x15' => 'from_register24_data_out_net',
11551 
              'data_out_x16' => 'from_register25_data_out_net',
11552 
              'data_out_x17' => 'from_register26_data_out_net',
11553 
              'data_out_x18' => 'from_register27_data_out_net',
11554 
              'data_out_x19' => 'from_register28_data_out_net',
11555 
              'data_out_x2' => 'from_register12_data_out_net',
11556 
              'data_out_x20' => 'from_register3_data_out_net',
11557 
              'data_out_x21' => 'from_register4_data_out_net',
11558 
              'data_out_x22' => 'from_register5_data_out_net',
11559 
              'data_out_x23' => 'from_register6_data_out_net',
11560 
              'data_out_x24' => 'from_register7_data_out_net',
11561 
              'data_out_x25' => 'from_register8_data_out_net',
11562 
              'data_out_x26' => 'from_register9_data_out_net',
11563 
              'data_out_x3' => 'from_register13_data_out_net',
11564 
              'data_out_x4' => 'from_register14_data_out_net',
11565 
              'data_out_x5' => 'from_register15_data_out_net',
11566 
              'data_out_x6' => 'from_register16_data_out_net',
11567 
              'data_out_x7' => 'from_register17_data_out_net',
11568 
              'data_out_x8' => 'from_register18_data_out_net',
11569 
              'data_out_x9' => 'from_register19_data_out_net',
11570 
              'debug_in_1i' => 'debug_in_1i_net',
11571 
              'debug_in_2i' => 'debug_in_2i_net',
11572 
              'debug_in_3i' => 'debug_in_3i_net',
11573 
              'debug_in_4i' => 'debug_in_4i_net',
11574 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
11575 
              'dma_host2board_done' => 'dma_host2board_done_net',
11576 
              'en' => 'constant5_op_net_x0',
11577 
              'en_x0' => 'constant5_op_net_x1',
11578 
              'en_x1' => 'constant5_op_net_x2',
11579 
              'en_x10' => 'constant5_op_net_x11',
11580 
              'en_x11' => 'constant5_op_net_x12',
11581 
              'en_x12' => 'constant1_op_net_x0',
11582 
              'en_x13' => 'constant1_op_net_x1',
11583 
              'en_x14' => 'constant1_op_net_x2',
11584 
              'en_x15' => 'constant1_op_net_x3',
11585 
              'en_x16' => 'constant1_op_net_x4',
11586 
              'en_x17' => 'constant1_op_net_x5',
11587 
              'en_x18' => 'constant1_op_net_x6',
11588 
              'en_x19' => 'constant1_op_net_x7',
11589 
              'en_x2' => 'constant5_op_net_x3',
11590 
              'en_x20' => 'constant1_op_net_x8',
11591 
              'en_x21' => 'constant5_op_net_x13',
11592 
              'en_x22' => 'constant1_op_net_x9',
11593 
              'en_x23' => 'constant1_op_net_x10',
11594 
              'en_x24' => 'constant1_op_net_x11',
11595 
              'en_x25' => 'constant1_op_net_x12',
11596 
              'en_x26' => 'constant1_op_net_x13',
11597 
              'en_x27' => 'constant5_op_net_x14',
11598 
              'en_x28' => 'constant5_op_net_x15',
11599 
              'en_x29' => 'constant5_op_net_x16',
11600 
              'en_x3' => 'constant5_op_net_x4',
11601 
              'en_x30' => 'constant5_op_net_x17',
11602 
              'en_x31' => 'constant5_op_net_x18',
11603 
              'en_x32' => 'constant5_op_net_x19',
11604 
              'en_x4' => 'constant5_op_net_x5',
11605 
              'en_x5' => 'constant5_op_net_x6',
11606 
              'en_x6' => 'constant5_op_net_x7',
11607 
              'en_x7' => 'constant5_op_net_x8',
11608 
              'en_x8' => 'constant5_op_net_x9',
11609 
              'en_x9' => 'constant5_op_net_x10',
11610 
              'reg01_rd' => 'from_register3_data_out_net_x0',
11611 
              'reg01_rv' => 'from_register1_data_out_net_x0',
11612 
              'reg01_td' => 'reg01_td_net',
11613 
              'reg01_tv' => 'reg01_tv_net',
11614 
              'reg02_rd' => 'from_register5_data_out_net_x0',
11615 
              'reg02_rv' => 'from_register2_data_out_net_x0',
11616 
              'reg02_td' => 'reg02_td_net',
11617 
              'reg02_tv' => 'reg02_tv_net',
11618 
              'reg03_rd' => 'from_register7_data_out_net_x0',
11619 
              'reg03_rv' => 'from_register6_data_out_net_x0',
11620 
              'reg03_td' => 'reg03_td_net',
11621 
              'reg03_tv' => 'reg03_tv_net',
11622 
              'reg04_rd' => 'from_register8_data_out_net_x0',
11623 
              'reg04_rv' => 'from_register4_data_out_net_x0',
11624 
              'reg04_td' => 'reg04_td_net',
11625 
              'reg04_tv' => 'reg04_tv_net',
11626 
              'reg05_rd' => 'from_register10_data_out_net_x0',
11627 
              'reg05_rv' => 'from_register9_data_out_net_x0',
11628 
              'reg05_td' => 'reg05_td_net',
11629 
              'reg05_tv' => 'reg05_tv_net',
11630 
              'reg06_rd' => 'from_register11_data_out_net_x0',
11631 
              'reg06_rv' => 'from_register12_data_out_net_x0',
11632 
              'reg06_td' => 'reg06_td_net',
11633 
              'reg06_tv' => 'reg06_tv_net',
11634 
              'reg07_rd' => 'from_register13_data_out_net_x0',
11635 
              'reg07_rv' => 'from_register14_data_out_net_x0',
11636 
              'reg07_td' => 'reg07_td_net',
11637 
              'reg07_tv' => 'reg07_tv_net',
11638 
              'reg08_rd' => 'from_register15_data_out_net_x0',
11639 
              'reg08_rv' => 'from_register16_data_out_net_x0',
11640 
              'reg08_td' => 'reg08_td_net',
11641 
              'reg08_tv' => 'reg08_tv_net',
11642 
              'reg09_rd' => 'from_register17_data_out_net_x0',
11643 
              'reg09_rv' => 'from_register18_data_out_net_x0',
11644 
              'reg09_td' => 'reg09_td_net',
11645 
              'reg09_tv' => 'reg09_tv_net',
11646 
              'reg10_rd' => 'from_register19_data_out_net_x0',
11647 
              'reg10_rv' => 'from_register20_data_out_net_x0',
11648 
              'reg10_td' => 'reg10_td_net',
11649 
              'reg10_tv' => 'reg10_tv_net',
11650 
              'reg11_rd' => 'from_register21_data_out_net_x0',
11651 
              'reg11_rv' => 'from_register22_data_out_net_x0',
11652 
              'reg11_td' => 'reg11_td_net',
11653 
              'reg11_tv' => 'reg11_tv_net',
11654 
              'reg12_rd' => 'from_register23_data_out_net_x0',
11655 
              'reg12_rv' => 'from_register24_data_out_net_x0',
11656 
              'reg12_td' => 'reg12_td_net',
11657 
              'reg12_tv' => 'reg12_tv_net',
11658 
              'reg13_rd' => 'from_register25_data_out_net_x0',
11659 
              'reg13_rv' => 'from_register26_data_out_net_x0',
11660 
              'reg13_td' => 'reg13_td_net',
11661 
              'reg13_tv' => 'reg13_tv_net',
11662 
              'reg14_rd' => 'from_register27_data_out_net_x0',
11663 
              'reg14_rv' => 'from_register28_data_out_net_x0',
11664 
              'reg14_td' => 'reg14_td_net',
11665 
              'reg14_tv' => 'reg14_tv_net',
11666 
            },
11667 
            'entity' => {
11668 
              'attributes' => {
11669 
                'entityAlreadyNetlisted' => 1,
11670 
                'hdlKind' => 'vhdl',
11671 
                'isDesign' => 1,
11672 
                'simulinkName' => 'INOUT_LOGIC',
11673 
              },
11674 
              'entityName' => 'inout_logic',
11675 
              'ports' => {
11676 
                'data_in' => {
11677 
                  'attributes' => {
11678 
                    'bin_pt' => 0,
11679 
                    'is_floating_block' => 1,
11680 
                    'must_be_hdl_vector' => 1,
11681 
                    'period' => 1,
11682 
                    'port_id' => 0,
11683 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11684 
                    'type' => 'UFix_32_0',
11685 
                  },
11686 
                  'direction' => 'out',
11687 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11688 
                  'width' => 32,
11689 
                },
11690 
                'data_in_x0' => {
11691 
                  'attributes' => {
11692 
                    'bin_pt' => 0,
11693 
                    'is_floating_block' => 1,
11694 
                    'must_be_hdl_vector' => 1,
11695 
                    'period' => 1,
11696 
                    'port_id' => 0,
11697 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11698 
                    'type' => 'Bool',
11699 
                  },
11700 
                  'direction' => 'out',
11701 
                  'hdlType' => 'std_logic',
11702 
                  'width' => 1,
11703 
                },
11704 
                'data_in_x1' => {
11705 
                  'attributes' => {
11706 
                    'bin_pt' => 0,
11707 
                    'is_floating_block' => 1,
11708 
                    'must_be_hdl_vector' => 1,
11709 
                    'period' => 1,
11710 
                    'port_id' => 0,
11711 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11712 
                    'type' => 'UFix_32_0',
11713 
                  },
11714 
                  'direction' => 'out',
11715 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11716 
                  'width' => 32,
11717 
                },
11718 
                'data_in_x10' => {
11719 
                  'attributes' => {
11720 
                    'bin_pt' => 0,
11721 
                    'is_floating_block' => 1,
11722 
                    'must_be_hdl_vector' => 1,
11723 
                    'period' => 1,
11724 
                    'port_id' => 0,
11725 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11726 
                    'type' => 'UFix_32_0',
11727 
                  },
11728 
                  'direction' => 'out',
11729 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11730 
                  'width' => 32,
11731 
                },
11732 
                'data_in_x11' => {
11733 
                  'attributes' => {
11734 
                    'bin_pt' => 0,
11735 
                    'is_floating_block' => 1,
11736 
                    'must_be_hdl_vector' => 1,
11737 
                    'period' => 1,
11738 
                    'port_id' => 0,
11739 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11740 
                    'type' => 'UFix_32_0',
11741 
                  },
11742 
                  'direction' => 'out',
11743 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11744 
                  'width' => 32,
11745 
                },
11746 
                'data_in_x12' => {
11747 
                  'attributes' => {
11748 
                    'bin_pt' => 0,
11749 
                    'is_floating_block' => 1,
11750 
                    'must_be_hdl_vector' => 1,
11751 
                    'period' => 1,
11752 
                    'port_id' => 0,
11753 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11754 
                    'type' => 'Bool',
11755 
                  },
11756 
                  'direction' => 'out',
11757 
                  'hdlType' => 'std_logic',
11758 
                  'width' => 1,
11759 
                },
11760 
                'data_in_x13' => {
11761 
                  'attributes' => {
11762 
                    'bin_pt' => 0,
11763 
                    'is_floating_block' => 1,
11764 
                    'must_be_hdl_vector' => 1,
11765 
                    'period' => 1,
11766 
                    'port_id' => 0,
11767 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11768 
                    'type' => 'UFix_32_0',
11769 
                  },
11770 
                  'direction' => 'out',
11771 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11772 
                  'width' => 32,
11773 
                },
11774 
                'data_in_x14' => {
11775 
                  'attributes' => {
11776 
                    'bin_pt' => 0,
11777 
                    'is_floating_block' => 1,
11778 
                    'must_be_hdl_vector' => 1,
11779 
                    'period' => 1,
11780 
                    'port_id' => 0,
11781 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11782 
                    'type' => 'Bool',
11783 
                  },
11784 
                  'direction' => 'out',
11785 
                  'hdlType' => 'std_logic',
11786 
                  'width' => 1,
11787 
                },
11788 
                'data_in_x15' => {
11789 
                  'attributes' => {
11790 
                    'bin_pt' => 0,
11791 
                    'is_floating_block' => 1,
11792 
                    'must_be_hdl_vector' => 1,
11793 
                    'period' => 1,
11794 
                    'port_id' => 0,
11795 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11796 
                    'type' => 'UFix_32_0',
11797 
                  },
11798 
                  'direction' => 'out',
11799 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11800 
                  'width' => 32,
11801 
                },
11802 
                'data_in_x16' => {
11803 
                  'attributes' => {
11804 
                    'bin_pt' => 0,
11805 
                    'is_floating_block' => 1,
11806 
                    'must_be_hdl_vector' => 1,
11807 
                    'period' => 1,
11808 
                    'port_id' => 0,
11809 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11810 
                    'type' => 'Bool',
11811 
                  },
11812 
                  'direction' => 'out',
11813 
                  'hdlType' => 'std_logic',
11814 
                  'width' => 1,
11815 
                },
11816 
                'data_in_x17' => {
11817 
                  'attributes' => {
11818 
                    'bin_pt' => 0,
11819 
                    'is_floating_block' => 1,
11820 
                    'must_be_hdl_vector' => 1,
11821 
                    'period' => 1,
11822 
                    'port_id' => 0,
11823 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11824 
                    'type' => 'UFix_32_0',
11825 
                  },
11826 
                  'direction' => 'out',
11827 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11828 
                  'width' => 32,
11829 
                },
11830 
                'data_in_x18' => {
11831 
                  'attributes' => {
11832 
                    'bin_pt' => 0,
11833 
                    'is_floating_block' => 1,
11834 
                    'must_be_hdl_vector' => 1,
11835 
                    'period' => 1,
11836 
                    'port_id' => 0,
11837 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11838 
                    'type' => 'Bool',
11839 
                  },
11840 
                  'direction' => 'out',
11841 
                  'hdlType' => 'std_logic',
11842 
                  'width' => 1,
11843 
                },
11844 
                'data_in_x19' => {
11845 
                  'attributes' => {
11846 
                    'bin_pt' => 0,
11847 
                    'is_floating_block' => 1,
11848 
                    'must_be_hdl_vector' => 1,
11849 
                    'period' => 1,
11850 
                    'port_id' => 0,
11851 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11852 
                    'type' => 'UFix_32_0',
11853 
                  },
11854 
                  'direction' => 'out',
11855 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11856 
                  'width' => 32,
11857 
                },
11858 
                'data_in_x2' => {
11859 
                  'attributes' => {
11860 
                    'bin_pt' => 0,
11861 
                    'is_floating_block' => 1,
11862 
                    'must_be_hdl_vector' => 1,
11863 
                    'period' => 1,
11864 
                    'port_id' => 0,
11865 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11866 
                    'type' => 'Bool',
11867 
                  },
11868 
                  'direction' => 'out',
11869 
                  'hdlType' => 'std_logic',
11870 
                  'width' => 1,
11871 
                },
11872 
                'data_in_x20' => {
11873 
                  'attributes' => {
11874 
                    'bin_pt' => 0,
11875 
                    'is_floating_block' => 1,
11876 
                    'must_be_hdl_vector' => 1,
11877 
                    'period' => 1,
11878 
                    'port_id' => 0,
11879 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11880 
                    'type' => 'Bool',
11881 
                  },
11882 
                  'direction' => 'out',
11883 
                  'hdlType' => 'std_logic',
11884 
                  'width' => 1,
11885 
                },
11886 
                'data_in_x21' => {
11887 
                  'attributes' => {
11888 
                    'bin_pt' => 0,
11889 
                    'is_floating_block' => 1,
11890 
                    'must_be_hdl_vector' => 1,
11891 
                    'period' => 1,
11892 
                    'port_id' => 0,
11893 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11894 
                    'type' => 'Bool',
11895 
                  },
11896 
                  'direction' => 'out',
11897 
                  'hdlType' => 'std_logic',
11898 
                  'width' => 1,
11899 
                },
11900 
                'data_in_x22' => {
11901 
                  'attributes' => {
11902 
                    'bin_pt' => 0,
11903 
                    'is_floating_block' => 1,
11904 
                    'must_be_hdl_vector' => 1,
11905 
                    'period' => 1,
11906 
                    'port_id' => 0,
11907 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11908 
                    'type' => 'UFix_32_0',
11909 
                  },
11910 
                  'direction' => 'out',
11911 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11912 
                  'width' => 32,
11913 
                },
11914 
                'data_in_x23' => {
11915 
                  'attributes' => {
11916 
                    'bin_pt' => 0,
11917 
                    'is_floating_block' => 1,
11918 
                    'must_be_hdl_vector' => 1,
11919 
                    'period' => 1,
11920 
                    'port_id' => 0,
11921 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11922 
                    'type' => 'Bool',
11923 
                  },
11924 
                  'direction' => 'out',
11925 
                  'hdlType' => 'std_logic',
11926 
                  'width' => 1,
11927 
                },
11928 
                'data_in_x24' => {
11929 
                  'attributes' => {
11930 
                    'bin_pt' => 0,
11931 
                    'is_floating_block' => 1,
11932 
                    'must_be_hdl_vector' => 1,
11933 
                    'period' => 1,
11934 
                    'port_id' => 0,
11935 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11936 
                    'type' => 'UFix_32_0',
11937 
                  },
11938 
                  'direction' => 'out',
11939 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11940 
                  'width' => 32,
11941 
                },
11942 
                'data_in_x25' => {
11943 
                  'attributes' => {
11944 
                    'bin_pt' => 0,
11945 
                    'is_floating_block' => 1,
11946 
                    'must_be_hdl_vector' => 1,
11947 
                    'period' => 1,
11948 
                    'port_id' => 0,
11949 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11950 
                    'type' => 'Bool',
11951 
                  },
11952 
                  'direction' => 'out',
11953 
                  'hdlType' => 'std_logic',
11954 
                  'width' => 1,
11955 
                },
11956 
                'data_in_x26' => {
11957 
                  'attributes' => {
11958 
                    'bin_pt' => 0,
11959 
                    'is_floating_block' => 1,
11960 
                    'must_be_hdl_vector' => 1,
11961 
                    'period' => 1,
11962 
                    'port_id' => 0,
11963 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11964 
                    'type' => 'UFix_32_0',
11965 
                  },
11966 
                  'direction' => 'out',
11967 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11968 
                  'width' => 32,
11969 
                },
11970 
                'data_in_x27' => {
11971 
                  'attributes' => {
11972 
                    'bin_pt' => 0,
11973 
                    'is_floating_block' => 1,
11974 
                    'must_be_hdl_vector' => 1,
11975 
                    'period' => 1,
11976 
                    'port_id' => 0,
11977 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11978 
                    'type' => 'Bool',
11979 
                  },
11980 
                  'direction' => 'out',
11981 
                  'hdlType' => 'std_logic',
11982 
                  'width' => 1,
11983 
                },
11984 
                'data_in_x28' => {
11985 
                  'attributes' => {
11986 
                    'bin_pt' => 0,
11987 
                    'is_floating_block' => 1,
11988 
                    'must_be_hdl_vector' => 1,
11989 
                    'period' => 1,
11990 
                    'port_id' => 0,
11991 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11992 
                    'type' => 'UFix_32_0',
11993 
                  },
11994 
                  'direction' => 'out',
11995 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11996 
                  'width' => 32,
11997 
                },
11998 
                'data_in_x29' => {
11999 
                  'attributes' => {
12000 
                    'bin_pt' => 0,
12001 
                    'is_floating_block' => 1,
12002 
                    'must_be_hdl_vector' => 1,
12003 
                    'period' => 1,
12004 
                    'port_id' => 0,
12005 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12006 
                    'type' => 'UFix_32_0',
12007 
                  },
12008 
                  'direction' => 'out',
12009 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12010 
                  'width' => 32,
12011 
                },
12012 
                'data_in_x3' => {
12013 
                  'attributes' => {
12014 
                    'bin_pt' => 0,
12015 
                    'is_floating_block' => 1,
12016 
                    'must_be_hdl_vector' => 1,
12017 
                    'period' => 1,
12018 
                    'port_id' => 0,
12019 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12020 
                    'type' => 'UFix_32_0',
12021 
                  },
12022 
                  'direction' => 'out',
12023 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12024 
                  'width' => 32,
12025 
                },
12026 
                'data_in_x30' => {
12027 
                  'attributes' => {
12028 
                    'bin_pt' => 0,
12029 
                    'is_floating_block' => 1,
12030 
                    'must_be_hdl_vector' => 1,
12031 
                    'period' => 1,
12032 
                    'port_id' => 0,
12033 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12034 
                    'type' => 'UFix_32_0',
12035 
                  },
12036 
                  'direction' => 'out',
12037 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12038 
                  'width' => 32,
12039 
                },
12040 
                'data_in_x31' => {
12041 
                  'attributes' => {
12042 
                    'bin_pt' => 0,
12043 
                    'is_floating_block' => 1,
12044 
                    'must_be_hdl_vector' => 1,
12045 
                    'period' => 1,
12046 
                    'port_id' => 0,
12047 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12048 
                    'type' => 'Bool',
12049 
                  },
12050 
                  'direction' => 'out',
12051 
                  'hdlType' => 'std_logic',
12052 
                  'width' => 1,
12053 
                },
12054 
                'data_in_x32' => {
12055 
                  'attributes' => {
12056 
                    'bin_pt' => 0,
12057 
                    'is_floating_block' => 1,
12058 
                    'must_be_hdl_vector' => 1,
12059 
                    'period' => 1,
12060 
                    'port_id' => 0,
12061 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12062 
                    'type' => 'UFix_32_0',
12063 
                  },
12064 
                  'direction' => 'out',
12065 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12066 
                  'width' => 32,
12067 
                },
12068 
                'data_in_x4' => {
12069 
                  'attributes' => {
12070 
                    'bin_pt' => 0,
12071 
                    'is_floating_block' => 1,
12072 
                    'must_be_hdl_vector' => 1,
12073 
                    'period' => 1,
12074 
                    'port_id' => 0,
12075 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12076 
                    'type' => 'Bool',
12077 
                  },
12078 
                  'direction' => 'out',
12079 
                  'hdlType' => 'std_logic',
12080 
                  'width' => 1,
12081 
                },
12082 
                'data_in_x5' => {
12083 
                  'attributes' => {
12084 
                    'bin_pt' => 0,
12085 
                    'is_floating_block' => 1,
12086 
                    'must_be_hdl_vector' => 1,
12087 
                    'period' => 1,
12088 
                    'port_id' => 0,
12089 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12090 
                    'type' => 'UFix_32_0',
12091 
                  },
12092 
                  'direction' => 'out',
12093 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12094 
                  'width' => 32,
12095 
                },
12096 
                'data_in_x6' => {
12097 
                  'attributes' => {
12098 
                    'bin_pt' => 0,
12099 
                    'is_floating_block' => 1,
12100 
                    'must_be_hdl_vector' => 1,
12101 
                    'period' => 1,
12102 
                    'port_id' => 0,
12103 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12104 
                    'type' => 'Bool',
12105 
                  },
12106 
                  'direction' => 'out',
12107 
                  'hdlType' => 'std_logic',
12108 
                  'width' => 1,
12109 
                },
12110 
                'data_in_x7' => {
12111 
                  'attributes' => {
12112 
                    'bin_pt' => 0,
12113 
                    'is_floating_block' => 1,
12114 
                    'must_be_hdl_vector' => 1,
12115 
                    'period' => 1,
12116 
                    'port_id' => 0,
12117 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12118 
                    'type' => 'UFix_32_0',
12119 
                  },
12120 
                  'direction' => 'out',
12121 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12122 
                  'width' => 32,
12123 
                },
12124 
                'data_in_x8' => {
12125 
                  'attributes' => {
12126 
                    'bin_pt' => 0,
12127 
                    'is_floating_block' => 1,
12128 
                    'must_be_hdl_vector' => 1,
12129 
                    'period' => 1,
12130 
                    'port_id' => 0,
12131 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12132 
                    'type' => 'UFix_1_0',
12133 
                  },
12134 
                  'direction' => 'out',
12135 
                  'hdlType' => 'std_logic',
12136 
                  'width' => 1,
12137 
                },
12138 
                'data_in_x9' => {
12139 
                  'attributes' => {
12140 
                    'bin_pt' => 0,
12141 
                    'is_floating_block' => 1,
12142 
                    'must_be_hdl_vector' => 1,
12143 
                    'period' => 1,
12144 
                    'port_id' => 0,
12145 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12146 
                    'type' => 'UFix_1_0',
12147 
                  },
12148 
                  'direction' => 'out',
12149 
                  'hdlType' => 'std_logic',
12150 
                  'width' => 1,
12151 
                },
12152 
                'data_out' => {
12153 
                  'attributes' => {
12154 
                    'bin_pt' => 0,
12155 
                    'is_floating_block' => 1,
12156 
                    'must_be_hdl_vector' => 1,
12157 
                    'period' => 1,
12158 
                    'port_id' => 0,
12159 
                    'simulinkName' => 'INOUT_LOGIC/From Register1',
12160 
                    'type' => 'UFix_1_0',
12161 
                  },
12162 
                  'direction' => 'in',
12163 
                  'hdlType' => 'std_logic',
12164 
                  'width' => 1,
12165 
                },
12166 
                'data_out_x0' => {
12167 
                  'attributes' => {
12168 
                    'bin_pt' => 0,
12169 
                    'is_floating_block' => 1,
12170 
                    'must_be_hdl_vector' => 1,
12171 
                    'period' => 1,
12172 
                    'port_id' => 0,
12173 
                    'simulinkName' => 'INOUT_LOGIC/From Register10',
12174 
                    'type' => 'UFix_32_0',
12175 
                  },
12176 
                  'direction' => 'in',
12177 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12178 
                  'width' => 32,
12179 
                },
12180 
                'data_out_x1' => {
12181 
                  'attributes' => {
12182 
                    'bin_pt' => 0,
12183 
                    'is_floating_block' => 1,
12184 
                    'must_be_hdl_vector' => 1,
12185 
                    'period' => 1,
12186 
                    'port_id' => 0,
12187 
                    'simulinkName' => 'INOUT_LOGIC/From Register11',
12188 
                    'type' => 'UFix_32_0',
12189 
                  },
12190 
                  'direction' => 'in',
12191 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12192 
                  'width' => 32,
12193 
                },
12194 
                'data_out_x10' => {
12195 
                  'attributes' => {
12196 
                    'bin_pt' => 0,
12197 
                    'is_floating_block' => 1,
12198 
                    'must_be_hdl_vector' => 1,
12199 
                    'period' => 1,
12200 
                    'port_id' => 0,
12201 
                    'simulinkName' => 'INOUT_LOGIC/From Register2',
12202 
                    'type' => 'UFix_1_0',
12203 
                  },
12204 
                  'direction' => 'in',
12205 
                  'hdlType' => 'std_logic',
12206 
                  'width' => 1,
12207 
                },
12208 
                'data_out_x11' => {
12209 
                  'attributes' => {
12210 
                    'bin_pt' => 0,
12211 
                    'is_floating_block' => 1,
12212 
                    'must_be_hdl_vector' => 1,
12213 
                    'period' => 1,
12214 
                    'port_id' => 0,
12215 
                    'simulinkName' => 'INOUT_LOGIC/From Register20',
12216 
                    'type' => 'UFix_1_0',
12217 
                  },
12218 
                  'direction' => 'in',
12219 
                  'hdlType' => 'std_logic',
12220 
                  'width' => 1,
12221 
                },
12222 
                'data_out_x12' => {
12223 
                  'attributes' => {
12224 
                    'bin_pt' => 0,
12225 
                    'is_floating_block' => 1,
12226 
                    'must_be_hdl_vector' => 1,
12227 
                    'period' => 1,
12228 
                    'port_id' => 0,
12229 
                    'simulinkName' => 'INOUT_LOGIC/From Register21',
12230 
                    'type' => 'UFix_32_0',
12231 
                  },
12232 
                  'direction' => 'in',
12233 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12234 
                  'width' => 32,
12235 
                },
12236 
                'data_out_x13' => {
12237 
                  'attributes' => {
12238 
                    'bin_pt' => 0,
12239 
                    'is_floating_block' => 1,
12240 
                    'must_be_hdl_vector' => 1,
12241 
                    'period' => 1,
12242 
                    'port_id' => 0,
12243 
                    'simulinkName' => 'INOUT_LOGIC/From Register22',
12244 
                    'type' => 'UFix_1_0',
12245 
                  },
12246 
                  'direction' => 'in',
12247 
                  'hdlType' => 'std_logic',
12248 
                  'width' => 1,
12249 
                },
12250 
                'data_out_x14' => {
12251 
                  'attributes' => {
12252 
                    'bin_pt' => 0,
12253 
                    'is_floating_block' => 1,
12254 
                    'must_be_hdl_vector' => 1,
12255 
                    'period' => 1,
12256 
                    'port_id' => 0,
12257 
                    'simulinkName' => 'INOUT_LOGIC/From Register23',
12258 
                    'type' => 'UFix_32_0',
12259 
                  },
12260 
                  'direction' => 'in',
12261 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12262 
                  'width' => 32,
12263 
                },
12264 
                'data_out_x15' => {
12265 
                  'attributes' => {
12266 
                    'bin_pt' => 0,
12267 
                    'is_floating_block' => 1,
12268 
                    'must_be_hdl_vector' => 1,
12269 
                    'period' => 1,
12270 
                    'port_id' => 0,
12271 
                    'simulinkName' => 'INOUT_LOGIC/From Register24',
12272 
                    'type' => 'UFix_1_0',
12273 
                  },
12274 
                  'direction' => 'in',
12275 
                  'hdlType' => 'std_logic',
12276 
                  'width' => 1,
12277 
                },
12278 
                'data_out_x16' => {
12279 
                  'attributes' => {
12280 
                    'bin_pt' => 0,
12281 
                    'is_floating_block' => 1,
12282 
                    'must_be_hdl_vector' => 1,
12283 
                    'period' => 1,
12284 
                    'port_id' => 0,
12285 
                    'simulinkName' => 'INOUT_LOGIC/From Register25',
12286 
                    'type' => 'UFix_32_0',
12287 
                  },
12288 
                  'direction' => 'in',
12289 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12290 
                  'width' => 32,
12291 
                },
12292 
                'data_out_x17' => {
12293 
                  'attributes' => {
12294 
                    'bin_pt' => 0,
12295 
                    'is_floating_block' => 1,
12296 
                    'must_be_hdl_vector' => 1,
12297 
                    'period' => 1,
12298 
                    'port_id' => 0,
12299 
                    'simulinkName' => 'INOUT_LOGIC/From Register26',
12300 
                    'type' => 'UFix_1_0',
12301 
                  },
12302 
                  'direction' => 'in',
12303 
                  'hdlType' => 'std_logic',
12304 
                  'width' => 1,
12305 
                },
12306 
                'data_out_x18' => {
12307 
                  'attributes' => {
12308 
                    'bin_pt' => 0,
12309 
                    'is_floating_block' => 1,
12310 
                    'must_be_hdl_vector' => 1,
12311 
                    'period' => 1,
12312 
                    'port_id' => 0,
12313 
                    'simulinkName' => 'INOUT_LOGIC/From Register27',
12314 
                    'type' => 'UFix_32_0',
12315 
                  },
12316 
                  'direction' => 'in',
12317 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12318 
                  'width' => 32,
12319 
                },
12320 
                'data_out_x19' => {
12321 
                  'attributes' => {
12322 
                    'bin_pt' => 0,
12323 
                    'is_floating_block' => 1,
12324 
                    'must_be_hdl_vector' => 1,
12325 
                    'period' => 1,
12326 
                    'port_id' => 0,
12327 
                    'simulinkName' => 'INOUT_LOGIC/From Register28',
12328 
                    'type' => 'UFix_1_0',
12329 
                  },
12330 
                  'direction' => 'in',
12331 
                  'hdlType' => 'std_logic',
12332 
                  'width' => 1,
12333 
                },
12334 
                'data_out_x2' => {
12335 
                  'attributes' => {
12336 
                    'bin_pt' => 0,
12337 
                    'is_floating_block' => 1,
12338 
                    'must_be_hdl_vector' => 1,
12339 
                    'period' => 1,
12340 
                    'port_id' => 0,
12341 
                    'simulinkName' => 'INOUT_LOGIC/From Register12',
12342 
                    'type' => 'UFix_1_0',
12343 
                  },
12344 
                  'direction' => 'in',
12345 
                  'hdlType' => 'std_logic',
12346 
                  'width' => 1,
12347 
                },
12348 
                'data_out_x20' => {
12349 
                  'attributes' => {
12350 
                    'bin_pt' => 0,
12351 
                    'is_floating_block' => 1,
12352 
                    'must_be_hdl_vector' => 1,
12353 
                    'period' => 1,
12354 
                    'port_id' => 0,
12355 
                    'simulinkName' => 'INOUT_LOGIC/From Register3',
12356 
                    'type' => 'UFix_32_0',
12357 
                  },
12358 
                  'direction' => 'in',
12359 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12360 
                  'width' => 32,
12361 
                },
12362 
                'data_out_x21' => {
12363 
                  'attributes' => {
12364 
                    'bin_pt' => 0,
12365 
                    'is_floating_block' => 1,
12366 
                    'must_be_hdl_vector' => 1,
12367 
                    'period' => 1,
12368 
                    'port_id' => 0,
12369 
                    'simulinkName' => 'INOUT_LOGIC/From Register4',
12370 
                    'type' => 'UFix_1_0',
12371 
                  },
12372 
                  'direction' => 'in',
12373 
                  'hdlType' => 'std_logic',
12374 
                  'width' => 1,
12375 
                },
12376 
                'data_out_x22' => {
12377 
                  'attributes' => {
12378 
                    'bin_pt' => 0,
12379 
                    'is_floating_block' => 1,
12380 
                    'must_be_hdl_vector' => 1,
12381 
                    'period' => 1,
12382 
                    'port_id' => 0,
12383 
                    'simulinkName' => 'INOUT_LOGIC/From Register5',
12384 
                    'type' => 'UFix_32_0',
12385 
                  },
12386 
                  'direction' => 'in',
12387 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12388 
                  'width' => 32,
12389 
                },
12390 
                'data_out_x23' => {
12391 
                  'attributes' => {
12392 
                    'bin_pt' => 0,
12393 
                    'is_floating_block' => 1,
12394 
                    'must_be_hdl_vector' => 1,
12395 
                    'period' => 1,
12396 
                    'port_id' => 0,
12397 
                    'simulinkName' => 'INOUT_LOGIC/From Register6',
12398 
                    'type' => 'UFix_1_0',
12399 
                  },
12400 
                  'direction' => 'in',
12401 
                  'hdlType' => 'std_logic',
12402 
                  'width' => 1,
12403 
                },
12404 
                'data_out_x24' => {
12405 
                  'attributes' => {
12406 
                    'bin_pt' => 0,
12407 
                    'is_floating_block' => 1,
12408 
                    'must_be_hdl_vector' => 1,
12409 
                    'period' => 1,
12410 
                    'port_id' => 0,
12411 
                    'simulinkName' => 'INOUT_LOGIC/From Register7',
12412 
                    'type' => 'UFix_32_0',
12413 
                  },
12414 
                  'direction' => 'in',
12415 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12416 
                  'width' => 32,
12417 
                },
12418 
                'data_out_x25' => {
12419 
                  'attributes' => {
12420 
                    'bin_pt' => 0,
12421 
                    'is_floating_block' => 1,
12422 
                    'must_be_hdl_vector' => 1,
12423 
                    'period' => 1,
12424 
                    'port_id' => 0,
12425 
                    'simulinkName' => 'INOUT_LOGIC/From Register8',
12426 
                    'type' => 'UFix_32_0',
12427 
                  },
12428 
                  'direction' => 'in',
12429 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12430 
                  'width' => 32,
12431 
                },
12432 
                'data_out_x26' => {
12433 
                  'attributes' => {
12434 
                    'bin_pt' => 0,
12435 
                    'is_floating_block' => 1,
12436 
                    'must_be_hdl_vector' => 1,
12437 
                    'period' => 1,
12438 
                    'port_id' => 0,
12439 
                    'simulinkName' => 'INOUT_LOGIC/From Register9',
12440 
                    'type' => 'UFix_1_0',
12441 
                  },
12442 
                  'direction' => 'in',
12443 
                  'hdlType' => 'std_logic',
12444 
                  'width' => 1,
12445 
                },
12446 
                'data_out_x3' => {
12447 
                  'attributes' => {
12448 
                    'bin_pt' => 0,
12449 
                    'is_floating_block' => 1,
12450 
                    'must_be_hdl_vector' => 1,
12451 
                    'period' => 1,
12452 
                    'port_id' => 0,
12453 
                    'simulinkName' => 'INOUT_LOGIC/From Register13',
12454 
                    'type' => 'UFix_32_0',
12455 
                  },
12456 
                  'direction' => 'in',
12457 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12458 
                  'width' => 32,
12459 
                },
12460 
                'data_out_x4' => {
12461 
                  'attributes' => {
12462 
                    'bin_pt' => 0,
12463 
                    'is_floating_block' => 1,
12464 
                    'must_be_hdl_vector' => 1,
12465 
                    'period' => 1,
12466 
                    'port_id' => 0,
12467 
                    'simulinkName' => 'INOUT_LOGIC/From Register14',
12468 
                    'type' => 'UFix_1_0',
12469 
                  },
12470 
                  'direction' => 'in',
12471 
                  'hdlType' => 'std_logic',
12472 
                  'width' => 1,
12473 
                },
12474 
                'data_out_x5' => {
12475 
                  'attributes' => {
12476 
                    'bin_pt' => 0,
12477 
                    'is_floating_block' => 1,
12478 
                    'must_be_hdl_vector' => 1,
12479 
                    'period' => 1,
12480 
                    'port_id' => 0,
12481 
                    'simulinkName' => 'INOUT_LOGIC/From Register15',
12482 
                    'type' => 'UFix_32_0',
12483 
                  },
12484 
                  'direction' => 'in',
12485 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12486 
                  'width' => 32,
12487 
                },
12488 
                'data_out_x6' => {
12489 
                  'attributes' => {
12490 
                    'bin_pt' => 0,
12491 
                    'is_floating_block' => 1,
12492 
                    'must_be_hdl_vector' => 1,
12493 
                    'period' => 1,
12494 
                    'port_id' => 0,
12495 
                    'simulinkName' => 'INOUT_LOGIC/From Register16',
12496 
                    'type' => 'UFix_1_0',
12497 
                  },
12498 
                  'direction' => 'in',
12499 
                  'hdlType' => 'std_logic',
12500 
                  'width' => 1,
12501 
                },
12502 
                'data_out_x7' => {
12503 
                  'attributes' => {
12504 
                    'bin_pt' => 0,
12505 
                    'is_floating_block' => 1,
12506 
                    'must_be_hdl_vector' => 1,
12507 
                    'period' => 1,
12508 
                    'port_id' => 0,
12509 
                    'simulinkName' => 'INOUT_LOGIC/From Register17',
12510 
                    'type' => 'UFix_32_0',
12511 
                  },
12512 
                  'direction' => 'in',
12513 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12514 
                  'width' => 32,
12515 
                },
12516 
                'data_out_x8' => {
12517 
                  'attributes' => {
12518 
                    'bin_pt' => 0,
12519 
                    'is_floating_block' => 1,
12520 
                    'must_be_hdl_vector' => 1,
12521 
                    'period' => 1,
12522 
                    'port_id' => 0,
12523 
                    'simulinkName' => 'INOUT_LOGIC/From Register18',
12524 
                    'type' => 'UFix_1_0',
12525 
                  },
12526 
                  'direction' => 'in',
12527 
                  'hdlType' => 'std_logic',
12528 
                  'width' => 1,
12529 
                },
12530 
                'data_out_x9' => {
12531 
                  'attributes' => {
12532 
                    'bin_pt' => 0,
12533 
                    'is_floating_block' => 1,
12534 
                    'must_be_hdl_vector' => 1,
12535 
                    'period' => 1,
12536 
                    'port_id' => 0,
12537 
                    'simulinkName' => 'INOUT_LOGIC/From Register19',
12538 
                    'type' => 'UFix_32_0',
12539 
                  },
12540 
                  'direction' => 'in',
12541 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12542 
                  'width' => 32,
12543 
                },
12544 
                'debug_in_1i' => {
12545 
                  'attributes' => {
12546 
                    'bin_pt' => 0,
12547 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
12548 
                    'is_floating_block' => 1,
12549 
                    'is_gateway_port' => 1,
12550 
                    'must_be_hdl_vector' => 1,
12551 
                    'period' => 1,
12552 
                    'port_id' => 0,
12553 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_1i',
12554 
                    'source_block' => 'INOUT_LOGIC',
12555 
                    'timingConstraint' => 'none',
12556 
                    'type' => 'UFix_32_0',
12557 
                  },
12558 
                  'direction' => 'in',
12559 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12560 
                  'width' => 32,
12561 
                },
12562 
                'debug_in_2i' => {
12563 
                  'attributes' => {
12564 
                    'bin_pt' => 0,
12565 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
12566 
                    'is_floating_block' => 1,
12567 
                    'is_gateway_port' => 1,
12568 
                    'must_be_hdl_vector' => 1,
12569 
                    'period' => 1,
12570 
                    'port_id' => 0,
12571 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_2i',
12572 
                    'source_block' => 'INOUT_LOGIC',
12573 
                    'timingConstraint' => 'none',
12574 
                    'type' => 'UFix_32_0',
12575 
                  },
12576 
                  'direction' => 'in',
12577 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12578 
                  'width' => 32,
12579 
                },
12580 
                'debug_in_3i' => {
12581 
                  'attributes' => {
12582 
                    'bin_pt' => 0,
12583 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
12584 
                    'is_floating_block' => 1,
12585 
                    'is_gateway_port' => 1,
12586 
                    'must_be_hdl_vector' => 1,
12587 
                    'period' => 1,
12588 
                    'port_id' => 0,
12589 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_3i',
12590 
                    'source_block' => 'INOUT_LOGIC',
12591 
                    'timingConstraint' => 'none',
12592 
                    'type' => 'UFix_32_0',
12593 
                  },
12594 
                  'direction' => 'in',
12595 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12596 
                  'width' => 32,
12597 
                },
12598 
                'debug_in_4i' => {
12599 
                  'attributes' => {
12600 
                    'bin_pt' => 0,
12601 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
12602 
                    'is_floating_block' => 1,
12603 
                    'is_gateway_port' => 1,
12604 
                    'must_be_hdl_vector' => 1,
12605 
                    'period' => 1,
12606 
                    'port_id' => 0,
12607 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_4i',
12608 
                    'source_block' => 'INOUT_LOGIC',
12609 
                    'timingConstraint' => 'none',
12610 
                    'type' => 'UFix_32_0',
12611 
                  },
12612 
                  'direction' => 'in',
12613 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12614 
                  'width' => 32,
12615 
                },
12616 
                'dma_host2board_busy' => {
12617 
                  'attributes' => {
12618 
                    'bin_pt' => 0,
12619 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
12620 
                    'is_floating_block' => 1,
12621 
                    'is_gateway_port' => 1,
12622 
                    'must_be_hdl_vector' => 1,
12623 
                    'period' => 1,
12624 
                    'port_id' => 0,
12625 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Busy',
12626 
                    'source_block' => 'INOUT_LOGIC',
12627 
                    'timingConstraint' => 'none',
12628 
                    'type' => 'UFix_1_0',
12629 
                  },
12630 
                  'direction' => 'in',
12631 
                  'hdlType' => 'std_logic',
12632 
                  'width' => 1,
12633 
                },
12634 
                'dma_host2board_done' => {
12635 
                  'attributes' => {
12636 
                    'bin_pt' => 0,
12637 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
12638 
                    'is_floating_block' => 1,
12639 
                    'is_gateway_port' => 1,
12640 
                    'must_be_hdl_vector' => 1,
12641 
                    'period' => 1,
12642 
                    'port_id' => 0,
12643 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Done',
12644 
                    'source_block' => 'INOUT_LOGIC',
12645 
                    'timingConstraint' => 'none',
12646 
                    'type' => 'UFix_1_0',
12647 
                  },
12648 
                  'direction' => 'in',
12649 
                  'hdlType' => 'std_logic',
12650 
                  'width' => 1,
12651 
                },
12652 
                'en' => {
12653 
                  'attributes' => {
12654 
                    'bin_pt' => 0,
12655 
                    'is_floating_block' => 1,
12656 
                    'must_be_hdl_vector' => 1,
12657 
                    'period' => 1,
12658 
                    'port_id' => 0,
12659 
                    'simulinkName' => 'INOUT_LOGIC/en',
12660 
                    'type' => 'Bool',
12661 
                  },
12662 
                  'direction' => 'out',
12663 
                  'hdlType' => 'std_logic',
12664 
                  'width' => 1,
12665 
                },
12666 
                'en_x0' => {
12667 
                  'attributes' => {
12668 
                    'bin_pt' => 0,
12669 
                    'is_floating_block' => 1,
12670 
                    'must_be_hdl_vector' => 1,
12671 
                    'period' => 1,
12672 
                    'port_id' => 0,
12673 
                    'simulinkName' => 'INOUT_LOGIC/en',
12674 
                    'type' => 'Bool',
12675 
                  },
12676 
                  'direction' => 'out',
12677 
                  'hdlType' => 'std_logic',
12678 
                  'width' => 1,
12679 
                },
12680 
                'en_x1' => {
12681 
                  'attributes' => {
12682 
                    'bin_pt' => 0,
12683 
                    'is_floating_block' => 1,
12684 
                    'must_be_hdl_vector' => 1,
12685 
                    'period' => 1,
12686 
                    'port_id' => 0,
12687 
                    'simulinkName' => 'INOUT_LOGIC/en',
12688 
                    'type' => 'Bool',
12689 
                  },
12690 
                  'direction' => 'out',
12691 
                  'hdlType' => 'std_logic',
12692 
                  'width' => 1,
12693 
                },
12694 
                'en_x10' => {
12695 
                  'attributes' => {
12696 
                    'bin_pt' => 0,
12697 
                    'is_floating_block' => 1,
12698 
                    'must_be_hdl_vector' => 1,
12699 
                    'period' => 1,
12700 
                    'port_id' => 0,
12701 
                    'simulinkName' => 'INOUT_LOGIC/en',
12702 
                    'type' => 'Bool',
12703 
                  },
12704 
                  'direction' => 'out',
12705 
                  'hdlType' => 'std_logic',
12706 
                  'width' => 1,
12707 
                },
12708 
                'en_x11' => {
12709 
                  'attributes' => {
12710 
                    'bin_pt' => 0,
12711 
                    'is_floating_block' => 1,
12712 
                    'must_be_hdl_vector' => 1,
12713 
                    'period' => 1,
12714 
                    'port_id' => 0,
12715 
                    'simulinkName' => 'INOUT_LOGIC/en',
12716 
                    'type' => 'Bool',
12717 
                  },
12718 
                  'direction' => 'out',
12719 
                  'hdlType' => 'std_logic',
12720 
                  'width' => 1,
12721 
                },
12722 
                'en_x12' => {
12723 
                  'attributes' => {
12724 
                    'bin_pt' => 0,
12725 
                    'is_floating_block' => 1,
12726 
                    'must_be_hdl_vector' => 1,
12727 
                    'period' => 1,
12728 
                    'port_id' => 0,
12729 
                    'simulinkName' => 'INOUT_LOGIC/en',
12730 
                    'type' => 'Bool',
12731 
                  },
12732 
                  'direction' => 'out',
12733 
                  'hdlType' => 'std_logic',
12734 
                  'width' => 1,
12735 
                },
12736 
                'en_x13' => {
12737 
                  'attributes' => {
12738 
                    'bin_pt' => 0,
12739 
                    'is_floating_block' => 1,
12740 
                    'must_be_hdl_vector' => 1,
12741 
                    'period' => 1,
12742 
                    'port_id' => 0,
12743 
                    'simulinkName' => 'INOUT_LOGIC/en',
12744 
                    'type' => 'Bool',
12745 
                  },
12746 
                  'direction' => 'out',
12747 
                  'hdlType' => 'std_logic',
12748 
                  'width' => 1,
12749 
                },
12750 
                'en_x14' => {
12751 
                  'attributes' => {
12752 
                    'bin_pt' => 0,
12753 
                    'is_floating_block' => 1,
12754 
                    'must_be_hdl_vector' => 1,
12755 
                    'period' => 1,
12756 
                    'port_id' => 0,
12757 
                    'simulinkName' => 'INOUT_LOGIC/en',
12758 
                    'type' => 'Bool',
12759 
                  },
12760 
                  'direction' => 'out',
12761 
                  'hdlType' => 'std_logic',
12762 
                  'width' => 1,
12763 
                },
12764 
                'en_x15' => {
12765 
                  'attributes' => {
12766 
                    'bin_pt' => 0,
12767 
                    'is_floating_block' => 1,
12768 
                    'must_be_hdl_vector' => 1,
12769 
                    'period' => 1,
12770 
                    'port_id' => 0,
12771 
                    'simulinkName' => 'INOUT_LOGIC/en',
12772 
                    'type' => 'Bool',
12773 
                  },
12774 
                  'direction' => 'out',
12775 
                  'hdlType' => 'std_logic',
12776 
                  'width' => 1,
12777 
                },
12778 
                'en_x16' => {
12779 
                  'attributes' => {
12780 
                    'bin_pt' => 0,
12781 
                    'is_floating_block' => 1,
12782 
                    'must_be_hdl_vector' => 1,
12783 
                    'period' => 1,
12784 
                    'port_id' => 0,
12785 
                    'simulinkName' => 'INOUT_LOGIC/en',
12786 
                    'type' => 'Bool',
12787 
                  },
12788 
                  'direction' => 'out',
12789 
                  'hdlType' => 'std_logic',
12790 
                  'width' => 1,
12791 
                },
12792 
                'en_x17' => {
12793 
                  'attributes' => {
12794 
                    'bin_pt' => 0,
12795 
                    'is_floating_block' => 1,
12796 
                    'must_be_hdl_vector' => 1,
12797 
                    'period' => 1,
12798 
                    'port_id' => 0,
12799 
                    'simulinkName' => 'INOUT_LOGIC/en',
12800 
                    'type' => 'Bool',
12801 
                  },
12802 
                  'direction' => 'out',
12803 
                  'hdlType' => 'std_logic',
12804 
                  'width' => 1,
12805 
                },
12806 
                'en_x18' => {
12807 
                  'attributes' => {
12808 
                    'bin_pt' => 0,
12809 
                    'is_floating_block' => 1,
12810 
                    'must_be_hdl_vector' => 1,
12811 
                    'period' => 1,
12812 
                    'port_id' => 0,
12813 
                    'simulinkName' => 'INOUT_LOGIC/en',
12814 
                    'type' => 'Bool',
12815 
                  },
12816 
                  'direction' => 'out',
12817 
                  'hdlType' => 'std_logic',
12818 
                  'width' => 1,
12819 
                },
12820 
                'en_x19' => {
12821 
                  'attributes' => {
12822 
                    'bin_pt' => 0,
12823 
                    'is_floating_block' => 1,
12824 
                    'must_be_hdl_vector' => 1,
12825 
                    'period' => 1,
12826 
                    'port_id' => 0,
12827 
                    'simulinkName' => 'INOUT_LOGIC/en',
12828 
                    'type' => 'Bool',
12829 
                  },
12830 
                  'direction' => 'out',
12831 
                  'hdlType' => 'std_logic',
12832 
                  'width' => 1,
12833 
                },
12834 
                'en_x2' => {
12835 
                  'attributes' => {
12836 
                    'bin_pt' => 0,
12837 
                    'is_floating_block' => 1,
12838 
                    'must_be_hdl_vector' => 1,
12839 
                    'period' => 1,
12840 
                    'port_id' => 0,
12841 
                    'simulinkName' => 'INOUT_LOGIC/en',
12842 
                    'type' => 'Bool',
12843 
                  },
12844 
                  'direction' => 'out',
12845 
                  'hdlType' => 'std_logic',
12846 
                  'width' => 1,
12847 
                },
12848 
                'en_x20' => {
12849 
                  'attributes' => {
12850 
                    'bin_pt' => 0,
12851 
                    'is_floating_block' => 1,
12852 
                    'must_be_hdl_vector' => 1,
12853 
                    'period' => 1,
12854 
                    'port_id' => 0,
12855 
                    'simulinkName' => 'INOUT_LOGIC/en',
12856 
                    'type' => 'Bool',
12857 
                  },
12858 
                  'direction' => 'out',
12859 
                  'hdlType' => 'std_logic',
12860 
                  'width' => 1,
12861 
                },
12862 
                'en_x21' => {
12863 
                  'attributes' => {
12864 
                    'bin_pt' => 0,
12865 
                    'is_floating_block' => 1,
12866 
                    'must_be_hdl_vector' => 1,
12867 
                    'period' => 1,
12868 
                    'port_id' => 0,
12869 
                    'simulinkName' => 'INOUT_LOGIC/en',
12870 
                    'type' => 'Bool',
12871 
                  },
12872 
                  'direction' => 'out',
12873 
                  'hdlType' => 'std_logic',
12874 
                  'width' => 1,
12875 
                },
12876 
                'en_x22' => {
12877 
                  'attributes' => {
12878 
                    'bin_pt' => 0,
12879 
                    'is_floating_block' => 1,
12880 
                    'must_be_hdl_vector' => 1,
12881 
                    'period' => 1,
12882 
                    'port_id' => 0,
12883 
                    'simulinkName' => 'INOUT_LOGIC/en',
12884 
                    'type' => 'Bool',
12885 
                  },
12886 
                  'direction' => 'out',
12887 
                  'hdlType' => 'std_logic',
12888 
                  'width' => 1,
12889 
                },
12890 
                'en_x23' => {
12891 
                  'attributes' => {
12892 
                    'bin_pt' => 0,
12893 
                    'is_floating_block' => 1,
12894 
                    'must_be_hdl_vector' => 1,
12895 
                    'period' => 1,
12896 
                    'port_id' => 0,
12897 
                    'simulinkName' => 'INOUT_LOGIC/en',
12898 
                    'type' => 'Bool',
12899 
                  },
12900 
                  'direction' => 'out',
12901 
                  'hdlType' => 'std_logic',
12902 
                  'width' => 1,
12903 
                },
12904 
                'en_x24' => {
12905 
                  'attributes' => {
12906 
                    'bin_pt' => 0,
12907 
                    'is_floating_block' => 1,
12908 
                    'must_be_hdl_vector' => 1,
12909 
                    'period' => 1,
12910 
                    'port_id' => 0,
12911 
                    'simulinkName' => 'INOUT_LOGIC/en',
12912 
                    'type' => 'Bool',
12913 
                  },
12914 
                  'direction' => 'out',
12915 
                  'hdlType' => 'std_logic',
12916 
                  'width' => 1,
12917 
                },
12918 
                'en_x25' => {
12919 
                  'attributes' => {
12920 
                    'bin_pt' => 0,
12921 
                    'is_floating_block' => 1,
12922 
                    'must_be_hdl_vector' => 1,
12923 
                    'period' => 1,
12924 
                    'port_id' => 0,
12925 
                    'simulinkName' => 'INOUT_LOGIC/en',
12926 
                    'type' => 'Bool',
12927 
                  },
12928 
                  'direction' => 'out',
12929 
                  'hdlType' => 'std_logic',
12930 
                  'width' => 1,
12931 
                },
12932 
                'en_x26' => {
12933 
                  'attributes' => {
12934 
                    'bin_pt' => 0,
12935 
                    'is_floating_block' => 1,
12936 
                    'must_be_hdl_vector' => 1,
12937 
                    'period' => 1,
12938 
                    'port_id' => 0,
12939 
                    'simulinkName' => 'INOUT_LOGIC/en',
12940 
                    'type' => 'Bool',
12941 
                  },
12942 
                  'direction' => 'out',
12943 
                  'hdlType' => 'std_logic',
12944 
                  'width' => 1,
12945 
                },
12946 
                'en_x27' => {
12947 
                  'attributes' => {
12948 
                    'bin_pt' => 0,
12949 
                    'is_floating_block' => 1,
12950 
                    'must_be_hdl_vector' => 1,
12951 
                    'period' => 1,
12952 
                    'port_id' => 0,
12953 
                    'simulinkName' => 'INOUT_LOGIC/en',
12954 
                    'type' => 'Bool',
12955 
                  },
12956 
                  'direction' => 'out',
12957 
                  'hdlType' => 'std_logic',
12958 
                  'width' => 1,
12959 
                },
12960 
                'en_x28' => {
12961 
                  'attributes' => {
12962 
                    'bin_pt' => 0,
12963 
                    'is_floating_block' => 1,
12964 
                    'must_be_hdl_vector' => 1,
12965 
                    'period' => 1,
12966 
                    'port_id' => 0,
12967 
                    'simulinkName' => 'INOUT_LOGIC/en',
12968 
                    'type' => 'Bool',
12969 
                  },
12970 
                  'direction' => 'out',
12971 
                  'hdlType' => 'std_logic',
12972 
                  'width' => 1,
12973 
                },
12974 
                'en_x29' => {
12975 
                  'attributes' => {
12976 
                    'bin_pt' => 0,
12977 
                    'is_floating_block' => 1,
12978 
                    'must_be_hdl_vector' => 1,
12979 
                    'period' => 1,
12980 
                    'port_id' => 0,
12981 
                    'simulinkName' => 'INOUT_LOGIC/en',
12982 
                    'type' => 'Bool',
12983 
                  },
12984 
                  'direction' => 'out',
12985 
                  'hdlType' => 'std_logic',
12986 
                  'width' => 1,
12987 
                },
12988 
                'en_x3' => {
12989 
                  'attributes' => {
12990 
                    'bin_pt' => 0,
12991 
                    'is_floating_block' => 1,
12992 
                    'must_be_hdl_vector' => 1,
12993 
                    'period' => 1,
12994 
                    'port_id' => 0,
12995 
                    'simulinkName' => 'INOUT_LOGIC/en',
12996 
                    'type' => 'Bool',
12997 
                  },
12998 
                  'direction' => 'out',
12999 
                  'hdlType' => 'std_logic',
13000 
                  'width' => 1,
13001 
                },
13002 
                'en_x30' => {
13003 
                  'attributes' => {
13004 
                    'bin_pt' => 0,
13005 
                    'is_floating_block' => 1,
13006 
                    'must_be_hdl_vector' => 1,
13007 
                    'period' => 1,
13008 
                    'port_id' => 0,
13009 
                    'simulinkName' => 'INOUT_LOGIC/en',
13010 
                    'type' => 'Bool',
13011 
                  },
13012 
                  'direction' => 'out',
13013 
                  'hdlType' => 'std_logic',
13014 
                  'width' => 1,
13015 
                },
13016 
                'en_x31' => {
13017 
                  'attributes' => {
13018 
                    'bin_pt' => 0,
13019 
                    'is_floating_block' => 1,
13020 
                    'must_be_hdl_vector' => 1,
13021 
                    'period' => 1,
13022 
                    'port_id' => 0,
13023 
                    'simulinkName' => 'INOUT_LOGIC/en',
13024 
                    'type' => 'Bool',
13025 
                  },
13026 
                  'direction' => 'out',
13027 
                  'hdlType' => 'std_logic',
13028 
                  'width' => 1,
13029 
                },
13030 
                'en_x32' => {
13031 
                  'attributes' => {
13032 
                    'bin_pt' => 0,
13033 
                    'is_floating_block' => 1,
13034 
                    'must_be_hdl_vector' => 1,
13035 
                    'period' => 1,
13036 
                    'port_id' => 0,
13037 
                    'simulinkName' => 'INOUT_LOGIC/en',
13038 
                    'type' => 'Bool',
13039 
                  },
13040 
                  'direction' => 'out',
13041 
                  'hdlType' => 'std_logic',
13042 
                  'width' => 1,
13043 
                },
13044 
                'en_x4' => {
13045 
                  'attributes' => {
13046 
                    'bin_pt' => 0,
13047 
                    'is_floating_block' => 1,
13048 
                    'must_be_hdl_vector' => 1,
13049 
                    'period' => 1,
13050 
                    'port_id' => 0,
13051 
                    'simulinkName' => 'INOUT_LOGIC/en',
13052 
                    'type' => 'Bool',
13053 
                  },
13054 
                  'direction' => 'out',
13055 
                  'hdlType' => 'std_logic',
13056 
                  'width' => 1,
13057 
                },
13058 
                'en_x5' => {
13059 
                  'attributes' => {
13060 
                    'bin_pt' => 0,
13061 
                    'is_floating_block' => 1,
13062 
                    'must_be_hdl_vector' => 1,
13063 
                    'period' => 1,
13064 
                    'port_id' => 0,
13065 
                    'simulinkName' => 'INOUT_LOGIC/en',
13066 
                    'type' => 'Bool',
13067 
                  },
13068 
                  'direction' => 'out',
13069 
                  'hdlType' => 'std_logic',
13070 
                  'width' => 1,
13071 
                },
13072 
                'en_x6' => {
13073 
                  'attributes' => {
13074 
                    'bin_pt' => 0,
13075 
                    'is_floating_block' => 1,
13076 
                    'must_be_hdl_vector' => 1,
13077 
                    'period' => 1,
13078 
                    'port_id' => 0,
13079 
                    'simulinkName' => 'INOUT_LOGIC/en',
13080 
                    'type' => 'Bool',
13081 
                  },
13082 
                  'direction' => 'out',
13083 
                  'hdlType' => 'std_logic',
13084 
                  'width' => 1,
13085 
                },
13086 
                'en_x7' => {
13087 
                  'attributes' => {
13088 
                    'bin_pt' => 0,
13089 
                    'is_floating_block' => 1,
13090 
                    'must_be_hdl_vector' => 1,
13091 
                    'period' => 1,
13092 
                    'port_id' => 0,
13093 
                    'simulinkName' => 'INOUT_LOGIC/en',
13094 
                    'type' => 'Bool',
13095 
                  },
13096 
                  'direction' => 'out',
13097 
                  'hdlType' => 'std_logic',
13098 
                  'width' => 1,
13099 
                },
13100 
                'en_x8' => {
13101 
                  'attributes' => {
13102 
                    'bin_pt' => 0,
13103 
                    'is_floating_block' => 1,
13104 
                    'must_be_hdl_vector' => 1,
13105 
                    'period' => 1,
13106 
                    'port_id' => 0,
13107 
                    'simulinkName' => 'INOUT_LOGIC/en',
13108 
                    'type' => 'Bool',
13109 
                  },
13110 
                  'direction' => 'out',
13111 
                  'hdlType' => 'std_logic',
13112 
                  'width' => 1,
13113 
                },
13114 
                'en_x9' => {
13115 
                  'attributes' => {
13116 
                    'bin_pt' => 0,
13117 
                    'is_floating_block' => 1,
13118 
                    'must_be_hdl_vector' => 1,
13119 
                    'period' => 1,
13120 
                    'port_id' => 0,
13121 
                    'simulinkName' => 'INOUT_LOGIC/en',
13122 
                    'type' => 'Bool',
13123 
                  },
13124 
                  'direction' => 'out',
13125 
                  'hdlType' => 'std_logic',
13126 
                  'width' => 1,
13127 
                },
13128 
                'reg01_rd' => {
13129 
                  'attributes' => {
13130 
                    'bin_pt' => 0,
13131 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
13132 
                    'is_floating_block' => 1,
13133 
                    'is_gateway_port' => 1,
13134 
                    'must_be_hdl_vector' => 1,
13135 
                    'period' => 1,
13136 
                    'port_id' => 0,
13137 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rd',
13138 
                    'source_block' => 'INOUT_LOGIC',
13139 
                    'timingConstraint' => 'none',
13140 
                    'type' => 'UFix_32_0',
13141 
                  },
13142 
                  'direction' => 'out',
13143 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13144 
                  'width' => 32,
13145 
                },
13146 
                'reg01_rv' => {
13147 
                  'attributes' => {
13148 
                    'bin_pt' => 0,
13149 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
13150 
                    'is_floating_block' => 1,
13151 
                    'is_gateway_port' => 1,
13152 
                    'must_be_hdl_vector' => 1,
13153 
                    'period' => 1,
13154 
                    'port_id' => 0,
13155 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rv',
13156 
                    'source_block' => 'INOUT_LOGIC',
13157 
                    'timingConstraint' => 'none',
13158 
                    'type' => 'UFix_1_0',
13159 
                  },
13160 
                  'direction' => 'out',
13161 
                  'hdlType' => 'std_logic',
13162 
                  'width' => 1,
13163 
                },
13164 
                'reg01_td' => {
13165 
                  'attributes' => {
13166 
                    'bin_pt' => 0,
13167 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
13168 
                    'is_floating_block' => 1,
13169 
                    'is_gateway_port' => 1,
13170 
                    'must_be_hdl_vector' => 1,
13171 
                    'period' => 1,
13172 
                    'port_id' => 0,
13173 
                    'simulinkName' => 'INOUT_LOGIC/reg01_td',
13174 
                    'source_block' => 'INOUT_LOGIC',
13175 
                    'timingConstraint' => 'none',
13176 
                    'type' => 'UFix_32_0',
13177 
                  },
13178 
                  'direction' => 'in',
13179 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13180 
                  'width' => 32,
13181 
                },
13182 
                'reg01_tv' => {
13183 
                  'attributes' => {
13184 
                    'bin_pt' => 0,
13185 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
13186 
                    'is_floating_block' => 1,
13187 
                    'is_gateway_port' => 1,
13188 
                    'must_be_hdl_vector' => 1,
13189 
                    'period' => 1,
13190 
                    'port_id' => 0,
13191 
                    'simulinkName' => 'INOUT_LOGIC/reg01_tv',
13192 
                    'source_block' => 'INOUT_LOGIC',
13193 
                    'timingConstraint' => 'none',
13194 
                    'type' => 'Bool',
13195 
                  },
13196 
                  'direction' => 'in',
13197 
                  'hdlType' => 'std_logic',
13198 
                  'width' => 1,
13199 
                },
13200 
                'reg02_rd' => {
13201 
                  'attributes' => {
13202 
                    'bin_pt' => 0,
13203 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
13204 
                    'is_floating_block' => 1,
13205 
                    'is_gateway_port' => 1,
13206 
                    'must_be_hdl_vector' => 1,
13207 
                    'period' => 1,
13208 
                    'port_id' => 0,
13209 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rd',
13210 
                    'source_block' => 'INOUT_LOGIC',
13211 
                    'timingConstraint' => 'none',
13212 
                    'type' => 'UFix_32_0',
13213 
                  },
13214 
                  'direction' => 'out',
13215 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13216 
                  'width' => 32,
13217 
                },
13218 
                'reg02_rv' => {
13219 
                  'attributes' => {
13220 
                    'bin_pt' => 0,
13221 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
13222 
                    'is_floating_block' => 1,
13223 
                    'is_gateway_port' => 1,
13224 
                    'must_be_hdl_vector' => 1,
13225 
                    'period' => 1,
13226 
                    'port_id' => 0,
13227 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rv',
13228 
                    'source_block' => 'INOUT_LOGIC',
13229 
                    'timingConstraint' => 'none',
13230 
                    'type' => 'UFix_1_0',
13231 
                  },
13232 
                  'direction' => 'out',
13233 
                  'hdlType' => 'std_logic',
13234 
                  'width' => 1,
13235 
                },
13236 
                'reg02_td' => {
13237 
                  'attributes' => {
13238 
                    'bin_pt' => 0,
13239 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
13240 
                    'is_floating_block' => 1,
13241 
                    'is_gateway_port' => 1,
13242 
                    'must_be_hdl_vector' => 1,
13243 
                    'period' => 1,
13244 
                    'port_id' => 0,
13245 
                    'simulinkName' => 'INOUT_LOGIC/reg02_td',
13246 
                    'source_block' => 'INOUT_LOGIC',
13247 
                    'timingConstraint' => 'none',
13248 
                    'type' => 'UFix_32_0',
13249 
                  },
13250 
                  'direction' => 'in',
13251 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13252 
                  'width' => 32,
13253 
                },
13254 
                'reg02_tv' => {
13255 
                  'attributes' => {
13256 
                    'bin_pt' => 0,
13257 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
13258 
                    'is_floating_block' => 1,
13259 
                    'is_gateway_port' => 1,
13260 
                    'must_be_hdl_vector' => 1,
13261 
                    'period' => 1,
13262 
                    'port_id' => 0,
13263 
                    'simulinkName' => 'INOUT_LOGIC/reg02_tv',
13264 
                    'source_block' => 'INOUT_LOGIC',
13265 
                    'timingConstraint' => 'none',
13266 
                    'type' => 'Bool',
13267 
                  },
13268 
                  'direction' => 'in',
13269 
                  'hdlType' => 'std_logic',
13270 
                  'width' => 1,
13271 
                },
13272 
                'reg03_rd' => {
13273 
                  'attributes' => {
13274 
                    'bin_pt' => 0,
13275 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
13276 
                    'is_floating_block' => 1,
13277 
                    'is_gateway_port' => 1,
13278 
                    'must_be_hdl_vector' => 1,
13279 
                    'period' => 1,
13280 
                    'port_id' => 0,
13281 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rd',
13282 
                    'source_block' => 'INOUT_LOGIC',
13283 
                    'timingConstraint' => 'none',
13284 
                    'type' => 'UFix_32_0',
13285 
                  },
13286 
                  'direction' => 'out',
13287 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13288 
                  'width' => 32,
13289 
                },
13290 
                'reg03_rv' => {
13291 
                  'attributes' => {
13292 
                    'bin_pt' => 0,
13293 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
13294 
                    'is_floating_block' => 1,
13295 
                    'is_gateway_port' => 1,
13296 
                    'must_be_hdl_vector' => 1,
13297 
                    'period' => 1,
13298 
                    'port_id' => 0,
13299 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rv',
13300 
                    'source_block' => 'INOUT_LOGIC',
13301 
                    'timingConstraint' => 'none',
13302 
                    'type' => 'UFix_1_0',
13303 
                  },
13304 
                  'direction' => 'out',
13305 
                  'hdlType' => 'std_logic',
13306 
                  'width' => 1,
13307 
                },
13308 
                'reg03_td' => {
13309 
                  'attributes' => {
13310 
                    'bin_pt' => 0,
13311 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
13312 
                    'is_floating_block' => 1,
13313 
                    'is_gateway_port' => 1,
13314 
                    'must_be_hdl_vector' => 1,
13315 
                    'period' => 1,
13316 
                    'port_id' => 0,
13317 
                    'simulinkName' => 'INOUT_LOGIC/reg03_td',
13318 
                    'source_block' => 'INOUT_LOGIC',
13319 
                    'timingConstraint' => 'none',
13320 
                    'type' => 'UFix_32_0',
13321 
                  },
13322 
                  'direction' => 'in',
13323 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13324 
                  'width' => 32,
13325 
                },
13326 
                'reg03_tv' => {
13327 
                  'attributes' => {
13328 
                    'bin_pt' => 0,
13329 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
13330 
                    'is_floating_block' => 1,
13331 
                    'is_gateway_port' => 1,
13332 
                    'must_be_hdl_vector' => 1,
13333 
                    'period' => 1,
13334 
                    'port_id' => 0,
13335 
                    'simulinkName' => 'INOUT_LOGIC/reg03_tv',
13336 
                    'source_block' => 'INOUT_LOGIC',
13337 
                    'timingConstraint' => 'none',
13338 
                    'type' => 'Bool',
13339 
                  },
13340 
                  'direction' => 'in',
13341 
                  'hdlType' => 'std_logic',
13342 
                  'width' => 1,
13343 
                },
13344 
                'reg04_rd' => {
13345 
                  'attributes' => {
13346 
                    'bin_pt' => 0,
13347 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
13348 
                    'is_floating_block' => 1,
13349 
                    'is_gateway_port' => 1,
13350 
                    'must_be_hdl_vector' => 1,
13351 
                    'period' => 1,
13352 
                    'port_id' => 0,
13353 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rd',
13354 
                    'source_block' => 'INOUT_LOGIC',
13355 
                    'timingConstraint' => 'none',
13356 
                    'type' => 'UFix_32_0',
13357 
                  },
13358 
                  'direction' => 'out',
13359 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13360 
                  'width' => 32,
13361 
                },
13362 
                'reg04_rv' => {
13363 
                  'attributes' => {
13364 
                    'bin_pt' => 0,
13365 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
13366 
                    'is_floating_block' => 1,
13367 
                    'is_gateway_port' => 1,
13368 
                    'must_be_hdl_vector' => 1,
13369 
                    'period' => 1,
13370 
                    'port_id' => 0,
13371 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rv',
13372 
                    'source_block' => 'INOUT_LOGIC',
13373 
                    'timingConstraint' => 'none',
13374 
                    'type' => 'UFix_1_0',
13375 
                  },
13376 
                  'direction' => 'out',
13377 
                  'hdlType' => 'std_logic',
13378 
                  'width' => 1,
13379 
                },
13380 
                'reg04_td' => {
13381 
                  'attributes' => {
13382 
                    'bin_pt' => 0,
13383 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
13384 
                    'is_floating_block' => 1,
13385 
                    'is_gateway_port' => 1,
13386 
                    'must_be_hdl_vector' => 1,
13387 
                    'period' => 1,
13388 
                    'port_id' => 0,
13389 
                    'simulinkName' => 'INOUT_LOGIC/reg04_td',
13390 
                    'source_block' => 'INOUT_LOGIC',
13391 
                    'timingConstraint' => 'none',
13392 
                    'type' => 'UFix_32_0',
13393 
                  },
13394 
                  'direction' => 'in',
13395 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13396 
                  'width' => 32,
13397 
                },
13398 
                'reg04_tv' => {
13399 
                  'attributes' => {
13400 
                    'bin_pt' => 0,
13401 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
13402 
                    'is_floating_block' => 1,
13403 
                    'is_gateway_port' => 1,
13404 
                    'must_be_hdl_vector' => 1,
13405 
                    'period' => 1,
13406 
                    'port_id' => 0,
13407 
                    'simulinkName' => 'INOUT_LOGIC/reg04_tv',
13408 
                    'source_block' => 'INOUT_LOGIC',
13409 
                    'timingConstraint' => 'none',
13410 
                    'type' => 'Bool',
13411 
                  },
13412 
                  'direction' => 'in',
13413 
                  'hdlType' => 'std_logic',
13414 
                  'width' => 1,
13415 
                },
13416 
                'reg05_rd' => {
13417 
                  'attributes' => {
13418 
                    'bin_pt' => 0,
13419 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
13420 
                    'is_floating_block' => 1,
13421 
                    'is_gateway_port' => 1,
13422 
                    'must_be_hdl_vector' => 1,
13423 
                    'period' => 1,
13424 
                    'port_id' => 0,
13425 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rd',
13426 
                    'source_block' => 'INOUT_LOGIC',
13427 
                    'timingConstraint' => 'none',
13428 
                    'type' => 'UFix_32_0',
13429 
                  },
13430 
                  'direction' => 'out',
13431 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13432 
                  'width' => 32,
13433 
                },
13434 
                'reg05_rv' => {
13435 
                  'attributes' => {
13436 
                    'bin_pt' => 0,
13437 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
13438 
                    'is_floating_block' => 1,
13439 
                    'is_gateway_port' => 1,
13440 
                    'must_be_hdl_vector' => 1,
13441 
                    'period' => 1,
13442 
                    'port_id' => 0,
13443 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rv',
13444 
                    'source_block' => 'INOUT_LOGIC',
13445 
                    'timingConstraint' => 'none',
13446 
                    'type' => 'UFix_1_0',
13447 
                  },
13448 
                  'direction' => 'out',
13449 
                  'hdlType' => 'std_logic',
13450 
                  'width' => 1,
13451 
                },
13452 
                'reg05_td' => {
13453 
                  'attributes' => {
13454 
                    'bin_pt' => 0,
13455 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
13456 
                    'is_floating_block' => 1,
13457 
                    'is_gateway_port' => 1,
13458 
                    'must_be_hdl_vector' => 1,
13459 
                    'period' => 1,
13460 
                    'port_id' => 0,
13461 
                    'simulinkName' => 'INOUT_LOGIC/reg05_td',
13462 
                    'source_block' => 'INOUT_LOGIC',
13463 
                    'timingConstraint' => 'none',
13464 
                    'type' => 'UFix_32_0',
13465 
                  },
13466 
                  'direction' => 'in',
13467 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13468 
                  'width' => 32,
13469 
                },
13470 
                'reg05_tv' => {
13471 
                  'attributes' => {
13472 
                    'bin_pt' => 0,
13473 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
13474 
                    'is_floating_block' => 1,
13475 
                    'is_gateway_port' => 1,
13476 
                    'must_be_hdl_vector' => 1,
13477 
                    'period' => 1,
13478 
                    'port_id' => 0,
13479 
                    'simulinkName' => 'INOUT_LOGIC/reg05_tv',
13480 
                    'source_block' => 'INOUT_LOGIC',
13481 
                    'timingConstraint' => 'none',
13482 
                    'type' => 'Bool',
13483 
                  },
13484 
                  'direction' => 'in',
13485 
                  'hdlType' => 'std_logic',
13486 
                  'width' => 1,
13487 
                },
13488 
                'reg06_rd' => {
13489 
                  'attributes' => {
13490 
                    'bin_pt' => 0,
13491 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
13492 
                    'is_floating_block' => 1,
13493 
                    'is_gateway_port' => 1,
13494 
                    'must_be_hdl_vector' => 1,
13495 
                    'period' => 1,
13496 
                    'port_id' => 0,
13497 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rd',
13498 
                    'source_block' => 'INOUT_LOGIC',
13499 
                    'timingConstraint' => 'none',
13500 
                    'type' => 'UFix_32_0',
13501 
                  },
13502 
                  'direction' => 'out',
13503 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13504 
                  'width' => 32,
13505 
                },
13506 
                'reg06_rv' => {
13507 
                  'attributes' => {
13508 
                    'bin_pt' => 0,
13509 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
13510 
                    'is_floating_block' => 1,
13511 
                    'is_gateway_port' => 1,
13512 
                    'must_be_hdl_vector' => 1,
13513 
                    'period' => 1,
13514 
                    'port_id' => 0,
13515 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rv',
13516 
                    'source_block' => 'INOUT_LOGIC',
13517 
                    'timingConstraint' => 'none',
13518 
                    'type' => 'UFix_1_0',
13519 
                  },
13520 
                  'direction' => 'out',
13521 
                  'hdlType' => 'std_logic',
13522 
                  'width' => 1,
13523 
                },
13524 
                'reg06_td' => {
13525 
                  'attributes' => {
13526 
                    'bin_pt' => 0,
13527 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
13528 
                    'is_floating_block' => 1,
13529 
                    'is_gateway_port' => 1,
13530 
                    'must_be_hdl_vector' => 1,
13531 
                    'period' => 1,
13532 
                    'port_id' => 0,
13533 
                    'simulinkName' => 'INOUT_LOGIC/reg06_td',
13534 
                    'source_block' => 'INOUT_LOGIC',
13535 
                    'timingConstraint' => 'none',
13536 
                    'type' => 'UFix_32_0',
13537 
                  },
13538 
                  'direction' => 'in',
13539 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13540 
                  'width' => 32,
13541 
                },
13542 
                'reg06_tv' => {
13543 
                  'attributes' => {
13544 
                    'bin_pt' => 0,
13545 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
13546 
                    'is_floating_block' => 1,
13547 
                    'is_gateway_port' => 1,
13548 
                    'must_be_hdl_vector' => 1,
13549 
                    'period' => 1,
13550 
                    'port_id' => 0,
13551 
                    'simulinkName' => 'INOUT_LOGIC/reg06_tv',
13552 
                    'source_block' => 'INOUT_LOGIC',
13553 
                    'timingConstraint' => 'none',
13554 
                    'type' => 'Bool',
13555 
                  },
13556 
                  'direction' => 'in',
13557 
                  'hdlType' => 'std_logic',
13558 
                  'width' => 1,
13559 
                },
13560 
                'reg07_rd' => {
13561 
                  'attributes' => {
13562 
                    'bin_pt' => 0,
13563 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
13564 
                    'is_floating_block' => 1,
13565 
                    'is_gateway_port' => 1,
13566 
                    'must_be_hdl_vector' => 1,
13567 
                    'period' => 1,
13568 
                    'port_id' => 0,
13569 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rd',
13570 
                    'source_block' => 'INOUT_LOGIC',
13571 
                    'timingConstraint' => 'none',
13572 
                    'type' => 'UFix_32_0',
13573 
                  },
13574 
                  'direction' => 'out',
13575 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13576 
                  'width' => 32,
13577 
                },
13578 
                'reg07_rv' => {
13579 
                  'attributes' => {
13580 
                    'bin_pt' => 0,
13581 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
13582 
                    'is_floating_block' => 1,
13583 
                    'is_gateway_port' => 1,
13584 
                    'must_be_hdl_vector' => 1,
13585 
                    'period' => 1,
13586 
                    'port_id' => 0,
13587 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rv',
13588 
                    'source_block' => 'INOUT_LOGIC',
13589 
                    'timingConstraint' => 'none',
13590 
                    'type' => 'UFix_1_0',
13591 
                  },
13592 
                  'direction' => 'out',
13593 
                  'hdlType' => 'std_logic',
13594 
                  'width' => 1,
13595 
                },
13596 
                'reg07_td' => {
13597 
                  'attributes' => {
13598 
                    'bin_pt' => 0,
13599 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
13600 
                    'is_floating_block' => 1,
13601 
                    'is_gateway_port' => 1,
13602 
                    'must_be_hdl_vector' => 1,
13603 
                    'period' => 1,
13604 
                    'port_id' => 0,
13605 
                    'simulinkName' => 'INOUT_LOGIC/reg07_td',
13606 
                    'source_block' => 'INOUT_LOGIC',
13607 
                    'timingConstraint' => 'none',
13608 
                    'type' => 'UFix_32_0',
13609 
                  },
13610 
                  'direction' => 'in',
13611 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13612 
                  'width' => 32,
13613 
                },
13614 
                'reg07_tv' => {
13615 
                  'attributes' => {
13616 
                    'bin_pt' => 0,
13617 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
13618 
                    'is_floating_block' => 1,
13619 
                    'is_gateway_port' => 1,
13620 
                    'must_be_hdl_vector' => 1,
13621 
                    'period' => 1,
13622 
                    'port_id' => 0,
13623 
                    'simulinkName' => 'INOUT_LOGIC/reg07_tv',
13624 
                    'source_block' => 'INOUT_LOGIC',
13625 
                    'timingConstraint' => 'none',
13626 
                    'type' => 'Bool',
13627 
                  },
13628 
                  'direction' => 'in',
13629 
                  'hdlType' => 'std_logic',
13630 
                  'width' => 1,
13631 
                },
13632 
                'reg08_rd' => {
13633 
                  'attributes' => {
13634 
                    'bin_pt' => 0,
13635 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
13636 
                    'is_floating_block' => 1,
13637 
                    'is_gateway_port' => 1,
13638 
                    'must_be_hdl_vector' => 1,
13639 
                    'period' => 1,
13640 
                    'port_id' => 0,
13641 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rd',
13642 
                    'source_block' => 'INOUT_LOGIC',
13643 
                    'timingConstraint' => 'none',
13644 
                    'type' => 'UFix_32_0',
13645 
                  },
13646 
                  'direction' => 'out',
13647 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13648 
                  'width' => 32,
13649 
                },
13650 
                'reg08_rv' => {
13651 
                  'attributes' => {
13652 
                    'bin_pt' => 0,
13653 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
13654 
                    'is_floating_block' => 1,
13655 
                    'is_gateway_port' => 1,
13656 
                    'must_be_hdl_vector' => 1,
13657 
                    'period' => 1,
13658 
                    'port_id' => 0,
13659 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rv',
13660 
                    'source_block' => 'INOUT_LOGIC',
13661 
                    'timingConstraint' => 'none',
13662 
                    'type' => 'UFix_1_0',
13663 
                  },
13664 
                  'direction' => 'out',
13665 
                  'hdlType' => 'std_logic',
13666 
                  'width' => 1,
13667 
                },
13668 
                'reg08_td' => {
13669 
                  'attributes' => {
13670 
                    'bin_pt' => 0,
13671 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
13672 
                    'is_floating_block' => 1,
13673 
                    'is_gateway_port' => 1,
13674 
                    'must_be_hdl_vector' => 1,
13675 
                    'period' => 1,
13676 
                    'port_id' => 0,
13677 
                    'simulinkName' => 'INOUT_LOGIC/reg08_td',
13678 
                    'source_block' => 'INOUT_LOGIC',
13679 
                    'timingConstraint' => 'none',
13680 
                    'type' => 'UFix_32_0',
13681 
                  },
13682 
                  'direction' => 'in',
13683 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13684 
                  'width' => 32,
13685 
                },
13686 
                'reg08_tv' => {
13687 
                  'attributes' => {
13688 
                    'bin_pt' => 0,
13689 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
13690 
                    'is_floating_block' => 1,
13691 
                    'is_gateway_port' => 1,
13692 
                    'must_be_hdl_vector' => 1,
13693 
                    'period' => 1,
13694 
                    'port_id' => 0,
13695 
                    'simulinkName' => 'INOUT_LOGIC/reg08_tv',
13696 
                    'source_block' => 'INOUT_LOGIC',
13697 
                    'timingConstraint' => 'none',
13698 
                    'type' => 'Bool',
13699 
                  },
13700 
                  'direction' => 'in',
13701 
                  'hdlType' => 'std_logic',
13702 
                  'width' => 1,
13703 
                },
13704 
                'reg09_rd' => {
13705 
                  'attributes' => {
13706 
                    'bin_pt' => 0,
13707 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
13708 
                    'is_floating_block' => 1,
13709 
                    'is_gateway_port' => 1,
13710 
                    'must_be_hdl_vector' => 1,
13711 
                    'period' => 1,
13712 
                    'port_id' => 0,
13713 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rd',
13714 
                    'source_block' => 'INOUT_LOGIC',
13715 
                    'timingConstraint' => 'none',
13716 
                    'type' => 'UFix_32_0',
13717 
                  },
13718 
                  'direction' => 'out',
13719 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13720 
                  'width' => 32,
13721 
                },
13722 
                'reg09_rv' => {
13723 
                  'attributes' => {
13724 
                    'bin_pt' => 0,
13725 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
13726 
                    'is_floating_block' => 1,
13727 
                    'is_gateway_port' => 1,
13728 
                    'must_be_hdl_vector' => 1,
13729 
                    'period' => 1,
13730 
                    'port_id' => 0,
13731 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rv',
13732 
                    'source_block' => 'INOUT_LOGIC',
13733 
                    'timingConstraint' => 'none',
13734 
                    'type' => 'UFix_1_0',
13735 
                  },
13736 
                  'direction' => 'out',
13737 
                  'hdlType' => 'std_logic',
13738 
                  'width' => 1,
13739 
                },
13740 
                'reg09_td' => {
13741 
                  'attributes' => {
13742 
                    'bin_pt' => 0,
13743 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
13744 
                    'is_floating_block' => 1,
13745 
                    'is_gateway_port' => 1,
13746 
                    'must_be_hdl_vector' => 1,
13747 
                    'period' => 1,
13748 
                    'port_id' => 0,
13749 
                    'simulinkName' => 'INOUT_LOGIC/reg09_td',
13750 
                    'source_block' => 'INOUT_LOGIC',
13751 
                    'timingConstraint' => 'none',
13752 
                    'type' => 'UFix_32_0',
13753 
                  },
13754 
                  'direction' => 'in',
13755 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13756 
                  'width' => 32,
13757 
                },
13758 
                'reg09_tv' => {
13759 
                  'attributes' => {
13760 
                    'bin_pt' => 0,
13761 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
13762 
                    'is_floating_block' => 1,
13763 
                    'is_gateway_port' => 1,
13764 
                    'must_be_hdl_vector' => 1,
13765 
                    'period' => 1,
13766 
                    'port_id' => 0,
13767 
                    'simulinkName' => 'INOUT_LOGIC/reg09_tv',
13768 
                    'source_block' => 'INOUT_LOGIC',
13769 
                    'timingConstraint' => 'none',
13770 
                    'type' => 'Bool',
13771 
                  },
13772 
                  'direction' => 'in',
13773 
                  'hdlType' => 'std_logic',
13774 
                  'width' => 1,
13775 
                },
13776 
                'reg10_rd' => {
13777 
                  'attributes' => {
13778 
                    'bin_pt' => 0,
13779 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
13780 
                    'is_floating_block' => 1,
13781 
                    'is_gateway_port' => 1,
13782 
                    'must_be_hdl_vector' => 1,
13783 
                    'period' => 1,
13784 
                    'port_id' => 0,
13785 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rd',
13786 
                    'source_block' => 'INOUT_LOGIC',
13787 
                    'timingConstraint' => 'none',
13788 
                    'type' => 'UFix_32_0',
13789 
                  },
13790 
                  'direction' => 'out',
13791 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13792 
                  'width' => 32,
13793 
                },
13794 
                'reg10_rv' => {
13795 
                  'attributes' => {
13796 
                    'bin_pt' => 0,
13797 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
13798 
                    'is_floating_block' => 1,
13799 
                    'is_gateway_port' => 1,
13800 
                    'must_be_hdl_vector' => 1,
13801 
                    'period' => 1,
13802 
                    'port_id' => 0,
13803 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rv',
13804 
                    'source_block' => 'INOUT_LOGIC',
13805 
                    'timingConstraint' => 'none',
13806 
                    'type' => 'UFix_1_0',
13807 
                  },
13808 
                  'direction' => 'out',
13809 
                  'hdlType' => 'std_logic',
13810 
                  'width' => 1,
13811 
                },
13812 
                'reg10_td' => {
13813 
                  'attributes' => {
13814 
                    'bin_pt' => 0,
13815 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
13816 
                    'is_floating_block' => 1,
13817 
                    'is_gateway_port' => 1,
13818 
                    'must_be_hdl_vector' => 1,
13819 
                    'period' => 1,
13820 
                    'port_id' => 0,
13821 
                    'simulinkName' => 'INOUT_LOGIC/reg10_td',
13822 
                    'source_block' => 'INOUT_LOGIC',
13823 
                    'timingConstraint' => 'none',
13824 
                    'type' => 'UFix_32_0',
13825 
                  },
13826 
                  'direction' => 'in',
13827 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13828 
                  'width' => 32,
13829 
                },
13830 
                'reg10_tv' => {
13831 
                  'attributes' => {
13832 
                    'bin_pt' => 0,
13833 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
13834 
                    'is_floating_block' => 1,
13835 
                    'is_gateway_port' => 1,
13836 
                    'must_be_hdl_vector' => 1,
13837 
                    'period' => 1,
13838 
                    'port_id' => 0,
13839 
                    'simulinkName' => 'INOUT_LOGIC/reg10_tv',
13840 
                    'source_block' => 'INOUT_LOGIC',
13841 
                    'timingConstraint' => 'none',
13842 
                    'type' => 'Bool',
13843 
                  },
13844 
                  'direction' => 'in',
13845 
                  'hdlType' => 'std_logic',
13846 
                  'width' => 1,
13847 
                },
13848 
                'reg11_rd' => {
13849 
                  'attributes' => {
13850 
                    'bin_pt' => 0,
13851 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
13852 
                    'is_floating_block' => 1,
13853 
                    'is_gateway_port' => 1,
13854 
                    'must_be_hdl_vector' => 1,
13855 
                    'period' => 1,
13856 
                    'port_id' => 0,
13857 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rd',
13858 
                    'source_block' => 'INOUT_LOGIC',
13859 
                    'timingConstraint' => 'none',
13860 
                    'type' => 'UFix_32_0',
13861 
                  },
13862 
                  'direction' => 'out',
13863 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13864 
                  'width' => 32,
13865 
                },
13866 
                'reg11_rv' => {
13867 
                  'attributes' => {
13868 
                    'bin_pt' => 0,
13869 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
13870 
                    'is_floating_block' => 1,
13871 
                    'is_gateway_port' => 1,
13872 
                    'must_be_hdl_vector' => 1,
13873 
                    'period' => 1,
13874 
                    'port_id' => 0,
13875 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rv',
13876 
                    'source_block' => 'INOUT_LOGIC',
13877 
                    'timingConstraint' => 'none',
13878 
                    'type' => 'UFix_1_0',
13879 
                  },
13880 
                  'direction' => 'out',
13881 
                  'hdlType' => 'std_logic',
13882 
                  'width' => 1,
13883 
                },
13884 
                'reg11_td' => {
13885 
                  'attributes' => {
13886 
                    'bin_pt' => 0,
13887 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
13888 
                    'is_floating_block' => 1,
13889 
                    'is_gateway_port' => 1,
13890 
                    'must_be_hdl_vector' => 1,
13891 
                    'period' => 1,
13892 
                    'port_id' => 0,
13893 
                    'simulinkName' => 'INOUT_LOGIC/reg11_td',
13894 
                    'source_block' => 'INOUT_LOGIC',
13895 
                    'timingConstraint' => 'none',
13896 
                    'type' => 'UFix_32_0',
13897 
                  },
13898 
                  'direction' => 'in',
13899 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13900 
                  'width' => 32,
13901 
                },
13902 
                'reg11_tv' => {
13903 
                  'attributes' => {
13904 
                    'bin_pt' => 0,
13905 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
13906 
                    'is_floating_block' => 1,
13907 
                    'is_gateway_port' => 1,
13908 
                    'must_be_hdl_vector' => 1,
13909 
                    'period' => 1,
13910 
                    'port_id' => 0,
13911 
                    'simulinkName' => 'INOUT_LOGIC/reg11_tv',
13912 
                    'source_block' => 'INOUT_LOGIC',
13913 
                    'timingConstraint' => 'none',
13914 
                    'type' => 'Bool',
13915 
                  },
13916 
                  'direction' => 'in',
13917 
                  'hdlType' => 'std_logic',
13918 
                  'width' => 1,
13919 
                },
13920 
                'reg12_rd' => {
13921 
                  'attributes' => {
13922 
                    'bin_pt' => 0,
13923 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
13924 
                    'is_floating_block' => 1,
13925 
                    'is_gateway_port' => 1,
13926 
                    'must_be_hdl_vector' => 1,
13927 
                    'period' => 1,
13928 
                    'port_id' => 0,
13929 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rd',
13930 
                    'source_block' => 'INOUT_LOGIC',
13931 
                    'timingConstraint' => 'none',
13932 
                    'type' => 'UFix_32_0',
13933 
                  },
13934 
                  'direction' => 'out',
13935 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13936 
                  'width' => 32,
13937 
                },
13938 
                'reg12_rv' => {
13939 
                  'attributes' => {
13940 
                    'bin_pt' => 0,
13941 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
13942 
                    'is_floating_block' => 1,
13943 
                    'is_gateway_port' => 1,
13944 
                    'must_be_hdl_vector' => 1,
13945 
                    'period' => 1,
13946 
                    'port_id' => 0,
13947 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rv',
13948 
                    'source_block' => 'INOUT_LOGIC',
13949 
                    'timingConstraint' => 'none',
13950 
                    'type' => 'UFix_1_0',
13951 
                  },
13952 
                  'direction' => 'out',
13953 
                  'hdlType' => 'std_logic',
13954 
                  'width' => 1,
13955 
                },
13956 
                'reg12_td' => {
13957 
                  'attributes' => {
13958 
                    'bin_pt' => 0,
13959 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
13960 
                    'is_floating_block' => 1,
13961 
                    'is_gateway_port' => 1,
13962 
                    'must_be_hdl_vector' => 1,
13963 
                    'period' => 1,
13964 
                    'port_id' => 0,
13965 
                    'simulinkName' => 'INOUT_LOGIC/reg12_td',
13966 
                    'source_block' => 'INOUT_LOGIC',
13967 
                    'timingConstraint' => 'none',
13968 
                    'type' => 'UFix_32_0',
13969 
                  },
13970 
                  'direction' => 'in',
13971 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13972 
                  'width' => 32,
13973 
                },
13974 
                'reg12_tv' => {
13975 
                  'attributes' => {
13976 
                    'bin_pt' => 0,
13977 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
13978 
                    'is_floating_block' => 1,
13979 
                    'is_gateway_port' => 1,
13980 
                    'must_be_hdl_vector' => 1,
13981 
                    'period' => 1,
13982 
                    'port_id' => 0,
13983 
                    'simulinkName' => 'INOUT_LOGIC/reg12_tv',
13984 
                    'source_block' => 'INOUT_LOGIC',
13985 
                    'timingConstraint' => 'none',
13986 
                    'type' => 'Bool',
13987 
                  },
13988 
                  'direction' => 'in',
13989 
                  'hdlType' => 'std_logic',
13990 
                  'width' => 1,
13991 
                },
13992 
                'reg13_rd' => {
13993 
                  'attributes' => {
13994 
                    'bin_pt' => 0,
13995 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
13996 
                    'is_floating_block' => 1,
13997 
                    'is_gateway_port' => 1,
13998 
                    'must_be_hdl_vector' => 1,
13999 
                    'period' => 1,
14000 
                    'port_id' => 0,
14001 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rd',
14002 
                    'source_block' => 'INOUT_LOGIC',
14003 
                    'timingConstraint' => 'none',
14004 
                    'type' => 'UFix_32_0',
14005 
                  },
14006 
                  'direction' => 'out',
14007 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14008 
                  'width' => 32,
14009 
                },
14010 
                'reg13_rv' => {
14011 
                  'attributes' => {
14012 
                    'bin_pt' => 0,
14013 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
14014 
                    'is_floating_block' => 1,
14015 
                    'is_gateway_port' => 1,
14016 
                    'must_be_hdl_vector' => 1,
14017 
                    'period' => 1,
14018 
                    'port_id' => 0,
14019 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rv',
14020 
                    'source_block' => 'INOUT_LOGIC',
14021 
                    'timingConstraint' => 'none',
14022 
                    'type' => 'UFix_1_0',
14023 
                  },
14024 
                  'direction' => 'out',
14025 
                  'hdlType' => 'std_logic',
14026 
                  'width' => 1,
14027 
                },
14028 
                'reg13_td' => {
14029 
                  'attributes' => {
14030 
                    'bin_pt' => 0,
14031 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
14032 
                    'is_floating_block' => 1,
14033 
                    'is_gateway_port' => 1,
14034 
                    'must_be_hdl_vector' => 1,
14035 
                    'period' => 1,
14036 
                    'port_id' => 0,
14037 
                    'simulinkName' => 'INOUT_LOGIC/reg13_td',
14038 
                    'source_block' => 'INOUT_LOGIC',
14039 
                    'timingConstraint' => 'none',
14040 
                    'type' => 'UFix_32_0',
14041 
                  },
14042 
                  'direction' => 'in',
14043 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14044 
                  'width' => 32,
14045 
                },
14046 
                'reg13_tv' => {
14047 
                  'attributes' => {
14048 
                    'bin_pt' => 0,
14049 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
14050 
                    'is_floating_block' => 1,
14051 
                    'is_gateway_port' => 1,
14052 
                    'must_be_hdl_vector' => 1,
14053 
                    'period' => 1,
14054 
                    'port_id' => 0,
14055 
                    'simulinkName' => 'INOUT_LOGIC/reg13_tv',
14056 
                    'source_block' => 'INOUT_LOGIC',
14057 
                    'timingConstraint' => 'none',
14058 
                    'type' => 'Bool',
14059 
                  },
14060 
                  'direction' => 'in',
14061 
                  'hdlType' => 'std_logic',
14062 
                  'width' => 1,
14063 
                },
14064 
                'reg14_rd' => {
14065 
                  'attributes' => {
14066 
                    'bin_pt' => 0,
14067 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
14068 
                    'is_floating_block' => 1,
14069 
                    'is_gateway_port' => 1,
14070 
                    'must_be_hdl_vector' => 1,
14071 
                    'period' => 1,
14072 
                    'port_id' => 0,
14073 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rd',
14074 
                    'source_block' => 'INOUT_LOGIC',
14075 
                    'timingConstraint' => 'none',
14076 
                    'type' => 'UFix_32_0',
14077 
                  },
14078 
                  'direction' => 'out',
14079 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14080 
                  'width' => 32,
14081 
                },
14082 
                'reg14_rv' => {
14083 
                  'attributes' => {
14084 
                    'bin_pt' => 0,
14085 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
14086 
                    'is_floating_block' => 1,
14087 
                    'is_gateway_port' => 1,
14088 
                    'must_be_hdl_vector' => 1,
14089 
                    'period' => 1,
14090 
                    'port_id' => 0,
14091 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rv',
14092 
                    'source_block' => 'INOUT_LOGIC',
14093 
                    'timingConstraint' => 'none',
14094 
                    'type' => 'UFix_1_0',
14095 
                  },
14096 
                  'direction' => 'out',
14097 
                  'hdlType' => 'std_logic',
14098 
                  'width' => 1,
14099 
                },
14100 
                'reg14_td' => {
14101 
                  'attributes' => {
14102 
                    'bin_pt' => 0,
14103 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
14104 
                    'is_floating_block' => 1,
14105 
                    'is_gateway_port' => 1,
14106 
                    'must_be_hdl_vector' => 1,
14107 
                    'period' => 1,
14108 
                    'port_id' => 0,
14109 
                    'simulinkName' => 'INOUT_LOGIC/reg14_td',
14110 
                    'source_block' => 'INOUT_LOGIC',
14111 
                    'timingConstraint' => 'none',
14112 
                    'type' => 'UFix_32_0',
14113 
                  },
14114 
                  'direction' => 'in',
14115 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14116 
                  'width' => 32,
14117 
                },
14118 
                'reg14_tv' => {
14119 
                  'attributes' => {
14120 
                    'bin_pt' => 0,
14121 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
14122 
                    'is_floating_block' => 1,
14123 
                    'is_gateway_port' => 1,
14124 
                    'must_be_hdl_vector' => 1,
14125 
                    'period' => 1,
14126 
                    'port_id' => 0,
14127 
                    'simulinkName' => 'INOUT_LOGIC/reg14_tv',
14128 
                    'source_block' => 'INOUT_LOGIC',
14129 
                    'timingConstraint' => 'none',
14130 
                    'type' => 'Bool',
14131 
                  },
14132 
                  'direction' => 'in',
14133 
                  'hdlType' => 'std_logic',
14134 
                  'width' => 1,
14135 
                },
14136 
              },
14137 
            },
14138 
            'entityName' => 'inout_logic',
14139 
          },
14140 
          'persistentdff_inst' => {
14141 
            'connections' => {
14142 
              'clk' => 'clkNet',
14143 
              'd' => 'persistentdff_inst_q',
14144 
              'q' => 'persistentdff_inst_q',
14145 
            },
14146 
            'entity' => {
14147 
              'attributes' => {
14148 
                'entityAlreadyNetlisted' => 1,
14149 
                'hdlCompAttributes' => [
14150 
                  [
14151 
                    'syn_black_box',
14152 
                    'boolean',
14153 
                    'true',
14154 
                  ],
14155 
                  [
14156 
                    'box_type',
14157 
                    'string',
14158 
                    '"black_box"',
14159 
                  ],
14160 
                ],
14161 
                'is_persistent_dff' => 1,
14162 
                'needsComponentDeclaration' => 1,
14163 
              },
14164 
              'entityName' => 'xlpersistentdff',
14165 
              'ports' => {
14166 
                'clk' => {
14167 
                  'direction' => 'in',
14168 
                  'hdlType' => 'std_logic',
14169 
                  'width' => 1,
14170 
                },
14171 
                'd' => {
14172 
                  'direction' => 'in',
14173 
                  'hdlType' => 'std_logic',
14174 
                  'width' => 1,
14175 
                },
14176 
                'q' => {
14177 
                  'direction' => 'out',
14178 
                  'hdlType' => 'std_logic',
14179 
                  'width' => 1,
14180 
                },
14181 
              },
14182 
            },
14183 
            'entityName' => 'xlpersistentdff',
14184 
          },
14185 
        },
14186 
      },
14187 
      'entityName' => 'inout_logic_cw',
14188 
    },
14189 
    'sysgen_gw_clk' => {
14190 
      'connections' => { 'clk' => '.clk', },
14191 
      'entity' => {
14192 
        'attributes' => {
14193 
          'entityAlreadyNetlisted' => 1,
14194 
          'isClk' => 1,
14195 
          'isGateway' => 1,
14196 
          'is_floating_block' => 1,
14197 
        },
14198 
        'entityName' => 'sysgen_gw_clk',
14199 
        'ports' => {
14200 
          'clk' => {
14201 
            'attributes' => { 'isClk' => 1, },
14202 
            'direction' => 'out',
14203 
            'hdlType' => 'std_logic',
14204 
            'width' => 1,
14205 
          },
14206 
        },
14207 
      },
14208 
      'entityName' => 'sysgen_gw_clk',
14209 
    },
14210 
    'to_register1' => {
14211 
      'connections' => {
14212 
        'ce' => 'sysgen_dut.to_register1_ce',
14213 
        'clk' => 'sysgen_dut.to_register1_clk',
14214 
        'clr' => 'sysgen_dut.to_register1_clr',
14215 
        'data_in' => 'sysgen_dut.to_register1_data_in',
14216 
        'dout' => 'to_register1.dout',
14217 
        'en' => 'sysgen_dut.to_register1_en',
14218 
      },
14219 
      'entity' => {
14220 
        'attributes' => {
14221 
          'entityAlreadyNetlisted' => 1,
14222 
          'generics' => [],
14223 
          'is_floating_block' => 1,
14224 
          'mask' => {
14225 
            'Block_Handle' => 38.0009765625,
14226 
            'Block_handle' => 38.0009765625,
14227 
            'MDL_Handle' => 3.0009765625,
14228 
            'MDL_handle' => 3.0009765625,
14229 
            'arith_type' => 1,
14230 
            'bin_pt' => 14,
14231 
            'block_config' => 'sysgen_blockset:toreg_config',
14232 
            'block_handle' => 38.0009765625,
14233 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14234 
            'block_type' => 'toreg',
14235 
            'dbl_ovrd' => 0,
14236 
            'explicit_data_type' => 0,
14237 
            'init' => 0,
14238 
            'init_bit_vector' => '00000000000000000000000000000000b',
14239 
            'mdl_handle' => 3.0009765625,
14240 
            'model_handle' => 3.0009765625,
14241 
            'n_bits' => 16,
14242 
            'ownership' => 1,
14243 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14244 
            'shared_memory_name' => 'debug2i',
14245 
          },
14246 
          'needs_vhdl_wrapper' => 0,
14247 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14248 
        },
14249 
        'entityName' => 'x',
14250 
        'ports' => {
14251 
          'ce' => {
14252 
            'attributes' => {
14253 
              'domain' => '',
14254 
              'group' => 1,
14255 
              'isCe' => 1,
14256 
              'is_floating_block' => 1,
14257 
              'period' => 1,
14258 
              'type' => 'logic',
14259 
            },
14260 
            'direction' => 'in',
14261 
            'hdlType' => 'std_logic',
14262 
            'width' => 1,
14263 
          },
14264 
          'clk' => {
14265 
            'attributes' => {
14266 
              'domain' => '',
14267 
              'group' => 1,
14268 
              'isClk' => 1,
14269 
              'is_floating_block' => 1,
14270 
              'period' => 1,
14271 
              'type' => 'logic',
14272 
            },
14273 
            'direction' => 'in',
14274 
            'hdlType' => 'std_logic',
14275 
            'width' => 1,
14276 
          },
14277 
          'clr' => {
14278 
            'attributes' => {
14279 
              'domain' => '',
14280 
              'group' => 1,
14281 
              'isClr' => 1,
14282 
              'is_floating_block' => 1,
14283 
              'period' => 1,
14284 
              'type' => 'logic',
14285 
              'valid_bit_used' => 0,
14286 
            },
14287 
            'direction' => 'in',
14288 
            'hdlType' => 'std_logic',
14289 
            'width' => 1,
14290 
          },
14291 
          'data_in' => {
14292 
            'attributes' => {
14293 
              'bin_pt' => 0,
14294 
              'is_floating_block' => 1,
14295 
              'must_be_hdl_vector' => 1,
14296 
              'period' => 1,
14297 
              'port_id' => 0,
14298 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
14299 
              'type' => 'UFix_32_0',
14300 
            },
14301 
            'direction' => 'in',
14302 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14303 
            'width' => 32,
14304 
          },
14305 
          'dout' => {
14306 
            'attributes' => {
14307 
              'bin_pt' => 0,
14308 
              'is_floating_block' => 1,
14309 
              'must_be_hdl_vector' => 1,
14310 
              'period' => 1,
14311 
              'port_id' => 0,
14312 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
14313 
              'type' => 'UFix_32_0',
14314 
            },
14315 
            'direction' => 'out',
14316 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14317 
            'width' => 32,
14318 
          },
14319 
          'en' => {
14320 
            'attributes' => {
14321 
              'bin_pt' => 0,
14322 
              'is_floating_block' => 1,
14323 
              'must_be_hdl_vector' => 1,
14324 
              'period' => 1,
14325 
              'port_id' => 1,
14326 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
14327 
              'type' => 'Bool',
14328 
            },
14329 
            'direction' => 'in',
14330 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14331 
            'width' => 1,
14332 
          },
14333 
        },
14334 
      },
14335 
      'entityName' => 'x',
14336 
    },
14337 
    'to_register10' => {
14338 
      'connections' => {
14339 
        'ce' => 'sysgen_dut.to_register10_ce',
14340 
        'clk' => 'sysgen_dut.to_register10_clk',
14341 
        'clr' => 'sysgen_dut.to_register10_clr',
14342 
        'data_in' => 'sysgen_dut.to_register10_data_in',
14343 
        'dout' => 'to_register10.dout',
14344 
        'en' => 'sysgen_dut.to_register10_en',
14345 
      },
14346 
      'entity' => {
14347 
        'attributes' => {
14348 
          'entityAlreadyNetlisted' => 1,
14349 
          'generics' => [],
14350 
          'is_floating_block' => 1,
14351 
          'mask' => {
14352 
            'Block_Handle' => 39.0009765625,
14353 
            'Block_handle' => 39.0009765625,
14354 
            'MDL_Handle' => 3.0009765625,
14355 
            'MDL_handle' => 3.0009765625,
14356 
            'arith_type' => 1,
14357 
            'bin_pt' => 14,
14358 
            'block_config' => 'sysgen_blockset:toreg_config',
14359 
            'block_handle' => 39.0009765625,
14360 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14361 
            'block_type' => 'toreg',
14362 
            'dbl_ovrd' => 0,
14363 
            'explicit_data_type' => 0,
14364 
            'init' => 0,
14365 
            'init_bit_vector' => '0b',
14366 
            'mdl_handle' => 3.0009765625,
14367 
            'model_handle' => 3.0009765625,
14368 
            'n_bits' => 16,
14369 
            'ownership' => 1,
14370 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14371 
            'shared_memory_name' => 'register04tv',
14372 
          },
14373 
          'needs_vhdl_wrapper' => 0,
14374 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14375 
        },
14376 
        'entityName' => 'x_x0',
14377 
        'ports' => {
14378 
          'ce' => {
14379 
            'attributes' => {
14380 
              'domain' => '',
14381 
              'group' => 1,
14382 
              'isCe' => 1,
14383 
              'is_floating_block' => 1,
14384 
              'period' => 1,
14385 
              'type' => 'logic',
14386 
            },
14387 
            'direction' => 'in',
14388 
            'hdlType' => 'std_logic',
14389 
            'width' => 1,
14390 
          },
14391 
          'clk' => {
14392 
            'attributes' => {
14393 
              'domain' => '',
14394 
              'group' => 1,
14395 
              'isClk' => 1,
14396 
              'is_floating_block' => 1,
14397 
              'period' => 1,
14398 
              'type' => 'logic',
14399 
            },
14400 
            'direction' => 'in',
14401 
            'hdlType' => 'std_logic',
14402 
            'width' => 1,
14403 
          },
14404 
          'clr' => {
14405 
            'attributes' => {
14406 
              'domain' => '',
14407 
              'group' => 1,
14408 
              'isClr' => 1,
14409 
              'is_floating_block' => 1,
14410 
              'period' => 1,
14411 
              'type' => 'logic',
14412 
              'valid_bit_used' => 0,
14413 
            },
14414 
            'direction' => 'in',
14415 
            'hdlType' => 'std_logic',
14416 
            'width' => 1,
14417 
          },
14418 
          'data_in' => {
14419 
            'attributes' => {
14420 
              'bin_pt' => 0,
14421 
              'is_floating_block' => 1,
14422 
              'must_be_hdl_vector' => 1,
14423 
              'period' => 1,
14424 
              'port_id' => 0,
14425 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
14426 
              'type' => 'Bool',
14427 
            },
14428 
            'direction' => 'in',
14429 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14430 
            'width' => 1,
14431 
          },
14432 
          'dout' => {
14433 
            'attributes' => {
14434 
              'bin_pt' => 0,
14435 
              'is_floating_block' => 1,
14436 
              'must_be_hdl_vector' => 1,
14437 
              'period' => 1,
14438 
              'port_id' => 0,
14439 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
14440 
              'type' => 'Bool',
14441 
            },
14442 
            'direction' => 'out',
14443 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14444 
            'width' => 1,
14445 
          },
14446 
          'en' => {
14447 
            'attributes' => {
14448 
              'bin_pt' => 0,
14449 
              'is_floating_block' => 1,
14450 
              'must_be_hdl_vector' => 1,
14451 
              'period' => 1,
14452 
              'port_id' => 1,
14453 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
14454 
              'type' => 'Bool',
14455 
            },
14456 
            'direction' => 'in',
14457 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14458 
            'width' => 1,
14459 
          },
14460 
        },
14461 
      },
14462 
      'entityName' => 'x_x0',
14463 
    },
14464 
    'to_register11' => {
14465 
      'connections' => {
14466 
        'ce' => 'sysgen_dut.to_register11_ce',
14467 
        'clk' => 'sysgen_dut.to_register11_clk',
14468 
        'clr' => 'sysgen_dut.to_register11_clr',
14469 
        'data_in' => 'sysgen_dut.to_register11_data_in',
14470 
        'dout' => 'to_register11.dout',
14471 
        'en' => 'sysgen_dut.to_register11_en',
14472 
      },
14473 
      'entity' => {
14474 
        'attributes' => {
14475 
          'entityAlreadyNetlisted' => 1,
14476 
          'generics' => [],
14477 
          'is_floating_block' => 1,
14478 
          'mask' => {
14479 
            'Block_Handle' => 40.0009765625,
14480 
            'Block_handle' => 40.0009765625,
14481 
            'MDL_Handle' => 3.0009765625,
14482 
            'MDL_handle' => 3.0009765625,
14483 
            'arith_type' => 1,
14484 
            'bin_pt' => 14,
14485 
            'block_config' => 'sysgen_blockset:toreg_config',
14486 
            'block_handle' => 40.0009765625,
14487 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14488 
            'block_type' => 'toreg',
14489 
            'dbl_ovrd' => 0,
14490 
            'explicit_data_type' => 0,
14491 
            'init' => 0,
14492 
            'init_bit_vector' => '00000000000000000000000000000000b',
14493 
            'mdl_handle' => 3.0009765625,
14494 
            'model_handle' => 3.0009765625,
14495 
            'n_bits' => 16,
14496 
            'ownership' => 1,
14497 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14498 
            'shared_memory_name' => 'register04td',
14499 
          },
14500 
          'needs_vhdl_wrapper' => 0,
14501 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14502 
        },
14503 
        'entityName' => 'x_x1',
14504 
        'ports' => {
14505 
          'ce' => {
14506 
            'attributes' => {
14507 
              'domain' => '',
14508 
              'group' => 1,
14509 
              'isCe' => 1,
14510 
              'is_floating_block' => 1,
14511 
              'period' => 1,
14512 
              'type' => 'logic',
14513 
            },
14514 
            'direction' => 'in',
14515 
            'hdlType' => 'std_logic',
14516 
            'width' => 1,
14517 
          },
14518 
          'clk' => {
14519 
            'attributes' => {
14520 
              'domain' => '',
14521 
              'group' => 1,
14522 
              'isClk' => 1,
14523 
              'is_floating_block' => 1,
14524 
              'period' => 1,
14525 
              'type' => 'logic',
14526 
            },
14527 
            'direction' => 'in',
14528 
            'hdlType' => 'std_logic',
14529 
            'width' => 1,
14530 
          },
14531 
          'clr' => {
14532 
            'attributes' => {
14533 
              'domain' => '',
14534 
              'group' => 1,
14535 
              'isClr' => 1,
14536 
              'is_floating_block' => 1,
14537 
              'period' => 1,
14538 
              'type' => 'logic',
14539 
              'valid_bit_used' => 0,
14540 
            },
14541 
            'direction' => 'in',
14542 
            'hdlType' => 'std_logic',
14543 
            'width' => 1,
14544 
          },
14545 
          'data_in' => {
14546 
            'attributes' => {
14547 
              'bin_pt' => 0,
14548 
              'is_floating_block' => 1,
14549 
              'must_be_hdl_vector' => 1,
14550 
              'period' => 1,
14551 
              'port_id' => 0,
14552 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
14553 
              'type' => 'UFix_32_0',
14554 
            },
14555 
            'direction' => 'in',
14556 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14557 
            'width' => 32,
14558 
          },
14559 
          'dout' => {
14560 
            'attributes' => {
14561 
              'bin_pt' => 0,
14562 
              'is_floating_block' => 1,
14563 
              'must_be_hdl_vector' => 1,
14564 
              'period' => 1,
14565 
              'port_id' => 0,
14566 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
14567 
              'type' => 'UFix_32_0',
14568 
            },
14569 
            'direction' => 'out',
14570 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14571 
            'width' => 32,
14572 
          },
14573 
          'en' => {
14574 
            'attributes' => {
14575 
              'bin_pt' => 0,
14576 
              'is_floating_block' => 1,
14577 
              'must_be_hdl_vector' => 1,
14578 
              'period' => 1,
14579 
              'port_id' => 1,
14580 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
14581 
              'type' => 'Bool',
14582 
            },
14583 
            'direction' => 'in',
14584 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14585 
            'width' => 1,
14586 
          },
14587 
        },
14588 
      },
14589 
      'entityName' => 'x_x1',
14590 
    },
14591 
    'to_register12' => {
14592 
      'connections' => {
14593 
        'ce' => 'sysgen_dut.to_register12_ce',
14594 
        'clk' => 'sysgen_dut.to_register12_clk',
14595 
        'clr' => 'sysgen_dut.to_register12_clr',
14596 
        'data_in' => 'sysgen_dut.to_register12_data_in',
14597 
        'dout' => 'to_register12.dout',
14598 
        'en' => 'sysgen_dut.to_register12_en',
14599 
      },
14600 
      'entity' => {
14601 
        'attributes' => {
14602 
          'entityAlreadyNetlisted' => 1,
14603 
          'generics' => [],
14604 
          'is_floating_block' => 1,
14605 
          'mask' => {
14606 
            'Block_Handle' => 41.0009765625,
14607 
            'Block_handle' => 41.0009765625,
14608 
            'MDL_Handle' => 3.0009765625,
14609 
            'MDL_handle' => 3.0009765625,
14610 
            'arith_type' => 1,
14611 
            'bin_pt' => 14,
14612 
            'block_config' => 'sysgen_blockset:toreg_config',
14613 
            'block_handle' => 41.0009765625,
14614 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
14615 
            'block_type' => 'toreg',
14616 
            'dbl_ovrd' => 0,
14617 
            'explicit_data_type' => 0,
14618 
            'init' => 0,
14619 
            'init_bit_vector' => '0b',
14620 
            'mdl_handle' => 3.0009765625,
14621 
            'model_handle' => 3.0009765625,
14622 
            'n_bits' => 16,
14623 
            'ownership' => 1,
14624 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14625 
            'shared_memory_name' => 'register05tv',
14626 
          },
14627 
          'needs_vhdl_wrapper' => 0,
14628 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
14629 
        },
14630 
        'entityName' => 'x_x2',
14631 
        'ports' => {
14632 
          'ce' => {
14633 
            'attributes' => {
14634 
              'domain' => '',
14635 
              'group' => 1,
14636 
              'isCe' => 1,
14637 
              'is_floating_block' => 1,
14638 
              'period' => 1,
14639 
              'type' => 'logic',
14640 
            },
14641 
            'direction' => 'in',
14642 
            'hdlType' => 'std_logic',
14643 
            'width' => 1,
14644 
          },
14645 
          'clk' => {
14646 
            'attributes' => {
14647 
              'domain' => '',
14648 
              'group' => 1,
14649 
              'isClk' => 1,
14650 
              'is_floating_block' => 1,
14651 
              'period' => 1,
14652 
              'type' => 'logic',
14653 
            },
14654 
            'direction' => 'in',
14655 
            'hdlType' => 'std_logic',
14656 
            'width' => 1,
14657 
          },
14658 
          'clr' => {
14659 
            'attributes' => {
14660 
              'domain' => '',
14661 
              'group' => 1,
14662 
              'isClr' => 1,
14663 
              'is_floating_block' => 1,
14664 
              'period' => 1,
14665 
              'type' => 'logic',
14666 
              'valid_bit_used' => 0,
14667 
            },
14668 
            'direction' => 'in',
14669 
            'hdlType' => 'std_logic',
14670 
            'width' => 1,
14671 
          },
14672 
          'data_in' => {
14673 
            'attributes' => {
14674 
              'bin_pt' => 0,
14675 
              'is_floating_block' => 1,
14676 
              'must_be_hdl_vector' => 1,
14677 
              'period' => 1,
14678 
              'port_id' => 0,
14679 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
14680 
              'type' => 'Bool',
14681 
            },
14682 
            'direction' => 'in',
14683 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14684 
            'width' => 1,
14685 
          },
14686 
          'dout' => {
14687 
            'attributes' => {
14688 
              'bin_pt' => 0,
14689 
              'is_floating_block' => 1,
14690 
              'must_be_hdl_vector' => 1,
14691 
              'period' => 1,
14692 
              'port_id' => 0,
14693 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
14694 
              'type' => 'Bool',
14695 
            },
14696 
            'direction' => 'out',
14697 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14698 
            'width' => 1,
14699 
          },
14700 
          'en' => {
14701 
            'attributes' => {
14702 
              'bin_pt' => 0,
14703 
              'is_floating_block' => 1,
14704 
              'must_be_hdl_vector' => 1,
14705 
              'period' => 1,
14706 
              'port_id' => 1,
14707 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
14708 
              'type' => 'Bool',
14709 
            },
14710 
            'direction' => 'in',
14711 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14712 
            'width' => 1,
14713 
          },
14714 
        },
14715 
      },
14716 
      'entityName' => 'x_x2',
14717 
    },
14718 
    'to_register13' => {
14719 
      'connections' => {
14720 
        'ce' => 'sysgen_dut.to_register13_ce',
14721 
        'clk' => 'sysgen_dut.to_register13_clk',
14722 
        'clr' => 'sysgen_dut.to_register13_clr',
14723 
        'data_in' => 'sysgen_dut.to_register13_data_in',
14724 
        'dout' => 'to_register13.dout',
14725 
        'en' => 'sysgen_dut.to_register13_en',
14726 
      },
14727 
      'entity' => {
14728 
        'attributes' => {
14729 
          'entityAlreadyNetlisted' => 1,
14730 
          'generics' => [],
14731 
          'is_floating_block' => 1,
14732 
          'mask' => {
14733 
            'Block_Handle' => 42.0009765625,
14734 
            'Block_handle' => 42.0009765625,
14735 
            'MDL_Handle' => 3.0009765625,
14736 
            'MDL_handle' => 3.0009765625,
14737 
            'arith_type' => 1,
14738 
            'bin_pt' => 14,
14739 
            'block_config' => 'sysgen_blockset:toreg_config',
14740 
            'block_handle' => 42.0009765625,
14741 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
14742 
            'block_type' => 'toreg',
14743 
            'dbl_ovrd' => 0,
14744 
            'explicit_data_type' => 0,
14745 
            'init' => 0,
14746 
            'init_bit_vector' => '00000000000000000000000000000000b',
14747 
            'mdl_handle' => 3.0009765625,
14748 
            'model_handle' => 3.0009765625,
14749 
            'n_bits' => 16,
14750 
            'ownership' => 1,
14751 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14752 
            'shared_memory_name' => 'register05td',
14753 
          },
14754 
          'needs_vhdl_wrapper' => 0,
14755 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
14756 
        },
14757 
        'entityName' => 'x_x3',
14758 
        'ports' => {
14759 
          'ce' => {
14760 
            'attributes' => {
14761 
              'domain' => '',
14762 
              'group' => 1,
14763 
              'isCe' => 1,
14764 
              'is_floating_block' => 1,
14765 
              'period' => 1,
14766 
              'type' => 'logic',
14767 
            },
14768 
            'direction' => 'in',
14769 
            'hdlType' => 'std_logic',
14770 
            'width' => 1,
14771 
          },
14772 
          'clk' => {
14773 
            'attributes' => {
14774 
              'domain' => '',
14775 
              'group' => 1,
14776 
              'isClk' => 1,
14777 
              'is_floating_block' => 1,
14778 
              'period' => 1,
14779 
              'type' => 'logic',
14780 
            },
14781 
            'direction' => 'in',
14782 
            'hdlType' => 'std_logic',
14783 
            'width' => 1,
14784 
          },
14785 
          'clr' => {
14786 
            'attributes' => {
14787 
              'domain' => '',
14788 
              'group' => 1,
14789 
              'isClr' => 1,
14790 
              'is_floating_block' => 1,
14791 
              'period' => 1,
14792 
              'type' => 'logic',
14793 
              'valid_bit_used' => 0,
14794 
            },
14795 
            'direction' => 'in',
14796 
            'hdlType' => 'std_logic',
14797 
            'width' => 1,
14798 
          },
14799 
          'data_in' => {
14800 
            'attributes' => {
14801 
              'bin_pt' => 0,
14802 
              'is_floating_block' => 1,
14803 
              'must_be_hdl_vector' => 1,
14804 
              'period' => 1,
14805 
              'port_id' => 0,
14806 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
14807 
              'type' => 'UFix_32_0',
14808 
            },
14809 
            'direction' => 'in',
14810 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14811 
            'width' => 32,
14812 
          },
14813 
          'dout' => {
14814 
            'attributes' => {
14815 
              'bin_pt' => 0,
14816 
              'is_floating_block' => 1,
14817 
              'must_be_hdl_vector' => 1,
14818 
              'period' => 1,
14819 
              'port_id' => 0,
14820 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
14821 
              'type' => 'UFix_32_0',
14822 
            },
14823 
            'direction' => 'out',
14824 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14825 
            'width' => 32,
14826 
          },
14827 
          'en' => {
14828 
            'attributes' => {
14829 
              'bin_pt' => 0,
14830 
              'is_floating_block' => 1,
14831 
              'must_be_hdl_vector' => 1,
14832 
              'period' => 1,
14833 
              'port_id' => 1,
14834 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
14835 
              'type' => 'Bool',
14836 
            },
14837 
            'direction' => 'in',
14838 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14839 
            'width' => 1,
14840 
          },
14841 
        },
14842 
      },
14843 
      'entityName' => 'x_x3',
14844 
    },
14845 
    'to_register14' => {
14846 
      'connections' => {
14847 
        'ce' => 'sysgen_dut.to_register14_ce',
14848 
        'clk' => 'sysgen_dut.to_register14_clk',
14849 
        'clr' => 'sysgen_dut.to_register14_clr',
14850 
        'data_in' => 'sysgen_dut.to_register14_data_in',
14851 
        'dout' => 'to_register14.dout',
14852 
        'en' => 'sysgen_dut.to_register14_en',
14853 
      },
14854 
      'entity' => {
14855 
        'attributes' => {
14856 
          'entityAlreadyNetlisted' => 1,
14857 
          'generics' => [],
14858 
          'is_floating_block' => 1,
14859 
          'mask' => {
14860 
            'Block_Handle' => 43.0009765625,
14861 
            'Block_handle' => 43.0009765625,
14862 
            'MDL_Handle' => 3.0009765625,
14863 
            'MDL_handle' => 3.0009765625,
14864 
            'arith_type' => 1,
14865 
            'bin_pt' => 14,
14866 
            'block_config' => 'sysgen_blockset:toreg_config',
14867 
            'block_handle' => 43.0009765625,
14868 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
14869 
            'block_type' => 'toreg',
14870 
            'dbl_ovrd' => 0,
14871 
            'explicit_data_type' => 0,
14872 
            'init' => 0,
14873 
            'init_bit_vector' => '0b',
14874 
            'mdl_handle' => 3.0009765625,
14875 
            'model_handle' => 3.0009765625,
14876 
            'n_bits' => 16,
14877 
            'ownership' => 1,
14878 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14879 
            'shared_memory_name' => 'register06tv',
14880 
          },
14881 
          'needs_vhdl_wrapper' => 0,
14882 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
14883 
        },
14884 
        'entityName' => 'x_x4',
14885 
        'ports' => {
14886 
          'ce' => {
14887 
            'attributes' => {
14888 
              'domain' => '',
14889 
              'group' => 1,
14890 
              'isCe' => 1,
14891 
              'is_floating_block' => 1,
14892 
              'period' => 1,
14893 
              'type' => 'logic',
14894 
            },
14895 
            'direction' => 'in',
14896 
            'hdlType' => 'std_logic',
14897 
            'width' => 1,
14898 
          },
14899 
          'clk' => {
14900 
            'attributes' => {
14901 
              'domain' => '',
14902 
              'group' => 1,
14903 
              'isClk' => 1,
14904 
              'is_floating_block' => 1,
14905 
              'period' => 1,
14906 
              'type' => 'logic',
14907 
            },
14908 
            'direction' => 'in',
14909 
            'hdlType' => 'std_logic',
14910 
            'width' => 1,
14911 
          },
14912 
          'clr' => {
14913 
            'attributes' => {
14914 
              'domain' => '',
14915 
              'group' => 1,
14916 
              'isClr' => 1,
14917 
              'is_floating_block' => 1,
14918 
              'period' => 1,
14919 
              'type' => 'logic',
14920 
              'valid_bit_used' => 0,
14921 
            },
14922 
            'direction' => 'in',
14923 
            'hdlType' => 'std_logic',
14924 
            'width' => 1,
14925 
          },
14926 
          'data_in' => {
14927 
            'attributes' => {
14928 
              'bin_pt' => 0,
14929 
              'is_floating_block' => 1,
14930 
              'must_be_hdl_vector' => 1,
14931 
              'period' => 1,
14932 
              'port_id' => 0,
14933 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
14934 
              'type' => 'Bool',
14935 
            },
14936 
            'direction' => 'in',
14937 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14938 
            'width' => 1,
14939 
          },
14940 
          'dout' => {
14941 
            'attributes' => {
14942 
              'bin_pt' => 0,
14943 
              'is_floating_block' => 1,
14944 
              'must_be_hdl_vector' => 1,
14945 
              'period' => 1,
14946 
              'port_id' => 0,
14947 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
14948 
              'type' => 'Bool',
14949 
            },
14950 
            'direction' => 'out',
14951 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14952 
            'width' => 1,
14953 
          },
14954 
          'en' => {
14955 
            'attributes' => {
14956 
              'bin_pt' => 0,
14957 
              'is_floating_block' => 1,
14958 
              'must_be_hdl_vector' => 1,
14959 
              'period' => 1,
14960 
              'port_id' => 1,
14961 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
14962 
              'type' => 'Bool',
14963 
            },
14964 
            'direction' => 'in',
14965 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14966 
            'width' => 1,
14967 
          },
14968 
        },
14969 
      },
14970 
      'entityName' => 'x_x4',
14971 
    },
14972 
    'to_register15' => {
14973 
      'connections' => {
14974 
        'ce' => 'sysgen_dut.to_register15_ce',
14975 
        'clk' => 'sysgen_dut.to_register15_clk',
14976 
        'clr' => 'sysgen_dut.to_register15_clr',
14977 
        'data_in' => 'sysgen_dut.to_register15_data_in',
14978 
        'dout' => 'to_register15.dout',
14979 
        'en' => 'sysgen_dut.to_register15_en',
14980 
      },
14981 
      'entity' => {
14982 
        'attributes' => {
14983 
          'entityAlreadyNetlisted' => 1,
14984 
          'generics' => [],
14985 
          'is_floating_block' => 1,
14986 
          'mask' => {
14987 
            'Block_Handle' => 44.0009765625,
14988 
            'Block_handle' => 44.0009765625,
14989 
            'MDL_Handle' => 3.0009765625,
14990 
            'MDL_handle' => 3.0009765625,
14991 
            'arith_type' => 1,
14992 
            'bin_pt' => 14,
14993 
            'block_config' => 'sysgen_blockset:toreg_config',
14994 
            'block_handle' => 44.0009765625,
14995 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
14996 
            'block_type' => 'toreg',
14997 
            'dbl_ovrd' => 0,
14998 
            'explicit_data_type' => 0,
14999 
            'init' => 0,
15000 
            'init_bit_vector' => '00000000000000000000000000000000b',
15001 
            'mdl_handle' => 3.0009765625,
15002 
            'model_handle' => 3.0009765625,
15003 
            'n_bits' => 16,
15004 
            'ownership' => 1,
15005 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15006 
            'shared_memory_name' => 'register06td',
15007 
          },
15008 
          'needs_vhdl_wrapper' => 0,
15009 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
15010 
        },
15011 
        'entityName' => 'x_x5',
15012 
        'ports' => {
15013 
          'ce' => {
15014 
            'attributes' => {
15015 
              'domain' => '',
15016 
              'group' => 1,
15017 
              'isCe' => 1,
15018 
              'is_floating_block' => 1,
15019 
              'period' => 1,
15020 
              'type' => 'logic',
15021 
            },
15022 
            'direction' => 'in',
15023 
            'hdlType' => 'std_logic',
15024 
            'width' => 1,
15025 
          },
15026 
          'clk' => {
15027 
            'attributes' => {
15028 
              'domain' => '',
15029 
              'group' => 1,
15030 
              'isClk' => 1,
15031 
              'is_floating_block' => 1,
15032 
              'period' => 1,
15033 
              'type' => 'logic',
15034 
            },
15035 
            'direction' => 'in',
15036 
            'hdlType' => 'std_logic',
15037 
            'width' => 1,
15038 
          },
15039 
          'clr' => {
15040 
            'attributes' => {
15041 
              'domain' => '',
15042 
              'group' => 1,
15043 
              'isClr' => 1,
15044 
              'is_floating_block' => 1,
15045 
              'period' => 1,
15046 
              'type' => 'logic',
15047 
              'valid_bit_used' => 0,
15048 
            },
15049 
            'direction' => 'in',
15050 
            'hdlType' => 'std_logic',
15051 
            'width' => 1,
15052 
          },
15053 
          'data_in' => {
15054 
            'attributes' => {
15055 
              'bin_pt' => 0,
15056 
              'is_floating_block' => 1,
15057 
              'must_be_hdl_vector' => 1,
15058 
              'period' => 1,
15059 
              'port_id' => 0,
15060 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
15061 
              'type' => 'UFix_32_0',
15062 
            },
15063 
            'direction' => 'in',
15064 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15065 
            'width' => 32,
15066 
          },
15067 
          'dout' => {
15068 
            'attributes' => {
15069 
              'bin_pt' => 0,
15070 
              'is_floating_block' => 1,
15071 
              'must_be_hdl_vector' => 1,
15072 
              'period' => 1,
15073 
              'port_id' => 0,
15074 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
15075 
              'type' => 'UFix_32_0',
15076 
            },
15077 
            'direction' => 'out',
15078 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15079 
            'width' => 32,
15080 
          },
15081 
          'en' => {
15082 
            'attributes' => {
15083 
              'bin_pt' => 0,
15084 
              'is_floating_block' => 1,
15085 
              'must_be_hdl_vector' => 1,
15086 
              'period' => 1,
15087 
              'port_id' => 1,
15088 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
15089 
              'type' => 'Bool',
15090 
            },
15091 
            'direction' => 'in',
15092 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15093 
            'width' => 1,
15094 
          },
15095 
        },
15096 
      },
15097 
      'entityName' => 'x_x5',
15098 
    },
15099 
    'to_register16' => {
15100 
      'connections' => {
15101 
        'ce' => 'sysgen_dut.to_register16_ce',
15102 
        'clk' => 'sysgen_dut.to_register16_clk',
15103 
        'clr' => 'sysgen_dut.to_register16_clr',
15104 
        'data_in' => 'sysgen_dut.to_register16_data_in',
15105 
        'dout' => 'to_register16.dout',
15106 
        'en' => 'sysgen_dut.to_register16_en',
15107 
      },
15108 
      'entity' => {
15109 
        'attributes' => {
15110 
          'entityAlreadyNetlisted' => 1,
15111 
          'generics' => [],
15112 
          'is_floating_block' => 1,
15113 
          'mask' => {
15114 
            'Block_Handle' => 45.0009765625,
15115 
            'Block_handle' => 45.0009765625,
15116 
            'MDL_Handle' => 3.0009765625,
15117 
            'MDL_handle' => 3.0009765625,
15118 
            'arith_type' => 1,
15119 
            'bin_pt' => 14,
15120 
            'block_config' => 'sysgen_blockset:toreg_config',
15121 
            'block_handle' => 45.0009765625,
15122 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15123 
            'block_type' => 'toreg',
15124 
            'dbl_ovrd' => 0,
15125 
            'explicit_data_type' => 0,
15126 
            'init' => 0,
15127 
            'init_bit_vector' => '0b',
15128 
            'mdl_handle' => 3.0009765625,
15129 
            'model_handle' => 3.0009765625,
15130 
            'n_bits' => 16,
15131 
            'ownership' => 1,
15132 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15133 
            'shared_memory_name' => 'register07tv',
15134 
          },
15135 
          'needs_vhdl_wrapper' => 0,
15136 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15137 
        },
15138 
        'entityName' => 'x_x6',
15139 
        'ports' => {
15140 
          'ce' => {
15141 
            'attributes' => {
15142 
              'domain' => '',
15143 
              'group' => 1,
15144 
              'isCe' => 1,
15145 
              'is_floating_block' => 1,
15146 
              'period' => 1,
15147 
              'type' => 'logic',
15148 
            },
15149 
            'direction' => 'in',
15150 
            'hdlType' => 'std_logic',
15151 
            'width' => 1,
15152 
          },
15153 
          'clk' => {
15154 
            'attributes' => {
15155 
              'domain' => '',
15156 
              'group' => 1,
15157 
              'isClk' => 1,
15158 
              'is_floating_block' => 1,
15159 
              'period' => 1,
15160 
              'type' => 'logic',
15161 
            },
15162 
            'direction' => 'in',
15163 
            'hdlType' => 'std_logic',
15164 
            'width' => 1,
15165 
          },
15166 
          'clr' => {
15167 
            'attributes' => {
15168 
              'domain' => '',
15169 
              'group' => 1,
15170 
              'isClr' => 1,
15171 
              'is_floating_block' => 1,
15172 
              'period' => 1,
15173 
              'type' => 'logic',
15174 
              'valid_bit_used' => 0,
15175 
            },
15176 
            'direction' => 'in',
15177 
            'hdlType' => 'std_logic',
15178 
            'width' => 1,
15179 
          },
15180 
          'data_in' => {
15181 
            'attributes' => {
15182 
              'bin_pt' => 0,
15183 
              'is_floating_block' => 1,
15184 
              'must_be_hdl_vector' => 1,
15185 
              'period' => 1,
15186 
              'port_id' => 0,
15187 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
15188 
              'type' => 'Bool',
15189 
            },
15190 
            'direction' => 'in',
15191 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15192 
            'width' => 1,
15193 
          },
15194 
          'dout' => {
15195 
            'attributes' => {
15196 
              'bin_pt' => 0,
15197 
              'is_floating_block' => 1,
15198 
              'must_be_hdl_vector' => 1,
15199 
              'period' => 1,
15200 
              'port_id' => 0,
15201 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
15202 
              'type' => 'Bool',
15203 
            },
15204 
            'direction' => 'out',
15205 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15206 
            'width' => 1,
15207 
          },
15208 
          'en' => {
15209 
            'attributes' => {
15210 
              'bin_pt' => 0,
15211 
              'is_floating_block' => 1,
15212 
              'must_be_hdl_vector' => 1,
15213 
              'period' => 1,
15214 
              'port_id' => 1,
15215 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
15216 
              'type' => 'Bool',
15217 
            },
15218 
            'direction' => 'in',
15219 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15220 
            'width' => 1,
15221 
          },
15222 
        },
15223 
      },
15224 
      'entityName' => 'x_x6',
15225 
    },
15226 
    'to_register17' => {
15227 
      'connections' => {
15228 
        'ce' => 'sysgen_dut.to_register17_ce',
15229 
        'clk' => 'sysgen_dut.to_register17_clk',
15230 
        'clr' => 'sysgen_dut.to_register17_clr',
15231 
        'data_in' => 'sysgen_dut.to_register17_data_in',
15232 
        'dout' => 'to_register17.dout',
15233 
        'en' => 'sysgen_dut.to_register17_en',
15234 
      },
15235 
      'entity' => {
15236 
        'attributes' => {
15237 
          'entityAlreadyNetlisted' => 1,
15238 
          'generics' => [],
15239 
          'is_floating_block' => 1,
15240 
          'mask' => {
15241 
            'Block_Handle' => 46.0009765625,
15242 
            'Block_handle' => 46.0009765625,
15243 
            'MDL_Handle' => 3.0009765625,
15244 
            'MDL_handle' => 3.0009765625,
15245 
            'arith_type' => 1,
15246 
            'bin_pt' => 14,
15247 
            'block_config' => 'sysgen_blockset:toreg_config',
15248 
            'block_handle' => 46.0009765625,
15249 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15250 
            'block_type' => 'toreg',
15251 
            'dbl_ovrd' => 0,
15252 
            'explicit_data_type' => 0,
15253 
            'init' => 0,
15254 
            'init_bit_vector' => '00000000000000000000000000000000b',
15255 
            'mdl_handle' => 3.0009765625,
15256 
            'model_handle' => 3.0009765625,
15257 
            'n_bits' => 16,
15258 
            'ownership' => 1,
15259 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15260 
            'shared_memory_name' => 'register07td',
15261 
          },
15262 
          'needs_vhdl_wrapper' => 0,
15263 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15264 
        },
15265 
        'entityName' => 'x_x7',
15266 
        'ports' => {
15267 
          'ce' => {
15268 
            'attributes' => {
15269 
              'domain' => '',
15270 
              'group' => 1,
15271 
              'isCe' => 1,
15272 
              'is_floating_block' => 1,
15273 
              'period' => 1,
15274 
              'type' => 'logic',
15275 
            },
15276 
            'direction' => 'in',
15277 
            'hdlType' => 'std_logic',
15278 
            'width' => 1,
15279 
          },
15280 
          'clk' => {
15281 
            'attributes' => {
15282 
              'domain' => '',
15283 
              'group' => 1,
15284 
              'isClk' => 1,
15285 
              'is_floating_block' => 1,
15286 
              'period' => 1,
15287 
              'type' => 'logic',
15288 
            },
15289 
            'direction' => 'in',
15290 
            'hdlType' => 'std_logic',
15291 
            'width' => 1,
15292 
          },
15293 
          'clr' => {
15294 
            'attributes' => {
15295 
              'domain' => '',
15296 
              'group' => 1,
15297 
              'isClr' => 1,
15298 
              'is_floating_block' => 1,
15299 
              'period' => 1,
15300 
              'type' => 'logic',
15301 
              'valid_bit_used' => 0,
15302 
            },
15303 
            'direction' => 'in',
15304 
            'hdlType' => 'std_logic',
15305 
            'width' => 1,
15306 
          },
15307 
          'data_in' => {
15308 
            'attributes' => {
15309 
              'bin_pt' => 0,
15310 
              'is_floating_block' => 1,
15311 
              'must_be_hdl_vector' => 1,
15312 
              'period' => 1,
15313 
              'port_id' => 0,
15314 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
15315 
              'type' => 'UFix_32_0',
15316 
            },
15317 
            'direction' => 'in',
15318 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15319 
            'width' => 32,
15320 
          },
15321 
          'dout' => {
15322 
            'attributes' => {
15323 
              'bin_pt' => 0,
15324 
              'is_floating_block' => 1,
15325 
              'must_be_hdl_vector' => 1,
15326 
              'period' => 1,
15327 
              'port_id' => 0,
15328 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
15329 
              'type' => 'UFix_32_0',
15330 
            },
15331 
            'direction' => 'out',
15332 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15333 
            'width' => 32,
15334 
          },
15335 
          'en' => {
15336 
            'attributes' => {
15337 
              'bin_pt' => 0,
15338 
              'is_floating_block' => 1,
15339 
              'must_be_hdl_vector' => 1,
15340 
              'period' => 1,
15341 
              'port_id' => 1,
15342 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
15343 
              'type' => 'Bool',
15344 
            },
15345 
            'direction' => 'in',
15346 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15347 
            'width' => 1,
15348 
          },
15349 
        },
15350 
      },
15351 
      'entityName' => 'x_x7',
15352 
    },
15353 
    'to_register18' => {
15354 
      'connections' => {
15355 
        'ce' => 'sysgen_dut.to_register18_ce',
15356 
        'clk' => 'sysgen_dut.to_register18_clk',
15357 
        'clr' => 'sysgen_dut.to_register18_clr',
15358 
        'data_in' => 'sysgen_dut.to_register18_data_in',
15359 
        'dout' => 'to_register18.dout',
15360 
        'en' => 'sysgen_dut.to_register18_en',
15361 
      },
15362 
      'entity' => {
15363 
        'attributes' => {
15364 
          'entityAlreadyNetlisted' => 1,
15365 
          'generics' => [],
15366 
          'is_floating_block' => 1,
15367 
          'mask' => {
15368 
            'Block_Handle' => 47.0009765625,
15369 
            'Block_handle' => 47.0009765625,
15370 
            'MDL_Handle' => 3.0009765625,
15371 
            'MDL_handle' => 3.0009765625,
15372 
            'arith_type' => 1,
15373 
            'bin_pt' => 14,
15374 
            'block_config' => 'sysgen_blockset:toreg_config',
15375 
            'block_handle' => 47.0009765625,
15376 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15377 
            'block_type' => 'toreg',
15378 
            'dbl_ovrd' => 0,
15379 
            'explicit_data_type' => 0,
15380 
            'init' => 0,
15381 
            'init_bit_vector' => '0b',
15382 
            'mdl_handle' => 3.0009765625,
15383 
            'model_handle' => 3.0009765625,
15384 
            'n_bits' => 16,
15385 
            'ownership' => 1,
15386 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15387 
            'shared_memory_name' => 'DMA_Host2Board_Busy',
15388 
          },
15389 
          'needs_vhdl_wrapper' => 0,
15390 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15391 
        },
15392 
        'entityName' => 'x_x8',
15393 
        'ports' => {
15394 
          'ce' => {
15395 
            'attributes' => {
15396 
              'domain' => '',
15397 
              'group' => 1,
15398 
              'isCe' => 1,
15399 
              'is_floating_block' => 1,
15400 
              'period' => 1,
15401 
              'type' => 'logic',
15402 
            },
15403 
            'direction' => 'in',
15404 
            'hdlType' => 'std_logic',
15405 
            'width' => 1,
15406 
          },
15407 
          'clk' => {
15408 
            'attributes' => {
15409 
              'domain' => '',
15410 
              'group' => 1,
15411 
              'isClk' => 1,
15412 
              'is_floating_block' => 1,
15413 
              'period' => 1,
15414 
              'type' => 'logic',
15415 
            },
15416 
            'direction' => 'in',
15417 
            'hdlType' => 'std_logic',
15418 
            'width' => 1,
15419 
          },
15420 
          'clr' => {
15421 
            'attributes' => {
15422 
              'domain' => '',
15423 
              'group' => 1,
15424 
              'isClr' => 1,
15425 
              'is_floating_block' => 1,
15426 
              'period' => 1,
15427 
              'type' => 'logic',
15428 
              'valid_bit_used' => 0,
15429 
            },
15430 
            'direction' => 'in',
15431 
            'hdlType' => 'std_logic',
15432 
            'width' => 1,
15433 
          },
15434 
          'data_in' => {
15435 
            'attributes' => {
15436 
              'bin_pt' => 0,
15437 
              'is_floating_block' => 1,
15438 
              'must_be_hdl_vector' => 1,
15439 
              'period' => 1,
15440 
              'port_id' => 0,
15441 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
15442 
              'type' => 'UFix_1_0',
15443 
            },
15444 
            'direction' => 'in',
15445 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15446 
            'width' => 1,
15447 
          },
15448 
          'dout' => {
15449 
            'attributes' => {
15450 
              'bin_pt' => 0,
15451 
              'is_floating_block' => 1,
15452 
              'must_be_hdl_vector' => 1,
15453 
              'period' => 1,
15454 
              'port_id' => 0,
15455 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
15456 
              'type' => 'UFix_1_0',
15457 
            },
15458 
            'direction' => 'out',
15459 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15460 
            'width' => 1,
15461 
          },
15462 
          'en' => {
15463 
            'attributes' => {
15464 
              'bin_pt' => 0,
15465 
              'is_floating_block' => 1,
15466 
              'must_be_hdl_vector' => 1,
15467 
              'period' => 1,
15468 
              'port_id' => 1,
15469 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
15470 
              'type' => 'Bool',
15471 
            },
15472 
            'direction' => 'in',
15473 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15474 
            'width' => 1,
15475 
          },
15476 
        },
15477 
      },
15478 
      'entityName' => 'x_x8',
15479 
    },
15480 
    'to_register19' => {
15481 
      'connections' => {
15482 
        'ce' => 'sysgen_dut.to_register19_ce',
15483 
        'clk' => 'sysgen_dut.to_register19_clk',
15484 
        'clr' => 'sysgen_dut.to_register19_clr',
15485 
        'data_in' => 'sysgen_dut.to_register19_data_in',
15486 
        'dout' => 'to_register19.dout',
15487 
        'en' => 'sysgen_dut.to_register19_en',
15488 
      },
15489 
      'entity' => {
15490 
        'attributes' => {
15491 
          'entityAlreadyNetlisted' => 1,
15492 
          'generics' => [],
15493 
          'is_floating_block' => 1,
15494 
          'mask' => {
15495 
            'Block_Handle' => 48.0009765625,
15496 
            'Block_handle' => 48.0009765625,
15497 
            'MDL_Handle' => 3.0009765625,
15498 
            'MDL_handle' => 3.0009765625,
15499 
            'arith_type' => 1,
15500 
            'bin_pt' => 14,
15501 
            'block_config' => 'sysgen_blockset:toreg_config',
15502 
            'block_handle' => 48.0009765625,
15503 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
15504 
            'block_type' => 'toreg',
15505 
            'dbl_ovrd' => 0,
15506 
            'explicit_data_type' => 0,
15507 
            'init' => 0,
15508 
            'init_bit_vector' => '0b',
15509 
            'mdl_handle' => 3.0009765625,
15510 
            'model_handle' => 3.0009765625,
15511 
            'n_bits' => 16,
15512 
            'ownership' => 1,
15513 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15514 
            'shared_memory_name' => 'DMA_Host2Board_Done',
15515 
          },
15516 
          'needs_vhdl_wrapper' => 0,
15517 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
15518 
        },
15519 
        'entityName' => 'x_x9',
15520 
        'ports' => {
15521 
          'ce' => {
15522 
            'attributes' => {
15523 
              'domain' => '',
15524 
              'group' => 1,
15525 
              'isCe' => 1,
15526 
              'is_floating_block' => 1,
15527 
              'period' => 1,
15528 
              'type' => 'logic',
15529 
            },
15530 
            'direction' => 'in',
15531 
            'hdlType' => 'std_logic',
15532 
            'width' => 1,
15533 
          },
15534 
          'clk' => {
15535 
            'attributes' => {
15536 
              'domain' => '',
15537 
              'group' => 1,
15538 
              'isClk' => 1,
15539 
              'is_floating_block' => 1,
15540 
              'period' => 1,
15541 
              'type' => 'logic',
15542 
            },
15543 
            'direction' => 'in',
15544 
            'hdlType' => 'std_logic',
15545 
            'width' => 1,
15546 
          },
15547 
          'clr' => {
15548 
            'attributes' => {
15549 
              'domain' => '',
15550 
              'group' => 1,
15551 
              'isClr' => 1,
15552 
              'is_floating_block' => 1,
15553 
              'period' => 1,
15554 
              'type' => 'logic',
15555 
              'valid_bit_used' => 0,
15556 
            },
15557 
            'direction' => 'in',
15558 
            'hdlType' => 'std_logic',
15559 
            'width' => 1,
15560 
          },
15561 
          'data_in' => {
15562 
            'attributes' => {
15563 
              'bin_pt' => 0,
15564 
              'is_floating_block' => 1,
15565 
              'must_be_hdl_vector' => 1,
15566 
              'period' => 1,
15567 
              'port_id' => 0,
15568 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
15569 
              'type' => 'UFix_1_0',
15570 
            },
15571 
            'direction' => 'in',
15572 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15573 
            'width' => 1,
15574 
          },
15575 
          'dout' => {
15576 
            'attributes' => {
15577 
              'bin_pt' => 0,
15578 
              'is_floating_block' => 1,
15579 
              'must_be_hdl_vector' => 1,
15580 
              'period' => 1,
15581 
              'port_id' => 0,
15582 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
15583 
              'type' => 'UFix_1_0',
15584 
            },
15585 
            'direction' => 'out',
15586 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15587 
            'width' => 1,
15588 
          },
15589 
          'en' => {
15590 
            'attributes' => {
15591 
              'bin_pt' => 0,
15592 
              'is_floating_block' => 1,
15593 
              'must_be_hdl_vector' => 1,
15594 
              'period' => 1,
15595 
              'port_id' => 1,
15596 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
15597 
              'type' => 'Bool',
15598 
            },
15599 
            'direction' => 'in',
15600 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15601 
            'width' => 1,
15602 
          },
15603 
        },
15604 
      },
15605 
      'entityName' => 'x_x9',
15606 
    },
15607 
    'to_register2' => {
15608 
      'connections' => {
15609 
        'ce' => 'sysgen_dut.to_register2_ce',
15610 
        'clk' => 'sysgen_dut.to_register2_clk',
15611 
        'clr' => 'sysgen_dut.to_register2_clr',
15612 
        'data_in' => 'sysgen_dut.to_register2_data_in',
15613 
        'dout' => 'to_register2.dout',
15614 
        'en' => 'sysgen_dut.to_register2_en',
15615 
      },
15616 
      'entity' => {
15617 
        'attributes' => {
15618 
          'entityAlreadyNetlisted' => 1,
15619 
          'generics' => [],
15620 
          'is_floating_block' => 1,
15621 
          'mask' => {
15622 
            'Block_Handle' => 49.0009765625,
15623 
            'Block_handle' => 49.0009765625,
15624 
            'MDL_Handle' => 3.0009765625,
15625 
            'MDL_handle' => 3.0009765625,
15626 
            'arith_type' => 1,
15627 
            'bin_pt' => 14,
15628 
            'block_config' => 'sysgen_blockset:toreg_config',
15629 
            'block_handle' => 49.0009765625,
15630 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
15631 
            'block_type' => 'toreg',
15632 
            'dbl_ovrd' => 0,
15633 
            'explicit_data_type' => 0,
15634 
            'init' => 0,
15635 
            'init_bit_vector' => '00000000000000000000000000000000b',
15636 
            'mdl_handle' => 3.0009765625,
15637 
            'model_handle' => 3.0009765625,
15638 
            'n_bits' => 16,
15639 
            'ownership' => 1,
15640 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15641 
            'shared_memory_name' => 'debug3i',
15642 
          },
15643 
          'needs_vhdl_wrapper' => 0,
15644 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
15645 
        },
15646 
        'entityName' => 'x_x10',
15647 
        'ports' => {
15648 
          'ce' => {
15649 
            'attributes' => {
15650 
              'domain' => '',
15651 
              'group' => 1,
15652 
              'isCe' => 1,
15653 
              'is_floating_block' => 1,
15654 
              'period' => 1,
15655 
              'type' => 'logic',
15656 
            },
15657 
            'direction' => 'in',
15658 
            'hdlType' => 'std_logic',
15659 
            'width' => 1,
15660 
          },
15661 
          'clk' => {
15662 
            'attributes' => {
15663 
              'domain' => '',
15664 
              'group' => 1,
15665 
              'isClk' => 1,
15666 
              'is_floating_block' => 1,
15667 
              'period' => 1,
15668 
              'type' => 'logic',
15669 
            },
15670 
            'direction' => 'in',
15671 
            'hdlType' => 'std_logic',
15672 
            'width' => 1,
15673 
          },
15674 
          'clr' => {
15675 
            'attributes' => {
15676 
              'domain' => '',
15677 
              'group' => 1,
15678 
              'isClr' => 1,
15679 
              'is_floating_block' => 1,
15680 
              'period' => 1,
15681 
              'type' => 'logic',
15682 
              'valid_bit_used' => 0,
15683 
            },
15684 
            'direction' => 'in',
15685 
            'hdlType' => 'std_logic',
15686 
            'width' => 1,
15687 
          },
15688 
          'data_in' => {
15689 
            'attributes' => {
15690 
              'bin_pt' => 0,
15691 
              'is_floating_block' => 1,
15692 
              'must_be_hdl_vector' => 1,
15693 
              'period' => 1,
15694 
              'port_id' => 0,
15695 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
15696 
              'type' => 'UFix_32_0',
15697 
            },
15698 
            'direction' => 'in',
15699 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15700 
            'width' => 32,
15701 
          },
15702 
          'dout' => {
15703 
            'attributes' => {
15704 
              'bin_pt' => 0,
15705 
              'is_floating_block' => 1,
15706 
              'must_be_hdl_vector' => 1,
15707 
              'period' => 1,
15708 
              'port_id' => 0,
15709 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
15710 
              'type' => 'UFix_32_0',
15711 
            },
15712 
            'direction' => 'out',
15713 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15714 
            'width' => 32,
15715 
          },
15716 
          'en' => {
15717 
            'attributes' => {
15718 
              'bin_pt' => 0,
15719 
              'is_floating_block' => 1,
15720 
              'must_be_hdl_vector' => 1,
15721 
              'period' => 1,
15722 
              'port_id' => 1,
15723 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
15724 
              'type' => 'Bool',
15725 
            },
15726 
            'direction' => 'in',
15727 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15728 
            'width' => 1,
15729 
          },
15730 
        },
15731 
      },
15732 
      'entityName' => 'x_x10',
15733 
    },
15734 
    'to_register20' => {
15735 
      'connections' => {
15736 
        'ce' => 'sysgen_dut.to_register20_ce',
15737 
        'clk' => 'sysgen_dut.to_register20_clk',
15738 
        'clr' => 'sysgen_dut.to_register20_clr',
15739 
        'data_in' => 'sysgen_dut.to_register20_data_in',
15740 
        'dout' => 'to_register20.dout',
15741 
        'en' => 'sysgen_dut.to_register20_en',
15742 
      },
15743 
      'entity' => {
15744 
        'attributes' => {
15745 
          'entityAlreadyNetlisted' => 1,
15746 
          'generics' => [],
15747 
          'is_floating_block' => 1,
15748 
          'mask' => {
15749 
            'Block_Handle' => 50.0009765625,
15750 
            'Block_handle' => 50.0009765625,
15751 
            'MDL_Handle' => 3.0009765625,
15752 
            'MDL_handle' => 3.0009765625,
15753 
            'arith_type' => 1,
15754 
            'bin_pt' => 14,
15755 
            'block_config' => 'sysgen_blockset:toreg_config',
15756 
            'block_handle' => 50.0009765625,
15757 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
15758 
            'block_type' => 'toreg',
15759 
            'dbl_ovrd' => 0,
15760 
            'explicit_data_type' => 0,
15761 
            'init' => 0,
15762 
            'init_bit_vector' => '00000000000000000000000000000000b',
15763 
            'mdl_handle' => 3.0009765625,
15764 
            'model_handle' => 3.0009765625,
15765 
            'n_bits' => 16,
15766 
            'ownership' => 1,
15767 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15768 
            'shared_memory_name' => 'debug4i',
15769 
          },
15770 
          'needs_vhdl_wrapper' => 0,
15771 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
15772 
        },
15773 
        'entityName' => 'x_x11',
15774 
        'ports' => {
15775 
          'ce' => {
15776 
            'attributes' => {
15777 
              'domain' => '',
15778 
              'group' => 1,
15779 
              'isCe' => 1,
15780 
              'is_floating_block' => 1,
15781 
              'period' => 1,
15782 
              'type' => 'logic',
15783 
            },
15784 
            'direction' => 'in',
15785 
            'hdlType' => 'std_logic',
15786 
            'width' => 1,
15787 
          },
15788 
          'clk' => {
15789 
            'attributes' => {
15790 
              'domain' => '',
15791 
              'group' => 1,
15792 
              'isClk' => 1,
15793 
              'is_floating_block' => 1,
15794 
              'period' => 1,
15795 
              'type' => 'logic',
15796 
            },
15797 
            'direction' => 'in',
15798 
            'hdlType' => 'std_logic',
15799 
            'width' => 1,
15800 
          },
15801 
          'clr' => {
15802 
            'attributes' => {
15803 
              'domain' => '',
15804 
              'group' => 1,
15805 
              'isClr' => 1,
15806 
              'is_floating_block' => 1,
15807 
              'period' => 1,
15808 
              'type' => 'logic',
15809 
              'valid_bit_used' => 0,
15810 
            },
15811 
            'direction' => 'in',
15812 
            'hdlType' => 'std_logic',
15813 
            'width' => 1,
15814 
          },
15815 
          'data_in' => {
15816 
            'attributes' => {
15817 
              'bin_pt' => 0,
15818 
              'is_floating_block' => 1,
15819 
              'must_be_hdl_vector' => 1,
15820 
              'period' => 1,
15821 
              'port_id' => 0,
15822 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
15823 
              'type' => 'UFix_32_0',
15824 
            },
15825 
            'direction' => 'in',
15826 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15827 
            'width' => 32,
15828 
          },
15829 
          'dout' => {
15830 
            'attributes' => {
15831 
              'bin_pt' => 0,
15832 
              'is_floating_block' => 1,
15833 
              'must_be_hdl_vector' => 1,
15834 
              'period' => 1,
15835 
              'port_id' => 0,
15836 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
15837 
              'type' => 'UFix_32_0',
15838 
            },
15839 
            'direction' => 'out',
15840 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15841 
            'width' => 32,
15842 
          },
15843 
          'en' => {
15844 
            'attributes' => {
15845 
              'bin_pt' => 0,
15846 
              'is_floating_block' => 1,
15847 
              'must_be_hdl_vector' => 1,
15848 
              'period' => 1,
15849 
              'port_id' => 1,
15850 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
15851 
              'type' => 'Bool',
15852 
            },
15853 
            'direction' => 'in',
15854 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15855 
            'width' => 1,
15856 
          },
15857 
        },
15858 
      },
15859 
      'entityName' => 'x_x11',
15860 
    },
15861 
    'to_register21' => {
15862 
      'connections' => {
15863 
        'ce' => 'sysgen_dut.to_register21_ce',
15864 
        'clk' => 'sysgen_dut.to_register21_clk',
15865 
        'clr' => 'sysgen_dut.to_register21_clr',
15866 
        'data_in' => 'sysgen_dut.to_register21_data_in',
15867 
        'dout' => 'to_register21.dout',
15868 
        'en' => 'sysgen_dut.to_register21_en',
15869 
      },
15870 
      'entity' => {
15871 
        'attributes' => {
15872 
          'entityAlreadyNetlisted' => 1,
15873 
          'generics' => [],
15874 
          'is_floating_block' => 1,
15875 
          'mask' => {
15876 
            'Block_Handle' => 51.0009765625,
15877 
            'Block_handle' => 51.0009765625,
15878 
            'MDL_Handle' => 3.0009765625,
15879 
            'MDL_handle' => 3.0009765625,
15880 
            'arith_type' => 1,
15881 
            'bin_pt' => 14,
15882 
            'block_config' => 'sysgen_blockset:toreg_config',
15883 
            'block_handle' => 51.0009765625,
15884 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
15885 
            'block_type' => 'toreg',
15886 
            'dbl_ovrd' => 0,
15887 
            'explicit_data_type' => 0,
15888 
            'init' => 0,
15889 
            'init_bit_vector' => '0b',
15890 
            'mdl_handle' => 3.0009765625,
15891 
            'model_handle' => 3.0009765625,
15892 
            'n_bits' => 16,
15893 
            'ownership' => 1,
15894 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15895 
            'shared_memory_name' => 'register09tv',
15896 
          },
15897 
          'needs_vhdl_wrapper' => 0,
15898 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
15899 
        },
15900 
        'entityName' => 'x_x12',
15901 
        'ports' => {
15902 
          'ce' => {
15903 
            'attributes' => {
15904 
              'domain' => '',
15905 
              'group' => 1,
15906 
              'isCe' => 1,
15907 
              'is_floating_block' => 1,
15908 
              'period' => 1,
15909 
              'type' => 'logic',
15910 
            },
15911 
            'direction' => 'in',
15912 
            'hdlType' => 'std_logic',
15913 
            'width' => 1,
15914 
          },
15915 
          'clk' => {
15916 
            'attributes' => {
15917 
              'domain' => '',
15918 
              'group' => 1,
15919 
              'isClk' => 1,
15920 
              'is_floating_block' => 1,
15921 
              'period' => 1,
15922 
              'type' => 'logic',
15923 
            },
15924 
            'direction' => 'in',
15925 
            'hdlType' => 'std_logic',
15926 
            'width' => 1,
15927 
          },
15928 
          'clr' => {
15929 
            'attributes' => {
15930 
              'domain' => '',
15931 
              'group' => 1,
15932 
              'isClr' => 1,
15933 
              'is_floating_block' => 1,
15934 
              'period' => 1,
15935 
              'type' => 'logic',
15936 
              'valid_bit_used' => 0,
15937 
            },
15938 
            'direction' => 'in',
15939 
            'hdlType' => 'std_logic',
15940 
            'width' => 1,
15941 
          },
15942 
          'data_in' => {
15943 
            'attributes' => {
15944 
              'bin_pt' => 0,
15945 
              'is_floating_block' => 1,
15946 
              'must_be_hdl_vector' => 1,
15947 
              'period' => 1,
15948 
              'port_id' => 0,
15949 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
15950 
              'type' => 'Bool',
15951 
            },
15952 
            'direction' => 'in',
15953 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15954 
            'width' => 1,
15955 
          },
15956 
          'dout' => {
15957 
            'attributes' => {
15958 
              'bin_pt' => 0,
15959 
              'is_floating_block' => 1,
15960 
              'must_be_hdl_vector' => 1,
15961 
              'period' => 1,
15962 
              'port_id' => 0,
15963 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
15964 
              'type' => 'Bool',
15965 
            },
15966 
            'direction' => 'out',
15967 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15968 
            'width' => 1,
15969 
          },
15970 
          'en' => {
15971 
            'attributes' => {
15972 
              'bin_pt' => 0,
15973 
              'is_floating_block' => 1,
15974 
              'must_be_hdl_vector' => 1,
15975 
              'period' => 1,
15976 
              'port_id' => 1,
15977 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
15978 
              'type' => 'Bool',
15979 
            },
15980 
            'direction' => 'in',
15981 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15982 
            'width' => 1,
15983 
          },
15984 
        },
15985 
      },
15986 
      'entityName' => 'x_x12',
15987 
    },
15988 
    'to_register22' => {
15989 
      'connections' => {
15990 
        'ce' => 'sysgen_dut.to_register22_ce',
15991 
        'clk' => 'sysgen_dut.to_register22_clk',
15992 
        'clr' => 'sysgen_dut.to_register22_clr',
15993 
        'data_in' => 'sysgen_dut.to_register22_data_in',
15994 
        'dout' => 'to_register22.dout',
15995 
        'en' => 'sysgen_dut.to_register22_en',
15996 
      },
15997 
      'entity' => {
15998 
        'attributes' => {
15999 
          'entityAlreadyNetlisted' => 1,
16000 
          'generics' => [],
16001 
          'is_floating_block' => 1,
16002 
          'mask' => {
16003 
            'Block_Handle' => 52.0009765625,
16004 
            'Block_handle' => 52.0009765625,
16005 
            'MDL_Handle' => 3.0009765625,
16006 
            'MDL_handle' => 3.0009765625,
16007 
            'arith_type' => 1,
16008 
            'bin_pt' => 14,
16009 
            'block_config' => 'sysgen_blockset:toreg_config',
16010 
            'block_handle' => 52.0009765625,
16011 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16012 
            'block_type' => 'toreg',
16013 
            'dbl_ovrd' => 0,
16014 
            'explicit_data_type' => 0,
16015 
            'init' => 0,
16016 
            'init_bit_vector' => '00000000000000000000000000000000b',
16017 
            'mdl_handle' => 3.0009765625,
16018 
            'model_handle' => 3.0009765625,
16019 
            'n_bits' => 16,
16020 
            'ownership' => 1,
16021 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16022 
            'shared_memory_name' => 'register09td',
16023 
          },
16024 
          'needs_vhdl_wrapper' => 0,
16025 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16026 
        },
16027 
        'entityName' => 'x_x13',
16028 
        'ports' => {
16029 
          'ce' => {
16030 
            'attributes' => {
16031 
              'domain' => '',
16032 
              'group' => 1,
16033 
              'isCe' => 1,
16034 
              'is_floating_block' => 1,
16035 
              'period' => 1,
16036 
              'type' => 'logic',
16037 
            },
16038 
            'direction' => 'in',
16039 
            'hdlType' => 'std_logic',
16040 
            'width' => 1,
16041 
          },
16042 
          'clk' => {
16043 
            'attributes' => {
16044 
              'domain' => '',
16045 
              'group' => 1,
16046 
              'isClk' => 1,
16047 
              'is_floating_block' => 1,
16048 
              'period' => 1,
16049 
              'type' => 'logic',
16050 
            },
16051 
            'direction' => 'in',
16052 
            'hdlType' => 'std_logic',
16053 
            'width' => 1,
16054 
          },
16055 
          'clr' => {
16056 
            'attributes' => {
16057 
              'domain' => '',
16058 
              'group' => 1,
16059 
              'isClr' => 1,
16060 
              'is_floating_block' => 1,
16061 
              'period' => 1,
16062 
              'type' => 'logic',
16063 
              'valid_bit_used' => 0,
16064 
            },
16065 
            'direction' => 'in',
16066 
            'hdlType' => 'std_logic',
16067 
            'width' => 1,
16068 
          },
16069 
          'data_in' => {
16070 
            'attributes' => {
16071 
              'bin_pt' => 0,
16072 
              'is_floating_block' => 1,
16073 
              'must_be_hdl_vector' => 1,
16074 
              'period' => 1,
16075 
              'port_id' => 0,
16076 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
16077 
              'type' => 'UFix_32_0',
16078 
            },
16079 
            'direction' => 'in',
16080 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16081 
            'width' => 32,
16082 
          },
16083 
          'dout' => {
16084 
            'attributes' => {
16085 
              'bin_pt' => 0,
16086 
              'is_floating_block' => 1,
16087 
              'must_be_hdl_vector' => 1,
16088 
              'period' => 1,
16089 
              'port_id' => 0,
16090 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
16091 
              'type' => 'UFix_32_0',
16092 
            },
16093 
            'direction' => 'out',
16094 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16095 
            'width' => 32,
16096 
          },
16097 
          'en' => {
16098 
            'attributes' => {
16099 
              'bin_pt' => 0,
16100 
              'is_floating_block' => 1,
16101 
              'must_be_hdl_vector' => 1,
16102 
              'period' => 1,
16103 
              'port_id' => 1,
16104 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
16105 
              'type' => 'Bool',
16106 
            },
16107 
            'direction' => 'in',
16108 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16109 
            'width' => 1,
16110 
          },
16111 
        },
16112 
      },
16113 
      'entityName' => 'x_x13',
16114 
    },
16115 
    'to_register23' => {
16116 
      'connections' => {
16117 
        'ce' => 'sysgen_dut.to_register23_ce',
16118 
        'clk' => 'sysgen_dut.to_register23_clk',
16119 
        'clr' => 'sysgen_dut.to_register23_clr',
16120 
        'data_in' => 'sysgen_dut.to_register23_data_in',
16121 
        'dout' => 'to_register23.dout',
16122 
        'en' => 'sysgen_dut.to_register23_en',
16123 
      },
16124 
      'entity' => {
16125 
        'attributes' => {
16126 
          'entityAlreadyNetlisted' => 1,
16127 
          'generics' => [],
16128 
          'is_floating_block' => 1,
16129 
          'mask' => {
16130 
            'Block_Handle' => 53.0009765625,
16131 
            'Block_handle' => 53.0009765625,
16132 
            'MDL_Handle' => 3.0009765625,
16133 
            'MDL_handle' => 3.0009765625,
16134 
            'arith_type' => 1,
16135 
            'bin_pt' => 14,
16136 
            'block_config' => 'sysgen_blockset:toreg_config',
16137 
            'block_handle' => 53.0009765625,
16138 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16139 
            'block_type' => 'toreg',
16140 
            'dbl_ovrd' => 0,
16141 
            'explicit_data_type' => 0,
16142 
            'init' => 0,
16143 
            'init_bit_vector' => '0b',
16144 
            'mdl_handle' => 3.0009765625,
16145 
            'model_handle' => 3.0009765625,
16146 
            'n_bits' => 16,
16147 
            'ownership' => 1,
16148 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16149 
            'shared_memory_name' => 'register10tv',
16150 
          },
16151 
          'needs_vhdl_wrapper' => 0,
16152 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16153 
        },
16154 
        'entityName' => 'x_x14',
16155 
        'ports' => {
16156 
          'ce' => {
16157 
            'attributes' => {
16158 
              'domain' => '',
16159 
              'group' => 1,
16160 
              'isCe' => 1,
16161 
              'is_floating_block' => 1,
16162 
              'period' => 1,
16163 
              'type' => 'logic',
16164 
            },
16165 
            'direction' => 'in',
16166 
            'hdlType' => 'std_logic',
16167 
            'width' => 1,
16168 
          },
16169 
          'clk' => {
16170 
            'attributes' => {
16171 
              'domain' => '',
16172 
              'group' => 1,
16173 
              'isClk' => 1,
16174 
              'is_floating_block' => 1,
16175 
              'period' => 1,
16176 
              'type' => 'logic',
16177 
            },
16178 
            'direction' => 'in',
16179 
            'hdlType' => 'std_logic',
16180 
            'width' => 1,
16181 
          },
16182 
          'clr' => {
16183 
            'attributes' => {
16184 
              'domain' => '',
16185 
              'group' => 1,
16186 
              'isClr' => 1,
16187 
              'is_floating_block' => 1,
16188 
              'period' => 1,
16189 
              'type' => 'logic',
16190 
              'valid_bit_used' => 0,
16191 
            },
16192 
            'direction' => 'in',
16193 
            'hdlType' => 'std_logic',
16194 
            'width' => 1,
16195 
          },
16196 
          'data_in' => {
16197 
            'attributes' => {
16198 
              'bin_pt' => 0,
16199 
              'is_floating_block' => 1,
16200 
              'must_be_hdl_vector' => 1,
16201 
              'period' => 1,
16202 
              'port_id' => 0,
16203 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
16204 
              'type' => 'Bool',
16205 
            },
16206 
            'direction' => 'in',
16207 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16208 
            'width' => 1,
16209 
          },
16210 
          'dout' => {
16211 
            'attributes' => {
16212 
              'bin_pt' => 0,
16213 
              'is_floating_block' => 1,
16214 
              'must_be_hdl_vector' => 1,
16215 
              'period' => 1,
16216 
              'port_id' => 0,
16217 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
16218 
              'type' => 'Bool',
16219 
            },
16220 
            'direction' => 'out',
16221 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16222 
            'width' => 1,
16223 
          },
16224 
          'en' => {
16225 
            'attributes' => {
16226 
              'bin_pt' => 0,
16227 
              'is_floating_block' => 1,
16228 
              'must_be_hdl_vector' => 1,
16229 
              'period' => 1,
16230 
              'port_id' => 1,
16231 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
16232 
              'type' => 'Bool',
16233 
            },
16234 
            'direction' => 'in',
16235 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16236 
            'width' => 1,
16237 
          },
16238 
        },
16239 
      },
16240 
      'entityName' => 'x_x14',
16241 
    },
16242 
    'to_register24' => {
16243 
      'connections' => {
16244 
        'ce' => 'sysgen_dut.to_register24_ce',
16245 
        'clk' => 'sysgen_dut.to_register24_clk',
16246 
        'clr' => 'sysgen_dut.to_register24_clr',
16247 
        'data_in' => 'sysgen_dut.to_register24_data_in',
16248 
        'dout' => 'to_register24.dout',
16249 
        'en' => 'sysgen_dut.to_register24_en',
16250 
      },
16251 
      'entity' => {
16252 
        'attributes' => {
16253 
          'entityAlreadyNetlisted' => 1,
16254 
          'generics' => [],
16255 
          'is_floating_block' => 1,
16256 
          'mask' => {
16257 
            'Block_Handle' => 54.0009765625,
16258 
            'Block_handle' => 54.0009765625,
16259 
            'MDL_Handle' => 3.0009765625,
16260 
            'MDL_handle' => 3.0009765625,
16261 
            'arith_type' => 1,
16262 
            'bin_pt' => 14,
16263 
            'block_config' => 'sysgen_blockset:toreg_config',
16264 
            'block_handle' => 54.0009765625,
16265 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16266 
            'block_type' => 'toreg',
16267 
            'dbl_ovrd' => 0,
16268 
            'explicit_data_type' => 0,
16269 
            'init' => 0,
16270 
            'init_bit_vector' => '00000000000000000000000000000000b',
16271 
            'mdl_handle' => 3.0009765625,
16272 
            'model_handle' => 3.0009765625,
16273 
            'n_bits' => 16,
16274 
            'ownership' => 1,
16275 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16276 
            'shared_memory_name' => 'register10td',
16277 
          },
16278 
          'needs_vhdl_wrapper' => 0,
16279 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16280 
        },
16281 
        'entityName' => 'x_x15',
16282 
        'ports' => {
16283 
          'ce' => {
16284 
            'attributes' => {
16285 
              'domain' => '',
16286 
              'group' => 1,
16287 
              'isCe' => 1,
16288 
              'is_floating_block' => 1,
16289 
              'period' => 1,
16290 
              'type' => 'logic',
16291 
            },
16292 
            'direction' => 'in',
16293 
            'hdlType' => 'std_logic',
16294 
            'width' => 1,
16295 
          },
16296 
          'clk' => {
16297 
            'attributes' => {
16298 
              'domain' => '',
16299 
              'group' => 1,
16300 
              'isClk' => 1,
16301 
              'is_floating_block' => 1,
16302 
              'period' => 1,
16303 
              'type' => 'logic',
16304 
            },
16305 
            'direction' => 'in',
16306 
            'hdlType' => 'std_logic',
16307 
            'width' => 1,
16308 
          },
16309 
          'clr' => {
16310 
            'attributes' => {
16311 
              'domain' => '',
16312 
              'group' => 1,
16313 
              'isClr' => 1,
16314 
              'is_floating_block' => 1,
16315 
              'period' => 1,
16316 
              'type' => 'logic',
16317 
              'valid_bit_used' => 0,
16318 
            },
16319 
            'direction' => 'in',
16320 
            'hdlType' => 'std_logic',
16321 
            'width' => 1,
16322 
          },
16323 
          'data_in' => {
16324 
            'attributes' => {
16325 
              'bin_pt' => 0,
16326 
              'is_floating_block' => 1,
16327 
              'must_be_hdl_vector' => 1,
16328 
              'period' => 1,
16329 
              'port_id' => 0,
16330 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
16331 
              'type' => 'UFix_32_0',
16332 
            },
16333 
            'direction' => 'in',
16334 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16335 
            'width' => 32,
16336 
          },
16337 
          'dout' => {
16338 
            'attributes' => {
16339 
              'bin_pt' => 0,
16340 
              'is_floating_block' => 1,
16341 
              'must_be_hdl_vector' => 1,
16342 
              'period' => 1,
16343 
              'port_id' => 0,
16344 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
16345 
              'type' => 'UFix_32_0',
16346 
            },
16347 
            'direction' => 'out',
16348 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16349 
            'width' => 32,
16350 
          },
16351 
          'en' => {
16352 
            'attributes' => {
16353 
              'bin_pt' => 0,
16354 
              'is_floating_block' => 1,
16355 
              'must_be_hdl_vector' => 1,
16356 
              'period' => 1,
16357 
              'port_id' => 1,
16358 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
16359 
              'type' => 'Bool',
16360 
            },
16361 
            'direction' => 'in',
16362 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16363 
            'width' => 1,
16364 
          },
16365 
        },
16366 
      },
16367 
      'entityName' => 'x_x15',
16368 
    },
16369 
    'to_register25' => {
16370 
      'connections' => {
16371 
        'ce' => 'sysgen_dut.to_register25_ce',
16372 
        'clk' => 'sysgen_dut.to_register25_clk',
16373 
        'clr' => 'sysgen_dut.to_register25_clr',
16374 
        'data_in' => 'sysgen_dut.to_register25_data_in',
16375 
        'dout' => 'to_register25.dout',
16376 
        'en' => 'sysgen_dut.to_register25_en',
16377 
      },
16378 
      'entity' => {
16379 
        'attributes' => {
16380 
          'entityAlreadyNetlisted' => 1,
16381 
          'generics' => [],
16382 
          'is_floating_block' => 1,
16383 
          'mask' => {
16384 
            'Block_Handle' => 55.0009765625,
16385 
            'Block_handle' => 55.0009765625,
16386 
            'MDL_Handle' => 3.0009765625,
16387 
            'MDL_handle' => 3.0009765625,
16388 
            'arith_type' => 1,
16389 
            'bin_pt' => 14,
16390 
            'block_config' => 'sysgen_blockset:toreg_config',
16391 
            'block_handle' => 55.0009765625,
16392 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16393 
            'block_type' => 'toreg',
16394 
            'dbl_ovrd' => 0,
16395 
            'explicit_data_type' => 0,
16396 
            'init' => 0,
16397 
            'init_bit_vector' => '0b',
16398 
            'mdl_handle' => 3.0009765625,
16399 
            'model_handle' => 3.0009765625,
16400 
            'n_bits' => 16,
16401 
            'ownership' => 1,
16402 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16403 
            'shared_memory_name' => 'register08tv',
16404 
          },
16405 
          'needs_vhdl_wrapper' => 0,
16406 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16407 
        },
16408 
        'entityName' => 'x_x16',
16409 
        'ports' => {
16410 
          'ce' => {
16411 
            'attributes' => {
16412 
              'domain' => '',
16413 
              'group' => 1,
16414 
              'isCe' => 1,
16415 
              'is_floating_block' => 1,
16416 
              'period' => 1,
16417 
              'type' => 'logic',
16418 
            },
16419 
            'direction' => 'in',
16420 
            'hdlType' => 'std_logic',
16421 
            'width' => 1,
16422 
          },
16423 
          'clk' => {
16424 
            'attributes' => {
16425 
              'domain' => '',
16426 
              'group' => 1,
16427 
              'isClk' => 1,
16428 
              'is_floating_block' => 1,
16429 
              'period' => 1,
16430 
              'type' => 'logic',
16431 
            },
16432 
            'direction' => 'in',
16433 
            'hdlType' => 'std_logic',
16434 
            'width' => 1,
16435 
          },
16436 
          'clr' => {
16437 
            'attributes' => {
16438 
              'domain' => '',
16439 
              'group' => 1,
16440 
              'isClr' => 1,
16441 
              'is_floating_block' => 1,
16442 
              'period' => 1,
16443 
              'type' => 'logic',
16444 
              'valid_bit_used' => 0,
16445 
            },
16446 
            'direction' => 'in',
16447 
            'hdlType' => 'std_logic',
16448 
            'width' => 1,
16449 
          },
16450 
          'data_in' => {
16451 
            'attributes' => {
16452 
              'bin_pt' => 0,
16453 
              'is_floating_block' => 1,
16454 
              'must_be_hdl_vector' => 1,
16455 
              'period' => 1,
16456 
              'port_id' => 0,
16457 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
16458 
              'type' => 'Bool',
16459 
            },
16460 
            'direction' => 'in',
16461 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16462 
            'width' => 1,
16463 
          },
16464 
          'dout' => {
16465 
            'attributes' => {
16466 
              'bin_pt' => 0,
16467 
              'is_floating_block' => 1,
16468 
              'must_be_hdl_vector' => 1,
16469 
              'period' => 1,
16470 
              'port_id' => 0,
16471 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
16472 
              'type' => 'Bool',
16473 
            },
16474 
            'direction' => 'out',
16475 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16476 
            'width' => 1,
16477 
          },
16478 
          'en' => {
16479 
            'attributes' => {
16480 
              'bin_pt' => 0,
16481 
              'is_floating_block' => 1,
16482 
              'must_be_hdl_vector' => 1,
16483 
              'period' => 1,
16484 
              'port_id' => 1,
16485 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
16486 
              'type' => 'Bool',
16487 
            },
16488 
            'direction' => 'in',
16489 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16490 
            'width' => 1,
16491 
          },
16492 
        },
16493 
      },
16494 
      'entityName' => 'x_x16',
16495 
    },
16496 
    'to_register26' => {
16497 
      'connections' => {
16498 
        'ce' => 'sysgen_dut.to_register26_ce',
16499 
        'clk' => 'sysgen_dut.to_register26_clk',
16500 
        'clr' => 'sysgen_dut.to_register26_clr',
16501 
        'data_in' => 'sysgen_dut.to_register26_data_in',
16502 
        'dout' => 'to_register26.dout',
16503 
        'en' => 'sysgen_dut.to_register26_en',
16504 
      },
16505 
      'entity' => {
16506 
        'attributes' => {
16507 
          'entityAlreadyNetlisted' => 1,
16508 
          'generics' => [],
16509 
          'is_floating_block' => 1,
16510 
          'mask' => {
16511 
            'Block_Handle' => 56.0009765625,
16512 
            'Block_handle' => 56.0009765625,
16513 
            'MDL_Handle' => 3.0009765625,
16514 
            'MDL_handle' => 3.0009765625,
16515 
            'arith_type' => 1,
16516 
            'bin_pt' => 14,
16517 
            'block_config' => 'sysgen_blockset:toreg_config',
16518 
            'block_handle' => 56.0009765625,
16519 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
16520 
            'block_type' => 'toreg',
16521 
            'dbl_ovrd' => 0,
16522 
            'explicit_data_type' => 0,
16523 
            'init' => 0,
16524 
            'init_bit_vector' => '00000000000000000000000000000000b',
16525 
            'mdl_handle' => 3.0009765625,
16526 
            'model_handle' => 3.0009765625,
16527 
            'n_bits' => 16,
16528 
            'ownership' => 1,
16529 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16530 
            'shared_memory_name' => 'register08td',
16531 
          },
16532 
          'needs_vhdl_wrapper' => 0,
16533 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
16534 
        },
16535 
        'entityName' => 'x_x17',
16536 
        'ports' => {
16537 
          'ce' => {
16538 
            'attributes' => {
16539 
              'domain' => '',
16540 
              'group' => 1,
16541 
              'isCe' => 1,
16542 
              'is_floating_block' => 1,
16543 
              'period' => 1,
16544 
              'type' => 'logic',
16545 
            },
16546 
            'direction' => 'in',
16547 
            'hdlType' => 'std_logic',
16548 
            'width' => 1,
16549 
          },
16550 
          'clk' => {
16551 
            'attributes' => {
16552 
              'domain' => '',
16553 
              'group' => 1,
16554 
              'isClk' => 1,
16555 
              'is_floating_block' => 1,
16556 
              'period' => 1,
16557 
              'type' => 'logic',
16558 
            },
16559 
            'direction' => 'in',
16560 
            'hdlType' => 'std_logic',
16561 
            'width' => 1,
16562 
          },
16563 
          'clr' => {
16564 
            'attributes' => {
16565 
              'domain' => '',
16566 
              'group' => 1,
16567 
              'isClr' => 1,
16568 
              'is_floating_block' => 1,
16569 
              'period' => 1,
16570 
              'type' => 'logic',
16571 
              'valid_bit_used' => 0,
16572 
            },
16573 
            'direction' => 'in',
16574 
            'hdlType' => 'std_logic',
16575 
            'width' => 1,
16576 
          },
16577 
          'data_in' => {
16578 
            'attributes' => {
16579 
              'bin_pt' => 0,
16580 
              'is_floating_block' => 1,
16581 
              'must_be_hdl_vector' => 1,
16582 
              'period' => 1,
16583 
              'port_id' => 0,
16584 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
16585 
              'type' => 'UFix_32_0',
16586 
            },
16587 
            'direction' => 'in',
16588 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16589 
            'width' => 32,
16590 
          },
16591 
          'dout' => {
16592 
            'attributes' => {
16593 
              'bin_pt' => 0,
16594 
              'is_floating_block' => 1,
16595 
              'must_be_hdl_vector' => 1,
16596 
              'period' => 1,
16597 
              'port_id' => 0,
16598 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
16599 
              'type' => 'UFix_32_0',
16600 
            },
16601 
            'direction' => 'out',
16602 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16603 
            'width' => 32,
16604 
          },
16605 
          'en' => {
16606 
            'attributes' => {
16607 
              'bin_pt' => 0,
16608 
              'is_floating_block' => 1,
16609 
              'must_be_hdl_vector' => 1,
16610 
              'period' => 1,
16611 
              'port_id' => 1,
16612 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
16613 
              'type' => 'Bool',
16614 
            },
16615 
            'direction' => 'in',
16616 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16617 
            'width' => 1,
16618 
          },
16619 
        },
16620 
      },
16621 
      'entityName' => 'x_x17',
16622 
    },
16623 
    'to_register27' => {
16624 
      'connections' => {
16625 
        'ce' => 'sysgen_dut.to_register27_ce',
16626 
        'clk' => 'sysgen_dut.to_register27_clk',
16627 
        'clr' => 'sysgen_dut.to_register27_clr',
16628 
        'data_in' => 'sysgen_dut.to_register27_data_in',
16629 
        'dout' => 'to_register27.dout',
16630 
        'en' => 'sysgen_dut.to_register27_en',
16631 
      },
16632 
      'entity' => {
16633 
        'attributes' => {
16634 
          'entityAlreadyNetlisted' => 1,
16635 
          'generics' => [],
16636 
          'is_floating_block' => 1,
16637 
          'mask' => {
16638 
            'Block_Handle' => 57.0009765625,
16639 
            'Block_handle' => 57.0009765625,
16640 
            'MDL_Handle' => 3.0009765625,
16641 
            'MDL_handle' => 3.0009765625,
16642 
            'arith_type' => 1,
16643 
            'bin_pt' => 14,
16644 
            'block_config' => 'sysgen_blockset:toreg_config',
16645 
            'block_handle' => 57.0009765625,
16646 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
16647 
            'block_type' => 'toreg',
16648 
            'dbl_ovrd' => 0,
16649 
            'explicit_data_type' => 0,
16650 
            'init' => 0,
16651 
            'init_bit_vector' => '0b',
16652 
            'mdl_handle' => 3.0009765625,
16653 
            'model_handle' => 3.0009765625,
16654 
            'n_bits' => 16,
16655 
            'ownership' => 1,
16656 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16657 
            'shared_memory_name' => 'register11tv',
16658 
          },
16659 
          'needs_vhdl_wrapper' => 0,
16660 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
16661 
        },
16662 
        'entityName' => 'x_x18',
16663 
        'ports' => {
16664 
          'ce' => {
16665 
            'attributes' => {
16666 
              'domain' => '',
16667 
              'group' => 1,
16668 
              'isCe' => 1,
16669 
              'is_floating_block' => 1,
16670 
              'period' => 1,
16671 
              'type' => 'logic',
16672 
            },
16673 
            'direction' => 'in',
16674 
            'hdlType' => 'std_logic',
16675 
            'width' => 1,
16676 
          },
16677 
          'clk' => {
16678 
            'attributes' => {
16679 
              'domain' => '',
16680 
              'group' => 1,
16681 
              'isClk' => 1,
16682 
              'is_floating_block' => 1,
16683 
              'period' => 1,
16684 
              'type' => 'logic',
16685 
            },
16686 
            'direction' => 'in',
16687 
            'hdlType' => 'std_logic',
16688 
            'width' => 1,
16689 
          },
16690 
          'clr' => {
16691 
            'attributes' => {
16692 
              'domain' => '',
16693 
              'group' => 1,
16694 
              'isClr' => 1,
16695 
              'is_floating_block' => 1,
16696 
              'period' => 1,
16697 
              'type' => 'logic',
16698 
              'valid_bit_used' => 0,
16699 
            },
16700 
            'direction' => 'in',
16701 
            'hdlType' => 'std_logic',
16702 
            'width' => 1,
16703 
          },
16704 
          'data_in' => {
16705 
            'attributes' => {
16706 
              'bin_pt' => 0,
16707 
              'is_floating_block' => 1,
16708 
              'must_be_hdl_vector' => 1,
16709 
              'period' => 1,
16710 
              'port_id' => 0,
16711 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
16712 
              'type' => 'Bool',
16713 
            },
16714 
            'direction' => 'in',
16715 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16716 
            'width' => 1,
16717 
          },
16718 
          'dout' => {
16719 
            'attributes' => {
16720 
              'bin_pt' => 0,
16721 
              'is_floating_block' => 1,
16722 
              'must_be_hdl_vector' => 1,
16723 
              'period' => 1,
16724 
              'port_id' => 0,
16725 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
16726 
              'type' => 'Bool',
16727 
            },
16728 
            'direction' => 'out',
16729 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16730 
            'width' => 1,
16731 
          },
16732 
          'en' => {
16733 
            'attributes' => {
16734 
              'bin_pt' => 0,
16735 
              'is_floating_block' => 1,
16736 
              'must_be_hdl_vector' => 1,
16737 
              'period' => 1,
16738 
              'port_id' => 1,
16739 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
16740 
              'type' => 'Bool',
16741 
            },
16742 
            'direction' => 'in',
16743 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16744 
            'width' => 1,
16745 
          },
16746 
        },
16747 
      },
16748 
      'entityName' => 'x_x18',
16749 
    },
16750 
    'to_register28' => {
16751 
      'connections' => {
16752 
        'ce' => 'sysgen_dut.to_register28_ce',
16753 
        'clk' => 'sysgen_dut.to_register28_clk',
16754 
        'clr' => 'sysgen_dut.to_register28_clr',
16755 
        'data_in' => 'sysgen_dut.to_register28_data_in',
16756 
        'dout' => 'to_register28.dout',
16757 
        'en' => 'sysgen_dut.to_register28_en',
16758 
      },
16759 
      'entity' => {
16760 
        'attributes' => {
16761 
          'entityAlreadyNetlisted' => 1,
16762 
          'generics' => [],
16763 
          'is_floating_block' => 1,
16764 
          'mask' => {
16765 
            'Block_Handle' => 58.0009765625,
16766 
            'Block_handle' => 58.0009765625,
16767 
            'MDL_Handle' => 3.0009765625,
16768 
            'MDL_handle' => 3.0009765625,
16769 
            'arith_type' => 1,
16770 
            'bin_pt' => 14,
16771 
            'block_config' => 'sysgen_blockset:toreg_config',
16772 
            'block_handle' => 58.0009765625,
16773 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
16774 
            'block_type' => 'toreg',
16775 
            'dbl_ovrd' => 0,
16776 
            'explicit_data_type' => 0,
16777 
            'init' => 0,
16778 
            'init_bit_vector' => '00000000000000000000000000000000b',
16779 
            'mdl_handle' => 3.0009765625,
16780 
            'model_handle' => 3.0009765625,
16781 
            'n_bits' => 16,
16782 
            'ownership' => 1,
16783 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16784 
            'shared_memory_name' => 'register11td',
16785 
          },
16786 
          'needs_vhdl_wrapper' => 0,
16787 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
16788 
        },
16789 
        'entityName' => 'x_x19',
16790 
        'ports' => {
16791 
          'ce' => {
16792 
            'attributes' => {
16793 
              'domain' => '',
16794 
              'group' => 1,
16795 
              'isCe' => 1,
16796 
              'is_floating_block' => 1,
16797 
              'period' => 1,
16798 
              'type' => 'logic',
16799 
            },
16800 
            'direction' => 'in',
16801 
            'hdlType' => 'std_logic',
16802 
            'width' => 1,
16803 
          },
16804 
          'clk' => {
16805 
            'attributes' => {
16806 
              'domain' => '',
16807 
              'group' => 1,
16808 
              'isClk' => 1,
16809 
              'is_floating_block' => 1,
16810 
              'period' => 1,
16811 
              'type' => 'logic',
16812 
            },
16813 
            'direction' => 'in',
16814 
            'hdlType' => 'std_logic',
16815 
            'width' => 1,
16816 
          },
16817 
          'clr' => {
16818 
            'attributes' => {
16819 
              'domain' => '',
16820 
              'group' => 1,
16821 
              'isClr' => 1,
16822 
              'is_floating_block' => 1,
16823 
              'period' => 1,
16824 
              'type' => 'logic',
16825 
              'valid_bit_used' => 0,
16826 
            },
16827 
            'direction' => 'in',
16828 
            'hdlType' => 'std_logic',
16829 
            'width' => 1,
16830 
          },
16831 
          'data_in' => {
16832 
            'attributes' => {
16833 
              'bin_pt' => 0,
16834 
              'is_floating_block' => 1,
16835 
              'must_be_hdl_vector' => 1,
16836 
              'period' => 1,
16837 
              'port_id' => 0,
16838 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
16839 
              'type' => 'UFix_32_0',
16840 
            },
16841 
            'direction' => 'in',
16842 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16843 
            'width' => 32,
16844 
          },
16845 
          'dout' => {
16846 
            'attributes' => {
16847 
              'bin_pt' => 0,
16848 
              'is_floating_block' => 1,
16849 
              'must_be_hdl_vector' => 1,
16850 
              'period' => 1,
16851 
              'port_id' => 0,
16852 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
16853 
              'type' => 'UFix_32_0',
16854 
            },
16855 
            'direction' => 'out',
16856 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16857 
            'width' => 32,
16858 
          },
16859 
          'en' => {
16860 
            'attributes' => {
16861 
              'bin_pt' => 0,
16862 
              'is_floating_block' => 1,
16863 
              'must_be_hdl_vector' => 1,
16864 
              'period' => 1,
16865 
              'port_id' => 1,
16866 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
16867 
              'type' => 'Bool',
16868 
            },
16869 
            'direction' => 'in',
16870 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16871 
            'width' => 1,
16872 
          },
16873 
        },
16874 
      },
16875 
      'entityName' => 'x_x19',
16876 
    },
16877 
    'to_register29' => {
16878 
      'connections' => {
16879 
        'ce' => 'sysgen_dut.to_register29_ce',
16880 
        'clk' => 'sysgen_dut.to_register29_clk',
16881 
        'clr' => 'sysgen_dut.to_register29_clr',
16882 
        'data_in' => 'sysgen_dut.to_register29_data_in',
16883 
        'dout' => 'to_register29.dout',
16884 
        'en' => 'sysgen_dut.to_register29_en',
16885 
      },
16886 
      'entity' => {
16887 
        'attributes' => {
16888 
          'entityAlreadyNetlisted' => 1,
16889 
          'generics' => [],
16890 
          'is_floating_block' => 1,
16891 
          'mask' => {
16892 
            'Block_Handle' => 59.0009765625,
16893 
            'Block_handle' => 59.0009765625,
16894 
            'MDL_Handle' => 3.0009765625,
16895 
            'MDL_handle' => 3.0009765625,
16896 
            'arith_type' => 1,
16897 
            'bin_pt' => 14,
16898 
            'block_config' => 'sysgen_blockset:toreg_config',
16899 
            'block_handle' => 59.0009765625,
16900 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
16901 
            'block_type' => 'toreg',
16902 
            'dbl_ovrd' => 0,
16903 
            'explicit_data_type' => 0,
16904 
            'init' => 0,
16905 
            'init_bit_vector' => '0b',
16906 
            'mdl_handle' => 3.0009765625,
16907 
            'model_handle' => 3.0009765625,
16908 
            'n_bits' => 16,
16909 
            'ownership' => 1,
16910 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16911 
            'shared_memory_name' => 'register12tv',
16912 
          },
16913 
          'needs_vhdl_wrapper' => 0,
16914 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
16915 
        },
16916 
        'entityName' => 'x_x20',
16917 
        'ports' => {
16918 
          'ce' => {
16919 
            'attributes' => {
16920 
              'domain' => '',
16921 
              'group' => 1,
16922 
              'isCe' => 1,
16923 
              'is_floating_block' => 1,
16924 
              'period' => 1,
16925 
              'type' => 'logic',
16926 
            },
16927 
            'direction' => 'in',
16928 
            'hdlType' => 'std_logic',
16929 
            'width' => 1,
16930 
          },
16931 
          'clk' => {
16932 
            'attributes' => {
16933 
              'domain' => '',
16934 
              'group' => 1,
16935 
              'isClk' => 1,
16936 
              'is_floating_block' => 1,
16937 
              'period' => 1,
16938 
              'type' => 'logic',
16939 
            },
16940 
            'direction' => 'in',
16941 
            'hdlType' => 'std_logic',
16942 
            'width' => 1,
16943 
          },
16944 
          'clr' => {
16945 
            'attributes' => {
16946 
              'domain' => '',
16947 
              'group' => 1,
16948 
              'isClr' => 1,
16949 
              'is_floating_block' => 1,
16950 
              'period' => 1,
16951 
              'type' => 'logic',
16952 
              'valid_bit_used' => 0,
16953 
            },
16954 
            'direction' => 'in',
16955 
            'hdlType' => 'std_logic',
16956 
            'width' => 1,
16957 
          },
16958 
          'data_in' => {
16959 
            'attributes' => {
16960 
              'bin_pt' => 0,
16961 
              'is_floating_block' => 1,
16962 
              'must_be_hdl_vector' => 1,
16963 
              'period' => 1,
16964 
              'port_id' => 0,
16965 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
16966 
              'type' => 'Bool',
16967 
            },
16968 
            'direction' => 'in',
16969 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16970 
            'width' => 1,
16971 
          },
16972 
          'dout' => {
16973 
            'attributes' => {
16974 
              'bin_pt' => 0,
16975 
              'is_floating_block' => 1,
16976 
              'must_be_hdl_vector' => 1,
16977 
              'period' => 1,
16978 
              'port_id' => 0,
16979 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
16980 
              'type' => 'Bool',
16981 
            },
16982 
            'direction' => 'out',
16983 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16984 
            'width' => 1,
16985 
          },
16986 
          'en' => {
16987 
            'attributes' => {
16988 
              'bin_pt' => 0,
16989 
              'is_floating_block' => 1,
16990 
              'must_be_hdl_vector' => 1,
16991 
              'period' => 1,
16992 
              'port_id' => 1,
16993 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
16994 
              'type' => 'Bool',
16995 
            },
16996 
            'direction' => 'in',
16997 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16998 
            'width' => 1,
16999 
          },
17000 
        },
17001 
      },
17002 
      'entityName' => 'x_x20',
17003 
    },
17004 
    'to_register3' => {
17005 
      'connections' => {
17006 
        'ce' => 'sysgen_dut.to_register3_ce',
17007 
        'clk' => 'sysgen_dut.to_register3_clk',
17008 
        'clr' => 'sysgen_dut.to_register3_clr',
17009 
        'data_in' => 'sysgen_dut.to_register3_data_in',
17010 
        'dout' => 'to_register3.dout',
17011 
        'en' => 'sysgen_dut.to_register3_en',
17012 
      },
17013 
      'entity' => {
17014 
        'attributes' => {
17015 
          'entityAlreadyNetlisted' => 1,
17016 
          'generics' => [],
17017 
          'is_floating_block' => 1,
17018 
          'mask' => {
17019 
            'Block_Handle' => 60.0009765625,
17020 
            'Block_handle' => 60.0009765625,
17021 
            'MDL_Handle' => 3.0009765625,
17022 
            'MDL_handle' => 3.0009765625,
17023 
            'arith_type' => 1,
17024 
            'bin_pt' => 14,
17025 
            'block_config' => 'sysgen_blockset:toreg_config',
17026 
            'block_handle' => 60.0009765625,
17027 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17028 
            'block_type' => 'toreg',
17029 
            'dbl_ovrd' => 0,
17030 
            'explicit_data_type' => 0,
17031 
            'init' => 0,
17032 
            'init_bit_vector' => '0b',
17033 
            'mdl_handle' => 3.0009765625,
17034 
            'model_handle' => 3.0009765625,
17035 
            'n_bits' => 16,
17036 
            'ownership' => 1,
17037 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17038 
            'shared_memory_name' => 'register01tv',
17039 
          },
17040 
          'needs_vhdl_wrapper' => 0,
17041 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17042 
        },
17043 
        'entityName' => 'x_x21',
17044 
        'ports' => {
17045 
          'ce' => {
17046 
            'attributes' => {
17047 
              'domain' => '',
17048 
              'group' => 1,
17049 
              'isCe' => 1,
17050 
              'is_floating_block' => 1,
17051 
              'period' => 1,
17052 
              'type' => 'logic',
17053 
            },
17054 
            'direction' => 'in',
17055 
            'hdlType' => 'std_logic',
17056 
            'width' => 1,
17057 
          },
17058 
          'clk' => {
17059 
            'attributes' => {
17060 
              'domain' => '',
17061 
              'group' => 1,
17062 
              'isClk' => 1,
17063 
              'is_floating_block' => 1,
17064 
              'period' => 1,
17065 
              'type' => 'logic',
17066 
            },
17067 
            'direction' => 'in',
17068 
            'hdlType' => 'std_logic',
17069 
            'width' => 1,
17070 
          },
17071 
          'clr' => {
17072 
            'attributes' => {
17073 
              'domain' => '',
17074 
              'group' => 1,
17075 
              'isClr' => 1,
17076 
              'is_floating_block' => 1,
17077 
              'period' => 1,
17078 
              'type' => 'logic',
17079 
              'valid_bit_used' => 0,
17080 
            },
17081 
            'direction' => 'in',
17082 
            'hdlType' => 'std_logic',
17083 
            'width' => 1,
17084 
          },
17085 
          'data_in' => {
17086 
            'attributes' => {
17087 
              'bin_pt' => 0,
17088 
              'is_floating_block' => 1,
17089 
              'must_be_hdl_vector' => 1,
17090 
              'period' => 1,
17091 
              'port_id' => 0,
17092 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
17093 
              'type' => 'Bool',
17094 
            },
17095 
            'direction' => 'in',
17096 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17097 
            'width' => 1,
17098 
          },
17099 
          'dout' => {
17100 
            'attributes' => {
17101 
              'bin_pt' => 0,
17102 
              'is_floating_block' => 1,
17103 
              'must_be_hdl_vector' => 1,
17104 
              'period' => 1,
17105 
              'port_id' => 0,
17106 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
17107 
              'type' => 'Bool',
17108 
            },
17109 
            'direction' => 'out',
17110 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17111 
            'width' => 1,
17112 
          },
17113 
          'en' => {
17114 
            'attributes' => {
17115 
              'bin_pt' => 0,
17116 
              'is_floating_block' => 1,
17117 
              'must_be_hdl_vector' => 1,
17118 
              'period' => 1,
17119 
              'port_id' => 1,
17120 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
17121 
              'type' => 'Bool',
17122 
            },
17123 
            'direction' => 'in',
17124 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17125 
            'width' => 1,
17126 
          },
17127 
        },
17128 
      },
17129 
      'entityName' => 'x_x21',
17130 
    },
17131 
    'to_register30' => {
17132 
      'connections' => {
17133 
        'ce' => 'sysgen_dut.to_register30_ce',
17134 
        'clk' => 'sysgen_dut.to_register30_clk',
17135 
        'clr' => 'sysgen_dut.to_register30_clr',
17136 
        'data_in' => 'sysgen_dut.to_register30_data_in',
17137 
        'dout' => 'to_register30.dout',
17138 
        'en' => 'sysgen_dut.to_register30_en',
17139 
      },
17140 
      'entity' => {
17141 
        'attributes' => {
17142 
          'entityAlreadyNetlisted' => 1,
17143 
          'generics' => [],
17144 
          'is_floating_block' => 1,
17145 
          'mask' => {
17146 
            'Block_Handle' => 61.0009765625,
17147 
            'Block_handle' => 61.0009765625,
17148 
            'MDL_Handle' => 3.0009765625,
17149 
            'MDL_handle' => 3.0009765625,
17150 
            'arith_type' => 1,
17151 
            'bin_pt' => 14,
17152 
            'block_config' => 'sysgen_blockset:toreg_config',
17153 
            'block_handle' => 61.0009765625,
17154 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17155 
            'block_type' => 'toreg',
17156 
            'dbl_ovrd' => 0,
17157 
            'explicit_data_type' => 0,
17158 
            'init' => 0,
17159 
            'init_bit_vector' => '00000000000000000000000000000000b',
17160 
            'mdl_handle' => 3.0009765625,
17161 
            'model_handle' => 3.0009765625,
17162 
            'n_bits' => 16,
17163 
            'ownership' => 1,
17164 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17165 
            'shared_memory_name' => 'register12td',
17166 
          },
17167 
          'needs_vhdl_wrapper' => 0,
17168 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17169 
        },
17170 
        'entityName' => 'x_x22',
17171 
        'ports' => {
17172 
          'ce' => {
17173 
            'attributes' => {
17174 
              'domain' => '',
17175 
              'group' => 1,
17176 
              'isCe' => 1,
17177 
              'is_floating_block' => 1,
17178 
              'period' => 1,
17179 
              'type' => 'logic',
17180 
            },
17181 
            'direction' => 'in',
17182 
            'hdlType' => 'std_logic',
17183 
            'width' => 1,
17184 
          },
17185 
          'clk' => {
17186 
            'attributes' => {
17187 
              'domain' => '',
17188 
              'group' => 1,
17189 
              'isClk' => 1,
17190 
              'is_floating_block' => 1,
17191 
              'period' => 1,
17192 
              'type' => 'logic',
17193 
            },
17194 
            'direction' => 'in',
17195 
            'hdlType' => 'std_logic',
17196 
            'width' => 1,
17197 
          },
17198 
          'clr' => {
17199 
            'attributes' => {
17200 
              'domain' => '',
17201 
              'group' => 1,
17202 
              'isClr' => 1,
17203 
              'is_floating_block' => 1,
17204 
              'period' => 1,
17205 
              'type' => 'logic',
17206 
              'valid_bit_used' => 0,
17207 
            },
17208 
            'direction' => 'in',
17209 
            'hdlType' => 'std_logic',
17210 
            'width' => 1,
17211 
          },
17212 
          'data_in' => {
17213 
            'attributes' => {
17214 
              'bin_pt' => 0,
17215 
              'is_floating_block' => 1,
17216 
              'must_be_hdl_vector' => 1,
17217 
              'period' => 1,
17218 
              'port_id' => 0,
17219 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
17220 
              'type' => 'UFix_32_0',
17221 
            },
17222 
            'direction' => 'in',
17223 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17224 
            'width' => 32,
17225 
          },
17226 
          'dout' => {
17227 
            'attributes' => {
17228 
              'bin_pt' => 0,
17229 
              'is_floating_block' => 1,
17230 
              'must_be_hdl_vector' => 1,
17231 
              'period' => 1,
17232 
              'port_id' => 0,
17233 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
17234 
              'type' => 'UFix_32_0',
17235 
            },
17236 
            'direction' => 'out',
17237 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17238 
            'width' => 32,
17239 
          },
17240 
          'en' => {
17241 
            'attributes' => {
17242 
              'bin_pt' => 0,
17243 
              'is_floating_block' => 1,
17244 
              'must_be_hdl_vector' => 1,
17245 
              'period' => 1,
17246 
              'port_id' => 1,
17247 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
17248 
              'type' => 'Bool',
17249 
            },
17250 
            'direction' => 'in',
17251 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17252 
            'width' => 1,
17253 
          },
17254 
        },
17255 
      },
17256 
      'entityName' => 'x_x22',
17257 
    },
17258 
    'to_register31' => {
17259 
      'connections' => {
17260 
        'ce' => 'sysgen_dut.to_register31_ce',
17261 
        'clk' => 'sysgen_dut.to_register31_clk',
17262 
        'clr' => 'sysgen_dut.to_register31_clr',
17263 
        'data_in' => 'sysgen_dut.to_register31_data_in',
17264 
        'dout' => 'to_register31.dout',
17265 
        'en' => 'sysgen_dut.to_register31_en',
17266 
      },
17267 
      'entity' => {
17268 
        'attributes' => {
17269 
          'entityAlreadyNetlisted' => 1,
17270 
          'generics' => [],
17271 
          'is_floating_block' => 1,
17272 
          'mask' => {
17273 
            'Block_Handle' => 62.0009765625,
17274 
            'Block_handle' => 62.0009765625,
17275 
            'MDL_Handle' => 3.0009765625,
17276 
            'MDL_handle' => 3.0009765625,
17277 
            'arith_type' => 1,
17278 
            'bin_pt' => 14,
17279 
            'block_config' => 'sysgen_blockset:toreg_config',
17280 
            'block_handle' => 62.0009765625,
17281 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17282 
            'block_type' => 'toreg',
17283 
            'dbl_ovrd' => 0,
17284 
            'explicit_data_type' => 0,
17285 
            'init' => 0,
17286 
            'init_bit_vector' => '0b',
17287 
            'mdl_handle' => 3.0009765625,
17288 
            'model_handle' => 3.0009765625,
17289 
            'n_bits' => 16,
17290 
            'ownership' => 1,
17291 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17292 
            'shared_memory_name' => 'register13tv',
17293 
          },
17294 
          'needs_vhdl_wrapper' => 0,
17295 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17296 
        },
17297 
        'entityName' => 'x_x23',
17298 
        'ports' => {
17299 
          'ce' => {
17300 
            'attributes' => {
17301 
              'domain' => '',
17302 
              'group' => 1,
17303 
              'isCe' => 1,
17304 
              'is_floating_block' => 1,
17305 
              'period' => 1,
17306 
              'type' => 'logic',
17307 
            },
17308 
            'direction' => 'in',
17309 
            'hdlType' => 'std_logic',
17310 
            'width' => 1,
17311 
          },
17312 
          'clk' => {
17313 
            'attributes' => {
17314 
              'domain' => '',
17315 
              'group' => 1,
17316 
              'isClk' => 1,
17317 
              'is_floating_block' => 1,
17318 
              'period' => 1,
17319 
              'type' => 'logic',
17320 
            },
17321 
            'direction' => 'in',
17322 
            'hdlType' => 'std_logic',
17323 
            'width' => 1,
17324 
          },
17325 
          'clr' => {
17326 
            'attributes' => {
17327 
              'domain' => '',
17328 
              'group' => 1,
17329 
              'isClr' => 1,
17330 
              'is_floating_block' => 1,
17331 
              'period' => 1,
17332 
              'type' => 'logic',
17333 
              'valid_bit_used' => 0,
17334 
            },
17335 
            'direction' => 'in',
17336 
            'hdlType' => 'std_logic',
17337 
            'width' => 1,
17338 
          },
17339 
          'data_in' => {
17340 
            'attributes' => {
17341 
              'bin_pt' => 0,
17342 
              'is_floating_block' => 1,
17343 
              'must_be_hdl_vector' => 1,
17344 
              'period' => 1,
17345 
              'port_id' => 0,
17346 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
17347 
              'type' => 'Bool',
17348 
            },
17349 
            'direction' => 'in',
17350 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17351 
            'width' => 1,
17352 
          },
17353 
          'dout' => {
17354 
            'attributes' => {
17355 
              'bin_pt' => 0,
17356 
              'is_floating_block' => 1,
17357 
              'must_be_hdl_vector' => 1,
17358 
              'period' => 1,
17359 
              'port_id' => 0,
17360 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
17361 
              'type' => 'Bool',
17362 
            },
17363 
            'direction' => 'out',
17364 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17365 
            'width' => 1,
17366 
          },
17367 
          'en' => {
17368 
            'attributes' => {
17369 
              'bin_pt' => 0,
17370 
              'is_floating_block' => 1,
17371 
              'must_be_hdl_vector' => 1,
17372 
              'period' => 1,
17373 
              'port_id' => 1,
17374 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
17375 
              'type' => 'Bool',
17376 
            },
17377 
            'direction' => 'in',
17378 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17379 
            'width' => 1,
17380 
          },
17381 
        },
17382 
      },
17383 
      'entityName' => 'x_x23',
17384 
    },
17385 
    'to_register32' => {
17386 
      'connections' => {
17387 
        'ce' => 'sysgen_dut.to_register32_ce',
17388 
        'clk' => 'sysgen_dut.to_register32_clk',
17389 
        'clr' => 'sysgen_dut.to_register32_clr',
17390 
        'data_in' => 'sysgen_dut.to_register32_data_in',
17391 
        'dout' => 'to_register32.dout',
17392 
        'en' => 'sysgen_dut.to_register32_en',
17393 
      },
17394 
      'entity' => {
17395 
        'attributes' => {
17396 
          'entityAlreadyNetlisted' => 1,
17397 
          'generics' => [],
17398 
          'is_floating_block' => 1,
17399 
          'mask' => {
17400 
            'Block_Handle' => 63.0009765625,
17401 
            'Block_handle' => 63.0009765625,
17402 
            'MDL_Handle' => 3.0009765625,
17403 
            'MDL_handle' => 3.0009765625,
17404 
            'arith_type' => 1,
17405 
            'bin_pt' => 14,
17406 
            'block_config' => 'sysgen_blockset:toreg_config',
17407 
            'block_handle' => 63.0009765625,
17408 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17409 
            'block_type' => 'toreg',
17410 
            'dbl_ovrd' => 0,
17411 
            'explicit_data_type' => 0,
17412 
            'init' => 0,
17413 
            'init_bit_vector' => '00000000000000000000000000000000b',
17414 
            'mdl_handle' => 3.0009765625,
17415 
            'model_handle' => 3.0009765625,
17416 
            'n_bits' => 16,
17417 
            'ownership' => 1,
17418 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17419 
            'shared_memory_name' => 'register13td',
17420 
          },
17421 
          'needs_vhdl_wrapper' => 0,
17422 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17423 
        },
17424 
        'entityName' => 'x_x24',
17425 
        'ports' => {
17426 
          'ce' => {
17427 
            'attributes' => {
17428 
              'domain' => '',
17429 
              'group' => 1,
17430 
              'isCe' => 1,
17431 
              'is_floating_block' => 1,
17432 
              'period' => 1,
17433 
              'type' => 'logic',
17434 
            },
17435 
            'direction' => 'in',
17436 
            'hdlType' => 'std_logic',
17437 
            'width' => 1,
17438 
          },
17439 
          'clk' => {
17440 
            'attributes' => {
17441 
              'domain' => '',
17442 
              'group' => 1,
17443 
              'isClk' => 1,
17444 
              'is_floating_block' => 1,
17445 
              'period' => 1,
17446 
              'type' => 'logic',
17447 
            },
17448 
            'direction' => 'in',
17449 
            'hdlType' => 'std_logic',
17450 
            'width' => 1,
17451 
          },
17452 
          'clr' => {
17453 
            'attributes' => {
17454 
              'domain' => '',
17455 
              'group' => 1,
17456 
              'isClr' => 1,
17457 
              'is_floating_block' => 1,
17458 
              'period' => 1,
17459 
              'type' => 'logic',
17460 
              'valid_bit_used' => 0,
17461 
            },
17462 
            'direction' => 'in',
17463 
            'hdlType' => 'std_logic',
17464 
            'width' => 1,
17465 
          },
17466 
          'data_in' => {
17467 
            'attributes' => {
17468 
              'bin_pt' => 0,
17469 
              'is_floating_block' => 1,
17470 
              'must_be_hdl_vector' => 1,
17471 
              'period' => 1,
17472 
              'port_id' => 0,
17473 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
17474 
              'type' => 'UFix_32_0',
17475 
            },
17476 
            'direction' => 'in',
17477 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17478 
            'width' => 32,
17479 
          },
17480 
          'dout' => {
17481 
            'attributes' => {
17482 
              'bin_pt' => 0,
17483 
              'is_floating_block' => 1,
17484 
              'must_be_hdl_vector' => 1,
17485 
              'period' => 1,
17486 
              'port_id' => 0,
17487 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
17488 
              'type' => 'UFix_32_0',
17489 
            },
17490 
            'direction' => 'out',
17491 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17492 
            'width' => 32,
17493 
          },
17494 
          'en' => {
17495 
            'attributes' => {
17496 
              'bin_pt' => 0,
17497 
              'is_floating_block' => 1,
17498 
              'must_be_hdl_vector' => 1,
17499 
              'period' => 1,
17500 
              'port_id' => 1,
17501 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
17502 
              'type' => 'Bool',
17503 
            },
17504 
            'direction' => 'in',
17505 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17506 
            'width' => 1,
17507 
          },
17508 
        },
17509 
      },
17510 
      'entityName' => 'x_x24',
17511 
    },
17512 
    'to_register33' => {
17513 
      'connections' => {
17514 
        'ce' => 'sysgen_dut.to_register33_ce',
17515 
        'clk' => 'sysgen_dut.to_register33_clk',
17516 
        'clr' => 'sysgen_dut.to_register33_clr',
17517 
        'data_in' => 'sysgen_dut.to_register33_data_in',
17518 
        'dout' => 'to_register33.dout',
17519 
        'en' => 'sysgen_dut.to_register33_en',
17520 
      },
17521 
      'entity' => {
17522 
        'attributes' => {
17523 
          'entityAlreadyNetlisted' => 1,
17524 
          'generics' => [],
17525 
          'is_floating_block' => 1,
17526 
          'mask' => {
17527 
            'Block_Handle' => 64.0009765625,
17528 
            'Block_handle' => 64.0009765625,
17529 
            'MDL_Handle' => 3.0009765625,
17530 
            'MDL_handle' => 3.0009765625,
17531 
            'arith_type' => 1,
17532 
            'bin_pt' => 14,
17533 
            'block_config' => 'sysgen_blockset:toreg_config',
17534 
            'block_handle' => 64.0009765625,
17535 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
17536 
            'block_type' => 'toreg',
17537 
            'dbl_ovrd' => 0,
17538 
            'explicit_data_type' => 0,
17539 
            'init' => 0,
17540 
            'init_bit_vector' => '0b',
17541 
            'mdl_handle' => 3.0009765625,
17542 
            'model_handle' => 3.0009765625,
17543 
            'n_bits' => 16,
17544 
            'ownership' => 1,
17545 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17546 
            'shared_memory_name' => 'register14tv',
17547 
          },
17548 
          'needs_vhdl_wrapper' => 0,
17549 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
17550 
        },
17551 
        'entityName' => 'x_x25',
17552 
        'ports' => {
17553 
          'ce' => {
17554 
            'attributes' => {
17555 
              'domain' => '',
17556 
              'group' => 1,
17557 
              'isCe' => 1,
17558 
              'is_floating_block' => 1,
17559 
              'period' => 1,
17560 
              'type' => 'logic',
17561 
            },
17562 
            'direction' => 'in',
17563 
            'hdlType' => 'std_logic',
17564 
            'width' => 1,
17565 
          },
17566 
          'clk' => {
17567 
            'attributes' => {
17568 
              'domain' => '',
17569 
              'group' => 1,
17570 
              'isClk' => 1,
17571 
              'is_floating_block' => 1,
17572 
              'period' => 1,
17573 
              'type' => 'logic',
17574 
            },
17575 
            'direction' => 'in',
17576 
            'hdlType' => 'std_logic',
17577 
            'width' => 1,
17578 
          },
17579 
          'clr' => {
17580 
            'attributes' => {
17581 
              'domain' => '',
17582 
              'group' => 1,
17583 
              'isClr' => 1,
17584 
              'is_floating_block' => 1,
17585 
              'period' => 1,
17586 
              'type' => 'logic',
17587 
              'valid_bit_used' => 0,
17588 
            },
17589 
            'direction' => 'in',
17590 
            'hdlType' => 'std_logic',
17591 
            'width' => 1,
17592 
          },
17593 
          'data_in' => {
17594 
            'attributes' => {
17595 
              'bin_pt' => 0,
17596 
              'is_floating_block' => 1,
17597 
              'must_be_hdl_vector' => 1,
17598 
              'period' => 1,
17599 
              'port_id' => 0,
17600 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
17601 
              'type' => 'Bool',
17602 
            },
17603 
            'direction' => 'in',
17604 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17605 
            'width' => 1,
17606 
          },
17607 
          'dout' => {
17608 
            'attributes' => {
17609 
              'bin_pt' => 0,
17610 
              'is_floating_block' => 1,
17611 
              'must_be_hdl_vector' => 1,
17612 
              'period' => 1,
17613 
              'port_id' => 0,
17614 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
17615 
              'type' => 'Bool',
17616 
            },
17617 
            'direction' => 'out',
17618 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17619 
            'width' => 1,
17620 
          },
17621 
          'en' => {
17622 
            'attributes' => {
17623 
              'bin_pt' => 0,
17624 
              'is_floating_block' => 1,
17625 
              'must_be_hdl_vector' => 1,
17626 
              'period' => 1,
17627 
              'port_id' => 1,
17628 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
17629 
              'type' => 'Bool',
17630 
            },
17631 
            'direction' => 'in',
17632 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17633 
            'width' => 1,
17634 
          },
17635 
        },
17636 
      },
17637 
      'entityName' => 'x_x25',
17638 
    },
17639 
    'to_register34' => {
17640 
      'connections' => {
17641 
        'ce' => 'sysgen_dut.to_register34_ce',
17642 
        'clk' => 'sysgen_dut.to_register34_clk',
17643 
        'clr' => 'sysgen_dut.to_register34_clr',
17644 
        'data_in' => 'sysgen_dut.to_register34_data_in',
17645 
        'dout' => 'to_register34.dout',
17646 
        'en' => 'sysgen_dut.to_register34_en',
17647 
      },
17648 
      'entity' => {
17649 
        'attributes' => {
17650 
          'entityAlreadyNetlisted' => 1,
17651 
          'generics' => [],
17652 
          'is_floating_block' => 1,
17653 
          'mask' => {
17654 
            'Block_Handle' => 65.0009765625,
17655 
            'Block_handle' => 65.0009765625,
17656 
            'MDL_Handle' => 3.0009765625,
17657 
            'MDL_handle' => 3.0009765625,
17658 
            'arith_type' => 1,
17659 
            'bin_pt' => 14,
17660 
            'block_config' => 'sysgen_blockset:toreg_config',
17661 
            'block_handle' => 65.0009765625,
17662 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
17663 
            'block_type' => 'toreg',
17664 
            'dbl_ovrd' => 0,
17665 
            'explicit_data_type' => 0,
17666 
            'init' => 0,
17667 
            'init_bit_vector' => '00000000000000000000000000000000b',
17668 
            'mdl_handle' => 3.0009765625,
17669 
            'model_handle' => 3.0009765625,
17670 
            'n_bits' => 16,
17671 
            'ownership' => 1,
17672 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17673 
            'shared_memory_name' => 'register14td',
17674 
          },
17675 
          'needs_vhdl_wrapper' => 0,
17676 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
17677 
        },
17678 
        'entityName' => 'x_x26',
17679 
        'ports' => {
17680 
          'ce' => {
17681 
            'attributes' => {
17682 
              'domain' => '',
17683 
              'group' => 1,
17684 
              'isCe' => 1,
17685 
              'is_floating_block' => 1,
17686 
              'period' => 1,
17687 
              'type' => 'logic',
17688 
            },
17689 
            'direction' => 'in',
17690 
            'hdlType' => 'std_logic',
17691 
            'width' => 1,
17692 
          },
17693 
          'clk' => {
17694 
            'attributes' => {
17695 
              'domain' => '',
17696 
              'group' => 1,
17697 
              'isClk' => 1,
17698 
              'is_floating_block' => 1,
17699 
              'period' => 1,
17700 
              'type' => 'logic',
17701 
            },
17702 
            'direction' => 'in',
17703 
            'hdlType' => 'std_logic',
17704 
            'width' => 1,
17705 
          },
17706 
          'clr' => {
17707 
            'attributes' => {
17708 
              'domain' => '',
17709 
              'group' => 1,
17710 
              'isClr' => 1,
17711 
              'is_floating_block' => 1,
17712 
              'period' => 1,
17713 
              'type' => 'logic',
17714 
              'valid_bit_used' => 0,
17715 
            },
17716 
            'direction' => 'in',
17717 
            'hdlType' => 'std_logic',
17718 
            'width' => 1,
17719 
          },
17720 
          'data_in' => {
17721 
            'attributes' => {
17722 
              'bin_pt' => 0,
17723 
              'is_floating_block' => 1,
17724 
              'must_be_hdl_vector' => 1,
17725 
              'period' => 1,
17726 
              'port_id' => 0,
17727 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
17728 
              'type' => 'UFix_32_0',
17729 
            },
17730 
            'direction' => 'in',
17731 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17732 
            'width' => 32,
17733 
          },
17734 
          'dout' => {
17735 
            'attributes' => {
17736 
              'bin_pt' => 0,
17737 
              'is_floating_block' => 1,
17738 
              'must_be_hdl_vector' => 1,
17739 
              'period' => 1,
17740 
              'port_id' => 0,
17741 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
17742 
              'type' => 'UFix_32_0',
17743 
            },
17744 
            'direction' => 'out',
17745 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17746 
            'width' => 32,
17747 
          },
17748 
          'en' => {
17749 
            'attributes' => {
17750 
              'bin_pt' => 0,
17751 
              'is_floating_block' => 1,
17752 
              'must_be_hdl_vector' => 1,
17753 
              'period' => 1,
17754 
              'port_id' => 1,
17755 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
17756 
              'type' => 'Bool',
17757 
            },
17758 
            'direction' => 'in',
17759 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17760 
            'width' => 1,
17761 
          },
17762 
        },
17763 
      },
17764 
      'entityName' => 'x_x26',
17765 
    },
17766 
    'to_register4' => {
17767 
      'connections' => {
17768 
        'ce' => 'sysgen_dut.to_register4_ce',
17769 
        'clk' => 'sysgen_dut.to_register4_clk',
17770 
        'clr' => 'sysgen_dut.to_register4_clr',
17771 
        'data_in' => 'sysgen_dut.to_register4_data_in',
17772 
        'dout' => 'to_register4.dout',
17773 
        'en' => 'sysgen_dut.to_register4_en',
17774 
      },
17775 
      'entity' => {
17776 
        'attributes' => {
17777 
          'entityAlreadyNetlisted' => 1,
17778 
          'generics' => [],
17779 
          'is_floating_block' => 1,
17780 
          'mask' => {
17781 
            'Block_Handle' => 66.0009765625,
17782 
            'Block_handle' => 66.0009765625,
17783 
            'MDL_Handle' => 3.0009765625,
17784 
            'MDL_handle' => 3.0009765625,
17785 
            'arith_type' => 1,
17786 
            'bin_pt' => 14,
17787 
            'block_config' => 'sysgen_blockset:toreg_config',
17788 
            'block_handle' => 66.0009765625,
17789 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
17790 
            'block_type' => 'toreg',
17791 
            'dbl_ovrd' => 0,
17792 
            'explicit_data_type' => 0,
17793 
            'init' => 0,
17794 
            'init_bit_vector' => '0b',
17795 
            'mdl_handle' => 3.0009765625,
17796 
            'model_handle' => 3.0009765625,
17797 
            'n_bits' => 16,
17798 
            'ownership' => 1,
17799 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17800 
            'shared_memory_name' => 'register02tv',
17801 
          },
17802 
          'needs_vhdl_wrapper' => 0,
17803 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
17804 
        },
17805 
        'entityName' => 'x_x27',
17806 
        'ports' => {
17807 
          'ce' => {
17808 
            'attributes' => {
17809 
              'domain' => '',
17810 
              'group' => 1,
17811 
              'isCe' => 1,
17812 
              'is_floating_block' => 1,
17813 
              'period' => 1,
17814 
              'type' => 'logic',
17815 
            },
17816 
            'direction' => 'in',
17817 
            'hdlType' => 'std_logic',
17818 
            'width' => 1,
17819 
          },
17820 
          'clk' => {
17821 
            'attributes' => {
17822 
              'domain' => '',
17823 
              'group' => 1,
17824 
              'isClk' => 1,
17825 
              'is_floating_block' => 1,
17826 
              'period' => 1,
17827 
              'type' => 'logic',
17828 
            },
17829 
            'direction' => 'in',
17830 
            'hdlType' => 'std_logic',
17831 
            'width' => 1,
17832 
          },
17833 
          'clr' => {
17834 
            'attributes' => {
17835 
              'domain' => '',
17836 
              'group' => 1,
17837 
              'isClr' => 1,
17838 
              'is_floating_block' => 1,
17839 
              'period' => 1,
17840 
              'type' => 'logic',
17841 
              'valid_bit_used' => 0,
17842 
            },
17843 
            'direction' => 'in',
17844 
            'hdlType' => 'std_logic',
17845 
            'width' => 1,
17846 
          },
17847 
          'data_in' => {
17848 
            'attributes' => {
17849 
              'bin_pt' => 0,
17850 
              'is_floating_block' => 1,
17851 
              'must_be_hdl_vector' => 1,
17852 
              'period' => 1,
17853 
              'port_id' => 0,
17854 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
17855 
              'type' => 'Bool',
17856 
            },
17857 
            'direction' => 'in',
17858 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17859 
            'width' => 1,
17860 
          },
17861 
          'dout' => {
17862 
            'attributes' => {
17863 
              'bin_pt' => 0,
17864 
              'is_floating_block' => 1,
17865 
              'must_be_hdl_vector' => 1,
17866 
              'period' => 1,
17867 
              'port_id' => 0,
17868 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
17869 
              'type' => 'Bool',
17870 
            },
17871 
            'direction' => 'out',
17872 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17873 
            'width' => 1,
17874 
          },
17875 
          'en' => {
17876 
            'attributes' => {
17877 
              'bin_pt' => 0,
17878 
              'is_floating_block' => 1,
17879 
              'must_be_hdl_vector' => 1,
17880 
              'period' => 1,
17881 
              'port_id' => 1,
17882 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
17883 
              'type' => 'Bool',
17884 
            },
17885 
            'direction' => 'in',
17886 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17887 
            'width' => 1,
17888 
          },
17889 
        },
17890 
      },
17891 
      'entityName' => 'x_x27',
17892 
    },
17893 
    'to_register5' => {
17894 
      'connections' => {
17895 
        'ce' => 'sysgen_dut.to_register5_ce',
17896 
        'clk' => 'sysgen_dut.to_register5_clk',
17897 
        'clr' => 'sysgen_dut.to_register5_clr',
17898 
        'data_in' => 'sysgen_dut.to_register5_data_in',
17899 
        'dout' => 'to_register5.dout',
17900 
        'en' => 'sysgen_dut.to_register5_en',
17901 
      },
17902 
      'entity' => {
17903 
        'attributes' => {
17904 
          'entityAlreadyNetlisted' => 1,
17905 
          'generics' => [],
17906 
          'is_floating_block' => 1,
17907 
          'mask' => {
17908 
            'Block_Handle' => 67.0009765625,
17909 
            'Block_handle' => 67.0009765625,
17910 
            'MDL_Handle' => 3.0009765625,
17911 
            'MDL_handle' => 3.0009765625,
17912 
            'arith_type' => 1,
17913 
            'bin_pt' => 14,
17914 
            'block_config' => 'sysgen_blockset:toreg_config',
17915 
            'block_handle' => 67.0009765625,
17916 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
17917 
            'block_type' => 'toreg',
17918 
            'dbl_ovrd' => 0,
17919 
            'explicit_data_type' => 0,
17920 
            'init' => 0,
17921 
            'init_bit_vector' => '00000000000000000000000000000000b',
17922 
            'mdl_handle' => 3.0009765625,
17923 
            'model_handle' => 3.0009765625,
17924 
            'n_bits' => 16,
17925 
            'ownership' => 1,
17926 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17927 
            'shared_memory_name' => 'register02td',
17928 
          },
17929 
          'needs_vhdl_wrapper' => 0,
17930 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
17931 
        },
17932 
        'entityName' => 'x_x28',
17933 
        'ports' => {
17934 
          'ce' => {
17935 
            'attributes' => {
17936 
              'domain' => '',
17937 
              'group' => 1,
17938 
              'isCe' => 1,
17939 
              'is_floating_block' => 1,
17940 
              'period' => 1,
17941 
              'type' => 'logic',
17942 
            },
17943 
            'direction' => 'in',
17944 
            'hdlType' => 'std_logic',
17945 
            'width' => 1,
17946 
          },
17947 
          'clk' => {
17948 
            'attributes' => {
17949 
              'domain' => '',
17950 
              'group' => 1,
17951 
              'isClk' => 1,
17952 
              'is_floating_block' => 1,
17953 
              'period' => 1,
17954 
              'type' => 'logic',
17955 
            },
17956 
            'direction' => 'in',
17957 
            'hdlType' => 'std_logic',
17958 
            'width' => 1,
17959 
          },
17960 
          'clr' => {
17961 
            'attributes' => {
17962 
              'domain' => '',
17963 
              'group' => 1,
17964 
              'isClr' => 1,
17965 
              'is_floating_block' => 1,
17966 
              'period' => 1,
17967 
              'type' => 'logic',
17968 
              'valid_bit_used' => 0,
17969 
            },
17970 
            'direction' => 'in',
17971 
            'hdlType' => 'std_logic',
17972 
            'width' => 1,
17973 
          },
17974 
          'data_in' => {
17975 
            'attributes' => {
17976 
              'bin_pt' => 0,
17977 
              'is_floating_block' => 1,
17978 
              'must_be_hdl_vector' => 1,
17979 
              'period' => 1,
17980 
              'port_id' => 0,
17981 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
17982 
              'type' => 'UFix_32_0',
17983 
            },
17984 
            'direction' => 'in',
17985 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17986 
            'width' => 32,
17987 
          },
17988 
          'dout' => {
17989 
            'attributes' => {
17990 
              'bin_pt' => 0,
17991 
              'is_floating_block' => 1,
17992 
              'must_be_hdl_vector' => 1,
17993 
              'period' => 1,
17994 
              'port_id' => 0,
17995 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
17996 
              'type' => 'UFix_32_0',
17997 
            },
17998 
            'direction' => 'out',
17999 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18000 
            'width' => 32,
18001 
          },
18002 
          'en' => {
18003 
            'attributes' => {
18004 
              'bin_pt' => 0,
18005 
              'is_floating_block' => 1,
18006 
              'must_be_hdl_vector' => 1,
18007 
              'period' => 1,
18008 
              'port_id' => 1,
18009 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
18010 
              'type' => 'Bool',
18011 
            },
18012 
            'direction' => 'in',
18013 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18014 
            'width' => 1,
18015 
          },
18016 
        },
18017 
      },
18018 
      'entityName' => 'x_x28',
18019 
    },
18020 
    'to_register6' => {
18021 
      'connections' => {
18022 
        'ce' => 'sysgen_dut.to_register6_ce',
18023 
        'clk' => 'sysgen_dut.to_register6_clk',
18024 
        'clr' => 'sysgen_dut.to_register6_clr',
18025 
        'data_in' => 'sysgen_dut.to_register6_data_in',
18026 
        'dout' => 'to_register6.dout',
18027 
        'en' => 'sysgen_dut.to_register6_en',
18028 
      },
18029 
      'entity' => {
18030 
        'attributes' => {
18031 
          'entityAlreadyNetlisted' => 1,
18032 
          'generics' => [],
18033 
          'is_floating_block' => 1,
18034 
          'mask' => {
18035 
            'Block_Handle' => 68.0009765625,
18036 
            'Block_handle' => 68.0009765625,
18037 
            'MDL_Handle' => 3.0009765625,
18038 
            'MDL_handle' => 3.0009765625,
18039 
            'arith_type' => 1,
18040 
            'bin_pt' => 14,
18041 
            'block_config' => 'sysgen_blockset:toreg_config',
18042 
            'block_handle' => 68.0009765625,
18043 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18044 
            'block_type' => 'toreg',
18045 
            'dbl_ovrd' => 0,
18046 
            'explicit_data_type' => 0,
18047 
            'init' => 0,
18048 
            'init_bit_vector' => '00000000000000000000000000000000b',
18049 
            'mdl_handle' => 3.0009765625,
18050 
            'model_handle' => 3.0009765625,
18051 
            'n_bits' => 16,
18052 
            'ownership' => 1,
18053 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18054 
            'shared_memory_name' => 'debug1i',
18055 
          },
18056 
          'needs_vhdl_wrapper' => 0,
18057 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18058 
        },
18059 
        'entityName' => 'x_x29',
18060 
        'ports' => {
18061 
          'ce' => {
18062 
            'attributes' => {
18063 
              'domain' => '',
18064 
              'group' => 1,
18065 
              'isCe' => 1,
18066 
              'is_floating_block' => 1,
18067 
              'period' => 1,
18068 
              'type' => 'logic',
18069 
            },
18070 
            'direction' => 'in',
18071 
            'hdlType' => 'std_logic',
18072 
            'width' => 1,
18073 
          },
18074 
          'clk' => {
18075 
            'attributes' => {
18076 
              'domain' => '',
18077 
              'group' => 1,
18078 
              'isClk' => 1,
18079 
              'is_floating_block' => 1,
18080 
              'period' => 1,
18081 
              'type' => 'logic',
18082 
            },
18083 
            'direction' => 'in',
18084 
            'hdlType' => 'std_logic',
18085 
            'width' => 1,
18086 
          },
18087 
          'clr' => {
18088 
            'attributes' => {
18089 
              'domain' => '',
18090 
              'group' => 1,
18091 
              'isClr' => 1,
18092 
              'is_floating_block' => 1,
18093 
              'period' => 1,
18094 
              'type' => 'logic',
18095 
              'valid_bit_used' => 0,
18096 
            },
18097 
            'direction' => 'in',
18098 
            'hdlType' => 'std_logic',
18099 
            'width' => 1,
18100 
          },
18101 
          'data_in' => {
18102 
            'attributes' => {
18103 
              'bin_pt' => 0,
18104 
              'is_floating_block' => 1,
18105 
              'must_be_hdl_vector' => 1,
18106 
              'period' => 1,
18107 
              'port_id' => 0,
18108 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
18109 
              'type' => 'UFix_32_0',
18110 
            },
18111 
            'direction' => 'in',
18112 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18113 
            'width' => 32,
18114 
          },
18115 
          'dout' => {
18116 
            'attributes' => {
18117 
              'bin_pt' => 0,
18118 
              'is_floating_block' => 1,
18119 
              'must_be_hdl_vector' => 1,
18120 
              'period' => 1,
18121 
              'port_id' => 0,
18122 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
18123 
              'type' => 'UFix_32_0',
18124 
            },
18125 
            'direction' => 'out',
18126 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18127 
            'width' => 32,
18128 
          },
18129 
          'en' => {
18130 
            'attributes' => {
18131 
              'bin_pt' => 0,
18132 
              'is_floating_block' => 1,
18133 
              'must_be_hdl_vector' => 1,
18134 
              'period' => 1,
18135 
              'port_id' => 1,
18136 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
18137 
              'type' => 'Bool',
18138 
            },
18139 
            'direction' => 'in',
18140 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18141 
            'width' => 1,
18142 
          },
18143 
        },
18144 
      },
18145 
      'entityName' => 'x_x29',
18146 
    },
18147 
    'to_register7' => {
18148 
      'connections' => {
18149 
        'ce' => 'sysgen_dut.to_register7_ce',
18150 
        'clk' => 'sysgen_dut.to_register7_clk',
18151 
        'clr' => 'sysgen_dut.to_register7_clr',
18152 
        'data_in' => 'sysgen_dut.to_register7_data_in',
18153 
        'dout' => 'to_register7.dout',
18154 
        'en' => 'sysgen_dut.to_register7_en',
18155 
      },
18156 
      'entity' => {
18157 
        'attributes' => {
18158 
          'entityAlreadyNetlisted' => 1,
18159 
          'generics' => [],
18160 
          'is_floating_block' => 1,
18161 
          'mask' => {
18162 
            'Block_Handle' => 69.0009765625,
18163 
            'Block_handle' => 69.0009765625,
18164 
            'MDL_Handle' => 3.0009765625,
18165 
            'MDL_handle' => 3.0009765625,
18166 
            'arith_type' => 1,
18167 
            'bin_pt' => 14,
18168 
            'block_config' => 'sysgen_blockset:toreg_config',
18169 
            'block_handle' => 69.0009765625,
18170 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18171 
            'block_type' => 'toreg',
18172 
            'dbl_ovrd' => 0,
18173 
            'explicit_data_type' => 0,
18174 
            'init' => 0,
18175 
            'init_bit_vector' => '00000000000000000000000000000000b',
18176 
            'mdl_handle' => 3.0009765625,
18177 
            'model_handle' => 3.0009765625,
18178 
            'n_bits' => 16,
18179 
            'ownership' => 1,
18180 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18181 
            'shared_memory_name' => 'register01td',
18182 
          },
18183 
          'needs_vhdl_wrapper' => 0,
18184 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18185 
        },
18186 
        'entityName' => 'x_x30',
18187 
        'ports' => {
18188 
          'ce' => {
18189 
            'attributes' => {
18190 
              'domain' => '',
18191 
              'group' => 1,
18192 
              'isCe' => 1,
18193 
              'is_floating_block' => 1,
18194 
              'period' => 1,
18195 
              'type' => 'logic',
18196 
            },
18197 
            'direction' => 'in',
18198 
            'hdlType' => 'std_logic',
18199 
            'width' => 1,
18200 
          },
18201 
          'clk' => {
18202 
            'attributes' => {
18203 
              'domain' => '',
18204 
              'group' => 1,
18205 
              'isClk' => 1,
18206 
              'is_floating_block' => 1,
18207 
              'period' => 1,
18208 
              'type' => 'logic',
18209 
            },
18210 
            'direction' => 'in',
18211 
            'hdlType' => 'std_logic',
18212 
            'width' => 1,
18213 
          },
18214 
          'clr' => {
18215 
            'attributes' => {
18216 
              'domain' => '',
18217 
              'group' => 1,
18218 
              'isClr' => 1,
18219 
              'is_floating_block' => 1,
18220 
              'period' => 1,
18221 
              'type' => 'logic',
18222 
              'valid_bit_used' => 0,
18223 
            },
18224 
            'direction' => 'in',
18225 
            'hdlType' => 'std_logic',
18226 
            'width' => 1,
18227 
          },
18228 
          'data_in' => {
18229 
            'attributes' => {
18230 
              'bin_pt' => 0,
18231 
              'is_floating_block' => 1,
18232 
              'must_be_hdl_vector' => 1,
18233 
              'period' => 1,
18234 
              'port_id' => 0,
18235 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
18236 
              'type' => 'UFix_32_0',
18237 
            },
18238 
            'direction' => 'in',
18239 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18240 
            'width' => 32,
18241 
          },
18242 
          'dout' => {
18243 
            'attributes' => {
18244 
              'bin_pt' => 0,
18245 
              'is_floating_block' => 1,
18246 
              'must_be_hdl_vector' => 1,
18247 
              'period' => 1,
18248 
              'port_id' => 0,
18249 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
18250 
              'type' => 'UFix_32_0',
18251 
            },
18252 
            'direction' => 'out',
18253 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18254 
            'width' => 32,
18255 
          },
18256 
          'en' => {
18257 
            'attributes' => {
18258 
              'bin_pt' => 0,
18259 
              'is_floating_block' => 1,
18260 
              'must_be_hdl_vector' => 1,
18261 
              'period' => 1,
18262 
              'port_id' => 1,
18263 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
18264 
              'type' => 'Bool',
18265 
            },
18266 
            'direction' => 'in',
18267 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18268 
            'width' => 1,
18269 
          },
18270 
        },
18271 
      },
18272 
      'entityName' => 'x_x30',
18273 
    },
18274 
    'to_register8' => {
18275 
      'connections' => {
18276 
        'ce' => 'sysgen_dut.to_register8_ce',
18277 
        'clk' => 'sysgen_dut.to_register8_clk',
18278 
        'clr' => 'sysgen_dut.to_register8_clr',
18279 
        'data_in' => 'sysgen_dut.to_register8_data_in',
18280 
        'dout' => 'to_register8.dout',
18281 
        'en' => 'sysgen_dut.to_register8_en',
18282 
      },
18283 
      'entity' => {
18284 
        'attributes' => {
18285 
          'entityAlreadyNetlisted' => 1,
18286 
          'generics' => [],
18287 
          'is_floating_block' => 1,
18288 
          'mask' => {
18289 
            'Block_Handle' => 70.0009765625,
18290 
            'Block_handle' => 70.0009765625,
18291 
            'MDL_Handle' => 3.0009765625,
18292 
            'MDL_handle' => 3.0009765625,
18293 
            'arith_type' => 1,
18294 
            'bin_pt' => 14,
18295 
            'block_config' => 'sysgen_blockset:toreg_config',
18296 
            'block_handle' => 70.0009765625,
18297 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18298 
            'block_type' => 'toreg',
18299 
            'dbl_ovrd' => 0,
18300 
            'explicit_data_type' => 0,
18301 
            'init' => 0,
18302 
            'init_bit_vector' => '0b',
18303 
            'mdl_handle' => 3.0009765625,
18304 
            'model_handle' => 3.0009765625,
18305 
            'n_bits' => 16,
18306 
            'ownership' => 1,
18307 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18308 
            'shared_memory_name' => 'register03tv',
18309 
          },
18310 
          'needs_vhdl_wrapper' => 0,
18311 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18312 
        },
18313 
        'entityName' => 'x_x31',
18314 
        'ports' => {
18315 
          'ce' => {
18316 
            'attributes' => {
18317 
              'domain' => '',
18318 
              'group' => 1,
18319 
              'isCe' => 1,
18320 
              'is_floating_block' => 1,
18321 
              'period' => 1,
18322 
              'type' => 'logic',
18323 
            },
18324 
            'direction' => 'in',
18325 
            'hdlType' => 'std_logic',
18326 
            'width' => 1,
18327 
          },
18328 
          'clk' => {
18329 
            'attributes' => {
18330 
              'domain' => '',
18331 
              'group' => 1,
18332 
              'isClk' => 1,
18333 
              'is_floating_block' => 1,
18334 
              'period' => 1,
18335 
              'type' => 'logic',
18336 
            },
18337 
            'direction' => 'in',
18338 
            'hdlType' => 'std_logic',
18339 
            'width' => 1,
18340 
          },
18341 
          'clr' => {
18342 
            'attributes' => {
18343 
              'domain' => '',
18344 
              'group' => 1,
18345 
              'isClr' => 1,
18346 
              'is_floating_block' => 1,
18347 
              'period' => 1,
18348 
              'type' => 'logic',
18349 
              'valid_bit_used' => 0,
18350 
            },
18351 
            'direction' => 'in',
18352 
            'hdlType' => 'std_logic',
18353 
            'width' => 1,
18354 
          },
18355 
          'data_in' => {
18356 
            'attributes' => {
18357 
              'bin_pt' => 0,
18358 
              'is_floating_block' => 1,
18359 
              'must_be_hdl_vector' => 1,
18360 
              'period' => 1,
18361 
              'port_id' => 0,
18362 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
18363 
              'type' => 'Bool',
18364 
            },
18365 
            'direction' => 'in',
18366 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18367 
            'width' => 1,
18368 
          },
18369 
          'dout' => {
18370 
            'attributes' => {
18371 
              'bin_pt' => 0,
18372 
              'is_floating_block' => 1,
18373 
              'must_be_hdl_vector' => 1,
18374 
              'period' => 1,
18375 
              'port_id' => 0,
18376 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
18377 
              'type' => 'Bool',
18378 
            },
18379 
            'direction' => 'out',
18380 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18381 
            'width' => 1,
18382 
          },
18383 
          'en' => {
18384 
            'attributes' => {
18385 
              'bin_pt' => 0,
18386 
              'is_floating_block' => 1,
18387 
              'must_be_hdl_vector' => 1,
18388 
              'period' => 1,
18389 
              'port_id' => 1,
18390 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
18391 
              'type' => 'Bool',
18392 
            },
18393 
            'direction' => 'in',
18394 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18395 
            'width' => 1,
18396 
          },
18397 
        },
18398 
      },
18399 
      'entityName' => 'x_x31',
18400 
    },
18401 
    'to_register9' => {
18402 
      'connections' => {
18403 
        'ce' => 'sysgen_dut.to_register9_ce',
18404 
        'clk' => 'sysgen_dut.to_register9_clk',
18405 
        'clr' => 'sysgen_dut.to_register9_clr',
18406 
        'data_in' => 'sysgen_dut.to_register9_data_in',
18407 
        'dout' => 'to_register9.dout',
18408 
        'en' => 'sysgen_dut.to_register9_en',
18409 
      },
18410 
      'entity' => {
18411 
        'attributes' => {
18412 
          'entityAlreadyNetlisted' => 1,
18413 
          'generics' => [],
18414 
          'is_floating_block' => 1,
18415 
          'mask' => {
18416 
            'Block_Handle' => 71.0009765625,
18417 
            'Block_handle' => 71.0009765625,
18418 
            'MDL_Handle' => 3.0009765625,
18419 
            'MDL_handle' => 3.0009765625,
18420 
            'arith_type' => 1,
18421 
            'bin_pt' => 14,
18422 
            'block_config' => 'sysgen_blockset:toreg_config',
18423 
            'block_handle' => 71.0009765625,
18424 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
18425 
            'block_type' => 'toreg',
18426 
            'dbl_ovrd' => 0,
18427 
            'explicit_data_type' => 0,
18428 
            'init' => 0,
18429 
            'init_bit_vector' => '00000000000000000000000000000000b',
18430 
            'mdl_handle' => 3.0009765625,
18431 
            'model_handle' => 3.0009765625,
18432 
            'n_bits' => 16,
18433 
            'ownership' => 1,
18434 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18435 
            'shared_memory_name' => 'register03td',
18436 
          },
18437 
          'needs_vhdl_wrapper' => 0,
18438 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
18439 
        },
18440 
        'entityName' => 'x_x32',
18441 
        'ports' => {
18442 
          'ce' => {
18443 
            'attributes' => {
18444 
              'domain' => '',
18445 
              'group' => 1,
18446 
              'isCe' => 1,
18447 
              'is_floating_block' => 1,
18448 
              'period' => 1,
18449 
              'type' => 'logic',
18450 
            },
18451 
            'direction' => 'in',
18452 
            'hdlType' => 'std_logic',
18453 
            'width' => 1,
18454 
          },
18455 
          'clk' => {
18456 
            'attributes' => {
18457 
              'domain' => '',
18458 
              'group' => 1,
18459 
              'isClk' => 1,
18460 
              'is_floating_block' => 1,
18461 
              'period' => 1,
18462 
              'type' => 'logic',
18463 
            },
18464 
            'direction' => 'in',
18465 
            'hdlType' => 'std_logic',
18466 
            'width' => 1,
18467 
          },
18468 
          'clr' => {
18469 
            'attributes' => {
18470 
              'domain' => '',
18471 
              'group' => 1,
18472 
              'isClr' => 1,
18473 
              'is_floating_block' => 1,
18474 
              'period' => 1,
18475 
              'type' => 'logic',
18476 
              'valid_bit_used' => 0,
18477 
            },
18478 
            'direction' => 'in',
18479 
            'hdlType' => 'std_logic',
18480 
            'width' => 1,
18481 
          },
18482 
          'data_in' => {
18483 
            'attributes' => {
18484 
              'bin_pt' => 0,
18485 
              'is_floating_block' => 1,
18486 
              'must_be_hdl_vector' => 1,
18487 
              'period' => 1,
18488 
              'port_id' => 0,
18489 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
18490 
              'type' => 'UFix_32_0',
18491 
            },
18492 
            'direction' => 'in',
18493 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18494 
            'width' => 32,
18495 
          },
18496 
          'dout' => {
18497 
            'attributes' => {
18498 
              'bin_pt' => 0,
18499 
              'is_floating_block' => 1,
18500 
              'must_be_hdl_vector' => 1,
18501 
              'period' => 1,
18502 
              'port_id' => 0,
18503 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
18504 
              'type' => 'UFix_32_0',
18505 
            },
18506 
            'direction' => 'out',
18507 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18508 
            'width' => 32,
18509 
          },
18510 
          'en' => {
18511 
            'attributes' => {
18512 
              'bin_pt' => 0,
18513 
              'is_floating_block' => 1,
18514 
              'must_be_hdl_vector' => 1,
18515 
              'period' => 1,
18516 
              'port_id' => 1,
18517 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
18518 
              'type' => 'Bool',
18519 
            },
18520 
            'direction' => 'in',
18521 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18522 
            'width' => 1,
18523 
          },
18524 
        },
18525 
      },
18526 
      'entityName' => 'x_x32',
18527 
    },
18528 
  },
18529 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.