OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis_com.xilinx.sysgen.netlister.ClockWrapper] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0,
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    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
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    'Impl_file' => 'ISE Defaults',
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    'Impl_file_sgadvanced' => '',
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    'Synth_file' => 'XST Defaults',
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    'Synth_file_sgadvanced' => '',
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    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'base_system_period_hardware' => 5,
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    'base_system_period_simulink' => '8e-009',
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    'block_icon_display' => 'Default',
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    'block_type' => 'sysgen',
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    'block_version' => '',
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    'ce_clr' => 0,
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    'clkWrapper' => 'inout_logic_cw',
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    'clkWrapperFile' => 'inout_logic_cw.vhd',
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    'clock_loc' => '',
22 
    'clock_wrapper' => 'Clock Enables',
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    'clock_wrapper_sgadvanced' => '',
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    'compilation' => 'NGC Netlist',
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    'compilation_lut' => {
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      'keys' => [
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        'HDL Netlist',
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        'Bitstream',
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      'values' => [
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        'target1',
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        'target2',
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        'target3',
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      ],
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    },
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    'compilation_target' => 'NGC Netlist',
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    'core_generation' => 1,
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    'core_generation_sgadvanced' => '',
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    'core_is_deployed' => 0,
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    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c00613f6911dfdaa6',
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    'coregen_part_family' => 'virtex6',
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    'createTestbench' => 0,
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    'create_interface_document' => 'off',
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    'dbl_ovrd' => -1,
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    'dbl_ovrd_sgadvanced' => '',
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    'dcm_info' => {},
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    'dcm_input_clock_period' => 5,
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    'deprecated_control' => 'off',
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    'deprecated_control_sgadvanced' => '',
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    'design' => 'inout_logic',
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    'designFile' => 'inout_logic.vhd',
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    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\pcie-v6-ml605_ISE12_OpenCores\\MySysGen\\PCIe_UserLogic_00.mdl',
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    'device_speed' => -3,
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    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
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    'entityNamingInstrs' => {
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      'nameMap' => undef,
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      'namesAlreadyUsed' => {
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        'default_clock_driver' => 1,
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        'inout_logic_cw' => 1,
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      },
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    },
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    'fileAttributes' => {
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      'nonleaf_results.vhd' => { 'producer' => 'nonleafNetlister', },
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    },
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      'xlpersistentdff.ngc',
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      'synopsis',
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      'inout_logic.vhd',
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      'xlpersistentdff.ngc',
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      'inout_logic_cw.vhd',
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    ],
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    'generating_subsystem_handle' => 4.0009765625,
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    'generation_directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
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    'has_advanced_control' => 0,
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    'hdlKind' => 'vhdl',
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    'hdl_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
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    'impl_file' => 'ISE Defaults*',
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    'incr_netlist' => 'off',
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    'incr_netlist_sgadvanced' => '',
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    'infoedit' => ' System Generator',
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    'isCombinatorial' => 1,
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    'isdeployed' => 0,
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    'ise_version' => '12.3i',
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    'master_sysgen_token_handle' => 5.0009765625,
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    'matlab_fixedpoint' => 1,
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    'mdlHandle' => 3.0009765625,
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        'type' => 'Xilinx Shared Memory Based From Register Block',
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        'isMask' => 1,
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        'type' => 'Xilinx Subsystem Generator Block',
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        'count' => 2,
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        'isMask' => 1,
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        'type' => 'Xilinx System Generator Block',
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      },
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        'count' => 14,
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        'isMask' => 1,
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        'type' => 'Xilinx Type Converter Block',
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      },
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    ],
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    'model_globals_initialized' => 1,
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    'model_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
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    'myxilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
187 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
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    'ngc_config' => {
189 
      'include_cf' => 1,
190 
      'include_clockwrapper' => 1,
191 
    },
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    'ngc_files' => [ 'xlpersistentdff.ngc', ],
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    'num_sim_cycles' => 1250000000,
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    'package' => 'ff784',
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    'part' => 'xc6vlx240t',
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    'partFamily' => 'virtex6',
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    'port_data_types_enabled' => 1,
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    'postgeneration_fcn' => 'xlNGCPostGeneration',
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    'preserve_hierarchy' => 0,
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    'proj_type_sgadvanced' => '',
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    'run_coregen' => 'off',
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    'run_coregen_sgadvanced' => '',
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    'sample_time_colors_enabled' => 1,
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    'sampletimecolors' => 1,
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    'settings_fcn' => 'xlngcsettings',
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    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
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    'sg_list_contents' => '',
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    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
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patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
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patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
216 
fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
218 
fprintf(\'\',\'COMMENT: end icon text\');',
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    'simulink_accelerator_running' => 0,
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    'simulink_period' => '8e-009',
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    'synthesis_language' => 'vhdl',
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    'synthesis_tool' => 'XST',
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      'Synth_file' => 'XST Defaults',
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      'Synth_file_sgadvanced' => '',
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      'base_system_period_hardware' => 5,
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patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
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patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
303 
fprintf(\'\',\'COMMENT: end icon text\');',
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      'sggui_pos' => '-1,-1,-1,-1',
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      'xilinx_device' => 'xc6vlx240t-3ff784',
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    },
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    '.reg12_td' => {
474 
      'hdlType' => 'std_logic_vector(31 downto 0)',
475 
      'width' => 32,
476 
    },
477 
    '.reg12_tv' => {
478 
      'hdlType' => 'std_logic',
479 
      'width' => 1,
480 
    },
481 
    '.reg13_td' => {
482 
      'hdlType' => 'std_logic_vector(31 downto 0)',
483 
      'width' => 32,
484 
    },
485 
    '.reg13_tv' => {
486 
      'hdlType' => 'std_logic',
487 
      'width' => 1,
488 
    },
489 
    '.reg14_td' => {
490 
      'hdlType' => 'std_logic_vector(31 downto 0)',
491 
      'width' => 32,
492 
    },
493 
    '.reg14_tv' => {
494 
      'hdlType' => 'std_logic',
495 
      'width' => 1,
496 
    },
497 
    'from_register1.data_out' => {
498 
      'hdlType' => 'std_logic',
499 
      'width' => 1,
500 
    },
501 
    'from_register10.data_out' => {
502 
      'hdlType' => 'std_logic_vector(31 downto 0)',
503 
      'width' => 32,
504 
    },
505 
    'from_register11.data_out' => {
506 
      'hdlType' => 'std_logic_vector(31 downto 0)',
507 
      'width' => 32,
508 
    },
509 
    'from_register12.data_out' => {
510 
      'hdlType' => 'std_logic',
511 
      'width' => 1,
512 
    },
513 
    'from_register13.data_out' => {
514 
      'hdlType' => 'std_logic_vector(31 downto 0)',
515 
      'width' => 32,
516 
    },
517 
    'from_register14.data_out' => {
518 
      'hdlType' => 'std_logic',
519 
      'width' => 1,
520 
    },
521 
    'from_register15.data_out' => {
522 
      'hdlType' => 'std_logic_vector(31 downto 0)',
523 
      'width' => 32,
524 
    },
525 
    'from_register16.data_out' => {
526 
      'hdlType' => 'std_logic',
527 
      'width' => 1,
528 
    },
529 
    'from_register17.data_out' => {
530 
      'hdlType' => 'std_logic_vector(31 downto 0)',
531 
      'width' => 32,
532 
    },
533 
    'from_register18.data_out' => {
534 
      'hdlType' => 'std_logic',
535 
      'width' => 1,
536 
    },
537 
    'from_register19.data_out' => {
538 
      'hdlType' => 'std_logic_vector(31 downto 0)',
539 
      'width' => 32,
540 
    },
541 
    'from_register2.data_out' => {
542 
      'hdlType' => 'std_logic',
543 
      'width' => 1,
544 
    },
545 
    'from_register20.data_out' => {
546 
      'hdlType' => 'std_logic',
547 
      'width' => 1,
548 
    },
549 
    'from_register21.data_out' => {
550 
      'hdlType' => 'std_logic_vector(31 downto 0)',
551 
      'width' => 32,
552 
    },
553 
    'from_register22.data_out' => {
554 
      'hdlType' => 'std_logic',
555 
      'width' => 1,
556 
    },
557 
    'from_register23.data_out' => {
558 
      'hdlType' => 'std_logic_vector(31 downto 0)',
559 
      'width' => 32,
560 
    },
561 
    'from_register24.data_out' => {
562 
      'hdlType' => 'std_logic',
563 
      'width' => 1,
564 
    },
565 
    'from_register25.data_out' => {
566 
      'hdlType' => 'std_logic_vector(31 downto 0)',
567 
      'width' => 32,
568 
    },
569 
    'from_register26.data_out' => {
570 
      'hdlType' => 'std_logic',
571 
      'width' => 1,
572 
    },
573 
    'from_register27.data_out' => {
574 
      'hdlType' => 'std_logic_vector(31 downto 0)',
575 
      'width' => 32,
576 
    },
577 
    'from_register28.data_out' => {
578 
      'hdlType' => 'std_logic',
579 
      'width' => 1,
580 
    },
581 
    'from_register3.data_out' => {
582 
      'hdlType' => 'std_logic_vector(31 downto 0)',
583 
      'width' => 32,
584 
    },
585 
    'from_register4.data_out' => {
586 
      'hdlType' => 'std_logic',
587 
      'width' => 1,
588 
    },
589 
    'from_register5.data_out' => {
590 
      'hdlType' => 'std_logic_vector(31 downto 0)',
591 
      'width' => 32,
592 
    },
593 
    'from_register6.data_out' => {
594 
      'hdlType' => 'std_logic',
595 
      'width' => 1,
596 
    },
597 
    'from_register7.data_out' => {
598 
      'hdlType' => 'std_logic_vector(31 downto 0)',
599 
      'width' => 32,
600 
    },
601 
    'from_register8.data_out' => {
602 
      'hdlType' => 'std_logic_vector(31 downto 0)',
603 
      'width' => 32,
604 
    },
605 
    'from_register9.data_out' => {
606 
      'hdlType' => 'std_logic',
607 
      'width' => 1,
608 
    },
609 
    'sysgen_dut.reg01_rd' => {
610 
      'hdlType' => 'std_logic_vector(31 downto 0)',
611 
      'width' => 32,
612 
    },
613 
    'sysgen_dut.reg01_rv' => {
614 
      'hdlType' => 'std_logic',
615 
      'width' => 1,
616 
    },
617 
    'sysgen_dut.reg02_rd' => {
618 
      'hdlType' => 'std_logic_vector(31 downto 0)',
619 
      'width' => 32,
620 
    },
621 
    'sysgen_dut.reg02_rv' => {
622 
      'hdlType' => 'std_logic',
623 
      'width' => 1,
624 
    },
625 
    'sysgen_dut.reg03_rd' => {
626 
      'hdlType' => 'std_logic_vector(31 downto 0)',
627 
      'width' => 32,
628 
    },
629 
    'sysgen_dut.reg03_rv' => {
630 
      'hdlType' => 'std_logic',
631 
      'width' => 1,
632 
    },
633 
    'sysgen_dut.reg04_rd' => {
634 
      'hdlType' => 'std_logic_vector(31 downto 0)',
635 
      'width' => 32,
636 
    },
637 
    'sysgen_dut.reg04_rv' => {
638 
      'hdlType' => 'std_logic',
639 
      'width' => 1,
640 
    },
641 
    'sysgen_dut.reg05_rd' => {
642 
      'hdlType' => 'std_logic_vector(31 downto 0)',
643 
      'width' => 32,
644 
    },
645 
    'sysgen_dut.reg05_rv' => {
646 
      'hdlType' => 'std_logic',
647 
      'width' => 1,
648 
    },
649 
    'sysgen_dut.reg06_rd' => {
650 
      'hdlType' => 'std_logic_vector(31 downto 0)',
651 
      'width' => 32,
652 
    },
653 
    'sysgen_dut.reg06_rv' => {
654 
      'hdlType' => 'std_logic',
655 
      'width' => 1,
656 
    },
657 
    'sysgen_dut.reg07_rd' => {
658 
      'hdlType' => 'std_logic_vector(31 downto 0)',
659 
      'width' => 32,
660 
    },
661 
    'sysgen_dut.reg07_rv' => {
662 
      'hdlType' => 'std_logic',
663 
      'width' => 1,
664 
    },
665 
    'sysgen_dut.reg08_rd' => {
666 
      'hdlType' => 'std_logic_vector(31 downto 0)',
667 
      'width' => 32,
668 
    },
669 
    'sysgen_dut.reg08_rv' => {
670 
      'hdlType' => 'std_logic',
671 
      'width' => 1,
672 
    },
673 
    'sysgen_dut.reg09_rd' => {
674 
      'hdlType' => 'std_logic_vector(31 downto 0)',
675 
      'width' => 32,
676 
    },
677 
    'sysgen_dut.reg09_rv' => {
678 
      'hdlType' => 'std_logic',
679 
      'width' => 1,
680 
    },
681 
    'sysgen_dut.reg10_rd' => {
682 
      'hdlType' => 'std_logic_vector(31 downto 0)',
683 
      'width' => 32,
684 
    },
685 
    'sysgen_dut.reg10_rv' => {
686 
      'hdlType' => 'std_logic',
687 
      'width' => 1,
688 
    },
689 
    'sysgen_dut.reg11_rd' => {
690 
      'hdlType' => 'std_logic_vector(31 downto 0)',
691 
      'width' => 32,
692 
    },
693 
    'sysgen_dut.reg11_rv' => {
694 
      'hdlType' => 'std_logic',
695 
      'width' => 1,
696 
    },
697 
    'sysgen_dut.reg12_rd' => {
698 
      'hdlType' => 'std_logic_vector(31 downto 0)',
699 
      'width' => 32,
700 
    },
701 
    'sysgen_dut.reg12_rv' => {
702 
      'hdlType' => 'std_logic',
703 
      'width' => 1,
704 
    },
705 
    'sysgen_dut.reg13_rd' => {
706 
      'hdlType' => 'std_logic_vector(31 downto 0)',
707 
      'width' => 32,
708 
    },
709 
    'sysgen_dut.reg13_rv' => {
710 
      'hdlType' => 'std_logic',
711 
      'width' => 1,
712 
    },
713 
    'sysgen_dut.reg14_rd' => {
714 
      'hdlType' => 'std_logic_vector(31 downto 0)',
715 
      'width' => 32,
716 
    },
717 
    'sysgen_dut.reg14_rv' => {
718 
      'hdlType' => 'std_logic',
719 
      'width' => 1,
720 
    },
721 
    'sysgen_dut.to_register10_ce' => {
722 
      'hdlType' => 'std_logic',
723 
      'width' => 1,
724 
    },
725 
    'sysgen_dut.to_register10_clk' => {
726 
      'hdlType' => 'std_logic',
727 
      'width' => 1,
728 
    },
729 
    'sysgen_dut.to_register10_clr' => {
730 
      'hdlType' => 'std_logic',
731 
      'width' => 1,
732 
    },
733 
    'sysgen_dut.to_register10_data_in' => {
734 
      'hdlType' => 'std_logic',
735 
      'width' => 1,
736 
    },
737 
    'sysgen_dut.to_register10_en' => {
738 
      'hdlType' => 'std_logic',
739 
      'width' => 1,
740 
    },
741 
    'sysgen_dut.to_register11_ce' => {
742 
      'hdlType' => 'std_logic',
743 
      'width' => 1,
744 
    },
745 
    'sysgen_dut.to_register11_clk' => {
746 
      'hdlType' => 'std_logic',
747 
      'width' => 1,
748 
    },
749 
    'sysgen_dut.to_register11_clr' => {
750 
      'hdlType' => 'std_logic',
751 
      'width' => 1,
752 
    },
753 
    'sysgen_dut.to_register11_data_in' => {
754 
      'hdlType' => 'std_logic_vector(31 downto 0)',
755 
      'width' => 32,
756 
    },
757 
    'sysgen_dut.to_register11_en' => {
758 
      'hdlType' => 'std_logic',
759 
      'width' => 1,
760 
    },
761 
    'sysgen_dut.to_register12_ce' => {
762 
      'hdlType' => 'std_logic',
763 
      'width' => 1,
764 
    },
765 
    'sysgen_dut.to_register12_clk' => {
766 
      'hdlType' => 'std_logic',
767 
      'width' => 1,
768 
    },
769 
    'sysgen_dut.to_register12_clr' => {
770 
      'hdlType' => 'std_logic',
771 
      'width' => 1,
772 
    },
773 
    'sysgen_dut.to_register12_data_in' => {
774 
      'hdlType' => 'std_logic',
775 
      'width' => 1,
776 
    },
777 
    'sysgen_dut.to_register12_en' => {
778 
      'hdlType' => 'std_logic',
779 
      'width' => 1,
780 
    },
781 
    'sysgen_dut.to_register13_ce' => {
782 
      'hdlType' => 'std_logic',
783 
      'width' => 1,
784 
    },
785 
    'sysgen_dut.to_register13_clk' => {
786 
      'hdlType' => 'std_logic',
787 
      'width' => 1,
788 
    },
789 
    'sysgen_dut.to_register13_clr' => {
790 
      'hdlType' => 'std_logic',
791 
      'width' => 1,
792 
    },
793 
    'sysgen_dut.to_register13_data_in' => {
794 
      'hdlType' => 'std_logic_vector(31 downto 0)',
795 
      'width' => 32,
796 
    },
797 
    'sysgen_dut.to_register13_en' => {
798 
      'hdlType' => 'std_logic',
799 
      'width' => 1,
800 
    },
801 
    'sysgen_dut.to_register14_ce' => {
802 
      'hdlType' => 'std_logic',
803 
      'width' => 1,
804 
    },
805 
    'sysgen_dut.to_register14_clk' => {
806 
      'hdlType' => 'std_logic',
807 
      'width' => 1,
808 
    },
809 
    'sysgen_dut.to_register14_clr' => {
810 
      'hdlType' => 'std_logic',
811 
      'width' => 1,
812 
    },
813 
    'sysgen_dut.to_register14_data_in' => {
814 
      'hdlType' => 'std_logic',
815 
      'width' => 1,
816 
    },
817 
    'sysgen_dut.to_register14_en' => {
818 
      'hdlType' => 'std_logic',
819 
      'width' => 1,
820 
    },
821 
    'sysgen_dut.to_register15_ce' => {
822 
      'hdlType' => 'std_logic',
823 
      'width' => 1,
824 
    },
825 
    'sysgen_dut.to_register15_clk' => {
826 
      'hdlType' => 'std_logic',
827 
      'width' => 1,
828 
    },
829 
    'sysgen_dut.to_register15_clr' => {
830 
      'hdlType' => 'std_logic',
831 
      'width' => 1,
832 
    },
833 
    'sysgen_dut.to_register15_data_in' => {
834 
      'hdlType' => 'std_logic_vector(31 downto 0)',
835 
      'width' => 32,
836 
    },
837 
    'sysgen_dut.to_register15_en' => {
838 
      'hdlType' => 'std_logic',
839 
      'width' => 1,
840 
    },
841 
    'sysgen_dut.to_register16_ce' => {
842 
      'hdlType' => 'std_logic',
843 
      'width' => 1,
844 
    },
845 
    'sysgen_dut.to_register16_clk' => {
846 
      'hdlType' => 'std_logic',
847 
      'width' => 1,
848 
    },
849 
    'sysgen_dut.to_register16_clr' => {
850 
      'hdlType' => 'std_logic',
851 
      'width' => 1,
852 
    },
853 
    'sysgen_dut.to_register16_data_in' => {
854 
      'hdlType' => 'std_logic',
855 
      'width' => 1,
856 
    },
857 
    'sysgen_dut.to_register16_en' => {
858 
      'hdlType' => 'std_logic',
859 
      'width' => 1,
860 
    },
861 
    'sysgen_dut.to_register17_ce' => {
862 
      'hdlType' => 'std_logic',
863 
      'width' => 1,
864 
    },
865 
    'sysgen_dut.to_register17_clk' => {
866 
      'hdlType' => 'std_logic',
867 
      'width' => 1,
868 
    },
869 
    'sysgen_dut.to_register17_clr' => {
870 
      'hdlType' => 'std_logic',
871 
      'width' => 1,
872 
    },
873 
    'sysgen_dut.to_register17_data_in' => {
874 
      'hdlType' => 'std_logic_vector(31 downto 0)',
875 
      'width' => 32,
876 
    },
877 
    'sysgen_dut.to_register17_en' => {
878 
      'hdlType' => 'std_logic',
879 
      'width' => 1,
880 
    },
881 
    'sysgen_dut.to_register18_ce' => {
882 
      'hdlType' => 'std_logic',
883 
      'width' => 1,
884 
    },
885 
    'sysgen_dut.to_register18_clk' => {
886 
      'hdlType' => 'std_logic',
887 
      'width' => 1,
888 
    },
889 
    'sysgen_dut.to_register18_clr' => {
890 
      'hdlType' => 'std_logic',
891 
      'width' => 1,
892 
    },
893 
    'sysgen_dut.to_register18_data_in' => {
894 
      'hdlType' => 'std_logic',
895 
      'width' => 1,
896 
    },
897 
    'sysgen_dut.to_register18_en' => {
898 
      'hdlType' => 'std_logic',
899 
      'width' => 1,
900 
    },
901 
    'sysgen_dut.to_register19_ce' => {
902 
      'hdlType' => 'std_logic',
903 
      'width' => 1,
904 
    },
905 
    'sysgen_dut.to_register19_clk' => {
906 
      'hdlType' => 'std_logic',
907 
      'width' => 1,
908 
    },
909 
    'sysgen_dut.to_register19_clr' => {
910 
      'hdlType' => 'std_logic',
911 
      'width' => 1,
912 
    },
913 
    'sysgen_dut.to_register19_data_in' => {
914 
      'hdlType' => 'std_logic',
915 
      'width' => 1,
916 
    },
917 
    'sysgen_dut.to_register19_en' => {
918 
      'hdlType' => 'std_logic',
919 
      'width' => 1,
920 
    },
921 
    'sysgen_dut.to_register1_ce' => {
922 
      'hdlType' => 'std_logic',
923 
      'width' => 1,
924 
    },
925 
    'sysgen_dut.to_register1_clk' => {
926 
      'hdlType' => 'std_logic',
927 
      'width' => 1,
928 
    },
929 
    'sysgen_dut.to_register1_clr' => {
930 
      'hdlType' => 'std_logic',
931 
      'width' => 1,
932 
    },
933 
    'sysgen_dut.to_register1_data_in' => {
934 
      'hdlType' => 'std_logic_vector(31 downto 0)',
935 
      'width' => 32,
936 
    },
937 
    'sysgen_dut.to_register1_en' => {
938 
      'hdlType' => 'std_logic',
939 
      'width' => 1,
940 
    },
941 
    'sysgen_dut.to_register20_ce' => {
942 
      'hdlType' => 'std_logic',
943 
      'width' => 1,
944 
    },
945 
    'sysgen_dut.to_register20_clk' => {
946 
      'hdlType' => 'std_logic',
947 
      'width' => 1,
948 
    },
949 
    'sysgen_dut.to_register20_clr' => {
950 
      'hdlType' => 'std_logic',
951 
      'width' => 1,
952 
    },
953 
    'sysgen_dut.to_register20_data_in' => {
954 
      'hdlType' => 'std_logic_vector(31 downto 0)',
955 
      'width' => 32,
956 
    },
957 
    'sysgen_dut.to_register20_en' => {
958 
      'hdlType' => 'std_logic',
959 
      'width' => 1,
960 
    },
961 
    'sysgen_dut.to_register21_ce' => {
962 
      'hdlType' => 'std_logic',
963 
      'width' => 1,
964 
    },
965 
    'sysgen_dut.to_register21_clk' => {
966 
      'hdlType' => 'std_logic',
967 
      'width' => 1,
968 
    },
969 
    'sysgen_dut.to_register21_clr' => {
970 
      'hdlType' => 'std_logic',
971 
      'width' => 1,
972 
    },
973 
    'sysgen_dut.to_register21_data_in' => {
974 
      'hdlType' => 'std_logic',
975 
      'width' => 1,
976 
    },
977 
    'sysgen_dut.to_register21_en' => {
978 
      'hdlType' => 'std_logic',
979 
      'width' => 1,
980 
    },
981 
    'sysgen_dut.to_register22_ce' => {
982 
      'hdlType' => 'std_logic',
983 
      'width' => 1,
984 
    },
985 
    'sysgen_dut.to_register22_clk' => {
986 
      'hdlType' => 'std_logic',
987 
      'width' => 1,
988 
    },
989 
    'sysgen_dut.to_register22_clr' => {
990 
      'hdlType' => 'std_logic',
991 
      'width' => 1,
992 
    },
993 
    'sysgen_dut.to_register22_data_in' => {
994 
      'hdlType' => 'std_logic_vector(31 downto 0)',
995 
      'width' => 32,
996 
    },
997 
    'sysgen_dut.to_register22_en' => {
998 
      'hdlType' => 'std_logic',
999 
      'width' => 1,
1000 
    },
1001 
    'sysgen_dut.to_register23_ce' => {
1002 
      'hdlType' => 'std_logic',
1003 
      'width' => 1,
1004 
    },
1005 
    'sysgen_dut.to_register23_clk' => {
1006 
      'hdlType' => 'std_logic',
1007 
      'width' => 1,
1008 
    },
1009 
    'sysgen_dut.to_register23_clr' => {
1010 
      'hdlType' => 'std_logic',
1011 
      'width' => 1,
1012 
    },
1013 
    'sysgen_dut.to_register23_data_in' => {
1014 
      'hdlType' => 'std_logic',
1015 
      'width' => 1,
1016 
    },
1017 
    'sysgen_dut.to_register23_en' => {
1018 
      'hdlType' => 'std_logic',
1019 
      'width' => 1,
1020 
    },
1021 
    'sysgen_dut.to_register24_ce' => {
1022 
      'hdlType' => 'std_logic',
1023 
      'width' => 1,
1024 
    },
1025 
    'sysgen_dut.to_register24_clk' => {
1026 
      'hdlType' => 'std_logic',
1027 
      'width' => 1,
1028 
    },
1029 
    'sysgen_dut.to_register24_clr' => {
1030 
      'hdlType' => 'std_logic',
1031 
      'width' => 1,
1032 
    },
1033 
    'sysgen_dut.to_register24_data_in' => {
1034 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1035 
      'width' => 32,
1036 
    },
1037 
    'sysgen_dut.to_register24_en' => {
1038 
      'hdlType' => 'std_logic',
1039 
      'width' => 1,
1040 
    },
1041 
    'sysgen_dut.to_register25_ce' => {
1042 
      'hdlType' => 'std_logic',
1043 
      'width' => 1,
1044 
    },
1045 
    'sysgen_dut.to_register25_clk' => {
1046 
      'hdlType' => 'std_logic',
1047 
      'width' => 1,
1048 
    },
1049 
    'sysgen_dut.to_register25_clr' => {
1050 
      'hdlType' => 'std_logic',
1051 
      'width' => 1,
1052 
    },
1053 
    'sysgen_dut.to_register25_data_in' => {
1054 
      'hdlType' => 'std_logic',
1055 
      'width' => 1,
1056 
    },
1057 
    'sysgen_dut.to_register25_en' => {
1058 
      'hdlType' => 'std_logic',
1059 
      'width' => 1,
1060 
    },
1061 
    'sysgen_dut.to_register26_ce' => {
1062 
      'hdlType' => 'std_logic',
1063 
      'width' => 1,
1064 
    },
1065 
    'sysgen_dut.to_register26_clk' => {
1066 
      'hdlType' => 'std_logic',
1067 
      'width' => 1,
1068 
    },
1069 
    'sysgen_dut.to_register26_clr' => {
1070 
      'hdlType' => 'std_logic',
1071 
      'width' => 1,
1072 
    },
1073 
    'sysgen_dut.to_register26_data_in' => {
1074 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1075 
      'width' => 32,
1076 
    },
1077 
    'sysgen_dut.to_register26_en' => {
1078 
      'hdlType' => 'std_logic',
1079 
      'width' => 1,
1080 
    },
1081 
    'sysgen_dut.to_register27_ce' => {
1082 
      'hdlType' => 'std_logic',
1083 
      'width' => 1,
1084 
    },
1085 
    'sysgen_dut.to_register27_clk' => {
1086 
      'hdlType' => 'std_logic',
1087 
      'width' => 1,
1088 
    },
1089 
    'sysgen_dut.to_register27_clr' => {
1090 
      'hdlType' => 'std_logic',
1091 
      'width' => 1,
1092 
    },
1093 
    'sysgen_dut.to_register27_data_in' => {
1094 
      'hdlType' => 'std_logic',
1095 
      'width' => 1,
1096 
    },
1097 
    'sysgen_dut.to_register27_en' => {
1098 
      'hdlType' => 'std_logic',
1099 
      'width' => 1,
1100 
    },
1101 
    'sysgen_dut.to_register28_ce' => {
1102 
      'hdlType' => 'std_logic',
1103 
      'width' => 1,
1104 
    },
1105 
    'sysgen_dut.to_register28_clk' => {
1106 
      'hdlType' => 'std_logic',
1107 
      'width' => 1,
1108 
    },
1109 
    'sysgen_dut.to_register28_clr' => {
1110 
      'hdlType' => 'std_logic',
1111 
      'width' => 1,
1112 
    },
1113 
    'sysgen_dut.to_register28_data_in' => {
1114 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1115 
      'width' => 32,
1116 
    },
1117 
    'sysgen_dut.to_register28_en' => {
1118 
      'hdlType' => 'std_logic',
1119 
      'width' => 1,
1120 
    },
1121 
    'sysgen_dut.to_register29_ce' => {
1122 
      'hdlType' => 'std_logic',
1123 
      'width' => 1,
1124 
    },
1125 
    'sysgen_dut.to_register29_clk' => {
1126 
      'hdlType' => 'std_logic',
1127 
      'width' => 1,
1128 
    },
1129 
    'sysgen_dut.to_register29_clr' => {
1130 
      'hdlType' => 'std_logic',
1131 
      'width' => 1,
1132 
    },
1133 
    'sysgen_dut.to_register29_data_in' => {
1134 
      'hdlType' => 'std_logic',
1135 
      'width' => 1,
1136 
    },
1137 
    'sysgen_dut.to_register29_en' => {
1138 
      'hdlType' => 'std_logic',
1139 
      'width' => 1,
1140 
    },
1141 
    'sysgen_dut.to_register2_ce' => {
1142 
      'hdlType' => 'std_logic',
1143 
      'width' => 1,
1144 
    },
1145 
    'sysgen_dut.to_register2_clk' => {
1146 
      'hdlType' => 'std_logic',
1147 
      'width' => 1,
1148 
    },
1149 
    'sysgen_dut.to_register2_clr' => {
1150 
      'hdlType' => 'std_logic',
1151 
      'width' => 1,
1152 
    },
1153 
    'sysgen_dut.to_register2_data_in' => {
1154 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1155 
      'width' => 32,
1156 
    },
1157 
    'sysgen_dut.to_register2_en' => {
1158 
      'hdlType' => 'std_logic',
1159 
      'width' => 1,
1160 
    },
1161 
    'sysgen_dut.to_register30_ce' => {
1162 
      'hdlType' => 'std_logic',
1163 
      'width' => 1,
1164 
    },
1165 
    'sysgen_dut.to_register30_clk' => {
1166 
      'hdlType' => 'std_logic',
1167 
      'width' => 1,
1168 
    },
1169 
    'sysgen_dut.to_register30_clr' => {
1170 
      'hdlType' => 'std_logic',
1171 
      'width' => 1,
1172 
    },
1173 
    'sysgen_dut.to_register30_data_in' => {
1174 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1175 
      'width' => 32,
1176 
    },
1177 
    'sysgen_dut.to_register30_en' => {
1178 
      'hdlType' => 'std_logic',
1179 
      'width' => 1,
1180 
    },
1181 
    'sysgen_dut.to_register31_ce' => {
1182 
      'hdlType' => 'std_logic',
1183 
      'width' => 1,
1184 
    },
1185 
    'sysgen_dut.to_register31_clk' => {
1186 
      'hdlType' => 'std_logic',
1187 
      'width' => 1,
1188 
    },
1189 
    'sysgen_dut.to_register31_clr' => {
1190 
      'hdlType' => 'std_logic',
1191 
      'width' => 1,
1192 
    },
1193 
    'sysgen_dut.to_register31_data_in' => {
1194 
      'hdlType' => 'std_logic',
1195 
      'width' => 1,
1196 
    },
1197 
    'sysgen_dut.to_register31_en' => {
1198 
      'hdlType' => 'std_logic',
1199 
      'width' => 1,
1200 
    },
1201 
    'sysgen_dut.to_register32_ce' => {
1202 
      'hdlType' => 'std_logic',
1203 
      'width' => 1,
1204 
    },
1205 
    'sysgen_dut.to_register32_clk' => {
1206 
      'hdlType' => 'std_logic',
1207 
      'width' => 1,
1208 
    },
1209 
    'sysgen_dut.to_register32_clr' => {
1210 
      'hdlType' => 'std_logic',
1211 
      'width' => 1,
1212 
    },
1213 
    'sysgen_dut.to_register32_data_in' => {
1214 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1215 
      'width' => 32,
1216 
    },
1217 
    'sysgen_dut.to_register32_en' => {
1218 
      'hdlType' => 'std_logic',
1219 
      'width' => 1,
1220 
    },
1221 
    'sysgen_dut.to_register33_ce' => {
1222 
      'hdlType' => 'std_logic',
1223 
      'width' => 1,
1224 
    },
1225 
    'sysgen_dut.to_register33_clk' => {
1226 
      'hdlType' => 'std_logic',
1227 
      'width' => 1,
1228 
    },
1229 
    'sysgen_dut.to_register33_clr' => {
1230 
      'hdlType' => 'std_logic',
1231 
      'width' => 1,
1232 
    },
1233 
    'sysgen_dut.to_register33_data_in' => {
1234 
      'hdlType' => 'std_logic',
1235 
      'width' => 1,
1236 
    },
1237 
    'sysgen_dut.to_register33_en' => {
1238 
      'hdlType' => 'std_logic',
1239 
      'width' => 1,
1240 
    },
1241 
    'sysgen_dut.to_register34_ce' => {
1242 
      'hdlType' => 'std_logic',
1243 
      'width' => 1,
1244 
    },
1245 
    'sysgen_dut.to_register34_clk' => {
1246 
      'hdlType' => 'std_logic',
1247 
      'width' => 1,
1248 
    },
1249 
    'sysgen_dut.to_register34_clr' => {
1250 
      'hdlType' => 'std_logic',
1251 
      'width' => 1,
1252 
    },
1253 
    'sysgen_dut.to_register34_data_in' => {
1254 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1255 
      'width' => 32,
1256 
    },
1257 
    'sysgen_dut.to_register34_en' => {
1258 
      'hdlType' => 'std_logic',
1259 
      'width' => 1,
1260 
    },
1261 
    'sysgen_dut.to_register3_ce' => {
1262 
      'hdlType' => 'std_logic',
1263 
      'width' => 1,
1264 
    },
1265 
    'sysgen_dut.to_register3_clk' => {
1266 
      'hdlType' => 'std_logic',
1267 
      'width' => 1,
1268 
    },
1269 
    'sysgen_dut.to_register3_clr' => {
1270 
      'hdlType' => 'std_logic',
1271 
      'width' => 1,
1272 
    },
1273 
    'sysgen_dut.to_register3_data_in' => {
1274 
      'hdlType' => 'std_logic',
1275 
      'width' => 1,
1276 
    },
1277 
    'sysgen_dut.to_register3_en' => {
1278 
      'hdlType' => 'std_logic',
1279 
      'width' => 1,
1280 
    },
1281 
    'sysgen_dut.to_register4_ce' => {
1282 
      'hdlType' => 'std_logic',
1283 
      'width' => 1,
1284 
    },
1285 
    'sysgen_dut.to_register4_clk' => {
1286 
      'hdlType' => 'std_logic',
1287 
      'width' => 1,
1288 
    },
1289 
    'sysgen_dut.to_register4_clr' => {
1290 
      'hdlType' => 'std_logic',
1291 
      'width' => 1,
1292 
    },
1293 
    'sysgen_dut.to_register4_data_in' => {
1294 
      'hdlType' => 'std_logic',
1295 
      'width' => 1,
1296 
    },
1297 
    'sysgen_dut.to_register4_en' => {
1298 
      'hdlType' => 'std_logic',
1299 
      'width' => 1,
1300 
    },
1301 
    'sysgen_dut.to_register5_ce' => {
1302 
      'hdlType' => 'std_logic',
1303 
      'width' => 1,
1304 
    },
1305 
    'sysgen_dut.to_register5_clk' => {
1306 
      'hdlType' => 'std_logic',
1307 
      'width' => 1,
1308 
    },
1309 
    'sysgen_dut.to_register5_clr' => {
1310 
      'hdlType' => 'std_logic',
1311 
      'width' => 1,
1312 
    },
1313 
    'sysgen_dut.to_register5_data_in' => {
1314 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1315 
      'width' => 32,
1316 
    },
1317 
    'sysgen_dut.to_register5_en' => {
1318 
      'hdlType' => 'std_logic',
1319 
      'width' => 1,
1320 
    },
1321 
    'sysgen_dut.to_register6_ce' => {
1322 
      'hdlType' => 'std_logic',
1323 
      'width' => 1,
1324 
    },
1325 
    'sysgen_dut.to_register6_clk' => {
1326 
      'hdlType' => 'std_logic',
1327 
      'width' => 1,
1328 
    },
1329 
    'sysgen_dut.to_register6_clr' => {
1330 
      'hdlType' => 'std_logic',
1331 
      'width' => 1,
1332 
    },
1333 
    'sysgen_dut.to_register6_data_in' => {
1334 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1335 
      'width' => 32,
1336 
    },
1337 
    'sysgen_dut.to_register6_en' => {
1338 
      'hdlType' => 'std_logic',
1339 
      'width' => 1,
1340 
    },
1341 
    'sysgen_dut.to_register7_ce' => {
1342 
      'hdlType' => 'std_logic',
1343 
      'width' => 1,
1344 
    },
1345 
    'sysgen_dut.to_register7_clk' => {
1346 
      'hdlType' => 'std_logic',
1347 
      'width' => 1,
1348 
    },
1349 
    'sysgen_dut.to_register7_clr' => {
1350 
      'hdlType' => 'std_logic',
1351 
      'width' => 1,
1352 
    },
1353 
    'sysgen_dut.to_register7_data_in' => {
1354 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1355 
      'width' => 32,
1356 
    },
1357 
    'sysgen_dut.to_register7_en' => {
1358 
      'hdlType' => 'std_logic',
1359 
      'width' => 1,
1360 
    },
1361 
    'sysgen_dut.to_register8_ce' => {
1362 
      'hdlType' => 'std_logic',
1363 
      'width' => 1,
1364 
    },
1365 
    'sysgen_dut.to_register8_clk' => {
1366 
      'hdlType' => 'std_logic',
1367 
      'width' => 1,
1368 
    },
1369 
    'sysgen_dut.to_register8_clr' => {
1370 
      'hdlType' => 'std_logic',
1371 
      'width' => 1,
1372 
    },
1373 
    'sysgen_dut.to_register8_data_in' => {
1374 
      'hdlType' => 'std_logic',
1375 
      'width' => 1,
1376 
    },
1377 
    'sysgen_dut.to_register8_en' => {
1378 
      'hdlType' => 'std_logic',
1379 
      'width' => 1,
1380 
    },
1381 
    'sysgen_dut.to_register9_ce' => {
1382 
      'hdlType' => 'std_logic',
1383 
      'width' => 1,
1384 
    },
1385 
    'sysgen_dut.to_register9_clk' => {
1386 
      'hdlType' => 'std_logic',
1387 
      'width' => 1,
1388 
    },
1389 
    'sysgen_dut.to_register9_clr' => {
1390 
      'hdlType' => 'std_logic',
1391 
      'width' => 1,
1392 
    },
1393 
    'sysgen_dut.to_register9_data_in' => {
1394 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1395 
      'width' => 32,
1396 
    },
1397 
    'sysgen_dut.to_register9_en' => {
1398 
      'hdlType' => 'std_logic',
1399 
      'width' => 1,
1400 
    },
1401 
    'to_register1.dout' => {
1402 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1403 
      'width' => 32,
1404 
    },
1405 
    'to_register10.dout' => {
1406 
      'hdlType' => 'std_logic',
1407 
      'width' => 1,
1408 
    },
1409 
    'to_register11.dout' => {
1410 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1411 
      'width' => 32,
1412 
    },
1413 
    'to_register12.dout' => {
1414 
      'hdlType' => 'std_logic',
1415 
      'width' => 1,
1416 
    },
1417 
    'to_register13.dout' => {
1418 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1419 
      'width' => 32,
1420 
    },
1421 
    'to_register14.dout' => {
1422 
      'hdlType' => 'std_logic',
1423 
      'width' => 1,
1424 
    },
1425 
    'to_register15.dout' => {
1426 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1427 
      'width' => 32,
1428 
    },
1429 
    'to_register16.dout' => {
1430 
      'hdlType' => 'std_logic',
1431 
      'width' => 1,
1432 
    },
1433 
    'to_register17.dout' => {
1434 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1435 
      'width' => 32,
1436 
    },
1437 
    'to_register18.dout' => {
1438 
      'hdlType' => 'std_logic',
1439 
      'width' => 1,
1440 
    },
1441 
    'to_register19.dout' => {
1442 
      'hdlType' => 'std_logic',
1443 
      'width' => 1,
1444 
    },
1445 
    'to_register2.dout' => {
1446 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1447 
      'width' => 32,
1448 
    },
1449 
    'to_register20.dout' => {
1450 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1451 
      'width' => 32,
1452 
    },
1453 
    'to_register21.dout' => {
1454 
      'hdlType' => 'std_logic',
1455 
      'width' => 1,
1456 
    },
1457 
    'to_register22.dout' => {
1458 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1459 
      'width' => 32,
1460 
    },
1461 
    'to_register23.dout' => {
1462 
      'hdlType' => 'std_logic',
1463 
      'width' => 1,
1464 
    },
1465 
    'to_register24.dout' => {
1466 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1467 
      'width' => 32,
1468 
    },
1469 
    'to_register25.dout' => {
1470 
      'hdlType' => 'std_logic',
1471 
      'width' => 1,
1472 
    },
1473 
    'to_register26.dout' => {
1474 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1475 
      'width' => 32,
1476 
    },
1477 
    'to_register27.dout' => {
1478 
      'hdlType' => 'std_logic',
1479 
      'width' => 1,
1480 
    },
1481 
    'to_register28.dout' => {
1482 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1483 
      'width' => 32,
1484 
    },
1485 
    'to_register29.dout' => {
1486 
      'hdlType' => 'std_logic',
1487 
      'width' => 1,
1488 
    },
1489 
    'to_register3.dout' => {
1490 
      'hdlType' => 'std_logic',
1491 
      'width' => 1,
1492 
    },
1493 
    'to_register30.dout' => {
1494 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1495 
      'width' => 32,
1496 
    },
1497 
    'to_register31.dout' => {
1498 
      'hdlType' => 'std_logic',
1499 
      'width' => 1,
1500 
    },
1501 
    'to_register32.dout' => {
1502 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1503 
      'width' => 32,
1504 
    },
1505 
    'to_register33.dout' => {
1506 
      'hdlType' => 'std_logic',
1507 
      'width' => 1,
1508 
    },
1509 
    'to_register34.dout' => {
1510 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1511 
      'width' => 32,
1512 
    },
1513 
    'to_register4.dout' => {
1514 
      'hdlType' => 'std_logic',
1515 
      'width' => 1,
1516 
    },
1517 
    'to_register5.dout' => {
1518 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1519 
      'width' => 32,
1520 
    },
1521 
    'to_register6.dout' => {
1522 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1523 
      'width' => 32,
1524 
    },
1525 
    'to_register7.dout' => {
1526 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1527 
      'width' => 32,
1528 
    },
1529 
    'to_register8.dout' => {
1530 
      'hdlType' => 'std_logic',
1531 
      'width' => 1,
1532 
    },
1533 
    'to_register9.dout' => {
1534 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1535 
      'width' => 32,
1536 
    },
1537 
  },
1538 
  'subblocks' => {
1539 
    'debug_in_1i' => {
1540 
      'connections' => { 'debug_in_1i' => '.debug_in_1i', },
1541 
      'entity' => {
1542 
        'attributes' => {
1543 
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          'isGateway' => 1,
4921 
          'is_floating_block' => 1,
4922 
        },
4923 
        'entityName' => 'reg14_td',
4924 
        'ports' => {
4925 
          'reg14_td' => {
4926 
            'attributes' => {
4927 
              'bin_pt' => 0,
4928 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
4929 
              'is_floating_block' => 1,
4930 
              'is_gateway_port' => 1,
4931 
              'must_be_hdl_vector' => 1,
4932 
              'period' => 1,
4933 
              'port_id' => 0,
4934 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
4935 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
4936 
              'timingConstraint' => 'none',
4937 
              'type' => 'UFix_32_0',
4938 
            },
4939 
            'direction' => 'out',
4940 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4941 
            'width' => 32,
4942 
          },
4943 
        },
4944 
      },
4945 
      'entityName' => 'reg14_td',
4946 
    },
4947 
    'reg14_tv' => {
4948 
      'connections' => { 'reg14_tv' => '.reg14_tv', },
4949 
      'entity' => {
4950 
        'attributes' => {
4951 
          'entityAlreadyNetlisted' => 1,
4952 
          'isGateway' => 1,
4953 
          'is_floating_block' => 1,
4954 
        },
4955 
        'entityName' => 'reg14_tv',
4956 
        'ports' => {
4957 
          'reg14_tv' => {
4958 
            'attributes' => {
4959 
              'bin_pt' => 0,
4960 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
4961 
              'is_floating_block' => 1,
4962 
              'is_gateway_port' => 1,
4963 
              'must_be_hdl_vector' => 1,
4964 
              'period' => 1,
4965 
              'port_id' => 0,
4966 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
4967 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
4968 
              'timingConstraint' => 'none',
4969 
              'type' => 'Bool',
4970 
            },
4971 
            'direction' => 'out',
4972 
            'hdlType' => 'std_logic',
4973 
            'width' => 1,
4974 
          },
4975 
        },
4976 
      },
4977 
      'entityName' => 'reg14_tv',
4978 
    },
4979 
    'sysgen_dut' => {
4980 
      'connections' => {
4981 
        'clk' => '.clk',
4982 
        'debug_in_1i' => '.debug_in_1i',
4983 
        'debug_in_2i' => '.debug_in_2i',
4984 
        'debug_in_3i' => '.debug_in_3i',
4985 
        'debug_in_4i' => '.debug_in_4i',
4986 
        'dma_host2board_busy' => '.dma_host2board_busy',
4987 
        'dma_host2board_done' => '.dma_host2board_done',
4988 
        'from_register10_data_out' => 'from_register10.data_out',
4989 
        'from_register11_data_out' => 'from_register11.data_out',
4990 
        'from_register12_data_out' => 'from_register12.data_out',
4991 
        'from_register13_data_out' => 'from_register13.data_out',
4992 
        'from_register14_data_out' => 'from_register14.data_out',
4993 
        'from_register15_data_out' => 'from_register15.data_out',
4994 
        'from_register16_data_out' => 'from_register16.data_out',
4995 
        'from_register17_data_out' => 'from_register17.data_out',
4996 
        'from_register18_data_out' => 'from_register18.data_out',
4997 
        'from_register19_data_out' => 'from_register19.data_out',
4998 
        'from_register1_data_out' => 'from_register1.data_out',
4999 
        'from_register20_data_out' => 'from_register20.data_out',
5000 
        'from_register21_data_out' => 'from_register21.data_out',
5001 
        'from_register22_data_out' => 'from_register22.data_out',
5002 
        'from_register23_data_out' => 'from_register23.data_out',
5003 
        'from_register24_data_out' => 'from_register24.data_out',
5004 
        'from_register25_data_out' => 'from_register25.data_out',
5005 
        'from_register26_data_out' => 'from_register26.data_out',
5006 
        'from_register27_data_out' => 'from_register27.data_out',
5007 
        'from_register28_data_out' => 'from_register28.data_out',
5008 
        'from_register2_data_out' => 'from_register2.data_out',
5009 
        'from_register3_data_out' => 'from_register3.data_out',
5010 
        'from_register4_data_out' => 'from_register4.data_out',
5011 
        'from_register5_data_out' => 'from_register5.data_out',
5012 
        'from_register6_data_out' => 'from_register6.data_out',
5013 
        'from_register7_data_out' => 'from_register7.data_out',
5014 
        'from_register8_data_out' => 'from_register8.data_out',
5015 
        'from_register9_data_out' => 'from_register9.data_out',
5016 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5017 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5018 
        'reg01_td' => '.reg01_td',
5019 
        'reg01_tv' => '.reg01_tv',
5020 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5021 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5022 
        'reg02_td' => '.reg02_td',
5023 
        'reg02_tv' => '.reg02_tv',
5024 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5025 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5026 
        'reg03_td' => '.reg03_td',
5027 
        'reg03_tv' => '.reg03_tv',
5028 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5029 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5030 
        'reg04_td' => '.reg04_td',
5031 
        'reg04_tv' => '.reg04_tv',
5032 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5033 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5034 
        'reg05_td' => '.reg05_td',
5035 
        'reg05_tv' => '.reg05_tv',
5036 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5037 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5038 
        'reg06_td' => '.reg06_td',
5039 
        'reg06_tv' => '.reg06_tv',
5040 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5041 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5042 
        'reg07_td' => '.reg07_td',
5043 
        'reg07_tv' => '.reg07_tv',
5044 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5045 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5046 
        'reg08_td' => '.reg08_td',
5047 
        'reg08_tv' => '.reg08_tv',
5048 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5049 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5050 
        'reg09_td' => '.reg09_td',
5051 
        'reg09_tv' => '.reg09_tv',
5052 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5053 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5054 
        'reg10_td' => '.reg10_td',
5055 
        'reg10_tv' => '.reg10_tv',
5056 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5057 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5058 
        'reg11_td' => '.reg11_td',
5059 
        'reg11_tv' => '.reg11_tv',
5060 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5061 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5062 
        'reg12_td' => '.reg12_td',
5063 
        'reg12_tv' => '.reg12_tv',
5064 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5065 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5066 
        'reg13_td' => '.reg13_td',
5067 
        'reg13_tv' => '.reg13_tv',
5068 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5069 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5070 
        'reg14_td' => '.reg14_td',
5071 
        'reg14_tv' => '.reg14_tv',
5072 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5073 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5074 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5075 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5076 
        'to_register10_dout' => 'to_register10.dout',
5077 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5078 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5079 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5080 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5081 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5082 
        'to_register11_dout' => 'to_register11.dout',
5083 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5084 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5085 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5086 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5087 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5088 
        'to_register12_dout' => 'to_register12.dout',
5089 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5090 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5091 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5092 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5093 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5094 
        'to_register13_dout' => 'to_register13.dout',
5095 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5096 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5097 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5098 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5099 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5100 
        'to_register14_dout' => 'to_register14.dout',
5101 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5102 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5103 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5104 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5105 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5106 
        'to_register15_dout' => 'to_register15.dout',
5107 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5108 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5109 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5110 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5111 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5112 
        'to_register16_dout' => 'to_register16.dout',
5113 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5114 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5115 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5116 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5117 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5118 
        'to_register17_dout' => 'to_register17.dout',
5119 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5120 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5121 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5122 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5123 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5124 
        'to_register18_dout' => 'to_register18.dout',
5125 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5126 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5127 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5128 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5129 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5130 
        'to_register19_dout' => 'to_register19.dout',
5131 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5132 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5133 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5134 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5135 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5136 
        'to_register1_dout' => 'to_register1.dout',
5137 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5138 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5139 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5140 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5141 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5142 
        'to_register20_dout' => 'to_register20.dout',
5143 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5144 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5145 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5146 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5147 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5148 
        'to_register21_dout' => 'to_register21.dout',
5149 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5150 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5151 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5152 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5153 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5154 
        'to_register22_dout' => 'to_register22.dout',
5155 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5156 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5157 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5158 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5159 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5160 
        'to_register23_dout' => 'to_register23.dout',
5161 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5162 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5163 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5164 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5165 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5166 
        'to_register24_dout' => 'to_register24.dout',
5167 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5168 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5169 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5170 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5171 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5172 
        'to_register25_dout' => 'to_register25.dout',
5173 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5174 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5175 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5176 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5177 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5178 
        'to_register26_dout' => 'to_register26.dout',
5179 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5180 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5181 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5182 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5183 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5184 
        'to_register27_dout' => 'to_register27.dout',
5185 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5186 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5187 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5188 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5189 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5190 
        'to_register28_dout' => 'to_register28.dout',
5191 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5192 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5193 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5194 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5195 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5196 
        'to_register29_dout' => 'to_register29.dout',
5197 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5198 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5199 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5200 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5201 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5202 
        'to_register2_dout' => 'to_register2.dout',
5203 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5204 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5205 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5206 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5207 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5208 
        'to_register30_dout' => 'to_register30.dout',
5209 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5210 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5211 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5212 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5213 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5214 
        'to_register31_dout' => 'to_register31.dout',
5215 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5216 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5217 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5218 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5219 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5220 
        'to_register32_dout' => 'to_register32.dout',
5221 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5222 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5223 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5224 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5225 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5226 
        'to_register33_dout' => 'to_register33.dout',
5227 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5228 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5229 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5230 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5231 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5232 
        'to_register34_dout' => 'to_register34.dout',
5233 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5234 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5235 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5236 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5237 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5238 
        'to_register3_dout' => 'to_register3.dout',
5239 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5240 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5241 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5242 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5243 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5244 
        'to_register4_dout' => 'to_register4.dout',
5245 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5246 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5247 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5248 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5249 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5250 
        'to_register5_dout' => 'to_register5.dout',
5251 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5252 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5253 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5254 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5255 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5256 
        'to_register6_dout' => 'to_register6.dout',
5257 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5258 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5259 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5260 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5261 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5262 
        'to_register7_dout' => 'to_register7.dout',
5263 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5264 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5265 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5266 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5267 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5268 
        'to_register8_dout' => 'to_register8.dout',
5269 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5270 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5271 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5272 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5273 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5274 
        'to_register9_dout' => 'to_register9.dout',
5275 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5276 
      },
5277 
      'entity' => {
5278 
        'attributes' => {
5279 
          'entityAlreadyNetlisted' => 1,
5280 
          'hdlArchAttributes' => [],
5281 
          'hdlEntityAttributes' => [],
5282 
          'isClkWrapper' => 1,
5283 
        },
5284 
        'connections' => {
5285 
          'clk' => 'clkNet',
5286 
          'debug_in_1i' => 'debug_in_1i_net',
5287 
          'debug_in_2i' => 'debug_in_2i_net',
5288 
          'debug_in_3i' => 'debug_in_3i_net',
5289 
          'debug_in_4i' => 'debug_in_4i_net',
5290 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5291 
          'dma_host2board_done' => 'dma_host2board_done_net',
5292 
          'from_register10_data_out' => 'from_register10_data_out_net',
5293 
          'from_register11_data_out' => 'from_register11_data_out_net',
5294 
          'from_register12_data_out' => 'from_register12_data_out_net',
5295 
          'from_register13_data_out' => 'from_register13_data_out_net',
5296 
          'from_register14_data_out' => 'from_register14_data_out_net',
5297 
          'from_register15_data_out' => 'from_register15_data_out_net',
5298 
          'from_register16_data_out' => 'from_register16_data_out_net',
5299 
          'from_register17_data_out' => 'from_register17_data_out_net',
5300 
          'from_register18_data_out' => 'from_register18_data_out_net',
5301 
          'from_register19_data_out' => 'from_register19_data_out_net',
5302 
          'from_register1_data_out' => 'from_register1_data_out_net',
5303 
          'from_register20_data_out' => 'from_register20_data_out_net',
5304 
          'from_register21_data_out' => 'from_register21_data_out_net',
5305 
          'from_register22_data_out' => 'from_register22_data_out_net',
5306 
          'from_register23_data_out' => 'from_register23_data_out_net',
5307 
          'from_register24_data_out' => 'from_register24_data_out_net',
5308 
          'from_register25_data_out' => 'from_register25_data_out_net',
5309 
          'from_register26_data_out' => 'from_register26_data_out_net',
5310 
          'from_register27_data_out' => 'from_register27_data_out_net',
5311 
          'from_register28_data_out' => 'from_register28_data_out_net',
5312 
          'from_register2_data_out' => 'from_register2_data_out_net',
5313 
          'from_register3_data_out' => 'from_register3_data_out_net',
5314 
          'from_register4_data_out' => 'from_register4_data_out_net',
5315 
          'from_register5_data_out' => 'from_register5_data_out_net',
5316 
          'from_register6_data_out' => 'from_register6_data_out_net',
5317 
          'from_register7_data_out' => 'from_register7_data_out_net',
5318 
          'from_register8_data_out' => 'from_register8_data_out_net',
5319 
          'from_register9_data_out' => 'from_register9_data_out_net',
5320 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5321 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5322 
          'reg01_td' => 'reg01_td_net',
5323 
          'reg01_tv' => 'reg01_tv_net',
5324 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5325 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5326 
          'reg02_td' => 'reg02_td_net',
5327 
          'reg02_tv' => 'reg02_tv_net',
5328 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5329 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5330 
          'reg03_td' => 'reg03_td_net',
5331 
          'reg03_tv' => 'reg03_tv_net',
5332 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5333 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5334 
          'reg04_td' => 'reg04_td_net',
5335 
          'reg04_tv' => 'reg04_tv_net',
5336 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5337 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5338 
          'reg05_td' => 'reg05_td_net',
5339 
          'reg05_tv' => 'reg05_tv_net',
5340 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5341 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5342 
          'reg06_td' => 'reg06_td_net',
5343 
          'reg06_tv' => 'reg06_tv_net',
5344 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5345 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5346 
          'reg07_td' => 'reg07_td_net',
5347 
          'reg07_tv' => 'reg07_tv_net',
5348 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5349 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5350 
          'reg08_td' => 'reg08_td_net',
5351 
          'reg08_tv' => 'reg08_tv_net',
5352 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5353 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5354 
          'reg09_td' => 'reg09_td_net',
5355 
          'reg09_tv' => 'reg09_tv_net',
5356 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5357 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5358 
          'reg10_td' => 'reg10_td_net',
5359 
          'reg10_tv' => 'reg10_tv_net',
5360 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5361 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5362 
          'reg11_td' => 'reg11_td_net',
5363 
          'reg11_tv' => 'reg11_tv_net',
5364 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5365 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5366 
          'reg12_td' => 'reg12_td_net',
5367 
          'reg12_tv' => 'reg12_tv_net',
5368 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5369 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5370 
          'reg13_td' => 'reg13_td_net',
5371 
          'reg13_tv' => 'reg13_tv_net',
5372 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5373 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5374 
          'reg14_td' => 'reg14_td_net',
5375 
          'reg14_tv' => 'reg14_tv_net',
5376 
          'to_register10_ce' => 'ce_1_sg',
5377 
          'to_register10_clk' => 'clk_1_sg',
5378 
          'to_register10_clr' => [
5379 
            'constant',
5380 
            '\'0\'',
5381 
          ],
5382 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5383 
          'to_register10_dout' => 'to_register10_dout_net',
5384 
          'to_register10_en' => 'constant5_op_net_x1',
5385 
          'to_register11_ce' => 'ce_1_sg',
5386 
          'to_register11_clk' => 'clk_1_sg',
5387 
          'to_register11_clr' => [
5388 
            'constant',
5389 
            '\'0\'',
5390 
          ],
5391 
          'to_register11_data_in' => 'reg04_td_net_x0',
5392 
          'to_register11_dout' => 'to_register11_dout_net',
5393 
          'to_register11_en' => 'constant5_op_net_x2',
5394 
          'to_register12_ce' => 'ce_1_sg',
5395 
          'to_register12_clk' => 'clk_1_sg',
5396 
          'to_register12_clr' => [
5397 
            'constant',
5398 
            '\'0\'',
5399 
          ],
5400 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5401 
          'to_register12_dout' => 'to_register12_dout_net',
5402 
          'to_register12_en' => 'constant5_op_net_x3',
5403 
          'to_register13_ce' => 'ce_1_sg',
5404 
          'to_register13_clk' => 'clk_1_sg',
5405 
          'to_register13_clr' => [
5406 
            'constant',
5407 
            '\'0\'',
5408 
          ],
5409 
          'to_register13_data_in' => 'reg05_td_net_x0',
5410 
          'to_register13_dout' => 'to_register13_dout_net',
5411 
          'to_register13_en' => 'constant5_op_net_x4',
5412 
          'to_register14_ce' => 'ce_1_sg',
5413 
          'to_register14_clk' => 'clk_1_sg',
5414 
          'to_register14_clr' => [
5415 
            'constant',
5416 
            '\'0\'',
5417 
          ],
5418 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5419 
          'to_register14_dout' => 'to_register14_dout_net',
5420 
          'to_register14_en' => 'constant5_op_net_x5',
5421 
          'to_register15_ce' => 'ce_1_sg',
5422 
          'to_register15_clk' => 'clk_1_sg',
5423 
          'to_register15_clr' => [
5424 
            'constant',
5425 
            '\'0\'',
5426 
          ],
5427 
          'to_register15_data_in' => 'reg06_td_net_x0',
5428 
          'to_register15_dout' => 'to_register15_dout_net',
5429 
          'to_register15_en' => 'constant5_op_net_x6',
5430 
          'to_register16_ce' => 'ce_1_sg',
5431 
          'to_register16_clk' => 'clk_1_sg',
5432 
          'to_register16_clr' => [
5433 
            'constant',
5434 
            '\'0\'',
5435 
          ],
5436 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5437 
          'to_register16_dout' => 'to_register16_dout_net',
5438 
          'to_register16_en' => 'constant5_op_net_x7',
5439 
          'to_register17_ce' => 'ce_1_sg',
5440 
          'to_register17_clk' => 'clk_1_sg',
5441 
          'to_register17_clr' => [
5442 
            'constant',
5443 
            '\'0\'',
5444 
          ],
5445 
          'to_register17_data_in' => 'reg07_td_net_x0',
5446 
          'to_register17_dout' => 'to_register17_dout_net',
5447 
          'to_register17_en' => 'constant5_op_net_x8',
5448 
          'to_register18_ce' => 'ce_1_sg',
5449 
          'to_register18_clk' => 'clk_1_sg',
5450 
          'to_register18_clr' => [
5451 
            'constant',
5452 
            '\'0\'',
5453 
          ],
5454 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5455 
          'to_register18_dout' => 'to_register18_dout_net',
5456 
          'to_register18_en' => 'constant5_op_net_x9',
5457 
          'to_register19_ce' => 'ce_1_sg',
5458 
          'to_register19_clk' => 'clk_1_sg',
5459 
          'to_register19_clr' => [
5460 
            'constant',
5461 
            '\'0\'',
5462 
          ],
5463 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5464 
          'to_register19_dout' => 'to_register19_dout_net',
5465 
          'to_register19_en' => 'constant5_op_net_x10',
5466 
          'to_register1_ce' => 'ce_1_sg',
5467 
          'to_register1_clk' => 'clk_1_sg',
5468 
          'to_register1_clr' => [
5469 
            'constant',
5470 
            '\'0\'',
5471 
          ],
5472 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5473 
          'to_register1_dout' => 'to_register1_dout_net',
5474 
          'to_register1_en' => 'constant5_op_net_x0',
5475 
          'to_register20_ce' => 'ce_1_sg',
5476 
          'to_register20_clk' => 'clk_1_sg',
5477 
          'to_register20_clr' => [
5478 
            'constant',
5479 
            '\'0\'',
5480 
          ],
5481 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5482 
          'to_register20_dout' => 'to_register20_dout_net',
5483 
          'to_register20_en' => 'constant5_op_net_x12',
5484 
          'to_register21_ce' => 'ce_1_sg',
5485 
          'to_register21_clk' => 'clk_1_sg',
5486 
          'to_register21_clr' => [
5487 
            'constant',
5488 
            '\'0\'',
5489 
          ],
5490 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5491 
          'to_register21_dout' => 'to_register21_dout_net',
5492 
          'to_register21_en' => 'constant1_op_net_x0',
5493 
          'to_register22_ce' => 'ce_1_sg',
5494 
          'to_register22_clk' => 'clk_1_sg',
5495 
          'to_register22_clr' => [
5496 
            'constant',
5497 
            '\'0\'',
5498 
          ],
5499 
          'to_register22_data_in' => 'reg09_td_net_x0',
5500 
          'to_register22_dout' => 'to_register22_dout_net',
5501 
          'to_register22_en' => 'constant1_op_net_x1',
5502 
          'to_register23_ce' => 'ce_1_sg',
5503 
          'to_register23_clk' => 'clk_1_sg',
5504 
          'to_register23_clr' => [
5505 
            'constant',
5506 
            '\'0\'',
5507 
          ],
5508 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5509 
          'to_register23_dout' => 'to_register23_dout_net',
5510 
          'to_register23_en' => 'constant1_op_net_x2',
5511 
          'to_register24_ce' => 'ce_1_sg',
5512 
          'to_register24_clk' => 'clk_1_sg',
5513 
          'to_register24_clr' => [
5514 
            'constant',
5515 
            '\'0\'',
5516 
          ],
5517 
          'to_register24_data_in' => 'reg10_td_net_x0',
5518 
          'to_register24_dout' => 'to_register24_dout_net',
5519 
          'to_register24_en' => 'constant1_op_net_x3',
5520 
          'to_register25_ce' => 'ce_1_sg',
5521 
          'to_register25_clk' => 'clk_1_sg',
5522 
          'to_register25_clr' => [
5523 
            'constant',
5524 
            '\'0\'',
5525 
          ],
5526 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5527 
          'to_register25_dout' => 'to_register25_dout_net',
5528 
          'to_register25_en' => 'constant1_op_net_x4',
5529 
          'to_register26_ce' => 'ce_1_sg',
5530 
          'to_register26_clk' => 'clk_1_sg',
5531 
          'to_register26_clr' => [
5532 
            'constant',
5533 
            '\'0\'',
5534 
          ],
5535 
          'to_register26_data_in' => 'reg08_td_net_x0',
5536 
          'to_register26_dout' => 'to_register26_dout_net',
5537 
          'to_register26_en' => 'constant1_op_net_x5',
5538 
          'to_register27_ce' => 'ce_1_sg',
5539 
          'to_register27_clk' => 'clk_1_sg',
5540 
          'to_register27_clr' => [
5541 
            'constant',
5542 
            '\'0\'',
5543 
          ],
5544 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5545 
          'to_register27_dout' => 'to_register27_dout_net',
5546 
          'to_register27_en' => 'constant1_op_net_x6',
5547 
          'to_register28_ce' => 'ce_1_sg',
5548 
          'to_register28_clk' => 'clk_1_sg',
5549 
          'to_register28_clr' => [
5550 
            'constant',
5551 
            '\'0\'',
5552 
          ],
5553 
          'to_register28_data_in' => 'reg11_td_net_x0',
5554 
          'to_register28_dout' => 'to_register28_dout_net',
5555 
          'to_register28_en' => 'constant1_op_net_x7',
5556 
          'to_register29_ce' => 'ce_1_sg',
5557 
          'to_register29_clk' => 'clk_1_sg',
5558 
          'to_register29_clr' => [
5559 
            'constant',
5560 
            '\'0\'',
5561 
          ],
5562 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5563 
          'to_register29_dout' => 'to_register29_dout_net',
5564 
          'to_register29_en' => 'constant1_op_net_x8',
5565 
          'to_register2_ce' => 'ce_1_sg',
5566 
          'to_register2_clk' => 'clk_1_sg',
5567 
          'to_register2_clr' => [
5568 
            'constant',
5569 
            '\'0\'',
5570 
          ],
5571 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5572 
          'to_register2_dout' => 'to_register2_dout_net',
5573 
          'to_register2_en' => 'constant5_op_net_x11',
5574 
          'to_register30_ce' => 'ce_1_sg',
5575 
          'to_register30_clk' => 'clk_1_sg',
5576 
          'to_register30_clr' => [
5577 
            'constant',
5578 
            '\'0\'',
5579 
          ],
5580 
          'to_register30_data_in' => 'reg12_td_net_x0',
5581 
          'to_register30_dout' => 'to_register30_dout_net',
5582 
          'to_register30_en' => 'constant1_op_net_x9',
5583 
          'to_register31_ce' => 'ce_1_sg',
5584 
          'to_register31_clk' => 'clk_1_sg',
5585 
          'to_register31_clr' => [
5586 
            'constant',
5587 
            '\'0\'',
5588 
          ],
5589 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5590 
          'to_register31_dout' => 'to_register31_dout_net',
5591 
          'to_register31_en' => 'constant1_op_net_x10',
5592 
          'to_register32_ce' => 'ce_1_sg',
5593 
          'to_register32_clk' => 'clk_1_sg',
5594 
          'to_register32_clr' => [
5595 
            'constant',
5596 
            '\'0\'',
5597 
          ],
5598 
          'to_register32_data_in' => 'reg13_td_net_x0',
5599 
          'to_register32_dout' => 'to_register32_dout_net',
5600 
          'to_register32_en' => 'constant1_op_net_x11',
5601 
          'to_register33_ce' => 'ce_1_sg',
5602 
          'to_register33_clk' => 'clk_1_sg',
5603 
          'to_register33_clr' => [
5604 
            'constant',
5605 
            '\'0\'',
5606 
          ],
5607 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5608 
          'to_register33_dout' => 'to_register33_dout_net',
5609 
          'to_register33_en' => 'constant1_op_net_x12',
5610 
          'to_register34_ce' => 'ce_1_sg',
5611 
          'to_register34_clk' => 'clk_1_sg',
5612 
          'to_register34_clr' => [
5613 
            'constant',
5614 
            '\'0\'',
5615 
          ],
5616 
          'to_register34_data_in' => 'reg14_td_net_x0',
5617 
          'to_register34_dout' => 'to_register34_dout_net',
5618 
          'to_register34_en' => 'constant1_op_net_x13',
5619 
          'to_register3_ce' => 'ce_1_sg',
5620 
          'to_register3_clk' => 'clk_1_sg',
5621 
          'to_register3_clr' => [
5622 
            'constant',
5623 
            '\'0\'',
5624 
          ],
5625 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5626 
          'to_register3_dout' => 'to_register3_dout_net',
5627 
          'to_register3_en' => 'constant5_op_net_x13',
5628 
          'to_register4_ce' => 'ce_1_sg',
5629 
          'to_register4_clk' => 'clk_1_sg',
5630 
          'to_register4_clr' => [
5631 
            'constant',
5632 
            '\'0\'',
5633 
          ],
5634 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5635 
          'to_register4_dout' => 'to_register4_dout_net',
5636 
          'to_register4_en' => 'constant5_op_net_x14',
5637 
          'to_register5_ce' => 'ce_1_sg',
5638 
          'to_register5_clk' => 'clk_1_sg',
5639 
          'to_register5_clr' => [
5640 
            'constant',
5641 
            '\'0\'',
5642 
          ],
5643 
          'to_register5_data_in' => 'reg02_td_net_x0',
5644 
          'to_register5_dout' => 'to_register5_dout_net',
5645 
          'to_register5_en' => 'constant5_op_net_x15',
5646 
          'to_register6_ce' => 'ce_1_sg',
5647 
          'to_register6_clk' => 'clk_1_sg',
5648 
          'to_register6_clr' => [
5649 
            'constant',
5650 
            '\'0\'',
5651 
          ],
5652 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5653 
          'to_register6_dout' => 'to_register6_dout_net',
5654 
          'to_register6_en' => 'constant5_op_net_x16',
5655 
          'to_register7_ce' => 'ce_1_sg',
5656 
          'to_register7_clk' => 'clk_1_sg',
5657 
          'to_register7_clr' => [
5658 
            'constant',
5659 
            '\'0\'',
5660 
          ],
5661 
          'to_register7_data_in' => 'reg01_td_net_x0',
5662 
          'to_register7_dout' => 'to_register7_dout_net',
5663 
          'to_register7_en' => 'constant5_op_net_x17',
5664 
          'to_register8_ce' => 'ce_1_sg',
5665 
          'to_register8_clk' => 'clk_1_sg',
5666 
          'to_register8_clr' => [
5667 
            'constant',
5668 
            '\'0\'',
5669 
          ],
5670 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5671 
          'to_register8_dout' => 'to_register8_dout_net',
5672 
          'to_register8_en' => 'constant5_op_net_x18',
5673 
          'to_register9_ce' => 'ce_1_sg',
5674 
          'to_register9_clk' => 'clk_1_sg',
5675 
          'to_register9_clr' => [
5676 
            'constant',
5677 
            '\'0\'',
5678 
          ],
5679 
          'to_register9_data_in' => 'reg03_td_net_x0',
5680 
          'to_register9_dout' => 'to_register9_dout_net',
5681 
          'to_register9_en' => 'constant5_op_net_x19',
5682 
        },
5683 
        'entityName' => 'inout_logic_cw',
5684 
        'nets' => {
5685 
          'ce_1_sg' => {
5686 
            'attributes' => {
5687 
              'hdlNetAttributes' => [
5688 
                [
5689 
                  'MAX_FANOUT',
5690 
                  'string',
5691 
                  '"REDUCE"',
5692 
                ],
5693 
              ],
5694 
            },
5695 
            'hdlType' => 'std_logic',
5696 
            'width' => 1,
5697 
          },
5698 
          'clkNet' => {
5699 
            'attributes' => {
5700 
              'hdlNetAttributes' => [],
5701 
            },
5702 
            'hdlType' => 'std_logic',
5703 
            'width' => 1,
5704 
          },
5705 
          'clk_1_sg' => {
5706 
            'attributes' => {
5707 
              'hdlNetAttributes' => [],
5708 
            },
5709 
            'hdlType' => 'std_logic',
5710 
            'width' => 1,
5711 
          },
5712 
          'constant1_op_net_x0' => {
5713 
            'attributes' => {
5714 
              'hdlNetAttributes' => [],
5715 
            },
5716 
            'hdlType' => 'std_logic',
5717 
            'width' => 1,
5718 
          },
5719 
          'constant1_op_net_x1' => {
5720 
            'attributes' => {
5721 
              'hdlNetAttributes' => [],
5722 
            },
5723 
            'hdlType' => 'std_logic',
5724 
            'width' => 1,
5725 
          },
5726 
          'constant1_op_net_x10' => {
5727 
            'attributes' => {
5728 
              'hdlNetAttributes' => [],
5729 
            },
5730 
            'hdlType' => 'std_logic',
5731 
            'width' => 1,
5732 
          },
5733 
          'constant1_op_net_x11' => {
5734 
            'attributes' => {
5735 
              'hdlNetAttributes' => [],
5736 
            },
5737 
            'hdlType' => 'std_logic',
5738 
            'width' => 1,
5739 
          },
5740 
          'constant1_op_net_x12' => {
5741 
            'attributes' => {
5742 
              'hdlNetAttributes' => [],
5743 
            },
5744 
            'hdlType' => 'std_logic',
5745 
            'width' => 1,
5746 
          },
5747 
          'constant1_op_net_x13' => {
5748 
            'attributes' => {
5749 
              'hdlNetAttributes' => [],
5750 
            },
5751 
            'hdlType' => 'std_logic',
5752 
            'width' => 1,
5753 
          },
5754 
          'constant1_op_net_x2' => {
5755 
            'attributes' => {
5756 
              'hdlNetAttributes' => [],
5757 
            },
5758 
            'hdlType' => 'std_logic',
5759 
            'width' => 1,
5760 
          },
5761 
          'constant1_op_net_x3' => {
5762 
            'attributes' => {
5763 
              'hdlNetAttributes' => [],
5764 
            },
5765 
            'hdlType' => 'std_logic',
5766 
            'width' => 1,
5767 
          },
5768 
          'constant1_op_net_x4' => {
5769 
            'attributes' => {
5770 
              'hdlNetAttributes' => [],
5771 
            },
5772 
            'hdlType' => 'std_logic',
5773 
            'width' => 1,
5774 
          },
5775 
          'constant1_op_net_x5' => {
5776 
            'attributes' => {
5777 
              'hdlNetAttributes' => [],
5778 
            },
5779 
            'hdlType' => 'std_logic',
5780 
            'width' => 1,
5781 
          },
5782 
          'constant1_op_net_x6' => {
5783 
            'attributes' => {
5784 
              'hdlNetAttributes' => [],
5785 
            },
5786 
            'hdlType' => 'std_logic',
5787 
            'width' => 1,
5788 
          },
5789 
          'constant1_op_net_x7' => {
5790 
            'attributes' => {
5791 
              'hdlNetAttributes' => [],
5792 
            },
5793 
            'hdlType' => 'std_logic',
5794 
            'width' => 1,
5795 
          },
5796 
          'constant1_op_net_x8' => {
5797 
            'attributes' => {
5798 
              'hdlNetAttributes' => [],
5799 
            },
5800 
            'hdlType' => 'std_logic',
5801 
            'width' => 1,
5802 
          },
5803 
          'constant1_op_net_x9' => {
5804 
            'attributes' => {
5805 
              'hdlNetAttributes' => [],
5806 
            },
5807 
            'hdlType' => 'std_logic',
5808 
            'width' => 1,
5809 
          },
5810 
          'constant5_op_net_x0' => {
5811 
            'attributes' => {
5812 
              'hdlNetAttributes' => [],
5813 
            },
5814 
            'hdlType' => 'std_logic',
5815 
            'width' => 1,
5816 
          },
5817 
          'constant5_op_net_x1' => {
5818 
            'attributes' => {
5819 
              'hdlNetAttributes' => [],
5820 
            },
5821 
            'hdlType' => 'std_logic',
5822 
            'width' => 1,
5823 
          },
5824 
          'constant5_op_net_x10' => {
5825 
            'attributes' => {
5826 
              'hdlNetAttributes' => [],
5827 
            },
5828 
            'hdlType' => 'std_logic',
5829 
            'width' => 1,
5830 
          },
5831 
          'constant5_op_net_x11' => {
5832 
            'attributes' => {
5833 
              'hdlNetAttributes' => [],
5834 
            },
5835 
            'hdlType' => 'std_logic',
5836 
            'width' => 1,
5837 
          },
5838 
          'constant5_op_net_x12' => {
5839 
            'attributes' => {
5840 
              'hdlNetAttributes' => [],
5841 
            },
5842 
            'hdlType' => 'std_logic',
5843 
            'width' => 1,
5844 
          },
5845 
          'constant5_op_net_x13' => {
5846 
            'attributes' => {
5847 
              'hdlNetAttributes' => [],
5848 
            },
5849 
            'hdlType' => 'std_logic',
5850 
            'width' => 1,
5851 
          },
5852 
          'constant5_op_net_x14' => {
5853 
            'attributes' => {
5854 
              'hdlNetAttributes' => [],
5855 
            },
5856 
            'hdlType' => 'std_logic',
5857 
            'width' => 1,
5858 
          },
5859 
          'constant5_op_net_x15' => {
5860 
            'attributes' => {
5861 
              'hdlNetAttributes' => [],
5862 
            },
5863 
            'hdlType' => 'std_logic',
5864 
            'width' => 1,
5865 
          },
5866 
          'constant5_op_net_x16' => {
5867 
            'attributes' => {
5868 
              'hdlNetAttributes' => [],
5869 
            },
5870 
            'hdlType' => 'std_logic',
5871 
            'width' => 1,
5872 
          },
5873 
          'constant5_op_net_x17' => {
5874 
            'attributes' => {
5875 
              'hdlNetAttributes' => [],
5876 
            },
5877 
            'hdlType' => 'std_logic',
5878 
            'width' => 1,
5879 
          },
5880 
          'constant5_op_net_x18' => {
5881 
            'attributes' => {
5882 
              'hdlNetAttributes' => [],
5883 
            },
5884 
            'hdlType' => 'std_logic',
5885 
            'width' => 1,
5886 
          },
5887 
          'constant5_op_net_x19' => {
5888 
            'attributes' => {
5889 
              'hdlNetAttributes' => [],
5890 
            },
5891 
            'hdlType' => 'std_logic',
5892 
            'width' => 1,
5893 
          },
5894 
          'constant5_op_net_x2' => {
5895 
            'attributes' => {
5896 
              'hdlNetAttributes' => [],
5897 
            },
5898 
            'hdlType' => 'std_logic',
5899 
            'width' => 1,
5900 
          },
5901 
          'constant5_op_net_x3' => {
5902 
            'attributes' => {
5903 
              'hdlNetAttributes' => [],
5904 
            },
5905 
            'hdlType' => 'std_logic',
5906 
            'width' => 1,
5907 
          },
5908 
          'constant5_op_net_x4' => {
5909 
            'attributes' => {
5910 
              'hdlNetAttributes' => [],
5911 
            },
5912 
            'hdlType' => 'std_logic',
5913 
            'width' => 1,
5914 
          },
5915 
          'constant5_op_net_x5' => {
5916 
            'attributes' => {
5917 
              'hdlNetAttributes' => [],
5918 
            },
5919 
            'hdlType' => 'std_logic',
5920 
            'width' => 1,
5921 
          },
5922 
          'constant5_op_net_x6' => {
5923 
            'attributes' => {
5924 
              'hdlNetAttributes' => [],
5925 
            },
5926 
            'hdlType' => 'std_logic',
5927 
            'width' => 1,
5928 
          },
5929 
          'constant5_op_net_x7' => {
5930 
            'attributes' => {
5931 
              'hdlNetAttributes' => [],
5932 
            },
5933 
            'hdlType' => 'std_logic',
5934 
            'width' => 1,
5935 
          },
5936 
          'constant5_op_net_x8' => {
5937 
            'attributes' => {
5938 
              'hdlNetAttributes' => [],
5939 
            },
5940 
            'hdlType' => 'std_logic',
5941 
            'width' => 1,
5942 
          },
5943 
          'constant5_op_net_x9' => {
5944 
            'attributes' => {
5945 
              'hdlNetAttributes' => [],
5946 
            },
5947 
            'hdlType' => 'std_logic',
5948 
            'width' => 1,
5949 
          },
5950 
          'debug_in_1i_net' => {
5951 
            'attributes' => {
5952 
              'hdlNetAttributes' => [],
5953 
            },
5954 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5955 
            'width' => 32,
5956 
          },
5957 
          'debug_in_1i_net_x0' => {
5958 
            'attributes' => {
5959 
              'hdlNetAttributes' => [],
5960 
            },
5961 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5962 
            'width' => 32,
5963 
          },
5964 
          'debug_in_2i_net' => {
5965 
            'attributes' => {
5966 
              'hdlNetAttributes' => [],
5967 
            },
5968 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5969 
            'width' => 32,
5970 
          },
5971 
          'debug_in_2i_net_x0' => {
5972 
            'attributes' => {
5973 
              'hdlNetAttributes' => [],
5974 
            },
5975 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5976 
            'width' => 32,
5977 
          },
5978 
          'debug_in_3i_net' => {
5979 
            'attributes' => {
5980 
              'hdlNetAttributes' => [],
5981 
            },
5982 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5983 
            'width' => 32,
5984 
          },
5985 
          'debug_in_3i_net_x0' => {
5986 
            'attributes' => {
5987 
              'hdlNetAttributes' => [],
5988 
            },
5989 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5990 
            'width' => 32,
5991 
          },
5992 
          'debug_in_4i_net' => {
5993 
            'attributes' => {
5994 
              'hdlNetAttributes' => [],
5995 
            },
5996 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5997 
            'width' => 32,
5998 
          },
5999 
          'debug_in_4i_net_x0' => {
6000 
            'attributes' => {
6001 
              'hdlNetAttributes' => [],
6002 
            },
6003 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6004 
            'width' => 32,
6005 
          },
6006 
          'dma_host2board_busy_net' => {
6007 
            'attributes' => {
6008 
              'hdlNetAttributes' => [],
6009 
            },
6010 
            'hdlType' => 'std_logic',
6011 
            'width' => 1,
6012 
          },
6013 
          'dma_host2board_busy_net_x0' => {
6014 
            'attributes' => {
6015 
              'hdlNetAttributes' => [],
6016 
            },
6017 
            'hdlType' => 'std_logic',
6018 
            'width' => 1,
6019 
          },
6020 
          'dma_host2board_done_net' => {
6021 
            'attributes' => {
6022 
              'hdlNetAttributes' => [],
6023 
            },
6024 
            'hdlType' => 'std_logic',
6025 
            'width' => 1,
6026 
          },
6027 
          'dma_host2board_done_net_x0' => {
6028 
            'attributes' => {
6029 
              'hdlNetAttributes' => [],
6030 
            },
6031 
            'hdlType' => 'std_logic',
6032 
            'width' => 1,
6033 
          },
6034 
          'from_register10_data_out_net' => {
6035 
            'attributes' => {
6036 
              'hdlNetAttributes' => [],
6037 
            },
6038 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6039 
            'width' => 32,
6040 
          },
6041 
          'from_register10_data_out_net_x0' => {
6042 
            'attributes' => {
6043 
              'hdlNetAttributes' => [],
6044 
            },
6045 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6046 
            'width' => 32,
6047 
          },
6048 
          'from_register11_data_out_net' => {
6049 
            'attributes' => {
6050 
              'hdlNetAttributes' => [],
6051 
            },
6052 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6053 
            'width' => 32,
6054 
          },
6055 
          'from_register11_data_out_net_x0' => {
6056 
            'attributes' => {
6057 
              'hdlNetAttributes' => [],
6058 
            },
6059 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6060 
            'width' => 32,
6061 
          },
6062 
          'from_register12_data_out_net' => {
6063 
            'attributes' => {
6064 
              'hdlNetAttributes' => [],
6065 
            },
6066 
            'hdlType' => 'std_logic',
6067 
            'width' => 1,
6068 
          },
6069 
          'from_register12_data_out_net_x0' => {
6070 
            'attributes' => {
6071 
              'hdlNetAttributes' => [],
6072 
            },
6073 
            'hdlType' => 'std_logic',
6074 
            'width' => 1,
6075 
          },
6076 
          'from_register13_data_out_net' => {
6077 
            'attributes' => {
6078 
              'hdlNetAttributes' => [],
6079 
            },
6080 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6081 
            'width' => 32,
6082 
          },
6083 
          'from_register13_data_out_net_x0' => {
6084 
            'attributes' => {
6085 
              'hdlNetAttributes' => [],
6086 
            },
6087 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6088 
            'width' => 32,
6089 
          },
6090 
          'from_register14_data_out_net' => {
6091 
            'attributes' => {
6092 
              'hdlNetAttributes' => [],
6093 
            },
6094 
            'hdlType' => 'std_logic',
6095 
            'width' => 1,
6096 
          },
6097 
          'from_register14_data_out_net_x0' => {
6098 
            'attributes' => {
6099 
              'hdlNetAttributes' => [],
6100 
            },
6101 
            'hdlType' => 'std_logic',
6102 
            'width' => 1,
6103 
          },
6104 
          'from_register15_data_out_net' => {
6105 
            'attributes' => {
6106 
              'hdlNetAttributes' => [],
6107 
            },
6108 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6109 
            'width' => 32,
6110 
          },
6111 
          'from_register15_data_out_net_x0' => {
6112 
            'attributes' => {
6113 
              'hdlNetAttributes' => [],
6114 
            },
6115 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6116 
            'width' => 32,
6117 
          },
6118 
          'from_register16_data_out_net' => {
6119 
            'attributes' => {
6120 
              'hdlNetAttributes' => [],
6121 
            },
6122 
            'hdlType' => 'std_logic',
6123 
            'width' => 1,
6124 
          },
6125 
          'from_register16_data_out_net_x0' => {
6126 
            'attributes' => {
6127 
              'hdlNetAttributes' => [],
6128 
            },
6129 
            'hdlType' => 'std_logic',
6130 
            'width' => 1,
6131 
          },
6132 
          'from_register17_data_out_net' => {
6133 
            'attributes' => {
6134 
              'hdlNetAttributes' => [],
6135 
            },
6136 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6137 
            'width' => 32,
6138 
          },
6139 
          'from_register17_data_out_net_x0' => {
6140 
            'attributes' => {
6141 
              'hdlNetAttributes' => [],
6142 
            },
6143 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6144 
            'width' => 32,
6145 
          },
6146 
          'from_register18_data_out_net' => {
6147 
            'attributes' => {
6148 
              'hdlNetAttributes' => [],
6149 
            },
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10806 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
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10809 
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10811 
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10813 
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10814 
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10815 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
10821 
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10835 
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10847 
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10854 
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10855 
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10860 
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10869 
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10870 
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10874 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
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10877 
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10888 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
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10897 
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10899 
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10900 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
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10905 
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10910 
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10911 
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10913 
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10915 
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10918 
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10920 
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10923 
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10924 
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10928 
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10929 
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10936 
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10937 
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10940 
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10945 
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10946 
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10949 
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10950 
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10951 
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10952 
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10953 
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              'port_id' => 0,
10956 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
10957 
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10959 
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10960 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10961 
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10962 
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10963 
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10964 
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10965 
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10967 
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10970 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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10977 
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10978 
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10979 
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10980 
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10982 
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10983 
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10984 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
10985 
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            'hdlType' => 'std_logic_vector(0 downto 0)',
10989 
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10992 
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10993 
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11000 
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11010 
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11015 
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11018 
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11019 
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11020 
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11021 
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11023 
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11024 
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11026 
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11027 
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11028 
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11029 
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11030 
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11031 
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11032 
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11033 
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11034 
              'is_floating_block' => 1,
11035 
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11036 
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11038 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
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11042 
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11046 
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11047 
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11049 
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11050 
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11052 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
11053 
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11054 
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11055 
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11056 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11057 
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11058 
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11059 
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11060 
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11061 
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11062 
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11063 
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11064 
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11065 
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11066 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11067 
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11069 
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11070 
            'hdlType' => 'std_logic_vector(0 downto 0)',
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11072 
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11074 
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11075 
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11076 
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11077 
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11078 
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11079 
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11080 
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11082 
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11087 
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11088 
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11090 
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11091 
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11092 
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11093 
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11094 
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11095 
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11096 
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11097 
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11098 
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11099 
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11100 
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11101 
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11105 
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11108 
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11109 
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11110 
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11111 
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11112 
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11113 
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11114 
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11115 
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11116 
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11117 
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11118 
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11119 
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11120 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
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11123 
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11124 
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11125 
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11126 
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11127 
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11128 
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11129 
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11130 
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11131 
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11134 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
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11136 
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11137 
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11139 
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11140 
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11141 
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11142 
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11143 
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11144 
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11145 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
11149 
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11155 
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11156 
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11157 
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11158 
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11159 
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11160 
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11161 
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11164 
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11169 
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11170 
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11173 
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11174 
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11177 
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11179 
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11182 
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11183 
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11184 
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11186 
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11187 
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11188 
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11190 
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11191 
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11193 
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11194 
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11195 
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11196 
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11197 
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11200 
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11202 
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11205 
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11206 
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11207 
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11208 
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11209 
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11210 
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11213 
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11219 
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11220 
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11221 
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11222 
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11223 
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11224 
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11225 
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11227 
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11228 
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11229 
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11230 
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11231 
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11233 
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11237 
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11238 
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11239 
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11240 
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11242 
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11243 
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11246 
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11251 
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11252 
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11253 
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11254 
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11255 
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11256 
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11257 
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11259 
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11260 
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11261 
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11262 
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11263 
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11264 
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11265 
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11266 
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11267 
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11268 
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11269 
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11270 
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11271 
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11272 
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11273 
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11274 
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11275 
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11276 
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11277 
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11278 
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11279 
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11280 
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11281 
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11282 
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11283 
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11284 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11285 
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11286 
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11287 
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11288 
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11289 
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11290 
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11291 
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11292 
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11293 
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11294 
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11295 
              'must_be_hdl_vector' => 1,
11296 
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11297 
              'port_id' => 0,
11298 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11299 
              'type' => 'Bool',
11300 
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11301 
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11302 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11303 
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11304 
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11305 
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11306 
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11307 
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11308 
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11309 
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11310 
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11311 
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11312 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11313 
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11314 
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11315 
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11316 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11317 
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11318 
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11319 
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11320 
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11321 
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11322 
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11323 
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11324 
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11325 
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11326 
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11327 
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11328 
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11329 
            'hdlType' => 'std_logic',
11330 
            'width' => 1,
11331 
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11332 
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11333 
            'attributes' => {
11334 
              'domain' => '',
11335 
              'group' => 1,
11336 
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11337 
              'is_floating_block' => 1,
11338 
              'period' => 1,
11339 
              'type' => 'logic',
11340 
            },
11341 
            'direction' => 'out',
11342 
            'hdlType' => 'std_logic',
11343 
            'width' => 1,
11344 
          },
11345 
          'to_register9_clr' => {
11346 
            'attributes' => {
11347 
              'domain' => '',
11348 
              'group' => 1,
11349 
              'isClr' => 1,
11350 
              'is_floating_block' => 1,
11351 
              'period' => 1,
11352 
              'type' => 'logic',
11353 
              'valid_bit_used' => 0,
11354 
            },
11355 
            'direction' => 'out',
11356 
            'hdlType' => 'std_logic',
11357 
            'width' => 1,
11358 
          },
11359 
          'to_register9_data_in' => {
11360 
            'attributes' => {
11361 
              'bin_pt' => 0,
11362 
              'is_floating_block' => 1,
11363 
              'must_be_hdl_vector' => 1,
11364 
              'period' => 1,
11365 
              'port_id' => 0,
11366 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11367 
              'type' => 'UFix_32_0',
11368 
            },
11369 
            'direction' => 'out',
11370 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11371 
            'width' => 32,
11372 
          },
11373 
          'to_register9_dout' => {
11374 
            'attributes' => {
11375 
              'bin_pt' => 0,
11376 
              'is_floating_block' => 1,
11377 
              'must_be_hdl_vector' => 1,
11378 
              'period' => 1,
11379 
              'port_id' => 0,
11380 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11381 
              'type' => 'UFix_32_0',
11382 
            },
11383 
            'direction' => 'in',
11384 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11385 
            'width' => 32,
11386 
          },
11387 
          'to_register9_en' => {
11388 
            'attributes' => {
11389 
              'bin_pt' => 0,
11390 
              'is_floating_block' => 1,
11391 
              'must_be_hdl_vector' => 1,
11392 
              'period' => 1,
11393 
              'port_id' => 1,
11394 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11395 
              'type' => 'Bool',
11396 
            },
11397 
            'direction' => 'out',
11398 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11399 
            'width' => 1,
11400 
          },
11401 
        },
11402 
        'subblocks' => {
11403 
          'default_clock_driver_x0' => {
11404 
            'connections' => {
11405 
              'ce_1' => 'ce_1_sg',
11406 
              'clk_1' => 'clk_1_sg',
11407 
              'sysce' => [
11408 
                'constant',
11409 
                '\'1\'',
11410 
              ],
11411 
              'sysce_clr' => [
11412 
                'constant',
11413 
                '\'0\'',
11414 
              ],
11415 
              'sysclk' => 'clkNet',
11416 
            },
11417 
            'entity' => {
11418 
              'attributes' => {
11419 
                'domain' => 'default',
11420 
                'hdlArchAttributes' => [
11421 
                  [
11422 
                    'syn_noprune',
11423 
                    'boolean',
11424 
                    'true',
11425 
                  ],
11426 
                  [
11427 
                    'optimize_primitives',
11428 
                    'boolean',
11429 
                    'false',
11430 
                  ],
11431 
                  [
11432 
                    'dont_touch',
11433 
                    'boolean',
11434 
                    'true',
11435 
                  ],
11436 
                ],
11437 
                'hdlEntityAttributes' => [],
11438 
                'isClkDriver' => 1,
11439 
              },
11440 
              'entityName' => 'default_clock_driver',
11441 
              'ports' => {
11442 
                'ce_1' => {
11443 
                  'attributes' => {
11444 
                    'domain' => 'default',
11445 
                    'group' => 1,
11446 
                    'isCe' => 1,
11447 
                    'period' => 1,
11448 
                    'type' => 'logic',
11449 
                  },
11450 
                  'direction' => 'out',
11451 
                  'hdlType' => 'std_logic',
11452 
                  'width' => 1,
11453 
                },
11454 
                'clk_1' => {
11455 
                  'attributes' => {
11456 
                    'domain' => 'default',
11457 
                    'group' => 1,
11458 
                    'isClk' => 1,
11459 
                    'period' => 1,
11460 
                    'type' => 'logic',
11461 
                  },
11462 
                  'direction' => 'out',
11463 
                  'hdlType' => 'std_logic',
11464 
                  'width' => 1,
11465 
                },
11466 
                'sysce' => {
11467 
                  'attributes' => {
11468 
                    'group' => 4,
11469 
                    'isCe' => 1,
11470 
                    'period' => 1,
11471 
                  },
11472 
                  'direction' => 'in',
11473 
                  'hdlType' => 'std_logic',
11474 
                  'width' => 1,
11475 
                },
11476 
                'sysce_clr' => {
11477 
                  'attributes' => {
11478 
                    'group' => 4,
11479 
                    'isClr' => 1,
11480 
                    'period' => 1,
11481 
                  },
11482 
                  'direction' => 'in',
11483 
                  'hdlType' => 'std_logic',
11484 
                  'width' => 1,
11485 
                },
11486 
                'sysclk' => {
11487 
                  'attributes' => {
11488 
                    'group' => 4,
11489 
                    'isClk' => 1,
11490 
                    'period' => 1,
11491 
                  },
11492 
                  'direction' => 'in',
11493 
                  'hdlType' => 'std_logic',
11494 
                  'width' => 1,
11495 
                },
11496 
              },
11497 
            },
11498 
            'entityName' => 'default_clock_driver',
11499 
          },
11500 
          'inout_logic_x0' => {
11501 
            'connections' => {
11502 
              'data_in' => 'debug_in_2i_net_x0',
11503 
              'data_in_x0' => 'reg04_tv_net_x0',
11504 
              'data_in_x1' => 'reg04_td_net_x0',
11505 
              'data_in_x10' => 'debug_in_3i_net_x0',
11506 
              'data_in_x11' => 'debug_in_4i_net_x0',
11507 
              'data_in_x12' => 'reg09_tv_net_x0',
11508 
              'data_in_x13' => 'reg09_td_net_x0',
11509 
              'data_in_x14' => 'reg10_tv_net_x0',
11510 
              'data_in_x15' => 'reg10_td_net_x0',
11511 
              'data_in_x16' => 'reg08_tv_net_x0',
11512 
              'data_in_x17' => 'reg08_td_net_x0',
11513 
              'data_in_x18' => 'reg11_tv_net_x0',
11514 
              'data_in_x19' => 'reg11_td_net_x0',
11515 
              'data_in_x2' => 'reg05_tv_net_x0',
11516 
              'data_in_x20' => 'reg12_tv_net_x0',
11517 
              'data_in_x21' => 'reg01_tv_net_x0',
11518 
              'data_in_x22' => 'reg12_td_net_x0',
11519 
              'data_in_x23' => 'reg13_tv_net_x0',
11520 
              'data_in_x24' => 'reg13_td_net_x0',
11521 
              'data_in_x25' => 'reg14_tv_net_x0',
11522 
              'data_in_x26' => 'reg14_td_net_x0',
11523 
              'data_in_x27' => 'reg02_tv_net_x0',
11524 
              'data_in_x28' => 'reg02_td_net_x0',
11525 
              'data_in_x29' => 'debug_in_1i_net_x0',
11526 
              'data_in_x3' => 'reg05_td_net_x0',
11527 
              'data_in_x30' => 'reg01_td_net_x0',
11528 
              'data_in_x31' => 'reg03_tv_net_x0',
11529 
              'data_in_x32' => 'reg03_td_net_x0',
11530 
              'data_in_x4' => 'reg06_tv_net_x0',
11531 
              'data_in_x5' => 'reg06_td_net_x0',
11532 
              'data_in_x6' => 'reg07_tv_net_x0',
11533 
              'data_in_x7' => 'reg07_td_net_x0',
11534 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
11535 
              'data_in_x9' => 'dma_host2board_done_net_x0',
11536 
              'data_out' => 'from_register1_data_out_net',
11537 
              'data_out_x0' => 'from_register10_data_out_net',
11538 
              'data_out_x1' => 'from_register11_data_out_net',
11539 
              'data_out_x10' => 'from_register2_data_out_net',
11540 
              'data_out_x11' => 'from_register20_data_out_net',
11541 
              'data_out_x12' => 'from_register21_data_out_net',
11542 
              'data_out_x13' => 'from_register22_data_out_net',
11543 
              'data_out_x14' => 'from_register23_data_out_net',
11544 
              'data_out_x15' => 'from_register24_data_out_net',
11545 
              'data_out_x16' => 'from_register25_data_out_net',
11546 
              'data_out_x17' => 'from_register26_data_out_net',
11547 
              'data_out_x18' => 'from_register27_data_out_net',
11548 
              'data_out_x19' => 'from_register28_data_out_net',
11549 
              'data_out_x2' => 'from_register12_data_out_net',
11550 
              'data_out_x20' => 'from_register3_data_out_net',
11551 
              'data_out_x21' => 'from_register4_data_out_net',
11552 
              'data_out_x22' => 'from_register5_data_out_net',
11553 
              'data_out_x23' => 'from_register6_data_out_net',
11554 
              'data_out_x24' => 'from_register7_data_out_net',
11555 
              'data_out_x25' => 'from_register8_data_out_net',
11556 
              'data_out_x26' => 'from_register9_data_out_net',
11557 
              'data_out_x3' => 'from_register13_data_out_net',
11558 
              'data_out_x4' => 'from_register14_data_out_net',
11559 
              'data_out_x5' => 'from_register15_data_out_net',
11560 
              'data_out_x6' => 'from_register16_data_out_net',
11561 
              'data_out_x7' => 'from_register17_data_out_net',
11562 
              'data_out_x8' => 'from_register18_data_out_net',
11563 
              'data_out_x9' => 'from_register19_data_out_net',
11564 
              'debug_in_1i' => 'debug_in_1i_net',
11565 
              'debug_in_2i' => 'debug_in_2i_net',
11566 
              'debug_in_3i' => 'debug_in_3i_net',
11567 
              'debug_in_4i' => 'debug_in_4i_net',
11568 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
11569 
              'dma_host2board_done' => 'dma_host2board_done_net',
11570 
              'en' => 'constant5_op_net_x0',
11571 
              'en_x0' => 'constant5_op_net_x1',
11572 
              'en_x1' => 'constant5_op_net_x2',
11573 
              'en_x10' => 'constant5_op_net_x11',
11574 
              'en_x11' => 'constant5_op_net_x12',
11575 
              'en_x12' => 'constant1_op_net_x0',
11576 
              'en_x13' => 'constant1_op_net_x1',
11577 
              'en_x14' => 'constant1_op_net_x2',
11578 
              'en_x15' => 'constant1_op_net_x3',
11579 
              'en_x16' => 'constant1_op_net_x4',
11580 
              'en_x17' => 'constant1_op_net_x5',
11581 
              'en_x18' => 'constant1_op_net_x6',
11582 
              'en_x19' => 'constant1_op_net_x7',
11583 
              'en_x2' => 'constant5_op_net_x3',
11584 
              'en_x20' => 'constant1_op_net_x8',
11585 
              'en_x21' => 'constant5_op_net_x13',
11586 
              'en_x22' => 'constant1_op_net_x9',
11587 
              'en_x23' => 'constant1_op_net_x10',
11588 
              'en_x24' => 'constant1_op_net_x11',
11589 
              'en_x25' => 'constant1_op_net_x12',
11590 
              'en_x26' => 'constant1_op_net_x13',
11591 
              'en_x27' => 'constant5_op_net_x14',
11592 
              'en_x28' => 'constant5_op_net_x15',
11593 
              'en_x29' => 'constant5_op_net_x16',
11594 
              'en_x3' => 'constant5_op_net_x4',
11595 
              'en_x30' => 'constant5_op_net_x17',
11596 
              'en_x31' => 'constant5_op_net_x18',
11597 
              'en_x32' => 'constant5_op_net_x19',
11598 
              'en_x4' => 'constant5_op_net_x5',
11599 
              'en_x5' => 'constant5_op_net_x6',
11600 
              'en_x6' => 'constant5_op_net_x7',
11601 
              'en_x7' => 'constant5_op_net_x8',
11602 
              'en_x8' => 'constant5_op_net_x9',
11603 
              'en_x9' => 'constant5_op_net_x10',
11604 
              'reg01_rd' => 'from_register3_data_out_net_x0',
11605 
              'reg01_rv' => 'from_register1_data_out_net_x0',
11606 
              'reg01_td' => 'reg01_td_net',
11607 
              'reg01_tv' => 'reg01_tv_net',
11608 
              'reg02_rd' => 'from_register5_data_out_net_x0',
11609 
              'reg02_rv' => 'from_register2_data_out_net_x0',
11610 
              'reg02_td' => 'reg02_td_net',
11611 
              'reg02_tv' => 'reg02_tv_net',
11612 
              'reg03_rd' => 'from_register7_data_out_net_x0',
11613 
              'reg03_rv' => 'from_register6_data_out_net_x0',
11614 
              'reg03_td' => 'reg03_td_net',
11615 
              'reg03_tv' => 'reg03_tv_net',
11616 
              'reg04_rd' => 'from_register8_data_out_net_x0',
11617 
              'reg04_rv' => 'from_register4_data_out_net_x0',
11618 
              'reg04_td' => 'reg04_td_net',
11619 
              'reg04_tv' => 'reg04_tv_net',
11620 
              'reg05_rd' => 'from_register10_data_out_net_x0',
11621 
              'reg05_rv' => 'from_register9_data_out_net_x0',
11622 
              'reg05_td' => 'reg05_td_net',
11623 
              'reg05_tv' => 'reg05_tv_net',
11624 
              'reg06_rd' => 'from_register11_data_out_net_x0',
11625 
              'reg06_rv' => 'from_register12_data_out_net_x0',
11626 
              'reg06_td' => 'reg06_td_net',
11627 
              'reg06_tv' => 'reg06_tv_net',
11628 
              'reg07_rd' => 'from_register13_data_out_net_x0',
11629 
              'reg07_rv' => 'from_register14_data_out_net_x0',
11630 
              'reg07_td' => 'reg07_td_net',
11631 
              'reg07_tv' => 'reg07_tv_net',
11632 
              'reg08_rd' => 'from_register15_data_out_net_x0',
11633 
              'reg08_rv' => 'from_register16_data_out_net_x0',
11634 
              'reg08_td' => 'reg08_td_net',
11635 
              'reg08_tv' => 'reg08_tv_net',
11636 
              'reg09_rd' => 'from_register17_data_out_net_x0',
11637 
              'reg09_rv' => 'from_register18_data_out_net_x0',
11638 
              'reg09_td' => 'reg09_td_net',
11639 
              'reg09_tv' => 'reg09_tv_net',
11640 
              'reg10_rd' => 'from_register19_data_out_net_x0',
11641 
              'reg10_rv' => 'from_register20_data_out_net_x0',
11642 
              'reg10_td' => 'reg10_td_net',
11643 
              'reg10_tv' => 'reg10_tv_net',
11644 
              'reg11_rd' => 'from_register21_data_out_net_x0',
11645 
              'reg11_rv' => 'from_register22_data_out_net_x0',
11646 
              'reg11_td' => 'reg11_td_net',
11647 
              'reg11_tv' => 'reg11_tv_net',
11648 
              'reg12_rd' => 'from_register23_data_out_net_x0',
11649 
              'reg12_rv' => 'from_register24_data_out_net_x0',
11650 
              'reg12_td' => 'reg12_td_net',
11651 
              'reg12_tv' => 'reg12_tv_net',
11652 
              'reg13_rd' => 'from_register25_data_out_net_x0',
11653 
              'reg13_rv' => 'from_register26_data_out_net_x0',
11654 
              'reg13_td' => 'reg13_td_net',
11655 
              'reg13_tv' => 'reg13_tv_net',
11656 
              'reg14_rd' => 'from_register27_data_out_net_x0',
11657 
              'reg14_rv' => 'from_register28_data_out_net_x0',
11658 
              'reg14_td' => 'reg14_td_net',
11659 
              'reg14_tv' => 'reg14_tv_net',
11660 
            },
11661 
            'entity' => {
11662 
              'attributes' => {
11663 
                'entityAlreadyNetlisted' => 1,
11664 
                'hdlKind' => 'vhdl',
11665 
                'isDesign' => 1,
11666 
                'simulinkName' => 'INOUT_LOGIC',
11667 
              },
11668 
              'entityName' => 'inout_logic',
11669 
              'ports' => {
11670 
                'data_in' => {
11671 
                  'attributes' => {
11672 
                    'bin_pt' => 0,
11673 
                    'is_floating_block' => 1,
11674 
                    'must_be_hdl_vector' => 1,
11675 
                    'period' => 1,
11676 
                    'port_id' => 0,
11677 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11678 
                    'type' => 'UFix_32_0',
11679 
                  },
11680 
                  'direction' => 'out',
11681 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11682 
                  'width' => 32,
11683 
                },
11684 
                'data_in_x0' => {
11685 
                  'attributes' => {
11686 
                    'bin_pt' => 0,
11687 
                    'is_floating_block' => 1,
11688 
                    'must_be_hdl_vector' => 1,
11689 
                    'period' => 1,
11690 
                    'port_id' => 0,
11691 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11692 
                    'type' => 'Bool',
11693 
                  },
11694 
                  'direction' => 'out',
11695 
                  'hdlType' => 'std_logic',
11696 
                  'width' => 1,
11697 
                },
11698 
                'data_in_x1' => {
11699 
                  'attributes' => {
11700 
                    'bin_pt' => 0,
11701 
                    'is_floating_block' => 1,
11702 
                    'must_be_hdl_vector' => 1,
11703 
                    'period' => 1,
11704 
                    'port_id' => 0,
11705 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11706 
                    'type' => 'UFix_32_0',
11707 
                  },
11708 
                  'direction' => 'out',
11709 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11710 
                  'width' => 32,
11711 
                },
11712 
                'data_in_x10' => {
11713 
                  'attributes' => {
11714 
                    'bin_pt' => 0,
11715 
                    'is_floating_block' => 1,
11716 
                    'must_be_hdl_vector' => 1,
11717 
                    'period' => 1,
11718 
                    'port_id' => 0,
11719 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11720 
                    'type' => 'UFix_32_0',
11721 
                  },
11722 
                  'direction' => 'out',
11723 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11724 
                  'width' => 32,
11725 
                },
11726 
                'data_in_x11' => {
11727 
                  'attributes' => {
11728 
                    'bin_pt' => 0,
11729 
                    'is_floating_block' => 1,
11730 
                    'must_be_hdl_vector' => 1,
11731 
                    'period' => 1,
11732 
                    'port_id' => 0,
11733 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11734 
                    'type' => 'UFix_32_0',
11735 
                  },
11736 
                  'direction' => 'out',
11737 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11738 
                  'width' => 32,
11739 
                },
11740 
                'data_in_x12' => {
11741 
                  'attributes' => {
11742 
                    'bin_pt' => 0,
11743 
                    'is_floating_block' => 1,
11744 
                    'must_be_hdl_vector' => 1,
11745 
                    'period' => 1,
11746 
                    'port_id' => 0,
11747 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11748 
                    'type' => 'Bool',
11749 
                  },
11750 
                  'direction' => 'out',
11751 
                  'hdlType' => 'std_logic',
11752 
                  'width' => 1,
11753 
                },
11754 
                'data_in_x13' => {
11755 
                  'attributes' => {
11756 
                    'bin_pt' => 0,
11757 
                    'is_floating_block' => 1,
11758 
                    'must_be_hdl_vector' => 1,
11759 
                    'period' => 1,
11760 
                    'port_id' => 0,
11761 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11762 
                    'type' => 'UFix_32_0',
11763 
                  },
11764 
                  'direction' => 'out',
11765 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11766 
                  'width' => 32,
11767 
                },
11768 
                'data_in_x14' => {
11769 
                  'attributes' => {
11770 
                    'bin_pt' => 0,
11771 
                    'is_floating_block' => 1,
11772 
                    'must_be_hdl_vector' => 1,
11773 
                    'period' => 1,
11774 
                    'port_id' => 0,
11775 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11776 
                    'type' => 'Bool',
11777 
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11778 
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14145 
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14150 
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14206 
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14211 
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14332 
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14333 
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14338 
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14339 
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14340 
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18430 
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18431 
          'needs_vhdl_wrapper' => 0,
18432 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
18433 
        },
18434 
        'entityName' => 'x_x32',
18435 
        'ports' => {
18436 
          'ce' => {
18437 
            'attributes' => {
18438 
              'domain' => '',
18439 
              'group' => 1,
18440 
              'isCe' => 1,
18441 
              'is_floating_block' => 1,
18442 
              'period' => 1,
18443 
              'type' => 'logic',
18444 
            },
18445 
            'direction' => 'in',
18446 
            'hdlType' => 'std_logic',
18447 
            'width' => 1,
18448 
          },
18449 
          'clk' => {
18450 
            'attributes' => {
18451 
              'domain' => '',
18452 
              'group' => 1,
18453 
              'isClk' => 1,
18454 
              'is_floating_block' => 1,
18455 
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18456 
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18457 
            },
18458 
            'direction' => 'in',
18459 
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18460 
            'width' => 1,
18461 
          },
18462 
          'clr' => {
18463 
            'attributes' => {
18464 
              'domain' => '',
18465 
              'group' => 1,
18466 
              'isClr' => 1,
18467 
              'is_floating_block' => 1,
18468 
              'period' => 1,
18469 
              'type' => 'logic',
18470 
              'valid_bit_used' => 0,
18471 
            },
18472 
            'direction' => 'in',
18473 
            'hdlType' => 'std_logic',
18474 
            'width' => 1,
18475 
          },
18476 
          'data_in' => {
18477 
            'attributes' => {
18478 
              'bin_pt' => 0,
18479 
              'is_floating_block' => 1,
18480 
              'must_be_hdl_vector' => 1,
18481 
              'period' => 1,
18482 
              'port_id' => 0,
18483 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
18484 
              'type' => 'UFix_32_0',
18485 
            },
18486 
            'direction' => 'in',
18487 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18488 
            'width' => 32,
18489 
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18490 
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18491 
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18492 
              'bin_pt' => 0,
18493 
              'is_floating_block' => 1,
18494 
              'must_be_hdl_vector' => 1,
18495 
              'period' => 1,
18496 
              'port_id' => 0,
18497 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
18498 
              'type' => 'UFix_32_0',
18499 
            },
18500 
            'direction' => 'out',
18501 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18502 
            'width' => 32,
18503 
          },
18504 
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18505 
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18506 
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18507 
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18508 
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18509 
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18510 
              'port_id' => 1,
18511 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
18512 
              'type' => 'Bool',
18513 
            },
18514 
            'direction' => 'in',
18515 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18516 
            'width' => 1,
18517 
          },
18518 
        },
18519 
      },
18520 
      'entityName' => 'x_x32',
18521 
    },
18522 
  },
18523 
}

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