Subversion Repositories pcie_sg_dma

Release 12.3 - xst M.70d (nt)

Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

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Reading constraint file user_logic_cw.xcf.

XCF parsing done.

TABLE OF CONTENTS

  1) Synthesis Options Summary

  2) HDL Parsing

  3) HDL Elaboration

  4) HDL Synthesis

       4.1) HDL Synthesis Report

  5) Advanced HDL Synthesis

       5.1) Advanced HDL Synthesis Report

  6) Low Level Synthesis

  7) Partition Report

  8) Design Summary

       8.1) Primitive and Black Box Usage

       8.2) Device utilization summary

       8.3) Partition Resource Summary

       8.4) Timing Report

            8.4.1) Clock Information

            8.4.2) Asynchronous Control Signals Information

            8.4.3) Timing Summary

            8.4.4) Timing Details

            8.4.5) Cross Clock Domains Report

=========================================================================

*                      Synthesis Options Summary                        *

=========================================================================

---- Source Parameters

Input File Name                    : "xst_user_logic.prj"

Input Format                       : mixed

Synthesis Constraint File          : user_logic_cw.xcf

---- Target Parameters

Output File Name                   : "user_logic_cw.ngc"

Output Format                      : NGC

Target Device                      : xc6vlx240t-3ff784

---- Source Options

Entity Name                        : user_logic_cw

Top Module Name                    : user_logic_cw

Automatic Register Balancing       : no

---- Target Options

Add IO Buffers                     : NO

Pack IO Registers into IOBs        : Auto

---- General Options

Keep Hierarchy                     : NO

Bus Delimiter                      : ()

Hierarchy Separator                : /

Write Timing Constraints           : yes

---- Other Options

report_timing_constraint_problems  : warning

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified

The following parameters have been added:

Optimization Goal                  : SPEED

=========================================================================

=========================================================================

*                          HDL Parsing                                  *

=========================================================================

Parsing VHDL file "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" into library work

Parsing entity .

Parsing architecture  of entity .

Parsing package .

Parsing package body .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing VHDL file "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" into library work

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

Parsing entity .

Parsing architecture  of entity .

=========================================================================

*                            HDL Elaboration                            *

=========================================================================

Elaborating entity  (architecture ) from library .

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 814: Assignment to from_register15_data_out_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 815: Assignment to from_register16_data_out_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 818: Assignment to from_register19_data_out_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 819: Assignment to from_register1_data_out_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 830: Assignment to from_register2_data_out_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 842: Assignment to from_register_data_out_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 844: Assignment to to_register10_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 845: Assignment to to_register11_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 846: Assignment to to_register12_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 847: Assignment to to_register13_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 848: Assignment to to_register14_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 849: Assignment to to_register15_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 850: Assignment to to_register16_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 851: Assignment to to_register17_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 852: Assignment to to_register18_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 853: Assignment to to_register19_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 854: Assignment to to_register1_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 855: Assignment to to_register20_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 856: Assignment to to_register21_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 857: Assignment to to_register22_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 858: Assignment to to_register23_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 859: Assignment to to_register24_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 860: Assignment to to_register25_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 861: Assignment to to_register26_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 862: Assignment to to_register27_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 863: Assignment to to_register2_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 864: Assignment to to_register3_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 865: Assignment to to_register4_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 866: Assignment to to_register5_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 867: Assignment to to_register6_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 868: Assignment to to_register7_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 869: Assignment to to_register8_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 870: Assignment to to_register9_dout_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 871: Assignment to to_register_dout_net ignored, since the identifier is never used

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

WARNING:HDLCompiler:89 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1751:  remains a black-box since it has no binding entity.

Elaborating entity  (architecture ) from library .

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2634: Assignment to fifo_rd_count_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2637: Assignment to fifo_rd_pempty_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2639: Assignment to fifo_wr_count_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2640: Assignment to fifo_wr_full_net ignored, since the identifier is never used

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2641: Assignment to fifo_wr_pfull_net ignored, since the identifier is never used

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture <>) from library .

Elaborating entity  (architecture ) from library .

WARNING:HDLCompiler:871 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2278: Using initial value false for op_mem_22_20_front_din since it is never assigned

WARNING:HDLCompiler:1127 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2284: Assignment to op_mem_22_20_back ignored, since the identifier is never used

Elaborating entity  (architecture ) from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

WARNING:HDLCompiler:89 - "\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MyUserLogic\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1762:  remains a black-box since it has no binding entity.

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

Elaborating entity  (architecture ) with generics from library .

=========================================================================

*                           HDL Synthesis                               *

=========================================================================

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".

    Set property "syn_black_box = true" for instance .

    Set property "syn_noprune = true" for instance .

    Set property "optimize_primitives = false" for instance .

    Set property "dont_touch = true" for instance .

    Set property "MAX_FANOUT = REDUCE" for signal .

    Set property "syn_keep = true" for signal .

    Set property "KEEP = TRUE" for signal .

WARNING:Xst:37 - Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".

    Set property "syn_noprune = true".

    Set property "optimize_primitives = false".

    Set property "dont_touch = true".

INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port  of the instance  is unconnected or connected to loadless signal.

INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port  of the instance  is unconnected or connected to loadless signal.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".

        period = 1

        log_2_period = 1

        pipeline_regs = 5

        use_bufg = 0

    Set property "MAX_FANOUT = REDUCE" for signal .

    Set property "MAX_FANOUT = REDUCE" for signal .

INFO:Xst:3010 - "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 254: Output port  of the instance  is unconnected or connected to loadless signal.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 1

        init_index = 0

        init_value = "0000"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 1

        init_index = 0

        init_value = "0000"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        din_width = 1

        din_bin_pt = 0

        din_arith = 1

        dout_width = 1

        dout_bin_pt = 0

        dout_arith = 1

        en_width = 1

        en_bin_pt = 0

        en_arith = 1

        bool_conversion = 1

        latency = 0

        quantization = 1

        overflow = 1

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        core_name0 = "cntr_11_0_1a411d6ef586e892"

        op_width = 12

        op_arith = 1

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input  is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        d_width = 1

        init_value = "0"

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 1

        init_index = 2

        init_value = "0"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 1

        init_index = 2

        init_value = "0"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        d_width = 32

        init_value = "00000000000000000000000000000000"

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 32

        init_index = 2

        init_value = "00000000000000000000000000000000"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 32

        init_index = 2

        init_value = "00000000000000000000000000000000"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        d_width = 32

        init_value = "00000000000000110000110100100011"

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 32

        init_index = 2

        init_value = "00000000000000110000110100100011"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 32

        init_index = 2

        init_value = "00000000000000110000110100100011"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        d_width = 32

        init_value = "00000000000000000100101011000000"

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 32

        init_index = 2

        init_value = "00000000000000000100101011000000"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 32

        init_index = 2

        init_value = "00000000000000000100101011000000"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        d_width = 12

        init_value = "000000000000"

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 12

        init_index = 2

        init_value = "000000000000"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 12

        init_index = 2

        init_value = "000000000000"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        d_width = 8

        init_value = "00000000"

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 8

        init_index = 2

        init_value = "00000000"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 8

        init_index = 2

        init_value = "00000000"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        d_width = 64

        init_value = "0000000000000000000000000000000000000000000000000000000000000000"

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 64

        init_index = 2

        init_value = "0000000000000000000000000000000000000000000000000000000000000000"

        latency = 1

    Summary:

        no macro.

Unit  synthesized.

Synthesizing Unit .

    Related source file is "/temp/xilinx pci express/pcie-v6-ml605_ise12_opencores/myuserlogic/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".

        width = 64

        init_index = 2

        init_value = "0000000000000000000000000000000000000000000000000000000000000000"

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .

WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

    Set property "syn_black_box = true" for instance .