OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [masterScript8506854047852905440.pl] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
 
2 
open(PIDFILE, '> pidfile.txt') || die 'Couldn\'t write process ID to file.';
3 
print PIDFILE "$$\n";
4 
close(PIDFILE);
5 
 
6 
eval {
7 
  # Call script(s).
8 
  my $instrs;
9 
  my $results = [];
10 
$ENV{'SYSGEN'} = 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen';
11 
  use Sg;
12 
  $instrs = {
13 
    'HDLCodeGenStatus' => 0.0,
14 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
15 
    'Impl_file' => 'ISE Defaults',
16 
    'Impl_file_sgadvanced' => '',
17 
    'Synth_file' => 'XST Defaults',
18 
    'Synth_file_sgadvanced' => '',
19 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
20 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
21 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
22 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
23 
    'base_system_period_hardware' => 5.0,
24 
    'base_system_period_simulink' => 5.0E-9,
25 
    'block_icon_display' => 'Default',
26 
    'block_type' => 'sysgen',
27 
    'block_version' => '',
28 
    'ce_clr' => 0.0,
29 
    'clock_loc' => '',
30 
    'clock_wrapper' => 'Clock Enables',
31 
    'clock_wrapper_sgadvanced' => '',
32 
    'compilation' => 'NGC Netlist',
33 
    'compilation_lut' => {
34 
      'keys' => [
35 
        'HDL Netlist',
36 
        'Bitstream',
37 
        'NGC Netlist',
38 
      ],
39 
      'values' => [
40 
        'target1',
41 
        'target2',
42 
        'target3',
43 
      ],
44 
    },
45 
    'compilation_target' => 'NGC Netlist',
46 
    'core_generation' => 1.0,
47 
    'core_generation_sgadvanced' => '',
48 
    'core_is_deployed' => 0.0,
49 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c03f93279696b19bd',
50 
    'coregen_part_family' => 'virtex6',
51 
    'createTestbench' => 0,
52 
    'create_interface_document' => 'off',
53 
    'dbl_ovrd' => -1.0,
54 
    'dbl_ovrd_sgadvanced' => '',
55 
    'dcm_input_clock_period' => 5.0,
56 
    'deprecated_control' => 'off',
57 
    'deprecated_control_sgadvanced' => '',
58 
    'design' => 'PCIe_UserLogic_00',
59 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\pcie-v6-ml605_ISE12_OpenCores\\MySysGen\\PCIe_UserLogic_00.mdl',
60 
    'device' => 'xc6vlx240t-3ff784',
61 
    'device_speed' => '-3',
62 
    'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
63 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
64 
    'eval_field' => '0',
65 
    'fileDeliveryDefaults' => [
66 
      [
67 
        '(?i)\\.vhd$',
68 
        { 'fileName' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/perl_results.vhd', },
69 
      ],
70 
      [
71 
        '(?i)\\.v$',
72 
        { 'fileName' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/perl_results.v', },
73 
      ],
74 
    ],
75 
    'fxdptinstalled' => 1.0,
76 
    'generateUsing71FrontEnd' => 1,
77 
    'generating_island_subsystem_handle' => 261.0009765625,
78 
    'generating_subsystem_handle' => 261.0009765625,
79 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
80 
    'has_advanced_control' => '0',
81 
    'hdlDir' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl',
82 
    'hdlKind' => 'vhdl',
83 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
84 
    'impl_file' => 'ISE Defaults*',
85 
    'incr_netlist' => 'off',
86 
    'incr_netlist_sgadvanced' => '',
87 
    'infoedit' => ' System Generator',
88 
    'isdeployed' => 0,
89 
    'ise_version' => '12.3i',
90 
    'master_sysgen_token_handle' => 262.0009765625,
91 
    'matlab' => 'C:/Programmi/MATLAB/R2010a',
92 
    'matlab_fixedpoint' => 1.0,
93 
    'mdlHandle' => 3.0009765625,
94 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
95 
    'modelDiagnostics' => [
96 
      {
97 
        'count' => 339.0,
98 
        'isMask' => 0.0,
99 
        'type' => 'PCIe_UserLogic_00 Total blocks',
100 
      },
101 
      {
102 
        'count' => 4.0,
103 
        'isMask' => 0.0,
104 
        'type' => 'DiscretePulseGenerator',
105 
      },
106 
      {
107 
        'count' => 327.0,
108 
        'isMask' => 0.0,
109 
        'type' => 'S-Function',
110 
      },
111 
      {
112 
        'count' => 4.0,
113 
        'isMask' => 0.0,
114 
        'type' => 'SubSystem',
115 
      },
116 
      {
117 
        'count' => 4.0,
118 
        'isMask' => 0.0,
119 
        'type' => 'Terminator',
120 
      },
121 
      {
122 
        'count' => 23.0,
123 
        'isMask' => 1.0,
124 
        'type' => 'Xilinx Constant Block Block',
125 
      },
126 
      {
127 
        'count' => 1.0,
128 
        'isMask' => 1.0,
129 
        'type' => 'Xilinx Counter Block',
130 
      },
131 
      {
132 
        'count' => 44.0,
133 
        'isMask' => 1.0,
134 
        'type' => 'Xilinx Gateway In Block',
135 
      },
136 
      {
137 
        'count' => 39.0,
138 
        'isMask' => 1.0,
139 
        'type' => 'Xilinx Gateway Out Block',
140 
      },
141 
      {
142 
        'count' => 2.0,
143 
        'isMask' => 1.0,
144 
        'type' => 'Xilinx Inverter Block',
145 
      },
146 
      {
147 
        'count' => 1.0,
148 
        'isMask' => 1.0,
149 
        'type' => 'Xilinx Logical Block Block',
150 
      },
151 
      {
152 
        'count' => 78.0,
153 
        'isMask' => 1.0,
154 
        'type' => 'Xilinx Register Block',
155 
      },
156 
      {
157 
        'count' => 62.0,
158 
        'isMask' => 1.0,
159 
        'type' => 'Xilinx Shared Memory Based From Register Block',
160 
      },
161 
      {
162 
        'count' => 62.0,
163 
        'isMask' => 1.0,
164 
        'type' => 'Xilinx Shared Memory Based To Register Block',
165 
      },
166 
      {
167 
        'count' => 1.0,
168 
        'isMask' => 1.0,
169 
        'type' => 'Xilinx Subsystem Generator Block',
170 
      },
171 
      {
172 
        'count' => 2.0,
173 
        'isMask' => 1.0,
174 
        'type' => 'Xilinx System Generator Block',
175 
      },
176 
      {
177 
        'count' => 14.0,
178 
        'isMask' => 1.0,
179 
        'type' => 'Xilinx Type Converter Block',
180 
      },
181 
    ],
182 
    'model_globals_initialized' => 1.0,
183 
    'model_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
184 
    'myxilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
185 
    'ngc_config' => {
186 
      'include_cf' => 1,
187 
      'include_clockwrapper' => 1.0,
188 
    },
189 
    'ngc_files' => [ 'xlpersistentdff.ngc', ],
190 
    'num_sim_cycles' => '2000000000',
191 
    'package' => 'ff784',
192 
    'part' => 'xc6vlx240t',
193 
    'partFamily' => 'virtex6',
194 
    'port_data_types_enabled' => 1.0,
195 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
196 
    'preserve_hierarchy' => 0.0,
197 
    'proj_type' => 'Project Navigator',
198 
    'proj_type_sgadvanced' => '',
199 
    'run_coregen' => 'off',
200 
    'run_coregen_sgadvanced' => '',
201 
    'sample_time_colors_enabled' => 1.0,
202 
    'sampletimecolors' => 1.0,
203 
    'settings_fcn' => 'xlngcsettings',
204 
    'sg_blockgui_xml' => '',
205 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
206 
    'sg_list_contents' => '',
207 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
208 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
209 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
210 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
211 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
212 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
213 
fprintf(\'\',\'COMMENT: end icon graphics\');
214 
fprintf(\'\',\'COMMENT: begin icon text\');
215 
fprintf(\'\',\'COMMENT: end icon text\');',
216 
    'sg_version' => '',
217 
    'sggui_pos' => '-1,-1,-1,-1',
218 
    'simulation_island_subsystem_handle' => 261.0009765625,
219 
    'simulink_accelerator_running' => 0.0,
220 
    'simulink_debugger_running' => 0.0,
221 
    'simulink_period' => 5.0E-9,
222 
    'speed' => '-3',
223 
    'synth_file' => 'XST Defaults*',
224 
    'synthesisTool' => 'XST',
225 
    'synthesis_language' => 'vhdl',
226 
    'synthesis_tool' => 'XST',
227 
    'synthesis_tool_sgadvanced' => '',
228 
    'sysclk_period' => 5.0,
229 
    'sysgen' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
230 
    'sysgenRoot' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
231 
    'sysgenTokenSettings' => {
232 
      'Impl_file' => 'ISE Defaults',
233 
      'Impl_file_sgadvanced' => '',
234 
      'Synth_file' => 'XST Defaults',
235 
      'Synth_file_sgadvanced' => '',
236 
      'base_system_period_hardware' => 5.0,
237 
      'base_system_period_simulink' => 5.0E-9,
238 
      'block_icon_display' => 'Default',
239 
      'block_type' => 'sysgen',
240 
      'block_version' => '',
241 
      'ce_clr' => 0.0,
242 
      'clock_loc' => '',
243 
      'clock_wrapper' => 'Clock Enables',
244 
      'clock_wrapper_sgadvanced' => '',
245 
      'compilation' => 'NGC Netlist',
246 
      'compilation_lut' => {
247 
        'keys' => [
248 
          'HDL Netlist',
249 
          'Bitstream',
250 
          'NGC Netlist',
251 
        ],
252 
        'values' => [
253 
          'target1',
254 
          'target2',
255 
          'target3',
256 
        ],
257 
      },
258 
      'core_generation' => 1.0,
259 
      'core_generation_sgadvanced' => '',
260 
      'coregen_part_family' => 'virtex6',
261 
      'create_interface_document' => 'off',
262 
      'dbl_ovrd' => -1.0,
263 
      'dbl_ovrd_sgadvanced' => '',
264 
      'dcm_input_clock_period' => 5.0,
265 
      'deprecated_control' => 'off',
266 
      'deprecated_control_sgadvanced' => '',
267 
      'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
268 
      'eval_field' => '0',
269 
      'has_advanced_control' => '0',
270 
      'impl_file' => 'ISE Defaults*',
271 
      'incr_netlist' => 'off',
272 
      'incr_netlist_sgadvanced' => '',
273 
      'infoedit' => ' System Generator',
274 
      'master_sysgen_token_handle' => 262.0009765625,
275 
      'ngc_config' => {
276 
        'include_cf' => 1,
277 
        'include_clockwrapper' => 1.0,
278 
      },
279 
      'package' => 'ff784',
280 
      'part' => 'xc6vlx240t',
281 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
282 
      'preserve_hierarchy' => 0.0,
283 
      'proj_type' => 'Project Navigator',
284 
      'proj_type_sgadvanced' => '',
285 
      'run_coregen' => 'off',
286 
      'run_coregen_sgadvanced' => '',
287 
      'settings_fcn' => 'xlngcsettings',
288 
      'sg_blockgui_xml' => '',
289 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
290 
      'sg_list_contents' => '',
291 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
292 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
293 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
294 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
295 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
296 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
297 
fprintf(\'\',\'COMMENT: end icon graphics\');
298 
fprintf(\'\',\'COMMENT: begin icon text\');
299 
fprintf(\'\',\'COMMENT: end icon text\');',
300 
      'sggui_pos' => '-1,-1,-1,-1',
301 
      'simulation_island_subsystem_handle' => 261.0009765625,
302 
      'simulink_period' => 5.0E-9,
303 
      'speed' => '-3',
304 
      'synth_file' => 'XST Defaults*',
305 
      'synthesis_language' => 'vhdl',
306 
      'synthesis_tool' => 'XST',
307 
      'synthesis_tool_sgadvanced' => '',
308 
      'sysclk_period' => 5.0,
309 
      'testbench' => 0,
310 
      'testbench_sgadvanced' => '',
311 
      'trim_vbits' => 1.0,
312 
      'trim_vbits_sgadvanced' => '',
313 
      'xilinx_device' => 'xc6vlx240t-3ff784',
314 
      'xilinxfamily' => 'virtex6',
315 
    },
316 
    'sysgen_Root' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
317 
    'systemClockPeriod' => 5.0,
318 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
319 
    'testbench' => 0,
320 
    'testbench_sgadvanced' => '',
321 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen',
322 
    'trim_vbits' => 1.0,
323 
    'trim_vbits_sgadvanced' => '',
324 
    'use_ce_syn_keep' => 1,
325 
    'use_strict_names' => 1,
326 
    'user_tips_enabled' => 0.0,
327 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
328 
    'using71Netlister' => 1,
329 
    'verilog_files' => [
330 
      'conv_pkg.v',
331 
      'synth_reg.v',
332 
      'synth_reg_w_init.v',
333 
      'convert_type.v',
334 
    ],
335 
    'version' => '',
336 
    'vhdl_files' => [
337 
      'conv_pkg.vhd',
338 
      'synth_reg.vhd',
339 
      'synth_reg_w_init.vhd',
340 
    ],
341 
    'vsimtime' => '11000000275.000000 ns',
342 
    'xilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
343 
    'xilinx_device' => 'xc6vlx240t-3ff784',
344 
    'xilinx_family' => 'virtex6',
345 
    'xilinx_package' => 'ff784',
346 
    'xilinx_part' => 'xc6vlx240t',
347 
    'xilinxdevice' => 'xc6vlx240t-3ff784',
348 
    'xilinxfamily' => 'virtex6',
349 
    'xilinxpart' => 'xc6vlx240t',
350 
  };
351 
  push(@$results, &Sg::setAttributes($instrs));
352 
  use SgDeliverFile;
353 
  $instrs = {
354 
    'collaborationName' => 'conv_pkg.vhd',
355 
    'sourceFile' => 'hdl/conv_pkg.vhd',
356 
    'templateKeyValues' => {},
357 
  };
358 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
359 
  $instrs = {
360 
    'collaborationName' => 'synth_reg.vhd',
361 
    'sourceFile' => 'hdl/synth_reg.vhd',
362 
    'templateKeyValues' => {},
363 
  };
364 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
365 
  $instrs = {
366 
    'collaborationName' => 'synth_reg_w_init.vhd',
367 
    'sourceFile' => 'hdl/synth_reg_w_init.vhd',
368 
    'templateKeyValues' => {},
369 
  };
370 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
371 
  $instrs = {
372 
    'collaborationName' => 'xlpersistentdff.ngc',
373 
    'sourceFile' => 'hdl/xlpersistentdff.ngc',
374 
    'templateKeyValues' => {},
375 
  };
376 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
377 
  $instrs = {
378 
    'entity_declaration_hash' => 'a7dd946f5e9dd6fc958f288a53dd6858',
379 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlconvert.vhd',
380 
  };
381 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
382 
  $instrs = {
383 
    'entity_declaration_hash' => '26c90b101ce1ca8b2f28c242a8215ef7',
384 
    'sourceFile' => 'hdl/xlmcode.vhd',
385 
    'templateKeyValues' => {
386 
      'crippled_architecture' => 'is
387 
begin
388 
  op <= "0";
389 
end',
390 
      'crippled_entity' => 'is
391 
  port (
392 
    op : out std_logic_vector((1 - 1) downto 0);
393 
    clk : in std_logic;
394 
    ce : in std_logic;
395 
    clr : in std_logic);
396 
end',
397 
      'entity_name' => 'constant_963ed6358a',
398 
    },
399 
  };
400 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
401 
  $instrs = {
402 
    'entity_declaration_hash' => '0c4ac1a3e3f45847fa89e7315cf415da',
403 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
404 
  };
405 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
406 
  $instrs = {
407 
    'entity_declaration_hash' => 'e37176f4d33fddd201240d8ee9b0aede',
408 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
409 
  };
410 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
411 
  $instrs = {
412 
    'entity_declaration_hash' => '13366d021ddc9f5413827bc05cb9e24f',
413 
    'sourceFile' => 'hdl/xlmcode.vhd',
414 
    'templateKeyValues' => {
415 
      'crippled_architecture' => 'is
416 
begin
417 
  op <= "1";
418 
end',
419 
      'crippled_entity' => 'is
420 
  port (
421 
    op : out std_logic_vector((1 - 1) downto 0);
422 
    clk : in std_logic;
423 
    ce : in std_logic;
424 
    clr : in std_logic);
425 
end',
426 
      'entity_name' => 'constant_6293007044',
427 
    },
428 
  };
429 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
430 
  $instrs = {
431 
    'entity_declaration_hash' => '2ba5044b83e42ac193c1ef05b1f91478',
432 
    'sourceFile' => 'hdl/xlmcode.vhd',
433 
    'templateKeyValues' => {
434 
      'crippled_architecture' => 'is
435 
begin
436 
  op <= "11111111";
437 
end',
438 
      'crippled_entity' => 'is
439 
  port (
440 
    op : out std_logic_vector((8 - 1) downto 0);
441 
    clk : in std_logic;
442 
    ce : in std_logic;
443 
    clr : in std_logic);
444 
end',
445 
      'entity_name' => 'constant_19562ab42f',
446 
    },
447 
  };
448 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
449 
  use SgGenerateCores;
450 
  $instrs = [
451 
    'SELECT Binary_Counter virtex6 Xilinx,_Inc. 11.0',
452 
    '# 12.3_M.70d',
453 
    '# DEVICE virtex6',
454 
    '# VHDL',
455 
    'CSET ainit_value = 0',
456 
    'CSET ce = true',
457 
    'CSET count_mode = UP',
458 
    'CSET fb_latency = 0',
459 
    'CSET final_count_value = 1',
460 
    'CSET implementation = Fabric',
461 
    'CSET increment_value = 1',
462 
    'CSET latency = 1',
463 
    'CSET load = false',
464 
    'CSET output_width = 12',
465 
    'CSET restrict_count = false',
466 
    'CSET sclr = false',
467 
    'CSET sinit = true',
468 
    'CSET sinit_value = 0',
469 
    'CSET sset = false',
470 
    'CSET sync_ce_priority = Sync_Overrides_CE',
471 
    'CSET sync_threshold_output = false',
472 
    'CSET syncctrlpriority = Reset_Overrides_Set',
473 
    'CSET component_name = cntr_11_0_1a411d6ef586e892',
474 
    'GENERATE',
475 
  ];
476 
  push(@$results, &SgGenerateCores::saveXcoSequence($instrs));
477 
  $instrs = {
478 
    'entity_declaration_hash' => 'c756c264d15a5b2b927a6302c65ba025',
479 
    'sourceFile' => 'hdl/xlcounter_free.vhd',
480 
    'templateKeyValues' => {
481 
      'core_component_def' => '      clk: in std_logic;
482 
      ce: in std_logic;
483 
      SINIT: in std_logic;
484 
      q: out std_logic_vector(op_width - 1 downto 0)',
485 
      'core_instance_text' => '        clk => clk,
486 
        ce => core_ce,
487 
        SINIT => core_sinit,
488 
        q => op_net',
489 
      'core_name0' => 'cntr_11_0_1a411d6ef586e892',
490 
      'entity_name.0' => 'xlcounter_free',
491 
      'needs_core' => 1,
492 
    },
493 
  };
494 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
495 
  $instrs = {
496 
    'entity_declaration_hash' => 'b32a0080f8f47e0be7ec44c6ad81b20b',
497 
    'sourceFile' => 'hdl/xlmcode.vhd',
498 
    'templateKeyValues' => {
499 
      'crippled_architecture' => 'is
500 
  signal ip_1_26: boolean;
501 
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
502 
  signal op_mem_22_20: array_type_op_mem_22_20 := (
503 
 
504 
  signal op_mem_22_20_front_din: boolean;
505 
  signal op_mem_22_20_back: boolean;
506 
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
507 
  signal internal_ip_12_1_bitnot: boolean;
508 
begin
509 
  ip_1_26 <= ((ip) = "1");
510 
  op_mem_22_20_back <= op_mem_22_20(0);
511 
  proc_op_mem_22_20: process (clk)
512 
  is
513 
    variable i: integer;
514 
  begin
515 
    if (clk\'event and (clk = \'1\')) then
516 
      if ((ce = \'1\') and (op_mem_22_20_push_front_pop_back_en = \'1\')) then
517 
        op_mem_22_20(0) <= op_mem_22_20_front_din;
518 
      end if;
519 
    end if;
520 
  end process proc_op_mem_22_20;
521 
  internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
522 
  op_mem_22_20_push_front_pop_back_en <= \'0\';
523 
  op <= boolean_to_vector(internal_ip_12_1_bitnot);
524 
end',
525 
      'crippled_entity' => 'is
526 
  port (
527 
    ip : in std_logic_vector((1 - 1) downto 0);
528 
    op : out std_logic_vector((1 - 1) downto 0);
529 
    clk : in std_logic;
530 
    ce : in std_logic;
531 
    clr : in std_logic);
532 
end',
533 
      'entity_name' => 'inverter_e5b38cca3b',
534 
    },
535 
  };
536 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
537 
  $instrs = {
538 
    'entity_declaration_hash' => '298203483c3de52896eed04fd75246a4',
539 
    'sourceFile' => 'hdl/xlmcode.vhd',
540 
    'templateKeyValues' => {
541 
      'crippled_architecture' => 'is
542 
  signal d0_1_24: std_logic;
543 
  signal d1_1_27: std_logic;
544 
  signal fully_2_1_bit: std_logic;
545 
begin
546 
  d0_1_24 <= d0(0);
547 
  d1_1_27 <= d1(0);
548 
  fully_2_1_bit <= d0_1_24 and d1_1_27;
549 
  y <= std_logic_to_vector(fully_2_1_bit);
550 
end',
551 
      'crippled_entity' => 'is
552 
  port (
553 
    d0 : in std_logic_vector((1 - 1) downto 0);
554 
    d1 : in std_logic_vector((1 - 1) downto 0);
555 
    y : out std_logic_vector((1 - 1) downto 0);
556 
    clk : in std_logic;
557 
    ce : in std_logic;
558 
    clr : in std_logic);
559 
end',
560 
      'entity_name' => 'logical_80f90b97d0',
561 
    },
562 
  };
563 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
564 
  $instrs = {
565 
    'entity_declaration_hash' => '6c1006b5d6dfcc9d88216595284ba076',
566 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
567 
  };
568 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
569 
  $instrs = {
570 
    'entity_declaration_hash' => 'b862325e322cafaa1e5e578de2d9271e',
571 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
572 
  };
573 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
574 
  $instrs = {
575 
    'entity_declaration_hash' => '2d86c2a3a4d8d67fd62084d97c346256',
576 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
577 
  };
578 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
579 
  $instrs = {
580 
    'entity_declaration_hash' => 'd229ba08618a7db429a5cc03ce17d7b3',
581 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
582 
  };
583 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
584 
  $instrs = {
585 
    'entity_declaration_hash' => 'ff232d6f7135722c30c4cd389ee72aa2',
586 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
587 
  };
588 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
589 
  $instrs = {
590 
    'entity_declaration_hash' => 'cf40faaa77b411ce36d10e66338ef442',
591 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
592 
  };
593 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
594 
  $instrs = {
595 
    'entity_declaration_hash' => 'a3eaa5bcbe4a3aa0615393a3055651ed',
596 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
597 
  };
598 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
599 
  $instrs = {
600 
    'entity_declaration_hash' => '4120b68addbdabc307639f636a7e2c31',
601 
    'sourceFile' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
602 
  };
603 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
604 
  local *wrapup = $Sg::{'wrapup'};
605 
  push(@$results, &Sg::wrapup())   if (defined(&wrapup));
606 
  local *wrapup = $SgDeliverFile::{'wrapup'};
607 
  push(@$results, &SgDeliverFile::wrapup())   if (defined(&wrapup));
608 
  local *wrapup = $SgGenerateCores::{'wrapup'};
609 
  push(@$results, &SgGenerateCores::wrapup())   if (defined(&wrapup));
610 
  use Carp qw(croak);
611 
  $ENV{'SYSGEN'} = 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen';
612 
  open(RESULTS, '> C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results8853698742598689288') ||
613 
    croak 'couldn\'t open C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results8853698742598689288';
614 
  binmode(RESULTS);
615 
  print RESULTS &Sg::toString($results) . "\n";
616 
  close(RESULTS) ||
617 
    croak 'trouble writing C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results8853698742598689288';
618 
};
619 
 
620 
if ($@) {
621 
  open(RESULTS, '> C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results8853698742598689288') ||
622 
    croak 'couldn\'t open C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results8853698742598689288';
623 
  binmode(RESULTS);
624 
  print RESULTS $@ . "\n";
625 
  close(RESULTS) ||
626 
    croak 'trouble writing C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results8853698742598689288';
627 
  exit(1);
628 
}
629 
 
630 
exit(0);

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