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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [nonleaf_results.vhd] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
library IEEE;
2 
use IEEE.std_logic_1164.all;
3 
use work.conv_pkg.all;
4 
 
5 
-- Generated from Simulink block "USER_LOGIC"
6 
 
7 
entity user_logic is
8 
  port (
9 
    bram_rd_dout: in std_logic_vector(63 downto 0);
10 
    ce_1: in std_logic;
11 
    clk_1: in std_logic;
12 
    data_out: in std_logic;
13 
    data_out_x0: in std_logic_vector(31 downto 0);
14 
    data_out_x1: in std_logic;
15 
    data_out_x10: in std_logic_vector(31 downto 0);
16 
    data_out_x11: in std_logic;
17 
    data_out_x12: in std_logic_vector(31 downto 0);
18 
    data_out_x13: in std_logic;
19 
    data_out_x14: in std_logic_vector(31 downto 0);
20 
    data_out_x15: in std_logic;
21 
    data_out_x16: in std_logic_vector(31 downto 0);
22 
    data_out_x17: in std_logic;
23 
    data_out_x18: in std_logic_vector(31 downto 0);
24 
    data_out_x19: in std_logic_vector(31 downto 0);
25 
    data_out_x2: in std_logic_vector(31 downto 0);
26 
    data_out_x20: in std_logic;
27 
    data_out_x21: in std_logic_vector(31 downto 0);
28 
    data_out_x22: in std_logic;
29 
    data_out_x23: in std_logic;
30 
    data_out_x24: in std_logic_vector(31 downto 0);
31 
    data_out_x25: in std_logic;
32 
    data_out_x26: in std_logic_vector(31 downto 0);
33 
    data_out_x27: in std_logic;
34 
    data_out_x28: in std_logic_vector(31 downto 0);
35 
    data_out_x3: in std_logic;
36 
    data_out_x6: in std_logic_vector(31 downto 0);
37 
    data_out_x7: in std_logic;
38 
    data_out_x8: in std_logic_vector(31 downto 0);
39 
    data_out_x9: in std_logic;
40 
    fifo_rd_count: in std_logic_vector(14 downto 0);
41 
    fifo_rd_dout: in std_logic_vector(71 downto 0);
42 
    fifo_rd_empty: in std_logic;
43 
    fifo_rd_pempty: in std_logic;
44 
    fifo_rd_valid: in std_logic;
45 
    fifo_wr_count: in std_logic_vector(14 downto 0);
46 
    fifo_wr_full: in std_logic;
47 
    fifo_wr_pfull: in std_logic;
48 
    rst_i: in std_logic;
49 
    bram_rd_addr: out std_logic_vector(11 downto 0);
50 
    bram_wr_addr: out std_logic_vector(11 downto 0);
51 
    bram_wr_din: out std_logic_vector(63 downto 0);
52 
    bram_wr_en: out std_logic_vector(7 downto 0);
53 
    data_in: out std_logic_vector(31 downto 0);
54 
    data_in_x0: out std_logic;
55 
    data_in_x1: out std_logic;
56 
    data_in_x10: out std_logic_vector(31 downto 0);
57 
    data_in_x11: out std_logic_vector(31 downto 0);
58 
    data_in_x12: out std_logic;
59 
    data_in_x13: out std_logic_vector(31 downto 0);
60 
    data_in_x14: out std_logic;
61 
    data_in_x15: out std_logic_vector(31 downto 0);
62 
    data_in_x16: out std_logic;
63 
    data_in_x17: out std_logic_vector(31 downto 0);
64 
    data_in_x18: out std_logic;
65 
    data_in_x19: out std_logic_vector(31 downto 0);
66 
    data_in_x2: out std_logic;
67 
    data_in_x20: out std_logic_vector(31 downto 0);
68 
    data_in_x21: out std_logic;
69 
    data_in_x22: out std_logic;
70 
    data_in_x23: out std_logic_vector(31 downto 0);
71 
    data_in_x24: out std_logic;
72 
    data_in_x25: out std_logic_vector(31 downto 0);
73 
    data_in_x26: out std_logic_vector(31 downto 0);
74 
    data_in_x3: out std_logic;
75 
    data_in_x4: out std_logic_vector(31 downto 0);
76 
    data_in_x5: out std_logic;
77 
    data_in_x6: out std_logic_vector(31 downto 0);
78 
    data_in_x7: out std_logic;
79 
    data_in_x8: out std_logic_vector(31 downto 0);
80 
    data_in_x9: out std_logic;
81 
    en: out std_logic;
82 
    en_x0: out std_logic;
83 
    en_x1: out std_logic;
84 
    en_x10: out std_logic;
85 
    en_x11: out std_logic;
86 
    en_x12: out std_logic;
87 
    en_x13: out std_logic;
88 
    en_x14: out std_logic;
89 
    en_x15: out std_logic;
90 
    en_x16: out std_logic;
91 
    en_x17: out std_logic;
92 
    en_x18: out std_logic;
93 
    en_x19: out std_logic;
94 
    en_x2: out std_logic;
95 
    en_x20: out std_logic;
96 
    en_x21: out std_logic;
97 
    en_x22: out std_logic;
98 
    en_x23: out std_logic;
99 
    en_x24: out std_logic;
100 
    en_x25: out std_logic;
101 
    en_x26: out std_logic;
102 
    en_x3: out std_logic;
103 
    en_x4: out std_logic;
104 
    en_x5: out std_logic;
105 
    en_x6: out std_logic;
106 
    en_x7: out std_logic;
107 
    en_x8: out std_logic;
108 
    en_x9: out std_logic;
109 
    fifo_rd_en: out std_logic;
110 
    fifo_wr_din: out std_logic_vector(71 downto 0);
111 
    fifo_wr_en: out std_logic;
112 
    rst_o: out std_logic;
113 
    user_int_1o: out std_logic;
114 
    user_int_2o: out std_logic;
115 
    user_int_3o: out std_logic
116 
  );
117 
end user_logic;
118 
 
119 
architecture structural of user_logic is
120 
  attribute core_generation_info: string;
121 
  attribute core_generation_info of structural : architecture is "PCIe_UserLogic_00,sysgen_core,{clock_period=5.00000000,clocking=Clock_Enables,compilation=NGC_Netlist,sample_periods=1.00000000000,testbench=0,total_blocks=339,xilinx_constant_block_block=23,xilinx_counter_block=1,xilinx_gateway_in_block=44,xilinx_gateway_out_block=39,xilinx_inverter_block=2,xilinx_logical_block_block=1,xilinx_register_block=78,xilinx_shared_memory_based_from_register_block=62,xilinx_shared_memory_based_to_register_block=62,xilinx_subsystem_generator_block=1,xilinx_system_generator_block=2,xilinx_type_converter_block=14,}";
122 
 
123 
  signal bram_rd_addr_net: std_logic_vector(11 downto 0);
124 
  signal bram_rd_dout_net: std_logic_vector(63 downto 0);
125 
  signal bram_wr_addr_net: std_logic_vector(11 downto 0);
126 
  signal bram_wr_din_net: std_logic_vector(63 downto 0);
127 
  signal bram_wr_en_net: std_logic_vector(7 downto 0);
128 
  signal ce_1_sg_x0: std_logic;
129 
  signal clk_1_sg_x0: std_logic;
130 
  signal constant10_op_net: std_logic;
131 
  signal constant11_op_net: std_logic;
132 
  signal constant12_op_net: std_logic;
133 
  signal constant14_op_net: std_logic;
134 
  signal constant15_op_net: std_logic;
135 
  signal constant19_op_net: std_logic;
136 
  signal constant1_op_net: std_logic;
137 
  signal constant20_op_net: std_logic;
138 
  signal constant21_op_net: std_logic;
139 
  signal constant22_op_net: std_logic;
140 
  signal constant23_op_net: std_logic;
141 
  signal constant24_op_net: std_logic;
142 
  signal constant25_op_net: std_logic;
143 
  signal constant26_op_net: std_logic;
144 
  signal constant2_op_net: std_logic_vector(7 downto 0);
145 
  signal constant3_op_net: std_logic;
146 
  signal constant4_op_net: std_logic;
147 
  signal constant6_op_net_x0: std_logic;
148 
  signal constant7_op_net: std_logic;
149 
  signal constant8_op_net: std_logic;
150 
  signal constant9_op_net: std_logic;
151 
  signal convert11_dout_net: std_logic;
152 
  signal convert12_dout_net: std_logic;
153 
  signal convert14_dout_net: std_logic;
154 
  signal convert15_dout_net: std_logic;
155 
  signal convert16_dout_net: std_logic;
156 
  signal convert17_dout_net: std_logic;
157 
  signal convert1_dout_net: std_logic;
158 
  signal convert4_dout_net: std_logic;
159 
  signal convert5_dout_net: std_logic;
160 
  signal convert6_dout_net: std_logic;
161 
  signal convert7_dout_net: std_logic;
162 
  signal convert8_dout_net: std_logic;
163 
  signal counter4_op_net: std_logic_vector(11 downto 0);
164 
  signal data_in_net: std_logic_vector(31 downto 0);
165 
  signal data_in_x0_net: std_logic;
166 
  signal data_in_x10_net: std_logic_vector(31 downto 0);
167 
  signal data_in_x11_net: std_logic_vector(31 downto 0);
168 
  signal data_in_x12_net: std_logic;
169 
  signal data_in_x13_net: std_logic_vector(31 downto 0);
170 
  signal data_in_x14_net: std_logic;
171 
  signal data_in_x15_net: std_logic_vector(31 downto 0);
172 
  signal data_in_x16_net: std_logic;
173 
  signal data_in_x17_net: std_logic_vector(31 downto 0);
174 
  signal data_in_x18_net: std_logic;
175 
  signal data_in_x19_net: std_logic_vector(31 downto 0);
176 
  signal data_in_x1_net: std_logic;
177 
  signal data_in_x20_net: std_logic_vector(31 downto 0);
178 
  signal data_in_x21_net: std_logic;
179 
  signal data_in_x22_net: std_logic;
180 
  signal data_in_x23_net: std_logic_vector(31 downto 0);
181 
  signal data_in_x24_net: std_logic;
182 
  signal data_in_x25_net: std_logic_vector(31 downto 0);
183 
  signal data_in_x26_net: std_logic_vector(31 downto 0);
184 
  signal data_in_x2_net: std_logic;
185 
  signal data_in_x3_net: std_logic;
186 
  signal data_in_x4_net: std_logic_vector(31 downto 0);
187 
  signal data_in_x5_net: std_logic;
188 
  signal data_in_x6_net: std_logic_vector(31 downto 0);
189 
  signal data_in_x7_net: std_logic;
190 
  signal data_in_x8_net: std_logic_vector(31 downto 0);
191 
  signal data_in_x9_net: std_logic;
192 
  signal data_out_net: std_logic;
193 
  signal data_out_x0_net: std_logic_vector(31 downto 0);
194 
  signal data_out_x10_net: std_logic_vector(31 downto 0);
195 
  signal data_out_x11_net: std_logic;
196 
  signal data_out_x12_net: std_logic_vector(31 downto 0);
197 
  signal data_out_x13_net: std_logic;
198 
  signal data_out_x14_net: std_logic_vector(31 downto 0);
199 
  signal data_out_x15_net: std_logic;
200 
  signal data_out_x16_net: std_logic_vector(31 downto 0);
201 
  signal data_out_x17_net: std_logic;
202 
  signal data_out_x18_net: std_logic_vector(31 downto 0);
203 
  signal data_out_x19_net: std_logic_vector(31 downto 0);
204 
  signal data_out_x1_net: std_logic;
205 
  signal data_out_x20_net: std_logic;
206 
  signal data_out_x21_net: std_logic_vector(31 downto 0);
207 
  signal data_out_x22_net: std_logic;
208 
  signal data_out_x23_net: std_logic;
209 
  signal data_out_x24_net: std_logic_vector(31 downto 0);
210 
  signal data_out_x25_net: std_logic;
211 
  signal data_out_x26_net: std_logic_vector(31 downto 0);
212 
  signal data_out_x27_net: std_logic;
213 
  signal data_out_x28_net: std_logic_vector(31 downto 0);
214 
  signal data_out_x2_net: std_logic_vector(31 downto 0);
215 
  signal data_out_x3_net: std_logic;
216 
  signal data_out_x6_net: std_logic_vector(31 downto 0);
217 
  signal data_out_x7_net: std_logic;
218 
  signal data_out_x8_net: std_logic_vector(31 downto 0);
219 
  signal data_out_x9_net: std_logic;
220 
  signal dinb: std_logic_vector(31 downto 0);
221 
  signal dinb_x0: std_logic_vector(31 downto 0);
222 
  signal fifo_rd_count_net: std_logic_vector(14 downto 0);
223 
  signal fifo_rd_dout_net: std_logic_vector(71 downto 0);
224 
  signal fifo_rd_empty_net: std_logic;
225 
  signal fifo_rd_en_net: std_logic;
226 
  signal fifo_rd_pempty_net: std_logic;
227 
  signal fifo_rd_valid_net: std_logic;
228 
  signal fifo_wr_count_net: std_logic_vector(14 downto 0);
229 
  signal fifo_wr_din_net: std_logic_vector(71 downto 0);
230 
  signal fifo_wr_en_net: std_logic;
231 
  signal fifo_wr_full_net: std_logic;
232 
  signal fifo_wr_pfull_net: std_logic;
233 
  signal inverter3_op_net: std_logic;
234 
  signal inverter5_op_net: std_logic;
235 
  signal logical4_y_net: std_logic;
236 
  signal rst_i_net: std_logic;
237 
  signal rst_o_net: std_logic;
238 
  signal timecountreset: std_logic;
239 
  signal timecounttrigger: std_logic;
240 
  signal tx_en_in105_q_net: std_logic;
241 
  signal tx_en_in107_q_net: std_logic;
242 
  signal tx_en_in116_q_net: std_logic;
243 
  signal tx_en_in117_q_net: std_logic_vector(31 downto 0);
244 
  signal tx_en_in119_q_net: std_logic;
245 
  signal tx_en_in120_q_net: std_logic_vector(31 downto 0);
246 
  signal tx_en_in123_q_net: std_logic;
247 
  signal tx_en_in124_q_net: std_logic_vector(31 downto 0);
248 
  signal tx_en_in127_q_net: std_logic;
249 
  signal tx_en_in128_q_net: std_logic_vector(31 downto 0);
250 
  signal tx_en_in12_q_net: std_logic_vector(31 downto 0);
251 
  signal tx_en_in16_q_net: std_logic_vector(11 downto 0);
252 
  signal tx_en_in17_q_net: std_logic_vector(11 downto 0);
253 
  signal tx_en_in18_q_net: std_logic_vector(7 downto 0);
254 
  signal tx_en_in30_q_net: std_logic_vector(11 downto 0);
255 
  signal tx_en_in4_q_net: std_logic;
256 
  signal tx_en_in52_q_net: std_logic_vector(31 downto 0);
257 
  signal tx_en_in58_q_net: std_logic;
258 
  signal tx_en_in59_q_net: std_logic;
259 
  signal tx_en_in5_q_net: std_logic;
260 
  signal tx_en_in60_q_net: std_logic_vector(31 downto 0);
261 
  signal tx_en_in61_q_net: std_logic;
262 
  signal tx_en_in65_q_net: std_logic_vector(31 downto 0);
263 
  signal tx_en_in67_q_net: std_logic;
264 
  signal tx_en_in6_q_net: std_logic_vector(31 downto 0);
265 
  signal tx_en_in86_q_net: std_logic;
266 
  signal tx_en_in87_q_net: std_logic_vector(31 downto 0);
267 
  signal tx_en_in89_q_net: std_logic;
268 
  signal tx_en_in8_q_net: std_logic;
269 
  signal tx_en_in90_q_net: std_logic_vector(31 downto 0);
270 
  signal tx_en_in92_q_net: std_logic;
271 
  signal tx_en_in93_q_net: std_logic_vector(31 downto 0);
272 
  signal user_int_1o_net: std_logic;
273 
  signal user_int_2o_net: std_logic;
274 
  signal user_int_3o_net: std_logic;
275 
 
276 
begin
277 
  bram_rd_dout_net <= bram_rd_dout;
278 
  ce_1_sg_x0 <= ce_1;
279 
  clk_1_sg_x0 <= clk_1;
280 
  data_out_net <= data_out;
281 
  data_out_x0_net <= data_out_x0;
282 
  data_out_x1_net <= data_out_x1;
283 
  data_out_x10_net <= data_out_x10;
284 
  data_out_x11_net <= data_out_x11;
285 
  data_out_x12_net <= data_out_x12;
286 
  data_out_x13_net <= data_out_x13;
287 
  data_out_x14_net <= data_out_x14;
288 
  data_out_x15_net <= data_out_x15;
289 
  data_out_x16_net <= data_out_x16;
290 
  data_out_x17_net <= data_out_x17;
291 
  data_out_x18_net <= data_out_x18;
292 
  data_out_x19_net <= data_out_x19;
293 
  data_out_x2_net <= data_out_x2;
294 
  data_out_x20_net <= data_out_x20;
295 
  data_out_x21_net <= data_out_x21;
296 
  data_out_x22_net <= data_out_x22;
297 
  data_out_x23_net <= data_out_x23;
298 
  data_out_x24_net <= data_out_x24;
299 
  data_out_x25_net <= data_out_x25;
300 
  data_out_x26_net <= data_out_x26;
301 
  data_out_x27_net <= data_out_x27;
302 
  data_out_x28_net <= data_out_x28;
303 
  data_out_x3_net <= data_out_x3;
304 
  data_out_x6_net <= data_out_x6;
305 
  data_out_x7_net <= data_out_x7;
306 
  data_out_x8_net <= data_out_x8;
307 
  data_out_x9_net <= data_out_x9;
308 
  fifo_rd_count_net <= fifo_rd_count;
309 
  fifo_rd_dout_net <= fifo_rd_dout;
310 
  fifo_rd_empty_net <= fifo_rd_empty;
311 
  fifo_rd_pempty_net <= fifo_rd_pempty;
312 
  fifo_rd_valid_net <= fifo_rd_valid;
313 
  fifo_wr_count_net <= fifo_wr_count;
314 
  fifo_wr_full_net <= fifo_wr_full;
315 
  fifo_wr_pfull_net <= fifo_wr_pfull;
316 
  rst_i_net <= rst_i;
317 
  bram_rd_addr <= bram_rd_addr_net;
318 
  bram_wr_addr <= bram_wr_addr_net;
319 
  bram_wr_din <= bram_wr_din_net;
320 
  bram_wr_en <= bram_wr_en_net;
321 
  data_in <= data_in_net;
322 
  data_in_x0 <= data_in_x0_net;
323 
  data_in_x1 <= data_in_x1_net;
324 
  data_in_x10 <= data_in_x10_net;
325 
  data_in_x11 <= data_in_x11_net;
326 
  data_in_x12 <= data_in_x12_net;
327 
  data_in_x13 <= data_in_x13_net;
328 
  data_in_x14 <= data_in_x14_net;
329 
  data_in_x15 <= data_in_x15_net;
330 
  data_in_x16 <= data_in_x16_net;
331 
  data_in_x17 <= data_in_x17_net;
332 
  data_in_x18 <= data_in_x18_net;
333 
  data_in_x19 <= data_in_x19_net;
334 
  data_in_x2 <= data_in_x2_net;
335 
  data_in_x20 <= data_in_x20_net;
336 
  data_in_x21 <= data_in_x21_net;
337 
  data_in_x22 <= data_in_x22_net;
338 
  data_in_x23 <= data_in_x23_net;
339 
  data_in_x24 <= data_in_x24_net;
340 
  data_in_x25 <= data_in_x25_net;
341 
  data_in_x26 <= data_in_x26_net;
342 
  data_in_x3 <= data_in_x3_net;
343 
  data_in_x4 <= data_in_x4_net;
344 
  data_in_x5 <= data_in_x5_net;
345 
  data_in_x6 <= data_in_x6_net;
346 
  data_in_x7 <= data_in_x7_net;
347 
  data_in_x8 <= data_in_x8_net;
348 
  data_in_x9 <= data_in_x9_net;
349 
  en <= constant6_op_net_x0;
350 
  en_x0 <= constant6_op_net_x0;
351 
  en_x1 <= constant6_op_net_x0;
352 
  en_x10 <= constant6_op_net_x0;
353 
  en_x11 <= constant6_op_net_x0;
354 
  en_x12 <= constant6_op_net_x0;
355 
  en_x13 <= constant6_op_net_x0;
356 
  en_x14 <= constant6_op_net_x0;
357 
  en_x15 <= constant6_op_net_x0;
358 
  en_x16 <= constant6_op_net_x0;
359 
  en_x17 <= constant6_op_net_x0;
360 
  en_x18 <= constant6_op_net_x0;
361 
  en_x19 <= constant6_op_net_x0;
362 
  en_x2 <= constant6_op_net_x0;
363 
  en_x20 <= constant6_op_net_x0;
364 
  en_x21 <= constant6_op_net_x0;
365 
  en_x22 <= constant6_op_net_x0;
366 
  en_x23 <= constant6_op_net_x0;
367 
  en_x24 <= constant6_op_net_x0;
368 
  en_x25 <= constant6_op_net_x0;
369 
  en_x26 <= constant6_op_net_x0;
370 
  en_x3 <= constant6_op_net_x0;
371 
  en_x4 <= constant6_op_net_x0;
372 
  en_x5 <= constant6_op_net_x0;
373 
  en_x6 <= constant6_op_net_x0;
374 
  en_x7 <= constant6_op_net_x0;
375 
  en_x8 <= constant6_op_net_x0;
376 
  en_x9 <= constant6_op_net_x0;
377 
  fifo_rd_en <= fifo_rd_en_net;
378 
  fifo_wr_din <= fifo_wr_din_net;
379 
  fifo_wr_en <= fifo_wr_en_net;
380 
  rst_o <= rst_o_net;
381 
  user_int_1o <= user_int_1o_net;
382 
  user_int_2o <= user_int_2o_net;
383 
  user_int_3o <= user_int_3o_net;
384 
 
385 
  constant1: entity work.constant_963ed6358a
386 
    port map (
387 
      ce => '0',
388 
      clk => '0',
389 
      clr => '0',
390 
      op(0) => constant1_op_net
391 
    );
392 
 
393 
  constant10: entity work.constant_963ed6358a
394 
    port map (
395 
      ce => '0',
396 
      clk => '0',
397 
      clr => '0',
398 
      op(0) => constant10_op_net
399 
    );
400 
 
401 
  constant11: entity work.constant_963ed6358a
402 
    port map (
403 
      ce => '0',
404 
      clk => '0',
405 
      clr => '0',
406 
      op(0) => constant11_op_net
407 
    );
408 
 
409 
  constant12: entity work.constant_963ed6358a
410 
    port map (
411 
      ce => '0',
412 
      clk => '0',
413 
      clr => '0',
414 
      op(0) => constant12_op_net
415 
    );
416 
 
417 
  constant14: entity work.constant_6293007044
418 
    port map (
419 
      ce => '0',
420 
      clk => '0',
421 
      clr => '0',
422 
      op(0) => constant14_op_net
423 
    );
424 
 
425 
  constant15: entity work.constant_6293007044
426 
    port map (
427 
      ce => '0',
428 
      clk => '0',
429 
      clr => '0',
430 
      op(0) => constant15_op_net
431 
    );
432 
 
433 
  constant19: entity work.constant_963ed6358a
434 
    port map (
435 
      ce => '0',
436 
      clk => '0',
437 
      clr => '0',
438 
      op(0) => constant19_op_net
439 
    );
440 
 
441 
  constant2: entity work.constant_19562ab42f
442 
    port map (
443 
      ce => '0',
444 
      clk => '0',
445 
      clr => '0',
446 
      op => constant2_op_net
447 
    );
448 
 
449 
  constant20: entity work.constant_963ed6358a
450 
    port map (
451 
      ce => '0',
452 
      clk => '0',
453 
      clr => '0',
454 
      op(0) => constant20_op_net
455 
    );
456 
 
457 
  constant21: entity work.constant_963ed6358a
458 
    port map (
459 
      ce => '0',
460 
      clk => '0',
461 
      clr => '0',
462 
      op(0) => constant21_op_net
463 
    );
464 
 
465 
  constant22: entity work.constant_963ed6358a
466 
    port map (
467 
      ce => '0',
468 
      clk => '0',
469 
      clr => '0',
470 
      op(0) => constant22_op_net
471 
    );
472 
 
473 
  constant23: entity work.constant_963ed6358a
474 
    port map (
475 
      ce => '0',
476 
      clk => '0',
477 
      clr => '0',
478 
      op(0) => constant23_op_net
479 
    );
480 
 
481 
  constant24: entity work.constant_963ed6358a
482 
    port map (
483 
      ce => '0',
484 
      clk => '0',
485 
      clr => '0',
486 
      op(0) => constant24_op_net
487 
    );
488 
 
489 
  constant25: entity work.constant_963ed6358a
490 
    port map (
491 
      ce => '0',
492 
      clk => '0',
493 
      clr => '0',
494 
      op(0) => constant25_op_net
495 
    );
496 
 
497 
  constant26: entity work.constant_963ed6358a
498 
    port map (
499 
      ce => '0',
500 
      clk => '0',
501 
      clr => '0',
502 
      op(0) => constant26_op_net
503 
    );
504 
 
505 
  constant3: entity work.constant_963ed6358a
506 
    port map (
507 
      ce => '0',
508 
      clk => '0',
509 
      clr => '0',
510 
      op(0) => constant3_op_net
511 
    );
512 
 
513 
  constant4: entity work.constant_963ed6358a
514 
    port map (
515 
      ce => '0',
516 
      clk => '0',
517 
      clr => '0',
518 
      op(0) => constant4_op_net
519 
    );
520 
 
521 
  constant6: entity work.constant_6293007044
522 
    port map (
523 
      ce => '0',
524 
      clk => '0',
525 
      clr => '0',
526 
      op(0) => constant6_op_net_x0
527 
    );
528 
 
529 
  constant7: entity work.constant_963ed6358a
530 
    port map (
531 
      ce => '0',
532 
      clk => '0',
533 
      clr => '0',
534 
      op(0) => constant7_op_net
535 
    );
536 
 
537 
  constant8: entity work.constant_963ed6358a
538 
    port map (
539 
      ce => '0',
540 
      clk => '0',
541 
      clr => '0',
542 
      op(0) => constant8_op_net
543 
    );
544 
 
545 
  constant9: entity work.constant_963ed6358a
546 
    port map (
547 
      ce => '0',
548 
      clk => '0',
549 
      clr => '0',
550 
      op(0) => constant9_op_net
551 
    );
552 
 
553 
  convert1: entity work.xlconvert
554 
    generic map (
555 
      bool_conversion => 1,
556 
      din_arith => 1,
557 
      din_bin_pt => 0,
558 
      din_width => 1,
559 
      dout_arith => 1,
560 
      dout_bin_pt => 0,
561 
      dout_width => 1,
562 
      latency => 0,
563 
      overflow => xlWrap,
564 
      quantization => xlTruncate
565 
    )
566 
    port map (
567 
      ce => ce_1_sg_x0,
568 
      clk => clk_1_sg_x0,
569 
      clr => '0',
570 
      din(0) => tx_en_in5_q_net,
571 
      en => "1",
572 
      dout(0) => convert1_dout_net
573 
    );
574 
 
575 
  convert11: entity work.xlconvert
576 
    generic map (
577 
      bool_conversion => 1,
578 
      din_arith => 1,
579 
      din_bin_pt => 0,
580 
      din_width => 1,
581 
      dout_arith => 1,
582 
      dout_bin_pt => 0,
583 
      dout_width => 1,
584 
      latency => 0,
585 
      overflow => xlWrap,
586 
      quantization => xlTruncate
587 
    )
588 
    port map (
589 
      ce => ce_1_sg_x0,
590 
      clk => clk_1_sg_x0,
591 
      clr => '0',
592 
      din(0) => tx_en_in89_q_net,
593 
      en => "1",
594 
      dout(0) => convert11_dout_net
595 
    );
596 
 
597 
  convert12: entity work.xlconvert
598 
    generic map (
599 
      bool_conversion => 1,
600 
      din_arith => 1,
601 
      din_bin_pt => 0,
602 
      din_width => 1,
603 
      dout_arith => 1,
604 
      dout_bin_pt => 0,
605 
      dout_width => 1,
606 
      latency => 0,
607 
      overflow => xlWrap,
608 
      quantization => xlTruncate
609 
    )
610 
    port map (
611 
      ce => ce_1_sg_x0,
612 
      clk => clk_1_sg_x0,
613 
      clr => '0',
614 
      din(0) => tx_en_in92_q_net,
615 
      en => "1",
616 
      dout(0) => convert12_dout_net
617 
    );
618 
 
619 
  convert14: entity work.xlconvert
620 
    generic map (
621 
      bool_conversion => 1,
622 
      din_arith => 1,
623 
      din_bin_pt => 0,
624 
      din_width => 1,
625 
      dout_arith => 1,
626 
      dout_bin_pt => 0,
627 
      dout_width => 1,
628 
      latency => 0,
629 
      overflow => xlWrap,
630 
      quantization => xlTruncate
631 
    )
632 
    port map (
633 
      ce => ce_1_sg_x0,
634 
      clk => clk_1_sg_x0,
635 
      clr => '0',
636 
      din(0) => tx_en_in116_q_net,
637 
      en => "1",
638 
      dout(0) => convert14_dout_net
639 
    );
640 
 
641 
  convert15: entity work.xlconvert
642 
    generic map (
643 
      bool_conversion => 1,
644 
      din_arith => 1,
645 
      din_bin_pt => 0,
646 
      din_width => 1,
647 
      dout_arith => 1,
648 
      dout_bin_pt => 0,
649 
      dout_width => 1,
650 
      latency => 0,
651 
      overflow => xlWrap,
652 
      quantization => xlTruncate
653 
    )
654 
    port map (
655 
      ce => ce_1_sg_x0,
656 
      clk => clk_1_sg_x0,
657 
      clr => '0',
658 
      din(0) => tx_en_in119_q_net,
659 
      en => "1",
660 
      dout(0) => convert15_dout_net
661 
    );
662 
 
663 
  convert16: entity work.xlconvert
664 
    generic map (
665 
      bool_conversion => 1,
666 
      din_arith => 1,
667 
      din_bin_pt => 0,
668 
      din_width => 1,
669 
      dout_arith => 1,
670 
      dout_bin_pt => 0,
671 
      dout_width => 1,
672 
      latency => 0,
673 
      overflow => xlWrap,
674 
      quantization => xlTruncate
675 
    )
676 
    port map (
677 
      ce => ce_1_sg_x0,
678 
      clk => clk_1_sg_x0,
679 
      clr => '0',
680 
      din(0) => tx_en_in123_q_net,
681 
      en => "1",
682 
      dout(0) => convert16_dout_net
683 
    );
684 
 
685 
  convert17: entity work.xlconvert
686 
    generic map (
687 
      bool_conversion => 1,
688 
      din_arith => 1,
689 
      din_bin_pt => 0,
690 
      din_width => 1,
691 
      dout_arith => 1,
692 
      dout_bin_pt => 0,
693 
      dout_width => 1,
694 
      latency => 0,
695 
      overflow => xlWrap,
696 
      quantization => xlTruncate
697 
    )
698 
    port map (
699 
      ce => ce_1_sg_x0,
700 
      clk => clk_1_sg_x0,
701 
      clr => '0',
702 
      din(0) => tx_en_in127_q_net,
703 
      en => "1",
704 
      dout(0) => convert17_dout_net
705 
    );
706 
 
707 
  convert3: entity work.xlconvert
708 
    generic map (
709 
      bool_conversion => 1,
710 
      din_arith => 1,
711 
      din_bin_pt => 0,
712 
      din_width => 1,
713 
      dout_arith => 1,
714 
      dout_bin_pt => 0,
715 
      dout_width => 1,
716 
      latency => 0,
717 
      overflow => xlWrap,
718 
      quantization => xlTruncate
719 
    )
720 
    port map (
721 
      ce => ce_1_sg_x0,
722 
      clk => clk_1_sg_x0,
723 
      clr => '0',
724 
      din(0) => tx_en_in4_q_net,
725 
      en => "1",
726 
      dout(0) => timecountreset
727 
    );
728 
 
729 
  convert4: entity work.xlconvert
730 
    generic map (
731 
      bool_conversion => 1,
732 
      din_arith => 1,
733 
      din_bin_pt => 0,
734 
      din_width => 1,
735 
      dout_arith => 1,
736 
      dout_bin_pt => 0,
737 
      dout_width => 1,
738 
      latency => 0,
739 
      overflow => xlWrap,
740 
      quantization => xlTruncate
741 
    )
742 
    port map (
743 
      ce => ce_1_sg_x0,
744 
      clk => clk_1_sg_x0,
745 
      clr => '0',
746 
      din(0) => tx_en_in86_q_net,
747 
      en => "1",
748 
      dout(0) => convert4_dout_net
749 
    );
750 
 
751 
  convert5: entity work.xlconvert
752 
    generic map (
753 
      bool_conversion => 1,
754 
      din_arith => 1,
755 
      din_bin_pt => 0,
756 
      din_width => 1,
757 
      dout_arith => 1,
758 
      dout_bin_pt => 0,
759 
      dout_width => 1,
760 
      latency => 0,
761 
      overflow => xlWrap,
762 
      quantization => xlTruncate
763 
    )
764 
    port map (
765 
      ce => ce_1_sg_x0,
766 
      clk => clk_1_sg_x0,
767 
      clr => '0',
768 
      din(0) => tx_en_in58_q_net,
769 
      en => "1",
770 
      dout(0) => convert5_dout_net
771 
    );
772 
 
773 
  convert6: entity work.xlconvert
774 
    generic map (
775 
      bool_conversion => 1,
776 
      din_arith => 1,
777 
      din_bin_pt => 0,
778 
      din_width => 1,
779 
      dout_arith => 1,
780 
      dout_bin_pt => 0,
781 
      dout_width => 1,
782 
      latency => 0,
783 
      overflow => xlWrap,
784 
      quantization => xlTruncate
785 
    )
786 
    port map (
787 
      ce => ce_1_sg_x0,
788 
      clk => clk_1_sg_x0,
789 
      clr => '0',
790 
      din(0) => tx_en_in59_q_net,
791 
      en => "1",
792 
      dout(0) => convert6_dout_net
793 
    );
794 
 
795 
  convert7: entity work.xlconvert
796 
    generic map (
797 
      bool_conversion => 1,
798 
      din_arith => 1,
799 
      din_bin_pt => 0,
800 
      din_width => 1,
801 
      dout_arith => 1,
802 
      dout_bin_pt => 0,
803 
      dout_width => 1,
804 
      latency => 0,
805 
      overflow => xlWrap,
806 
      quantization => xlTruncate
807 
    )
808 
    port map (
809 
      ce => ce_1_sg_x0,
810 
      clk => clk_1_sg_x0,
811 
      clr => '0',
812 
      din(0) => tx_en_in61_q_net,
813 
      en => "1",
814 
      dout(0) => convert7_dout_net
815 
    );
816 
 
817 
  convert8: entity work.xlconvert
818 
    generic map (
819 
      bool_conversion => 1,
820 
      din_arith => 1,
821 
      din_bin_pt => 0,
822 
      din_width => 1,
823 
      dout_arith => 1,
824 
      dout_bin_pt => 0,
825 
      dout_width => 1,
826 
      latency => 0,
827 
      overflow => xlWrap,
828 
      quantization => xlTruncate
829 
    )
830 
    port map (
831 
      ce => ce_1_sg_x0,
832 
      clk => clk_1_sg_x0,
833 
      clr => '0',
834 
      din(0) => tx_en_in67_q_net,
835 
      en => "1",
836 
      dout(0) => convert8_dout_net
837 
    );
838 
 
839 
  convert9: entity work.xlconvert
840 
    generic map (
841 
      bool_conversion => 1,
842 
      din_arith => 1,
843 
      din_bin_pt => 0,
844 
      din_width => 1,
845 
      dout_arith => 1,
846 
      dout_bin_pt => 0,
847 
      dout_width => 1,
848 
      latency => 0,
849 
      overflow => xlWrap,
850 
      quantization => xlTruncate
851 
    )
852 
    port map (
853 
      ce => ce_1_sg_x0,
854 
      clk => clk_1_sg_x0,
855 
      clr => '0',
856 
      din(0) => tx_en_in8_q_net,
857 
      en => "1",
858 
      dout(0) => timecounttrigger
859 
    );
860 
 
861 
  counter4: entity work.xlcounter_free
862 
    generic map (
863 
      core_name0 => "cntr_11_0_1a411d6ef586e892",
864 
      op_arith => xlUnsigned,
865 
      op_width => 12
866 
    )
867 
    port map (
868 
      ce => ce_1_sg_x0,
869 
      clk => clk_1_sg_x0,
870 
      clr => '0',
871 
      en => "1",
872 
      rst => "0",
873 
      op => counter4_op_net
874 
    );
875 
 
876 
  inverter3: entity work.inverter_e5b38cca3b
877 
    port map (
878 
      ce => ce_1_sg_x0,
879 
      clk => clk_1_sg_x0,
880 
      clr => '0',
881 
      ip(0) => rst_i_net,
882 
      op(0) => inverter3_op_net
883 
    );
884 
 
885 
  inverter5: entity work.inverter_e5b38cca3b
886 
    port map (
887 
      ce => ce_1_sg_x0,
888 
      clk => clk_1_sg_x0,
889 
      clr => '0',
890 
      ip(0) => tx_en_in107_q_net,
891 
      op(0) => inverter5_op_net
892 
    );
893 
 
894 
  logical4: entity work.logical_80f90b97d0
895 
    port map (
896 
      ce => '0',
897 
      clk => '0',
898 
      clr => '0',
899 
      d0(0) => constant15_op_net,
900 
      d1(0) => inverter5_op_net,
901 
      y(0) => logical4_y_net
902 
    );
903 
 
904 
  tx_en_in1: entity work.xlregister
905 
    generic map (
906 
      d_width => 1,
907 
      init_value => b"0"
908 
    )
909 
    port map (
910 
      ce => ce_1_sg_x0,
911 
      clk => clk_1_sg_x0,
912 
      d(0) => timecountreset,
913 
      en => "1",
914 
      rst => "0",
915 
      q(0) => data_in_x0_net
916 
    );
917 
 
918 
  tx_en_in10: entity work.xlregister
919 
    generic map (
920 
      d_width => 32,
921 
      init_value => b"00000000000000000000000000000000"
922 
    )
923 
    port map (
924 
      ce => ce_1_sg_x0,
925 
      clk => clk_1_sg_x0,
926 
      d => tx_en_in12_q_net,
927 
      en(0) => timecounttrigger,
928 
      rst(0) => constant3_op_net,
929 
      q => data_in_x20_net
930 
    );
931 
 
932 
  tx_en_in100: entity work.xlregister
933 
    generic map (
934 
      d_width => 1,
935 
      init_value => b"0"
936 
    )
937 
    port map (
938 
      ce => ce_1_sg_x0,
939 
      clk => clk_1_sg_x0,
940 
      d(0) => convert12_dout_net,
941 
      en => "1",
942 
      rst => "0",
943 
      q(0) => data_in_x9_net
944 
    );
945 
 
946 
  tx_en_in105: entity work.xlregister
947 
    generic map (
948 
      d_width => 1,
949 
      init_value => b"0"
950 
    )
951 
    port map (
952 
      ce => ce_1_sg_x0,
953 
      clk => clk_1_sg_x0,
954 
      d(0) => fifo_rd_empty_net,
955 
      en => "1",
956 
      rst => "0",
957 
      q(0) => tx_en_in105_q_net
958 
    );
959 
 
960 
  tx_en_in107: entity work.xlregister
961 
    generic map (
962 
      d_width => 1,
963 
      init_value => b"0"
964 
    )
965 
    port map (
966 
      ce => ce_1_sg_x0,
967 
      clk => clk_1_sg_x0,
968 
      d(0) => tx_en_in105_q_net,
969 
      en => "1",
970 
      rst => "0",
971 
      q(0) => tx_en_in107_q_net
972 
    );
973 
 
974 
  tx_en_in108: entity work.xlregister
975 
    generic map (
976 
      d_width => 1,
977 
      init_value => b"0"
978 
    )
979 
    port map (
980 
      ce => ce_1_sg_x0,
981 
      clk => clk_1_sg_x0,
982 
      d(0) => logical4_y_net,
983 
      en(0) => constant14_op_net,
984 
      rst => "0",
985 
      q(0) => fifo_rd_en_net
986 
    );
987 
 
988 
  tx_en_in109: entity work.xlregister
989 
    generic map (
990 
      d_width => 1,
991 
      init_value => b"0"
992 
    )
993 
    port map (
994 
      ce => ce_1_sg_x0,
995 
      clk => clk_1_sg_x0,
996 
      d(0) => fifo_rd_valid_net,
997 
      en => "1",
998 
      rst => "0",
999 
      q(0) => fifo_wr_en_net
1000 
    );
1001 
 
1002 
  tx_en_in113: entity work.xlregister
1003 
    generic map (
1004 
      d_width => 1,
1005 
      init_value => b"0"
1006 
    )
1007 
    port map (
1008 
      ce => ce_1_sg_x0,
1009 
      clk => clk_1_sg_x0,
1010 
      d(0) => convert14_dout_net,
1011 
      en => "1",
1012 
      rst => "0",
1013 
      q(0) => data_in_x12_net
1014 
    );
1015 
 
1016 
  tx_en_in114: entity work.xlregister
1017 
    generic map (
1018 
      d_width => 1,
1019 
      init_value => b"0"
1020 
    )
1021 
    port map (
1022 
      ce => ce_1_sg_x0,
1023 
      clk => clk_1_sg_x0,
1024 
      d(0) => convert15_dout_net,
1025 
      en => "1",
1026 
      rst => "0",
1027 
      q(0) => data_in_x14_net
1028 
    );
1029 
 
1030 
  tx_en_in115: entity work.xlregister
1031 
    generic map (
1032 
      d_width => 32,
1033 
      init_value => b"00000000000000110000110100100011"
1034 
    )
1035 
    port map (
1036 
      ce => ce_1_sg_x0,
1037 
      clk => clk_1_sg_x0,
1038 
      d => tx_en_in117_q_net,
1039 
      en(0) => convert14_dout_net,
1040 
      rst(0) => constant19_op_net,
1041 
      q => data_in_x13_net
1042 
    );
1043 
 
1044 
  tx_en_in116: entity work.xlregister
1045 
    generic map (
1046 
      d_width => 1,
1047 
      init_value => b"0"
1048 
    )
1049 
    port map (
1050 
      ce => ce_1_sg_x0,
1051 
      clk => clk_1_sg_x0,
1052 
      d(0) => data_out_x15_net,
1053 
      en => "1",
1054 
      rst => "0",
1055 
      q(0) => tx_en_in116_q_net
1056 
    );
1057 
 
1058 
  tx_en_in117: entity work.xlregister
1059 
    generic map (
1060 
      d_width => 32,
1061 
      init_value => b"00000000000000000000000000000000"
1062 
    )
1063 
    port map (
1064 
      ce => ce_1_sg_x0,
1065 
      clk => clk_1_sg_x0,
1066 
      d => data_out_x14_net,
1067 
      en => "1",
1068 
      rst => "0",
1069 
      q => tx_en_in117_q_net
1070 
    );
1071 
 
1072 
  tx_en_in118: entity work.xlregister
1073 
    generic map (
1074 
      d_width => 32,
1075 
      init_value => b"00000000000000000100101011000000"
1076 
    )
1077 
    port map (
1078 
      ce => ce_1_sg_x0,
1079 
      clk => clk_1_sg_x0,
1080 
      d => tx_en_in120_q_net,
1081 
      en(0) => convert15_dout_net,
1082 
      rst(0) => constant21_op_net,
1083 
      q => data_in_x15_net
1084 
    );
1085 
 
1086 
  tx_en_in119: entity work.xlregister
1087 
    generic map (
1088 
      d_width => 1,
1089 
      init_value => b"0"
1090 
    )
1091 
    port map (
1092 
      ce => ce_1_sg_x0,
1093 
      clk => clk_1_sg_x0,
1094 
      d(0) => data_out_x17_net,
1095 
      en => "1",
1096 
      rst => "0",
1097 
      q(0) => tx_en_in119_q_net
1098 
    );
1099 
 
1100 
  tx_en_in12: entity work.xlregister
1101 
    generic map (
1102 
      d_width => 32,
1103 
      init_value => b"00000000000000000000000000000000"
1104 
    )
1105 
    port map (
1106 
      ce => ce_1_sg_x0,
1107 
      clk => clk_1_sg_x0,
1108 
      d => data_out_x26_net,
1109 
      en => "1",
1110 
      rst => "0",
1111 
      q => tx_en_in12_q_net
1112 
    );
1113 
 
1114 
  tx_en_in120: entity work.xlregister
1115 
    generic map (
1116 
      d_width => 32,
1117 
      init_value => b"00000000000000000000000000000000"
1118 
    )
1119 
    port map (
1120 
      ce => ce_1_sg_x0,
1121 
      clk => clk_1_sg_x0,
1122 
      d => data_out_x16_net,
1123 
      en => "1",
1124 
      rst => "0",
1125 
      q => tx_en_in120_q_net
1126 
    );
1127 
 
1128 
  tx_en_in121: entity work.xlregister
1129 
    generic map (
1130 
      d_width => 1,
1131 
      init_value => b"0"
1132 
    )
1133 
    port map (
1134 
      ce => ce_1_sg_x0,
1135 
      clk => clk_1_sg_x0,
1136 
      d(0) => convert16_dout_net,
1137 
      en => "1",
1138 
      rst => "0",
1139 
      q(0) => data_in_x16_net
1140 
    );
1141 
 
1142 
  tx_en_in122: entity work.xlregister
1143 
    generic map (
1144 
      d_width => 32,
1145 
      init_value => b"00000000000000000000000000000000"
1146 
    )
1147 
    port map (
1148 
      ce => ce_1_sg_x0,
1149 
      clk => clk_1_sg_x0,
1150 
      d => tx_en_in124_q_net,
1151 
      en(0) => convert16_dout_net,
1152 
      rst(0) => constant22_op_net,
1153 
      q => data_in_x17_net
1154 
    );
1155 
 
1156 
  tx_en_in123: entity work.xlregister
1157 
    generic map (
1158 
      d_width => 1,
1159 
      init_value => b"0"
1160 
    )
1161 
    port map (
1162 
      ce => ce_1_sg_x0,
1163 
      clk => clk_1_sg_x0,
1164 
      d(0) => data_out_x20_net,
1165 
      en => "1",
1166 
      rst => "0",
1167 
      q(0) => tx_en_in123_q_net
1168 
    );
1169 
 
1170 
  tx_en_in124: entity work.xlregister
1171 
    generic map (
1172 
      d_width => 32,
1173 
      init_value => b"00000000000000000000000000000000"
1174 
    )
1175 
    port map (
1176 
      ce => ce_1_sg_x0,
1177 
      clk => clk_1_sg_x0,
1178 
      d => data_out_x19_net,
1179 
      en => "1",
1180 
      rst => "0",
1181 
      q => tx_en_in124_q_net
1182 
    );
1183 
 
1184 
  tx_en_in125: entity work.xlregister
1185 
    generic map (
1186 
      d_width => 1,
1187 
      init_value => b"0"
1188 
    )
1189 
    port map (
1190 
      ce => ce_1_sg_x0,
1191 
      clk => clk_1_sg_x0,
1192 
      d(0) => convert17_dout_net,
1193 
      en => "1",
1194 
      rst => "0",
1195 
      q(0) => data_in_x18_net
1196 
    );
1197 
 
1198 
  tx_en_in126: entity work.xlregister
1199 
    generic map (
1200 
      d_width => 32,
1201 
      init_value => b"00000000000000000000000000000000"
1202 
    )
1203 
    port map (
1204 
      ce => ce_1_sg_x0,
1205 
      clk => clk_1_sg_x0,
1206 
      d => tx_en_in128_q_net,
1207 
      en(0) => convert17_dout_net,
1208 
      rst(0) => constant23_op_net,
1209 
      q => data_in_x19_net
1210 
    );
1211 
 
1212 
  tx_en_in127: entity work.xlregister
1213 
    generic map (
1214 
      d_width => 1,
1215 
      init_value => b"0"
1216 
    )
1217 
    port map (
1218 
      ce => ce_1_sg_x0,
1219 
      clk => clk_1_sg_x0,
1220 
      d(0) => data_out_x22_net,
1221 
      en => "1",
1222 
      rst => "0",
1223 
      q(0) => tx_en_in127_q_net
1224 
    );
1225 
 
1226 
  tx_en_in128: entity work.xlregister
1227 
    generic map (
1228 
      d_width => 32,
1229 
      init_value => b"00000000000000000000000000000000"
1230 
    )
1231 
    port map (
1232 
      ce => ce_1_sg_x0,
1233 
      clk => clk_1_sg_x0,
1234 
      d => data_out_x21_net,
1235 
      en => "1",
1236 
      rst => "0",
1237 
      q => tx_en_in128_q_net
1238 
    );
1239 
 
1240 
  tx_en_in13: entity work.xlregister
1241 
    generic map (
1242 
      d_width => 1,
1243 
      init_value => b"0"
1244 
    )
1245 
    port map (
1246 
      ce => ce_1_sg_x0,
1247 
      clk => clk_1_sg_x0,
1248 
      d(0) => convert8_dout_net,
1249 
      en => "1",
1250 
      rst => "0",
1251 
      q(0) => data_in_x3_net
1252 
    );
1253 
 
1254 
  tx_en_in15: entity work.xlregister
1255 
    generic map (
1256 
      d_width => 12,
1257 
      init_value => b"000000000000"
1258 
    )
1259 
    port map (
1260 
      ce => ce_1_sg_x0,
1261 
      clk => clk_1_sg_x0,
1262 
      d => counter4_op_net,
1263 
      en => "1",
1264 
      rst => "0",
1265 
      q => bram_rd_addr_net
1266 
    );
1267 
 
1268 
  tx_en_in16: entity work.xlregister
1269 
    generic map (
1270 
      d_width => 12,
1271 
      init_value => b"000000000000"
1272 
    )
1273 
    port map (
1274 
      ce => ce_1_sg_x0,
1275 
      clk => clk_1_sg_x0,
1276 
      d => tx_en_in30_q_net,
1277 
      en => "1",
1278 
      rst => "0",
1279 
      q => tx_en_in16_q_net
1280 
    );
1281 
 
1282 
  tx_en_in17: entity work.xlregister
1283 
    generic map (
1284 
      d_width => 12,
1285 
      init_value => b"000000000000"
1286 
    )
1287 
    port map (
1288 
      ce => ce_1_sg_x0,
1289 
      clk => clk_1_sg_x0,
1290 
      d => counter4_op_net,
1291 
      en => "1",
1292 
      rst => "0",
1293 
      q => tx_en_in17_q_net
1294 
    );
1295 
 
1296 
  tx_en_in18: entity work.xlregister
1297 
    generic map (
1298 
      d_width => 8,
1299 
      init_value => b"00000000"
1300 
    )
1301 
    port map (
1302 
      ce => ce_1_sg_x0,
1303 
      clk => clk_1_sg_x0,
1304 
      d => constant2_op_net,
1305 
      en => "1",
1306 
      rst => "0",
1307 
      q => tx_en_in18_q_net
1308 
    );
1309 
 
1310 
  tx_en_in19: entity work.xlregister
1311 
    generic map (
1312 
      d_width => 12,
1313 
      init_value => b"000000000000"
1314 
    )
1315 
    port map (
1316 
      ce => ce_1_sg_x0,
1317 
      clk => clk_1_sg_x0,
1318 
      d => tx_en_in16_q_net,
1319 
      en => "1",
1320 
      rst => "0",
1321 
      q => bram_wr_addr_net
1322 
    );
1323 
 
1324 
  tx_en_in2: entity work.xlregister
1325 
    generic map (
1326 
      d_width => 32,
1327 
      init_value => b"00000000000000000000000000000000"
1328 
    )
1329 
    port map (
1330 
      ce => ce_1_sg_x0,
1331 
      clk => clk_1_sg_x0,
1332 
      d => dinb_x0,
1333 
      en(0) => timecountreset,
1334 
      rst(0) => constant1_op_net,
1335 
      q => data_in_net
1336 
    );
1337 
 
1338 
  tx_en_in20: entity work.xlregister
1339 
    generic map (
1340 
      d_width => 64,
1341 
      init_value => b"0000000000000000000000000000000000000000000000000000000000000000"
1342 
    )
1343 
    port map (
1344 
      ce => ce_1_sg_x0,
1345 
      clk => clk_1_sg_x0,
1346 
      d => bram_rd_dout_net,
1347 
      en => "1",
1348 
      rst => "0",
1349 
      q => bram_wr_din_net
1350 
    );
1351 
 
1352 
  tx_en_in26: entity work.xlregister
1353 
    generic map (
1354 
      d_width => 1,
1355 
      init_value => b"0"
1356 
    )
1357 
    port map (
1358 
      ce => ce_1_sg_x0,
1359 
      clk => clk_1_sg_x0,
1360 
      d(0) => inverter3_op_net,
1361 
      en => "1",
1362 
      rst => "0",
1363 
      q(0) => rst_o_net
1364 
    );
1365 
 
1366 
  tx_en_in3: entity work.xlregister
1367 
    generic map (
1368 
      d_width => 1,
1369 
      init_value => b"0"
1370 
    )
1371 
    port map (
1372 
      ce => ce_1_sg_x0,
1373 
      clk => clk_1_sg_x0,
1374 
      d(0) => constant8_op_net,
1375 
      en => "1",
1376 
      rst => "0",
1377 
      q(0) => user_int_1o_net
1378 
    );
1379 
 
1380 
  tx_en_in30: entity work.xlregister
1381 
    generic map (
1382 
      d_width => 12,
1383 
      init_value => b"000000000000"
1384 
    )
1385 
    port map (
1386 
      ce => ce_1_sg_x0,
1387 
      clk => clk_1_sg_x0,
1388 
      d => tx_en_in17_q_net,
1389 
      en => "1",
1390 
      rst => "0",
1391 
      q => tx_en_in30_q_net
1392 
    );
1393 
 
1394 
  tx_en_in33: entity work.xlregister
1395 
    generic map (
1396 
      d_width => 32,
1397 
      init_value => b"00000000000000000000000000000000"
1398 
    )
1399 
    port map (
1400 
      ce => ce_1_sg_x0,
1401 
      clk => clk_1_sg_x0,
1402 
      d => tx_en_in6_q_net,
1403 
      en(0) => convert1_dout_net,
1404 
      rst(0) => constant26_op_net,
1405 
      q => data_in_x11_net
1406 
    );
1407 
 
1408 
  tx_en_in38: entity work.xlregister
1409 
    generic map (
1410 
      d_width => 72,
1411 
      init_value => b"000000000000000000000000000000000000000000000000000000000000000000000000"
1412 
    )
1413 
    port map (
1414 
      ce => ce_1_sg_x0,
1415 
      clk => clk_1_sg_x0,
1416 
      d => fifo_rd_dout_net,
1417 
      en => "1",
1418 
      rst => "0",
1419 
      q => fifo_wr_din_net
1420 
    );
1421 
 
1422 
  tx_en_in4: entity work.xlregister
1423 
    generic map (
1424 
      d_width => 1,
1425 
      init_value => b"0"
1426 
    )
1427 
    port map (
1428 
      ce => ce_1_sg_x0,
1429 
      clk => clk_1_sg_x0,
1430 
      d(0) => data_out_x23_net,
1431 
      en => "1",
1432 
      rst => "0",
1433 
      q(0) => tx_en_in4_q_net
1434 
    );
1435 
 
1436 
  tx_en_in43: entity work.xlregister
1437 
    generic map (
1438 
      d_width => 8,
1439 
      init_value => b"00000000"
1440 
    )
1441 
    port map (
1442 
      ce => ce_1_sg_x0,
1443 
      clk => clk_1_sg_x0,
1444 
      d => tx_en_in18_q_net,
1445 
      en => "1",
1446 
      rst => "0",
1447 
      q => bram_wr_en_net
1448 
    );
1449 
 
1450 
  tx_en_in5: entity work.xlregister
1451 
    generic map (
1452 
      d_width => 1,
1453 
      init_value => b"0"
1454 
    )
1455 
    port map (
1456 
      ce => ce_1_sg_x0,
1457 
      clk => clk_1_sg_x0,
1458 
      d(0) => data_out_x25_net,
1459 
      en => "1",
1460 
      rst => "0",
1461 
      q(0) => tx_en_in5_q_net
1462 
    );
1463 
 
1464 
  tx_en_in50: entity work.xlregister
1465 
    generic map (
1466 
      d_width => 32,
1467 
      init_value => b"00000000000000000000000000000000"
1468 
    )
1469 
    port map (
1470 
      ce => ce_1_sg_x0,
1471 
      clk => clk_1_sg_x0,
1472 
      d => dinb,
1473 
      en(0) => convert5_dout_net,
1474 
      rst(0) => constant25_op_net,
1475 
      q => data_in_x23_net
1476 
    );
1477 
 
1478 
  tx_en_in51: entity work.xlregister
1479 
    generic map (
1480 
      d_width => 1,
1481 
      init_value => b"0"
1482 
    )
1483 
    port map (
1484 
      ce => ce_1_sg_x0,
1485 
      clk => clk_1_sg_x0,
1486 
      d(0) => constant11_op_net,
1487 
      en => "1",
1488 
      rst => "0",
1489 
      q(0) => user_int_3o_net
1490 
    );
1491 
 
1492 
  tx_en_in52: entity work.xlregister
1493 
    generic map (
1494 
      d_width => 32,
1495 
      init_value => b"00000000000000000000000000000000"
1496 
    )
1497 
    port map (
1498 
      ce => ce_1_sg_x0,
1499 
      clk => clk_1_sg_x0,
1500 
      d => data_out_x2_net,
1501 
      en => "1",
1502 
      rst => "0",
1503 
      q => tx_en_in52_q_net
1504 
    );
1505 
 
1506 
  tx_en_in53: entity work.xlregister
1507 
    generic map (
1508 
      d_width => 32,
1509 
      init_value => b"00000000000000000000000000000000"
1510 
    )
1511 
    port map (
1512 
      ce => ce_1_sg_x0,
1513 
      clk => clk_1_sg_x0,
1514 
      d => tx_en_in60_q_net,
1515 
      en(0) => convert6_dout_net,
1516 
      rst(0) => constant24_op_net,
1517 
      q => data_in_x25_net
1518 
    );
1519 
 
1520 
  tx_en_in54: entity work.xlregister
1521 
    generic map (
1522 
      d_width => 32,
1523 
      init_value => b"00000000000000000000000000000000"
1524 
    )
1525 
    port map (
1526 
      ce => ce_1_sg_x0,
1527 
      clk => clk_1_sg_x0,
1528 
      d => tx_en_in52_q_net,
1529 
      en(0) => convert7_dout_net,
1530 
      rst(0) => constant20_op_net,
1531 
      q => data_in_x26_net
1532 
    );
1533 
 
1534 
  tx_en_in58: entity work.xlregister
1535 
    generic map (
1536 
      d_width => 1,
1537 
      init_value => b"0"
1538 
    )
1539 
    port map (
1540 
      ce => ce_1_sg_x0,
1541 
      clk => clk_1_sg_x0,
1542 
      d(0) => data_out_net,
1543 
      en => "1",
1544 
      rst => "0",
1545 
      q(0) => tx_en_in58_q_net
1546 
    );
1547 
 
1548 
  tx_en_in59: entity work.xlregister
1549 
    generic map (
1550 
      d_width => 1,
1551 
      init_value => b"0"
1552 
    )
1553 
    port map (
1554 
      ce => ce_1_sg_x0,
1555 
      clk => clk_1_sg_x0,
1556 
      d(0) => data_out_x1_net,
1557 
      en => "1",
1558 
      rst => "0",
1559 
      q(0) => tx_en_in59_q_net
1560 
    );
1561 
 
1562 
  tx_en_in6: entity work.xlregister
1563 
    generic map (
1564 
      d_width => 32,
1565 
      init_value => b"00000000000000000000000000000000"
1566 
    )
1567 
    port map (
1568 
      ce => ce_1_sg_x0,
1569 
      clk => clk_1_sg_x0,
1570 
      d => data_out_x24_net,
1571 
      en => "1",
1572 
      rst => "0",
1573 
      q => tx_en_in6_q_net
1574 
    );
1575 
 
1576 
  tx_en_in60: entity work.xlregister
1577 
    generic map (
1578 
      d_width => 32,
1579 
      init_value => b"00000000000000000000000000000000"
1580 
    )
1581 
    port map (
1582 
      ce => ce_1_sg_x0,
1583 
      clk => clk_1_sg_x0,
1584 
      d => data_out_x0_net,
1585 
      en => "1",
1586 
      rst => "0",
1587 
      q => tx_en_in60_q_net
1588 
    );
1589 
 
1590 
  tx_en_in61: entity work.xlregister
1591 
    generic map (
1592 
      d_width => 1,
1593 
      init_value => b"0"
1594 
    )
1595 
    port map (
1596 
      ce => ce_1_sg_x0,
1597 
      clk => clk_1_sg_x0,
1598 
      d(0) => data_out_x3_net,
1599 
      en => "1",
1600 
      rst => "0",
1601 
      q(0) => tx_en_in61_q_net
1602 
    );
1603 
 
1604 
  tx_en_in62: entity work.xlregister
1605 
    generic map (
1606 
      d_width => 32,
1607 
      init_value => b"00000000000000000000000000000000"
1608 
    )
1609 
    port map (
1610 
      ce => ce_1_sg_x0,
1611 
      clk => clk_1_sg_x0,
1612 
      d => data_out_x28_net,
1613 
      en => "1",
1614 
      rst => "0",
1615 
      q => dinb
1616 
    );
1617 
 
1618 
  tx_en_in65: entity work.xlregister
1619 
    generic map (
1620 
      d_width => 32,
1621 
      init_value => b"00000000000000000000000000000000"
1622 
    )
1623 
    port map (
1624 
      ce => ce_1_sg_x0,
1625 
      clk => clk_1_sg_x0,
1626 
      d => data_out_x6_net,
1627 
      en => "1",
1628 
      rst => "0",
1629 
      q => tx_en_in65_q_net
1630 
    );
1631 
 
1632 
  tx_en_in66: entity work.xlregister
1633 
    generic map (
1634 
      d_width => 32,
1635 
      init_value => b"00000000000000000000000000000000"
1636 
    )
1637 
    port map (
1638 
      ce => ce_1_sg_x0,
1639 
      clk => clk_1_sg_x0,
1640 
      d => tx_en_in65_q_net,
1641 
      en(0) => convert8_dout_net,
1642 
      rst(0) => constant12_op_net,
1643 
      q => data_in_x4_net
1644 
    );
1645 
 
1646 
  tx_en_in67: entity work.xlregister
1647 
    generic map (
1648 
      d_width => 1,
1649 
      init_value => b"0"
1650 
    )
1651 
    port map (
1652 
      ce => ce_1_sg_x0,
1653 
      clk => clk_1_sg_x0,
1654 
      d(0) => data_out_x7_net,
1655 
      en => "1",
1656 
      rst => "0",
1657 
      q(0) => tx_en_in67_q_net
1658 
    );
1659 
 
1660 
  tx_en_in7: entity work.xlregister
1661 
    generic map (
1662 
      d_width => 1,
1663 
      init_value => b"0"
1664 
    )
1665 
    port map (
1666 
      ce => ce_1_sg_x0,
1667 
      clk => clk_1_sg_x0,
1668 
      d(0) => timecounttrigger,
1669 
      en => "1",
1670 
      rst => "0",
1671 
      q(0) => data_in_x22_net
1672 
    );
1673 
 
1674 
  tx_en_in75: entity work.xlregister
1675 
    generic map (
1676 
      d_width => 1,
1677 
      init_value => b"0"
1678 
    )
1679 
    port map (
1680 
      ce => ce_1_sg_x0,
1681 
      clk => clk_1_sg_x0,
1682 
      d(0) => constant10_op_net,
1683 
      en => "1",
1684 
      rst => "0",
1685 
      q(0) => user_int_2o_net
1686 
    );
1687 
 
1688 
  tx_en_in8: entity work.xlregister
1689 
    generic map (
1690 
      d_width => 1,
1691 
      init_value => b"0"
1692 
    )
1693 
    port map (
1694 
      ce => ce_1_sg_x0,
1695 
      clk => clk_1_sg_x0,
1696 
      d(0) => data_out_x27_net,
1697 
      en => "1",
1698 
      rst => "0",
1699 
      q(0) => tx_en_in8_q_net
1700 
    );
1701 
 
1702 
  tx_en_in85: entity work.xlregister
1703 
    generic map (
1704 
      d_width => 32,
1705 
      init_value => b"00000000000000000000000000000001"
1706 
    )
1707 
    port map (
1708 
      ce => ce_1_sg_x0,
1709 
      clk => clk_1_sg_x0,
1710 
      d => tx_en_in87_q_net,
1711 
      en(0) => convert4_dout_net,
1712 
      rst(0) => constant7_op_net,
1713 
      q => data_in_x6_net
1714 
    );
1715 
 
1716 
  tx_en_in86: entity work.xlregister
1717 
    generic map (
1718 
      d_width => 1,
1719 
      init_value => b"0"
1720 
    )
1721 
    port map (
1722 
      ce => ce_1_sg_x0,
1723 
      clk => clk_1_sg_x0,
1724 
      d(0) => data_out_x9_net,
1725 
      en => "1",
1726 
      rst => "0",
1727 
      q(0) => tx_en_in86_q_net
1728 
    );
1729 
 
1730 
  tx_en_in87: entity work.xlregister
1731 
    generic map (
1732 
      d_width => 32,
1733 
      init_value => b"00000000000000000000000000000000"
1734 
    )
1735 
    port map (
1736 
      ce => ce_1_sg_x0,
1737 
      clk => clk_1_sg_x0,
1738 
      d => data_out_x8_net,
1739 
      en => "1",
1740 
      rst => "0",
1741 
      q => tx_en_in87_q_net
1742 
    );
1743 
 
1744 
  tx_en_in88: entity work.xlregister
1745 
    generic map (
1746 
      d_width => 32,
1747 
      init_value => b"10000000000000000000000000000000"
1748 
    )
1749 
    port map (
1750 
      ce => ce_1_sg_x0,
1751 
      clk => clk_1_sg_x0,
1752 
      d => tx_en_in90_q_net,
1753 
      en(0) => convert11_dout_net,
1754 
      rst(0) => constant4_op_net,
1755 
      q => data_in_x8_net
1756 
    );
1757 
 
1758 
  tx_en_in89: entity work.xlregister
1759 
    generic map (
1760 
      d_width => 1,
1761 
      init_value => b"0"
1762 
    )
1763 
    port map (
1764 
      ce => ce_1_sg_x0,
1765 
      clk => clk_1_sg_x0,
1766 
      d(0) => data_out_x11_net,
1767 
      en => "1",
1768 
      rst => "0",
1769 
      q(0) => tx_en_in89_q_net
1770 
    );
1771 
 
1772 
  tx_en_in9: entity work.xlregister
1773 
    generic map (
1774 
      d_width => 32,
1775 
      init_value => b"00000000000000000000000000000000"
1776 
    )
1777 
    port map (
1778 
      ce => ce_1_sg_x0,
1779 
      clk => clk_1_sg_x0,
1780 
      d => data_out_x18_net,
1781 
      en => "1",
1782 
      rst => "0",
1783 
      q => dinb_x0
1784 
    );
1785 
 
1786 
  tx_en_in90: entity work.xlregister
1787 
    generic map (
1788 
      d_width => 32,
1789 
      init_value => b"00000000000000000000000000000000"
1790 
    )
1791 
    port map (
1792 
      ce => ce_1_sg_x0,
1793 
      clk => clk_1_sg_x0,
1794 
      d => data_out_x10_net,
1795 
      en => "1",
1796 
      rst => "0",
1797 
      q => tx_en_in90_q_net
1798 
    );
1799 
 
1800 
  tx_en_in91: entity work.xlregister
1801 
    generic map (
1802 
      d_width => 32,
1803 
      init_value => b"00000000000000000000000000000000"
1804 
    )
1805 
    port map (
1806 
      ce => ce_1_sg_x0,
1807 
      clk => clk_1_sg_x0,
1808 
      d => tx_en_in93_q_net,
1809 
      en(0) => convert12_dout_net,
1810 
      rst(0) => constant9_op_net,
1811 
      q => data_in_x10_net
1812 
    );
1813 
 
1814 
  tx_en_in92: entity work.xlregister
1815 
    generic map (
1816 
      d_width => 1,
1817 
      init_value => b"0"
1818 
    )
1819 
    port map (
1820 
      ce => ce_1_sg_x0,
1821 
      clk => clk_1_sg_x0,
1822 
      d(0) => data_out_x13_net,
1823 
      en => "1",
1824 
      rst => "0",
1825 
      q(0) => tx_en_in92_q_net
1826 
    );
1827 
 
1828 
  tx_en_in93: entity work.xlregister
1829 
    generic map (
1830 
      d_width => 32,
1831 
      init_value => b"00000000000000000000000000000000"
1832 
    )
1833 
    port map (
1834 
      ce => ce_1_sg_x0,
1835 
      clk => clk_1_sg_x0,
1836 
      d => data_out_x12_net,
1837 
      en => "1",
1838 
      rst => "0",
1839 
      q => tx_en_in93_q_net
1840 
    );
1841 
 
1842 
  tx_en_in94: entity work.xlregister
1843 
    generic map (
1844 
      d_width => 1,
1845 
      init_value => b"0"
1846 
    )
1847 
    port map (
1848 
      ce => ce_1_sg_x0,
1849 
      clk => clk_1_sg_x0,
1850 
      d(0) => convert1_dout_net,
1851 
      en => "1",
1852 
      rst => "0",
1853 
      q(0) => data_in_x21_net
1854 
    );
1855 
 
1856 
  tx_en_in95: entity work.xlregister
1857 
    generic map (
1858 
      d_width => 1,
1859 
      init_value => b"0"
1860 
    )
1861 
    port map (
1862 
      ce => ce_1_sg_x0,
1863 
      clk => clk_1_sg_x0,
1864 
      d(0) => convert5_dout_net,
1865 
      en => "1",
1866 
      rst => "0",
1867 
      q(0) => data_in_x24_net
1868 
    );
1869 
 
1870 
  tx_en_in96: entity work.xlregister
1871 
    generic map (
1872 
      d_width => 1,
1873 
      init_value => b"0"
1874 
    )
1875 
    port map (
1876 
      ce => ce_1_sg_x0,
1877 
      clk => clk_1_sg_x0,
1878 
      d(0) => convert6_dout_net,
1879 
      en => "1",
1880 
      rst => "0",
1881 
      q(0) => data_in_x1_net
1882 
    );
1883 
 
1884 
  tx_en_in97: entity work.xlregister
1885 
    generic map (
1886 
      d_width => 1,
1887 
      init_value => b"0"
1888 
    )
1889 
    port map (
1890 
      ce => ce_1_sg_x0,
1891 
      clk => clk_1_sg_x0,
1892 
      d(0) => convert7_dout_net,
1893 
      en => "1",
1894 
      rst => "0",
1895 
      q(0) => data_in_x2_net
1896 
    );
1897 
 
1898 
  tx_en_in98: entity work.xlregister
1899 
    generic map (
1900 
      d_width => 1,
1901 
      init_value => b"0"
1902 
    )
1903 
    port map (
1904 
      ce => ce_1_sg_x0,
1905 
      clk => clk_1_sg_x0,
1906 
      d(0) => convert4_dout_net,
1907 
      en => "1",
1908 
      rst => "0",
1909 
      q(0) => data_in_x5_net
1910 
    );
1911 
 
1912 
  tx_en_in99: entity work.xlregister
1913 
    generic map (
1914 
      d_width => 1,
1915 
      init_value => b"0"
1916 
    )
1917 
    port map (
1918 
      ce => ce_1_sg_x0,
1919 
      clk => clk_1_sg_x0,
1920 
      d(0) => convert11_dout_net,
1921 
      en => "1",
1922 
      rst => "0",
1923 
      q(0) => data_in_x7_net
1924 
    );
1925 
 
1926 
end structural;

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