OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [synopsis] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
{
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    'from_register20.data_out' => {
471 
      'hdlType' => 'std_logic_vector(31 downto 0)',
472 
      'width' => 32,
473 
    },
474 
    'from_register21.data_out' => {
475 
      'hdlType' => 'std_logic',
476 
      'width' => 1,
477 
    },
478 
    'from_register22.data_out' => {
479 
      'hdlType' => 'std_logic_vector(31 downto 0)',
480 
      'width' => 32,
481 
    },
482 
    'from_register23.data_out' => {
483 
      'hdlType' => 'std_logic',
484 
      'width' => 1,
485 
    },
486 
    'from_register24.data_out' => {
487 
      'hdlType' => 'std_logic_vector(31 downto 0)',
488 
      'width' => 32,
489 
    },
490 
    'from_register25.data_out' => {
491 
      'hdlType' => 'std_logic',
492 
      'width' => 1,
493 
    },
494 
    'from_register26.data_out' => {
495 
      'hdlType' => 'std_logic_vector(31 downto 0)',
496 
      'width' => 32,
497 
    },
498 
    'from_register27.data_out' => {
499 
      'hdlType' => 'std_logic',
500 
      'width' => 1,
501 
    },
502 
    'from_register28.data_out' => {
503 
      'hdlType' => 'std_logic_vector(31 downto 0)',
504 
      'width' => 32,
505 
    },
506 
    'from_register29.data_out' => {
507 
      'hdlType' => 'std_logic',
508 
      'width' => 1,
509 
    },
510 
    'from_register3.data_out' => {
511 
      'hdlType' => 'std_logic_vector(31 downto 0)',
512 
      'width' => 32,
513 
    },
514 
    'from_register30.data_out' => {
515 
      'hdlType' => 'std_logic_vector(31 downto 0)',
516 
      'width' => 32,
517 
    },
518 
    'from_register31.data_out' => {
519 
      'hdlType' => 'std_logic',
520 
      'width' => 1,
521 
    },
522 
    'from_register32.data_out' => {
523 
      'hdlType' => 'std_logic_vector(31 downto 0)',
524 
      'width' => 32,
525 
    },
526 
    'from_register33.data_out' => {
527 
      'hdlType' => 'std_logic',
528 
      'width' => 1,
529 
    },
530 
    'from_register4.data_out' => {
531 
      'hdlType' => 'std_logic',
532 
      'width' => 1,
533 
    },
534 
    'from_register5.data_out' => {
535 
      'hdlType' => 'std_logic_vector(31 downto 0)',
536 
      'width' => 32,
537 
    },
538 
    'from_register6.data_out' => {
539 
      'hdlType' => 'std_logic',
540 
      'width' => 1,
541 
    },
542 
    'from_register7.data_out' => {
543 
      'hdlType' => 'std_logic_vector(31 downto 0)',
544 
      'width' => 32,
545 
    },
546 
    'from_register8.data_out' => {
547 
      'hdlType' => 'std_logic',
548 
      'width' => 1,
549 
    },
550 
    'from_register9.data_out' => {
551 
      'hdlType' => 'std_logic_vector(31 downto 0)',
552 
      'width' => 32,
553 
    },
554 
    'sysgen_dut.bram_rd_addr' => {
555 
      'hdlType' => 'std_logic_vector(11 downto 0)',
556 
      'width' => 12,
557 
    },
558 
    'sysgen_dut.bram_wr_addr' => {
559 
      'hdlType' => 'std_logic_vector(11 downto 0)',
560 
      'width' => 12,
561 
    },
562 
    'sysgen_dut.bram_wr_din' => {
563 
      'hdlType' => 'std_logic_vector(63 downto 0)',
564 
      'width' => 64,
565 
    },
566 
    'sysgen_dut.bram_wr_en' => {
567 
      'hdlType' => 'std_logic_vector(7 downto 0)',
568 
      'width' => 8,
569 
    },
570 
    'sysgen_dut.fifo_rd_en' => {
571 
      'hdlType' => 'std_logic',
572 
      'width' => 1,
573 
    },
574 
    'sysgen_dut.fifo_wr_din' => {
575 
      'hdlType' => 'std_logic_vector(71 downto 0)',
576 
      'width' => 72,
577 
    },
578 
    'sysgen_dut.fifo_wr_en' => {
579 
      'hdlType' => 'std_logic',
580 
      'width' => 1,
581 
    },
582 
    'sysgen_dut.rst_o' => {
583 
      'hdlType' => 'std_logic',
584 
      'width' => 1,
585 
    },
586 
    'sysgen_dut.to_register10_ce' => {
587 
      'hdlType' => 'std_logic',
588 
      'width' => 1,
589 
    },
590 
    'sysgen_dut.to_register10_clk' => {
591 
      'hdlType' => 'std_logic',
592 
      'width' => 1,
593 
    },
594 
    'sysgen_dut.to_register10_clr' => {
595 
      'hdlType' => 'std_logic',
596 
      'width' => 1,
597 
    },
598 
    'sysgen_dut.to_register10_data_in' => {
599 
      'hdlType' => 'std_logic',
600 
      'width' => 1,
601 
    },
602 
    'sysgen_dut.to_register10_en' => {
603 
      'hdlType' => 'std_logic',
604 
      'width' => 1,
605 
    },
606 
    'sysgen_dut.to_register11_ce' => {
607 
      'hdlType' => 'std_logic',
608 
      'width' => 1,
609 
    },
610 
    'sysgen_dut.to_register11_clk' => {
611 
      'hdlType' => 'std_logic',
612 
      'width' => 1,
613 
    },
614 
    'sysgen_dut.to_register11_clr' => {
615 
      'hdlType' => 'std_logic',
616 
      'width' => 1,
617 
    },
618 
    'sysgen_dut.to_register11_data_in' => {
619 
      'hdlType' => 'std_logic',
620 
      'width' => 1,
621 
    },
622 
    'sysgen_dut.to_register11_en' => {
623 
      'hdlType' => 'std_logic',
624 
      'width' => 1,
625 
    },
626 
    'sysgen_dut.to_register12_ce' => {
627 
      'hdlType' => 'std_logic',
628 
      'width' => 1,
629 
    },
630 
    'sysgen_dut.to_register12_clk' => {
631 
      'hdlType' => 'std_logic',
632 
      'width' => 1,
633 
    },
634 
    'sysgen_dut.to_register12_clr' => {
635 
      'hdlType' => 'std_logic',
636 
      'width' => 1,
637 
    },
638 
    'sysgen_dut.to_register12_data_in' => {
639 
      'hdlType' => 'std_logic',
640 
      'width' => 1,
641 
    },
642 
    'sysgen_dut.to_register12_en' => {
643 
      'hdlType' => 'std_logic',
644 
      'width' => 1,
645 
    },
646 
    'sysgen_dut.to_register13_ce' => {
647 
      'hdlType' => 'std_logic',
648 
      'width' => 1,
649 
    },
650 
    'sysgen_dut.to_register13_clk' => {
651 
      'hdlType' => 'std_logic',
652 
      'width' => 1,
653 
    },
654 
    'sysgen_dut.to_register13_clr' => {
655 
      'hdlType' => 'std_logic',
656 
      'width' => 1,
657 
    },
658 
    'sysgen_dut.to_register13_data_in' => {
659 
      'hdlType' => 'std_logic_vector(31 downto 0)',
660 
      'width' => 32,
661 
    },
662 
    'sysgen_dut.to_register13_en' => {
663 
      'hdlType' => 'std_logic',
664 
      'width' => 1,
665 
    },
666 
    'sysgen_dut.to_register14_ce' => {
667 
      'hdlType' => 'std_logic',
668 
      'width' => 1,
669 
    },
670 
    'sysgen_dut.to_register14_clk' => {
671 
      'hdlType' => 'std_logic',
672 
      'width' => 1,
673 
    },
674 
    'sysgen_dut.to_register14_clr' => {
675 
      'hdlType' => 'std_logic',
676 
      'width' => 1,
677 
    },
678 
    'sysgen_dut.to_register14_data_in' => {
679 
      'hdlType' => 'std_logic',
680 
      'width' => 1,
681 
    },
682 
    'sysgen_dut.to_register14_en' => {
683 
      'hdlType' => 'std_logic',
684 
      'width' => 1,
685 
    },
686 
    'sysgen_dut.to_register15_ce' => {
687 
      'hdlType' => 'std_logic',
688 
      'width' => 1,
689 
    },
690 
    'sysgen_dut.to_register15_clk' => {
691 
      'hdlType' => 'std_logic',
692 
      'width' => 1,
693 
    },
694 
    'sysgen_dut.to_register15_clr' => {
695 
      'hdlType' => 'std_logic',
696 
      'width' => 1,
697 
    },
698 
    'sysgen_dut.to_register15_data_in' => {
699 
      'hdlType' => 'std_logic_vector(31 downto 0)',
700 
      'width' => 32,
701 
    },
702 
    'sysgen_dut.to_register15_en' => {
703 
      'hdlType' => 'std_logic',
704 
      'width' => 1,
705 
    },
706 
    'sysgen_dut.to_register16_ce' => {
707 
      'hdlType' => 'std_logic',
708 
      'width' => 1,
709 
    },
710 
    'sysgen_dut.to_register16_clk' => {
711 
      'hdlType' => 'std_logic',
712 
      'width' => 1,
713 
    },
714 
    'sysgen_dut.to_register16_clr' => {
715 
      'hdlType' => 'std_logic',
716 
      'width' => 1,
717 
    },
718 
    'sysgen_dut.to_register16_data_in' => {
719 
      'hdlType' => 'std_logic',
720 
      'width' => 1,
721 
    },
722 
    'sysgen_dut.to_register16_en' => {
723 
      'hdlType' => 'std_logic',
724 
      'width' => 1,
725 
    },
726 
    'sysgen_dut.to_register17_ce' => {
727 
      'hdlType' => 'std_logic',
728 
      'width' => 1,
729 
    },
730 
    'sysgen_dut.to_register17_clk' => {
731 
      'hdlType' => 'std_logic',
732 
      'width' => 1,
733 
    },
734 
    'sysgen_dut.to_register17_clr' => {
735 
      'hdlType' => 'std_logic',
736 
      'width' => 1,
737 
    },
738 
    'sysgen_dut.to_register17_data_in' => {
739 
      'hdlType' => 'std_logic_vector(31 downto 0)',
740 
      'width' => 32,
741 
    },
742 
    'sysgen_dut.to_register17_en' => {
743 
      'hdlType' => 'std_logic',
744 
      'width' => 1,
745 
    },
746 
    'sysgen_dut.to_register18_ce' => {
747 
      'hdlType' => 'std_logic',
748 
      'width' => 1,
749 
    },
750 
    'sysgen_dut.to_register18_clk' => {
751 
      'hdlType' => 'std_logic',
752 
      'width' => 1,
753 
    },
754 
    'sysgen_dut.to_register18_clr' => {
755 
      'hdlType' => 'std_logic',
756 
      'width' => 1,
757 
    },
758 
    'sysgen_dut.to_register18_data_in' => {
759 
      'hdlType' => 'std_logic',
760 
      'width' => 1,
761 
    },
762 
    'sysgen_dut.to_register18_en' => {
763 
      'hdlType' => 'std_logic',
764 
      'width' => 1,
765 
    },
766 
    'sysgen_dut.to_register19_ce' => {
767 
      'hdlType' => 'std_logic',
768 
      'width' => 1,
769 
    },
770 
    'sysgen_dut.to_register19_clk' => {
771 
      'hdlType' => 'std_logic',
772 
      'width' => 1,
773 
    },
774 
    'sysgen_dut.to_register19_clr' => {
775 
      'hdlType' => 'std_logic',
776 
      'width' => 1,
777 
    },
778 
    'sysgen_dut.to_register19_data_in' => {
779 
      'hdlType' => 'std_logic_vector(31 downto 0)',
780 
      'width' => 32,
781 
    },
782 
    'sysgen_dut.to_register19_en' => {
783 
      'hdlType' => 'std_logic',
784 
      'width' => 1,
785 
    },
786 
    'sysgen_dut.to_register1_ce' => {
787 
      'hdlType' => 'std_logic',
788 
      'width' => 1,
789 
    },
790 
    'sysgen_dut.to_register1_clk' => {
791 
      'hdlType' => 'std_logic',
792 
      'width' => 1,
793 
    },
794 
    'sysgen_dut.to_register1_clr' => {
795 
      'hdlType' => 'std_logic',
796 
      'width' => 1,
797 
    },
798 
    'sysgen_dut.to_register1_data_in' => {
799 
      'hdlType' => 'std_logic',
800 
      'width' => 1,
801 
    },
802 
    'sysgen_dut.to_register1_en' => {
803 
      'hdlType' => 'std_logic',
804 
      'width' => 1,
805 
    },
806 
    'sysgen_dut.to_register20_ce' => {
807 
      'hdlType' => 'std_logic',
808 
      'width' => 1,
809 
    },
810 
    'sysgen_dut.to_register20_clk' => {
811 
      'hdlType' => 'std_logic',
812 
      'width' => 1,
813 
    },
814 
    'sysgen_dut.to_register20_clr' => {
815 
      'hdlType' => 'std_logic',
816 
      'width' => 1,
817 
    },
818 
    'sysgen_dut.to_register20_data_in' => {
819 
      'hdlType' => 'std_logic',
820 
      'width' => 1,
821 
    },
822 
    'sysgen_dut.to_register20_en' => {
823 
      'hdlType' => 'std_logic',
824 
      'width' => 1,
825 
    },
826 
    'sysgen_dut.to_register21_ce' => {
827 
      'hdlType' => 'std_logic',
828 
      'width' => 1,
829 
    },
830 
    'sysgen_dut.to_register21_clk' => {
831 
      'hdlType' => 'std_logic',
832 
      'width' => 1,
833 
    },
834 
    'sysgen_dut.to_register21_clr' => {
835 
      'hdlType' => 'std_logic',
836 
      'width' => 1,
837 
    },
838 
    'sysgen_dut.to_register21_data_in' => {
839 
      'hdlType' => 'std_logic_vector(31 downto 0)',
840 
      'width' => 32,
841 
    },
842 
    'sysgen_dut.to_register21_en' => {
843 
      'hdlType' => 'std_logic',
844 
      'width' => 1,
845 
    },
846 
    'sysgen_dut.to_register22_ce' => {
847 
      'hdlType' => 'std_logic',
848 
      'width' => 1,
849 
    },
850 
    'sysgen_dut.to_register22_clk' => {
851 
      'hdlType' => 'std_logic',
852 
      'width' => 1,
853 
    },
854 
    'sysgen_dut.to_register22_clr' => {
855 
      'hdlType' => 'std_logic',
856 
      'width' => 1,
857 
    },
858 
    'sysgen_dut.to_register22_data_in' => {
859 
      'hdlType' => 'std_logic',
860 
      'width' => 1,
861 
    },
862 
    'sysgen_dut.to_register22_en' => {
863 
      'hdlType' => 'std_logic',
864 
      'width' => 1,
865 
    },
866 
    'sysgen_dut.to_register23_ce' => {
867 
      'hdlType' => 'std_logic',
868 
      'width' => 1,
869 
    },
870 
    'sysgen_dut.to_register23_clk' => {
871 
      'hdlType' => 'std_logic',
872 
      'width' => 1,
873 
    },
874 
    'sysgen_dut.to_register23_clr' => {
875 
      'hdlType' => 'std_logic',
876 
      'width' => 1,
877 
    },
878 
    'sysgen_dut.to_register23_data_in' => {
879 
      'hdlType' => 'std_logic_vector(31 downto 0)',
880 
      'width' => 32,
881 
    },
882 
    'sysgen_dut.to_register23_en' => {
883 
      'hdlType' => 'std_logic',
884 
      'width' => 1,
885 
    },
886 
    'sysgen_dut.to_register24_ce' => {
887 
      'hdlType' => 'std_logic',
888 
      'width' => 1,
889 
    },
890 
    'sysgen_dut.to_register24_clk' => {
891 
      'hdlType' => 'std_logic',
892 
      'width' => 1,
893 
    },
894 
    'sysgen_dut.to_register24_clr' => {
895 
      'hdlType' => 'std_logic',
896 
      'width' => 1,
897 
    },
898 
    'sysgen_dut.to_register24_data_in' => {
899 
      'hdlType' => 'std_logic',
900 
      'width' => 1,
901 
    },
902 
    'sysgen_dut.to_register24_en' => {
903 
      'hdlType' => 'std_logic',
904 
      'width' => 1,
905 
    },
906 
    'sysgen_dut.to_register25_ce' => {
907 
      'hdlType' => 'std_logic',
908 
      'width' => 1,
909 
    },
910 
    'sysgen_dut.to_register25_clk' => {
911 
      'hdlType' => 'std_logic',
912 
      'width' => 1,
913 
    },
914 
    'sysgen_dut.to_register25_clr' => {
915 
      'hdlType' => 'std_logic',
916 
      'width' => 1,
917 
    },
918 
    'sysgen_dut.to_register25_data_in' => {
919 
      'hdlType' => 'std_logic_vector(31 downto 0)',
920 
      'width' => 32,
921 
    },
922 
    'sysgen_dut.to_register25_en' => {
923 
      'hdlType' => 'std_logic',
924 
      'width' => 1,
925 
    },
926 
    'sysgen_dut.to_register26_ce' => {
927 
      'hdlType' => 'std_logic',
928 
      'width' => 1,
929 
    },
930 
    'sysgen_dut.to_register26_clk' => {
931 
      'hdlType' => 'std_logic',
932 
      'width' => 1,
933 
    },
934 
    'sysgen_dut.to_register26_clr' => {
935 
      'hdlType' => 'std_logic',
936 
      'width' => 1,
937 
    },
938 
    'sysgen_dut.to_register26_data_in' => {
939 
      'hdlType' => 'std_logic',
940 
      'width' => 1,
941 
    },
942 
    'sysgen_dut.to_register26_en' => {
943 
      'hdlType' => 'std_logic',
944 
      'width' => 1,
945 
    },
946 
    'sysgen_dut.to_register27_ce' => {
947 
      'hdlType' => 'std_logic',
948 
      'width' => 1,
949 
    },
950 
    'sysgen_dut.to_register27_clk' => {
951 
      'hdlType' => 'std_logic',
952 
      'width' => 1,
953 
    },
954 
    'sysgen_dut.to_register27_clr' => {
955 
      'hdlType' => 'std_logic',
956 
      'width' => 1,
957 
    },
958 
    'sysgen_dut.to_register27_data_in' => {
959 
      'hdlType' => 'std_logic_vector(31 downto 0)',
960 
      'width' => 32,
961 
    },
962 
    'sysgen_dut.to_register27_en' => {
963 
      'hdlType' => 'std_logic',
964 
      'width' => 1,
965 
    },
966 
    'sysgen_dut.to_register2_ce' => {
967 
      'hdlType' => 'std_logic',
968 
      'width' => 1,
969 
    },
970 
    'sysgen_dut.to_register2_clk' => {
971 
      'hdlType' => 'std_logic',
972 
      'width' => 1,
973 
    },
974 
    'sysgen_dut.to_register2_clr' => {
975 
      'hdlType' => 'std_logic',
976 
      'width' => 1,
977 
    },
978 
    'sysgen_dut.to_register2_data_in' => {
979 
      'hdlType' => 'std_logic_vector(31 downto 0)',
980 
      'width' => 32,
981 
    },
982 
    'sysgen_dut.to_register2_en' => {
983 
      'hdlType' => 'std_logic',
984 
      'width' => 1,
985 
    },
986 
    'sysgen_dut.to_register3_ce' => {
987 
      'hdlType' => 'std_logic',
988 
      'width' => 1,
989 
    },
990 
    'sysgen_dut.to_register3_clk' => {
991 
      'hdlType' => 'std_logic',
992 
      'width' => 1,
993 
    },
994 
    'sysgen_dut.to_register3_clr' => {
995 
      'hdlType' => 'std_logic',
996 
      'width' => 1,
997 
    },
998 
    'sysgen_dut.to_register3_data_in' => {
999 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1000 
      'width' => 32,
1001 
    },
1002 
    'sysgen_dut.to_register3_en' => {
1003 
      'hdlType' => 'std_logic',
1004 
      'width' => 1,
1005 
    },
1006 
    'sysgen_dut.to_register4_ce' => {
1007 
      'hdlType' => 'std_logic',
1008 
      'width' => 1,
1009 
    },
1010 
    'sysgen_dut.to_register4_clk' => {
1011 
      'hdlType' => 'std_logic',
1012 
      'width' => 1,
1013 
    },
1014 
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1015 
      'hdlType' => 'std_logic',
1016 
      'width' => 1,
1017 
    },
1018 
    'sysgen_dut.to_register4_data_in' => {
1019 
      'hdlType' => 'std_logic',
1020 
      'width' => 1,
1021 
    },
1022 
    'sysgen_dut.to_register4_en' => {
1023 
      'hdlType' => 'std_logic',
1024 
      'width' => 1,
1025 
    },
1026 
    'sysgen_dut.to_register5_ce' => {
1027 
      'hdlType' => 'std_logic',
1028 
      'width' => 1,
1029 
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1030 
    'sysgen_dut.to_register5_clk' => {
1031 
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1032 
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1033 
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1034 
    'sysgen_dut.to_register5_clr' => {
1035 
      'hdlType' => 'std_logic',
1036 
      'width' => 1,
1037 
    },
1038 
    'sysgen_dut.to_register5_data_in' => {
1039 
      'hdlType' => 'std_logic',
1040 
      'width' => 1,
1041 
    },
1042 
    'sysgen_dut.to_register5_en' => {
1043 
      'hdlType' => 'std_logic',
1044 
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1045 
    },
1046 
    'sysgen_dut.to_register6_ce' => {
1047 
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1048 
      'width' => 1,
1049 
    },
1050 
    'sysgen_dut.to_register6_clk' => {
1051 
      'hdlType' => 'std_logic',
1052 
      'width' => 1,
1053 
    },
1054 
    'sysgen_dut.to_register6_clr' => {
1055 
      'hdlType' => 'std_logic',
1056 
      'width' => 1,
1057 
    },
1058 
    'sysgen_dut.to_register6_data_in' => {
1059 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1060 
      'width' => 32,
1061 
    },
1062 
    'sysgen_dut.to_register6_en' => {
1063 
      'hdlType' => 'std_logic',
1064 
      'width' => 1,
1065 
    },
1066 
    'sysgen_dut.to_register7_ce' => {
1067 
      'hdlType' => 'std_logic',
1068 
      'width' => 1,
1069 
    },
1070 
    'sysgen_dut.to_register7_clk' => {
1071 
      'hdlType' => 'std_logic',
1072 
      'width' => 1,
1073 
    },
1074 
    'sysgen_dut.to_register7_clr' => {
1075 
      'hdlType' => 'std_logic',
1076 
      'width' => 1,
1077 
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1078 
    'sysgen_dut.to_register7_data_in' => {
1079 
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1080 
      'width' => 1,
1081 
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1082 
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1083 
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1084 
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1085 
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1086 
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1087 
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1088 
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1089 
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1090 
    'sysgen_dut.to_register8_clk' => {
1091 
      'hdlType' => 'std_logic',
1092 
      'width' => 1,
1093 
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1094 
    'sysgen_dut.to_register8_clr' => {
1095 
      'hdlType' => 'std_logic',
1096 
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1097 
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1098 
    'sysgen_dut.to_register8_data_in' => {
1099 
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1100 
      'width' => 32,
1101 
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1102 
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1103 
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1104 
      'width' => 1,
1105 
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1106 
    'sysgen_dut.to_register9_ce' => {
1107 
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1108 
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1109 
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1110 
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1111 
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1112 
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1113 
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1114 
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1115 
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1116 
      'width' => 1,
1117 
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1118 
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1119 
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1120 
      'width' => 32,
1121 
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1122 
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1123 
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1124 
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1125 
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1126 
    'sysgen_dut.to_register_ce' => {
1127 
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1128 
      'width' => 1,
1129 
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1130 
    'sysgen_dut.to_register_clk' => {
1131 
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1132 
      'width' => 1,
1133 
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1134 
    'sysgen_dut.to_register_clr' => {
1135 
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1136 
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1137 
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1138 
    'sysgen_dut.to_register_data_in' => {
1139 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1140 
      'width' => 32,
1141 
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1142 
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1143 
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1144 
      'width' => 1,
1145 
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1146 
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1147 
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1148 
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1150 
    'sysgen_dut.user_int_2o' => {
1151 
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1152 
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1153 
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1154 
    'sysgen_dut.user_int_3o' => {
1155 
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1156 
      'width' => 1,
1157 
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1158 
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1159 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1160 
      'width' => 32,
1161 
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1162 
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1163 
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1164 
      'width' => 1,
1165 
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1166 
    'to_register10.dout' => {
1167 
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1168 
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1169 
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1170 
    'to_register11.dout' => {
1171 
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1172 
      'width' => 1,
1173 
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1174 
    'to_register12.dout' => {
1175 
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1176 
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1177 
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1178 
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1179 
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1180 
      'width' => 32,
1181 
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1182 
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1183 
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1184 
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1185 
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1186 
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1187 
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1188 
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1189 
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1190 
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1191 
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1192 
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1193 
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1194 
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1195 
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1196 
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1197 
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1198 
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1199 
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1200 
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1201 
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1202 
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1203 
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1204 
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1205 
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1206 
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1207 
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1208 
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1209 
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1210 
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1211 
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1212 
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1213 
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1214 
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1215 
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1216 
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1217 
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1218 
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1219 
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1220 
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1221 
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1222 
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1223 
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1224 
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1225 
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1226 
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1227 
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1228 
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1229 
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1230 
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1231 
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1232 
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1233 
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1234 
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1235 
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1236 
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1237 
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1238 
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1239 
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1240 
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1241 
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1242 
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1243 
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1244 
      'width' => 32,
1245 
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1246 
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1247 
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1248 
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1249 
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1250 
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1251 
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1252 
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1253 
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1254 
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1255 
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1256 
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1257 
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1258 
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1259 
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1260 
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1261 
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1262 
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1263 
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1264 
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1265 
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1266 
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1267 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1268 
      'width' => 32,
1269 
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1270 
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1271 
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1272 
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1273 
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1274 
        'bram_rd_addr' => 'sysgen_dut.bram_rd_addr',
1275 
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1276 
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1277 
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1278 
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1279 
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1280 
          'is_floating_block' => 1,
1281 
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1282 
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1283 
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1284 
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1285 
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1286 
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1287 
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1288 
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1289 
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1290 
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1291 
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1294 
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1295 
              'timingConstraint' => 'none',
1296 
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1297 
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1298 
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1299 
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1300 
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1301 
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1302 
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1303 
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1304 
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1305 
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1306 
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1307 
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1308 
        'bram_rd_dout' => '.bram_rd_dout',
1309 
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1310 
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1311 
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1312 
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1313 
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1314 
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1315 
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1316 
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1317 
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1318 
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1319 
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1320 
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1328 
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1329 
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1339 
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1340 
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1341 
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1342 
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1343 
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1344 
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1345 
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1346 
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1347 
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1348 
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1349 
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1350 
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1351 
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1352 
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1353 
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1362 
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1363 
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1371 
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1373 
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1374 
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1375 
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1376 
        'bram_wr_din' => 'sysgen_dut.bram_wr_din',
1377 
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1378 
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1379 
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1380 
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1381 
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1382 
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1383 
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1384 
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1385 
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1386 
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1387 
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1388 
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1396 
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1397 
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1405 
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1407 
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1408 
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1409 
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1410 
        'bram_wr_en' => 'sysgen_dut.bram_wr_en',
1411 
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1412 
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1413 
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1414 
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1415 
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1416 
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1417 
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1419 
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1420 
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1421 
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1422 
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1430 
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1431 
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1435 
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1443 
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1444 
        'fifo_rd_count' => '.fifo_rd_count',
1445 
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1446 
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1447 
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1448 
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1449 
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1450 
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1451 
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1452 
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1453 
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1454 
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1455 
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1456 
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1457 
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1463 
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1465 
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1467 
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1473 
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1474 
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1475 
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1477 
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1478 
        'fifo_rd_dout' => '.fifo_rd_dout',
1479 
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1480 
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1481 
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1482 
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1490 
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              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout',
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1504 
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1511 
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1512 
        'fifo_rd_empty' => '.fifo_rd_empty',
1513 
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1514 
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1517 
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1518 
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1519 
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1520 
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1521 
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1522 
          'fifo_rd_empty' => {
1523 
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1524 
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1525 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_empty.dat',
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            'period' => '5e-009',
3495 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3496 
            'shared_memory_name' => 'register02tv',
3497 
          },
3498 
          'needs_vhdl_wrapper' => 0,
3499 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register6',
3500 
        },
3501 
        'entityName' => 'x_x115',
3502 
        'ports' => {
3503 
          'data_out' => {
3504 
            'attributes' => {
3505 
              'bin_pt' => 0,
3506 
              'is_floating_block' => 1,
3507 
              'must_be_hdl_vector' => 1,
3508 
              'period' => 1,
3509 
              'port_id' => 0,
3510 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register6/data_out',
3511 
              'type' => 'UFix_1_0',
3512 
            },
3513 
            'direction' => 'out',
3514 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3515 
            'width' => 1,
3516 
          },
3517 
        },
3518 
      },
3519 
      'entityName' => 'x_x115',
3520 
    },
3521 
    'from_register7' => {
3522 
      'connections' => {
3523 
        'data_out' => 'from_register7.data_out',
3524 
      },
3525 
      'entity' => {
3526 
        'attributes' => {
3527 
          'entityAlreadyNetlisted' => 1,
3528 
          'generics' => [
3529 
          ],
3530 
          'is_floating_block' => 1,
3531 
          'mask' => {
3532 
            'Block_Handle' => 414.0009765625,
3533 
            'Block_handle' => 414.0009765625,
3534 
            'MDL_Handle' => 3.0009765625,
3535 
            'MDL_handle' => 3.0009765625,
3536 
            'arith_type' => 2,
3537 
            'bin_pt' => 0,
3538 
            'block_config' => 'sysgen_blockset:fromreg_config',
3539 
            'block_handle' => 414.0009765625,
3540 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7',
3541 
            'block_type' => 'fromreg',
3542 
            'dbl_ovrd' => 0,
3543 
            'init' => 0,
3544 
            'init_bit_vector' => '00000000000000000000000000000000b',
3545 
            'mdl_handle' => 3.0009765625,
3546 
            'model_handle' => 3.0009765625,
3547 
            'n_bits' => 32,
3548 
            'ownership' => 2,
3549 
            'period' => '5e-009',
3550 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3551 
            'shared_memory_name' => 'register03td',
3552 
          },
3553 
          'needs_vhdl_wrapper' => 0,
3554 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7',
3555 
        },
3556 
        'entityName' => 'x_x116',
3557 
        'ports' => {
3558 
          'data_out' => {
3559 
            'attributes' => {
3560 
              'bin_pt' => 0,
3561 
              'is_floating_block' => 1,
3562 
              'must_be_hdl_vector' => 1,
3563 
              'period' => 1,
3564 
              'port_id' => 0,
3565 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7/data_out',
3566 
              'type' => 'UFix_32_0',
3567 
            },
3568 
            'direction' => 'out',
3569 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3570 
            'width' => 32,
3571 
          },
3572 
        },
3573 
      },
3574 
      'entityName' => 'x_x116',
3575 
    },
3576 
    'from_register8' => {
3577 
      'connections' => {
3578 
        'data_out' => 'from_register8.data_out',
3579 
      },
3580 
      'entity' => {
3581 
        'attributes' => {
3582 
          'entityAlreadyNetlisted' => 1,
3583 
          'generics' => [
3584 
          ],
3585 
          'is_floating_block' => 1,
3586 
          'mask' => {
3587 
            'Block_Handle' => 415.0009765625,
3588 
            'Block_handle' => 415.0009765625,
3589 
            'MDL_Handle' => 3.0009765625,
3590 
            'MDL_handle' => 3.0009765625,
3591 
            'arith_type' => 2,
3592 
            'bin_pt' => 0,
3593 
            'block_config' => 'sysgen_blockset:fromreg_config',
3594 
            'block_handle' => 415.0009765625,
3595 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8',
3596 
            'block_type' => 'fromreg',
3597 
            'dbl_ovrd' => 0,
3598 
            'init' => 0,
3599 
            'init_bit_vector' => '0b',
3600 
            'mdl_handle' => 3.0009765625,
3601 
            'model_handle' => 3.0009765625,
3602 
            'n_bits' => 1,
3603 
            'ownership' => 2,
3604 
            'period' => '5e-009',
3605 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3606 
            'shared_memory_name' => 'register03tv',
3607 
          },
3608 
          'needs_vhdl_wrapper' => 0,
3609 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8',
3610 
        },
3611 
        'entityName' => 'x_x117',
3612 
        'ports' => {
3613 
          'data_out' => {
3614 
            'attributes' => {
3615 
              'bin_pt' => 0,
3616 
              'is_floating_block' => 1,
3617 
              'must_be_hdl_vector' => 1,
3618 
              'period' => 1,
3619 
              'port_id' => 0,
3620 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8/data_out',
3621 
              'type' => 'UFix_1_0',
3622 
            },
3623 
            'direction' => 'out',
3624 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3625 
            'width' => 1,
3626 
          },
3627 
        },
3628 
      },
3629 
      'entityName' => 'x_x117',
3630 
    },
3631 
    'from_register9' => {
3632 
      'connections' => {
3633 
        'data_out' => 'from_register9.data_out',
3634 
      },
3635 
      'entity' => {
3636 
        'attributes' => {
3637 
          'entityAlreadyNetlisted' => 1,
3638 
          'generics' => [
3639 
          ],
3640 
          'is_floating_block' => 1,
3641 
          'mask' => {
3642 
            'Block_Handle' => 416.0009765625,
3643 
            'Block_handle' => 416.0009765625,
3644 
            'MDL_Handle' => 3.0009765625,
3645 
            'MDL_handle' => 3.0009765625,
3646 
            'arith_type' => 2,
3647 
            'bin_pt' => 0,
3648 
            'block_config' => 'sysgen_blockset:fromreg_config',
3649 
            'block_handle' => 416.0009765625,
3650 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9',
3651 
            'block_type' => 'fromreg',
3652 
            'dbl_ovrd' => 0,
3653 
            'init' => 0,
3654 
            'init_bit_vector' => '00000000000000000000000000000000b',
3655 
            'mdl_handle' => 3.0009765625,
3656 
            'model_handle' => 3.0009765625,
3657 
            'n_bits' => 32,
3658 
            'ownership' => 2,
3659 
            'period' => '5e-009',
3660 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3661 
            'shared_memory_name' => 'register04td',
3662 
          },
3663 
          'needs_vhdl_wrapper' => 0,
3664 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9',
3665 
        },
3666 
        'entityName' => 'x_x118',
3667 
        'ports' => {
3668 
          'data_out' => {
3669 
            'attributes' => {
3670 
              'bin_pt' => 0,
3671 
              'is_floating_block' => 1,
3672 
              'must_be_hdl_vector' => 1,
3673 
              'period' => 1,
3674 
              'port_id' => 0,
3675 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9/data_out',
3676 
              'type' => 'UFix_32_0',
3677 
            },
3678 
            'direction' => 'out',
3679 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3680 
            'width' => 32,
3681 
          },
3682 
        },
3683 
      },
3684 
      'entityName' => 'x_x118',
3685 
    },
3686 
    'rst_i' => {
3687 
      'connections' => {
3688 
        'rst_i' => '.rst_i',
3689 
      },
3690 
      'entity' => {
3691 
        'attributes' => {
3692 
          'entityAlreadyNetlisted' => 1,
3693 
          'isGateway' => 1,
3694 
          'is_floating_block' => 1,
3695 
        },
3696 
        'entityName' => 'rst_i',
3697 
        'ports' => {
3698 
          'rst_i' => {
3699 
            'attributes' => {
3700 
              'bin_pt' => 0,
3701 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_i.dat',
3702 
              'is_floating_block' => 1,
3703 
              'is_gateway_port' => 1,
3704 
              'must_be_hdl_vector' => 1,
3705 
              'period' => 1,
3706 
              'port_id' => 0,
3707 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_i/rst_i',
3708 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/rst_i',
3709 
              'timingConstraint' => 'none',
3710 
              'type' => 'Bool',
3711 
            },
3712 
            'direction' => 'out',
3713 
            'hdlType' => 'std_logic',
3714 
            'width' => 1,
3715 
          },
3716 
        },
3717 
      },
3718 
      'entityName' => 'rst_i',
3719 
    },
3720 
    'rst_o' => {
3721 
      'connections' => {
3722 
        'rst_o' => 'sysgen_dut.rst_o',
3723 
      },
3724 
      'entity' => {
3725 
        'attributes' => {
3726 
          'entityAlreadyNetlisted' => 1,
3727 
          'isGateway' => 1,
3728 
          'is_floating_block' => 1,
3729 
        },
3730 
        'entityName' => 'rst_o',
3731 
        'ports' => {
3732 
          'rst_o' => {
3733 
            'attributes' => {
3734 
              'bin_pt' => 0,
3735 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
3736 
              'is_floating_block' => 1,
3737 
              'is_gateway_port' => 1,
3738 
              'must_be_hdl_vector' => 1,
3739 
              'period' => 1,
3740 
              'port_id' => 0,
3741 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_o/rst_o',
3742 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/rst_o',
3743 
              'timingConstraint' => 'none',
3744 
              'type' => 'Bool',
3745 
            },
3746 
            'direction' => 'in',
3747 
            'hdlType' => 'std_logic',
3748 
            'width' => 1,
3749 
          },
3750 
        },
3751 
      },
3752 
      'entityName' => 'rst_o',
3753 
    },
3754 
    'sysgen_dut' => {
3755 
      'connections' => {
3756 
        'bram_rd_addr' => 'sysgen_dut.bram_rd_addr',
3757 
        'bram_rd_dout' => '.bram_rd_dout',
3758 
        'bram_wr_addr' => 'sysgen_dut.bram_wr_addr',
3759 
        'bram_wr_din' => 'sysgen_dut.bram_wr_din',
3760 
        'bram_wr_en' => 'sysgen_dut.bram_wr_en',
3761 
        'clk' => '.clk',
3762 
        'fifo_rd_count' => '.fifo_rd_count',
3763 
        'fifo_rd_dout' => '.fifo_rd_dout',
3764 
        'fifo_rd_empty' => '.fifo_rd_empty',
3765 
        'fifo_rd_en' => 'sysgen_dut.fifo_rd_en',
3766 
        'fifo_rd_pempty' => '.fifo_rd_pempty',
3767 
        'fifo_rd_valid' => '.fifo_rd_valid',
3768 
        'fifo_wr_count' => '.fifo_wr_count',
3769 
        'fifo_wr_din' => 'sysgen_dut.fifo_wr_din',
3770 
        'fifo_wr_en' => 'sysgen_dut.fifo_wr_en',
3771 
        'fifo_wr_full' => '.fifo_wr_full',
3772 
        'fifo_wr_pfull' => '.fifo_wr_pfull',
3773 
        'from_register10_data_out' => 'from_register10.data_out',
3774 
        'from_register11_data_out' => 'from_register11.data_out',
3775 
        'from_register12_data_out' => 'from_register12.data_out',
3776 
        'from_register13_data_out' => 'from_register13.data_out',
3777 
        'from_register14_data_out' => 'from_register14.data_out',
3778 
        'from_register15_data_out' => 'from_register15.data_out',
3779 
        'from_register16_data_out' => 'from_register16.data_out',
3780 
        'from_register17_data_out' => 'from_register17.data_out',
3781 
        'from_register18_data_out' => 'from_register18.data_out',
3782 
        'from_register19_data_out' => 'from_register19.data_out',
3783 
        'from_register1_data_out' => 'from_register1.data_out',
3784 
        'from_register20_data_out' => 'from_register20.data_out',
3785 
        'from_register21_data_out' => 'from_register21.data_out',
3786 
        'from_register22_data_out' => 'from_register22.data_out',
3787 
        'from_register23_data_out' => 'from_register23.data_out',
3788 
        'from_register24_data_out' => 'from_register24.data_out',
3789 
        'from_register25_data_out' => 'from_register25.data_out',
3790 
        'from_register26_data_out' => 'from_register26.data_out',
3791 
        'from_register27_data_out' => 'from_register27.data_out',
3792 
        'from_register28_data_out' => 'from_register28.data_out',
3793 
        'from_register29_data_out' => 'from_register29.data_out',
3794 
        'from_register2_data_out' => 'from_register2.data_out',
3795 
        'from_register30_data_out' => 'from_register30.data_out',
3796 
        'from_register31_data_out' => 'from_register31.data_out',
3797 
        'from_register32_data_out' => 'from_register32.data_out',
3798 
        'from_register33_data_out' => 'from_register33.data_out',
3799 
        'from_register3_data_out' => 'from_register3.data_out',
3800 
        'from_register4_data_out' => 'from_register4.data_out',
3801 
        'from_register5_data_out' => 'from_register5.data_out',
3802 
        'from_register6_data_out' => 'from_register6.data_out',
3803 
        'from_register7_data_out' => 'from_register7.data_out',
3804 
        'from_register8_data_out' => 'from_register8.data_out',
3805 
        'from_register9_data_out' => 'from_register9.data_out',
3806 
        'from_register_data_out' => 'from_register.data_out',
3807 
        'rst_i' => '.rst_i',
3808 
        'rst_o' => 'sysgen_dut.rst_o',
3809 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
3810 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
3811 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
3812 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
3813 
        'to_register10_dout' => 'to_register10.dout',
3814 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
3815 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
3816 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
3817 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
3818 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
3819 
        'to_register11_dout' => 'to_register11.dout',
3820 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
3821 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
3822 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
3823 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
3824 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
3825 
        'to_register12_dout' => 'to_register12.dout',
3826 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
3827 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
3828 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
3829 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
3830 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
3831 
        'to_register13_dout' => 'to_register13.dout',
3832 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
3833 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
3834 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
3835 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
3836 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
3837 
        'to_register14_dout' => 'to_register14.dout',
3838 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
3839 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
3840 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
3841 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
3842 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
3843 
        'to_register15_dout' => 'to_register15.dout',
3844 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
3845 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
3846 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
3847 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
3848 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
3849 
        'to_register16_dout' => 'to_register16.dout',
3850 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
3851 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
3852 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
3853 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
3854 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
3855 
        'to_register17_dout' => 'to_register17.dout',
3856 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
3857 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
3858 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
3859 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
3860 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
3861 
        'to_register18_dout' => 'to_register18.dout',
3862 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
3863 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
3864 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
3865 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
3866 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
3867 
        'to_register19_dout' => 'to_register19.dout',
3868 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
3869 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
3870 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
3871 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
3872 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
3873 
        'to_register1_dout' => 'to_register1.dout',
3874 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
3875 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
3876 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
3877 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
3878 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
3879 
        'to_register20_dout' => 'to_register20.dout',
3880 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
3881 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
3882 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
3883 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
3884 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
3885 
        'to_register21_dout' => 'to_register21.dout',
3886 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
3887 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
3888 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
3889 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
3890 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
3891 
        'to_register22_dout' => 'to_register22.dout',
3892 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
3893 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
3894 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
3895 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
3896 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
3897 
        'to_register23_dout' => 'to_register23.dout',
3898 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
3899 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
3900 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
3901 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
3902 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
3903 
        'to_register24_dout' => 'to_register24.dout',
3904 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
3905 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
3906 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
3907 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
3908 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
3909 
        'to_register25_dout' => 'to_register25.dout',
3910 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
3911 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
3912 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
3913 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
3914 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
3915 
        'to_register26_dout' => 'to_register26.dout',
3916 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
3917 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
3918 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
3919 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
3920 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
3921 
        'to_register27_dout' => 'to_register27.dout',
3922 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
3923 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
3924 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
3925 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
3926 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
3927 
        'to_register2_dout' => 'to_register2.dout',
3928 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
3929 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
3930 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
3931 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
3932 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
3933 
        'to_register3_dout' => 'to_register3.dout',
3934 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
3935 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
3936 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
3937 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
3938 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
3939 
        'to_register4_dout' => 'to_register4.dout',
3940 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
3941 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
3942 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
3943 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
3944 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
3945 
        'to_register5_dout' => 'to_register5.dout',
3946 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
3947 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
3948 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
3949 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
3950 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
3951 
        'to_register6_dout' => 'to_register6.dout',
3952 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
3953 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
3954 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
3955 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
3956 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
3957 
        'to_register7_dout' => 'to_register7.dout',
3958 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
3959 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
3960 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
3961 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
3962 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
3963 
        'to_register8_dout' => 'to_register8.dout',
3964 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
3965 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
3966 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
3967 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
3968 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
3969 
        'to_register9_dout' => 'to_register9.dout',
3970 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
3971 
        'to_register_ce' => 'sysgen_dut.to_register_ce',
3972 
        'to_register_clk' => 'sysgen_dut.to_register_clk',
3973 
        'to_register_clr' => 'sysgen_dut.to_register_clr',
3974 
        'to_register_data_in' => 'sysgen_dut.to_register_data_in',
3975 
        'to_register_dout' => 'to_register.dout',
3976 
        'to_register_en' => 'sysgen_dut.to_register_en',
3977 
        'user_int_1o' => 'sysgen_dut.user_int_1o',
3978 
        'user_int_2o' => 'sysgen_dut.user_int_2o',
3979 
        'user_int_3o' => 'sysgen_dut.user_int_3o',
3980 
      },
3981 
      'entity' => {
3982 
        'attributes' => {
3983 
          'entityAlreadyNetlisted' => 1,
3984 
          'hdlArchAttributes' => [
3985 
          ],
3986 
          'hdlEntityAttributes' => [
3987 
          ],
3988 
          'isClkWrapper' => 1,
3989 
        },
3990 
        'connections' => {
3991 
          'bram_rd_addr' => 'bram_rd_addr_net',
3992 
          'bram_rd_dout' => 'bram_rd_dout_net',
3993 
          'bram_wr_addr' => 'bram_wr_addr_net',
3994 
          'bram_wr_din' => 'bram_wr_din_net',
3995 
          'bram_wr_en' => 'bram_wr_en_net',
3996 
          'clk' => 'clkNet',
3997 
          'fifo_rd_count' => 'fifo_rd_count_net',
3998 
          'fifo_rd_dout' => 'fifo_rd_dout_net',
3999 
          'fifo_rd_empty' => 'fifo_rd_empty_net',
4000 
          'fifo_rd_en' => 'fifo_rd_en_net',
4001 
          'fifo_rd_pempty' => 'fifo_rd_pempty_net',
4002 
          'fifo_rd_valid' => 'fifo_rd_valid_net',
4003 
          'fifo_wr_count' => 'fifo_wr_count_net',
4004 
          'fifo_wr_din' => 'fifo_wr_din_net',
4005 
          'fifo_wr_en' => 'fifo_wr_en_net',
4006 
          'fifo_wr_full' => 'fifo_wr_full_net',
4007 
          'fifo_wr_pfull' => 'fifo_wr_pfull_net',
4008 
          'from_register10_data_out' => 'data_out_net',
4009 
          'from_register11_data_out' => 'data_out_x0_net',
4010 
          'from_register12_data_out' => 'data_out_x1_net',
4011 
          'from_register13_data_out' => 'data_out_x2_net',
4012 
          'from_register14_data_out' => 'data_out_x3_net',
4013 
          'from_register15_data_out' => 'from_register15_data_out_net',
4014 
          'from_register16_data_out' => 'from_register16_data_out_net',
4015 
          'from_register17_data_out' => 'data_out_x6_net',
4016 
          'from_register18_data_out' => 'data_out_x7_net',
4017 
          'from_register19_data_out' => 'from_register19_data_out_net',
4018 
          'from_register1_data_out' => 'from_register1_data_out_net',
4019 
          'from_register20_data_out' => 'data_out_x8_net',
4020 
          'from_register21_data_out' => 'data_out_x9_net',
4021 
          'from_register22_data_out' => 'data_out_x10_net',
4022 
          'from_register23_data_out' => 'data_out_x11_net',
4023 
          'from_register24_data_out' => 'data_out_x12_net',
4024 
          'from_register25_data_out' => 'data_out_x13_net',
4025 
          'from_register26_data_out' => 'data_out_x14_net',
4026 
          'from_register27_data_out' => 'data_out_x15_net',
4027 
          'from_register28_data_out' => 'data_out_x16_net',
4028 
          'from_register29_data_out' => 'data_out_x17_net',
4029 
          'from_register2_data_out' => 'from_register2_data_out_net',
4030 
          'from_register30_data_out' => 'data_out_x19_net',
4031 
          'from_register31_data_out' => 'data_out_x20_net',
4032 
          'from_register32_data_out' => 'data_out_x21_net',
4033 
          'from_register33_data_out' => 'data_out_x22_net',
4034 
          'from_register3_data_out' => 'data_out_x18_net',
4035 
          'from_register4_data_out' => 'data_out_x23_net',
4036 
          'from_register5_data_out' => 'data_out_x24_net',
4037 
          'from_register6_data_out' => 'data_out_x25_net',
4038 
          'from_register7_data_out' => 'data_out_x26_net',
4039 
          'from_register8_data_out' => 'data_out_x27_net',
4040 
          'from_register9_data_out' => 'data_out_x28_net',
4041 
          'from_register_data_out' => 'from_register_data_out_net',
4042 
          'rst_i' => 'rst_i_net',
4043 
          'rst_o' => 'rst_o_net',
4044 
          'to_register10_ce' => 'ce_1_sg_x0',
4045 
          'to_register10_clk' => 'clk_1_sg_x0',
4046 
          'to_register10_clr' => [
4047 
            'constant',
4048 
            '\'0\'',
4049 
          ],
4050 
          'to_register10_data_in' => 'data_in_x1_net',
4051 
          'to_register10_dout' => 'to_register10_dout_net',
4052 
          'to_register10_en' => 'constant6_op_net_x2',
4053 
          'to_register11_ce' => 'ce_1_sg_x0',
4054 
          'to_register11_clk' => 'clk_1_sg_x0',
4055 
          'to_register11_clr' => [
4056 
            'constant',
4057 
            '\'0\'',
4058 
          ],
4059 
          'to_register11_data_in' => 'data_in_x2_net',
4060 
          'to_register11_dout' => 'to_register11_dout_net',
4061 
          'to_register11_en' => 'constant6_op_net_x3',
4062 
          'to_register12_ce' => 'ce_1_sg_x0',
4063 
          'to_register12_clk' => 'clk_1_sg_x0',
4064 
          'to_register12_clr' => [
4065 
            'constant',
4066 
            '\'0\'',
4067 
          ],
4068 
          'to_register12_data_in' => 'data_in_x3_net',
4069 
          'to_register12_dout' => 'to_register12_dout_net',
4070 
          'to_register12_en' => 'constant6_op_net_x4',
4071 
          'to_register13_ce' => 'ce_1_sg_x0',
4072 
          'to_register13_clk' => 'clk_1_sg_x0',
4073 
          'to_register13_clr' => [
4074 
            'constant',
4075 
            '\'0\'',
4076 
          ],
4077 
          'to_register13_data_in' => 'data_in_x4_net',
4078 
          'to_register13_dout' => 'to_register13_dout_net',
4079 
          'to_register13_en' => 'constant6_op_net_x5',
4080 
          'to_register14_ce' => 'ce_1_sg_x0',
4081 
          'to_register14_clk' => 'clk_1_sg_x0',
4082 
          'to_register14_clr' => [
4083 
            'constant',
4084 
            '\'0\'',
4085 
          ],
4086 
          'to_register14_data_in' => 'data_in_x5_net',
4087 
          'to_register14_dout' => 'to_register14_dout_net',
4088 
          'to_register14_en' => 'constant6_op_net_x6',
4089 
          'to_register15_ce' => 'ce_1_sg_x0',
4090 
          'to_register15_clk' => 'clk_1_sg_x0',
4091 
          'to_register15_clr' => [
4092 
            'constant',
4093 
            '\'0\'',
4094 
          ],
4095 
          'to_register15_data_in' => 'data_in_x6_net',
4096 
          'to_register15_dout' => 'to_register15_dout_net',
4097 
          'to_register15_en' => 'constant6_op_net_x7',
4098 
          'to_register16_ce' => 'ce_1_sg_x0',
4099 
          'to_register16_clk' => 'clk_1_sg_x0',
4100 
          'to_register16_clr' => [
4101 
            'constant',
4102 
            '\'0\'',
4103 
          ],
4104 
          'to_register16_data_in' => 'data_in_x7_net',
4105 
          'to_register16_dout' => 'to_register16_dout_net',
4106 
          'to_register16_en' => 'constant6_op_net_x8',
4107 
          'to_register17_ce' => 'ce_1_sg_x0',
4108 
          'to_register17_clk' => 'clk_1_sg_x0',
4109 
          'to_register17_clr' => [
4110 
            'constant',
4111 
            '\'0\'',
4112 
          ],
4113 
          'to_register17_data_in' => 'data_in_x8_net',
4114 
          'to_register17_dout' => 'to_register17_dout_net',
4115 
          'to_register17_en' => 'constant6_op_net_x9',
4116 
          'to_register18_ce' => 'ce_1_sg_x0',
4117 
          'to_register18_clk' => 'clk_1_sg_x0',
4118 
          'to_register18_clr' => [
4119 
            'constant',
4120 
            '\'0\'',
4121 
          ],
4122 
          'to_register18_data_in' => 'data_in_x9_net',
4123 
          'to_register18_dout' => 'to_register18_dout_net',
4124 
          'to_register18_en' => 'constant6_op_net_x10',
4125 
          'to_register19_ce' => 'ce_1_sg_x0',
4126 
          'to_register19_clk' => 'clk_1_sg_x0',
4127 
          'to_register19_clr' => [
4128 
            'constant',
4129 
            '\'0\'',
4130 
          ],
4131 
          'to_register19_data_in' => 'data_in_x10_net',
4132 
          'to_register19_dout' => 'to_register19_dout_net',
4133 
          'to_register19_en' => 'constant6_op_net_x11',
4134 
          'to_register1_ce' => 'ce_1_sg_x0',
4135 
          'to_register1_clk' => 'clk_1_sg_x0',
4136 
          'to_register1_clr' => [
4137 
            'constant',
4138 
            '\'0\'',
4139 
          ],
4140 
          'to_register1_data_in' => 'data_in_x0_net',
4141 
          'to_register1_dout' => 'to_register1_dout_net',
4142 
          'to_register1_en' => 'constant6_op_net_x1',
4143 
          'to_register20_ce' => 'ce_1_sg_x0',
4144 
          'to_register20_clk' => 'clk_1_sg_x0',
4145 
          'to_register20_clr' => [
4146 
            'constant',
4147 
            '\'0\'',
4148 
          ],
4149 
          'to_register20_data_in' => 'data_in_x12_net',
4150 
          'to_register20_dout' => 'to_register20_dout_net',
4151 
          'to_register20_en' => 'constant6_op_net_x13',
4152 
          'to_register21_ce' => 'ce_1_sg_x0',
4153 
          'to_register21_clk' => 'clk_1_sg_x0',
4154 
          'to_register21_clr' => [
4155 
            'constant',
4156 
            '\'0\'',
4157 
          ],
4158 
          'to_register21_data_in' => 'data_in_x13_net',
4159 
          'to_register21_dout' => 'to_register21_dout_net',
4160 
          'to_register21_en' => 'constant6_op_net_x14',
4161 
          'to_register22_ce' => 'ce_1_sg_x0',
4162 
          'to_register22_clk' => 'clk_1_sg_x0',
4163 
          'to_register22_clr' => [
4164 
            'constant',
4165 
            '\'0\'',
4166 
          ],
4167 
          'to_register22_data_in' => 'data_in_x14_net',
4168 
          'to_register22_dout' => 'to_register22_dout_net',
4169 
          'to_register22_en' => 'constant6_op_net_x15',
4170 
          'to_register23_ce' => 'ce_1_sg_x0',
4171 
          'to_register23_clk' => 'clk_1_sg_x0',
4172 
          'to_register23_clr' => [
4173 
            'constant',
4174 
            '\'0\'',
4175 
          ],
4176 
          'to_register23_data_in' => 'data_in_x15_net',
4177 
          'to_register23_dout' => 'to_register23_dout_net',
4178 
          'to_register23_en' => 'constant6_op_net_x16',
4179 
          'to_register24_ce' => 'ce_1_sg_x0',
4180 
          'to_register24_clk' => 'clk_1_sg_x0',
4181 
          'to_register24_clr' => [
4182 
            'constant',
4183 
            '\'0\'',
4184 
          ],
4185 
          'to_register24_data_in' => 'data_in_x16_net',
4186 
          'to_register24_dout' => 'to_register24_dout_net',
4187 
          'to_register24_en' => 'constant6_op_net_x17',
4188 
          'to_register25_ce' => 'ce_1_sg_x0',
4189 
          'to_register25_clk' => 'clk_1_sg_x0',
4190 
          'to_register25_clr' => [
4191 
            'constant',
4192 
            '\'0\'',
4193 
          ],
4194 
          'to_register25_data_in' => 'data_in_x17_net',
4195 
          'to_register25_dout' => 'to_register25_dout_net',
4196 
          'to_register25_en' => 'constant6_op_net_x18',
4197 
          'to_register26_ce' => 'ce_1_sg_x0',
4198 
          'to_register26_clk' => 'clk_1_sg_x0',
4199 
          'to_register26_clr' => [
4200 
            'constant',
4201 
            '\'0\'',
4202 
          ],
4203 
          'to_register26_data_in' => 'data_in_x18_net',
4204 
          'to_register26_dout' => 'to_register26_dout_net',
4205 
          'to_register26_en' => 'constant6_op_net_x19',
4206 
          'to_register27_ce' => 'ce_1_sg_x0',
4207 
          'to_register27_clk' => 'clk_1_sg_x0',
4208 
          'to_register27_clr' => [
4209 
            'constant',
4210 
            '\'0\'',
4211 
          ],
4212 
          'to_register27_data_in' => 'data_in_x19_net',
4213 
          'to_register27_dout' => 'to_register27_dout_net',
4214 
          'to_register27_en' => 'constant6_op_net_x20',
4215 
          'to_register2_ce' => 'ce_1_sg_x0',
4216 
          'to_register2_clk' => 'clk_1_sg_x0',
4217 
          'to_register2_clr' => [
4218 
            'constant',
4219 
            '\'0\'',
4220 
          ],
4221 
          'to_register2_data_in' => 'data_in_x11_net',
4222 
          'to_register2_dout' => 'to_register2_dout_net',
4223 
          'to_register2_en' => 'constant6_op_net_x12',
4224 
          'to_register3_ce' => 'ce_1_sg_x0',
4225 
          'to_register3_clk' => 'clk_1_sg_x0',
4226 
          'to_register3_clr' => [
4227 
            'constant',
4228 
            '\'0\'',
4229 
          ],
4230 
          'to_register3_data_in' => 'data_in_x20_net',
4231 
          'to_register3_dout' => 'to_register3_dout_net',
4232 
          'to_register3_en' => 'constant6_op_net_x21',
4233 
          'to_register4_ce' => 'ce_1_sg_x0',
4234 
          'to_register4_clk' => 'clk_1_sg_x0',
4235 
          'to_register4_clr' => [
4236 
            'constant',
4237 
            '\'0\'',
4238 
          ],
4239 
          'to_register4_data_in' => 'data_in_x21_net',
4240 
          'to_register4_dout' => 'to_register4_dout_net',
4241 
          'to_register4_en' => 'constant6_op_net_x22',
4242 
          'to_register5_ce' => 'ce_1_sg_x0',
4243 
          'to_register5_clk' => 'clk_1_sg_x0',
4244 
          'to_register5_clr' => [
4245 
            'constant',
4246 
            '\'0\'',
4247 
          ],
4248 
          'to_register5_data_in' => 'data_in_x22_net',
4249 
          'to_register5_dout' => 'to_register5_dout_net',
4250 
          'to_register5_en' => 'constant6_op_net_x23',
4251 
          'to_register6_ce' => 'ce_1_sg_x0',
4252 
          'to_register6_clk' => 'clk_1_sg_x0',
4253 
          'to_register6_clr' => [
4254 
            'constant',
4255 
            '\'0\'',
4256 
          ],
4257 
          'to_register6_data_in' => 'data_in_x23_net',
4258 
          'to_register6_dout' => 'to_register6_dout_net',
4259 
          'to_register6_en' => 'constant6_op_net_x24',
4260 
          'to_register7_ce' => 'ce_1_sg_x0',
4261 
          'to_register7_clk' => 'clk_1_sg_x0',
4262 
          'to_register7_clr' => [
4263 
            'constant',
4264 
            '\'0\'',
4265 
          ],
4266 
          'to_register7_data_in' => 'data_in_x24_net',
4267 
          'to_register7_dout' => 'to_register7_dout_net',
4268 
          'to_register7_en' => 'constant6_op_net_x25',
4269 
          'to_register8_ce' => 'ce_1_sg_x0',
4270 
          'to_register8_clk' => 'clk_1_sg_x0',
4271 
          'to_register8_clr' => [
4272 
            'constant',
4273 
            '\'0\'',
4274 
          ],
4275 
          'to_register8_data_in' => 'data_in_x25_net',
4276 
          'to_register8_dout' => 'to_register8_dout_net',
4277 
          'to_register8_en' => 'constant6_op_net_x26',
4278 
          'to_register9_ce' => 'ce_1_sg_x0',
4279 
          'to_register9_clk' => 'clk_1_sg_x0',
4280 
          'to_register9_clr' => [
4281 
            'constant',
4282 
            '\'0\'',
4283 
          ],
4284 
          'to_register9_data_in' => 'data_in_x26_net',
4285 
          'to_register9_dout' => 'to_register9_dout_net',
4286 
          'to_register9_en' => 'constant6_op_net_x27',
4287 
          'to_register_ce' => 'ce_1_sg_x0',
4288 
          'to_register_clk' => 'clk_1_sg_x0',
4289 
          'to_register_clr' => [
4290 
            'constant',
4291 
            '\'0\'',
4292 
          ],
4293 
          'to_register_data_in' => 'data_in_net',
4294 
          'to_register_dout' => 'to_register_dout_net',
4295 
          'to_register_en' => 'constant6_op_net_x0',
4296 
          'user_int_1o' => 'user_int_1o_net',
4297 
          'user_int_2o' => 'user_int_2o_net',
4298 
          'user_int_3o' => 'user_int_3o_net',
4299 
        },
4300 
        'entityName' => 'user_logic_cw',
4301 
        'nets' => {
4302 
          'bram_rd_addr_net' => {
4303 
            'attributes' => {
4304 
              'hdlNetAttributes' => [
4305 
              ],
4306 
            },
4307 
            'hdlType' => 'std_logic_vector(11 downto 0)',
4308 
            'width' => 12,
4309 
          },
4310 
          'bram_rd_dout_net' => {
4311 
            'attributes' => {
4312 
              'hdlNetAttributes' => [
4313 
              ],
4314 
            },
4315 
            'hdlType' => 'std_logic_vector(63 downto 0)',
4316 
            'width' => 64,
4317 
          },
4318 
          'bram_wr_addr_net' => {
4319 
            'attributes' => {
4320 
              'hdlNetAttributes' => [
4321 
              ],
4322 
            },
4323 
            'hdlType' => 'std_logic_vector(11 downto 0)',
4324 
            'width' => 12,
4325 
          },
4326 
          'bram_wr_din_net' => {
4327 
            'attributes' => {
4328 
              'hdlNetAttributes' => [
4329 
              ],
4330 
            },
4331 
            'hdlType' => 'std_logic_vector(63 downto 0)',
4332 
            'width' => 64,
4333 
          },
4334 
          'bram_wr_en_net' => {
4335 
            'attributes' => {
4336 
              'hdlNetAttributes' => [
4337 
              ],
4338 
            },
4339 
            'hdlType' => 'std_logic_vector(7 downto 0)',
4340 
            'width' => 8,
4341 
          },
4342 
          'ce_1_sg_x0' => {
4343 
            'attributes' => {
4344 
              'hdlNetAttributes' => [
4345 
                [
4346 
                  'MAX_FANOUT',
4347 
                  'string',
4348 
                  '"REDUCE"',
4349 
                ],
4350 
              ],
4351 
            },
4352 
            'hdlType' => 'std_logic',
4353 
            'width' => 1,
4354 
          },
4355 
          'clkNet' => {
4356 
            'attributes' => {
4357 
              'hdlNetAttributes' => [
4358 
              ],
4359 
            },
4360 
            'hdlType' => 'std_logic',
4361 
            'width' => 1,
4362 
          },
4363 
          'clk_1_sg_x0' => {
4364 
            'attributes' => {
4365 
              'hdlNetAttributes' => [
4366 
              ],
4367 
            },
4368 
            'hdlType' => 'std_logic',
4369 
            'width' => 1,
4370 
          },
4371 
          'constant6_op_net_x0' => {
4372 
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4373 
              'hdlNetAttributes' => [
4374 
              ],
4375 
            },
4376 
            'hdlType' => 'std_logic',
4377 
            'width' => 1,
4378 
          },
4379 
          'constant6_op_net_x1' => {
4380 
            'attributes' => {
4381 
              'hdlNetAttributes' => [
4382 
              ],
4383 
            },
4384 
            'hdlType' => 'std_logic',
4385 
            'width' => 1,
4386 
          },
4387 
          'constant6_op_net_x10' => {
4388 
            'attributes' => {
4389 
              'hdlNetAttributes' => [
4390 
              ],
4391 
            },
4392 
            'hdlType' => 'std_logic',
4393 
            'width' => 1,
4394 
          },
4395 
          'constant6_op_net_x11' => {
4396 
            'attributes' => {
4397 
              'hdlNetAttributes' => [
4398 
              ],
4399 
            },
4400 
            'hdlType' => 'std_logic',
4401 
            'width' => 1,
4402 
          },
4403 
          'constant6_op_net_x12' => {
4404 
            'attributes' => {
4405 
              'hdlNetAttributes' => [
4406 
              ],
4407 
            },
4408 
            'hdlType' => 'std_logic',
4409 
            'width' => 1,
4410 
          },
4411 
          'constant6_op_net_x13' => {
4412 
            'attributes' => {
4413 
              'hdlNetAttributes' => [
4414 
              ],
4415 
            },
4416 
            'hdlType' => 'std_logic',
4417 
            'width' => 1,
4418 
          },
4419 
          'constant6_op_net_x14' => {
4420 
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4421 
              'hdlNetAttributes' => [
4422 
              ],
4423 
            },
4424 
            'hdlType' => 'std_logic',
4425 
            'width' => 1,
4426 
          },
4427 
          'constant6_op_net_x15' => {
4428 
            'attributes' => {
4429 
              'hdlNetAttributes' => [
4430 
              ],
4431 
            },
4432 
            'hdlType' => 'std_logic',
4433 
            'width' => 1,
4434 
          },
4435 
          'constant6_op_net_x16' => {
4436 
            'attributes' => {
4437 
              'hdlNetAttributes' => [
4438 
              ],
4439 
            },
4440 
            'hdlType' => 'std_logic',
4441 
            'width' => 1,
4442 
          },
4443 
          'constant6_op_net_x17' => {
4444 
            'attributes' => {
4445 
              'hdlNetAttributes' => [
4446 
              ],
4447 
            },
4448 
            'hdlType' => 'std_logic',
4449 
            'width' => 1,
4450 
          },
4451 
          'constant6_op_net_x18' => {
4452 
            'attributes' => {
4453 
              'hdlNetAttributes' => [
4454 
              ],
4455 
            },
4456 
            'hdlType' => 'std_logic',
4457 
            'width' => 1,
4458 
          },
4459 
          'constant6_op_net_x19' => {
4460 
            'attributes' => {
4461 
              'hdlNetAttributes' => [
4462 
              ],
4463 
            },
4464 
            'hdlType' => 'std_logic',
4465 
            'width' => 1,
4466 
          },
4467 
          'constant6_op_net_x2' => {
4468 
            'attributes' => {
4469 
              'hdlNetAttributes' => [
4470 
              ],
4471 
            },
4472 
            'hdlType' => 'std_logic',
4473 
            'width' => 1,
4474 
          },
4475 
          'constant6_op_net_x20' => {
4476 
            'attributes' => {
4477 
              'hdlNetAttributes' => [
4478 
              ],
4479 
            },
4480 
            'hdlType' => 'std_logic',
4481 
            'width' => 1,
4482 
          },
4483 
          'constant6_op_net_x21' => {
4484 
            'attributes' => {
4485 
              'hdlNetAttributes' => [
4486 
              ],
4487 
            },
4488 
            'hdlType' => 'std_logic',
4489 
            'width' => 1,
4490 
          },
4491 
          'constant6_op_net_x22' => {
4492 
            'attributes' => {
4493 
              'hdlNetAttributes' => [
4494 
              ],
4495 
            },
4496 
            'hdlType' => 'std_logic',
4497 
            'width' => 1,
4498 
          },
4499 
          'constant6_op_net_x23' => {
4500 
            'attributes' => {
4501 
              'hdlNetAttributes' => [
4502 
              ],
4503 
            },
4504 
            'hdlType' => 'std_logic',
4505 
            'width' => 1,
4506 
          },
4507 
          'constant6_op_net_x24' => {
4508 
            'attributes' => {
4509 
              'hdlNetAttributes' => [
4510 
              ],
4511 
            },
4512 
            'hdlType' => 'std_logic',
4513 
            'width' => 1,
4514 
          },
4515 
          'constant6_op_net_x25' => {
4516 
            'attributes' => {
4517 
              'hdlNetAttributes' => [
4518 
              ],
4519 
            },
4520 
            'hdlType' => 'std_logic',
4521 
            'width' => 1,
4522 
          },
4523 
          'constant6_op_net_x26' => {
4524 
            'attributes' => {
4525 
              'hdlNetAttributes' => [
4526 
              ],
4527 
            },
4528 
            'hdlType' => 'std_logic',
4529 
            'width' => 1,
4530 
          },
4531 
          'constant6_op_net_x27' => {
4532 
            'attributes' => {
4533 
              'hdlNetAttributes' => [
4534 
              ],
4535 
            },
4536 
            'hdlType' => 'std_logic',
4537 
            'width' => 1,
4538 
          },
4539 
          'constant6_op_net_x3' => {
4540 
            'attributes' => {
4541 
              'hdlNetAttributes' => [
4542 
              ],
4543 
            },
4544 
            'hdlType' => 'std_logic',
4545 
            'width' => 1,
4546 
          },
4547 
          'constant6_op_net_x4' => {
4548 
            'attributes' => {
4549 
              'hdlNetAttributes' => [
4550 
              ],
4551 
            },
4552 
            'hdlType' => 'std_logic',
4553 
            'width' => 1,
4554 
          },
4555 
          'constant6_op_net_x5' => {
4556 
            'attributes' => {
4557 
              'hdlNetAttributes' => [
4558 
              ],
4559 
            },
4560 
            'hdlType' => 'std_logic',
4561 
            'width' => 1,
4562 
          },
4563 
          'constant6_op_net_x6' => {
4564 
            'attributes' => {
4565 
              'hdlNetAttributes' => [
4566 
              ],
4567 
            },
4568 
            'hdlType' => 'std_logic',
4569 
            'width' => 1,
4570 
          },
4571 
          'constant6_op_net_x7' => {
4572 
            'attributes' => {
4573 
              'hdlNetAttributes' => [
4574 
              ],
4575 
            },
4576 
            'hdlType' => 'std_logic',
4577 
            'width' => 1,
4578 
          },
4579 
          'constant6_op_net_x8' => {
4580 
            'attributes' => {
4581 
              'hdlNetAttributes' => [
4582 
              ],
4583 
            },
4584 
            'hdlType' => 'std_logic',
4585 
            'width' => 1,
4586 
          },
4587 
          'constant6_op_net_x9' => {
4588 
            'attributes' => {
4589 
              'hdlNetAttributes' => [
4590 
              ],
4591 
            },
4592 
            'hdlType' => 'std_logic',
4593 
            'width' => 1,
4594 
          },
4595 
          'data_in_net' => {
4596 
            'attributes' => {
4597 
              'hdlNetAttributes' => [
4598 
              ],
4599 
            },
4600 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4601 
            'width' => 32,
4602 
          },
4603 
          'data_in_x0_net' => {
4604 
            'attributes' => {
4605 
              'hdlNetAttributes' => [
4606 
              ],
4607 
            },
4608 
            'hdlType' => 'std_logic',
4609 
            'width' => 1,
4610 
          },
4611 
          'data_in_x10_net' => {
4612 
            'attributes' => {
4613 
              'hdlNetAttributes' => [
4614 
              ],
4615 
            },
4616 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4617 
            'width' => 32,
4618 
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4619 
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4620 
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4621 
              'hdlNetAttributes' => [
4622 
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4623 
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4624 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4625 
            'width' => 32,
4626 
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4627 
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4628 
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4629 
              'hdlNetAttributes' => [
4630 
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4631 
            },
4632 
            'hdlType' => 'std_logic',
4633 
            'width' => 1,
4634 
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4635 
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4636 
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4637 
              'hdlNetAttributes' => [
4638 
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4639 
            },
4640 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4641 
            'width' => 32,
4642 
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4643 
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4644 
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4645 
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4646 
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4647 
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4648 
            'hdlType' => 'std_logic',
4649 
            'width' => 1,
4650 
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4651 
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4652 
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4653 
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4654 
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4655 
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4656 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4657 
            'width' => 32,
4658 
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4659 
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4660 
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4661 
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4662 
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4663 
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4664 
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4665 
            'width' => 1,
4666 
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4667 
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4668 
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4669 
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4670 
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4671 
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4672 
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4673 
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4674 
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4675 
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4676 
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4677 
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4678 
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4679 
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4680 
            'hdlType' => 'std_logic',
4681 
            'width' => 1,
4682 
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4683 
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4684 
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4685 
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4686 
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4687 
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4688 
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4689 
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4690 
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4691 
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4692 
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4693 
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4694 
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4695 
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4696 
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4697 
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4698 
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4699 
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4700 
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4701 
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4702 
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4703 
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4704 
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4705 
            'width' => 32,
4706 
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4707 
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4708 
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4709 
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4710 
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4711 
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4712 
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4713 
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4714 
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4715 
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4716 
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4717 
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4718 
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4719 
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4720 
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4721 
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4723 
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4724 
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4725 
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4726 
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4727 
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4728 
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4729 
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4730 
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4731 
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4732 
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4733 
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4734 
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4735 
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4736 
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4737 
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4738 
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4739 
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4740 
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4741 
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4743 
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4746 
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4748 
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4749 
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4751 
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4752 
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4753 
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4754 
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4755 
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4756 
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4757 
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4758 
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4759 
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4760 
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4761 
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4762 
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4763 
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4764 
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4765 
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4767 
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4768 
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4769 
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4771 
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4772 
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4773 
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4774 
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4775 
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4776 
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4777 
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4778 
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4779 
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4780 
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4781 
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4782 
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4783 
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4784 
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4785 
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4786 
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4787 
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4788 
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4789 
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4796 
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4797 
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4799 
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4801 
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4803 
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4804 
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4805 
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4806 
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4807 
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4809 
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4811 
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4812 
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4813 
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4814 
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4815 
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4816 
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4817 
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4818 
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4819 
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4820 
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4821 
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4822 
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4823 
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4824 
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4825 
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5468 
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5469 
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5650 
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8590 
              'bin_pt' => 0,
8591 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
8592 
              'is_floating_block' => 1,
8593 
              'is_gateway_port' => 1,
8594 
              'must_be_hdl_vector' => 1,
8595 
              'period' => 1,
8596 
              'port_id' => 0,
8597 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
8598 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
8599 
              'timingConstraint' => 'none',
8600 
              'type' => 'Bool',
8601 
            },
8602 
            'direction' => 'out',
8603 
            'hdlType' => 'std_logic',
8604 
            'width' => 1,
8605 
          },
8606 
          'user_int_2o' => {
8607 
            'attributes' => {
8608 
              'bin_pt' => 0,
8609 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
8610 
              'is_floating_block' => 1,
8611 
              'is_gateway_port' => 1,
8612 
              'must_be_hdl_vector' => 1,
8613 
              'period' => 1,
8614 
              'port_id' => 0,
8615 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
8616 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
8617 
              'timingConstraint' => 'none',
8618 
              'type' => 'Bool',
8619 
            },
8620 
            'direction' => 'out',
8621 
            'hdlType' => 'std_logic',
8622 
            'width' => 1,
8623 
          },
8624 
          'user_int_3o' => {
8625 
            'attributes' => {
8626 
              'bin_pt' => 0,
8627 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
8628 
              'is_floating_block' => 1,
8629 
              'is_gateway_port' => 1,
8630 
              'must_be_hdl_vector' => 1,
8631 
              'period' => 1,
8632 
              'port_id' => 0,
8633 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
8634 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
8635 
              'timingConstraint' => 'none',
8636 
              'type' => 'Bool',
8637 
            },
8638 
            'direction' => 'out',
8639 
            'hdlType' => 'std_logic',
8640 
            'width' => 1,
8641 
          },
8642 
        },
8643 
        'subblocks' => {
8644 
          'default_clock_driver_x0' => {
8645 
            'connections' => {
8646 
              'ce_1' => 'ce_1_sg_x0',
8647 
              'clk_1' => 'clk_1_sg_x0',
8648 
              'sysce' => [
8649 
                'constant',
8650 
                '\'1\'',
8651 
              ],
8652 
              'sysce_clr' => [
8653 
                'constant',
8654 
                '\'0\'',
8655 
              ],
8656 
              'sysclk' => 'clkNet',
8657 
            },
8658 
            'entity' => {
8659 
              'attributes' => {
8660 
                'domain' => 'default',
8661 
                'hdlArchAttributes' => [
8662 
                  [
8663 
                    'syn_noprune',
8664 
                    'boolean',
8665 
                    'true',
8666 
                  ],
8667 
                  [
8668 
                    'optimize_primitives',
8669 
                    'boolean',
8670 
                    'false',
8671 
                  ],
8672 
                  [
8673 
                    'dont_touch',
8674 
                    'boolean',
8675 
                    'true',
8676 
                  ],
8677 
                ],
8678 
                'hdlEntityAttributes' => [
8679 
                ],
8680 
                'isClkDriver' => 1,
8681 
              },
8682 
              'entityName' => 'default_clock_driver',
8683 
              'ports' => {
8684 
                'ce_1' => {
8685 
                  'attributes' => {
8686 
                    'domain' => 'default',
8687 
                    'group' => 1,
8688 
                    'isCe' => 1,
8689 
                    'period' => 1,
8690 
                    'type' => 'logic',
8691 
                  },
8692 
                  'direction' => 'out',
8693 
                  'hdlType' => 'std_logic',
8694 
                  'width' => 1,
8695 
                },
8696 
                'clk_1' => {
8697 
                  'attributes' => {
8698 
                    'domain' => 'default',
8699 
                    'group' => 1,
8700 
                    'isClk' => 1,
8701 
                    'period' => 1,
8702 
                    'type' => 'logic',
8703 
                  },
8704 
                  'direction' => 'out',
8705 
                  'hdlType' => 'std_logic',
8706 
                  'width' => 1,
8707 
                },
8708 
                'sysce' => {
8709 
                  'attributes' => {
8710 
                    'group' => 6,
8711 
                    'isCe' => 1,
8712 
                    'period' => 1,
8713 
                  },
8714 
                  'direction' => 'in',
8715 
                  'hdlType' => 'std_logic',
8716 
                  'width' => 1,
8717 
                },
8718 
                'sysce_clr' => {
8719 
                  'attributes' => {
8720 
                    'group' => 6,
8721 
                    'isClr' => 1,
8722 
                    'period' => 1,
8723 
                  },
8724 
                  'direction' => 'in',
8725 
                  'hdlType' => 'std_logic',
8726 
                  'width' => 1,
8727 
                },
8728 
                'sysclk' => {
8729 
                  'attributes' => {
8730 
                    'group' => 6,
8731 
                    'isClk' => 1,
8732 
                    'period' => 1,
8733 
                  },
8734 
                  'direction' => 'in',
8735 
                  'hdlType' => 'std_logic',
8736 
                  'width' => 1,
8737 
                },
8738 
              },
8739 
            },
8740 
            'entityName' => 'default_clock_driver',
8741 
          },
8742 
          'persistentdff_inst' => {
8743 
            'connections' => {
8744 
              'clk' => 'clkNet',
8745 
              'd' => 'persistentdff_inst_q',
8746 
              'q' => 'persistentdff_inst_q',
8747 
            },
8748 
            'entity' => {
8749 
              'attributes' => {
8750 
                'entityAlreadyNetlisted' => 1,
8751 
                'hdlCompAttributes' => [
8752 
                  [
8753 
                    'syn_black_box',
8754 
                    'boolean',
8755 
                    'true',
8756 
                  ],
8757 
                  [
8758 
                    'box_type',
8759 
                    'string',
8760 
                    '"black_box"',
8761 
                  ],
8762 
                ],
8763 
                'is_persistent_dff' => 1,
8764 
                'needsComponentDeclaration' => 1,
8765 
              },
8766 
              'entityName' => 'xlpersistentdff',
8767 
              'ports' => {
8768 
                'clk' => {
8769 
                  'direction' => 'in',
8770 
                  'hdlType' => 'std_logic',
8771 
                  'width' => 1,
8772 
                },
8773 
                'd' => {
8774 
                  'direction' => 'in',
8775 
                  'hdlType' => 'std_logic',
8776 
                  'width' => 1,
8777 
                },
8778 
                'q' => {
8779 
                  'direction' => 'out',
8780 
                  'hdlType' => 'std_logic',
8781 
                  'width' => 1,
8782 
                },
8783 
              },
8784 
            },
8785 
            'entityName' => 'xlpersistentdff',
8786 
          },
8787 
          'user_logic_x0' => {
8788 
            'connections' => {
8789 
              'bram_rd_addr' => 'bram_rd_addr_net',
8790 
              'bram_rd_dout' => 'bram_rd_dout_net',
8791 
              'bram_wr_addr' => 'bram_wr_addr_net',
8792 
              'bram_wr_din' => 'bram_wr_din_net',
8793 
              'bram_wr_en' => 'bram_wr_en_net',
8794 
              'ce_1' => 'ce_1_sg_x0',
8795 
              'clk_1' => 'clk_1_sg_x0',
8796 
              'data_in' => 'data_in_net',
8797 
              'data_in_x0' => 'data_in_x0_net',
8798 
              'data_in_x1' => 'data_in_x1_net',
8799 
              'data_in_x10' => 'data_in_x10_net',
8800 
              'data_in_x11' => 'data_in_x11_net',
8801 
              'data_in_x12' => 'data_in_x12_net',
8802 
              'data_in_x13' => 'data_in_x13_net',
8803 
              'data_in_x14' => 'data_in_x14_net',
8804 
              'data_in_x15' => 'data_in_x15_net',
8805 
              'data_in_x16' => 'data_in_x16_net',
8806 
              'data_in_x17' => 'data_in_x17_net',
8807 
              'data_in_x18' => 'data_in_x18_net',
8808 
              'data_in_x19' => 'data_in_x19_net',
8809 
              'data_in_x2' => 'data_in_x2_net',
8810 
              'data_in_x20' => 'data_in_x20_net',
8811 
              'data_in_x21' => 'data_in_x21_net',
8812 
              'data_in_x22' => 'data_in_x22_net',
8813 
              'data_in_x23' => 'data_in_x23_net',
8814 
              'data_in_x24' => 'data_in_x24_net',
8815 
              'data_in_x25' => 'data_in_x25_net',
8816 
              'data_in_x26' => 'data_in_x26_net',
8817 
              'data_in_x3' => 'data_in_x3_net',
8818 
              'data_in_x4' => 'data_in_x4_net',
8819 
              'data_in_x5' => 'data_in_x5_net',
8820 
              'data_in_x6' => 'data_in_x6_net',
8821 
              'data_in_x7' => 'data_in_x7_net',
8822 
              'data_in_x8' => 'data_in_x8_net',
8823 
              'data_in_x9' => 'data_in_x9_net',
8824 
              'data_out' => 'data_out_net',
8825 
              'data_out_x0' => 'data_out_x0_net',
8826 
              'data_out_x1' => 'data_out_x1_net',
8827 
              'data_out_x10' => 'data_out_x10_net',
8828 
              'data_out_x11' => 'data_out_x11_net',
8829 
              'data_out_x12' => 'data_out_x12_net',
8830 
              'data_out_x13' => 'data_out_x13_net',
8831 
              'data_out_x14' => 'data_out_x14_net',
8832 
              'data_out_x15' => 'data_out_x15_net',
8833 
              'data_out_x16' => 'data_out_x16_net',
8834 
              'data_out_x17' => 'data_out_x17_net',
8835 
              'data_out_x18' => 'data_out_x18_net',
8836 
              'data_out_x19' => 'data_out_x19_net',
8837 
              'data_out_x2' => 'data_out_x2_net',
8838 
              'data_out_x20' => 'data_out_x20_net',
8839 
              'data_out_x21' => 'data_out_x21_net',
8840 
              'data_out_x22' => 'data_out_x22_net',
8841 
              'data_out_x23' => 'data_out_x23_net',
8842 
              'data_out_x24' => 'data_out_x24_net',
8843 
              'data_out_x25' => 'data_out_x25_net',
8844 
              'data_out_x26' => 'data_out_x26_net',
8845 
              'data_out_x27' => 'data_out_x27_net',
8846 
              'data_out_x28' => 'data_out_x28_net',
8847 
              'data_out_x3' => 'data_out_x3_net',
8848 
              'data_out_x6' => 'data_out_x6_net',
8849 
              'data_out_x7' => 'data_out_x7_net',
8850 
              'data_out_x8' => 'data_out_x8_net',
8851 
              'data_out_x9' => 'data_out_x9_net',
8852 
              'en' => 'constant6_op_net_x0',
8853 
              'en_x0' => 'constant6_op_net_x1',
8854 
              'en_x1' => 'constant6_op_net_x2',
8855 
              'en_x10' => 'constant6_op_net_x11',
8856 
              'en_x11' => 'constant6_op_net_x12',
8857 
              'en_x12' => 'constant6_op_net_x13',
8858 
              'en_x13' => 'constant6_op_net_x14',
8859 
              'en_x14' => 'constant6_op_net_x15',
8860 
              'en_x15' => 'constant6_op_net_x16',
8861 
              'en_x16' => 'constant6_op_net_x17',
8862 
              'en_x17' => 'constant6_op_net_x18',
8863 
              'en_x18' => 'constant6_op_net_x19',
8864 
              'en_x19' => 'constant6_op_net_x20',
8865 
              'en_x2' => 'constant6_op_net_x3',
8866 
              'en_x20' => 'constant6_op_net_x21',
8867 
              'en_x21' => 'constant6_op_net_x22',
8868 
              'en_x22' => 'constant6_op_net_x23',
8869 
              'en_x23' => 'constant6_op_net_x24',
8870 
              'en_x24' => 'constant6_op_net_x25',
8871 
              'en_x25' => 'constant6_op_net_x26',
8872 
              'en_x26' => 'constant6_op_net_x27',
8873 
              'en_x3' => 'constant6_op_net_x4',
8874 
              'en_x4' => 'constant6_op_net_x5',
8875 
              'en_x5' => 'constant6_op_net_x6',
8876 
              'en_x6' => 'constant6_op_net_x7',
8877 
              'en_x7' => 'constant6_op_net_x8',
8878 
              'en_x8' => 'constant6_op_net_x9',
8879 
              'en_x9' => 'constant6_op_net_x10',
8880 
              'fifo_rd_count' => 'fifo_rd_count_net',
8881 
              'fifo_rd_dout' => 'fifo_rd_dout_net',
8882 
              'fifo_rd_empty' => 'fifo_rd_empty_net',
8883 
              'fifo_rd_en' => 'fifo_rd_en_net',
8884 
              'fifo_rd_pempty' => 'fifo_rd_pempty_net',
8885 
              'fifo_rd_valid' => 'fifo_rd_valid_net',
8886 
              'fifo_wr_count' => 'fifo_wr_count_net',
8887 
              'fifo_wr_din' => 'fifo_wr_din_net',
8888 
              'fifo_wr_en' => 'fifo_wr_en_net',
8889 
              'fifo_wr_full' => 'fifo_wr_full_net',
8890 
              'fifo_wr_pfull' => 'fifo_wr_pfull_net',
8891 
              'rst_i' => 'rst_i_net',
8892 
              'rst_o' => 'rst_o_net',
8893 
              'user_int_1o' => 'user_int_1o_net',
8894 
              'user_int_2o' => 'user_int_2o_net',
8895 
              'user_int_3o' => 'user_int_3o_net',
8896 
            },
8897 
            'entity' => {
8898 
              'attributes' => {
8899 
                'entityAlreadyNetlisted' => 1,
8900 
                'hdlKind' => 'vhdl',
8901 
                'isDesign' => 1,
8902 
                'simulinkName' => 'USER_LOGIC',
8903 
              },
8904 
              'entityName' => 'user_logic',
8905 
              'ports' => {
8906 
                'bram_rd_addr' => {
8907 
                  'attributes' => {
8908 
                    'bin_pt' => 0,
8909 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
8910 
                    'is_floating_block' => 1,
8911 
                    'is_gateway_port' => 1,
8912 
                    'must_be_hdl_vector' => 1,
8913 
                    'period' => 1,
8914 
                    'port_id' => 15,
8915 
                    'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
8916 
                    'source_block' => 'USER_LOGIC',
8917 
                    'timingConstraint' => 'none',
8918 
                    'type' => 'UFix_12_0',
8919 
                  },
8920 
                  'direction' => 'out',
8921 
                  'hdlType' => 'std_logic_vector(11 downto 0)',
8922 
                  'width' => 12,
8923 
                },
8924 
                'bram_rd_dout' => {
8925 
                  'attributes' => {
8926 
                    'bin_pt' => 0,
8927 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
8928 
                    'is_floating_block' => 1,
8929 
                    'is_gateway_port' => 1,
8930 
                    'must_be_hdl_vector' => 1,
8931 
                    'period' => 1,
8932 
                    'port_id' => 0,
8933 
                    'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
8934 
                    'source_block' => 'USER_LOGIC',
8935 
                    'timingConstraint' => 'none',
8936 
                    'type' => 'UFix_64_0',
8937 
                  },
8938 
                  'direction' => 'in',
8939 
                  'hdlType' => 'std_logic_vector(63 downto 0)',
8940 
                  'width' => 64,
8941 
                },
8942 
                'bram_wr_addr' => {
8943 
                  'attributes' => {
8944 
                    'bin_pt' => 0,
8945 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
8946 
                    'is_floating_block' => 1,
8947 
                    'is_gateway_port' => 1,
8948 
                    'must_be_hdl_vector' => 1,
8949 
                    'period' => 1,
8950 
                    'port_id' => 16,
8951 
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
8952 
                    'source_block' => 'USER_LOGIC',
8953 
                    'timingConstraint' => 'none',
8954 
                    'type' => 'UFix_12_0',
8955 
                  },
8956 
                  'direction' => 'out',
8957 
                  'hdlType' => 'std_logic_vector(11 downto 0)',
8958 
                  'width' => 12,
8959 
                },
8960 
                'bram_wr_din' => {
8961 
                  'attributes' => {
8962 
                    'bin_pt' => 0,
8963 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
8964 
                    'is_floating_block' => 1,
8965 
                    'is_gateway_port' => 1,
8966 
                    'must_be_hdl_vector' => 1,
8967 
                    'period' => 1,
8968 
                    'port_id' => 18,
8969 
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
8970 
                    'source_block' => 'USER_LOGIC',
8971 
                    'timingConstraint' => 'none',
8972 
                    'type' => 'UFix_64_0',
8973 
                  },
8974 
                  'direction' => 'out',
8975 
                  'hdlType' => 'std_logic_vector(63 downto 0)',
8976 
                  'width' => 64,
8977 
                },
8978 
                'bram_wr_en' => {
8979 
                  'attributes' => {
8980 
                    'bin_pt' => 0,
8981 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
8982 
                    'is_floating_block' => 1,
8983 
                    'is_gateway_port' => 1,
8984 
                    'must_be_hdl_vector' => 1,
8985 
                    'period' => 1,
8986 
                    'port_id' => 23,
8987 
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
8988 
                    'source_block' => 'USER_LOGIC',
8989 
                    'timingConstraint' => 'none',
8990 
                    'type' => 'UFix_8_0',
8991 
                  },
8992 
                  'direction' => 'out',
8993 
                  'hdlType' => 'std_logic_vector(7 downto 0)',
8994 
                  'width' => 8,
8995 
                },
8996 
                'ce_1' => {
8997 
                  'attributes' => {
8998 
                    'domain' => '',
8999 
                    'group' => 1,
9000 
                    'isCe' => 1,
9001 
                    'is_subsys_port' => 1,
9002 
                    'period' => 1,
9003 
                    'subsys_port_index' => 0,
9004 
                    'type' => 'logic',
9005 
                  },
9006 
                  'direction' => 'in',
9007 
                  'hdlType' => 'std_logic',
9008 
                  'width' => 1,
9009 
                },
9010 
                'clk_1' => {
9011 
                  'attributes' => {
9012 
                    'domain' => '',
9013 
                    'group' => 1,
9014 
                    'isClk' => 1,
9015 
                    'is_subsys_port' => 1,
9016 
                    'period' => 1,
9017 
                    'subsys_port_index' => 0,
9018 
                    'type' => 'logic',
9019 
                  },
9020 
                  'direction' => 'in',
9021 
                  'hdlType' => 'std_logic',
9022 
                  'width' => 1,
9023 
                },
9024 
                'data_in' => {
9025 
                  'attributes' => {
9026 
                    'bin_pt' => 0,
9027 
                    'is_floating_block' => 1,
9028 
                    'must_be_hdl_vector' => 1,
9029 
                    'period' => 1,
9030 
                    'port_id' => 17,
9031 
                    'simulinkName' => 'USER_LOGIC/tx_en_in2',
9032 
                    'type' => 'UFix_32_0',
9033 
                  },
9034 
                  'direction' => 'out',
9035 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
9036 
                  'width' => 32,
9037 
                },
9038 
                'data_in_x0' => {
9039 
                  'attributes' => {
9040 
                    'bin_pt' => 0,
9041 
                    'is_floating_block' => 1,
9042 
                    'must_be_hdl_vector' => 1,
9043 
                    'period' => 1,
9044 
                    'port_id' => 1,
9045 
                    'simulinkName' => 'USER_LOGIC/tx_en_in1',
9046 
                    'type' => 'Bool',
9047 
                  },
9048 
                  'direction' => 'out',
9049 
                  'hdlType' => 'std_logic',
9050 
                  'width' => 1,
9051 
                },
9052 
                'data_in_x1' => {
9053 
                  'attributes' => {
9054 
                    'bin_pt' => 0,
9055 
                    'is_floating_block' => 1,
9056 
                    'must_be_hdl_vector' => 1,
9057 
                    'period' => 1,
9058 
                    'port_id' => 36,
9059 
                    'simulinkName' => 'USER_LOGIC/tx_en_in96',
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