OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [synopsis.1] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0.0,
4 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
5 
    'Impl_file' => 'ISE Defaults',
6 
    'Impl_file_sgadvanced' => '',
7 
    'Synth_file' => 'XST Defaults',
8 
    'Synth_file_sgadvanced' => '',
9 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
10 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
11 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
12 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
13 
    'base_system_period_hardware' => 5.0,
14 
    'base_system_period_simulink' => 5.0E-9,
15 
    'block_icon_display' => 'Default',
16 
    'block_type' => 'sysgen',
17 
    'block_version' => '',
18 
    'ce_clr' => 0.0,
19 
    'clock_loc' => '',
20 
    'clock_wrapper' => 'Clock Enables',
21 
    'clock_wrapper_sgadvanced' => '',
22 
    'compilation' => 'NGC Netlist',
23 
    'compilation_lut' => {
24 
      'keys' => [
25 
        'HDL Netlist',
26 
        'Bitstream',
27 
        'NGC Netlist',
28 
      ],
29 
      'values' => [
30 
        'target1',
31 
        'target2',
32 
        'target3',
33 
      ],
34 
    },
35 
    'compilation_target' => 'NGC Netlist',
36 
    'core_generation' => 1.0,
37 
    'core_generation_sgadvanced' => '',
38 
    'core_is_deployed' => 0.0,
39 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c03f93279696b19bd',
40 
    'coregen_part_family' => 'virtex6',
41 
    'createTestbench' => 0,
42 
    'create_interface_document' => 'off',
43 
    'dbl_ovrd' => -1.0,
44 
    'dbl_ovrd_sgadvanced' => '',
45 
    'dcm_info' => {},
46 
    'dcm_input_clock_period' => 5.0,
47 
    'deprecated_control' => 'off',
48 
    'deprecated_control_sgadvanced' => '',
49 
    'design' => 'user_logic',
50 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\pcie-v6-ml605_ISE12_OpenCores\\MySysGen\\PCIe_UserLogic_00.mdl',
51 
    'device' => 'xc6vlx240t-3ff784',
52 
    'device_speed' => '-3',
53 
    'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
54 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
55 
    'entityNamingInstrs' => {
56 
      'nameMap' => undef,
57 
      'namesAlreadyUsed' => undef,
58 
    },
59 
    'eval_field' => '0',
60 
    'fileAttributes' => {
61 
      'cntr_11_0_1a411d6ef586e892.ngc' => { 'producer' => 'coregen', },
62 
      'cntr_11_0_1a411d6ef586e892.vhd' => { 'producer' => 'coregen', },
63 
      'nonleaf_results.vhd' => { 'producer' => 'nonleafNetlister', },
64 
      'producer' => 'coregen',
65 
    },
66 
    'files' => [
67 
      'xlpersistentdff.ngc',
68 
      'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/perl_results.vhd',
69 
      'cntr_11_0_1a411d6ef586e892.ngc',
70 
      'cntr_11_0_1a411d6ef586e892.vhd',
71 
      'nonleaf_results.vhd',
72 
      'synopsis',
73 
    ],
74 
    'fxdptinstalled' => 1.0,
75 
    'generateUsing71FrontEnd' => 1,
76 
    'generating_island_subsystem_handle' => 261.0009765625,
77 
    'generating_subsystem_handle' => 261.0009765625,
78 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
79 
    'has_advanced_control' => '0',
80 
    'hdlDir' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl',
81 
    'hdlKind' => 'vhdl',
82 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
83 
    'impl_file' => 'ISE Defaults*',
84 
    'incr_netlist' => 'off',
85 
    'incr_netlist_sgadvanced' => '',
86 
    'infoedit' => ' System Generator',
87 
    'isdeployed' => 0,
88 
    'ise_version' => '12.3i',
89 
    'master_sysgen_token_handle' => 262.0009765625,
90 
    'matlab' => 'C:/Programmi/MATLAB/R2010a',
91 
    'matlab_fixedpoint' => 1.0,
92 
    'mdlHandle' => 3.0009765625,
93 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
94 
    'modelDiagnostics' => [
95 
      {
96 
        'count' => 339.0,
97 
        'isMask' => 0.0,
98 
        'type' => 'PCIe_UserLogic_00 Total blocks',
99 
      },
100 
      {
101 
        'count' => 4.0,
102 
        'isMask' => 0.0,
103 
        'type' => 'DiscretePulseGenerator',
104 
      },
105 
      {
106 
        'count' => 327.0,
107 
        'isMask' => 0.0,
108 
        'type' => 'S-Function',
109 
      },
110 
      {
111 
        'count' => 4.0,
112 
        'isMask' => 0.0,
113 
        'type' => 'SubSystem',
114 
      },
115 
      {
116 
        'count' => 4.0,
117 
        'isMask' => 0.0,
118 
        'type' => 'Terminator',
119 
      },
120 
      {
121 
        'count' => 23.0,
122 
        'isMask' => 1.0,
123 
        'type' => 'Xilinx Constant Block Block',
124 
      },
125 
      {
126 
        'count' => 1.0,
127 
        'isMask' => 1.0,
128 
        'type' => 'Xilinx Counter Block',
129 
      },
130 
      {
131 
        'count' => 44.0,
132 
        'isMask' => 1.0,
133 
        'type' => 'Xilinx Gateway In Block',
134 
      },
135 
      {
136 
        'count' => 39.0,
137 
        'isMask' => 1.0,
138 
        'type' => 'Xilinx Gateway Out Block',
139 
      },
140 
      {
141 
        'count' => 2.0,
142 
        'isMask' => 1.0,
143 
        'type' => 'Xilinx Inverter Block',
144 
      },
145 
      {
146 
        'count' => 1.0,
147 
        'isMask' => 1.0,
148 
        'type' => 'Xilinx Logical Block Block',
149 
      },
150 
      {
151 
        'count' => 78.0,
152 
        'isMask' => 1.0,
153 
        'type' => 'Xilinx Register Block',
154 
      },
155 
      {
156 
        'count' => 62.0,
157 
        'isMask' => 1.0,
158 
        'type' => 'Xilinx Shared Memory Based From Register Block',
159 
      },
160 
      {
161 
        'count' => 62.0,
162 
        'isMask' => 1.0,
163 
        'type' => 'Xilinx Shared Memory Based To Register Block',
164 
      },
165 
      {
166 
        'count' => 1.0,
167 
        'isMask' => 1.0,
168 
        'type' => 'Xilinx Subsystem Generator Block',
169 
      },
170 
      {
171 
        'count' => 2.0,
172 
        'isMask' => 1.0,
173 
        'type' => 'Xilinx System Generator Block',
174 
      },
175 
      {
176 
        'count' => 14.0,
177 
        'isMask' => 1.0,
178 
        'type' => 'Xilinx Type Converter Block',
179 
      },
180 
    ],
181 
    'model_globals_initialized' => 1.0,
182 
    'model_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
183 
    'myxilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
184 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
185 
    'ngc_config' => {
186 
      'include_cf' => 1,
187 
      'include_clockwrapper' => 1.0,
188 
    },
189 
    'ngc_files' => [ 'xlpersistentdff.ngc', ],
190 
    'num_sim_cycles' => '2000000000',
191 
    'package' => 'ff784',
192 
    'part' => 'xc6vlx240t',
193 
    'partFamily' => 'virtex6',
194 
    'port_data_types_enabled' => 1.0,
195 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
196 
    'preserve_hierarchy' => 0.0,
197 
    'proj_type' => 'Project Navigator',
198 
    'proj_type_sgadvanced' => '',
199 
    'run_coregen' => 'off',
200 
    'run_coregen_sgadvanced' => '',
201 
    'sample_time_colors_enabled' => 1.0,
202 
    'sampletimecolors' => 1.0,
203 
    'settings_fcn' => 'xlngcsettings',
204 
    'sg_blockgui_xml' => '',
205 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
206 
    'sg_list_contents' => '',
207 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
208 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
209 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
210 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
211 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
212 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
213 
fprintf(\'\',\'COMMENT: end icon graphics\');
214 
fprintf(\'\',\'COMMENT: begin icon text\');
215 
fprintf(\'\',\'COMMENT: end icon text\');',
216 
    'sg_version' => '',
217 
    'sggui_pos' => '-1,-1,-1,-1',
218 
    'simulation_island_subsystem_handle' => 261.0009765625,
219 
    'simulinkName' => 'parking_lot',
220 
    'simulink_accelerator_running' => 0.0,
221 
    'simulink_debugger_running' => 0.0,
222 
    'simulink_period' => 5.0E-9,
223 
    'speed' => '-3',
224 
    'synth_file' => 'XST Defaults*',
225 
    'synthesisTool' => 'XST',
226 
    'synthesis_language' => 'vhdl',
227 
    'synthesis_tool' => 'XST',
228 
    'synthesis_tool_sgadvanced' => '',
229 
    'sysclk_period' => 5.0,
230 
    'sysgen' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
231 
    'sysgenRoot' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
232 
    'sysgenTokenSettings' => {
233 
      'Impl_file' => 'ISE Defaults',
234 
      'Impl_file_sgadvanced' => '',
235 
      'Synth_file' => 'XST Defaults',
236 
      'Synth_file_sgadvanced' => '',
237 
      'base_system_period_hardware' => 5.0,
238 
      'base_system_period_simulink' => 5.0E-9,
239 
      'block_icon_display' => 'Default',
240 
      'block_type' => 'sysgen',
241 
      'block_version' => '',
242 
      'ce_clr' => 0.0,
243 
      'clock_loc' => '',
244 
      'clock_wrapper' => 'Clock Enables',
245 
      'clock_wrapper_sgadvanced' => '',
246 
      'compilation' => 'NGC Netlist',
247 
      'compilation_lut' => {
248 
        'keys' => [
249 
          'HDL Netlist',
250 
          'Bitstream',
251 
          'NGC Netlist',
252 
        ],
253 
        'values' => [
254 
          'target1',
255 
          'target2',
256 
          'target3',
257 
        ],
258 
      },
259 
      'core_generation' => 1.0,
260 
      'core_generation_sgadvanced' => '',
261 
      'coregen_part_family' => 'virtex6',
262 
      'create_interface_document' => 'off',
263 
      'dbl_ovrd' => -1.0,
264 
      'dbl_ovrd_sgadvanced' => '',
265 
      'dcm_input_clock_period' => 5.0,
266 
      'deprecated_control' => 'off',
267 
      'deprecated_control_sgadvanced' => '',
268 
      'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
269 
      'eval_field' => '0',
270 
      'has_advanced_control' => '0',
271 
      'impl_file' => 'ISE Defaults*',
272 
      'incr_netlist' => 'off',
273 
      'incr_netlist_sgadvanced' => '',
274 
      'infoedit' => ' System Generator',
275 
      'master_sysgen_token_handle' => 262.0009765625,
276 
      'ngc_config' => {
277 
        'include_cf' => 1,
278 
        'include_clockwrapper' => 1.0,
279 
      },
280 
      'package' => 'ff784',
281 
      'part' => 'xc6vlx240t',
282 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
283 
      'preserve_hierarchy' => 0.0,
284 
      'proj_type' => 'Project Navigator',
285 
      'proj_type_sgadvanced' => '',
286 
      'run_coregen' => 'off',
287 
      'run_coregen_sgadvanced' => '',
288 
      'settings_fcn' => 'xlngcsettings',
289 
      'sg_blockgui_xml' => '',
290 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
291 
      'sg_list_contents' => '',
292 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
293 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
294 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
295 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
296 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
297 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
298 
fprintf(\'\',\'COMMENT: end icon graphics\');
299 
fprintf(\'\',\'COMMENT: begin icon text\');
300 
fprintf(\'\',\'COMMENT: end icon text\');',
301 
      'sggui_pos' => '-1,-1,-1,-1',
302 
      'simulation_island_subsystem_handle' => 261.0009765625,
303 
      'simulink_period' => 5.0E-9,
304 
      'speed' => '-3',
305 
      'synth_file' => 'XST Defaults*',
306 
      'synthesis_language' => 'vhdl',
307 
      'synthesis_tool' => 'XST',
308 
      'synthesis_tool_sgadvanced' => '',
309 
      'sysclk_period' => 5.0,
310 
      'testbench' => 0,
311 
      'testbench_sgadvanced' => '',
312 
      'trim_vbits' => 1.0,
313 
      'trim_vbits_sgadvanced' => '',
314 
      'xilinx_device' => 'xc6vlx240t-3ff784',
315 
      'xilinxfamily' => 'virtex6',
316 
    },
317 
    'sysgen_Root' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
318 
    'systemClockPeriod' => 5.0,
319 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
320 
    'testbench' => 0,
321 
    'testbench_sgadvanced' => '',
322 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen',
323 
    'trim_vbits' => 1.0,
324 
    'trim_vbits_sgadvanced' => '',
325 
    'use_ce_syn_keep' => 1,
326 
    'use_strict_names' => 1,
327 
    'user_tips_enabled' => 0.0,
328 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
329 
    'using71Netlister' => 1,
330 
    'verilog_files' => [
331 
      'conv_pkg.v',
332 
      'synth_reg.v',
333 
      'synth_reg_w_init.v',
334 
      'convert_type.v',
335 
    ],
336 
    'version' => '',
337 
    'vhdl_files' => [
338 
      'conv_pkg.vhd',
339 
      'synth_reg.vhd',
340 
      'synth_reg_w_init.vhd',
341 
    ],
342 
    'vsimtime' => '11000000275.000000 ns',
343 
    'xilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
344 
    'xilinx_device' => 'xc6vlx240t-3ff784',
345 
    'xilinx_family' => 'virtex6',
346 
    'xilinx_package' => 'ff784',
347 
    'xilinx_part' => 'xc6vlx240t',
348 
    'xilinxdevice' => 'xc6vlx240t-3ff784',
349 
    'xilinxfamily' => 'virtex6',
350 
    'xilinxpart' => 'xc6vlx240t',
351 
  },
352 
  'entityName' => '',
353 
  'nets' => {
354 
    'bram_rd_addr_net' => {
355 
      'hdlType' => 'std_logic_vector(11 downto 0)',
356 
      'width' => 12,
357 
    },
358 
    'bram_rd_dout_net' => {
359 
      'hdlType' => 'std_logic_vector(63 downto 0)',
360 
      'width' => 64,
361 
    },
362 
    'bram_wr_addr_net' => {
363 
      'hdlType' => 'std_logic_vector(11 downto 0)',
364 
      'width' => 12,
365 
    },
366 
    'bram_wr_din_net' => {
367 
      'hdlType' => 'std_logic_vector(63 downto 0)',
368 
      'width' => 64,
369 
    },
370 
    'bram_wr_en_net' => {
371 
      'hdlType' => 'std_logic_vector(7 downto 0)',
372 
      'width' => 8,
373 
    },
374 
    'ce_1_sg_x0' => {
375 
      'hdlType' => 'std_logic',
376 
      'width' => 1,
377 
    },
378 
    'clk_1_sg_x0' => {
379 
      'hdlType' => 'std_logic',
380 
      'width' => 1,
381 
    },
382 
    'constant6_op_net_x0' => {
383 
      'hdlType' => 'std_logic',
384 
      'width' => 1,
385 
    },
386 
    'constant6_op_net_x1' => {
387 
      'hdlType' => 'std_logic',
388 
      'width' => 1,
389 
    },
390 
    'constant6_op_net_x10' => {
391 
      'hdlType' => 'std_logic',
392 
      'width' => 1,
393 
    },
394 
    'constant6_op_net_x11' => {
395 
      'hdlType' => 'std_logic',
396 
      'width' => 1,
397 
    },
398 
    'constant6_op_net_x12' => {
399 
      'hdlType' => 'std_logic',
400 
      'width' => 1,
401 
    },
402 
    'constant6_op_net_x13' => {
403 
      'hdlType' => 'std_logic',
404 
      'width' => 1,
405 
    },
406 
    'constant6_op_net_x14' => {
407 
      'hdlType' => 'std_logic',
408 
      'width' => 1,
409 
    },
410 
    'constant6_op_net_x15' => {
411 
      'hdlType' => 'std_logic',
412 
      'width' => 1,
413 
    },
414 
    'constant6_op_net_x16' => {
415 
      'hdlType' => 'std_logic',
416 
      'width' => 1,
417 
    },
418 
    'constant6_op_net_x17' => {
419 
      'hdlType' => 'std_logic',
420 
      'width' => 1,
421 
    },
422 
    'constant6_op_net_x18' => {
423 
      'hdlType' => 'std_logic',
424 
      'width' => 1,
425 
    },
426 
    'constant6_op_net_x19' => {
427 
      'hdlType' => 'std_logic',
428 
      'width' => 1,
429 
    },
430 
    'constant6_op_net_x2' => {
431 
      'hdlType' => 'std_logic',
432 
      'width' => 1,
433 
    },
434 
    'constant6_op_net_x20' => {
435 
      'hdlType' => 'std_logic',
436 
      'width' => 1,
437 
    },
438 
    'constant6_op_net_x21' => {
439 
      'hdlType' => 'std_logic',
440 
      'width' => 1,
441 
    },
442 
    'constant6_op_net_x22' => {
443 
      'hdlType' => 'std_logic',
444 
      'width' => 1,
445 
    },
446 
    'constant6_op_net_x23' => {
447 
      'hdlType' => 'std_logic',
448 
      'width' => 1,
449 
    },
450 
    'constant6_op_net_x24' => {
451 
      'hdlType' => 'std_logic',
452 
      'width' => 1,
453 
    },
454 
    'constant6_op_net_x25' => {
455 
      'hdlType' => 'std_logic',
456 
      'width' => 1,
457 
    },
458 
    'constant6_op_net_x26' => {
459 
      'hdlType' => 'std_logic',
460 
      'width' => 1,
461 
    },
462 
    'constant6_op_net_x27' => {
463 
      'hdlType' => 'std_logic',
464 
      'width' => 1,
465 
    },
466 
    'constant6_op_net_x3' => {
467 
      'hdlType' => 'std_logic',
468 
      'width' => 1,
469 
    },
470 
    'constant6_op_net_x4' => {
471 
      'hdlType' => 'std_logic',
472 
      'width' => 1,
473 
    },
474 
    'constant6_op_net_x5' => {
475 
      'hdlType' => 'std_logic',
476 
      'width' => 1,
477 
    },
478 
    'constant6_op_net_x6' => {
479 
      'hdlType' => 'std_logic',
480 
      'width' => 1,
481 
    },
482 
    'constant6_op_net_x7' => {
483 
      'hdlType' => 'std_logic',
484 
      'width' => 1,
485 
    },
486 
    'constant6_op_net_x8' => {
487 
      'hdlType' => 'std_logic',
488 
      'width' => 1,
489 
    },
490 
    'constant6_op_net_x9' => {
491 
      'hdlType' => 'std_logic',
492 
      'width' => 1,
493 
    },
494 
    'data_in_net' => {
495 
      'hdlType' => 'std_logic_vector(31 downto 0)',
496 
      'width' => 32,
497 
    },
498 
    'data_in_x0_net' => {
499 
      'hdlType' => 'std_logic',
500 
      'width' => 1,
501 
    },
502 
    'data_in_x10_net' => {
503 
      'hdlType' => 'std_logic_vector(31 downto 0)',
504 
      'width' => 32,
505 
    },
506 
    'data_in_x11_net' => {
507 
      'hdlType' => 'std_logic_vector(31 downto 0)',
508 
      'width' => 32,
509 
    },
510 
    'data_in_x12_net' => {
511 
      'hdlType' => 'std_logic',
512 
      'width' => 1,
513 
    },
514 
    'data_in_x13_net' => {
515 
      'hdlType' => 'std_logic_vector(31 downto 0)',
516 
      'width' => 32,
517 
    },
518 
    'data_in_x14_net' => {
519 
      'hdlType' => 'std_logic',
520 
      'width' => 1,
521 
    },
522 
    'data_in_x15_net' => {
523 
      'hdlType' => 'std_logic_vector(31 downto 0)',
524 
      'width' => 32,
525 
    },
526 
    'data_in_x16_net' => {
527 
      'hdlType' => 'std_logic',
528 
      'width' => 1,
529 
    },
530 
    'data_in_x17_net' => {
531 
      'hdlType' => 'std_logic_vector(31 downto 0)',
532 
      'width' => 32,
533 
    },
534 
    'data_in_x18_net' => {
535 
      'hdlType' => 'std_logic',
536 
      'width' => 1,
537 
    },
538 
    'data_in_x19_net' => {
539 
      'hdlType' => 'std_logic_vector(31 downto 0)',
540 
      'width' => 32,
541 
    },
542 
    'data_in_x1_net' => {
543 
      'hdlType' => 'std_logic',
544 
      'width' => 1,
545 
    },
546 
    'data_in_x20_net' => {
547 
      'hdlType' => 'std_logic_vector(31 downto 0)',
548 
      'width' => 32,
549 
    },
550 
    'data_in_x21_net' => {
551 
      'hdlType' => 'std_logic',
552 
      'width' => 1,
553 
    },
554 
    'data_in_x22_net' => {
555 
      'hdlType' => 'std_logic',
556 
      'width' => 1,
557 
    },
558 
    'data_in_x23_net' => {
559 
      'hdlType' => 'std_logic_vector(31 downto 0)',
560 
      'width' => 32,
561 
    },
562 
    'data_in_x24_net' => {
563 
      'hdlType' => 'std_logic',
564 
      'width' => 1,
565 
    },
566 
    'data_in_x25_net' => {
567 
      'hdlType' => 'std_logic_vector(31 downto 0)',
568 
      'width' => 32,
569 
    },
570 
    'data_in_x26_net' => {
571 
      'hdlType' => 'std_logic_vector(31 downto 0)',
572 
      'width' => 32,
573 
    },
574 
    'data_in_x2_net' => {
575 
      'hdlType' => 'std_logic',
576 
      'width' => 1,
577 
    },
578 
    'data_in_x3_net' => {
579 
      'hdlType' => 'std_logic',
580 
      'width' => 1,
581 
    },
582 
    'data_in_x4_net' => {
583 
      'hdlType' => 'std_logic_vector(31 downto 0)',
584 
      'width' => 32,
585 
    },
586 
    'data_in_x5_net' => {
587 
      'hdlType' => 'std_logic',
588 
      'width' => 1,
589 
    },
590 
    'data_in_x6_net' => {
591 
      'hdlType' => 'std_logic_vector(31 downto 0)',
592 
      'width' => 32,
593 
    },
594 
    'data_in_x7_net' => {
595 
      'hdlType' => 'std_logic',
596 
      'width' => 1,
597 
    },
598 
    'data_in_x8_net' => {
599 
      'hdlType' => 'std_logic_vector(31 downto 0)',
600 
      'width' => 32,
601 
    },
602 
    'data_in_x9_net' => {
603 
      'hdlType' => 'std_logic',
604 
      'width' => 1,
605 
    },
606 
    'data_out_net' => {
607 
      'hdlType' => 'std_logic',
608 
      'width' => 1,
609 
    },
610 
    'data_out_x0_net' => {
611 
      'hdlType' => 'std_logic_vector(31 downto 0)',
612 
      'width' => 32,
613 
    },
614 
    'data_out_x10_net' => {
615 
      'hdlType' => 'std_logic_vector(31 downto 0)',
616 
      'width' => 32,
617 
    },
618 
    'data_out_x11_net' => {
619 
      'hdlType' => 'std_logic',
620 
      'width' => 1,
621 
    },
622 
    'data_out_x12_net' => {
623 
      'hdlType' => 'std_logic_vector(31 downto 0)',
624 
      'width' => 32,
625 
    },
626 
    'data_out_x13_net' => {
627 
      'hdlType' => 'std_logic',
628 
      'width' => 1,
629 
    },
630 
    'data_out_x14_net' => {
631 
      'hdlType' => 'std_logic_vector(31 downto 0)',
632 
      'width' => 32,
633 
    },
634 
    'data_out_x15_net' => {
635 
      'hdlType' => 'std_logic',
636 
      'width' => 1,
637 
    },
638 
    'data_out_x16_net' => {
639 
      'hdlType' => 'std_logic_vector(31 downto 0)',
640 
      'width' => 32,
641 
    },
642 
    'data_out_x17_net' => {
643 
      'hdlType' => 'std_logic',
644 
      'width' => 1,
645 
    },
646 
    'data_out_x18_net' => {
647 
      'hdlType' => 'std_logic_vector(31 downto 0)',
648 
      'width' => 32,
649 
    },
650 
    'data_out_x19_net' => {
651 
      'hdlType' => 'std_logic_vector(31 downto 0)',
652 
      'width' => 32,
653 
    },
654 
    'data_out_x1_net' => {
655 
      'hdlType' => 'std_logic',
656 
      'width' => 1,
657 
    },
658 
    'data_out_x20_net' => {
659 
      'hdlType' => 'std_logic',
660 
      'width' => 1,
661 
    },
662 
    'data_out_x21_net' => {
663 
      'hdlType' => 'std_logic_vector(31 downto 0)',
664 
      'width' => 32,
665 
    },
666 
    'data_out_x22_net' => {
667 
      'hdlType' => 'std_logic',
668 
      'width' => 1,
669 
    },
670 
    'data_out_x23_net' => {
671 
      'hdlType' => 'std_logic',
672 
      'width' => 1,
673 
    },
674 
    'data_out_x24_net' => {
675 
      'hdlType' => 'std_logic_vector(31 downto 0)',
676 
      'width' => 32,
677 
    },
678 
    'data_out_x25_net' => {
679 
      'hdlType' => 'std_logic',
680 
      'width' => 1,
681 
    },
682 
    'data_out_x26_net' => {
683 
      'hdlType' => 'std_logic_vector(31 downto 0)',
684 
      'width' => 32,
685 
    },
686 
    'data_out_x27_net' => {
687 
      'hdlType' => 'std_logic',
688 
      'width' => 1,
689 
    },
690 
    'data_out_x28_net' => {
691 
      'hdlType' => 'std_logic_vector(31 downto 0)',
692 
      'width' => 32,
693 
    },
694 
    'data_out_x2_net' => {
695 
      'hdlType' => 'std_logic_vector(31 downto 0)',
696 
      'width' => 32,
697 
    },
698 
    'data_out_x3_net' => {
699 
      'hdlType' => 'std_logic',
700 
      'width' => 1,
701 
    },
702 
    'data_out_x6_net' => {
703 
      'hdlType' => 'std_logic_vector(31 downto 0)',
704 
      'width' => 32,
705 
    },
706 
    'data_out_x7_net' => {
707 
      'hdlType' => 'std_logic',
708 
      'width' => 1,
709 
    },
710 
    'data_out_x8_net' => {
711 
      'hdlType' => 'std_logic_vector(31 downto 0)',
712 
      'width' => 32,
713 
    },
714 
    'data_out_x9_net' => {
715 
      'hdlType' => 'std_logic',
716 
      'width' => 1,
717 
    },
718 
    'fifo_rd_count_net' => {
719 
      'hdlType' => 'std_logic_vector(14 downto 0)',
720 
      'width' => 15,
721 
    },
722 
    'fifo_rd_dout_net' => {
723 
      'hdlType' => 'std_logic_vector(71 downto 0)',
724 
      'width' => 72,
725 
    },
726 
    'fifo_rd_empty_net' => {
727 
      'hdlType' => 'std_logic',
728 
      'width' => 1,
729 
    },
730 
    'fifo_rd_en_net' => {
731 
      'hdlType' => 'std_logic',
732 
      'width' => 1,
733 
    },
734 
    'fifo_rd_pempty_net' => {
735 
      'hdlType' => 'std_logic',
736 
      'width' => 1,
737 
    },
738 
    'fifo_rd_valid_net' => {
739 
      'hdlType' => 'std_logic',
740 
      'width' => 1,
741 
    },
742 
    'fifo_wr_count_net' => {
743 
      'hdlType' => 'std_logic_vector(14 downto 0)',
744 
      'width' => 15,
745 
    },
746 
    'fifo_wr_din_net' => {
747 
      'hdlType' => 'std_logic_vector(71 downto 0)',
748 
      'width' => 72,
749 
    },
750 
    'fifo_wr_en_net' => {
751 
      'hdlType' => 'std_logic',
752 
      'width' => 1,
753 
    },
754 
    'fifo_wr_full_net' => {
755 
      'hdlType' => 'std_logic',
756 
      'width' => 1,
757 
    },
758 
    'fifo_wr_pfull_net' => {
759 
      'hdlType' => 'std_logic',
760 
      'width' => 1,
761 
    },
762 
    'from_register15_data_out_net' => {
763 
      'hdlType' => 'std_logic',
764 
      'width' => 1,
765 
    },
766 
    'from_register16_data_out_net' => {
767 
      'hdlType' => 'std_logic',
768 
      'width' => 1,
769 
    },
770 
    'from_register19_data_out_net' => {
771 
      'hdlType' => 'std_logic_vector(31 downto 0)',
772 
      'width' => 32,
773 
    },
774 
    'from_register1_data_out_net' => {
775 
      'hdlType' => 'std_logic_vector(31 downto 0)',
776 
      'width' => 32,
777 
    },
778 
    'from_register2_data_out_net' => {
779 
      'hdlType' => 'std_logic_vector(31 downto 0)',
780 
      'width' => 32,
781 
    },
782 
    'from_register_data_out_net' => {
783 
      'hdlType' => 'std_logic_vector(31 downto 0)',
784 
      'width' => 32,
785 
    },
786 
    'rst_i_net' => {
787 
      'hdlType' => 'std_logic',
788 
      'width' => 1,
789 
    },
790 
    'rst_o_net' => {
791 
      'hdlType' => 'std_logic',
792 
      'width' => 1,
793 
    },
794 
    'to_register10_dout_net' => {
795 
      'hdlType' => 'std_logic',
796 
      'width' => 1,
797 
    },
798 
    'to_register11_dout_net' => {
799 
      'hdlType' => 'std_logic',
800 
      'width' => 1,
801 
    },
802 
    'to_register12_dout_net' => {
803 
      'hdlType' => 'std_logic',
804 
      'width' => 1,
805 
    },
806 
    'to_register13_dout_net' => {
807 
      'hdlType' => 'std_logic_vector(31 downto 0)',
808 
      'width' => 32,
809 
    },
810 
    'to_register14_dout_net' => {
811 
      'hdlType' => 'std_logic',
812 
      'width' => 1,
813 
    },
814 
    'to_register15_dout_net' => {
815 
      'hdlType' => 'std_logic_vector(31 downto 0)',
816 
      'width' => 32,
817 
    },
818 
    'to_register16_dout_net' => {
819 
      'hdlType' => 'std_logic',
820 
      'width' => 1,
821 
    },
822 
    'to_register17_dout_net' => {
823 
      'hdlType' => 'std_logic_vector(31 downto 0)',
824 
      'width' => 32,
825 
    },
826 
    'to_register18_dout_net' => {
827 
      'hdlType' => 'std_logic',
828 
      'width' => 1,
829 
    },
830 
    'to_register19_dout_net' => {
831 
      'hdlType' => 'std_logic_vector(31 downto 0)',
832 
      'width' => 32,
833 
    },
834 
    'to_register1_dout_net' => {
835 
      'hdlType' => 'std_logic',
836 
      'width' => 1,
837 
    },
838 
    'to_register20_dout_net' => {
839 
      'hdlType' => 'std_logic',
840 
      'width' => 1,
841 
    },
842 
    'to_register21_dout_net' => {
843 
      'hdlType' => 'std_logic_vector(31 downto 0)',
844 
      'width' => 32,
845 
    },
846 
    'to_register22_dout_net' => {
847 
      'hdlType' => 'std_logic',
848 
      'width' => 1,
849 
    },
850 
    'to_register23_dout_net' => {
851 
      'hdlType' => 'std_logic_vector(31 downto 0)',
852 
      'width' => 32,
853 
    },
854 
    'to_register24_dout_net' => {
855 
      'hdlType' => 'std_logic',
856 
      'width' => 1,
857 
    },
858 
    'to_register25_dout_net' => {
859 
      'hdlType' => 'std_logic_vector(31 downto 0)',
860 
      'width' => 32,
861 
    },
862 
    'to_register26_dout_net' => {
863 
      'hdlType' => 'std_logic',
864 
      'width' => 1,
865 
    },
866 
    'to_register27_dout_net' => {
867 
      'hdlType' => 'std_logic_vector(31 downto 0)',
868 
      'width' => 32,
869 
    },
870 
    'to_register2_dout_net' => {
871 
      'hdlType' => 'std_logic_vector(31 downto 0)',
872 
      'width' => 32,
873 
    },
874 
    'to_register3_dout_net' => {
875 
      'hdlType' => 'std_logic_vector(31 downto 0)',
876 
      'width' => 32,
877 
    },
878 
    'to_register4_dout_net' => {
879 
      'hdlType' => 'std_logic',
880 
      'width' => 1,
881 
    },
882 
    'to_register5_dout_net' => {
883 
      'hdlType' => 'std_logic',
884 
      'width' => 1,
885 
    },
886 
    'to_register6_dout_net' => {
887 
      'hdlType' => 'std_logic_vector(31 downto 0)',
888 
      'width' => 32,
889 
    },
890 
    'to_register7_dout_net' => {
891 
      'hdlType' => 'std_logic',
892 
      'width' => 1,
893 
    },
894 
    'to_register8_dout_net' => {
895 
      'hdlType' => 'std_logic_vector(31 downto 0)',
896 
      'width' => 32,
897 
    },
898 
    'to_register9_dout_net' => {
899 
      'hdlType' => 'std_logic_vector(31 downto 0)',
900 
      'width' => 32,
901 
    },
902 
    'to_register_dout_net' => {
903 
      'hdlType' => 'std_logic_vector(31 downto 0)',
904 
      'width' => 32,
905 
    },
906 
    'user_int_1o_net' => {
907 
      'hdlType' => 'std_logic',
908 
      'width' => 1,
909 
    },
910 
    'user_int_2o_net' => {
911 
      'hdlType' => 'std_logic',
912 
      'width' => 1,
913 
    },
914 
    'user_int_3o_net' => {
915 
      'hdlType' => 'std_logic',
916 
      'width' => 1,
917 
    },
918 
  },
919 
  'subblocks' => {
920 
    'bram_rd_addr' => {
921 
      'connections' => { 'bram_rd_addr' => 'bram_rd_addr_net', },
922 
      'entity' => {
923 
        'attributes' => {
924 
          'isGateway' => 1,
925 
          'is_floating_block' => 1,
926 
        },
927 
        'entityName' => 'bram_rd_addr',
928 
        'ports' => {
929 
          'bram_rd_addr' => {
930 
            'attributes' => {
931 
              'bin_pt' => 0,
932 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
933 
              'is_floating_block' => 1,
934 
              'is_gateway_port' => 1,
935 
              'must_be_hdl_vector' => 1,
936 
              'period' => 1.0,
937 
              'port_id' => '0',
938 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr/BRAM_rd_addr',
939 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr',
940 
              'timingConstraint' => 'none',
941 
              'type' => 'UFix_12_0',
942 
            },
943 
            'direction' => 'in',
944 
            'hdlType' => 'std_logic_vector(11 downto 0)',
945 
            'width' => 12,
946 
          },
947 
        },
948 
      },
949 
      'entityName' => 'bram_rd_addr',
950 
    },
951 
    'bram_rd_dout' => {
952 
      'connections' => { 'bram_rd_dout' => 'bram_rd_dout_net', },
953 
      'entity' => {
954 
        'attributes' => {
955 
          'isGateway' => 1,
956 
          'is_floating_block' => 1,
957 
        },
958 
        'entityName' => 'bram_rd_dout',
959 
        'ports' => {
960 
          'bram_rd_dout' => {
961 
            'attributes' => {
962 
              'bin_pt' => 0,
963 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
964 
              'is_floating_block' => 1,
965 
              'is_gateway_port' => 1,
966 
              'must_be_hdl_vector' => 1,
967 
              'period' => 1.0,
968 
              'port_id' => '0',
969 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout/BRAM_rd_dout',
970 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout',
971 
              'timingConstraint' => 'none',
972 
              'type' => 'UFix_64_0',
973 
            },
974 
            'direction' => 'out',
975 
            'hdlType' => 'std_logic_vector(63 downto 0)',
976 
            'width' => 64,
977 
          },
978 
        },
979 
      },
980 
      'entityName' => 'bram_rd_dout',
981 
    },
982 
    'bram_wr_addr' => {
983 
      'connections' => { 'bram_wr_addr' => 'bram_wr_addr_net', },
984 
      'entity' => {
985 
        'attributes' => {
986 
          'isGateway' => 1,
987 
          'is_floating_block' => 1,
988 
        },
989 
        'entityName' => 'bram_wr_addr',
990 
        'ports' => {
991 
          'bram_wr_addr' => {
992 
            'attributes' => {
993 
              'bin_pt' => 0,
994 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
995 
              'is_floating_block' => 1,
996 
              'is_gateway_port' => 1,
997 
              'must_be_hdl_vector' => 1,
998 
              'period' => 1.0,
999 
              'port_id' => '0',
1000 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr/BRAM_wr_addr',
1001 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr',
1002 
              'timingConstraint' => 'none',
1003 
              'type' => 'UFix_12_0',
1004 
            },
1005 
            'direction' => 'in',
1006 
            'hdlType' => 'std_logic_vector(11 downto 0)',
1007 
            'width' => 12,
1008 
          },
1009 
        },
1010 
      },
1011 
      'entityName' => 'bram_wr_addr',
1012 
    },
1013 
    'bram_wr_din' => {
1014 
      'connections' => { 'bram_wr_din' => 'bram_wr_din_net', },
1015 
      'entity' => {
1016 
        'attributes' => {
1017 
          'isGateway' => 1,
1018 
          'is_floating_block' => 1,
1019 
        },
1020 
        'entityName' => 'bram_wr_din',
1021 
        'ports' => {
1022 
          'bram_wr_din' => {
1023 
            'attributes' => {
1024 
              'bin_pt' => 0,
1025 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
1026 
              'is_floating_block' => 1,
1027 
              'is_gateway_port' => 1,
1028 
              'must_be_hdl_vector' => 1,
1029 
              'period' => 1.0,
1030 
              'port_id' => '0',
1031 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din/BRAM_wr_din',
1032 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din',
1033 
              'timingConstraint' => 'none',
1034 
              'type' => 'UFix_64_0',
1035 
            },
1036 
            'direction' => 'in',
1037 
            'hdlType' => 'std_logic_vector(63 downto 0)',
1038 
            'width' => 64,
1039 
          },
1040 
        },
1041 
      },
1042 
      'entityName' => 'bram_wr_din',
1043 
    },
1044 
    'bram_wr_en' => {
1045 
      'connections' => { 'bram_wr_en' => 'bram_wr_en_net', },
1046 
      'entity' => {
1047 
        'attributes' => {
1048 
          'isGateway' => 1,
1049 
          'is_floating_block' => 1,
1050 
        },
1051 
        'entityName' => 'bram_wr_en',
1052 
        'ports' => {
1053 
          'bram_wr_en' => {
1054 
            'attributes' => {
1055 
              'bin_pt' => 0,
1056 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
1057 
              'is_floating_block' => 1,
1058 
              'is_gateway_port' => 1,
1059 
              'must_be_hdl_vector' => 1,
1060 
              'period' => 1.0,
1061 
              'port_id' => '0',
1062 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en/BRAM_wr_en',
1063 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en',
1064 
              'timingConstraint' => 'none',
1065 
              'type' => 'UFix_8_0',
1066 
            },
1067 
            'direction' => 'in',
1068 
            'hdlType' => 'std_logic_vector(7 downto 0)',
1069 
            'width' => 8,
1070 
          },
1071 
        },
1072 
      },
1073 
      'entityName' => 'bram_wr_en',
1074 
    },
1075 
    'default_clock_driver' => {
1076 
      'connections' => {
1077 
        'ce_1' => 'ce_1_sg_x0',
1078 
        'clk_1' => 'clk_1_sg_x0',
1079 
      },
1080 
      'entity' => {
1081 
        'attributes' => {
1082 
          'domain' => 'default',
1083 
          'isClkDriver' => 1,
1084 
        },
1085 
        'entityName' => 'default_clock_driver',
1086 
        'ports' => {
1087 
          'ce_1' => {
1088 
            'attributes' => {
1089 
              'domain' => 'default',
1090 
              'group' => 1,
1091 
              'isCe' => 1,
1092 
              'period' => 1.0,
1093 
              'type' => 'logic',
1094 
            },
1095 
            'direction' => 'out',
1096 
            'hdlType' => 'std_logic',
1097 
            'width' => 1,
1098 
          },
1099 
          'clk_1' => {
1100 
            'attributes' => {
1101 
              'domain' => 'default',
1102 
              'group' => 1,
1103 
              'isClk' => 1,
1104 
              'period' => 1.0,
1105 
              'type' => 'logic',
1106 
            },
1107 
            'direction' => 'out',
1108 
            'hdlType' => 'std_logic',
1109 
            'width' => 1,
1110 
          },
1111 
        },
1112 
      },
1113 
      'entityName' => 'default_clock_driver',
1114 
    },
1115 
    'fifo_rd_count' => {
1116 
      'connections' => { 'fifo_rd_count' => 'fifo_rd_count_net', },
1117 
      'entity' => {
1118 
        'attributes' => {
1119 
          'isGateway' => 1,
1120 
          'is_floating_block' => 1,
1121 
        },
1122 
        'entityName' => 'fifo_rd_count',
1123 
        'ports' => {
1124 
          'fifo_rd_count' => {
1125 
            'attributes' => {
1126 
              'bin_pt' => 0,
1127 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_count.dat',
1128 
              'is_floating_block' => 1,
1129 
              'is_gateway_port' => 1,
1130 
              'must_be_hdl_vector' => 1,
1131 
              'period' => 1.0,
1132 
              'port_id' => '0',
1133 
              'simulinkName' => 'fifo_rd_count',
1134 
              'source_block' => '',
1135 
              'timingConstraint' => 'none',
1136 
              'type' => 'UFix_15_0',
1137 
            },
1138 
            'direction' => 'out',
1139 
            'hdlType' => 'std_logic_vector(14 downto 0)',
1140 
            'width' => 15,
1141 
          },
1142 
        },
1143 
      },
1144 
      'entityName' => 'fifo_rd_count',
1145 
    },
1146 
    'fifo_rd_dout' => {
1147 
      'connections' => { 'fifo_rd_dout' => 'fifo_rd_dout_net', },
1148 
      'entity' => {
1149 
        'attributes' => {
1150 
          'isGateway' => 1,
1151 
          'is_floating_block' => 1,
1152 
        },
1153 
        'entityName' => 'fifo_rd_dout',
1154 
        'ports' => {
1155 
          'fifo_rd_dout' => {
1156 
            'attributes' => {
1157 
              'bin_pt' => 0,
1158 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_dout.dat',
1159 
              'is_floating_block' => 1,
1160 
              'is_gateway_port' => 1,
1161 
              'must_be_hdl_vector' => 1,
1162 
              'period' => 1.0,
1163 
              'port_id' => '0',
1164 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout/FIFO_rd_dout',
1165 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout',
1166 
              'timingConstraint' => 'none',
1167 
              'type' => 'UFix_72_0',
1168 
            },
1169 
            'direction' => 'out',
1170 
            'hdlType' => 'std_logic_vector(71 downto 0)',
1171 
            'width' => 72,
1172 
          },
1173 
        },
1174 
      },
1175 
      'entityName' => 'fifo_rd_dout',
1176 
    },
1177 
    'fifo_rd_empty' => {
1178 
      'connections' => { 'fifo_rd_empty' => 'fifo_rd_empty_net', },
1179 
      'entity' => {
1180 
        'attributes' => {
1181 
          'isGateway' => 1,
1182 
          'is_floating_block' => 1,
1183 
        },
1184 
        'entityName' => 'fifo_rd_empty',
1185 
        'ports' => {
1186 
          'fifo_rd_empty' => {
1187 
            'attributes' => {
1188 
              'bin_pt' => 0,
1189 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_empty.dat',
1190 
              'is_floating_block' => 1,
1191 
              'is_gateway_port' => 1,
1192 
              'must_be_hdl_vector' => 1,
1193 
              'period' => 1.0,
1194 
              'port_id' => '0',
1195 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_empty/FIFO_rd_empty',
1196 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_empty',
1197 
              'timingConstraint' => 'none',
1198 
              'type' => 'Bool',
1199 
            },
1200 
            'direction' => 'out',
1201 
            'hdlType' => 'std_logic',
1202 
            'width' => 1,
1203 
          },
1204 
        },
1205 
      },
1206 
      'entityName' => 'fifo_rd_empty',
1207 
    },
1208 
    'fifo_rd_en' => {
1209 
      'connections' => { 'fifo_rd_en' => 'fifo_rd_en_net', },
1210 
      'entity' => {
1211 
        'attributes' => {
1212 
          'isGateway' => 1,
1213 
          'is_floating_block' => 1,
1214 
        },
1215 
        'entityName' => 'fifo_rd_en',
1216 
        'ports' => {
1217 
          'fifo_rd_en' => {
1218 
            'attributes' => {
1219 
              'bin_pt' => 0,
1220 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_en.dat',
1221 
              'is_floating_block' => 1,
1222 
              'is_gateway_port' => 1,
1223 
              'must_be_hdl_vector' => 1,
1224 
              'period' => 1.0,
1225 
              'port_id' => '0',
1226 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_en/FIFO_rd_en',
1227 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_en',
1228 
              'timingConstraint' => 'none',
1229 
              'type' => 'Bool',
1230 
            },
1231 
            'direction' => 'in',
1232 
            'hdlType' => 'std_logic',
1233 
            'width' => 1,
1234 
          },
1235 
        },
1236 
      },
1237 
      'entityName' => 'fifo_rd_en',
1238 
    },
1239 
    'fifo_rd_pempty' => {
1240 
      'connections' => { 'fifo_rd_pempty' => 'fifo_rd_pempty_net', },
1241 
      'entity' => {
1242 
        'attributes' => {
1243 
          'isGateway' => 1,
1244 
          'is_floating_block' => 1,
1245 
        },
1246 
        'entityName' => 'fifo_rd_pempty',
1247 
        'ports' => {
1248 
          'fifo_rd_pempty' => {
1249 
            'attributes' => {
1250 
              'bin_pt' => 0,
1251 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_pempty.dat',
1252 
              'is_floating_block' => 1,
1253 
              'is_gateway_port' => 1,
1254 
              'must_be_hdl_vector' => 1,
1255 
              'period' => 1.0,
1256 
              'port_id' => '0',
1257 
              'simulinkName' => 'fifo_rd_pempty',
1258 
              'source_block' => '',
1259 
              'timingConstraint' => 'none',
1260 
              'type' => 'Bool',
1261 
            },
1262 
            'direction' => 'out',
1263 
            'hdlType' => 'std_logic',
1264 
            'width' => 1,
1265 
          },
1266 
        },
1267 
      },
1268 
      'entityName' => 'fifo_rd_pempty',
1269 
    },
1270 
    'fifo_rd_valid' => {
1271 
      'connections' => { 'fifo_rd_valid' => 'fifo_rd_valid_net', },
1272 
      'entity' => {
1273 
        'attributes' => {
1274 
          'isGateway' => 1,
1275 
          'is_floating_block' => 1,
1276 
        },
1277 
        'entityName' => 'fifo_rd_valid',
1278 
        'ports' => {
1279 
          'fifo_rd_valid' => {
1280 
            'attributes' => {
1281 
              'bin_pt' => 0,
1282 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_valid.dat',
1283 
              'is_floating_block' => 1,
1284 
              'is_gateway_port' => 1,
1285 
              'must_be_hdl_vector' => 1,
1286 
              'period' => 1.0,
1287 
              'port_id' => '0',
1288 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_valid/FIFO_rd_valid',
1289 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_valid',
1290 
              'timingConstraint' => 'none',
1291 
              'type' => 'Bool',
1292 
            },
1293 
            'direction' => 'out',
1294 
            'hdlType' => 'std_logic',
1295 
            'width' => 1,
1296 
          },
1297 
        },
1298 
      },
1299 
      'entityName' => 'fifo_rd_valid',
1300 
    },
1301 
    'fifo_wr_count' => {
1302 
      'connections' => { 'fifo_wr_count' => 'fifo_wr_count_net', },
1303 
      'entity' => {
1304 
        'attributes' => {
1305 
          'isGateway' => 1,
1306 
          'is_floating_block' => 1,
1307 
        },
1308 
        'entityName' => 'fifo_wr_count',
1309 
        'ports' => {
1310 
          'fifo_wr_count' => {
1311 
            'attributes' => {
1312 
              'bin_pt' => 0,
1313 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_count.dat',
1314 
              'is_floating_block' => 1,
1315 
              'is_gateway_port' => 1,
1316 
              'must_be_hdl_vector' => 1,
1317 
              'period' => 1.0,
1318 
              'port_id' => '0',
1319 
              'simulinkName' => 'fifo_wr_count',
1320 
              'source_block' => '',
1321 
              'timingConstraint' => 'none',
1322 
              'type' => 'UFix_15_0',
1323 
            },
1324 
            'direction' => 'out',
1325 
            'hdlType' => 'std_logic_vector(14 downto 0)',
1326 
            'width' => 15,
1327 
          },
1328 
        },
1329 
      },
1330 
      'entityName' => 'fifo_wr_count',
1331 
    },
1332 
    'fifo_wr_din' => {
1333 
      'connections' => { 'fifo_wr_din' => 'fifo_wr_din_net', },
1334 
      'entity' => {
1335 
        'attributes' => {
1336 
          'isGateway' => 1,
1337 
          'is_floating_block' => 1,
1338 
        },
1339 
        'entityName' => 'fifo_wr_din',
1340 
        'ports' => {
1341 
          'fifo_wr_din' => {
1342 
            'attributes' => {
1343 
              'bin_pt' => 0,
1344 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_din.dat',
1345 
              'is_floating_block' => 1,
1346 
              'is_gateway_port' => 1,
1347 
              'must_be_hdl_vector' => 1,
1348 
              'period' => 1.0,
1349 
              'port_id' => '0',
1350 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_din/FIFO_wr_din',
1351 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_din',
1352 
              'timingConstraint' => 'none',
1353 
              'type' => 'UFix_72_0',
1354 
            },
1355 
            'direction' => 'in',
1356 
            'hdlType' => 'std_logic_vector(71 downto 0)',
1357 
            'width' => 72,
1358 
          },
1359 
        },
1360 
      },
1361 
      'entityName' => 'fifo_wr_din',
1362 
    },
1363 
    'fifo_wr_en' => {
1364 
      'connections' => { 'fifo_wr_en' => 'fifo_wr_en_net', },
1365 
      'entity' => {
1366 
        'attributes' => {
1367 
          'isGateway' => 1,
1368 
          'is_floating_block' => 1,
1369 
        },
1370 
        'entityName' => 'fifo_wr_en',
1371 
        'ports' => {
1372 
          'fifo_wr_en' => {
1373 
            'attributes' => {
1374 
              'bin_pt' => 0,
1375 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_en.dat',
1376 
              'is_floating_block' => 1,
1377 
              'is_gateway_port' => 1,
1378 
              'must_be_hdl_vector' => 1,
1379 
              'period' => 1.0,
1380 
              'port_id' => '0',
1381 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_en/FIFO_wr_en',
1382 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_en',
1383 
              'timingConstraint' => 'none',
1384 
              'type' => 'Bool',
1385 
            },
1386 
            'direction' => 'in',
1387 
            'hdlType' => 'std_logic',
1388 
            'width' => 1,
1389 
          },
1390 
        },
1391 
      },
1392 
      'entityName' => 'fifo_wr_en',
1393 
    },
1394 
    'fifo_wr_full' => {
1395 
      'connections' => { 'fifo_wr_full' => 'fifo_wr_full_net', },
1396 
      'entity' => {
1397 
        'attributes' => {
1398 
          'isGateway' => 1,
1399 
          'is_floating_block' => 1,
1400 
        },
1401 
        'entityName' => 'fifo_wr_full',
1402 
        'ports' => {
1403 
          'fifo_wr_full' => {
1404 
            'attributes' => {
1405 
              'bin_pt' => 0,
1406 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_full.dat',
1407 
              'is_floating_block' => 1,
1408 
              'is_gateway_port' => 1,
1409 
              'must_be_hdl_vector' => 1,
1410 
              'period' => 1.0,
1411 
              'port_id' => '0',
1412 
              'simulinkName' => 'fifo_wr_full',
1413 
              'source_block' => '',
1414 
              'timingConstraint' => 'none',
1415 
              'type' => 'Bool',
1416 
            },
1417 
            'direction' => 'out',
1418 
            'hdlType' => 'std_logic',
1419 
            'width' => 1,
1420 
          },
1421 
        },
1422 
      },
1423 
      'entityName' => 'fifo_wr_full',
1424 
    },
1425 
    'fifo_wr_pfull' => {
1426 
      'connections' => { 'fifo_wr_pfull' => 'fifo_wr_pfull_net', },
1427 
      'entity' => {
1428 
        'attributes' => {
1429 
          'isGateway' => 1,
1430 
          'is_floating_block' => 1,
1431 
        },
1432 
        'entityName' => 'fifo_wr_pfull',
1433 
        'ports' => {
1434 
          'fifo_wr_pfull' => {
1435 
            'attributes' => {
1436 
              'bin_pt' => 0,
1437 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_pfull.dat',
1438 
              'is_floating_block' => 1,
1439 
              'is_gateway_port' => 1,
1440 
              'must_be_hdl_vector' => 1,
1441 
              'period' => 1.0,
1442 
              'port_id' => '0',
1443 
              'simulinkName' => 'fifo_wr_pfull',
1444 
              'source_block' => '',
1445 
              'timingConstraint' => 'none',
1446 
              'type' => 'Bool',
1447 
            },
1448 
            'direction' => 'out',
1449 
            'hdlType' => 'std_logic',
1450 
            'width' => 1,
1451 
          },
1452 
        },
1453 
      },
1454 
      'entityName' => 'fifo_wr_pfull',
1455 
    },
1456 
    'from_register' => {
1457 
      'connections' => { 'data_out' => 'from_register_data_out_net', },
1458 
      'entity' => {
1459 
        'attributes' => {
1460 
          'generics' => [],
1461 
          'is_floating_block' => 1,
1462 
          'mask' => {
1463 
            'Block_Handle' => 2524.0018310546875,
1464 
            'Block_handle' => 2524.0018310546875,
1465 
            'MDL_Handle' => 3.0009765625,
1466 
            'MDL_handle' => 3.0009765625,
1467 
            'arith_type' => 2,
1468 
            'bin_pt' => 0,
1469 
            'block_config' => 'sysgen_blockset:fromreg_config',
1470 
            'block_handle' => 2524.0018310546875,
1471 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register',
1472 
            'block_type' => 'fromreg',
1473 
            'dbl_ovrd' => 0,
1474 
            'init' => 0.0,
1475 
            'init_bit_vector' => '00000000000000000000000000000000b',
1476 
            'mdl_handle' => 3.0009765625,
1477 
            'model_handle' => 3.0009765625,
1478 
            'n_bits' => 32,
1479 
            'ownership' => 2,
1480 
            'period' => 5.0E-9,
1481 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1482 
            'shared_memory_name' => 'debug1i',
1483 
          },
1484 
          'needs_vhdl_wrapper' => 0,
1485 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register',
1486 
        },
1487 
        'entityName' => 'x_x119',
1488 
        'ports' => {
1489 
          'data_out' => {
1490 
            'attributes' => {
1491 
              'bin_pt' => 0,
1492 
              'is_floating_block' => 1,
1493 
              'must_be_hdl_vector' => 1,
1494 
              'period' => 1.0,
1495 
              'port_id' => '0',
1496 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register/data_out',
1497 
              'type' => 'UFix_32_0',
1498 
            },
1499 
            'direction' => 'out',
1500 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1501 
            'width' => 32,
1502 
          },
1503 
        },
1504 
      },
1505 
      'entityName' => 'x_x119',
1506 
    },
1507 
    'from_register1' => {
1508 
      'connections' => { 'data_out' => 'from_register1_data_out_net', },
1509 
      'entity' => {
1510 
        'attributes' => {
1511 
          'generics' => [],
1512 
          'is_floating_block' => 1,
1513 
          'mask' => {
1514 
            'Block_Handle' => 2525.3526611328125,
1515 
            'Block_handle' => 2525.3526611328125,
1516 
            'MDL_Handle' => 3.0009765625,
1517 
            'MDL_handle' => 3.0009765625,
1518 
            'arith_type' => 2,
1519 
            'bin_pt' => 0,
1520 
            'block_config' => 'sysgen_blockset:fromreg_config',
1521 
            'block_handle' => 2525.3526611328125,
1522 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register1',
1523 
            'block_type' => 'fromreg',
1524 
            'dbl_ovrd' => 0,
1525 
            'init' => 0.0,
1526 
            'init_bit_vector' => '00000000000000000000000000000000b',
1527 
            'mdl_handle' => 3.0009765625,
1528 
            'model_handle' => 3.0009765625,
1529 
            'n_bits' => 32,
1530 
            'ownership' => 2,
1531 
            'period' => 5.0E-9,
1532 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1533 
            'shared_memory_name' => 'debug2i',
1534 
          },
1535 
          'needs_vhdl_wrapper' => 0,
1536 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register1',
1537 
        },
1538 
        'entityName' => 'x_x120',
1539 
        'ports' => {
1540 
          'data_out' => {
1541 
            'attributes' => {
1542 
              'bin_pt' => 0,
1543 
              'is_floating_block' => 1,
1544 
              'must_be_hdl_vector' => 1,
1545 
              'period' => 1.0,
1546 
              'port_id' => '0',
1547 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register1/data_out',
1548 
              'type' => 'UFix_32_0',
1549 
            },
1550 
            'direction' => 'out',
1551 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1552 
            'width' => 32,
1553 
          },
1554 
        },
1555 
      },
1556 
      'entityName' => 'x_x120',
1557 
    },
1558 
    'from_register10' => {
1559 
      'connections' => { 'data_out' => 'data_out_net', },
1560 
      'entity' => {
1561 
        'attributes' => {
1562 
          'generics' => [],
1563 
          'is_floating_block' => 1,
1564 
          'mask' => {
1565 
            'Block_Handle' => 385.0009765625,
1566 
            'Block_handle' => 385.0009765625,
1567 
            'MDL_Handle' => 3.0009765625,
1568 
            'MDL_handle' => 3.0009765625,
1569 
            'arith_type' => 2,
1570 
            'bin_pt' => 0,
1571 
            'block_config' => 'sysgen_blockset:fromreg_config',
1572 
            'block_handle' => 385.0009765625,
1573 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register10',
1574 
            'block_type' => 'fromreg',
1575 
            'dbl_ovrd' => 0,
1576 
            'init' => 0.0,
1577 
            'init_bit_vector' => '0b',
1578 
            'mdl_handle' => 3.0009765625,
1579 
            'model_handle' => 3.0009765625,
1580 
            'n_bits' => 1,
1581 
            'ownership' => 2,
1582 
            'period' => 5.0E-9,
1583 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1584 
            'shared_memory_name' => 'register04tv',
1585 
          },
1586 
          'needs_vhdl_wrapper' => 0,
1587 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register10',
1588 
        },
1589 
        'entityName' => 'x_x89',
1590 
        'ports' => {
1591 
          'data_out' => {
1592 
            'attributes' => {
1593 
              'bin_pt' => 0,
1594 
              'is_floating_block' => 1,
1595 
              'must_be_hdl_vector' => 1,
1596 
              'period' => 1.0,
1597 
              'port_id' => '0',
1598 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register10/data_out',
1599 
              'type' => 'UFix_1_0',
1600 
            },
1601 
            'direction' => 'out',
1602 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1603 
            'width' => 1,
1604 
          },
1605 
        },
1606 
      },
1607 
      'entityName' => 'x_x89',
1608 
    },
1609 
    'from_register11' => {
1610 
      'connections' => { 'data_out' => 'data_out_x0_net', },
1611 
      'entity' => {
1612 
        'attributes' => {
1613 
          'generics' => [],
1614 
          'is_floating_block' => 1,
1615 
          'mask' => {
1616 
            'Block_Handle' => 386.0009765625,
1617 
            'Block_handle' => 386.0009765625,
1618 
            'MDL_Handle' => 3.0009765625,
1619 
            'MDL_handle' => 3.0009765625,
1620 
            'arith_type' => 2,
1621 
            'bin_pt' => 0,
1622 
            'block_config' => 'sysgen_blockset:fromreg_config',
1623 
            'block_handle' => 386.0009765625,
1624 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register11',
1625 
            'block_type' => 'fromreg',
1626 
            'dbl_ovrd' => 0,
1627 
            'init' => 0.0,
1628 
            'init_bit_vector' => '00000000000000000000000000000000b',
1629 
            'mdl_handle' => 3.0009765625,
1630 
            'model_handle' => 3.0009765625,
1631 
            'n_bits' => 32,
1632 
            'ownership' => 2,
1633 
            'period' => 5.0E-9,
1634 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1635 
            'shared_memory_name' => 'register05td',
1636 
          },
1637 
          'needs_vhdl_wrapper' => 0,
1638 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register11',
1639 
        },
1640 
        'entityName' => 'x_x90',
1641 
        'ports' => {
1642 
          'data_out' => {
1643 
            'attributes' => {
1644 
              'bin_pt' => 0,
1645 
              'is_floating_block' => 1,
1646 
              'must_be_hdl_vector' => 1,
1647 
              'period' => 1.0,
1648 
              'port_id' => '0',
1649 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register11/data_out',
1650 
              'type' => 'UFix_32_0',
1651 
            },
1652 
            'direction' => 'out',
1653 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1654 
            'width' => 32,
1655 
          },
1656 
        },
1657 
      },
1658 
      'entityName' => 'x_x90',
1659 
    },
1660 
    'from_register12' => {
1661 
      'connections' => { 'data_out' => 'data_out_x1_net', },
1662 
      'entity' => {
1663 
        'attributes' => {
1664 
          'generics' => [],
1665 
          'is_floating_block' => 1,
1666 
          'mask' => {
1667 
            'Block_Handle' => 387.0009765625,
1668 
            'Block_handle' => 387.0009765625,
1669 
            'MDL_Handle' => 3.0009765625,
1670 
            'MDL_handle' => 3.0009765625,
1671 
            'arith_type' => 2,
1672 
            'bin_pt' => 0,
1673 
            'block_config' => 'sysgen_blockset:fromreg_config',
1674 
            'block_handle' => 387.0009765625,
1675 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register12',
1676 
            'block_type' => 'fromreg',
1677 
            'dbl_ovrd' => 0,
1678 
            'init' => 0.0,
1679 
            'init_bit_vector' => '0b',
1680 
            'mdl_handle' => 3.0009765625,
1681 
            'model_handle' => 3.0009765625,
1682 
            'n_bits' => 1,
1683 
            'ownership' => 2,
1684 
            'period' => 5.0E-9,
1685 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1686 
            'shared_memory_name' => 'register05tv',
1687 
          },
1688 
          'needs_vhdl_wrapper' => 0,
1689 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register12',
1690 
        },
1691 
        'entityName' => 'x_x91',
1692 
        'ports' => {
1693 
          'data_out' => {
1694 
            'attributes' => {
1695 
              'bin_pt' => 0,
1696 
              'is_floating_block' => 1,
1697 
              'must_be_hdl_vector' => 1,
1698 
              'period' => 1.0,
1699 
              'port_id' => '0',
1700 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register12/data_out',
1701 
              'type' => 'UFix_1_0',
1702 
            },
1703 
            'direction' => 'out',
1704 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1705 
            'width' => 1,
1706 
          },
1707 
        },
1708 
      },
1709 
      'entityName' => 'x_x91',
1710 
    },
1711 
    'from_register13' => {
1712 
      'connections' => { 'data_out' => 'data_out_x2_net', },
1713 
      'entity' => {
1714 
        'attributes' => {
1715 
          'generics' => [],
1716 
          'is_floating_block' => 1,
1717 
          'mask' => {
1718 
            'Block_Handle' => 388.0009765625,
1719 
            'Block_handle' => 388.0009765625,
1720 
            'MDL_Handle' => 3.0009765625,
1721 
            'MDL_handle' => 3.0009765625,
1722 
            'arith_type' => 2,
1723 
            'bin_pt' => 0,
1724 
            'block_config' => 'sysgen_blockset:fromreg_config',
1725 
            'block_handle' => 388.0009765625,
1726 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register13',
1727 
            'block_type' => 'fromreg',
1728 
            'dbl_ovrd' => 0,
1729 
            'init' => 0.0,
1730 
            'init_bit_vector' => '00000000000000000000000000000000b',
1731 
            'mdl_handle' => 3.0009765625,
1732 
            'model_handle' => 3.0009765625,
1733 
            'n_bits' => 32,
1734 
            'ownership' => 2,
1735 
            'period' => 5.0E-9,
1736 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1737 
            'shared_memory_name' => 'register06td',
1738 
          },
1739 
          'needs_vhdl_wrapper' => 0,
1740 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register13',
1741 
        },
1742 
        'entityName' => 'x_x92',
1743 
        'ports' => {
1744 
          'data_out' => {
1745 
            'attributes' => {
1746 
              'bin_pt' => 0,
1747 
              'is_floating_block' => 1,
1748 
              'must_be_hdl_vector' => 1,
1749 
              'period' => 1.0,
1750 
              'port_id' => '0',
1751 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register13/data_out',
1752 
              'type' => 'UFix_32_0',
1753 
            },
1754 
            'direction' => 'out',
1755 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1756 
            'width' => 32,
1757 
          },
1758 
        },
1759 
      },
1760 
      'entityName' => 'x_x92',
1761 
    },
1762 
    'from_register14' => {
1763 
      'connections' => { 'data_out' => 'data_out_x3_net', },
1764 
      'entity' => {
1765 
        'attributes' => {
1766 
          'generics' => [],
1767 
          'is_floating_block' => 1,
1768 
          'mask' => {
1769 
            'Block_Handle' => 389.0009765625,
1770 
            'Block_handle' => 389.0009765625,
1771 
            'MDL_Handle' => 3.0009765625,
1772 
            'MDL_handle' => 3.0009765625,
1773 
            'arith_type' => 2,
1774 
            'bin_pt' => 0,
1775 
            'block_config' => 'sysgen_blockset:fromreg_config',
1776 
            'block_handle' => 389.0009765625,
1777 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register14',
1778 
            'block_type' => 'fromreg',
1779 
            'dbl_ovrd' => 0,
1780 
            'init' => 0.0,
1781 
            'init_bit_vector' => '0b',
1782 
            'mdl_handle' => 3.0009765625,
1783 
            'model_handle' => 3.0009765625,
1784 
            'n_bits' => 1,
1785 
            'ownership' => 2,
1786 
            'period' => 5.0E-9,
1787 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1788 
            'shared_memory_name' => 'register06tv',
1789 
          },
1790 
          'needs_vhdl_wrapper' => 0,
1791 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register14',
1792 
        },
1793 
        'entityName' => 'x_x93',
1794 
        'ports' => {
1795 
          'data_out' => {
1796 
            'attributes' => {
1797 
              'bin_pt' => 0,
1798 
              'is_floating_block' => 1,
1799 
              'must_be_hdl_vector' => 1,
1800 
              'period' => 1.0,
1801 
              'port_id' => '0',
1802 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register14/data_out',
1803 
              'type' => 'UFix_1_0',
1804 
            },
1805 
            'direction' => 'out',
1806 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1807 
            'width' => 1,
1808 
          },
1809 
        },
1810 
      },
1811 
      'entityName' => 'x_x93',
1812 
    },
1813 
    'from_register15' => {
1814 
      'connections' => { 'data_out' => 'from_register15_data_out_net', },
1815 
      'entity' => {
1816 
        'attributes' => {
1817 
          'generics' => [],
1818 
          'is_floating_block' => 1,
1819 
          'mask' => {
1820 
            'Block_Handle' => 390.0009765625,
1821 
            'Block_handle' => 390.0009765625,
1822 
            'MDL_Handle' => 3.0009765625,
1823 
            'MDL_handle' => 3.0009765625,
1824 
            'arith_type' => 2,
1825 
            'bin_pt' => 0,
1826 
            'block_config' => 'sysgen_blockset:fromreg_config',
1827 
            'block_handle' => 390.0009765625,
1828 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register15',
1829 
            'block_type' => 'fromreg',
1830 
            'dbl_ovrd' => 0,
1831 
            'init' => 0.0,
1832 
            'init_bit_vector' => '0b',
1833 
            'mdl_handle' => 3.0009765625,
1834 
            'model_handle' => 3.0009765625,
1835 
            'n_bits' => 1,
1836 
            'ownership' => 2,
1837 
            'period' => 5.0E-9,
1838 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1839 
            'shared_memory_name' => 'DMA_Host2Board_Done',
1840 
          },
1841 
          'needs_vhdl_wrapper' => 0,
1842 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register15',
1843 
        },
1844 
        'entityName' => 'x_x94',
1845 
        'ports' => {
1846 
          'data_out' => {
1847 
            'attributes' => {
1848 
              'bin_pt' => 0,
1849 
              'is_floating_block' => 1,
1850 
              'must_be_hdl_vector' => 1,
1851 
              'period' => 1.0,
1852 
              'port_id' => '0',
1853 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register15/data_out',
1854 
              'type' => 'UFix_1_0',
1855 
            },
1856 
            'direction' => 'out',
1857 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1858 
            'width' => 1,
1859 
          },
1860 
        },
1861 
      },
1862 
      'entityName' => 'x_x94',
1863 
    },
1864 
    'from_register16' => {
1865 
      'connections' => { 'data_out' => 'from_register16_data_out_net', },
1866 
      'entity' => {
1867 
        'attributes' => {
1868 
          'generics' => [],
1869 
          'is_floating_block' => 1,
1870 
          'mask' => {
1871 
            'Block_Handle' => 391.0009765625,
1872 
            'Block_handle' => 391.0009765625,
1873 
            'MDL_Handle' => 3.0009765625,
1874 
            'MDL_handle' => 3.0009765625,
1875 
            'arith_type' => 2,
1876 
            'bin_pt' => 0,
1877 
            'block_config' => 'sysgen_blockset:fromreg_config',
1878 
            'block_handle' => 391.0009765625,
1879 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register16',
1880 
            'block_type' => 'fromreg',
1881 
            'dbl_ovrd' => 0,
1882 
            'init' => 0.0,
1883 
            'init_bit_vector' => '0b',
1884 
            'mdl_handle' => 3.0009765625,
1885 
            'model_handle' => 3.0009765625,
1886 
            'n_bits' => 1,
1887 
            'ownership' => 2,
1888 
            'period' => 5.0E-9,
1889 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1890 
            'shared_memory_name' => 'DMA_Host2Board_Busy',
1891 
          },
1892 
          'needs_vhdl_wrapper' => 0,
1893 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register16',
1894 
        },
1895 
        'entityName' => 'x_x95',
1896 
        'ports' => {
1897 
          'data_out' => {
1898 
            'attributes' => {
1899 
              'bin_pt' => 0,
1900 
              'is_floating_block' => 1,
1901 
              'must_be_hdl_vector' => 1,
1902 
              'period' => 1.0,
1903 
              'port_id' => '0',
1904 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register16/data_out',
1905 
              'type' => 'UFix_1_0',
1906 
            },
1907 
            'direction' => 'out',
1908 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1909 
            'width' => 1,
1910 
          },
1911 
        },
1912 
      },
1913 
      'entityName' => 'x_x95',
1914 
    },
1915 
    'from_register17' => {
1916 
      'connections' => { 'data_out' => 'data_out_x6_net', },
1917 
      'entity' => {
1918 
        'attributes' => {
1919 
          'generics' => [],
1920 
          'is_floating_block' => 1,
1921 
          'mask' => {
1922 
            'Block_Handle' => 392.0009765625,
1923 
            'Block_handle' => 392.0009765625,
1924 
            'MDL_Handle' => 3.0009765625,
1925 
            'MDL_handle' => 3.0009765625,
1926 
            'arith_type' => 2,
1927 
            'bin_pt' => 0,
1928 
            'block_config' => 'sysgen_blockset:fromreg_config',
1929 
            'block_handle' => 392.0009765625,
1930 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register17',
1931 
            'block_type' => 'fromreg',
1932 
            'dbl_ovrd' => 0,
1933 
            'init' => 0.0,
1934 
            'init_bit_vector' => '00000000000000000000000000000000b',
1935 
            'mdl_handle' => 3.0009765625,
1936 
            'model_handle' => 3.0009765625,
1937 
            'n_bits' => 32,
1938 
            'ownership' => 2,
1939 
            'period' => 5.0E-9,
1940 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1941 
            'shared_memory_name' => 'register07td',
1942 
          },
1943 
          'needs_vhdl_wrapper' => 0,
1944 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register17',
1945 
        },
1946 
        'entityName' => 'x_x96',
1947 
        'ports' => {
1948 
          'data_out' => {
1949 
            'attributes' => {
1950 
              'bin_pt' => 0,
1951 
              'is_floating_block' => 1,
1952 
              'must_be_hdl_vector' => 1,
1953 
              'period' => 1.0,
1954 
              'port_id' => '0',
1955 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register17/data_out',
1956 
              'type' => 'UFix_32_0',
1957 
            },
1958 
            'direction' => 'out',
1959 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1960 
            'width' => 32,
1961 
          },
1962 
        },
1963 
      },
1964 
      'entityName' => 'x_x96',
1965 
    },
1966 
    'from_register18' => {
1967 
      'connections' => { 'data_out' => 'data_out_x7_net', },
1968 
      'entity' => {
1969 
        'attributes' => {
1970 
          'generics' => [],
1971 
          'is_floating_block' => 1,
1972 
          'mask' => {
1973 
            'Block_Handle' => 393.0009765625,
1974 
            'Block_handle' => 393.0009765625,
1975 
            'MDL_Handle' => 3.0009765625,
1976 
            'MDL_handle' => 3.0009765625,
1977 
            'arith_type' => 2,
1978 
            'bin_pt' => 0,
1979 
            'block_config' => 'sysgen_blockset:fromreg_config',
1980 
            'block_handle' => 393.0009765625,
1981 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register18',
1982 
            'block_type' => 'fromreg',
1983 
            'dbl_ovrd' => 0,
1984 
            'init' => 0.0,
1985 
            'init_bit_vector' => '0b',
1986 
            'mdl_handle' => 3.0009765625,
1987 
            'model_handle' => 3.0009765625,
1988 
            'n_bits' => 1,
1989 
            'ownership' => 2,
1990 
            'period' => 5.0E-9,
1991 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1992 
            'shared_memory_name' => 'register07tv',
1993 
          },
1994 
          'needs_vhdl_wrapper' => 0,
1995 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register18',
1996 
        },
1997 
        'entityName' => 'x_x97',
1998 
        'ports' => {
1999 
          'data_out' => {
2000 
            'attributes' => {
2001 
              'bin_pt' => 0,
2002 
              'is_floating_block' => 1,
2003 
              'must_be_hdl_vector' => 1,
2004 
              'period' => 1.0,
2005 
              'port_id' => '0',
2006 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register18/data_out',
2007 
              'type' => 'UFix_1_0',
2008 
            },
2009 
            'direction' => 'out',
2010 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2011 
            'width' => 1,
2012 
          },
2013 
        },
2014 
      },
2015 
      'entityName' => 'x_x97',
2016 
    },
2017 
    'from_register19' => {
2018 
      'connections' => { 'data_out' => 'from_register19_data_out_net', },
2019 
      'entity' => {
2020 
        'attributes' => {
2021 
          'generics' => [],
2022 
          'is_floating_block' => 1,
2023 
          'mask' => {
2024 
            'Block_Handle' => 2526.0640869140625,
2025 
            'Block_handle' => 2526.0640869140625,
2026 
            'MDL_Handle' => 3.0009765625,
2027 
            'MDL_handle' => 3.0009765625,
2028 
            'arith_type' => 2,
2029 
            'bin_pt' => 0,
2030 
            'block_config' => 'sysgen_blockset:fromreg_config',
2031 
            'block_handle' => 2526.0640869140625,
2032 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register19',
2033 
            'block_type' => 'fromreg',
2034 
            'dbl_ovrd' => 0,
2035 
            'init' => 0.0,
2036 
            'init_bit_vector' => '00000000000000000000000000000000b',
2037 
            'mdl_handle' => 3.0009765625,
2038 
            'model_handle' => 3.0009765625,
2039 
            'n_bits' => 32,
2040 
            'ownership' => 2,
2041 
            'period' => 5.0E-9,
2042 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2043 
            'shared_memory_name' => 'debug4i',
2044 
          },
2045 
          'needs_vhdl_wrapper' => 0,
2046 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register19',
2047 
        },
2048 
        'entityName' => 'x_x121',
2049 
        'ports' => {
2050 
          'data_out' => {
2051 
            'attributes' => {
2052 
              'bin_pt' => 0,
2053 
              'is_floating_block' => 1,
2054 
              'must_be_hdl_vector' => 1,
2055 
              'period' => 1.0,
2056 
              'port_id' => '0',
2057 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register19/data_out',
2058 
              'type' => 'UFix_32_0',
2059 
            },
2060 
            'direction' => 'out',
2061 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2062 
            'width' => 32,
2063 
          },
2064 
        },
2065 
      },
2066 
      'entityName' => 'x_x121',
2067 
    },
2068 
    'from_register2' => {
2069 
      'connections' => { 'data_out' => 'from_register2_data_out_net', },
2070 
      'entity' => {
2071 
        'attributes' => {
2072 
          'generics' => [],
2073 
          'is_floating_block' => 1,
2074 
          'mask' => {
2075 
            'Block_Handle' => 2527.0015869140625,
2076 
            'Block_handle' => 2527.0015869140625,
2077 
            'MDL_Handle' => 3.0009765625,
2078 
            'MDL_handle' => 3.0009765625,
2079 
            'arith_type' => 2,
2080 
            'bin_pt' => 0,
2081 
            'block_config' => 'sysgen_blockset:fromreg_config',
2082 
            'block_handle' => 2527.0015869140625,
2083 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register2',
2084 
            'block_type' => 'fromreg',
2085 
            'dbl_ovrd' => 0,
2086 
            'init' => 0.0,
2087 
            'init_bit_vector' => '00000000000000000000000000000000b',
2088 
            'mdl_handle' => 3.0009765625,
2089 
            'model_handle' => 3.0009765625,
2090 
            'n_bits' => 32,
2091 
            'ownership' => 2,
2092 
            'period' => 5.0E-9,
2093 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2094 
            'shared_memory_name' => 'debug3i',
2095 
          },
2096 
          'needs_vhdl_wrapper' => 0,
2097 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register2',
2098 
        },
2099 
        'entityName' => 'x_x122',
2100 
        'ports' => {
2101 
          'data_out' => {
2102 
            'attributes' => {
2103 
              'bin_pt' => 0,
2104 
              'is_floating_block' => 1,
2105 
              'must_be_hdl_vector' => 1,
2106 
              'period' => 1.0,
2107 
              'port_id' => '0',
2108 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register2/data_out',
2109 
              'type' => 'UFix_32_0',
2110 
            },
2111 
            'direction' => 'out',
2112 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2113 
            'width' => 32,
2114 
          },
2115 
        },
2116 
      },
2117 
      'entityName' => 'x_x122',
2118 
    },
2119 
    'from_register20' => {
2120 
      'connections' => { 'data_out' => 'data_out_x8_net', },
2121 
      'entity' => {
2122 
        'attributes' => {
2123 
          'generics' => [],
2124 
          'is_floating_block' => 1,
2125 
          'mask' => {
2126 
            'Block_Handle' => 396.0009765625,
2127 
            'Block_handle' => 396.0009765625,
2128 
            'MDL_Handle' => 3.0009765625,
2129 
            'MDL_handle' => 3.0009765625,
2130 
            'arith_type' => 2,
2131 
            'bin_pt' => 0,
2132 
            'block_config' => 'sysgen_blockset:fromreg_config',
2133 
            'block_handle' => 396.0009765625,
2134 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register20',
2135 
            'block_type' => 'fromreg',
2136 
            'dbl_ovrd' => 0,
2137 
            'init' => 0.0,
2138 
            'init_bit_vector' => '00000000000000000000000000000000b',
2139 
            'mdl_handle' => 3.0009765625,
2140 
            'model_handle' => 3.0009765625,
2141 
            'n_bits' => 32,
2142 
            'ownership' => 2,
2143 
            'period' => 5.0E-9,
2144 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2145 
            'shared_memory_name' => 'register08td',
2146 
          },
2147 
          'needs_vhdl_wrapper' => 0,
2148 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register20',
2149 
        },
2150 
        'entityName' => 'x_x98',
2151 
        'ports' => {
2152 
          'data_out' => {
2153 
            'attributes' => {
2154 
              'bin_pt' => 0,
2155 
              'is_floating_block' => 1,
2156 
              'must_be_hdl_vector' => 1,
2157 
              'period' => 1.0,
2158 
              'port_id' => '0',
2159 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register20/data_out',
2160 
              'type' => 'UFix_32_0',
2161 
            },
2162 
            'direction' => 'out',
2163 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2164 
            'width' => 32,
2165 
          },
2166 
        },
2167 
      },
2168 
      'entityName' => 'x_x98',
2169 
    },
2170 
    'from_register21' => {
2171 
      'connections' => { 'data_out' => 'data_out_x9_net', },
2172 
      'entity' => {
2173 
        'attributes' => {
2174 
          'generics' => [],
2175 
          'is_floating_block' => 1,
2176 
          'mask' => {
2177 
            'Block_Handle' => 397.0009765625,
2178 
            'Block_handle' => 397.0009765625,
2179 
            'MDL_Handle' => 3.0009765625,
2180 
            'MDL_handle' => 3.0009765625,
2181 
            'arith_type' => 2,
2182 
            'bin_pt' => 0,
2183 
            'block_config' => 'sysgen_blockset:fromreg_config',
2184 
            'block_handle' => 397.0009765625,
2185 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register21',
2186 
            'block_type' => 'fromreg',
2187 
            'dbl_ovrd' => 0,
2188 
            'init' => 0.0,
2189 
            'init_bit_vector' => '0b',
2190 
            'mdl_handle' => 3.0009765625,
2191 
            'model_handle' => 3.0009765625,
2192 
            'n_bits' => 1,
2193 
            'ownership' => 2,
2194 
            'period' => 5.0E-9,
2195 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2196 
            'shared_memory_name' => 'register08tv',
2197 
          },
2198 
          'needs_vhdl_wrapper' => 0,
2199 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register21',
2200 
        },
2201 
        'entityName' => 'x_x99',
2202 
        'ports' => {
2203 
          'data_out' => {
2204 
            'attributes' => {
2205 
              'bin_pt' => 0,
2206 
              'is_floating_block' => 1,
2207 
              'must_be_hdl_vector' => 1,
2208 
              'period' => 1.0,
2209 
              'port_id' => '0',
2210 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register21/data_out',
2211 
              'type' => 'UFix_1_0',
2212 
            },
2213 
            'direction' => 'out',
2214 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2215 
            'width' => 1,
2216 
          },
2217 
        },
2218 
      },
2219 
      'entityName' => 'x_x99',
2220 
    },
2221 
    'from_register22' => {
2222 
      'connections' => { 'data_out' => 'data_out_x10_net', },
2223 
      'entity' => {
2224 
        'attributes' => {
2225 
          'generics' => [],
2226 
          'is_floating_block' => 1,
2227 
          'mask' => {
2228 
            'Block_Handle' => 398.0009765625,
2229 
            'Block_handle' => 398.0009765625,
2230 
            'MDL_Handle' => 3.0009765625,
2231 
            'MDL_handle' => 3.0009765625,
2232 
            'arith_type' => 2,
2233 
            'bin_pt' => 0,
2234 
            'block_config' => 'sysgen_blockset:fromreg_config',
2235 
            'block_handle' => 398.0009765625,
2236 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register22',
2237 
            'block_type' => 'fromreg',
2238 
            'dbl_ovrd' => 0,
2239 
            'init' => 0.0,
2240 
            'init_bit_vector' => '00000000000000000000000000000000b',
2241 
            'mdl_handle' => 3.0009765625,
2242 
            'model_handle' => 3.0009765625,
2243 
            'n_bits' => 32,
2244 
            'ownership' => 2,
2245 
            'period' => 5.0E-9,
2246 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2247 
            'shared_memory_name' => 'register09td',
2248 
          },
2249 
          'needs_vhdl_wrapper' => 0,
2250 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register22',
2251 
        },
2252 
        'entityName' => 'x_x100',
2253 
        'ports' => {
2254 
          'data_out' => {
2255 
            'attributes' => {
2256 
              'bin_pt' => 0,
2257 
              'is_floating_block' => 1,
2258 
              'must_be_hdl_vector' => 1,
2259 
              'period' => 1.0,
2260 
              'port_id' => '0',
2261 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register22/data_out',
2262 
              'type' => 'UFix_32_0',
2263 
            },
2264 
            'direction' => 'out',
2265 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2266 
            'width' => 32,
2267 
          },
2268 
        },
2269 
      },
2270 
      'entityName' => 'x_x100',
2271 
    },
2272 
    'from_register23' => {
2273 
      'connections' => { 'data_out' => 'data_out_x11_net', },
2274 
      'entity' => {
2275 
        'attributes' => {
2276 
          'generics' => [],
2277 
          'is_floating_block' => 1,
2278 
          'mask' => {
2279 
            'Block_Handle' => 399.0009765625,
2280 
            'Block_handle' => 399.0009765625,
2281 
            'MDL_Handle' => 3.0009765625,
2282 
            'MDL_handle' => 3.0009765625,
2283 
            'arith_type' => 2,
2284 
            'bin_pt' => 0,
2285 
            'block_config' => 'sysgen_blockset:fromreg_config',
2286 
            'block_handle' => 399.0009765625,
2287 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register23',
2288 
            'block_type' => 'fromreg',
2289 
            'dbl_ovrd' => 0,
2290 
            'init' => 0.0,
2291 
            'init_bit_vector' => '0b',
2292 
            'mdl_handle' => 3.0009765625,
2293 
            'model_handle' => 3.0009765625,
2294 
            'n_bits' => 1,
2295 
            'ownership' => 2,
2296 
            'period' => 5.0E-9,
2297 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2298 
            'shared_memory_name' => 'register09tv',
2299 
          },
2300 
          'needs_vhdl_wrapper' => 0,
2301 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register23',
2302 
        },
2303 
        'entityName' => 'x_x101',
2304 
        'ports' => {
2305 
          'data_out' => {
2306 
            'attributes' => {
2307 
              'bin_pt' => 0,
2308 
              'is_floating_block' => 1,
2309 
              'must_be_hdl_vector' => 1,
2310 
              'period' => 1.0,
2311 
              'port_id' => '0',
2312 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register23/data_out',
2313 
              'type' => 'UFix_1_0',
2314 
            },
2315 
            'direction' => 'out',
2316 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2317 
            'width' => 1,
2318 
          },
2319 
        },
2320 
      },
2321 
      'entityName' => 'x_x101',
2322 
    },
2323 
    'from_register24' => {
2324 
      'connections' => { 'data_out' => 'data_out_x12_net', },
2325 
      'entity' => {
2326 
        'attributes' => {
2327 
          'generics' => [],
2328 
          'is_floating_block' => 1,
2329 
          'mask' => {
2330 
            'Block_Handle' => 400.0009765625,
2331 
            'Block_handle' => 400.0009765625,
2332 
            'MDL_Handle' => 3.0009765625,
2333 
            'MDL_handle' => 3.0009765625,
2334 
            'arith_type' => 2,
2335 
            'bin_pt' => 0,
2336 
            'block_config' => 'sysgen_blockset:fromreg_config',
2337 
            'block_handle' => 400.0009765625,
2338 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register24',
2339 
            'block_type' => 'fromreg',
2340 
            'dbl_ovrd' => 0,
2341 
            'init' => 0.0,
2342 
            'init_bit_vector' => '00000000000000000000000000000000b',
2343 
            'mdl_handle' => 3.0009765625,
2344 
            'model_handle' => 3.0009765625,
2345 
            'n_bits' => 32,
2346 
            'ownership' => 2,
2347 
            'period' => 5.0E-9,
2348 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2349 
            'shared_memory_name' => 'register10td',
2350 
          },
2351 
          'needs_vhdl_wrapper' => 0,
2352 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register24',
2353 
        },
2354 
        'entityName' => 'x_x102',
2355 
        'ports' => {
2356 
          'data_out' => {
2357 
            'attributes' => {
2358 
              'bin_pt' => 0,
2359 
              'is_floating_block' => 1,
2360 
              'must_be_hdl_vector' => 1,
2361 
              'period' => 1.0,
2362 
              'port_id' => '0',
2363 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register24/data_out',
2364 
              'type' => 'UFix_32_0',
2365 
            },
2366 
            'direction' => 'out',
2367 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2368 
            'width' => 32,
2369 
          },
2370 
        },
2371 
      },
2372 
      'entityName' => 'x_x102',
2373 
    },
2374 
    'from_register25' => {
2375 
      'connections' => { 'data_out' => 'data_out_x13_net', },
2376 
      'entity' => {
2377 
        'attributes' => {
2378 
          'generics' => [],
2379 
          'is_floating_block' => 1,
2380 
          'mask' => {
2381 
            'Block_Handle' => 401.0009765625,
2382 
            'Block_handle' => 401.0009765625,
2383 
            'MDL_Handle' => 3.0009765625,
2384 
            'MDL_handle' => 3.0009765625,
2385 
            'arith_type' => 2,
2386 
            'bin_pt' => 0,
2387 
            'block_config' => 'sysgen_blockset:fromreg_config',
2388 
            'block_handle' => 401.0009765625,
2389 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register25',
2390 
            'block_type' => 'fromreg',
2391 
            'dbl_ovrd' => 0,
2392 
            'init' => 0.0,
2393 
            'init_bit_vector' => '0b',
2394 
            'mdl_handle' => 3.0009765625,
2395 
            'model_handle' => 3.0009765625,
2396 
            'n_bits' => 1,
2397 
            'ownership' => 2,
2398 
            'period' => 5.0E-9,
2399 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2400 
            'shared_memory_name' => 'register10tv',
2401 
          },
2402 
          'needs_vhdl_wrapper' => 0,
2403 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register25',
2404 
        },
2405 
        'entityName' => 'x_x103',
2406 
        'ports' => {
2407 
          'data_out' => {
2408 
            'attributes' => {
2409 
              'bin_pt' => 0,
2410 
              'is_floating_block' => 1,
2411 
              'must_be_hdl_vector' => 1,
2412 
              'period' => 1.0,
2413 
              'port_id' => '0',
2414 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register25/data_out',
2415 
              'type' => 'UFix_1_0',
2416 
            },
2417 
            'direction' => 'out',
2418 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2419 
            'width' => 1,
2420 
          },
2421 
        },
2422 
      },
2423 
      'entityName' => 'x_x103',
2424 
    },
2425 
    'from_register26' => {
2426 
      'connections' => { 'data_out' => 'data_out_x14_net', },
2427 
      'entity' => {
2428 
        'attributes' => {
2429 
          'generics' => [],
2430 
          'is_floating_block' => 1,
2431 
          'mask' => {
2432 
            'Block_Handle' => 402.0009765625,
2433 
            'Block_handle' => 402.0009765625,
2434 
            'MDL_Handle' => 3.0009765625,
2435 
            'MDL_handle' => 3.0009765625,
2436 
            'arith_type' => 2,
2437 
            'bin_pt' => 0,
2438 
            'block_config' => 'sysgen_blockset:fromreg_config',
2439 
            'block_handle' => 402.0009765625,
2440 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register26',
2441 
            'block_type' => 'fromreg',
2442 
            'dbl_ovrd' => 0,
2443 
            'init' => 0.0,
2444 
            'init_bit_vector' => '00000000000000000000000000000000b',
2445 
            'mdl_handle' => 3.0009765625,
2446 
            'model_handle' => 3.0009765625,
2447 
            'n_bits' => 32,
2448 
            'ownership' => 2,
2449 
            'period' => 5.0E-9,
2450 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2451 
            'shared_memory_name' => 'register11td',
2452 
          },
2453 
          'needs_vhdl_wrapper' => 0,
2454 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register26',
2455 
        },
2456 
        'entityName' => 'x_x104',
2457 
        'ports' => {
2458 
          'data_out' => {
2459 
            'attributes' => {
2460 
              'bin_pt' => 0,
2461 
              'is_floating_block' => 1,
2462 
              'must_be_hdl_vector' => 1,
2463 
              'period' => 1.0,
2464 
              'port_id' => '0',
2465 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register26/data_out',
2466 
              'type' => 'UFix_32_0',
2467 
            },
2468 
            'direction' => 'out',
2469 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2470 
            'width' => 32,
2471 
          },
2472 
        },
2473 
      },
2474 
      'entityName' => 'x_x104',
2475 
    },
2476 
    'from_register27' => {
2477 
      'connections' => { 'data_out' => 'data_out_x15_net', },
2478 
      'entity' => {
2479 
        'attributes' => {
2480 
          'generics' => [],
2481 
          'is_floating_block' => 1,
2482 
          'mask' => {
2483 
            'Block_Handle' => 403.0009765625,
2484 
            'Block_handle' => 403.0009765625,
2485 
            'MDL_Handle' => 3.0009765625,
2486 
            'MDL_handle' => 3.0009765625,
2487 
            'arith_type' => 2,
2488 
            'bin_pt' => 0,
2489 
            'block_config' => 'sysgen_blockset:fromreg_config',
2490 
            'block_handle' => 403.0009765625,
2491 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register27',
2492 
            'block_type' => 'fromreg',
2493 
            'dbl_ovrd' => 0,
2494 
            'init' => 0.0,
2495 
            'init_bit_vector' => '0b',
2496 
            'mdl_handle' => 3.0009765625,
2497 
            'model_handle' => 3.0009765625,
2498 
            'n_bits' => 1,
2499 
            'ownership' => 2,
2500 
            'period' => 5.0E-9,
2501 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2502 
            'shared_memory_name' => 'register11tv',
2503 
          },
2504 
          'needs_vhdl_wrapper' => 0,
2505 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register27',
2506 
        },
2507 
        'entityName' => 'x_x105',
2508 
        'ports' => {
2509 
          'data_out' => {
2510 
            'attributes' => {
2511 
              'bin_pt' => 0,
2512 
              'is_floating_block' => 1,
2513 
              'must_be_hdl_vector' => 1,
2514 
              'period' => 1.0,
2515 
              'port_id' => '0',
2516 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register27/data_out',
2517 
              'type' => 'UFix_1_0',
2518 
            },
2519 
            'direction' => 'out',
2520 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2521 
            'width' => 1,
2522 
          },
2523 
        },
2524 
      },
2525 
      'entityName' => 'x_x105',
2526 
    },
2527 
    'from_register28' => {
2528 
      'connections' => { 'data_out' => 'data_out_x16_net', },
2529 
      'entity' => {
2530 
        'attributes' => {
2531 
          'generics' => [],
2532 
          'is_floating_block' => 1,
2533 
          'mask' => {
2534 
            'Block_Handle' => 404.0009765625,
2535 
            'Block_handle' => 404.0009765625,
2536 
            'MDL_Handle' => 3.0009765625,
2537 
            'MDL_handle' => 3.0009765625,
2538 
            'arith_type' => 2,
2539 
            'bin_pt' => 0,
2540 
            'block_config' => 'sysgen_blockset:fromreg_config',
2541 
            'block_handle' => 404.0009765625,
2542 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register28',
2543 
            'block_type' => 'fromreg',
2544 
            'dbl_ovrd' => 0,
2545 
            'init' => 0.0,
2546 
            'init_bit_vector' => '00000000000000000000000000000000b',
2547 
            'mdl_handle' => 3.0009765625,
2548 
            'model_handle' => 3.0009765625,
2549 
            'n_bits' => 32,
2550 
            'ownership' => 2,
2551 
            'period' => 5.0E-9,
2552 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2553 
            'shared_memory_name' => 'register12td',
2554 
          },
2555 
          'needs_vhdl_wrapper' => 0,
2556 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register28',
2557 
        },
2558 
        'entityName' => 'x_x106',
2559 
        'ports' => {
2560 
          'data_out' => {
2561 
            'attributes' => {
2562 
              'bin_pt' => 0,
2563 
              'is_floating_block' => 1,
2564 
              'must_be_hdl_vector' => 1,
2565 
              'period' => 1.0,
2566 
              'port_id' => '0',
2567 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register28/data_out',
2568 
              'type' => 'UFix_32_0',
2569 
            },
2570 
            'direction' => 'out',
2571 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2572 
            'width' => 32,
2573 
          },
2574 
        },
2575 
      },
2576 
      'entityName' => 'x_x106',
2577 
    },
2578 
    'from_register29' => {
2579 
      'connections' => { 'data_out' => 'data_out_x17_net', },
2580 
      'entity' => {
2581 
        'attributes' => {
2582 
          'generics' => [],
2583 
          'is_floating_block' => 1,
2584 
          'mask' => {
2585 
            'Block_Handle' => 405.0009765625,
2586 
            'Block_handle' => 405.0009765625,
2587 
            'MDL_Handle' => 3.0009765625,
2588 
            'MDL_handle' => 3.0009765625,
2589 
            'arith_type' => 2,
2590 
            'bin_pt' => 0,
2591 
            'block_config' => 'sysgen_blockset:fromreg_config',
2592 
            'block_handle' => 405.0009765625,
2593 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register29',
2594 
            'block_type' => 'fromreg',
2595 
            'dbl_ovrd' => 0,
2596 
            'init' => 0.0,
2597 
            'init_bit_vector' => '0b',
2598 
            'mdl_handle' => 3.0009765625,
2599 
            'model_handle' => 3.0009765625,
2600 
            'n_bits' => 1,
2601 
            'ownership' => 2,
2602 
            'period' => 5.0E-9,
2603 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2604 
            'shared_memory_name' => 'register12tv',
2605 
          },
2606 
          'needs_vhdl_wrapper' => 0,
2607 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register29',
2608 
        },
2609 
        'entityName' => 'x_x107',
2610 
        'ports' => {
2611 
          'data_out' => {
2612 
            'attributes' => {
2613 
              'bin_pt' => 0,
2614 
              'is_floating_block' => 1,
2615 
              'must_be_hdl_vector' => 1,
2616 
              'period' => 1.0,
2617 
              'port_id' => '0',
2618 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register29/data_out',
2619 
              'type' => 'UFix_1_0',
2620 
            },
2621 
            'direction' => 'out',
2622 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2623 
            'width' => 1,
2624 
          },
2625 
        },
2626 
      },
2627 
      'entityName' => 'x_x107',
2628 
    },
2629 
    'from_register3' => {
2630 
      'connections' => { 'data_out' => 'data_out_x18_net', },
2631 
      'entity' => {
2632 
        'attributes' => {
2633 
          'generics' => [],
2634 
          'is_floating_block' => 1,
2635 
          'mask' => {
2636 
            'Block_Handle' => 406.0009765625,
2637 
            'Block_handle' => 406.0009765625,
2638 
            'MDL_Handle' => 3.0009765625,
2639 
            'MDL_handle' => 3.0009765625,
2640 
            'arith_type' => 2,
2641 
            'bin_pt' => 0,
2642 
            'block_config' => 'sysgen_blockset:fromreg_config',
2643 
            'block_handle' => 406.0009765625,
2644 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register3',
2645 
            'block_type' => 'fromreg',
2646 
            'dbl_ovrd' => 0,
2647 
            'init' => 0.0,
2648 
            'init_bit_vector' => '00000000000000000000000000000000b',
2649 
            'mdl_handle' => 3.0009765625,
2650 
            'model_handle' => 3.0009765625,
2651 
            'n_bits' => 32,
2652 
            'ownership' => 2,
2653 
            'period' => 5.0E-9,
2654 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2655 
            'shared_memory_name' => 'register01td',
2656 
          },
2657 
          'needs_vhdl_wrapper' => 0,
2658 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register3',
2659 
        },
2660 
        'entityName' => 'x_x108',
2661 
        'ports' => {
2662 
          'data_out' => {
2663 
            'attributes' => {
2664 
              'bin_pt' => 0,
2665 
              'is_floating_block' => 1,
2666 
              'must_be_hdl_vector' => 1,
2667 
              'period' => 1.0,
2668 
              'port_id' => '0',
2669 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register3/data_out',
2670 
              'type' => 'UFix_32_0',
2671 
            },
2672 
            'direction' => 'out',
2673 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2674 
            'width' => 32,
2675 
          },
2676 
        },
2677 
      },
2678 
      'entityName' => 'x_x108',
2679 
    },
2680 
    'from_register30' => {
2681 
      'connections' => { 'data_out' => 'data_out_x19_net', },
2682 
      'entity' => {
2683 
        'attributes' => {
2684 
          'generics' => [],
2685 
          'is_floating_block' => 1,
2686 
          'mask' => {
2687 
            'Block_Handle' => 407.0009765625,
2688 
            'Block_handle' => 407.0009765625,
2689 
            'MDL_Handle' => 3.0009765625,
2690 
            'MDL_handle' => 3.0009765625,
2691 
            'arith_type' => 2,
2692 
            'bin_pt' => 0,
2693 
            'block_config' => 'sysgen_blockset:fromreg_config',
2694 
            'block_handle' => 407.0009765625,
2695 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register30',
2696 
            'block_type' => 'fromreg',
2697 
            'dbl_ovrd' => 0,
2698 
            'init' => 0.0,
2699 
            'init_bit_vector' => '00000000000000000000000000000000b',
2700 
            'mdl_handle' => 3.0009765625,
2701 
            'model_handle' => 3.0009765625,
2702 
            'n_bits' => 32,
2703 
            'ownership' => 2,
2704 
            'period' => 5.0E-9,
2705 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2706 
            'shared_memory_name' => 'register13td',
2707 
          },
2708 
          'needs_vhdl_wrapper' => 0,
2709 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register30',
2710 
        },
2711 
        'entityName' => 'x_x109',
2712 
        'ports' => {
2713 
          'data_out' => {
2714 
            'attributes' => {
2715 
              'bin_pt' => 0,
2716 
              'is_floating_block' => 1,
2717 
              'must_be_hdl_vector' => 1,
2718 
              'period' => 1.0,
2719 
              'port_id' => '0',
2720 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register30/data_out',
2721 
              'type' => 'UFix_32_0',
2722 
            },
2723 
            'direction' => 'out',
2724 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2725 
            'width' => 32,
2726 
          },
2727 
        },
2728 
      },
2729 
      'entityName' => 'x_x109',
2730 
    },
2731 
    'from_register31' => {
2732 
      'connections' => { 'data_out' => 'data_out_x20_net', },
2733 
      'entity' => {
2734 
        'attributes' => {
2735 
          'generics' => [],
2736 
          'is_floating_block' => 1,
2737 
          'mask' => {
2738 
            'Block_Handle' => 408.0009765625,
2739 
            'Block_handle' => 408.0009765625,
2740 
            'MDL_Handle' => 3.0009765625,
2741 
            'MDL_handle' => 3.0009765625,
2742 
            'arith_type' => 2,
2743 
            'bin_pt' => 0,
2744 
            'block_config' => 'sysgen_blockset:fromreg_config',
2745 
            'block_handle' => 408.0009765625,
2746 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register31',
2747 
            'block_type' => 'fromreg',
2748 
            'dbl_ovrd' => 0,
2749 
            'init' => 0.0,
2750 
            'init_bit_vector' => '0b',
2751 
            'mdl_handle' => 3.0009765625,
2752 
            'model_handle' => 3.0009765625,
2753 
            'n_bits' => 1,
2754 
            'ownership' => 2,
2755 
            'period' => 5.0E-9,
2756 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2757 
            'shared_memory_name' => 'register13tv',
2758 
          },
2759 
          'needs_vhdl_wrapper' => 0,
2760 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register31',
2761 
        },
2762 
        'entityName' => 'x_x110',
2763 
        'ports' => {
2764 
          'data_out' => {
2765 
            'attributes' => {
2766 
              'bin_pt' => 0,
2767 
              'is_floating_block' => 1,
2768 
              'must_be_hdl_vector' => 1,
2769 
              'period' => 1.0,
2770 
              'port_id' => '0',
2771 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register31/data_out',
2772 
              'type' => 'UFix_1_0',
2773 
            },
2774 
            'direction' => 'out',
2775 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2776 
            'width' => 1,
2777 
          },
2778 
        },
2779 
      },
2780 
      'entityName' => 'x_x110',
2781 
    },
2782 
    'from_register32' => {
2783 
      'connections' => { 'data_out' => 'data_out_x21_net', },
2784 
      'entity' => {
2785 
        'attributes' => {
2786 
          'generics' => [],
2787 
          'is_floating_block' => 1,
2788 
          'mask' => {
2789 
            'Block_Handle' => 409.0009765625,
2790 
            'Block_handle' => 409.0009765625,
2791 
            'MDL_Handle' => 3.0009765625,
2792 
            'MDL_handle' => 3.0009765625,
2793 
            'arith_type' => 2,
2794 
            'bin_pt' => 0,
2795 
            'block_config' => 'sysgen_blockset:fromreg_config',
2796 
            'block_handle' => 409.0009765625,
2797 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register32',
2798 
            'block_type' => 'fromreg',
2799 
            'dbl_ovrd' => 0,
2800 
            'init' => 0.0,
2801 
            'init_bit_vector' => '00000000000000000000000000000000b',
2802 
            'mdl_handle' => 3.0009765625,
2803 
            'model_handle' => 3.0009765625,
2804 
            'n_bits' => 32,
2805 
            'ownership' => 2,
2806 
            'period' => 5.0E-9,
2807 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2808 
            'shared_memory_name' => 'register14td',
2809 
          },
2810 
          'needs_vhdl_wrapper' => 0,
2811 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register32',
2812 
        },
2813 
        'entityName' => 'x_x111',
2814 
        'ports' => {
2815 
          'data_out' => {
2816 
            'attributes' => {
2817 
              'bin_pt' => 0,
2818 
              'is_floating_block' => 1,
2819 
              'must_be_hdl_vector' => 1,
2820 
              'period' => 1.0,
2821 
              'port_id' => '0',
2822 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register32/data_out',
2823 
              'type' => 'UFix_32_0',
2824 
            },
2825 
            'direction' => 'out',
2826 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2827 
            'width' => 32,
2828 
          },
2829 
        },
2830 
      },
2831 
      'entityName' => 'x_x111',
2832 
    },
2833 
    'from_register33' => {
2834 
      'connections' => { 'data_out' => 'data_out_x22_net', },
2835 
      'entity' => {
2836 
        'attributes' => {
2837 
          'generics' => [],
2838 
          'is_floating_block' => 1,
2839 
          'mask' => {
2840 
            'Block_Handle' => 410.0009765625,
2841 
            'Block_handle' => 410.0009765625,
2842 
            'MDL_Handle' => 3.0009765625,
2843 
            'MDL_handle' => 3.0009765625,
2844 
            'arith_type' => 2,
2845 
            'bin_pt' => 0,
2846 
            'block_config' => 'sysgen_blockset:fromreg_config',
2847 
            'block_handle' => 410.0009765625,
2848 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register33',
2849 
            'block_type' => 'fromreg',
2850 
            'dbl_ovrd' => 0,
2851 
            'init' => 0.0,
2852 
            'init_bit_vector' => '0b',
2853 
            'mdl_handle' => 3.0009765625,
2854 
            'model_handle' => 3.0009765625,
2855 
            'n_bits' => 1,
2856 
            'ownership' => 2,
2857 
            'period' => 5.0E-9,
2858 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2859 
            'shared_memory_name' => 'register14tv',
2860 
          },
2861 
          'needs_vhdl_wrapper' => 0,
2862 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register33',
2863 
        },
2864 
        'entityName' => 'x_x112',
2865 
        'ports' => {
2866 
          'data_out' => {
2867 
            'attributes' => {
2868 
              'bin_pt' => 0,
2869 
              'is_floating_block' => 1,
2870 
              'must_be_hdl_vector' => 1,
2871 
              'period' => 1.0,
2872 
              'port_id' => '0',
2873 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register33/data_out',
2874 
              'type' => 'UFix_1_0',
2875 
            },
2876 
            'direction' => 'out',
2877 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2878 
            'width' => 1,
2879 
          },
2880 
        },
2881 
      },
2882 
      'entityName' => 'x_x112',
2883 
    },
2884 
    'from_register4' => {
2885 
      'connections' => { 'data_out' => 'data_out_x23_net', },
2886 
      'entity' => {
2887 
        'attributes' => {
2888 
          'generics' => [],
2889 
          'is_floating_block' => 1,
2890 
          'mask' => {
2891 
            'Block_Handle' => 411.0009765625,
2892 
            'Block_handle' => 411.0009765625,
2893 
            'MDL_Handle' => 3.0009765625,
2894 
            'MDL_handle' => 3.0009765625,
2895 
            'arith_type' => 2,
2896 
            'bin_pt' => 0,
2897 
            'block_config' => 'sysgen_blockset:fromreg_config',
2898 
            'block_handle' => 411.0009765625,
2899 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register4',
2900 
            'block_type' => 'fromreg',
2901 
            'dbl_ovrd' => 0,
2902 
            'init' => 0.0,
2903 
            'init_bit_vector' => '0b',
2904 
            'mdl_handle' => 3.0009765625,
2905 
            'model_handle' => 3.0009765625,
2906 
            'n_bits' => 1,
2907 
            'ownership' => 2,
2908 
            'period' => 5.0E-9,
2909 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2910 
            'shared_memory_name' => 'register01tv',
2911 
          },
2912 
          'needs_vhdl_wrapper' => 0,
2913 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register4',
2914 
        },
2915 
        'entityName' => 'x_x113',
2916 
        'ports' => {
2917 
          'data_out' => {
2918 
            'attributes' => {
2919 
              'bin_pt' => 0,
2920 
              'is_floating_block' => 1,
2921 
              'must_be_hdl_vector' => 1,
2922 
              'period' => 1.0,
2923 
              'port_id' => '0',
2924 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register4/data_out',
2925 
              'type' => 'UFix_1_0',
2926 
            },
2927 
            'direction' => 'out',
2928 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2929 
            'width' => 1,
2930 
          },
2931 
        },
2932 
      },
2933 
      'entityName' => 'x_x113',
2934 
    },
2935 
    'from_register5' => {
2936 
      'connections' => { 'data_out' => 'data_out_x24_net', },
2937 
      'entity' => {
2938 
        'attributes' => {
2939 
          'generics' => [],
2940 
          'is_floating_block' => 1,
2941 
          'mask' => {
2942 
            'Block_Handle' => 412.0009765625,
2943 
            'Block_handle' => 412.0009765625,
2944 
            'MDL_Handle' => 3.0009765625,
2945 
            'MDL_handle' => 3.0009765625,
2946 
            'arith_type' => 2,
2947 
            'bin_pt' => 0,
2948 
            'block_config' => 'sysgen_blockset:fromreg_config',
2949 
            'block_handle' => 412.0009765625,
2950 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register5',
2951 
            'block_type' => 'fromreg',
2952 
            'dbl_ovrd' => 0,
2953 
            'init' => 0.0,
2954 
            'init_bit_vector' => '00000000000000000000000000000000b',
2955 
            'mdl_handle' => 3.0009765625,
2956 
            'model_handle' => 3.0009765625,
2957 
            'n_bits' => 32,
2958 
            'ownership' => 2,
2959 
            'period' => 5.0E-9,
2960 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2961 
            'shared_memory_name' => 'register02td',
2962 
          },
2963 
          'needs_vhdl_wrapper' => 0,
2964 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register5',
2965 
        },
2966 
        'entityName' => 'x_x114',
2967 
        'ports' => {
2968 
          'data_out' => {
2969 
            'attributes' => {
2970 
              'bin_pt' => 0,
2971 
              'is_floating_block' => 1,
2972 
              'must_be_hdl_vector' => 1,
2973 
              'period' => 1.0,
2974 
              'port_id' => '0',
2975 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register5/data_out',
2976 
              'type' => 'UFix_32_0',
2977 
            },
2978 
            'direction' => 'out',
2979 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2980 
            'width' => 32,
2981 
          },
2982 
        },
2983 
      },
2984 
      'entityName' => 'x_x114',
2985 
    },
2986 
    'from_register6' => {
2987 
      'connections' => { 'data_out' => 'data_out_x25_net', },
2988 
      'entity' => {
2989 
        'attributes' => {
2990 
          'generics' => [],
2991 
          'is_floating_block' => 1,
2992 
          'mask' => {
2993 
            'Block_Handle' => 413.0009765625,
2994 
            'Block_handle' => 413.0009765625,
2995 
            'MDL_Handle' => 3.0009765625,
2996 
            'MDL_handle' => 3.0009765625,
2997 
            'arith_type' => 2,
2998 
            'bin_pt' => 0,
2999 
            'block_config' => 'sysgen_blockset:fromreg_config',
3000 
            'block_handle' => 413.0009765625,
3001 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register6',
3002 
            'block_type' => 'fromreg',
3003 
            'dbl_ovrd' => 0,
3004 
            'init' => 0.0,
3005 
            'init_bit_vector' => '0b',
3006 
            'mdl_handle' => 3.0009765625,
3007 
            'model_handle' => 3.0009765625,
3008 
            'n_bits' => 1,
3009 
            'ownership' => 2,
3010 
            'period' => 5.0E-9,
3011 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3012 
            'shared_memory_name' => 'register02tv',
3013 
          },
3014 
          'needs_vhdl_wrapper' => 0,
3015 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register6',
3016 
        },
3017 
        'entityName' => 'x_x115',
3018 
        'ports' => {
3019 
          'data_out' => {
3020 
            'attributes' => {
3021 
              'bin_pt' => 0,
3022 
              'is_floating_block' => 1,
3023 
              'must_be_hdl_vector' => 1,
3024 
              'period' => 1.0,
3025 
              'port_id' => '0',
3026 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register6/data_out',
3027 
              'type' => 'UFix_1_0',
3028 
            },
3029 
            'direction' => 'out',
3030 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3031 
            'width' => 1,
3032 
          },
3033 
        },
3034 
      },
3035 
      'entityName' => 'x_x115',
3036 
    },
3037 
    'from_register7' => {
3038 
      'connections' => { 'data_out' => 'data_out_x26_net', },
3039 
      'entity' => {
3040 
        'attributes' => {
3041 
          'generics' => [],
3042 
          'is_floating_block' => 1,
3043 
          'mask' => {
3044 
            'Block_Handle' => 414.0009765625,
3045 
            'Block_handle' => 414.0009765625,
3046 
            'MDL_Handle' => 3.0009765625,
3047 
            'MDL_handle' => 3.0009765625,
3048 
            'arith_type' => 2,
3049 
            'bin_pt' => 0,
3050 
            'block_config' => 'sysgen_blockset:fromreg_config',
3051 
            'block_handle' => 414.0009765625,
3052 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7',
3053 
            'block_type' => 'fromreg',
3054 
            'dbl_ovrd' => 0,
3055 
            'init' => 0.0,
3056 
            'init_bit_vector' => '00000000000000000000000000000000b',
3057 
            'mdl_handle' => 3.0009765625,
3058 
            'model_handle' => 3.0009765625,
3059 
            'n_bits' => 32,
3060 
            'ownership' => 2,
3061 
            'period' => 5.0E-9,
3062 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3063 
            'shared_memory_name' => 'register03td',
3064 
          },
3065 
          'needs_vhdl_wrapper' => 0,
3066 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7',
3067 
        },
3068 
        'entityName' => 'x_x116',
3069 
        'ports' => {
3070 
          'data_out' => {
3071 
            'attributes' => {
3072 
              'bin_pt' => 0,
3073 
              'is_floating_block' => 1,
3074 
              'must_be_hdl_vector' => 1,
3075 
              'period' => 1.0,
3076 
              'port_id' => '0',
3077 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7/data_out',
3078 
              'type' => 'UFix_32_0',
3079 
            },
3080 
            'direction' => 'out',
3081 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3082 
            'width' => 32,
3083 
          },
3084 
        },
3085 
      },
3086 
      'entityName' => 'x_x116',
3087 
    },
3088 
    'from_register8' => {
3089 
      'connections' => { 'data_out' => 'data_out_x27_net', },
3090 
      'entity' => {
3091 
        'attributes' => {
3092 
          'generics' => [],
3093 
          'is_floating_block' => 1,
3094 
          'mask' => {
3095 
            'Block_Handle' => 415.0009765625,
3096 
            'Block_handle' => 415.0009765625,
3097 
            'MDL_Handle' => 3.0009765625,
3098 
            'MDL_handle' => 3.0009765625,
3099 
            'arith_type' => 2,
3100 
            'bin_pt' => 0,
3101 
            'block_config' => 'sysgen_blockset:fromreg_config',
3102 
            'block_handle' => 415.0009765625,
3103 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8',
3104 
            'block_type' => 'fromreg',
3105 
            'dbl_ovrd' => 0,
3106 
            'init' => 0.0,
3107 
            'init_bit_vector' => '0b',
3108 
            'mdl_handle' => 3.0009765625,
3109 
            'model_handle' => 3.0009765625,
3110 
            'n_bits' => 1,
3111 
            'ownership' => 2,
3112 
            'period' => 5.0E-9,
3113 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3114 
            'shared_memory_name' => 'register03tv',
3115 
          },
3116 
          'needs_vhdl_wrapper' => 0,
3117 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8',
3118 
        },
3119 
        'entityName' => 'x_x117',
3120 
        'ports' => {
3121 
          'data_out' => {
3122 
            'attributes' => {
3123 
              'bin_pt' => 0,
3124 
              'is_floating_block' => 1,
3125 
              'must_be_hdl_vector' => 1,
3126 
              'period' => 1.0,
3127 
              'port_id' => '0',
3128 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8/data_out',
3129 
              'type' => 'UFix_1_0',
3130 
            },
3131 
            'direction' => 'out',
3132 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3133 
            'width' => 1,
3134 
          },
3135 
        },
3136 
      },
3137 
      'entityName' => 'x_x117',
3138 
    },
3139 
    'from_register9' => {
3140 
      'connections' => { 'data_out' => 'data_out_x28_net', },
3141 
      'entity' => {
3142 
        'attributes' => {
3143 
          'generics' => [],
3144 
          'is_floating_block' => 1,
3145 
          'mask' => {
3146 
            'Block_Handle' => 416.0009765625,
3147 
            'Block_handle' => 416.0009765625,
3148 
            'MDL_Handle' => 3.0009765625,
3149 
            'MDL_handle' => 3.0009765625,
3150 
            'arith_type' => 2,
3151 
            'bin_pt' => 0,
3152 
            'block_config' => 'sysgen_blockset:fromreg_config',
3153 
            'block_handle' => 416.0009765625,
3154 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9',
3155 
            'block_type' => 'fromreg',
3156 
            'dbl_ovrd' => 0,
3157 
            'init' => 0.0,
3158 
            'init_bit_vector' => '00000000000000000000000000000000b',
3159 
            'mdl_handle' => 3.0009765625,
3160 
            'model_handle' => 3.0009765625,
3161 
            'n_bits' => 32,
3162 
            'ownership' => 2,
3163 
            'period' => 5.0E-9,
3164 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3165 
            'shared_memory_name' => 'register04td',
3166 
          },
3167 
          'needs_vhdl_wrapper' => 0,
3168 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9',
3169 
        },
3170 
        'entityName' => 'x_x118',
3171 
        'ports' => {
3172 
          'data_out' => {
3173 
            'attributes' => {
3174 
              'bin_pt' => 0,
3175 
              'is_floating_block' => 1,
3176 
              'must_be_hdl_vector' => 1,
3177 
              'period' => 1.0,
3178 
              'port_id' => '0',
3179 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9/data_out',
3180 
              'type' => 'UFix_32_0',
3181 
            },
3182 
            'direction' => 'out',
3183 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3184 
            'width' => 32,
3185 
          },
3186 
        },
3187 
      },
3188 
      'entityName' => 'x_x118',
3189 
    },
3190 
    'rst_i' => {
3191 
      'connections' => { 'rst_i' => 'rst_i_net', },
3192 
      'entity' => {
3193 
        'attributes' => {
3194 
          'isGateway' => 1,
3195 
          'is_floating_block' => 1,
3196 
        },
3197 
        'entityName' => 'rst_i',
3198 
        'ports' => {
3199 
          'rst_i' => {
3200 
            'attributes' => {
3201 
              'bin_pt' => 0,
3202 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_i.dat',
3203 
              'is_floating_block' => 1,
3204 
              'is_gateway_port' => 1,
3205 
              'must_be_hdl_vector' => 1,
3206 
              'period' => 1.0,
3207 
              'port_id' => '0',
3208 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_i/rst_i',
3209 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/rst_i',
3210 
              'timingConstraint' => 'none',
3211 
              'type' => 'Bool',
3212 
            },
3213 
            'direction' => 'out',
3214 
            'hdlType' => 'std_logic',
3215 
            'width' => 1,
3216 
          },
3217 
        },
3218 
      },
3219 
      'entityName' => 'rst_i',
3220 
    },
3221 
    'rst_o' => {
3222 
      'connections' => { 'rst_o' => 'rst_o_net', },
3223 
      'entity' => {
3224 
        'attributes' => {
3225 
          'isGateway' => 1,
3226 
          'is_floating_block' => 1,
3227 
        },
3228 
        'entityName' => 'rst_o',
3229 
        'ports' => {
3230 
          'rst_o' => {
3231 
            'attributes' => {
3232 
              'bin_pt' => 0,
3233 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
3234 
              'is_floating_block' => 1,
3235 
              'is_gateway_port' => 1,
3236 
              'must_be_hdl_vector' => 1,
3237 
              'period' => 1.0,
3238 
              'port_id' => '0',
3239 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_o/rst_o',
3240 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/rst_o',
3241 
              'timingConstraint' => 'none',
3242 
              'type' => 'Bool',
3243 
            },
3244 
            'direction' => 'in',
3245 
            'hdlType' => 'std_logic',
3246 
            'width' => 1,
3247 
          },
3248 
        },
3249 
      },
3250 
      'entityName' => 'rst_o',
3251 
    },
3252 
    'to_register' => {
3253 
      'connections' => {
3254 
        'ce' => 'ce_1_sg_x0',
3255 
        'clk' => 'clk_1_sg_x0',
3256 
        'clr' => [
3257 
          'constant',
3258 
          '\'0\'',
3259 
        ],
3260 
        'data_in' => 'data_in_net',
3261 
        'dout' => 'to_register_dout_net',
3262 
        'en' => 'constant6_op_net_x0',
3263 
      },
3264 
      'entity' => {
3265 
        'attributes' => {
3266 
          'generics' => [],
3267 
          'is_floating_block' => 1,
3268 
          'mask' => {
3269 
            'Block_Handle' => 981.0003662109375,
3270 
            'Block_handle' => 981.0003662109375,
3271 
            'MDL_Handle' => 3.0009765625,
3272 
            'MDL_handle' => 3.0009765625,
3273 
            'arith_type' => 1,
3274 
            'bin_pt' => 14,
3275 
            'block_config' => 'sysgen_blockset:toreg_config',
3276 
            'block_handle' => 981.0003662109375,
3277 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register',
3278 
            'block_type' => 'toreg',
3279 
            'dbl_ovrd' => 0,
3280 
            'explicit_data_type' => 0,
3281 
            'init' => 0.0,
3282 
            'init_bit_vector' => '00000000000000000000000000000000b',
3283 
            'mdl_handle' => 3.0009765625,
3284 
            'model_handle' => 3.0009765625,
3285 
            'n_bits' => 16,
3286 
            'ownership' => 1,
3287 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
3288 
            'shared_memory_name' => 'register01rd',
3289 
          },
3290 
          'needs_vhdl_wrapper' => 0,
3291 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register',
3292 
        },
3293 
        'entityName' => 'x_x33',
3294 
        'ports' => {
3295 
          'ce' => {
3296 
            'attributes' => {
3297 
              'domain' => '',
3298 
              'group' => 1,
3299 
              'isCe' => 1,
3300 
              'is_floating_block' => 1,
3301 
              'period' => 1.0,
3302 
              'type' => 'logic',
3303 
            },
3304 
            'direction' => 'in',
3305 
            'hdlType' => 'std_logic',
3306 
            'width' => 1,
3307 
          },
3308 
          'clk' => {
3309 
            'attributes' => {
3310 
              'domain' => '',
3311 
              'group' => 1,
3312 
              'isClk' => 1,
3313 
              'is_floating_block' => 1,
3314 
              'period' => 1.0,
3315 
              'type' => 'logic',
3316 
            },
3317 
            'direction' => 'in',
3318 
            'hdlType' => 'std_logic',
3319 
            'width' => 1,
3320 
          },
3321 
          'clr' => {
3322 
            'attributes' => {
3323 
              'domain' => '',
3324 
              'group' => 1,
3325 
              'isClr' => 1,
3326 
              'is_floating_block' => 1,
3327 
              'period' => 1,
3328 
              'type' => 'logic',
3329 
              'valid_bit_used' => 0,
3330 
            },
3331 
            'direction' => 'in',
3332 
            'hdlType' => 'std_logic',
3333 
            'width' => 1,
3334 
          },
3335 
          'data_in' => {
3336 
            'attributes' => {
3337 
              'bin_pt' => 0,
3338 
              'is_floating_block' => 1,
3339 
              'must_be_hdl_vector' => 1,
3340 
              'period' => 1.0,
3341 
              'port_id' => '0',
3342 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/data_in',
3343 
              'type' => 'UFix_32_0',
3344 
            },
3345 
            'direction' => 'in',
3346 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3347 
            'width' => 32,
3348 
          },
3349 
          'dout' => {
3350 
            'attributes' => {
3351 
              'bin_pt' => 0,
3352 
              'is_floating_block' => 1,
3353 
              'must_be_hdl_vector' => 1,
3354 
              'period' => 1.0,
3355 
              'port_id' => '0',
3356 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/dout',
3357 
              'type' => 'UFix_32_0',
3358 
            },
3359 
            'direction' => 'out',
3360 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3361 
            'width' => 32,
3362 
          },
3363 
          'en' => {
3364 
            'attributes' => {
3365 
              'bin_pt' => 0,
3366 
              'is_floating_block' => 1,
3367 
              'must_be_hdl_vector' => 1,
3368 
              'period' => 1.0,
3369 
              'port_id' => '1',
3370 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/en',
3371 
              'type' => 'Bool',
3372 
            },
3373 
            'direction' => 'in',
3374 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3375 
            'width' => 1,
3376 
          },
3377 
        },
3378 
      },
3379 
      'entityName' => 'x_x33',
3380 
    },
3381 
    'to_register1' => {
3382 
      'connections' => {
3383 
        'ce' => 'ce_1_sg_x0',
3384 
        'clk' => 'clk_1_sg_x0',
3385 
        'clr' => [
3386 
          'constant',
3387 
          '\'0\'',
3388 
        ],
3389 
        'data_in' => 'data_in_x0_net',
3390 
        'dout' => 'to_register1_dout_net',
3391 
        'en' => 'constant6_op_net_x1',
3392 
      },
3393 
      'entity' => {
3394 
        'attributes' => {
3395 
          'generics' => [],
3396 
          'is_floating_block' => 1,
3397 
          'mask' => {
3398 
            'Block_Handle' => 982.0001220703125,
3399 
            'Block_handle' => 982.0001220703125,
3400 
            'MDL_Handle' => 3.0009765625,
3401 
            'MDL_handle' => 3.0009765625,
3402 
            'arith_type' => 1,
3403 
            'bin_pt' => 14,
3404 
            'block_config' => 'sysgen_blockset:toreg_config',
3405 
            'block_handle' => 982.0001220703125,
3406 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register1',
3407 
            'block_type' => 'toreg',
3408 
            'dbl_ovrd' => 0,
3409 
            'explicit_data_type' => 0,
3410 
            'init' => 0.0,
3411 
            'init_bit_vector' => '0b',
3412 
            'mdl_handle' => 3.0009765625,
3413 
            'model_handle' => 3.0009765625,
3414 
            'n_bits' => 16,
3415 
            'ownership' => 1,
3416 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
3417 
            'shared_memory_name' => 'register01rv',
3418 
          },
3419 
          'needs_vhdl_wrapper' => 0,
3420 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register1',
3421 
        },
3422 
        'entityName' => 'x_x34',
3423 
        'ports' => {
3424 
          'ce' => {
3425 
            'attributes' => {
3426 
              'domain' => '',
3427 
              'group' => 1,
3428 
              'isCe' => 1,
3429 
              'is_floating_block' => 1,
3430 
              'period' => 1.0,
3431 
              'type' => 'logic',
3432 
            },
3433 
            'direction' => 'in',
3434 
            'hdlType' => 'std_logic',
3435 
            'width' => 1,
3436 
          },
3437 
          'clk' => {
3438 
            'attributes' => {
3439 
              'domain' => '',
3440 
              'group' => 1,
3441 
              'isClk' => 1,
3442 
              'is_floating_block' => 1,
3443 
              'period' => 1.0,
3444 
              'type' => 'logic',
3445 
            },
3446 
            'direction' => 'in',
3447 
            'hdlType' => 'std_logic',
3448 
            'width' => 1,
3449 
          },
3450 
          'clr' => {
3451 
            'attributes' => {
3452 
              'domain' => '',
3453 
              'group' => 1,
3454 
              'isClr' => 1,
3455 
              'is_floating_block' => 1,
3456 
              'period' => 1,
3457 
              'type' => 'logic',
3458 
              'valid_bit_used' => 0,
3459 
            },
3460 
            'direction' => 'in',
3461 
            'hdlType' => 'std_logic',
3462 
            'width' => 1,
3463 
          },
3464 
          'data_in' => {
3465 
            'attributes' => {
3466 
              'bin_pt' => 0,
3467 
              'is_floating_block' => 1,
3468 
              'must_be_hdl_vector' => 1,
3469 
              'period' => 1.0,
3470 
              'port_id' => '0',
3471 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register1/data_in',
3472 
              'type' => 'Bool',
3473 
            },
3474 
            'direction' => 'in',
3475 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3476 
            'width' => 1,
3477 
          },
3478 
          'dout' => {
3479 
            'attributes' => {
3480 
              'bin_pt' => 0,
3481 
              'is_floating_block' => 1,
3482 
              'must_be_hdl_vector' => 1,
3483 
              'period' => 1.0,
3484 
              'port_id' => '0',
3485 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register1/dout',
3486 
              'type' => 'Bool',
3487 
            },
3488 
            'direction' => 'out',
3489 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3490 
            'width' => 1,
3491 
          },
3492 
          'en' => {
3493 
            'attributes' => {
3494 
              'bin_pt' => 0,
3495 
              'is_floating_block' => 1,
3496 
              'must_be_hdl_vector' => 1,
3497 
              'period' => 1.0,
3498 
              'port_id' => '1',
3499 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register1/en',
3500 
              'type' => 'Bool',
3501 
            },
3502 
            'direction' => 'in',
3503 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3504 
            'width' => 1,
3505 
          },
3506 
        },
3507 
      },
3508 
      'entityName' => 'x_x34',
3509 
    },
3510 
    'to_register10' => {
3511 
      'connections' => {
3512 
        'ce' => 'ce_1_sg_x0',
3513 
        'clk' => 'clk_1_sg_x0',
3514 
        'clr' => [
3515 
          'constant',
3516 
          '\'0\'',
3517 
        ],
3518 
        'data_in' => 'data_in_x1_net',
3519 
        'dout' => 'to_register10_dout_net',
3520 
        'en' => 'constant6_op_net_x2',
3521 
      },
3522 
      'entity' => {
3523 
        'attributes' => {
3524 
          'generics' => [],
3525 
          'is_floating_block' => 1,
3526 
          'mask' => {
3527 
            'Block_Handle' => 983.0001220703125,
3528 
            'Block_handle' => 983.0001220703125,
3529 
            'MDL_Handle' => 3.0009765625,
3530 
            'MDL_handle' => 3.0009765625,
3531 
            'arith_type' => 1,
3532 
            'bin_pt' => 14,
3533 
            'block_config' => 'sysgen_blockset:toreg_config',
3534 
            'block_handle' => 983.0001220703125,
3535 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register10',
3536 
            'block_type' => 'toreg',
3537 
            'dbl_ovrd' => 0,
3538 
            'explicit_data_type' => 0,
3539 
            'init' => 0.0,
3540 
            'init_bit_vector' => '0b',
3541 
            'mdl_handle' => 3.0009765625,
3542 
            'model_handle' => 3.0009765625,
3543 
            'n_bits' => 16,
3544 
            'ownership' => 1,
3545 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
3546 
            'shared_memory_name' => 'register05rv',
3547 
          },
3548 
          'needs_vhdl_wrapper' => 0,
3549 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register10',
3550 
        },
3551 
        'entityName' => 'x_x35',
3552 
        'ports' => {
3553 
          'ce' => {
3554 
            'attributes' => {
3555 
              'domain' => '',
3556 
              'group' => 1,
3557 
              'isCe' => 1,
3558 
              'is_floating_block' => 1,
3559 
              'period' => 1.0,
3560 
              'type' => 'logic',
3561 
            },
3562 
            'direction' => 'in',
3563 
            'hdlType' => 'std_logic',
3564 
            'width' => 1,
3565 
          },
3566 
          'clk' => {
3567 
            'attributes' => {
3568 
              'domain' => '',
3569 
              'group' => 1,
3570 
              'isClk' => 1,
3571 
              'is_floating_block' => 1,
3572 
              'period' => 1.0,
3573 
              'type' => 'logic',
3574 
            },
3575 
            'direction' => 'in',
3576 
            'hdlType' => 'std_logic',
3577 
            'width' => 1,
3578 
          },
3579 
          'clr' => {
3580 
            'attributes' => {
3581 
              'domain' => '',
3582 
              'group' => 1,
3583 
              'isClr' => 1,
3584 
              'is_floating_block' => 1,
3585 
              'period' => 1,
3586 
              'type' => 'logic',
3587 
              'valid_bit_used' => 0,
3588 
            },
3589 
            'direction' => 'in',
3590 
            'hdlType' => 'std_logic',
3591 
            'width' => 1,
3592 
          },
3593 
          'data_in' => {
3594 
            'attributes' => {
3595 
              'bin_pt' => 0,
3596 
              'is_floating_block' => 1,
3597 
              'must_be_hdl_vector' => 1,
3598 
              'period' => 1.0,
3599 
              'port_id' => '0',
3600 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register10/data_in',
3601 
              'type' => 'Bool',
3602 
            },
3603 
            'direction' => 'in',
3604 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3605 
            'width' => 1,
3606 
          },
3607 
          'dout' => {
3608 
            'attributes' => {
3609 
              'bin_pt' => 0,
3610 
              'is_floating_block' => 1,
3611 
              'must_be_hdl_vector' => 1,
3612 
              'period' => 1.0,
3613 
              'port_id' => '0',
3614 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register10/dout',
3615 
              'type' => 'Bool',
3616 
            },
3617 
            'direction' => 'out',
3618 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3619 
            'width' => 1,
3620 
          },
3621 
          'en' => {
3622 
            'attributes' => {
3623 
              'bin_pt' => 0,
3624 
              'is_floating_block' => 1,
3625 
              'must_be_hdl_vector' => 1,
3626 
              'period' => 1.0,
3627 
              'port_id' => '1',
3628 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register10/en',
3629 
              'type' => 'Bool',
3630 
            },
3631 
            'direction' => 'in',
3632 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3633 
            'width' => 1,
3634 
          },
3635 
        },
3636 
      },
3637 
      'entityName' => 'x_x35',
3638 
    },
3639 
    'to_register11' => {
3640 
      'connections' => {
3641 
        'ce' => 'ce_1_sg_x0',
3642 
        'clk' => 'clk_1_sg_x0',
3643 
        'clr' => [
3644 
          'constant',
3645 
          '\'0\'',
3646 
        ],
3647 
        'data_in' => 'data_in_x2_net',
3648 
        'dout' => 'to_register11_dout_net',
3649 
        'en' => 'constant6_op_net_x3',
3650 
      },
3651 
      'entity' => {
3652 
        'attributes' => {
3653 
          'generics' => [],
3654 
          'is_floating_block' => 1,
3655 
          'mask' => {
3656 
            'Block_Handle' => 984.0001220703125,
3657 
            'Block_handle' => 984.0001220703125,
3658 
            'MDL_Handle' => 3.0009765625,
3659 
            'MDL_handle' => 3.0009765625,
3660 
            'arith_type' => 1,
3661 
            'bin_pt' => 14,
3662 
            'block_config' => 'sysgen_blockset:toreg_config',
3663 
            'block_handle' => 984.0001220703125,
3664 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register11',
3665 
            'block_type' => 'toreg',
3666 
            'dbl_ovrd' => 0,
3667 
            'explicit_data_type' => 0,
3668 
            'init' => 0.0,
3669 
            'init_bit_vector' => '0b',
3670 
            'mdl_handle' => 3.0009765625,
3671 
            'model_handle' => 3.0009765625,
3672 
            'n_bits' => 16,
3673 
            'ownership' => 1,
3674 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
3675 
            'shared_memory_name' => 'register06rv',
3676 
          },
3677 
          'needs_vhdl_wrapper' => 0,
3678 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register11',
3679 
        },
3680 
        'entityName' => 'x_x36',
3681 
        'ports' => {
3682 
          'ce' => {
3683 
            'attributes' => {
3684 
              'domain' => '',
3685 
              'group' => 1,
3686 
              'isCe' => 1,
3687 
              'is_floating_block' => 1,
3688 
              'period' => 1.0,
3689 
              'type' => 'logic',
3690 
            },
3691 
            'direction' => 'in',
3692 
            'hdlType' => 'std_logic',
3693 
            'width' => 1,
3694 
          },
3695 
          'clk' => {
3696 
            'attributes' => {
3697 
              'domain' => '',
3698 
              'group' => 1,
3699 
              'isClk' => 1,
3700 
              'is_floating_block' => 1,
3701 
              'period' => 1.0,
3702 
              'type' => 'logic',
3703 
            },
3704 
            'direction' => 'in',
3705 
            'hdlType' => 'std_logic',
3706 
            'width' => 1,
3707 
          },
3708 
          'clr' => {
3709 
            'attributes' => {
3710 
              'domain' => '',
3711 
              'group' => 1,
3712 
              'isClr' => 1,
3713 
              'is_floating_block' => 1,
3714 
              'period' => 1,
3715 
              'type' => 'logic',
3716 
              'valid_bit_used' => 0,
3717 
            },
3718 
            'direction' => 'in',
3719 
            'hdlType' => 'std_logic',
3720 
            'width' => 1,
3721 
          },
3722 
          'data_in' => {
3723 
            'attributes' => {
3724 
              'bin_pt' => 0,
3725 
              'is_floating_block' => 1,
3726 
              'must_be_hdl_vector' => 1,
3727 
              'period' => 1.0,
3728 
              'port_id' => '0',
3729 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register11/data_in',
3730 
              'type' => 'Bool',
3731 
            },
3732 
            'direction' => 'in',
3733 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3734 
            'width' => 1,
3735 
          },
3736 
          'dout' => {
3737 
            'attributes' => {
3738 
              'bin_pt' => 0,
3739 
              'is_floating_block' => 1,
3740 
              'must_be_hdl_vector' => 1,
3741 
              'period' => 1.0,
3742 
              'port_id' => '0',
3743 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register11/dout',
3744 
              'type' => 'Bool',
3745 
            },
3746 
            'direction' => 'out',
3747 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3748 
            'width' => 1,
3749 
          },
3750 
          'en' => {
3751 
            'attributes' => {
3752 
              'bin_pt' => 0,
3753 
              'is_floating_block' => 1,
3754 
              'must_be_hdl_vector' => 1,
3755 
              'period' => 1.0,
3756 
              'port_id' => '1',
3757 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register11/en',
3758 
              'type' => 'Bool',
3759 
            },
3760 
            'direction' => 'in',
3761 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3762 
            'width' => 1,
3763 
          },
3764 
        },
3765 
      },
3766 
      'entityName' => 'x_x36',
3767 
    },
3768 
    'to_register12' => {
3769 
      'connections' => {
3770 
        'ce' => 'ce_1_sg_x0',
3771 
        'clk' => 'clk_1_sg_x0',
3772 
        'clr' => [
3773 
          'constant',
3774 
          '\'0\'',
3775 
        ],
3776 
        'data_in' => 'data_in_x3_net',
3777 
        'dout' => 'to_register12_dout_net',
3778 
        'en' => 'constant6_op_net_x4',
3779 
      },
3780 
      'entity' => {
3781 
        'attributes' => {
3782 
          'generics' => [],
3783 
          'is_floating_block' => 1,
3784 
          'mask' => {
3785 
            'Block_Handle' => 985.0001220703125,
3786 
            'Block_handle' => 985.0001220703125,
3787 
            'MDL_Handle' => 3.0009765625,
3788 
            'MDL_handle' => 3.0009765625,
3789 
            'arith_type' => 1,
3790 
            'bin_pt' => 14,
3791 
            'block_config' => 'sysgen_blockset:toreg_config',
3792 
            'block_handle' => 985.0001220703125,
3793 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register12',
3794 
            'block_type' => 'toreg',
3795 
            'dbl_ovrd' => 0,
3796 
            'explicit_data_type' => 0,
3797 
            'init' => 0.0,
3798 
            'init_bit_vector' => '0b',
3799 
            'mdl_handle' => 3.0009765625,
3800 
            'model_handle' => 3.0009765625,
3801 
            'n_bits' => 16,
3802 
            'ownership' => 1,
3803 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
3804 
            'shared_memory_name' => 'register07rv',
3805 
          },
3806 
          'needs_vhdl_wrapper' => 0,
3807 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register12',
3808 
        },
3809 
        'entityName' => 'x_x37',
3810 
        'ports' => {
3811 
          'ce' => {
3812 
            'attributes' => {
3813 
              'domain' => '',
3814 
              'group' => 1,
3815 
              'isCe' => 1,
3816 
              'is_floating_block' => 1,
3817 
              'period' => 1.0,
3818 
              'type' => 'logic',
3819 
            },
3820 
            'direction' => 'in',
3821 
            'hdlType' => 'std_logic',
3822 
            'width' => 1,
3823 
          },
3824 
          'clk' => {
3825 
            'attributes' => {
3826 
              'domain' => '',
3827 
              'group' => 1,
3828 
              'isClk' => 1,
3829 
              'is_floating_block' => 1,
3830 
              'period' => 1.0,
3831 
              'type' => 'logic',
3832 
            },
3833 
            'direction' => 'in',
3834 
            'hdlType' => 'std_logic',
3835 
            'width' => 1,
3836 
          },
3837 
          'clr' => {
3838 
            'attributes' => {
3839 
              'domain' => '',
3840 
              'group' => 1,
3841 
              'isClr' => 1,
3842 
              'is_floating_block' => 1,
3843 
              'period' => 1,
3844 
              'type' => 'logic',
3845 
              'valid_bit_used' => 0,
3846 
            },
3847 
            'direction' => 'in',
3848 
            'hdlType' => 'std_logic',
3849 
            'width' => 1,
3850 
          },
3851 
          'data_in' => {
3852 
            'attributes' => {
3853 
              'bin_pt' => 0,
3854 
              'is_floating_block' => 1,
3855 
              'must_be_hdl_vector' => 1,
3856 
              'period' => 1.0,
3857 
              'port_id' => '0',
3858 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register12/data_in',
3859 
              'type' => 'Bool',
3860 
            },
3861 
            'direction' => 'in',
3862 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3863 
            'width' => 1,
3864 
          },
3865 
          'dout' => {
3866 
            'attributes' => {
3867 
              'bin_pt' => 0,
3868 
              'is_floating_block' => 1,
3869 
              'must_be_hdl_vector' => 1,
3870 
              'period' => 1.0,
3871 
              'port_id' => '0',
3872 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register12/dout',
3873 
              'type' => 'Bool',
3874 
            },
3875 
            'direction' => 'out',
3876 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3877 
            'width' => 1,
3878 
          },
3879 
          'en' => {
3880 
            'attributes' => {
3881 
              'bin_pt' => 0,
3882 
              'is_floating_block' => 1,
3883 
              'must_be_hdl_vector' => 1,
3884 
              'period' => 1.0,
3885 
              'port_id' => '1',
3886 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register12/en',
3887 
              'type' => 'Bool',
3888 
            },
3889 
            'direction' => 'in',
3890 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3891 
            'width' => 1,
3892 
          },
3893 
        },
3894 
      },
3895 
      'entityName' => 'x_x37',
3896 
    },
3897 
    'to_register13' => {
3898 
      'connections' => {
3899 
        'ce' => 'ce_1_sg_x0',
3900 
        'clk' => 'clk_1_sg_x0',
3901 
        'clr' => [
3902 
          'constant',
3903 
          '\'0\'',
3904 
        ],
3905 
        'data_in' => 'data_in_x4_net',
3906 
        'dout' => 'to_register13_dout_net',
3907 
        'en' => 'constant6_op_net_x5',
3908 
      },
3909 
      'entity' => {
3910 
        'attributes' => {
3911 
          'generics' => [],
3912 
          'is_floating_block' => 1,
3913 
          'mask' => {
3914 
            'Block_Handle' => 986.0001220703125,
3915 
            'Block_handle' => 986.0001220703125,
3916 
            'MDL_Handle' => 3.0009765625,
3917 
            'MDL_handle' => 3.0009765625,
3918 
            'arith_type' => 1,
3919 
            'bin_pt' => 14,
3920 
            'block_config' => 'sysgen_blockset:toreg_config',
3921 
            'block_handle' => 986.0001220703125,
3922 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register13',
3923 
            'block_type' => 'toreg',
3924 
            'dbl_ovrd' => 0,
3925 
            'explicit_data_type' => 0,
3926 
            'init' => 0.0,
3927 
            'init_bit_vector' => '00000000000000000000000000000000b',
3928 
            'mdl_handle' => 3.0009765625,
3929 
            'model_handle' => 3.0009765625,
3930 
            'n_bits' => 16,
3931 
            'ownership' => 1,
3932 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
3933 
            'shared_memory_name' => 'register07rd',
3934 
          },
3935 
          'needs_vhdl_wrapper' => 0,
3936 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register13',
3937 
        },
3938 
        'entityName' => 'x_x38',
3939 
        'ports' => {
3940 
          'ce' => {
3941 
            'attributes' => {
3942 
              'domain' => '',
3943 
              'group' => 1,
3944 
              'isCe' => 1,
3945 
              'is_floating_block' => 1,
3946 
              'period' => 1.0,
3947 
              'type' => 'logic',
3948 
            },
3949 
            'direction' => 'in',
3950 
            'hdlType' => 'std_logic',
3951 
            'width' => 1,
3952 
          },
3953 
          'clk' => {
3954 
            'attributes' => {
3955 
              'domain' => '',
3956 
              'group' => 1,
3957 
              'isClk' => 1,
3958 
              'is_floating_block' => 1,
3959 
              'period' => 1.0,
3960 
              'type' => 'logic',
3961 
            },
3962 
            'direction' => 'in',
3963 
            'hdlType' => 'std_logic',
3964 
            'width' => 1,
3965 
          },
3966 
          'clr' => {
3967 
            'attributes' => {
3968 
              'domain' => '',
3969 
              'group' => 1,
3970 
              'isClr' => 1,
3971 
              'is_floating_block' => 1,
3972 
              'period' => 1,
3973 
              'type' => 'logic',
3974 
              'valid_bit_used' => 0,
3975 
            },
3976 
            'direction' => 'in',
3977 
            'hdlType' => 'std_logic',
3978 
            'width' => 1,
3979 
          },
3980 
          'data_in' => {
3981 
            'attributes' => {
3982 
              'bin_pt' => 0,
3983 
              'is_floating_block' => 1,
3984 
              'must_be_hdl_vector' => 1,
3985 
              'period' => 1.0,
3986 
              'port_id' => '0',
3987 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register13/data_in',
3988 
              'type' => 'UFix_32_0',
3989 
            },
3990 
            'direction' => 'in',
3991 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3992 
            'width' => 32,
3993 
          },
3994 
          'dout' => {
3995 
            'attributes' => {
3996 
              'bin_pt' => 0,
3997 
              'is_floating_block' => 1,
3998 
              'must_be_hdl_vector' => 1,
3999 
              'period' => 1.0,
4000 
              'port_id' => '0',
4001 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register13/dout',
4002 
              'type' => 'UFix_32_0',
4003 
            },
4004 
            'direction' => 'out',
4005 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4006 
            'width' => 32,
4007 
          },
4008 
          'en' => {
4009 
            'attributes' => {
4010 
              'bin_pt' => 0,
4011 
              'is_floating_block' => 1,
4012 
              'must_be_hdl_vector' => 1,
4013 
              'period' => 1.0,
4014 
              'port_id' => '1',
4015 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register13/en',
4016 
              'type' => 'Bool',
4017 
            },
4018 
            'direction' => 'in',
4019 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4020 
            'width' => 1,
4021 
          },
4022 
        },
4023 
      },
4024 
      'entityName' => 'x_x38',
4025 
    },
4026 
    'to_register14' => {
4027 
      'connections' => {
4028 
        'ce' => 'ce_1_sg_x0',
4029 
        'clk' => 'clk_1_sg_x0',
4030 
        'clr' => [
4031 
          'constant',
4032 
          '\'0\'',
4033 
        ],
4034 
        'data_in' => 'data_in_x5_net',
4035 
        'dout' => 'to_register14_dout_net',
4036 
        'en' => 'constant6_op_net_x6',
4037 
      },
4038 
      'entity' => {
4039 
        'attributes' => {
4040 
          'generics' => [],
4041 
          'is_floating_block' => 1,
4042 
          'mask' => {
4043 
            'Block_Handle' => 987.0001220703125,
4044 
            'Block_handle' => 987.0001220703125,
4045 
            'MDL_Handle' => 3.0009765625,
4046 
            'MDL_handle' => 3.0009765625,
4047 
            'arith_type' => 1,
4048 
            'bin_pt' => 14,
4049 
            'block_config' => 'sysgen_blockset:toreg_config',
4050 
            'block_handle' => 987.0001220703125,
4051 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register14',
4052 
            'block_type' => 'toreg',
4053 
            'dbl_ovrd' => 0,
4054 
            'explicit_data_type' => 0,
4055 
            'init' => 0.0,
4056 
            'init_bit_vector' => '0b',
4057 
            'mdl_handle' => 3.0009765625,
4058 
            'model_handle' => 3.0009765625,
4059 
            'n_bits' => 16,
4060 
            'ownership' => 1,
4061 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4062 
            'shared_memory_name' => 'register08rv',
4063 
          },
4064 
          'needs_vhdl_wrapper' => 0,
4065 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register14',
4066 
        },
4067 
        'entityName' => 'x_x39',
4068 
        'ports' => {
4069 
          'ce' => {
4070 
            'attributes' => {
4071 
              'domain' => '',
4072 
              'group' => 1,
4073 
              'isCe' => 1,
4074 
              'is_floating_block' => 1,
4075 
              'period' => 1.0,
4076 
              'type' => 'logic',
4077 
            },
4078 
            'direction' => 'in',
4079 
            'hdlType' => 'std_logic',
4080 
            'width' => 1,
4081 
          },
4082 
          'clk' => {
4083 
            'attributes' => {
4084 
              'domain' => '',
4085 
              'group' => 1,
4086 
              'isClk' => 1,
4087 
              'is_floating_block' => 1,
4088 
              'period' => 1.0,
4089 
              'type' => 'logic',
4090 
            },
4091 
            'direction' => 'in',
4092 
            'hdlType' => 'std_logic',
4093 
            'width' => 1,
4094 
          },
4095 
          'clr' => {
4096 
            'attributes' => {
4097 
              'domain' => '',
4098 
              'group' => 1,
4099 
              'isClr' => 1,
4100 
              'is_floating_block' => 1,
4101 
              'period' => 1,
4102 
              'type' => 'logic',
4103 
              'valid_bit_used' => 0,
4104 
            },
4105 
            'direction' => 'in',
4106 
            'hdlType' => 'std_logic',
4107 
            'width' => 1,
4108 
          },
4109 
          'data_in' => {
4110 
            'attributes' => {
4111 
              'bin_pt' => 0,
4112 
              'is_floating_block' => 1,
4113 
              'must_be_hdl_vector' => 1,
4114 
              'period' => 1.0,
4115 
              'port_id' => '0',
4116 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register14/data_in',
4117 
              'type' => 'Bool',
4118 
            },
4119 
            'direction' => 'in',
4120 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4121 
            'width' => 1,
4122 
          },
4123 
          'dout' => {
4124 
            'attributes' => {
4125 
              'bin_pt' => 0,
4126 
              'is_floating_block' => 1,
4127 
              'must_be_hdl_vector' => 1,
4128 
              'period' => 1.0,
4129 
              'port_id' => '0',
4130 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register14/dout',
4131 
              'type' => 'Bool',
4132 
            },
4133 
            'direction' => 'out',
4134 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4135 
            'width' => 1,
4136 
          },
4137 
          'en' => {
4138 
            'attributes' => {
4139 
              'bin_pt' => 0,
4140 
              'is_floating_block' => 1,
4141 
              'must_be_hdl_vector' => 1,
4142 
              'period' => 1.0,
4143 
              'port_id' => '1',
4144 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register14/en',
4145 
              'type' => 'Bool',
4146 
            },
4147 
            'direction' => 'in',
4148 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4149 
            'width' => 1,
4150 
          },
4151 
        },
4152 
      },
4153 
      'entityName' => 'x_x39',
4154 
    },
4155 
    'to_register15' => {
4156 
      'connections' => {
4157 
        'ce' => 'ce_1_sg_x0',
4158 
        'clk' => 'clk_1_sg_x0',
4159 
        'clr' => [
4160 
          'constant',
4161 
          '\'0\'',
4162 
        ],
4163 
        'data_in' => 'data_in_x6_net',
4164 
        'dout' => 'to_register15_dout_net',
4165 
        'en' => 'constant6_op_net_x7',
4166 
      },
4167 
      'entity' => {
4168 
        'attributes' => {
4169 
          'generics' => [],
4170 
          'is_floating_block' => 1,
4171 
          'mask' => {
4172 
            'Block_Handle' => 988.0001220703125,
4173 
            'Block_handle' => 988.0001220703125,
4174 
            'MDL_Handle' => 3.0009765625,
4175 
            'MDL_handle' => 3.0009765625,
4176 
            'arith_type' => 1,
4177 
            'bin_pt' => 14,
4178 
            'block_config' => 'sysgen_blockset:toreg_config',
4179 
            'block_handle' => 988.0001220703125,
4180 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register15',
4181 
            'block_type' => 'toreg',
4182 
            'dbl_ovrd' => 0,
4183 
            'explicit_data_type' => 0,
4184 
            'init' => 0.0,
4185 
            'init_bit_vector' => '00000000000000000000000000000000b',
4186 
            'mdl_handle' => 3.0009765625,
4187 
            'model_handle' => 3.0009765625,
4188 
            'n_bits' => 16,
4189 
            'ownership' => 1,
4190 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4191 
            'shared_memory_name' => 'register08rd',
4192 
          },
4193 
          'needs_vhdl_wrapper' => 0,
4194 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register15',
4195 
        },
4196 
        'entityName' => 'x_x40',
4197 
        'ports' => {
4198 
          'ce' => {
4199 
            'attributes' => {
4200 
              'domain' => '',
4201 
              'group' => 1,
4202 
              'isCe' => 1,
4203 
              'is_floating_block' => 1,
4204 
              'period' => 1.0,
4205 
              'type' => 'logic',
4206 
            },
4207 
            'direction' => 'in',
4208 
            'hdlType' => 'std_logic',
4209 
            'width' => 1,
4210 
          },
4211 
          'clk' => {
4212 
            'attributes' => {
4213 
              'domain' => '',
4214 
              'group' => 1,
4215 
              'isClk' => 1,
4216 
              'is_floating_block' => 1,
4217 
              'period' => 1.0,
4218 
              'type' => 'logic',
4219 
            },
4220 
            'direction' => 'in',
4221 
            'hdlType' => 'std_logic',
4222 
            'width' => 1,
4223 
          },
4224 
          'clr' => {
4225 
            'attributes' => {
4226 
              'domain' => '',
4227 
              'group' => 1,
4228 
              'isClr' => 1,
4229 
              'is_floating_block' => 1,
4230 
              'period' => 1,
4231 
              'type' => 'logic',
4232 
              'valid_bit_used' => 0,
4233 
            },
4234 
            'direction' => 'in',
4235 
            'hdlType' => 'std_logic',
4236 
            'width' => 1,
4237 
          },
4238 
          'data_in' => {
4239 
            'attributes' => {
4240 
              'bin_pt' => 0,
4241 
              'is_floating_block' => 1,
4242 
              'must_be_hdl_vector' => 1,
4243 
              'period' => 1.0,
4244 
              'port_id' => '0',
4245 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register15/data_in',
4246 
              'type' => 'UFix_32_0',
4247 
            },
4248 
            'direction' => 'in',
4249 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4250 
            'width' => 32,
4251 
          },
4252 
          'dout' => {
4253 
            'attributes' => {
4254 
              'bin_pt' => 0,
4255 
              'is_floating_block' => 1,
4256 
              'must_be_hdl_vector' => 1,
4257 
              'period' => 1.0,
4258 
              'port_id' => '0',
4259 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register15/dout',
4260 
              'type' => 'UFix_32_0',
4261 
            },
4262 
            'direction' => 'out',
4263 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4264 
            'width' => 32,
4265 
          },
4266 
          'en' => {
4267 
            'attributes' => {
4268 
              'bin_pt' => 0,
4269 
              'is_floating_block' => 1,
4270 
              'must_be_hdl_vector' => 1,
4271 
              'period' => 1.0,
4272 
              'port_id' => '1',
4273 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register15/en',
4274 
              'type' => 'Bool',
4275 
            },
4276 
            'direction' => 'in',
4277 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4278 
            'width' => 1,
4279 
          },
4280 
        },
4281 
      },
4282 
      'entityName' => 'x_x40',
4283 
    },
4284 
    'to_register16' => {
4285 
      'connections' => {
4286 
        'ce' => 'ce_1_sg_x0',
4287 
        'clk' => 'clk_1_sg_x0',
4288 
        'clr' => [
4289 
          'constant',
4290 
          '\'0\'',
4291 
        ],
4292 
        'data_in' => 'data_in_x7_net',
4293 
        'dout' => 'to_register16_dout_net',
4294 
        'en' => 'constant6_op_net_x8',
4295 
      },
4296 
      'entity' => {
4297 
        'attributes' => {
4298 
          'generics' => [],
4299 
          'is_floating_block' => 1,
4300 
          'mask' => {
4301 
            'Block_Handle' => 989.0001220703125,
4302 
            'Block_handle' => 989.0001220703125,
4303 
            'MDL_Handle' => 3.0009765625,
4304 
            'MDL_handle' => 3.0009765625,
4305 
            'arith_type' => 1,
4306 
            'bin_pt' => 14,
4307 
            'block_config' => 'sysgen_blockset:toreg_config',
4308 
            'block_handle' => 989.0001220703125,
4309 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register16',
4310 
            'block_type' => 'toreg',
4311 
            'dbl_ovrd' => 0,
4312 
            'explicit_data_type' => 0,
4313 
            'init' => 0.0,
4314 
            'init_bit_vector' => '0b',
4315 
            'mdl_handle' => 3.0009765625,
4316 
            'model_handle' => 3.0009765625,
4317 
            'n_bits' => 16,
4318 
            'ownership' => 1,
4319 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4320 
            'shared_memory_name' => 'register09rv',
4321 
          },
4322 
          'needs_vhdl_wrapper' => 0,
4323 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register16',
4324 
        },
4325 
        'entityName' => 'x_x41',
4326 
        'ports' => {
4327 
          'ce' => {
4328 
            'attributes' => {
4329 
              'domain' => '',
4330 
              'group' => 1,
4331 
              'isCe' => 1,
4332 
              'is_floating_block' => 1,
4333 
              'period' => 1.0,
4334 
              'type' => 'logic',
4335 
            },
4336 
            'direction' => 'in',
4337 
            'hdlType' => 'std_logic',
4338 
            'width' => 1,
4339 
          },
4340 
          'clk' => {
4341 
            'attributes' => {
4342 
              'domain' => '',
4343 
              'group' => 1,
4344 
              'isClk' => 1,
4345 
              'is_floating_block' => 1,
4346 
              'period' => 1.0,
4347 
              'type' => 'logic',
4348 
            },
4349 
            'direction' => 'in',
4350 
            'hdlType' => 'std_logic',
4351 
            'width' => 1,
4352 
          },
4353 
          'clr' => {
4354 
            'attributes' => {
4355 
              'domain' => '',
4356 
              'group' => 1,
4357 
              'isClr' => 1,
4358 
              'is_floating_block' => 1,
4359 
              'period' => 1,
4360 
              'type' => 'logic',
4361 
              'valid_bit_used' => 0,
4362 
            },
4363 
            'direction' => 'in',
4364 
            'hdlType' => 'std_logic',
4365 
            'width' => 1,
4366 
          },
4367 
          'data_in' => {
4368 
            'attributes' => {
4369 
              'bin_pt' => 0,
4370 
              'is_floating_block' => 1,
4371 
              'must_be_hdl_vector' => 1,
4372 
              'period' => 1.0,
4373 
              'port_id' => '0',
4374 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register16/data_in',
4375 
              'type' => 'Bool',
4376 
            },
4377 
            'direction' => 'in',
4378 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4379 
            'width' => 1,
4380 
          },
4381 
          'dout' => {
4382 
            'attributes' => {
4383 
              'bin_pt' => 0,
4384 
              'is_floating_block' => 1,
4385 
              'must_be_hdl_vector' => 1,
4386 
              'period' => 1.0,
4387 
              'port_id' => '0',
4388 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register16/dout',
4389 
              'type' => 'Bool',
4390 
            },
4391 
            'direction' => 'out',
4392 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4393 
            'width' => 1,
4394 
          },
4395 
          'en' => {
4396 
            'attributes' => {
4397 
              'bin_pt' => 0,
4398 
              'is_floating_block' => 1,
4399 
              'must_be_hdl_vector' => 1,
4400 
              'period' => 1.0,
4401 
              'port_id' => '1',
4402 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register16/en',
4403 
              'type' => 'Bool',
4404 
            },
4405 
            'direction' => 'in',
4406 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4407 
            'width' => 1,
4408 
          },
4409 
        },
4410 
      },
4411 
      'entityName' => 'x_x41',
4412 
    },
4413 
    'to_register17' => {
4414 
      'connections' => {
4415 
        'ce' => 'ce_1_sg_x0',
4416 
        'clk' => 'clk_1_sg_x0',
4417 
        'clr' => [
4418 
          'constant',
4419 
          '\'0\'',
4420 
        ],
4421 
        'data_in' => 'data_in_x8_net',
4422 
        'dout' => 'to_register17_dout_net',
4423 
        'en' => 'constant6_op_net_x9',
4424 
      },
4425 
      'entity' => {
4426 
        'attributes' => {
4427 
          'generics' => [],
4428 
          'is_floating_block' => 1,
4429 
          'mask' => {
4430 
            'Block_Handle' => 990.0001220703125,
4431 
            'Block_handle' => 990.0001220703125,
4432 
            'MDL_Handle' => 3.0009765625,
4433 
            'MDL_handle' => 3.0009765625,
4434 
            'arith_type' => 1,
4435 
            'bin_pt' => 14,
4436 
            'block_config' => 'sysgen_blockset:toreg_config',
4437 
            'block_handle' => 990.0001220703125,
4438 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register17',
4439 
            'block_type' => 'toreg',
4440 
            'dbl_ovrd' => 0,
4441 
            'explicit_data_type' => 0,
4442 
            'init' => 0.0,
4443 
            'init_bit_vector' => '00000000000000000000000000000000b',
4444 
            'mdl_handle' => 3.0009765625,
4445 
            'model_handle' => 3.0009765625,
4446 
            'n_bits' => 16,
4447 
            'ownership' => 1,
4448 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4449 
            'shared_memory_name' => 'register09rd',
4450 
          },
4451 
          'needs_vhdl_wrapper' => 0,
4452 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register17',
4453 
        },
4454 
        'entityName' => 'x_x42',
4455 
        'ports' => {
4456 
          'ce' => {
4457 
            'attributes' => {
4458 
              'domain' => '',
4459 
              'group' => 1,
4460 
              'isCe' => 1,
4461 
              'is_floating_block' => 1,
4462 
              'period' => 1.0,
4463 
              'type' => 'logic',
4464 
            },
4465 
            'direction' => 'in',
4466 
            'hdlType' => 'std_logic',
4467 
            'width' => 1,
4468 
          },
4469 
          'clk' => {
4470 
            'attributes' => {
4471 
              'domain' => '',
4472 
              'group' => 1,
4473 
              'isClk' => 1,
4474 
              'is_floating_block' => 1,
4475 
              'period' => 1.0,
4476 
              'type' => 'logic',
4477 
            },
4478 
            'direction' => 'in',
4479 
            'hdlType' => 'std_logic',
4480 
            'width' => 1,
4481 
          },
4482 
          'clr' => {
4483 
            'attributes' => {
4484 
              'domain' => '',
4485 
              'group' => 1,
4486 
              'isClr' => 1,
4487 
              'is_floating_block' => 1,
4488 
              'period' => 1,
4489 
              'type' => 'logic',
4490 
              'valid_bit_used' => 0,
4491 
            },
4492 
            'direction' => 'in',
4493 
            'hdlType' => 'std_logic',
4494 
            'width' => 1,
4495 
          },
4496 
          'data_in' => {
4497 
            'attributes' => {
4498 
              'bin_pt' => 0,
4499 
              'is_floating_block' => 1,
4500 
              'must_be_hdl_vector' => 1,
4501 
              'period' => 1.0,
4502 
              'port_id' => '0',
4503 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register17/data_in',
4504 
              'type' => 'UFix_32_0',
4505 
            },
4506 
            'direction' => 'in',
4507 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4508 
            'width' => 32,
4509 
          },
4510 
          'dout' => {
4511 
            'attributes' => {
4512 
              'bin_pt' => 0,
4513 
              'is_floating_block' => 1,
4514 
              'must_be_hdl_vector' => 1,
4515 
              'period' => 1.0,
4516 
              'port_id' => '0',
4517 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register17/dout',
4518 
              'type' => 'UFix_32_0',
4519 
            },
4520 
            'direction' => 'out',
4521 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4522 
            'width' => 32,
4523 
          },
4524 
          'en' => {
4525 
            'attributes' => {
4526 
              'bin_pt' => 0,
4527 
              'is_floating_block' => 1,
4528 
              'must_be_hdl_vector' => 1,
4529 
              'period' => 1.0,
4530 
              'port_id' => '1',
4531 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register17/en',
4532 
              'type' => 'Bool',
4533 
            },
4534 
            'direction' => 'in',
4535 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4536 
            'width' => 1,
4537 
          },
4538 
        },
4539 
      },
4540 
      'entityName' => 'x_x42',
4541 
    },
4542 
    'to_register18' => {
4543 
      'connections' => {
4544 
        'ce' => 'ce_1_sg_x0',
4545 
        'clk' => 'clk_1_sg_x0',
4546 
        'clr' => [
4547 
          'constant',
4548 
          '\'0\'',
4549 
        ],
4550 
        'data_in' => 'data_in_x9_net',
4551 
        'dout' => 'to_register18_dout_net',
4552 
        'en' => 'constant6_op_net_x10',
4553 
      },
4554 
      'entity' => {
4555 
        'attributes' => {
4556 
          'generics' => [],
4557 
          'is_floating_block' => 1,
4558 
          'mask' => {
4559 
            'Block_Handle' => 991.0001220703125,
4560 
            'Block_handle' => 991.0001220703125,
4561 
            'MDL_Handle' => 3.0009765625,
4562 
            'MDL_handle' => 3.0009765625,
4563 
            'arith_type' => 1,
4564 
            'bin_pt' => 14,
4565 
            'block_config' => 'sysgen_blockset:toreg_config',
4566 
            'block_handle' => 991.0001220703125,
4567 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register18',
4568 
            'block_type' => 'toreg',
4569 
            'dbl_ovrd' => 0,
4570 
            'explicit_data_type' => 0,
4571 
            'init' => 0.0,
4572 
            'init_bit_vector' => '0b',
4573 
            'mdl_handle' => 3.0009765625,
4574 
            'model_handle' => 3.0009765625,
4575 
            'n_bits' => 16,
4576 
            'ownership' => 1,
4577 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4578 
            'shared_memory_name' => 'register10rv',
4579 
          },
4580 
          'needs_vhdl_wrapper' => 0,
4581 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register18',
4582 
        },
4583 
        'entityName' => 'x_x43',
4584 
        'ports' => {
4585 
          'ce' => {
4586 
            'attributes' => {
4587 
              'domain' => '',
4588 
              'group' => 1,
4589 
              'isCe' => 1,
4590 
              'is_floating_block' => 1,
4591 
              'period' => 1.0,
4592 
              'type' => 'logic',
4593 
            },
4594 
            'direction' => 'in',
4595 
            'hdlType' => 'std_logic',
4596 
            'width' => 1,
4597 
          },
4598 
          'clk' => {
4599 
            'attributes' => {
4600 
              'domain' => '',
4601 
              'group' => 1,
4602 
              'isClk' => 1,
4603 
              'is_floating_block' => 1,
4604 
              'period' => 1.0,
4605 
              'type' => 'logic',
4606 
            },
4607 
            'direction' => 'in',
4608 
            'hdlType' => 'std_logic',
4609 
            'width' => 1,
4610 
          },
4611 
          'clr' => {
4612 
            'attributes' => {
4613 
              'domain' => '',
4614 
              'group' => 1,
4615 
              'isClr' => 1,
4616 
              'is_floating_block' => 1,
4617 
              'period' => 1,
4618 
              'type' => 'logic',
4619 
              'valid_bit_used' => 0,
4620 
            },
4621 
            'direction' => 'in',
4622 
            'hdlType' => 'std_logic',
4623 
            'width' => 1,
4624 
          },
4625 
          'data_in' => {
4626 
            'attributes' => {
4627 
              'bin_pt' => 0,
4628 
              'is_floating_block' => 1,
4629 
              'must_be_hdl_vector' => 1,
4630 
              'period' => 1.0,
4631 
              'port_id' => '0',
4632 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register18/data_in',
4633 
              'type' => 'Bool',
4634 
            },
4635 
            'direction' => 'in',
4636 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4637 
            'width' => 1,
4638 
          },
4639 
          'dout' => {
4640 
            'attributes' => {
4641 
              'bin_pt' => 0,
4642 
              'is_floating_block' => 1,
4643 
              'must_be_hdl_vector' => 1,
4644 
              'period' => 1.0,
4645 
              'port_id' => '0',
4646 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register18/dout',
4647 
              'type' => 'Bool',
4648 
            },
4649 
            'direction' => 'out',
4650 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4651 
            'width' => 1,
4652 
          },
4653 
          'en' => {
4654 
            'attributes' => {
4655 
              'bin_pt' => 0,
4656 
              'is_floating_block' => 1,
4657 
              'must_be_hdl_vector' => 1,
4658 
              'period' => 1.0,
4659 
              'port_id' => '1',
4660 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register18/en',
4661 
              'type' => 'Bool',
4662 
            },
4663 
            'direction' => 'in',
4664 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4665 
            'width' => 1,
4666 
          },
4667 
        },
4668 
      },
4669 
      'entityName' => 'x_x43',
4670 
    },
4671 
    'to_register19' => {
4672 
      'connections' => {
4673 
        'ce' => 'ce_1_sg_x0',
4674 
        'clk' => 'clk_1_sg_x0',
4675 
        'clr' => [
4676 
          'constant',
4677 
          '\'0\'',
4678 
        ],
4679 
        'data_in' => 'data_in_x10_net',
4680 
        'dout' => 'to_register19_dout_net',
4681 
        'en' => 'constant6_op_net_x11',
4682 
      },
4683 
      'entity' => {
4684 
        'attributes' => {
4685 
          'generics' => [],
4686 
          'is_floating_block' => 1,
4687 
          'mask' => {
4688 
            'Block_Handle' => 992.0001220703125,
4689 
            'Block_handle' => 992.0001220703125,
4690 
            'MDL_Handle' => 3.0009765625,
4691 
            'MDL_handle' => 3.0009765625,
4692 
            'arith_type' => 1,
4693 
            'bin_pt' => 14,
4694 
            'block_config' => 'sysgen_blockset:toreg_config',
4695 
            'block_handle' => 992.0001220703125,
4696 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register19',
4697 
            'block_type' => 'toreg',
4698 
            'dbl_ovrd' => 0,
4699 
            'explicit_data_type' => 0,
4700 
            'init' => 0.0,
4701 
            'init_bit_vector' => '00000000000000000000000000000000b',
4702 
            'mdl_handle' => 3.0009765625,
4703 
            'model_handle' => 3.0009765625,
4704 
            'n_bits' => 16,
4705 
            'ownership' => 1,
4706 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4707 
            'shared_memory_name' => 'register10rd',
4708 
          },
4709 
          'needs_vhdl_wrapper' => 0,
4710 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register19',
4711 
        },
4712 
        'entityName' => 'x_x44',
4713 
        'ports' => {
4714 
          'ce' => {
4715 
            'attributes' => {
4716 
              'domain' => '',
4717 
              'group' => 1,
4718 
              'isCe' => 1,
4719 
              'is_floating_block' => 1,
4720 
              'period' => 1.0,
4721 
              'type' => 'logic',
4722 
            },
4723 
            'direction' => 'in',
4724 
            'hdlType' => 'std_logic',
4725 
            'width' => 1,
4726 
          },
4727 
          'clk' => {
4728 
            'attributes' => {
4729 
              'domain' => '',
4730 
              'group' => 1,
4731 
              'isClk' => 1,
4732 
              'is_floating_block' => 1,
4733 
              'period' => 1.0,
4734 
              'type' => 'logic',
4735 
            },
4736 
            'direction' => 'in',
4737 
            'hdlType' => 'std_logic',
4738 
            'width' => 1,
4739 
          },
4740 
          'clr' => {
4741 
            'attributes' => {
4742 
              'domain' => '',
4743 
              'group' => 1,
4744 
              'isClr' => 1,
4745 
              'is_floating_block' => 1,
4746 
              'period' => 1,
4747 
              'type' => 'logic',
4748 
              'valid_bit_used' => 0,
4749 
            },
4750 
            'direction' => 'in',
4751 
            'hdlType' => 'std_logic',
4752 
            'width' => 1,
4753 
          },
4754 
          'data_in' => {
4755 
            'attributes' => {
4756 
              'bin_pt' => 0,
4757 
              'is_floating_block' => 1,
4758 
              'must_be_hdl_vector' => 1,
4759 
              'period' => 1.0,
4760 
              'port_id' => '0',
4761 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register19/data_in',
4762 
              'type' => 'UFix_32_0',
4763 
            },
4764 
            'direction' => 'in',
4765 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4766 
            'width' => 32,
4767 
          },
4768 
          'dout' => {
4769 
            'attributes' => {
4770 
              'bin_pt' => 0,
4771 
              'is_floating_block' => 1,
4772 
              'must_be_hdl_vector' => 1,
4773 
              'period' => 1.0,
4774 
              'port_id' => '0',
4775 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register19/dout',
4776 
              'type' => 'UFix_32_0',
4777 
            },
4778 
            'direction' => 'out',
4779 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4780 
            'width' => 32,
4781 
          },
4782 
          'en' => {
4783 
            'attributes' => {
4784 
              'bin_pt' => 0,
4785 
              'is_floating_block' => 1,
4786 
              'must_be_hdl_vector' => 1,
4787 
              'period' => 1.0,
4788 
              'port_id' => '1',
4789 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register19/en',
4790 
              'type' => 'Bool',
4791 
            },
4792 
            'direction' => 'in',
4793 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4794 
            'width' => 1,
4795 
          },
4796 
        },
4797 
      },
4798 
      'entityName' => 'x_x44',
4799 
    },
4800 
    'to_register2' => {
4801 
      'connections' => {
4802 
        'ce' => 'ce_1_sg_x0',
4803 
        'clk' => 'clk_1_sg_x0',
4804 
        'clr' => [
4805 
          'constant',
4806 
          '\'0\'',
4807 
        ],
4808 
        'data_in' => 'data_in_x11_net',
4809 
        'dout' => 'to_register2_dout_net',
4810 
        'en' => 'constant6_op_net_x12',
4811 
      },
4812 
      'entity' => {
4813 
        'attributes' => {
4814 
          'generics' => [],
4815 
          'is_floating_block' => 1,
4816 
          'mask' => {
4817 
            'Block_Handle' => 993.0001220703125,
4818 
            'Block_handle' => 993.0001220703125,
4819 
            'MDL_Handle' => 3.0009765625,
4820 
            'MDL_handle' => 3.0009765625,
4821 
            'arith_type' => 1,
4822 
            'bin_pt' => 14,
4823 
            'block_config' => 'sysgen_blockset:toreg_config',
4824 
            'block_handle' => 993.0001220703125,
4825 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2',
4826 
            'block_type' => 'toreg',
4827 
            'dbl_ovrd' => 0,
4828 
            'explicit_data_type' => 0,
4829 
            'init' => 0.0,
4830 
            'init_bit_vector' => '00000000000000000000000000000000b',
4831 
            'mdl_handle' => 3.0009765625,
4832 
            'model_handle' => 3.0009765625,
4833 
            'n_bits' => 16,
4834 
            'ownership' => 1,
4835 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4836 
            'shared_memory_name' => 'register02rd',
4837 
          },
4838 
          'needs_vhdl_wrapper' => 0,
4839 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2',
4840 
        },
4841 
        'entityName' => 'x_x45',
4842 
        'ports' => {
4843 
          'ce' => {
4844 
            'attributes' => {
4845 
              'domain' => '',
4846 
              'group' => 1,
4847 
              'isCe' => 1,
4848 
              'is_floating_block' => 1,
4849 
              'period' => 1.0,
4850 
              'type' => 'logic',
4851 
            },
4852 
            'direction' => 'in',
4853 
            'hdlType' => 'std_logic',
4854 
            'width' => 1,
4855 
          },
4856 
          'clk' => {
4857 
            'attributes' => {
4858 
              'domain' => '',
4859 
              'group' => 1,
4860 
              'isClk' => 1,
4861 
              'is_floating_block' => 1,
4862 
              'period' => 1.0,
4863 
              'type' => 'logic',
4864 
            },
4865 
            'direction' => 'in',
4866 
            'hdlType' => 'std_logic',
4867 
            'width' => 1,
4868 
          },
4869 
          'clr' => {
4870 
            'attributes' => {
4871 
              'domain' => '',
4872 
              'group' => 1,
4873 
              'isClr' => 1,
4874 
              'is_floating_block' => 1,
4875 
              'period' => 1,
4876 
              'type' => 'logic',
4877 
              'valid_bit_used' => 0,
4878 
            },
4879 
            'direction' => 'in',
4880 
            'hdlType' => 'std_logic',
4881 
            'width' => 1,
4882 
          },
4883 
          'data_in' => {
4884 
            'attributes' => {
4885 
              'bin_pt' => 0,
4886 
              'is_floating_block' => 1,
4887 
              'must_be_hdl_vector' => 1,
4888 
              'period' => 1.0,
4889 
              'port_id' => '0',
4890 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2/data_in',
4891 
              'type' => 'UFix_32_0',
4892 
            },
4893 
            'direction' => 'in',
4894 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4895 
            'width' => 32,
4896 
          },
4897 
          'dout' => {
4898 
            'attributes' => {
4899 
              'bin_pt' => 0,
4900 
              'is_floating_block' => 1,
4901 
              'must_be_hdl_vector' => 1,
4902 
              'period' => 1.0,
4903 
              'port_id' => '0',
4904 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2/dout',
4905 
              'type' => 'UFix_32_0',
4906 
            },
4907 
            'direction' => 'out',
4908 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4909 
            'width' => 32,
4910 
          },
4911 
          'en' => {
4912 
            'attributes' => {
4913 
              'bin_pt' => 0,
4914 
              'is_floating_block' => 1,
4915 
              'must_be_hdl_vector' => 1,
4916 
              'period' => 1.0,
4917 
              'port_id' => '1',
4918 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2/en',
4919 
              'type' => 'Bool',
4920 
            },
4921 
            'direction' => 'in',
4922 
            'hdlType' => 'std_logic_vector(0 downto 0)',
4923 
            'width' => 1,
4924 
          },
4925 
        },
4926 
      },
4927 
      'entityName' => 'x_x45',
4928 
    },
4929 
    'to_register20' => {
4930 
      'connections' => {
4931 
        'ce' => 'ce_1_sg_x0',
4932 
        'clk' => 'clk_1_sg_x0',
4933 
        'clr' => [
4934 
          'constant',
4935 
          '\'0\'',
4936 
        ],
4937 
        'data_in' => 'data_in_x12_net',
4938 
        'dout' => 'to_register20_dout_net',
4939 
        'en' => 'constant6_op_net_x13',
4940 
      },
4941 
      'entity' => {
4942 
        'attributes' => {
4943 
          'generics' => [],
4944 
          'is_floating_block' => 1,
4945 
          'mask' => {
4946 
            'Block_Handle' => 994.0001220703125,
4947 
            'Block_handle' => 994.0001220703125,
4948 
            'MDL_Handle' => 3.0009765625,
4949 
            'MDL_handle' => 3.0009765625,
4950 
            'arith_type' => 1,
4951 
            'bin_pt' => 14,
4952 
            'block_config' => 'sysgen_blockset:toreg_config',
4953 
            'block_handle' => 994.0001220703125,
4954 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register20',
4955 
            'block_type' => 'toreg',
4956 
            'dbl_ovrd' => 0,
4957 
            'explicit_data_type' => 0,
4958 
            'init' => 0.0,
4959 
            'init_bit_vector' => '0b',
4960 
            'mdl_handle' => 3.0009765625,
4961 
            'model_handle' => 3.0009765625,
4962 
            'n_bits' => 16,
4963 
            'ownership' => 1,
4964 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
4965 
            'shared_memory_name' => 'register11rv',
4966 
          },
4967 
          'needs_vhdl_wrapper' => 0,
4968 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register20',
4969 
        },
4970 
        'entityName' => 'x_x46',
4971 
        'ports' => {
4972 
          'ce' => {
4973 
            'attributes' => {
4974 
              'domain' => '',
4975 
              'group' => 1,
4976 
              'isCe' => 1,
4977 
              'is_floating_block' => 1,
4978 
              'period' => 1.0,
4979 
              'type' => 'logic',
4980 
            },
4981 
            'direction' => 'in',
4982 
            'hdlType' => 'std_logic',
4983 
            'width' => 1,
4984 
          },
4985 
          'clk' => {
4986 
            'attributes' => {
4987 
              'domain' => '',
4988 
              'group' => 1,
4989 
              'isClk' => 1,
4990 
              'is_floating_block' => 1,
4991 
              'period' => 1.0,
4992 
              'type' => 'logic',
4993 
            },
4994 
            'direction' => 'in',
4995 
            'hdlType' => 'std_logic',
4996 
            'width' => 1,
4997 
          },
4998 
          'clr' => {
4999 
            'attributes' => {
5000 
              'domain' => '',
5001 
              'group' => 1,
5002 
              'isClr' => 1,
5003 
              'is_floating_block' => 1,
5004 
              'period' => 1,
5005 
              'type' => 'logic',
5006 
              'valid_bit_used' => 0,
5007 
            },
5008 
            'direction' => 'in',
5009 
            'hdlType' => 'std_logic',
5010 
            'width' => 1,
5011 
          },
5012 
          'data_in' => {
5013 
            'attributes' => {
5014 
              'bin_pt' => 0,
5015 
              'is_floating_block' => 1,
5016 
              'must_be_hdl_vector' => 1,
5017 
              'period' => 1.0,
5018 
              'port_id' => '0',
5019 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register20/data_in',
5020 
              'type' => 'Bool',
5021 
            },
5022 
            'direction' => 'in',
5023 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5024 
            'width' => 1,
5025 
          },
5026 
          'dout' => {
5027 
            'attributes' => {
5028 
              'bin_pt' => 0,
5029 
              'is_floating_block' => 1,
5030 
              'must_be_hdl_vector' => 1,
5031 
              'period' => 1.0,
5032 
              'port_id' => '0',
5033 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register20/dout',
5034 
              'type' => 'Bool',
5035 
            },
5036 
            'direction' => 'out',
5037 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5038 
            'width' => 1,
5039 
          },
5040 
          'en' => {
5041 
            'attributes' => {
5042 
              'bin_pt' => 0,
5043 
              'is_floating_block' => 1,
5044 
              'must_be_hdl_vector' => 1,
5045 
              'period' => 1.0,
5046 
              'port_id' => '1',
5047 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register20/en',
5048 
              'type' => 'Bool',
5049 
            },
5050 
            'direction' => 'in',
5051 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5052 
            'width' => 1,
5053 
          },
5054 
        },
5055 
      },
5056 
      'entityName' => 'x_x46',
5057 
    },
5058 
    'to_register21' => {
5059 
      'connections' => {
5060 
        'ce' => 'ce_1_sg_x0',
5061 
        'clk' => 'clk_1_sg_x0',
5062 
        'clr' => [
5063 
          'constant',
5064 
          '\'0\'',
5065 
        ],
5066 
        'data_in' => 'data_in_x13_net',
5067 
        'dout' => 'to_register21_dout_net',
5068 
        'en' => 'constant6_op_net_x14',
5069 
      },
5070 
      'entity' => {
5071 
        'attributes' => {
5072 
          'generics' => [],
5073 
          'is_floating_block' => 1,
5074 
          'mask' => {
5075 
            'Block_Handle' => 995.0001220703125,
5076 
            'Block_handle' => 995.0001220703125,
5077 
            'MDL_Handle' => 3.0009765625,
5078 
            'MDL_handle' => 3.0009765625,
5079 
            'arith_type' => 1,
5080 
            'bin_pt' => 14,
5081 
            'block_config' => 'sysgen_blockset:toreg_config',
5082 
            'block_handle' => 995.0001220703125,
5083 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21',
5084 
            'block_type' => 'toreg',
5085 
            'dbl_ovrd' => 0,
5086 
            'explicit_data_type' => 0,
5087 
            'init' => 0.0,
5088 
            'init_bit_vector' => '00000000000000000000000000000000b',
5089 
            'mdl_handle' => 3.0009765625,
5090 
            'model_handle' => 3.0009765625,
5091 
            'n_bits' => 16,
5092 
            'ownership' => 1,
5093 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5094 
            'shared_memory_name' => 'register11rd',
5095 
          },
5096 
          'needs_vhdl_wrapper' => 0,
5097 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21',
5098 
        },
5099 
        'entityName' => 'x_x47',
5100 
        'ports' => {
5101 
          'ce' => {
5102 
            'attributes' => {
5103 
              'domain' => '',
5104 
              'group' => 1,
5105 
              'isCe' => 1,
5106 
              'is_floating_block' => 1,
5107 
              'period' => 1.0,
5108 
              'type' => 'logic',
5109 
            },
5110 
            'direction' => 'in',
5111 
            'hdlType' => 'std_logic',
5112 
            'width' => 1,
5113 
          },
5114 
          'clk' => {
5115 
            'attributes' => {
5116 
              'domain' => '',
5117 
              'group' => 1,
5118 
              'isClk' => 1,
5119 
              'is_floating_block' => 1,
5120 
              'period' => 1.0,
5121 
              'type' => 'logic',
5122 
            },
5123 
            'direction' => 'in',
5124 
            'hdlType' => 'std_logic',
5125 
            'width' => 1,
5126 
          },
5127 
          'clr' => {
5128 
            'attributes' => {
5129 
              'domain' => '',
5130 
              'group' => 1,
5131 
              'isClr' => 1,
5132 
              'is_floating_block' => 1,
5133 
              'period' => 1,
5134 
              'type' => 'logic',
5135 
              'valid_bit_used' => 0,
5136 
            },
5137 
            'direction' => 'in',
5138 
            'hdlType' => 'std_logic',
5139 
            'width' => 1,
5140 
          },
5141 
          'data_in' => {
5142 
            'attributes' => {
5143 
              'bin_pt' => 0,
5144 
              'is_floating_block' => 1,
5145 
              'must_be_hdl_vector' => 1,
5146 
              'period' => 1.0,
5147 
              'port_id' => '0',
5148 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21/data_in',
5149 
              'type' => 'UFix_32_0',
5150 
            },
5151 
            'direction' => 'in',
5152 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5153 
            'width' => 32,
5154 
          },
5155 
          'dout' => {
5156 
            'attributes' => {
5157 
              'bin_pt' => 0,
5158 
              'is_floating_block' => 1,
5159 
              'must_be_hdl_vector' => 1,
5160 
              'period' => 1.0,
5161 
              'port_id' => '0',
5162 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21/dout',
5163 
              'type' => 'UFix_32_0',
5164 
            },
5165 
            'direction' => 'out',
5166 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5167 
            'width' => 32,
5168 
          },
5169 
          'en' => {
5170 
            'attributes' => {
5171 
              'bin_pt' => 0,
5172 
              'is_floating_block' => 1,
5173 
              'must_be_hdl_vector' => 1,
5174 
              'period' => 1.0,
5175 
              'port_id' => '1',
5176 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21/en',
5177 
              'type' => 'Bool',
5178 
            },
5179 
            'direction' => 'in',
5180 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5181 
            'width' => 1,
5182 
          },
5183 
        },
5184 
      },
5185 
      'entityName' => 'x_x47',
5186 
    },
5187 
    'to_register22' => {
5188 
      'connections' => {
5189 
        'ce' => 'ce_1_sg_x0',
5190 
        'clk' => 'clk_1_sg_x0',
5191 
        'clr' => [
5192 
          'constant',
5193 
          '\'0\'',
5194 
        ],
5195 
        'data_in' => 'data_in_x14_net',
5196 
        'dout' => 'to_register22_dout_net',
5197 
        'en' => 'constant6_op_net_x15',
5198 
      },
5199 
      'entity' => {
5200 
        'attributes' => {
5201 
          'generics' => [],
5202 
          'is_floating_block' => 1,
5203 
          'mask' => {
5204 
            'Block_Handle' => 996.0001220703125,
5205 
            'Block_handle' => 996.0001220703125,
5206 
            'MDL_Handle' => 3.0009765625,
5207 
            'MDL_handle' => 3.0009765625,
5208 
            'arith_type' => 1,
5209 
            'bin_pt' => 14,
5210 
            'block_config' => 'sysgen_blockset:toreg_config',
5211 
            'block_handle' => 996.0001220703125,
5212 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22',
5213 
            'block_type' => 'toreg',
5214 
            'dbl_ovrd' => 0,
5215 
            'explicit_data_type' => 0,
5216 
            'init' => 0.0,
5217 
            'init_bit_vector' => '0b',
5218 
            'mdl_handle' => 3.0009765625,
5219 
            'model_handle' => 3.0009765625,
5220 
            'n_bits' => 16,
5221 
            'ownership' => 1,
5222 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5223 
            'shared_memory_name' => 'register12rv',
5224 
          },
5225 
          'needs_vhdl_wrapper' => 0,
5226 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22',
5227 
        },
5228 
        'entityName' => 'x_x48',
5229 
        'ports' => {
5230 
          'ce' => {
5231 
            'attributes' => {
5232 
              'domain' => '',
5233 
              'group' => 1,
5234 
              'isCe' => 1,
5235 
              'is_floating_block' => 1,
5236 
              'period' => 1.0,
5237 
              'type' => 'logic',
5238 
            },
5239 
            'direction' => 'in',
5240 
            'hdlType' => 'std_logic',
5241 
            'width' => 1,
5242 
          },
5243 
          'clk' => {
5244 
            'attributes' => {
5245 
              'domain' => '',
5246 
              'group' => 1,
5247 
              'isClk' => 1,
5248 
              'is_floating_block' => 1,
5249 
              'period' => 1.0,
5250 
              'type' => 'logic',
5251 
            },
5252 
            'direction' => 'in',
5253 
            'hdlType' => 'std_logic',
5254 
            'width' => 1,
5255 
          },
5256 
          'clr' => {
5257 
            'attributes' => {
5258 
              'domain' => '',
5259 
              'group' => 1,
5260 
              'isClr' => 1,
5261 
              'is_floating_block' => 1,
5262 
              'period' => 1,
5263 
              'type' => 'logic',
5264 
              'valid_bit_used' => 0,
5265 
            },
5266 
            'direction' => 'in',
5267 
            'hdlType' => 'std_logic',
5268 
            'width' => 1,
5269 
          },
5270 
          'data_in' => {
5271 
            'attributes' => {
5272 
              'bin_pt' => 0,
5273 
              'is_floating_block' => 1,
5274 
              'must_be_hdl_vector' => 1,
5275 
              'period' => 1.0,
5276 
              'port_id' => '0',
5277 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22/data_in',
5278 
              'type' => 'Bool',
5279 
            },
5280 
            'direction' => 'in',
5281 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5282 
            'width' => 1,
5283 
          },
5284 
          'dout' => {
5285 
            'attributes' => {
5286 
              'bin_pt' => 0,
5287 
              'is_floating_block' => 1,
5288 
              'must_be_hdl_vector' => 1,
5289 
              'period' => 1.0,
5290 
              'port_id' => '0',
5291 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22/dout',
5292 
              'type' => 'Bool',
5293 
            },
5294 
            'direction' => 'out',
5295 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5296 
            'width' => 1,
5297 
          },
5298 
          'en' => {
5299 
            'attributes' => {
5300 
              'bin_pt' => 0,
5301 
              'is_floating_block' => 1,
5302 
              'must_be_hdl_vector' => 1,
5303 
              'period' => 1.0,
5304 
              'port_id' => '1',
5305 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22/en',
5306 
              'type' => 'Bool',
5307 
            },
5308 
            'direction' => 'in',
5309 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5310 
            'width' => 1,
5311 
          },
5312 
        },
5313 
      },
5314 
      'entityName' => 'x_x48',
5315 
    },
5316 
    'to_register23' => {
5317 
      'connections' => {
5318 
        'ce' => 'ce_1_sg_x0',
5319 
        'clk' => 'clk_1_sg_x0',
5320 
        'clr' => [
5321 
          'constant',
5322 
          '\'0\'',
5323 
        ],
5324 
        'data_in' => 'data_in_x15_net',
5325 
        'dout' => 'to_register23_dout_net',
5326 
        'en' => 'constant6_op_net_x16',
5327 
      },
5328 
      'entity' => {
5329 
        'attributes' => {
5330 
          'generics' => [],
5331 
          'is_floating_block' => 1,
5332 
          'mask' => {
5333 
            'Block_Handle' => 997.0001220703125,
5334 
            'Block_handle' => 997.0001220703125,
5335 
            'MDL_Handle' => 3.0009765625,
5336 
            'MDL_handle' => 3.0009765625,
5337 
            'arith_type' => 1,
5338 
            'bin_pt' => 14,
5339 
            'block_config' => 'sysgen_blockset:toreg_config',
5340 
            'block_handle' => 997.0001220703125,
5341 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register23',
5342 
            'block_type' => 'toreg',
5343 
            'dbl_ovrd' => 0,
5344 
            'explicit_data_type' => 0,
5345 
            'init' => 0.0,
5346 
            'init_bit_vector' => '00000000000000000000000000000000b',
5347 
            'mdl_handle' => 3.0009765625,
5348 
            'model_handle' => 3.0009765625,
5349 
            'n_bits' => 16,
5350 
            'ownership' => 1,
5351 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5352 
            'shared_memory_name' => 'register12rd',
5353 
          },
5354 
          'needs_vhdl_wrapper' => 0,
5355 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register23',
5356 
        },
5357 
        'entityName' => 'x_x49',
5358 
        'ports' => {
5359 
          'ce' => {
5360 
            'attributes' => {
5361 
              'domain' => '',
5362 
              'group' => 1,
5363 
              'isCe' => 1,
5364 
              'is_floating_block' => 1,
5365 
              'period' => 1.0,
5366 
              'type' => 'logic',
5367 
            },
5368 
            'direction' => 'in',
5369 
            'hdlType' => 'std_logic',
5370 
            'width' => 1,
5371 
          },
5372 
          'clk' => {
5373 
            'attributes' => {
5374 
              'domain' => '',
5375 
              'group' => 1,
5376 
              'isClk' => 1,
5377 
              'is_floating_block' => 1,
5378 
              'period' => 1.0,
5379 
              'type' => 'logic',
5380 
            },
5381 
            'direction' => 'in',
5382 
            'hdlType' => 'std_logic',
5383 
            'width' => 1,
5384 
          },
5385 
          'clr' => {
5386 
            'attributes' => {
5387 
              'domain' => '',
5388 
              'group' => 1,
5389 
              'isClr' => 1,
5390 
              'is_floating_block' => 1,
5391 
              'period' => 1,
5392 
              'type' => 'logic',
5393 
              'valid_bit_used' => 0,
5394 
            },
5395 
            'direction' => 'in',
5396 
            'hdlType' => 'std_logic',
5397 
            'width' => 1,
5398 
          },
5399 
          'data_in' => {
5400 
            'attributes' => {
5401 
              'bin_pt' => 0,
5402 
              'is_floating_block' => 1,
5403 
              'must_be_hdl_vector' => 1,
5404 
              'period' => 1.0,
5405 
              'port_id' => '0',
5406 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register23/data_in',
5407 
              'type' => 'UFix_32_0',
5408 
            },
5409 
            'direction' => 'in',
5410 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5411 
            'width' => 32,
5412 
          },
5413 
          'dout' => {
5414 
            'attributes' => {
5415 
              'bin_pt' => 0,
5416 
              'is_floating_block' => 1,
5417 
              'must_be_hdl_vector' => 1,
5418 
              'period' => 1.0,
5419 
              'port_id' => '0',
5420 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register23/dout',
5421 
              'type' => 'UFix_32_0',
5422 
            },
5423 
            'direction' => 'out',
5424 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5425 
            'width' => 32,
5426 
          },
5427 
          'en' => {
5428 
            'attributes' => {
5429 
              'bin_pt' => 0,
5430 
              'is_floating_block' => 1,
5431 
              'must_be_hdl_vector' => 1,
5432 
              'period' => 1.0,
5433 
              'port_id' => '1',
5434 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register23/en',
5435 
              'type' => 'Bool',
5436 
            },
5437 
            'direction' => 'in',
5438 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5439 
            'width' => 1,
5440 
          },
5441 
        },
5442 
      },
5443 
      'entityName' => 'x_x49',
5444 
    },
5445 
    'to_register24' => {
5446 
      'connections' => {
5447 
        'ce' => 'ce_1_sg_x0',
5448 
        'clk' => 'clk_1_sg_x0',
5449 
        'clr' => [
5450 
          'constant',
5451 
          '\'0\'',
5452 
        ],
5453 
        'data_in' => 'data_in_x16_net',
5454 
        'dout' => 'to_register24_dout_net',
5455 
        'en' => 'constant6_op_net_x17',
5456 
      },
5457 
      'entity' => {
5458 
        'attributes' => {
5459 
          'generics' => [],
5460 
          'is_floating_block' => 1,
5461 
          'mask' => {
5462 
            'Block_Handle' => 998.0001220703125,
5463 
            'Block_handle' => 998.0001220703125,
5464 
            'MDL_Handle' => 3.0009765625,
5465 
            'MDL_handle' => 3.0009765625,
5466 
            'arith_type' => 1,
5467 
            'bin_pt' => 14,
5468 
            'block_config' => 'sysgen_blockset:toreg_config',
5469 
            'block_handle' => 998.0001220703125,
5470 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24',
5471 
            'block_type' => 'toreg',
5472 
            'dbl_ovrd' => 0,
5473 
            'explicit_data_type' => 0,
5474 
            'init' => 0.0,
5475 
            'init_bit_vector' => '0b',
5476 
            'mdl_handle' => 3.0009765625,
5477 
            'model_handle' => 3.0009765625,
5478 
            'n_bits' => 16,
5479 
            'ownership' => 1,
5480 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5481 
            'shared_memory_name' => 'register13rv',
5482 
          },
5483 
          'needs_vhdl_wrapper' => 0,
5484 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24',
5485 
        },
5486 
        'entityName' => 'x_x50',
5487 
        'ports' => {
5488 
          'ce' => {
5489 
            'attributes' => {
5490 
              'domain' => '',
5491 
              'group' => 1,
5492 
              'isCe' => 1,
5493 
              'is_floating_block' => 1,
5494 
              'period' => 1.0,
5495 
              'type' => 'logic',
5496 
            },
5497 
            'direction' => 'in',
5498 
            'hdlType' => 'std_logic',
5499 
            'width' => 1,
5500 
          },
5501 
          'clk' => {
5502 
            'attributes' => {
5503 
              'domain' => '',
5504 
              'group' => 1,
5505 
              'isClk' => 1,
5506 
              'is_floating_block' => 1,
5507 
              'period' => 1.0,
5508 
              'type' => 'logic',
5509 
            },
5510 
            'direction' => 'in',
5511 
            'hdlType' => 'std_logic',
5512 
            'width' => 1,
5513 
          },
5514 
          'clr' => {
5515 
            'attributes' => {
5516 
              'domain' => '',
5517 
              'group' => 1,
5518 
              'isClr' => 1,
5519 
              'is_floating_block' => 1,
5520 
              'period' => 1,
5521 
              'type' => 'logic',
5522 
              'valid_bit_used' => 0,
5523 
            },
5524 
            'direction' => 'in',
5525 
            'hdlType' => 'std_logic',
5526 
            'width' => 1,
5527 
          },
5528 
          'data_in' => {
5529 
            'attributes' => {
5530 
              'bin_pt' => 0,
5531 
              'is_floating_block' => 1,
5532 
              'must_be_hdl_vector' => 1,
5533 
              'period' => 1.0,
5534 
              'port_id' => '0',
5535 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24/data_in',
5536 
              'type' => 'Bool',
5537 
            },
5538 
            'direction' => 'in',
5539 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5540 
            'width' => 1,
5541 
          },
5542 
          'dout' => {
5543 
            'attributes' => {
5544 
              'bin_pt' => 0,
5545 
              'is_floating_block' => 1,
5546 
              'must_be_hdl_vector' => 1,
5547 
              'period' => 1.0,
5548 
              'port_id' => '0',
5549 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24/dout',
5550 
              'type' => 'Bool',
5551 
            },
5552 
            'direction' => 'out',
5553 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5554 
            'width' => 1,
5555 
          },
5556 
          'en' => {
5557 
            'attributes' => {
5558 
              'bin_pt' => 0,
5559 
              'is_floating_block' => 1,
5560 
              'must_be_hdl_vector' => 1,
5561 
              'period' => 1.0,
5562 
              'port_id' => '1',
5563 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24/en',
5564 
              'type' => 'Bool',
5565 
            },
5566 
            'direction' => 'in',
5567 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5568 
            'width' => 1,
5569 
          },
5570 
        },
5571 
      },
5572 
      'entityName' => 'x_x50',
5573 
    },
5574 
    'to_register25' => {
5575 
      'connections' => {
5576 
        'ce' => 'ce_1_sg_x0',
5577 
        'clk' => 'clk_1_sg_x0',
5578 
        'clr' => [
5579 
          'constant',
5580 
          '\'0\'',
5581 
        ],
5582 
        'data_in' => 'data_in_x17_net',
5583 
        'dout' => 'to_register25_dout_net',
5584 
        'en' => 'constant6_op_net_x18',
5585 
      },
5586 
      'entity' => {
5587 
        'attributes' => {
5588 
          'generics' => [],
5589 
          'is_floating_block' => 1,
5590 
          'mask' => {
5591 
            'Block_Handle' => 999.0001220703125,
5592 
            'Block_handle' => 999.0001220703125,
5593 
            'MDL_Handle' => 3.0009765625,
5594 
            'MDL_handle' => 3.0009765625,
5595 
            'arith_type' => 1,
5596 
            'bin_pt' => 14,
5597 
            'block_config' => 'sysgen_blockset:toreg_config',
5598 
            'block_handle' => 999.0001220703125,
5599 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25',
5600 
            'block_type' => 'toreg',
5601 
            'dbl_ovrd' => 0,
5602 
            'explicit_data_type' => 0,
5603 
            'init' => 0.0,
5604 
            'init_bit_vector' => '00000000000000000000000000000000b',
5605 
            'mdl_handle' => 3.0009765625,
5606 
            'model_handle' => 3.0009765625,
5607 
            'n_bits' => 16,
5608 
            'ownership' => 1,
5609 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5610 
            'shared_memory_name' => 'register13rd',
5611 
          },
5612 
          'needs_vhdl_wrapper' => 0,
5613 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25',
5614 
        },
5615 
        'entityName' => 'x_x51',
5616 
        'ports' => {
5617 
          'ce' => {
5618 
            'attributes' => {
5619 
              'domain' => '',
5620 
              'group' => 1,
5621 
              'isCe' => 1,
5622 
              'is_floating_block' => 1,
5623 
              'period' => 1.0,
5624 
              'type' => 'logic',
5625 
            },
5626 
            'direction' => 'in',
5627 
            'hdlType' => 'std_logic',
5628 
            'width' => 1,
5629 
          },
5630 
          'clk' => {
5631 
            'attributes' => {
5632 
              'domain' => '',
5633 
              'group' => 1,
5634 
              'isClk' => 1,
5635 
              'is_floating_block' => 1,
5636 
              'period' => 1.0,
5637 
              'type' => 'logic',
5638 
            },
5639 
            'direction' => 'in',
5640 
            'hdlType' => 'std_logic',
5641 
            'width' => 1,
5642 
          },
5643 
          'clr' => {
5644 
            'attributes' => {
5645 
              'domain' => '',
5646 
              'group' => 1,
5647 
              'isClr' => 1,
5648 
              'is_floating_block' => 1,
5649 
              'period' => 1,
5650 
              'type' => 'logic',
5651 
              'valid_bit_used' => 0,
5652 
            },
5653 
            'direction' => 'in',
5654 
            'hdlType' => 'std_logic',
5655 
            'width' => 1,
5656 
          },
5657 
          'data_in' => {
5658 
            'attributes' => {
5659 
              'bin_pt' => 0,
5660 
              'is_floating_block' => 1,
5661 
              'must_be_hdl_vector' => 1,
5662 
              'period' => 1.0,
5663 
              'port_id' => '0',
5664 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25/data_in',
5665 
              'type' => 'UFix_32_0',
5666 
            },
5667 
            'direction' => 'in',
5668 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5669 
            'width' => 32,
5670 
          },
5671 
          'dout' => {
5672 
            'attributes' => {
5673 
              'bin_pt' => 0,
5674 
              'is_floating_block' => 1,
5675 
              'must_be_hdl_vector' => 1,
5676 
              'period' => 1.0,
5677 
              'port_id' => '0',
5678 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25/dout',
5679 
              'type' => 'UFix_32_0',
5680 
            },
5681 
            'direction' => 'out',
5682 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5683 
            'width' => 32,
5684 
          },
5685 
          'en' => {
5686 
            'attributes' => {
5687 
              'bin_pt' => 0,
5688 
              'is_floating_block' => 1,
5689 
              'must_be_hdl_vector' => 1,
5690 
              'period' => 1.0,
5691 
              'port_id' => '1',
5692 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25/en',
5693 
              'type' => 'Bool',
5694 
            },
5695 
            'direction' => 'in',
5696 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5697 
            'width' => 1,
5698 
          },
5699 
        },
5700 
      },
5701 
      'entityName' => 'x_x51',
5702 
    },
5703 
    'to_register26' => {
5704 
      'connections' => {
5705 
        'ce' => 'ce_1_sg_x0',
5706 
        'clk' => 'clk_1_sg_x0',
5707 
        'clr' => [
5708 
          'constant',
5709 
          '\'0\'',
5710 
        ],
5711 
        'data_in' => 'data_in_x18_net',
5712 
        'dout' => 'to_register26_dout_net',
5713 
        'en' => 'constant6_op_net_x19',
5714 
      },
5715 
      'entity' => {
5716 
        'attributes' => {
5717 
          'generics' => [],
5718 
          'is_floating_block' => 1,
5719 
          'mask' => {
5720 
            'Block_Handle' => 1000.0001220703125,
5721 
            'Block_handle' => 1000.0001220703125,
5722 
            'MDL_Handle' => 3.0009765625,
5723 
            'MDL_handle' => 3.0009765625,
5724 
            'arith_type' => 1,
5725 
            'bin_pt' => 14,
5726 
            'block_config' => 'sysgen_blockset:toreg_config',
5727 
            'block_handle' => 1000.0001220703125,
5728 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26',
5729 
            'block_type' => 'toreg',
5730 
            'dbl_ovrd' => 0,
5731 
            'explicit_data_type' => 0,
5732 
            'init' => 0.0,
5733 
            'init_bit_vector' => '0b',
5734 
            'mdl_handle' => 3.0009765625,
5735 
            'model_handle' => 3.0009765625,
5736 
            'n_bits' => 16,
5737 
            'ownership' => 1,
5738 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5739 
            'shared_memory_name' => 'register14rv',
5740 
          },
5741 
          'needs_vhdl_wrapper' => 0,
5742 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26',
5743 
        },
5744 
        'entityName' => 'x_x52',
5745 
        'ports' => {
5746 
          'ce' => {
5747 
            'attributes' => {
5748 
              'domain' => '',
5749 
              'group' => 1,
5750 
              'isCe' => 1,
5751 
              'is_floating_block' => 1,
5752 
              'period' => 1.0,
5753 
              'type' => 'logic',
5754 
            },
5755 
            'direction' => 'in',
5756 
            'hdlType' => 'std_logic',
5757 
            'width' => 1,
5758 
          },
5759 
          'clk' => {
5760 
            'attributes' => {
5761 
              'domain' => '',
5762 
              'group' => 1,
5763 
              'isClk' => 1,
5764 
              'is_floating_block' => 1,
5765 
              'period' => 1.0,
5766 
              'type' => 'logic',
5767 
            },
5768 
            'direction' => 'in',
5769 
            'hdlType' => 'std_logic',
5770 
            'width' => 1,
5771 
          },
5772 
          'clr' => {
5773 
            'attributes' => {
5774 
              'domain' => '',
5775 
              'group' => 1,
5776 
              'isClr' => 1,
5777 
              'is_floating_block' => 1,
5778 
              'period' => 1,
5779 
              'type' => 'logic',
5780 
              'valid_bit_used' => 0,
5781 
            },
5782 
            'direction' => 'in',
5783 
            'hdlType' => 'std_logic',
5784 
            'width' => 1,
5785 
          },
5786 
          'data_in' => {
5787 
            'attributes' => {
5788 
              'bin_pt' => 0,
5789 
              'is_floating_block' => 1,
5790 
              'must_be_hdl_vector' => 1,
5791 
              'period' => 1.0,
5792 
              'port_id' => '0',
5793 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26/data_in',
5794 
              'type' => 'Bool',
5795 
            },
5796 
            'direction' => 'in',
5797 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5798 
            'width' => 1,
5799 
          },
5800 
          'dout' => {
5801 
            'attributes' => {
5802 
              'bin_pt' => 0,
5803 
              'is_floating_block' => 1,
5804 
              'must_be_hdl_vector' => 1,
5805 
              'period' => 1.0,
5806 
              'port_id' => '0',
5807 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26/dout',
5808 
              'type' => 'Bool',
5809 
            },
5810 
            'direction' => 'out',
5811 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5812 
            'width' => 1,
5813 
          },
5814 
          'en' => {
5815 
            'attributes' => {
5816 
              'bin_pt' => 0,
5817 
              'is_floating_block' => 1,
5818 
              'must_be_hdl_vector' => 1,
5819 
              'period' => 1.0,
5820 
              'port_id' => '1',
5821 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26/en',
5822 
              'type' => 'Bool',
5823 
            },
5824 
            'direction' => 'in',
5825 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5826 
            'width' => 1,
5827 
          },
5828 
        },
5829 
      },
5830 
      'entityName' => 'x_x52',
5831 
    },
5832 
    'to_register27' => {
5833 
      'connections' => {
5834 
        'ce' => 'ce_1_sg_x0',
5835 
        'clk' => 'clk_1_sg_x0',
5836 
        'clr' => [
5837 
          'constant',
5838 
          '\'0\'',
5839 
        ],
5840 
        'data_in' => 'data_in_x19_net',
5841 
        'dout' => 'to_register27_dout_net',
5842 
        'en' => 'constant6_op_net_x20',
5843 
      },
5844 
      'entity' => {
5845 
        'attributes' => {
5846 
          'generics' => [],
5847 
          'is_floating_block' => 1,
5848 
          'mask' => {
5849 
            'Block_Handle' => 1001.0001220703125,
5850 
            'Block_handle' => 1001.0001220703125,
5851 
            'MDL_Handle' => 3.0009765625,
5852 
            'MDL_handle' => 3.0009765625,
5853 
            'arith_type' => 1,
5854 
            'bin_pt' => 14,
5855 
            'block_config' => 'sysgen_blockset:toreg_config',
5856 
            'block_handle' => 1001.0001220703125,
5857 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27',
5858 
            'block_type' => 'toreg',
5859 
            'dbl_ovrd' => 0,
5860 
            'explicit_data_type' => 0,
5861 
            'init' => 0.0,
5862 
            'init_bit_vector' => '00000000000000000000000000000000b',
5863 
            'mdl_handle' => 3.0009765625,
5864 
            'model_handle' => 3.0009765625,
5865 
            'n_bits' => 16,
5866 
            'ownership' => 1,
5867 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5868 
            'shared_memory_name' => 'register14rd',
5869 
          },
5870 
          'needs_vhdl_wrapper' => 0,
5871 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27',
5872 
        },
5873 
        'entityName' => 'x_x53',
5874 
        'ports' => {
5875 
          'ce' => {
5876 
            'attributes' => {
5877 
              'domain' => '',
5878 
              'group' => 1,
5879 
              'isCe' => 1,
5880 
              'is_floating_block' => 1,
5881 
              'period' => 1.0,
5882 
              'type' => 'logic',
5883 
            },
5884 
            'direction' => 'in',
5885 
            'hdlType' => 'std_logic',
5886 
            'width' => 1,
5887 
          },
5888 
          'clk' => {
5889 
            'attributes' => {
5890 
              'domain' => '',
5891 
              'group' => 1,
5892 
              'isClk' => 1,
5893 
              'is_floating_block' => 1,
5894 
              'period' => 1.0,
5895 
              'type' => 'logic',
5896 
            },
5897 
            'direction' => 'in',
5898 
            'hdlType' => 'std_logic',
5899 
            'width' => 1,
5900 
          },
5901 
          'clr' => {
5902 
            'attributes' => {
5903 
              'domain' => '',
5904 
              'group' => 1,
5905 
              'isClr' => 1,
5906 
              'is_floating_block' => 1,
5907 
              'period' => 1,
5908 
              'type' => 'logic',
5909 
              'valid_bit_used' => 0,
5910 
            },
5911 
            'direction' => 'in',
5912 
            'hdlType' => 'std_logic',
5913 
            'width' => 1,
5914 
          },
5915 
          'data_in' => {
5916 
            'attributes' => {
5917 
              'bin_pt' => 0,
5918 
              'is_floating_block' => 1,
5919 
              'must_be_hdl_vector' => 1,
5920 
              'period' => 1.0,
5921 
              'port_id' => '0',
5922 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27/data_in',
5923 
              'type' => 'UFix_32_0',
5924 
            },
5925 
            'direction' => 'in',
5926 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5927 
            'width' => 32,
5928 
          },
5929 
          'dout' => {
5930 
            'attributes' => {
5931 
              'bin_pt' => 0,
5932 
              'is_floating_block' => 1,
5933 
              'must_be_hdl_vector' => 1,
5934 
              'period' => 1.0,
5935 
              'port_id' => '0',
5936 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27/dout',
5937 
              'type' => 'UFix_32_0',
5938 
            },
5939 
            'direction' => 'out',
5940 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5941 
            'width' => 32,
5942 
          },
5943 
          'en' => {
5944 
            'attributes' => {
5945 
              'bin_pt' => 0,
5946 
              'is_floating_block' => 1,
5947 
              'must_be_hdl_vector' => 1,
5948 
              'period' => 1.0,
5949 
              'port_id' => '1',
5950 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27/en',
5951 
              'type' => 'Bool',
5952 
            },
5953 
            'direction' => 'in',
5954 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5955 
            'width' => 1,
5956 
          },
5957 
        },
5958 
      },
5959 
      'entityName' => 'x_x53',
5960 
    },
5961 
    'to_register3' => {
5962 
      'connections' => {
5963 
        'ce' => 'ce_1_sg_x0',
5964 
        'clk' => 'clk_1_sg_x0',
5965 
        'clr' => [
5966 
          'constant',
5967 
          '\'0\'',
5968 
        ],
5969 
        'data_in' => 'data_in_x20_net',
5970 
        'dout' => 'to_register3_dout_net',
5971 
        'en' => 'constant6_op_net_x21',
5972 
      },
5973 
      'entity' => {
5974 
        'attributes' => {
5975 
          'generics' => [],
5976 
          'is_floating_block' => 1,
5977 
          'mask' => {
5978 
            'Block_Handle' => 1002.0001220703125,
5979 
            'Block_handle' => 1002.0001220703125,
5980 
            'MDL_Handle' => 3.0009765625,
5981 
            'MDL_handle' => 3.0009765625,
5982 
            'arith_type' => 1,
5983 
            'bin_pt' => 14,
5984 
            'block_config' => 'sysgen_blockset:toreg_config',
5985 
            'block_handle' => 1002.0001220703125,
5986 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3',
5987 
            'block_type' => 'toreg',
5988 
            'dbl_ovrd' => 0,
5989 
            'explicit_data_type' => 0,
5990 
            'init' => 0.0,
5991 
            'init_bit_vector' => '00000000000000000000000000000000b',
5992 
            'mdl_handle' => 3.0009765625,
5993 
            'model_handle' => 3.0009765625,
5994 
            'n_bits' => 16,
5995 
            'ownership' => 1,
5996 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
5997 
            'shared_memory_name' => 'register03rd',
5998 
          },
5999 
          'needs_vhdl_wrapper' => 0,
6000 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3',
6001 
        },
6002 
        'entityName' => 'x_x54',
6003 
        'ports' => {
6004 
          'ce' => {
6005 
            'attributes' => {
6006 
              'domain' => '',
6007 
              'group' => 1,
6008 
              'isCe' => 1,
6009 
              'is_floating_block' => 1,
6010 
              'period' => 1.0,
6011 
              'type' => 'logic',
6012 
            },
6013 
            'direction' => 'in',
6014 
            'hdlType' => 'std_logic',
6015 
            'width' => 1,
6016 
          },
6017 
          'clk' => {
6018 
            'attributes' => {
6019 
              'domain' => '',
6020 
              'group' => 1,
6021 
              'isClk' => 1,
6022 
              'is_floating_block' => 1,
6023 
              'period' => 1.0,
6024 
              'type' => 'logic',
6025 
            },
6026 
            'direction' => 'in',
6027 
            'hdlType' => 'std_logic',
6028 
            'width' => 1,
6029 
          },
6030 
          'clr' => {
6031 
            'attributes' => {
6032 
              'domain' => '',
6033 
              'group' => 1,
6034 
              'isClr' => 1,
6035 
              'is_floating_block' => 1,
6036 
              'period' => 1,
6037 
              'type' => 'logic',
6038 
              'valid_bit_used' => 0,
6039 
            },
6040 
            'direction' => 'in',
6041 
            'hdlType' => 'std_logic',
6042 
            'width' => 1,
6043 
          },
6044 
          'data_in' => {
6045 
            'attributes' => {
6046 
              'bin_pt' => 0,
6047 
              'is_floating_block' => 1,
6048 
              'must_be_hdl_vector' => 1,
6049 
              'period' => 1.0,
6050 
              'port_id' => '0',
6051 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/data_in',
6052 
              'type' => 'UFix_32_0',
6053 
            },
6054 
            'direction' => 'in',
6055 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6056 
            'width' => 32,
6057 
          },
6058 
          'dout' => {
6059 
            'attributes' => {
6060 
              'bin_pt' => 0,
6061 
              'is_floating_block' => 1,
6062 
              'must_be_hdl_vector' => 1,
6063 
              'period' => 1.0,
6064 
              'port_id' => '0',
6065 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/dout',
6066 
              'type' => 'UFix_32_0',
6067 
            },
6068 
            'direction' => 'out',
6069 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6070 
            'width' => 32,
6071 
          },
6072 
          'en' => {
6073 
            'attributes' => {
6074 
              'bin_pt' => 0,
6075 
              'is_floating_block' => 1,
6076 
              'must_be_hdl_vector' => 1,
6077 
              'period' => 1.0,
6078 
              'port_id' => '1',
6079 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/en',
6080 
              'type' => 'Bool',
6081 
            },
6082 
            'direction' => 'in',
6083 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6084 
            'width' => 1,
6085 
          },
6086 
        },
6087 
      },
6088 
      'entityName' => 'x_x54',
6089 
    },
6090 
    'to_register4' => {
6091 
      'connections' => {
6092 
        'ce' => 'ce_1_sg_x0',
6093 
        'clk' => 'clk_1_sg_x0',
6094 
        'clr' => [
6095 
          'constant',
6096 
          '\'0\'',
6097 
        ],
6098 
        'data_in' => 'data_in_x21_net',
6099 
        'dout' => 'to_register4_dout_net',
6100 
        'en' => 'constant6_op_net_x22',
6101 
      },
6102 
      'entity' => {
6103 
        'attributes' => {
6104 
          'generics' => [],
6105 
          'is_floating_block' => 1,
6106 
          'mask' => {
6107 
            'Block_Handle' => 1003.0001220703125,
6108 
            'Block_handle' => 1003.0001220703125,
6109 
            'MDL_Handle' => 3.0009765625,
6110 
            'MDL_handle' => 3.0009765625,
6111 
            'arith_type' => 1,
6112 
            'bin_pt' => 14,
6113 
            'block_config' => 'sysgen_blockset:toreg_config',
6114 
            'block_handle' => 1003.0001220703125,
6115 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4',
6116 
            'block_type' => 'toreg',
6117 
            'dbl_ovrd' => 0,
6118 
            'explicit_data_type' => 0,
6119 
            'init' => 0.0,
6120 
            'init_bit_vector' => '0b',
6121 
            'mdl_handle' => 3.0009765625,
6122 
            'model_handle' => 3.0009765625,
6123 
            'n_bits' => 16,
6124 
            'ownership' => 1,
6125 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
6126 
            'shared_memory_name' => 'register02rv',
6127 
          },
6128 
          'needs_vhdl_wrapper' => 0,
6129 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4',
6130 
        },
6131 
        'entityName' => 'x_x55',
6132 
        'ports' => {
6133 
          'ce' => {
6134 
            'attributes' => {
6135 
              'domain' => '',
6136 
              'group' => 1,
6137 
              'isCe' => 1,
6138 
              'is_floating_block' => 1,
6139 
              'period' => 1.0,
6140 
              'type' => 'logic',
6141 
            },
6142 
            'direction' => 'in',
6143 
            'hdlType' => 'std_logic',
6144 
            'width' => 1,
6145 
          },
6146 
          'clk' => {
6147 
            'attributes' => {
6148 
              'domain' => '',
6149 
              'group' => 1,
6150 
              'isClk' => 1,
6151 
              'is_floating_block' => 1,
6152 
              'period' => 1.0,
6153 
              'type' => 'logic',
6154 
            },
6155 
            'direction' => 'in',
6156 
            'hdlType' => 'std_logic',
6157 
            'width' => 1,
6158 
          },
6159 
          'clr' => {
6160 
            'attributes' => {
6161 
              'domain' => '',
6162 
              'group' => 1,
6163 
              'isClr' => 1,
6164 
              'is_floating_block' => 1,
6165 
              'period' => 1,
6166 
              'type' => 'logic',
6167 
              'valid_bit_used' => 0,
6168 
            },
6169 
            'direction' => 'in',
6170 
            'hdlType' => 'std_logic',
6171 
            'width' => 1,
6172 
          },
6173 
          'data_in' => {
6174 
            'attributes' => {
6175 
              'bin_pt' => 0,
6176 
              'is_floating_block' => 1,
6177 
              'must_be_hdl_vector' => 1,
6178 
              'period' => 1.0,
6179 
              'port_id' => '0',
6180 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/data_in',
6181 
              'type' => 'Bool',
6182 
            },
6183 
            'direction' => 'in',
6184 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6185 
            'width' => 1,
6186 
          },
6187 
          'dout' => {
6188 
            'attributes' => {
6189 
              'bin_pt' => 0,
6190 
              'is_floating_block' => 1,
6191 
              'must_be_hdl_vector' => 1,
6192 
              'period' => 1.0,
6193 
              'port_id' => '0',
6194 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/dout',
6195 
              'type' => 'Bool',
6196 
            },
6197 
            'direction' => 'out',
6198 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6199 
            'width' => 1,
6200 
          },
6201 
          'en' => {
6202 
            'attributes' => {
6203 
              'bin_pt' => 0,
6204 
              'is_floating_block' => 1,
6205 
              'must_be_hdl_vector' => 1,
6206 
              'period' => 1.0,
6207 
              'port_id' => '1',
6208 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/en',
6209 
              'type' => 'Bool',
6210 
            },
6211 
            'direction' => 'in',
6212 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6213 
            'width' => 1,
6214 
          },
6215 
        },
6216 
      },
6217 
      'entityName' => 'x_x55',
6218 
    },
6219 
    'to_register5' => {
6220 
      'connections' => {
6221 
        'ce' => 'ce_1_sg_x0',
6222 
        'clk' => 'clk_1_sg_x0',
6223 
        'clr' => [
6224 
          'constant',
6225 
          '\'0\'',
6226 
        ],
6227 
        'data_in' => 'data_in_x22_net',
6228 
        'dout' => 'to_register5_dout_net',
6229 
        'en' => 'constant6_op_net_x23',
6230 
      },
6231 
      'entity' => {
6232 
        'attributes' => {
6233 
          'generics' => [],
6234 
          'is_floating_block' => 1,
6235 
          'mask' => {
6236 
            'Block_Handle' => 1004.0001220703125,
6237 
            'Block_handle' => 1004.0001220703125,
6238 
            'MDL_Handle' => 3.0009765625,
6239 
            'MDL_handle' => 3.0009765625,
6240 
            'arith_type' => 1,
6241 
            'bin_pt' => 14,
6242 
            'block_config' => 'sysgen_blockset:toreg_config',
6243 
            'block_handle' => 1004.0001220703125,
6244 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5',
6245 
            'block_type' => 'toreg',
6246 
            'dbl_ovrd' => 0,
6247 
            'explicit_data_type' => 0,
6248 
            'init' => 0.0,
6249 
            'init_bit_vector' => '0b',
6250 
            'mdl_handle' => 3.0009765625,
6251 
            'model_handle' => 3.0009765625,
6252 
            'n_bits' => 16,
6253 
            'ownership' => 1,
6254 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
6255 
            'shared_memory_name' => 'register03rv',
6256 
          },
6257 
          'needs_vhdl_wrapper' => 0,
6258 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5',
6259 
        },
6260 
        'entityName' => 'x_x56',
6261 
        'ports' => {
6262 
          'ce' => {
6263 
            'attributes' => {
6264 
              'domain' => '',
6265 
              'group' => 1,
6266 
              'isCe' => 1,
6267 
              'is_floating_block' => 1,
6268 
              'period' => 1.0,
6269 
              'type' => 'logic',
6270 
            },
6271 
            'direction' => 'in',
6272 
            'hdlType' => 'std_logic',
6273 
            'width' => 1,
6274 
          },
6275 
          'clk' => {
6276 
            'attributes' => {
6277 
              'domain' => '',
6278 
              'group' => 1,
6279 
              'isClk' => 1,
6280 
              'is_floating_block' => 1,
6281 
              'period' => 1.0,
6282 
              'type' => 'logic',
6283 
            },
6284 
            'direction' => 'in',
6285 
            'hdlType' => 'std_logic',
6286 
            'width' => 1,
6287 
          },
6288 
          'clr' => {
6289 
            'attributes' => {
6290 
              'domain' => '',
6291 
              'group' => 1,
6292 
              'isClr' => 1,
6293 
              'is_floating_block' => 1,
6294 
              'period' => 1,
6295 
              'type' => 'logic',
6296 
              'valid_bit_used' => 0,
6297 
            },
6298 
            'direction' => 'in',
6299 
            'hdlType' => 'std_logic',
6300 
            'width' => 1,
6301 
          },
6302 
          'data_in' => {
6303 
            'attributes' => {
6304 
              'bin_pt' => 0,
6305 
              'is_floating_block' => 1,
6306 
              'must_be_hdl_vector' => 1,
6307 
              'period' => 1.0,
6308 
              'port_id' => '0',
6309 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/data_in',
6310 
              'type' => 'Bool',
6311 
            },
6312 
            'direction' => 'in',
6313 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6314 
            'width' => 1,
6315 
          },
6316 
          'dout' => {
6317 
            'attributes' => {
6318 
              'bin_pt' => 0,
6319 
              'is_floating_block' => 1,
6320 
              'must_be_hdl_vector' => 1,
6321 
              'period' => 1.0,
6322 
              'port_id' => '0',
6323 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/dout',
6324 
              'type' => 'Bool',
6325 
            },
6326 
            'direction' => 'out',
6327 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6328 
            'width' => 1,
6329 
          },
6330 
          'en' => {
6331 
            'attributes' => {
6332 
              'bin_pt' => 0,
6333 
              'is_floating_block' => 1,
6334 
              'must_be_hdl_vector' => 1,
6335 
              'period' => 1.0,
6336 
              'port_id' => '1',
6337 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/en',
6338 
              'type' => 'Bool',
6339 
            },
6340 
            'direction' => 'in',
6341 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6342 
            'width' => 1,
6343 
          },
6344 
        },
6345 
      },
6346 
      'entityName' => 'x_x56',
6347 
    },
6348 
    'to_register6' => {
6349 
      'connections' => {
6350 
        'ce' => 'ce_1_sg_x0',
6351 
        'clk' => 'clk_1_sg_x0',
6352 
        'clr' => [
6353 
          'constant',
6354 
          '\'0\'',
6355 
        ],
6356 
        'data_in' => 'data_in_x23_net',
6357 
        'dout' => 'to_register6_dout_net',
6358 
        'en' => 'constant6_op_net_x24',
6359 
      },
6360 
      'entity' => {
6361 
        'attributes' => {
6362 
          'generics' => [],
6363 
          'is_floating_block' => 1,
6364 
          'mask' => {
6365 
            'Block_Handle' => 1005.0001220703125,
6366 
            'Block_handle' => 1005.0001220703125,
6367 
            'MDL_Handle' => 3.0009765625,
6368 
            'MDL_handle' => 3.0009765625,
6369 
            'arith_type' => 1,
6370 
            'bin_pt' => 14,
6371 
            'block_config' => 'sysgen_blockset:toreg_config',
6372 
            'block_handle' => 1005.0001220703125,
6373 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6',
6374 
            'block_type' => 'toreg',
6375 
            'dbl_ovrd' => 0,
6376 
            'explicit_data_type' => 0,
6377 
            'init' => 0.0,
6378 
            'init_bit_vector' => '00000000000000000000000000000000b',
6379 
            'mdl_handle' => 3.0009765625,
6380 
            'model_handle' => 3.0009765625,
6381 
            'n_bits' => 16,
6382 
            'ownership' => 1,
6383 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
6384 
            'shared_memory_name' => 'register04rd',
6385 
          },
6386 
          'needs_vhdl_wrapper' => 0,
6387 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6',
6388 
        },
6389 
        'entityName' => 'x_x57',
6390 
        'ports' => {
6391 
          'ce' => {
6392 
            'attributes' => {
6393 
              'domain' => '',
6394 
              'group' => 1,
6395 
              'isCe' => 1,
6396 
              'is_floating_block' => 1,
6397 
              'period' => 1.0,
6398 
              'type' => 'logic',
6399 
            },
6400 
            'direction' => 'in',
6401 
            'hdlType' => 'std_logic',
6402 
            'width' => 1,
6403 
          },
6404 
          'clk' => {
6405 
            'attributes' => {
6406 
              'domain' => '',
6407 
              'group' => 1,
6408 
              'isClk' => 1,
6409 
              'is_floating_block' => 1,
6410 
              'period' => 1.0,
6411 
              'type' => 'logic',
6412 
            },
6413 
            'direction' => 'in',
6414 
            'hdlType' => 'std_logic',
6415 
            'width' => 1,
6416 
          },
6417 
          'clr' => {
6418 
            'attributes' => {
6419 
              'domain' => '',
6420 
              'group' => 1,
6421 
              'isClr' => 1,
6422 
              'is_floating_block' => 1,
6423 
              'period' => 1,
6424 
              'type' => 'logic',
6425 
              'valid_bit_used' => 0,
6426 
            },
6427 
            'direction' => 'in',
6428 
            'hdlType' => 'std_logic',
6429 
            'width' => 1,
6430 
          },
6431 
          'data_in' => {
6432 
            'attributes' => {
6433 
              'bin_pt' => 0,
6434 
              'is_floating_block' => 1,
6435 
              'must_be_hdl_vector' => 1,
6436 
              'period' => 1.0,
6437 
              'port_id' => '0',
6438 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/data_in',
6439 
              'type' => 'UFix_32_0',
6440 
            },
6441 
            'direction' => 'in',
6442 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6443 
            'width' => 32,
6444 
          },
6445 
          'dout' => {
6446 
            'attributes' => {
6447 
              'bin_pt' => 0,
6448 
              'is_floating_block' => 1,
6449 
              'must_be_hdl_vector' => 1,
6450 
              'period' => 1.0,
6451 
              'port_id' => '0',
6452 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/dout',
6453 
              'type' => 'UFix_32_0',
6454 
            },
6455 
            'direction' => 'out',
6456 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6457 
            'width' => 32,
6458 
          },
6459 
          'en' => {
6460 
            'attributes' => {
6461 
              'bin_pt' => 0,
6462 
              'is_floating_block' => 1,
6463 
              'must_be_hdl_vector' => 1,
6464 
              'period' => 1.0,
6465 
              'port_id' => '1',
6466 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/en',
6467 
              'type' => 'Bool',
6468 
            },
6469 
            'direction' => 'in',
6470 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6471 
            'width' => 1,
6472 
          },
6473 
        },
6474 
      },
6475 
      'entityName' => 'x_x57',
6476 
    },
6477 
    'to_register7' => {
6478 
      'connections' => {
6479 
        'ce' => 'ce_1_sg_x0',
6480 
        'clk' => 'clk_1_sg_x0',
6481 
        'clr' => [
6482 
          'constant',
6483 
          '\'0\'',
6484 
        ],
6485 
        'data_in' => 'data_in_x24_net',
6486 
        'dout' => 'to_register7_dout_net',
6487 
        'en' => 'constant6_op_net_x25',
6488 
      },
6489 
      'entity' => {
6490 
        'attributes' => {
6491 
          'generics' => [],
6492 
          'is_floating_block' => 1,
6493 
          'mask' => {
6494 
            'Block_Handle' => 1006.0001220703125,
6495 
            'Block_handle' => 1006.0001220703125,
6496 
            'MDL_Handle' => 3.0009765625,
6497 
            'MDL_handle' => 3.0009765625,
6498 
            'arith_type' => 1,
6499 
            'bin_pt' => 14,
6500 
            'block_config' => 'sysgen_blockset:toreg_config',
6501 
            'block_handle' => 1006.0001220703125,
6502 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7',
6503 
            'block_type' => 'toreg',
6504 
            'dbl_ovrd' => 0,
6505 
            'explicit_data_type' => 0,
6506 
            'init' => 0.0,
6507 
            'init_bit_vector' => '0b',
6508 
            'mdl_handle' => 3.0009765625,
6509 
            'model_handle' => 3.0009765625,
6510 
            'n_bits' => 16,
6511 
            'ownership' => 1,
6512 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
6513 
            'shared_memory_name' => 'register04rv',
6514 
          },
6515 
          'needs_vhdl_wrapper' => 0,
6516 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7',
6517 
        },
6518 
        'entityName' => 'x_x58',
6519 
        'ports' => {
6520 
          'ce' => {
6521 
            'attributes' => {
6522 
              'domain' => '',
6523 
              'group' => 1,
6524 
              'isCe' => 1,
6525 
              'is_floating_block' => 1,
6526 
              'period' => 1.0,
6527 
              'type' => 'logic',
6528 
            },
6529 
            'direction' => 'in',
6530 
            'hdlType' => 'std_logic',
6531 
            'width' => 1,
6532 
          },
6533 
          'clk' => {
6534 
            'attributes' => {
6535 
              'domain' => '',
6536 
              'group' => 1,
6537 
              'isClk' => 1,
6538 
              'is_floating_block' => 1,
6539 
              'period' => 1.0,
6540 
              'type' => 'logic',
6541 
            },
6542 
            'direction' => 'in',
6543 
            'hdlType' => 'std_logic',
6544 
            'width' => 1,
6545 
          },
6546 
          'clr' => {
6547 
            'attributes' => {
6548 
              'domain' => '',
6549 
              'group' => 1,
6550 
              'isClr' => 1,
6551 
              'is_floating_block' => 1,
6552 
              'period' => 1,
6553 
              'type' => 'logic',
6554 
              'valid_bit_used' => 0,
6555 
            },
6556 
            'direction' => 'in',
6557 
            'hdlType' => 'std_logic',
6558 
            'width' => 1,
6559 
          },
6560 
          'data_in' => {
6561 
            'attributes' => {
6562 
              'bin_pt' => 0,
6563 
              'is_floating_block' => 1,
6564 
              'must_be_hdl_vector' => 1,
6565 
              'period' => 1.0,
6566 
              'port_id' => '0',
6567 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/data_in',
6568 
              'type' => 'Bool',
6569 
            },
6570 
            'direction' => 'in',
6571 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6572 
            'width' => 1,
6573 
          },
6574 
          'dout' => {
6575 
            'attributes' => {
6576 
              'bin_pt' => 0,
6577 
              'is_floating_block' => 1,
6578 
              'must_be_hdl_vector' => 1,
6579 
              'period' => 1.0,
6580 
              'port_id' => '0',
6581 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/dout',
6582 
              'type' => 'Bool',
6583 
            },
6584 
            'direction' => 'out',
6585 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6586 
            'width' => 1,
6587 
          },
6588 
          'en' => {
6589 
            'attributes' => {
6590 
              'bin_pt' => 0,
6591 
              'is_floating_block' => 1,
6592 
              'must_be_hdl_vector' => 1,
6593 
              'period' => 1.0,
6594 
              'port_id' => '1',
6595 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/en',
6596 
              'type' => 'Bool',
6597 
            },
6598 
            'direction' => 'in',
6599 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6600 
            'width' => 1,
6601 
          },
6602 
        },
6603 
      },
6604 
      'entityName' => 'x_x58',
6605 
    },
6606 
    'to_register8' => {
6607 
      'connections' => {
6608 
        'ce' => 'ce_1_sg_x0',
6609 
        'clk' => 'clk_1_sg_x0',
6610 
        'clr' => [
6611 
          'constant',
6612 
          '\'0\'',
6613 
        ],
6614 
        'data_in' => 'data_in_x25_net',
6615 
        'dout' => 'to_register8_dout_net',
6616 
        'en' => 'constant6_op_net_x26',
6617 
      },
6618 
      'entity' => {
6619 
        'attributes' => {
6620 
          'generics' => [],
6621 
          'is_floating_block' => 1,
6622 
          'mask' => {
6623 
            'Block_Handle' => 1007.0001220703125,
6624 
            'Block_handle' => 1007.0001220703125,
6625 
            'MDL_Handle' => 3.0009765625,
6626 
            'MDL_handle' => 3.0009765625,
6627 
            'arith_type' => 1,
6628 
            'bin_pt' => 14,
6629 
            'block_config' => 'sysgen_blockset:toreg_config',
6630 
            'block_handle' => 1007.0001220703125,
6631 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8',
6632 
            'block_type' => 'toreg',
6633 
            'dbl_ovrd' => 0,
6634 
            'explicit_data_type' => 0,
6635 
            'init' => 0.0,
6636 
            'init_bit_vector' => '00000000000000000000000000000000b',
6637 
            'mdl_handle' => 3.0009765625,
6638 
            'model_handle' => 3.0009765625,
6639 
            'n_bits' => 16,
6640 
            'ownership' => 1,
6641 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
6642 
            'shared_memory_name' => 'register05rd',
6643 
          },
6644 
          'needs_vhdl_wrapper' => 0,
6645 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8',
6646 
        },
6647 
        'entityName' => 'x_x59',
6648 
        'ports' => {
6649 
          'ce' => {
6650 
            'attributes' => {
6651 
              'domain' => '',
6652 
              'group' => 1,
6653 
              'isCe' => 1,
6654 
              'is_floating_block' => 1,
6655 
              'period' => 1.0,
6656 
              'type' => 'logic',
6657 
            },
6658 
            'direction' => 'in',
6659 
            'hdlType' => 'std_logic',
6660 
            'width' => 1,
6661 
          },
6662 
          'clk' => {
6663 
            'attributes' => {
6664 
              'domain' => '',
6665 
              'group' => 1,
6666 
              'isClk' => 1,
6667 
              'is_floating_block' => 1,
6668 
              'period' => 1.0,
6669 
              'type' => 'logic',
6670 
            },
6671 
            'direction' => 'in',
6672 
            'hdlType' => 'std_logic',
6673 
            'width' => 1,
6674 
          },
6675 
          'clr' => {
6676 
            'attributes' => {
6677 
              'domain' => '',
6678 
              'group' => 1,
6679 
              'isClr' => 1,
6680 
              'is_floating_block' => 1,
6681 
              'period' => 1,
6682 
              'type' => 'logic',
6683 
              'valid_bit_used' => 0,
6684 
            },
6685 
            'direction' => 'in',
6686 
            'hdlType' => 'std_logic',
6687 
            'width' => 1,
6688 
          },
6689 
          'data_in' => {
6690 
            'attributes' => {
6691 
              'bin_pt' => 0,
6692 
              'is_floating_block' => 1,
6693 
              'must_be_hdl_vector' => 1,
6694 
              'period' => 1.0,
6695 
              'port_id' => '0',
6696 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/data_in',
6697 
              'type' => 'UFix_32_0',
6698 
            },
6699 
            'direction' => 'in',
6700 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6701 
            'width' => 32,
6702 
          },
6703 
          'dout' => {
6704 
            'attributes' => {
6705 
              'bin_pt' => 0,
6706 
              'is_floating_block' => 1,
6707 
              'must_be_hdl_vector' => 1,
6708 
              'period' => 1.0,
6709 
              'port_id' => '0',
6710 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/dout',
6711 
              'type' => 'UFix_32_0',
6712 
            },
6713 
            'direction' => 'out',
6714 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6715 
            'width' => 32,
6716 
          },
6717 
          'en' => {
6718 
            'attributes' => {
6719 
              'bin_pt' => 0,
6720 
              'is_floating_block' => 1,
6721 
              'must_be_hdl_vector' => 1,
6722 
              'period' => 1.0,
6723 
              'port_id' => '1',
6724 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/en',
6725 
              'type' => 'Bool',
6726 
            },
6727 
            'direction' => 'in',
6728 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6729 
            'width' => 1,
6730 
          },
6731 
        },
6732 
      },
6733 
      'entityName' => 'x_x59',
6734 
    },
6735 
    'to_register9' => {
6736 
      'connections' => {
6737 
        'ce' => 'ce_1_sg_x0',
6738 
        'clk' => 'clk_1_sg_x0',
6739 
        'clr' => [
6740 
          'constant',
6741 
          '\'0\'',
6742 
        ],
6743 
        'data_in' => 'data_in_x26_net',
6744 
        'dout' => 'to_register9_dout_net',
6745 
        'en' => 'constant6_op_net_x27',
6746 
      },
6747 
      'entity' => {
6748 
        'attributes' => {
6749 
          'generics' => [],
6750 
          'is_floating_block' => 1,
6751 
          'mask' => {
6752 
            'Block_Handle' => 1008.0001220703125,
6753 
            'Block_handle' => 1008.0001220703125,
6754 
            'MDL_Handle' => 3.0009765625,
6755 
            'MDL_handle' => 3.0009765625,
6756 
            'arith_type' => 1,
6757 
            'bin_pt' => 14,
6758 
            'block_config' => 'sysgen_blockset:toreg_config',
6759 
            'block_handle' => 1008.0001220703125,
6760 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9',
6761 
            'block_type' => 'toreg',
6762 
            'dbl_ovrd' => 0,
6763 
            'explicit_data_type' => 0,
6764 
            'init' => 0.0,
6765 
            'init_bit_vector' => '00000000000000000000000000000000b',
6766 
            'mdl_handle' => 3.0009765625,
6767 
            'model_handle' => 3.0009765625,
6768 
            'n_bits' => 16,
6769 
            'ownership' => 1,
6770 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
6771 
            'shared_memory_name' => 'register06rd',
6772 
          },
6773 
          'needs_vhdl_wrapper' => 0,
6774 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9',
6775 
        },
6776 
        'entityName' => 'x_x60',
6777 
        'ports' => {
6778 
          'ce' => {
6779 
            'attributes' => {
6780 
              'domain' => '',
6781 
              'group' => 1,
6782 
              'isCe' => 1,
6783 
              'is_floating_block' => 1,
6784 
              'period' => 1.0,
6785 
              'type' => 'logic',
6786 
            },
6787 
            'direction' => 'in',
6788 
            'hdlType' => 'std_logic',
6789 
            'width' => 1,
6790 
          },
6791 
          'clk' => {
6792 
            'attributes' => {
6793 
              'domain' => '',
6794 
              'group' => 1,
6795 
              'isClk' => 1,
6796 
              'is_floating_block' => 1,
6797 
              'period' => 1.0,
6798 
              'type' => 'logic',
6799 
            },
6800 
            'direction' => 'in',
6801 
            'hdlType' => 'std_logic',
6802 
            'width' => 1,
6803 
          },
6804 
          'clr' => {
6805 
            'attributes' => {
6806 
              'domain' => '',
6807 
              'group' => 1,
6808 
              'isClr' => 1,
6809 
              'is_floating_block' => 1,
6810 
              'period' => 1,
6811 
              'type' => 'logic',
6812 
              'valid_bit_used' => 0,
6813 
            },
6814 
            'direction' => 'in',
6815 
            'hdlType' => 'std_logic',
6816 
            'width' => 1,
6817 
          },
6818 
          'data_in' => {
6819 
            'attributes' => {
6820 
              'bin_pt' => 0,
6821 
              'is_floating_block' => 1,
6822 
              'must_be_hdl_vector' => 1,
6823 
              'period' => 1.0,
6824 
              'port_id' => '0',
6825 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/data_in',
6826 
              'type' => 'UFix_32_0',
6827 
            },
6828 
            'direction' => 'in',
6829 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6830 
            'width' => 32,
6831 
          },
6832 
          'dout' => {
6833 
            'attributes' => {
6834 
              'bin_pt' => 0,
6835 
              'is_floating_block' => 1,
6836 
              'must_be_hdl_vector' => 1,
6837 
              'period' => 1.0,
6838 
              'port_id' => '0',
6839 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/dout',
6840 
              'type' => 'UFix_32_0',
6841 
            },
6842 
            'direction' => 'out',
6843 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6844 
            'width' => 32,
6845 
          },
6846 
          'en' => {
6847 
            'attributes' => {
6848 
              'bin_pt' => 0,
6849 
              'is_floating_block' => 1,
6850 
              'must_be_hdl_vector' => 1,
6851 
              'period' => 1.0,
6852 
              'port_id' => '1',
6853 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/en',
6854 
              'type' => 'Bool',
6855 
            },
6856 
            'direction' => 'in',
6857 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6858 
            'width' => 1,
6859 
          },
6860 
        },
6861 
      },
6862 
      'entityName' => 'x_x60',
6863 
    },
6864 
    'user_int_1o' => {
6865 
      'connections' => { 'user_int_1o' => 'user_int_1o_net', },
6866 
      'entity' => {
6867 
        'attributes' => {
6868 
          'isGateway' => 1,
6869 
          'is_floating_block' => 1,
6870 
        },
6871 
        'entityName' => 'user_int_1o',
6872 
        'ports' => {
6873 
          'user_int_1o' => {
6874 
            'attributes' => {
6875 
              'bin_pt' => 0,
6876 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
6877 
              'is_floating_block' => 1,
6878 
              'is_gateway_port' => 1,
6879 
              'must_be_hdl_vector' => 1,
6880 
              'period' => 1.0,
6881 
              'port_id' => '0',
6882 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
6883 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
6884 
              'timingConstraint' => 'none',
6885 
              'type' => 'Bool',
6886 
            },
6887 
            'direction' => 'in',
6888 
            'hdlType' => 'std_logic',
6889 
            'width' => 1,
6890 
          },
6891 
        },
6892 
      },
6893 
      'entityName' => 'user_int_1o',
6894 
    },
6895 
    'user_int_2o' => {
6896 
      'connections' => { 'user_int_2o' => 'user_int_2o_net', },
6897 
      'entity' => {
6898 
        'attributes' => {
6899 
          'isGateway' => 1,
6900 
          'is_floating_block' => 1,
6901 
        },
6902 
        'entityName' => 'user_int_2o',
6903 
        'ports' => {
6904 
          'user_int_2o' => {
6905 
            'attributes' => {
6906 
              'bin_pt' => 0,
6907 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
6908 
              'is_floating_block' => 1,
6909 
              'is_gateway_port' => 1,
6910 
              'must_be_hdl_vector' => 1,
6911 
              'period' => 1.0,
6912 
              'port_id' => '0',
6913 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
6914 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
6915 
              'timingConstraint' => 'none',
6916 
              'type' => 'Bool',
6917 
            },
6918 
            'direction' => 'in',
6919 
            'hdlType' => 'std_logic',
6920 
            'width' => 1,
6921 
          },
6922 
        },
6923 
      },
6924 
      'entityName' => 'user_int_2o',
6925 
    },
6926 
    'user_int_3o' => {
6927 
      'connections' => { 'user_int_3o' => 'user_int_3o_net', },
6928 
      'entity' => {
6929 
        'attributes' => {
6930 
          'isGateway' => 1,
6931 
          'is_floating_block' => 1,
6932 
        },
6933 
        'entityName' => 'user_int_3o',
6934 
        'ports' => {
6935 
          'user_int_3o' => {
6936 
            'attributes' => {
6937 
              'bin_pt' => 0,
6938 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
6939 
              'is_floating_block' => 1,
6940 
              'is_gateway_port' => 1,
6941 
              'must_be_hdl_vector' => 1,
6942 
              'period' => 1.0,
6943 
              'port_id' => '0',
6944 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
6945 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
6946 
              'timingConstraint' => 'none',
6947 
              'type' => 'Bool',
6948 
            },
6949 
            'direction' => 'in',
6950 
            'hdlType' => 'std_logic',
6951 
            'width' => 1,
6952 
          },
6953 
        },
6954 
      },
6955 
      'entityName' => 'user_int_3o',
6956 
    },
6957 
    'user_logic' => {
6958 
      'connections' => {
6959 
        'bram_rd_addr' => 'bram_rd_addr_net',
6960 
        'bram_rd_dout' => 'bram_rd_dout_net',
6961 
        'bram_wr_addr' => 'bram_wr_addr_net',
6962 
        'bram_wr_din' => 'bram_wr_din_net',
6963 
        'bram_wr_en' => 'bram_wr_en_net',
6964 
        'ce_1' => 'ce_1_sg_x0',
6965 
        'clk_1' => 'clk_1_sg_x0',
6966 
        'data_in' => 'data_in_net',
6967 
        'data_in_x0' => 'data_in_x0_net',
6968 
        'data_in_x1' => 'data_in_x1_net',
6969 
        'data_in_x10' => 'data_in_x10_net',
6970 
        'data_in_x11' => 'data_in_x11_net',
6971 
        'data_in_x12' => 'data_in_x12_net',
6972 
        'data_in_x13' => 'data_in_x13_net',
6973 
        'data_in_x14' => 'data_in_x14_net',
6974 
        'data_in_x15' => 'data_in_x15_net',
6975 
        'data_in_x16' => 'data_in_x16_net',
6976 
        'data_in_x17' => 'data_in_x17_net',
6977 
        'data_in_x18' => 'data_in_x18_net',
6978 
        'data_in_x19' => 'data_in_x19_net',
6979 
        'data_in_x2' => 'data_in_x2_net',
6980 
        'data_in_x20' => 'data_in_x20_net',
6981 
        'data_in_x21' => 'data_in_x21_net',
6982 
        'data_in_x22' => 'data_in_x22_net',
6983 
        'data_in_x23' => 'data_in_x23_net',
6984 
        'data_in_x24' => 'data_in_x24_net',
6985 
        'data_in_x25' => 'data_in_x25_net',
6986 
        'data_in_x26' => 'data_in_x26_net',
6987 
        'data_in_x3' => 'data_in_x3_net',
6988 
        'data_in_x4' => 'data_in_x4_net',
6989 
        'data_in_x5' => 'data_in_x5_net',
6990 
        'data_in_x6' => 'data_in_x6_net',
6991 
        'data_in_x7' => 'data_in_x7_net',
6992 
        'data_in_x8' => 'data_in_x8_net',
6993 
        'data_in_x9' => 'data_in_x9_net',
6994 
        'data_out' => 'data_out_net',
6995 
        'data_out_x0' => 'data_out_x0_net',
6996 
        'data_out_x1' => 'data_out_x1_net',
6997 
        'data_out_x10' => 'data_out_x10_net',
6998 
        'data_out_x11' => 'data_out_x11_net',
6999 
        'data_out_x12' => 'data_out_x12_net',
7000 
        'data_out_x13' => 'data_out_x13_net',
7001 
        'data_out_x14' => 'data_out_x14_net',
7002 
        'data_out_x15' => 'data_out_x15_net',
7003 
        'data_out_x16' => 'data_out_x16_net',
7004 
        'data_out_x17' => 'data_out_x17_net',
7005 
        'data_out_x18' => 'data_out_x18_net',
7006 
        'data_out_x19' => 'data_out_x19_net',
7007 
        'data_out_x2' => 'data_out_x2_net',
7008 
        'data_out_x20' => 'data_out_x20_net',
7009 
        'data_out_x21' => 'data_out_x21_net',
7010 
        'data_out_x22' => 'data_out_x22_net',
7011 
        'data_out_x23' => 'data_out_x23_net',
7012 
        'data_out_x24' => 'data_out_x24_net',
7013 
        'data_out_x25' => 'data_out_x25_net',
7014 
        'data_out_x26' => 'data_out_x26_net',
7015 
        'data_out_x27' => 'data_out_x27_net',
7016 
        'data_out_x28' => 'data_out_x28_net',
7017 
        'data_out_x3' => 'data_out_x3_net',
7018 
        'data_out_x6' => 'data_out_x6_net',
7019 
        'data_out_x7' => 'data_out_x7_net',
7020 
        'data_out_x8' => 'data_out_x8_net',
7021 
        'data_out_x9' => 'data_out_x9_net',
7022 
        'en' => 'constant6_op_net_x0',
7023 
        'en_x0' => 'constant6_op_net_x1',
7024 
        'en_x1' => 'constant6_op_net_x2',
7025 
        'en_x10' => 'constant6_op_net_x11',
7026 
        'en_x11' => 'constant6_op_net_x12',
7027 
        'en_x12' => 'constant6_op_net_x13',
7028 
        'en_x13' => 'constant6_op_net_x14',
7029 
        'en_x14' => 'constant6_op_net_x15',
7030 
        'en_x15' => 'constant6_op_net_x16',
7031 
        'en_x16' => 'constant6_op_net_x17',
7032 
        'en_x17' => 'constant6_op_net_x18',
7033 
        'en_x18' => 'constant6_op_net_x19',
7034 
        'en_x19' => 'constant6_op_net_x20',
7035 
        'en_x2' => 'constant6_op_net_x3',
7036 
        'en_x20' => 'constant6_op_net_x21',
7037 
        'en_x21' => 'constant6_op_net_x22',
7038 
        'en_x22' => 'constant6_op_net_x23',
7039 
        'en_x23' => 'constant6_op_net_x24',
7040 
        'en_x24' => 'constant6_op_net_x25',
7041 
        'en_x25' => 'constant6_op_net_x26',
7042 
        'en_x26' => 'constant6_op_net_x27',
7043 
        'en_x3' => 'constant6_op_net_x4',
7044 
        'en_x4' => 'constant6_op_net_x5',
7045 
        'en_x5' => 'constant6_op_net_x6',
7046 
        'en_x6' => 'constant6_op_net_x7',
7047 
        'en_x7' => 'constant6_op_net_x8',
7048 
        'en_x8' => 'constant6_op_net_x9',
7049 
        'en_x9' => 'constant6_op_net_x10',
7050 
        'fifo_rd_count' => 'fifo_rd_count_net',
7051 
        'fifo_rd_dout' => 'fifo_rd_dout_net',
7052 
        'fifo_rd_empty' => 'fifo_rd_empty_net',
7053 
        'fifo_rd_en' => 'fifo_rd_en_net',
7054 
        'fifo_rd_pempty' => 'fifo_rd_pempty_net',
7055 
        'fifo_rd_valid' => 'fifo_rd_valid_net',
7056 
        'fifo_wr_count' => 'fifo_wr_count_net',
7057 
        'fifo_wr_din' => 'fifo_wr_din_net',
7058 
        'fifo_wr_en' => 'fifo_wr_en_net',
7059 
        'fifo_wr_full' => 'fifo_wr_full_net',
7060 
        'fifo_wr_pfull' => 'fifo_wr_pfull_net',
7061 
        'rst_i' => 'rst_i_net',
7062 
        'rst_o' => 'rst_o_net',
7063 
        'user_int_1o' => 'user_int_1o_net',
7064 
        'user_int_2o' => 'user_int_2o_net',
7065 
        'user_int_3o' => 'user_int_3o_net',
7066 
      },
7067 
      'entity' => {
7068 
        'attributes' => {
7069 
          'entityAlreadyNetlisted' => 1,
7070 
          'hdlKind' => 'vhdl',
7071 
          'isDesign' => 1,
7072 
          'simulinkName' => 'USER_LOGIC',
7073 
        },
7074 
        'entityName' => 'user_logic',
7075 
        'ports' => {
7076 
          'bram_rd_addr' => {
7077 
            'attributes' => {
7078 
              'bin_pt' => 0,
7079 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
7080 
              'is_floating_block' => 1,
7081 
              'is_gateway_port' => 1,
7082 
              'must_be_hdl_vector' => 1,
7083 
              'period' => 1.0,
7084 
              'port_id' => '15',
7085 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
7086 
              'source_block' => 'USER_LOGIC',
7087 
              'timingConstraint' => 'none',
7088 
              'type' => 'UFix_12_0',
7089 
            },
7090 
            'direction' => 'out',
7091 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7092 
            'width' => 12,
7093 
          },
7094 
          'bram_rd_dout' => {
7095 
            'attributes' => {
7096 
              'bin_pt' => 0,
7097 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
7098 
              'is_floating_block' => 1,
7099 
              'is_gateway_port' => 1,
7100 
              'must_be_hdl_vector' => 1,
7101 
              'period' => 1.0,
7102 
              'port_id' => '0',
7103 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
7104 
              'source_block' => 'USER_LOGIC',
7105 
              'timingConstraint' => 'none',
7106 
              'type' => 'UFix_64_0',
7107 
            },
7108 
            'direction' => 'in',
7109 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7110 
            'width' => 64,
7111 
          },
7112 
          'bram_wr_addr' => {
7113 
            'attributes' => {
7114 
              'bin_pt' => 0,
7115 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
7116 
              'is_floating_block' => 1,
7117 
              'is_gateway_port' => 1,
7118 
              'must_be_hdl_vector' => 1,
7119 
              'period' => 1.0,
7120 
              'port_id' => '16',
7121 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
7122 
              'source_block' => 'USER_LOGIC',
7123 
              'timingConstraint' => 'none',
7124 
              'type' => 'UFix_12_0',
7125 
            },
7126 
            'direction' => 'out',
7127 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7128 
            'width' => 12,
7129 
          },
7130 
          'bram_wr_din' => {
7131 
            'attributes' => {
7132 
              'bin_pt' => 0,
7133 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
7134 
              'is_floating_block' => 1,
7135 
              'is_gateway_port' => 1,
7136 
              'must_be_hdl_vector' => 1,
7137 
              'period' => 1.0,
7138 
              'port_id' => '18',
7139 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
7140 
              'source_block' => 'USER_LOGIC',
7141 
              'timingConstraint' => 'none',
7142 
              'type' => 'UFix_64_0',
7143 
            },
7144 
            'direction' => 'out',
7145 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7146 
            'width' => 64,
7147 
          },
7148 
          'bram_wr_en' => {
7149 
            'attributes' => {
7150 
              'bin_pt' => 0,
7151 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
7152 
              'is_floating_block' => 1,
7153 
              'is_gateway_port' => 1,
7154 
              'must_be_hdl_vector' => 1,
7155 
              'period' => 1.0,
7156 
              'port_id' => '23',
7157 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
7158 
              'source_block' => 'USER_LOGIC',
7159 
              'timingConstraint' => 'none',
7160 
              'type' => 'UFix_8_0',
7161 
            },
7162 
            'direction' => 'out',
7163 
            'hdlType' => 'std_logic_vector(7 downto 0)',
7164 
            'width' => 8,
7165 
          },
7166 
          'ce_1' => {
7167 
            'attributes' => {
7168 
              'domain' => '',
7169 
              'group' => 1,
7170 
              'isCe' => 1,
7171 
              'is_subsys_port' => 1,
7172 
              'period' => 1.0,
7173 
              'subsys_port_index' => '0',
7174 
              'type' => 'logic',
7175 
            },
7176 
            'direction' => 'in',
7177 
            'hdlType' => 'std_logic',
7178 
            'width' => 1,
7179 
          },
7180 
          'clk_1' => {
7181 
            'attributes' => {
7182 
              'domain' => '',
7183 
              'group' => 1,
7184 
              'isClk' => 1,
7185 
              'is_subsys_port' => 1,
7186 
              'period' => 1.0,
7187 
              'subsys_port_index' => '0',
7188 
              'type' => 'logic',
7189 
            },
7190 
            'direction' => 'in',
7191 
            'hdlType' => 'std_logic',
7192 
            'width' => 1,
7193 
          },
7194 
          'data_in' => {
7195 
            'attributes' => {
7196 
              'bin_pt' => 0,
7197 
              'is_floating_block' => 1,
7198 
              'must_be_hdl_vector' => 1,
7199 
              'period' => 1.0,
7200 
              'port_id' => '17',
7201 
              'simulinkName' => 'USER_LOGIC/tx_en_in2',
7202 
              'type' => 'UFix_32_0',
7203 
            },
7204 
            'direction' => 'out',
7205 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7206 
            'width' => 32,
7207 
          },
7208 
          'data_in_x0' => {
7209 
            'attributes' => {
7210 
              'bin_pt' => 0,
7211 
              'is_floating_block' => 1,
7212 
              'must_be_hdl_vector' => 1,
7213 
              'period' => 1.0,
7214 
              'port_id' => '1',
7215 
              'simulinkName' => 'USER_LOGIC/tx_en_in1',
7216 
              'type' => 'Bool',
7217 
            },
7218 
            'direction' => 'out',
7219 
            'hdlType' => 'std_logic',
7220 
            'width' => 1,
7221 
          },
7222 
          'data_in_x1' => {
7223 
            'attributes' => {
7224 
              'bin_pt' => 0,
7225 
              'is_floating_block' => 1,
7226 
              'must_be_hdl_vector' => 1,
7227 
              'period' => 1.0,
7228 
              'port_id' => '36',
7229 
              'simulinkName' => 'USER_LOGIC/tx_en_in96',
7230 
              'type' => 'Bool',
7231 
            },
7232 
            'direction' => 'out',
7233 
            'hdlType' => 'std_logic',
7234 
            'width' => 1,
7235 
          },
7236 
          'data_in_x10' => {
7237 
            'attributes' => {
7238 
              'bin_pt' => 0,
7239 
              'is_floating_block' => 1,
7240 
              'must_be_hdl_vector' => 1,
7241 
              'period' => 1.0,
7242 
              'port_id' => '33',
7243 
              'simulinkName' => 'USER_LOGIC/tx_en_in91',
7244 
              'type' => 'UFix_32_0',
7245 
            },
7246 
            'direction' => 'out',
7247 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7248 
            'width' => 32,
7249 
          },
7250 
          'data_in_x11' => {
7251 
            'attributes' => {
7252 
              'bin_pt' => 0,
7253 
              'is_floating_block' => 1,
7254 
              'must_be_hdl_vector' => 1,
7255 
              'period' => 1.0,
7256 
              'port_id' => '21',
7257 
              'simulinkName' => 'USER_LOGIC/tx_en_in33',
7258 
              'type' => 'UFix_32_0',
7259 
            },
7260 
            'direction' => 'out',
7261 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7262 
            'width' => 32,
7263 
          },
7264 
          'data_in_x12' => {
7265 
            'attributes' => {
7266 
              'bin_pt' => 0,
7267 
              'is_floating_block' => 1,
7268 
              'must_be_hdl_vector' => 1,
7269 
              'period' => 1.0,
7270 
              'port_id' => '6',
7271 
              'simulinkName' => 'USER_LOGIC/tx_en_in113',
7272 
              'type' => 'Bool',
7273 
            },
7274 
            'direction' => 'out',
7275 
            'hdlType' => 'std_logic',
7276 
            'width' => 1,
7277 
          },
7278 
          'data_in_x13' => {
7279 
            'attributes' => {
7280 
              'bin_pt' => 0,
7281 
              'is_floating_block' => 1,
7282 
              'must_be_hdl_vector' => 1,
7283 
              'period' => 1.0,
7284 
              'port_id' => '8',
7285 
              'simulinkName' => 'USER_LOGIC/tx_en_in115',
7286 
              'type' => 'UFix_32_0',
7287 
            },
7288 
            'direction' => 'out',
7289 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7290 
            'width' => 32,
7291 
          },
7292 
          'data_in_x14' => {
7293 
            'attributes' => {
7294 
              'bin_pt' => 0,
7295 
              'is_floating_block' => 1,
7296 
              'must_be_hdl_vector' => 1,
7297 
              'period' => 1.0,
7298 
              'port_id' => '7',
7299 
              'simulinkName' => 'USER_LOGIC/tx_en_in114',
7300 
              'type' => 'Bool',
7301 
            },
7302 
            'direction' => 'out',
7303 
            'hdlType' => 'std_logic',
7304 
            'width' => 1,
7305 
          },
7306 
          'data_in_x15' => {
7307 
            'attributes' => {
7308 
              'bin_pt' => 0,
7309 
              'is_floating_block' => 1,
7310 
              'must_be_hdl_vector' => 1,
7311 
              'period' => 1.0,
7312 
              'port_id' => '9',
7313 
              'simulinkName' => 'USER_LOGIC/tx_en_in118',
7314 
              'type' => 'UFix_32_0',
7315 
            },
7316 
            'direction' => 'out',
7317 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7318 
            'width' => 32,
7319 
          },
7320 
          'data_in_x16' => {
7321 
            'attributes' => {
7322 
              'bin_pt' => 0,
7323 
              'is_floating_block' => 1,
7324 
              'must_be_hdl_vector' => 1,
7325 
              'period' => 1.0,
7326 
              'port_id' => '10',
7327 
              'simulinkName' => 'USER_LOGIC/tx_en_in121',
7328 
              'type' => 'Bool',
7329 
            },
7330 
            'direction' => 'out',
7331 
            'hdlType' => 'std_logic',
7332 
            'width' => 1,
7333 
          },
7334 
          'data_in_x17' => {
7335 
            'attributes' => {
7336 
              'bin_pt' => 0,
7337 
              'is_floating_block' => 1,
7338 
              'must_be_hdl_vector' => 1,
7339 
              'period' => 1.0,
7340 
              'port_id' => '11',
7341 
              'simulinkName' => 'USER_LOGIC/tx_en_in122',
7342 
              'type' => 'UFix_32_0',
7343 
            },
7344 
            'direction' => 'out',
7345 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7346 
            'width' => 32,
7347 
          },
7348 
          'data_in_x18' => {
7349 
            'attributes' => {
7350 
              'bin_pt' => 0,
7351 
              'is_floating_block' => 1,
7352 
              'must_be_hdl_vector' => 1,
7353 
              'period' => 1.0,
7354 
              'port_id' => '12',
7355 
              'simulinkName' => 'USER_LOGIC/tx_en_in125',
7356 
              'type' => 'Bool',
7357 
            },
7358 
            'direction' => 'out',
7359 
            'hdlType' => 'std_logic',
7360 
            'width' => 1,
7361 
          },
7362 
          'data_in_x19' => {
7363 
            'attributes' => {
7364 
              'bin_pt' => 0,
7365 
              'is_floating_block' => 1,
7366 
              'must_be_hdl_vector' => 1,
7367 
              'period' => 1.0,
7368 
              'port_id' => '13',
7369 
              'simulinkName' => 'USER_LOGIC/tx_en_in126',
7370 
              'type' => 'UFix_32_0',
7371 
            },
7372 
            'direction' => 'out',
7373 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7374 
            'width' => 32,
7375 
          },
7376 
          'data_in_x2' => {
7377 
            'attributes' => {
7378 
              'bin_pt' => 0,
7379 
              'is_floating_block' => 1,
7380 
              'must_be_hdl_vector' => 1,
7381 
              'period' => 1.0,
7382 
              'port_id' => '37',
7383 
              'simulinkName' => 'USER_LOGIC/tx_en_in97',
7384 
              'type' => 'Bool',
7385 
            },
7386 
            'direction' => 'out',
7387 
            'hdlType' => 'std_logic',
7388 
            'width' => 1,
7389 
          },
7390 
          'data_in_x20' => {
7391 
            'attributes' => {
7392 
              'bin_pt' => 0,
7393 
              'is_floating_block' => 1,
7394 
              'must_be_hdl_vector' => 1,
7395 
              'period' => 1.0,
7396 
              'port_id' => '2',
7397 
              'simulinkName' => 'USER_LOGIC/tx_en_in10',
7398 
              'type' => 'UFix_32_0',
7399 
            },
7400 
            'direction' => 'out',
7401 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7402 
            'width' => 32,
7403 
          },
7404 
          'data_in_x21' => {
7405 
            'attributes' => {
7406 
              'bin_pt' => 0,
7407 
              'is_floating_block' => 1,
7408 
              'must_be_hdl_vector' => 1,
7409 
              'period' => 1.0,
7410 
              'port_id' => '34',
7411 
              'simulinkName' => 'USER_LOGIC/tx_en_in94',
7412 
              'type' => 'Bool',
7413 
            },
7414 
            'direction' => 'out',
7415 
            'hdlType' => 'std_logic',
7416 
            'width' => 1,
7417 
          },
7418 
          'data_in_x22' => {
7419 
            'attributes' => {
7420 
              'bin_pt' => 0,
7421 
              'is_floating_block' => 1,
7422 
              'must_be_hdl_vector' => 1,
7423 
              'period' => 1.0,
7424 
              'port_id' => '29',
7425 
              'simulinkName' => 'USER_LOGIC/tx_en_in7',
7426 
              'type' => 'Bool',
7427 
            },
7428 
            'direction' => 'out',
7429 
            'hdlType' => 'std_logic',
7430 
            'width' => 1,
7431 
          },
7432 
          'data_in_x23' => {
7433 
            'attributes' => {
7434 
              'bin_pt' => 0,
7435 
              'is_floating_block' => 1,
7436 
              'must_be_hdl_vector' => 1,
7437 
              'period' => 1.0,
7438 
              'port_id' => '24',
7439 
              'simulinkName' => 'USER_LOGIC/tx_en_in50',
7440 
              'type' => 'UFix_32_0',
7441 
            },
7442 
            'direction' => 'out',
7443 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7444 
            'width' => 32,
7445 
          },
7446 
          'data_in_x24' => {
7447 
            'attributes' => {
7448 
              'bin_pt' => 0,
7449 
              'is_floating_block' => 1,
7450 
              'must_be_hdl_vector' => 1,
7451 
              'period' => 1.0,
7452 
              'port_id' => '35',
7453 
              'simulinkName' => 'USER_LOGIC/tx_en_in95',
7454 
              'type' => 'Bool',
7455 
            },
7456 
            'direction' => 'out',
7457 
            'hdlType' => 'std_logic',
7458 
            'width' => 1,
7459 
          },
7460 
          'data_in_x25' => {
7461 
            'attributes' => {
7462 
              'bin_pt' => 0,
7463 
              'is_floating_block' => 1,
7464 
              'must_be_hdl_vector' => 1,
7465 
              'period' => 1.0,
7466 
              'port_id' => '26',
7467 
              'simulinkName' => 'USER_LOGIC/tx_en_in53',
7468 
              'type' => 'UFix_32_0',
7469 
            },
7470 
            'direction' => 'out',
7471 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7472 
            'width' => 32,
7473 
          },
7474 
          'data_in_x26' => {
7475 
            'attributes' => {
7476 
              'bin_pt' => 0,
7477 
              'is_floating_block' => 1,
7478 
              'must_be_hdl_vector' => 1,
7479 
              'period' => 1.0,
7480 
              'port_id' => '27',
7481 
              'simulinkName' => 'USER_LOGIC/tx_en_in54',
7482 
              'type' => 'UFix_32_0',
7483 
            },
7484 
            'direction' => 'out',
7485 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7486 
            'width' => 32,
7487 
          },
7488 
          'data_in_x3' => {
7489 
            'attributes' => {
7490 
              'bin_pt' => 0,
7491 
              'is_floating_block' => 1,
7492 
              'must_be_hdl_vector' => 1,
7493 
              'period' => 1.0,
7494 
              'port_id' => '14',
7495 
              'simulinkName' => 'USER_LOGIC/tx_en_in13',
7496 
              'type' => 'Bool',
7497 
            },
7498 
            'direction' => 'out',
7499 
            'hdlType' => 'std_logic',
7500 
            'width' => 1,
7501 
          },
7502 
          'data_in_x4' => {
7503 
            'attributes' => {
7504 
              'bin_pt' => 0,
7505 
              'is_floating_block' => 1,
7506 
              'must_be_hdl_vector' => 1,
7507 
              'period' => 1.0,
7508 
              'port_id' => '28',
7509 
              'simulinkName' => 'USER_LOGIC/tx_en_in66',
7510 
              'type' => 'UFix_32_0',
7511 
            },
7512 
            'direction' => 'out',
7513 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7514 
            'width' => 32,
7515 
          },
7516 
          'data_in_x5' => {
7517 
            'attributes' => {
7518 
              'bin_pt' => 0,
7519 
              'is_floating_block' => 1,
7520 
              'must_be_hdl_vector' => 1,
7521 
              'period' => 1.0,
7522 
              'port_id' => '38',
7523 
              'simulinkName' => 'USER_LOGIC/tx_en_in98',
7524 
              'type' => 'Bool',
7525 
            },
7526 
            'direction' => 'out',
7527 
            'hdlType' => 'std_logic',
7528 
            'width' => 1,
7529 
          },
7530 
          'data_in_x6' => {
7531 
            'attributes' => {
7532 
              'bin_pt' => 0,
7533 
              'is_floating_block' => 1,
7534 
              'must_be_hdl_vector' => 1,
7535 
              'period' => 1.0,
7536 
              'port_id' => '31',
7537 
              'simulinkName' => 'USER_LOGIC/tx_en_in85',
7538 
              'type' => 'UFix_32_0',
7539 
            },
7540 
            'direction' => 'out',
7541 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7542 
            'width' => 32,
7543 
          },
7544 
          'data_in_x7' => {
7545 
            'attributes' => {
7546 
              'bin_pt' => 0,
7547 
              'is_floating_block' => 1,
7548 
              'must_be_hdl_vector' => 1,
7549 
              'period' => 1.0,
7550 
              'port_id' => '39',
7551 
              'simulinkName' => 'USER_LOGIC/tx_en_in99',
7552 
              'type' => 'Bool',
7553 
            },
7554 
            'direction' => 'out',
7555 
            'hdlType' => 'std_logic',
7556 
            'width' => 1,
7557 
          },
7558 
          'data_in_x8' => {
7559 
            'attributes' => {
7560 
              'bin_pt' => 0,
7561 
              'is_floating_block' => 1,
7562 
              'must_be_hdl_vector' => 1,
7563 
              'period' => 1.0,
7564 
              'port_id' => '32',
7565 
              'simulinkName' => 'USER_LOGIC/tx_en_in88',
7566 
              'type' => 'UFix_32_0',
7567 
            },
7568 
            'direction' => 'out',
7569 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7570 
            'width' => 32,
7571 
          },
7572 
          'data_in_x9' => {
7573 
            'attributes' => {
7574 
              'bin_pt' => 0,
7575 
              'is_floating_block' => 1,
7576 
              'must_be_hdl_vector' => 1,
7577 
              'period' => 1.0,
7578 
              'port_id' => '3',
7579 
              'simulinkName' => 'USER_LOGIC/tx_en_in100',
7580 
              'type' => 'Bool',
7581 
            },
7582 
            'direction' => 'out',
7583 
            'hdlType' => 'std_logic',
7584 
            'width' => 1,
7585 
          },
7586 
          'data_out' => {
7587 
            'attributes' => {
7588 
              'bin_pt' => 0,
7589 
              'is_floating_block' => 1,
7590 
              'must_be_hdl_vector' => 1,
7591 
              'period' => 1.0,
7592 
              'port_id' => '4',
7593 
              'simulinkName' => 'USER_LOGIC/From Register10',
7594 
              'type' => 'UFix_1_0',
7595 
            },
7596 
            'direction' => 'in',
7597 
            'hdlType' => 'std_logic',
7598 
            'width' => 1,
7599 
          },
7600 
          'data_out_x0' => {
7601 
            'attributes' => {
7602 
              'bin_pt' => 0,
7603 
              'is_floating_block' => 1,
7604 
              'must_be_hdl_vector' => 1,
7605 
              'period' => 1.0,
7606 
              'port_id' => '5',
7607 
              'simulinkName' => 'USER_LOGIC/From Register11',
7608 
              'type' => 'UFix_32_0',
7609 
            },
7610 
            'direction' => 'in',
7611 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7612 
            'width' => 32,
7613 
          },
7614 
          'data_out_x1' => {
7615 
            'attributes' => {
7616 
              'bin_pt' => 0,
7617 
              'is_floating_block' => 1,
7618 
              'must_be_hdl_vector' => 1,
7619 
              'period' => 1.0,
7620 
              'port_id' => '6',
7621 
              'simulinkName' => 'USER_LOGIC/From Register12',
7622 
              'type' => 'UFix_1_0',
7623 
            },
7624 
            'direction' => 'in',
7625 
            'hdlType' => 'std_logic',
7626 
            'width' => 1,
7627 
          },
7628 
          'data_out_x10' => {
7629 
            'attributes' => {
7630 
              'bin_pt' => 0,
7631 
              'is_floating_block' => 1,
7632 
              'must_be_hdl_vector' => 1,
7633 
              'period' => 1.0,
7634 
              'port_id' => '13',
7635 
              'simulinkName' => 'USER_LOGIC/From Register22',
7636 
              'type' => 'UFix_32_0',
7637 
            },
7638 
            'direction' => 'in',
7639 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7640 
            'width' => 32,
7641 
          },
7642 
          'data_out_x11' => {
7643 
            'attributes' => {
7644 
              'bin_pt' => 0,
7645 
              'is_floating_block' => 1,
7646 
              'must_be_hdl_vector' => 1,
7647 
              'period' => 1.0,
7648 
              'port_id' => '14',
7649 
              'simulinkName' => 'USER_LOGIC/From Register23',
7650 
              'type' => 'UFix_1_0',
7651 
            },
7652 
            'direction' => 'in',
7653 
            'hdlType' => 'std_logic',
7654 
            'width' => 1,
7655 
          },
7656 
          'data_out_x12' => {
7657 
            'attributes' => {
7658 
              'bin_pt' => 0,
7659 
              'is_floating_block' => 1,
7660 
              'must_be_hdl_vector' => 1,
7661 
              'period' => 1.0,
7662 
              'port_id' => '15',
7663 
              'simulinkName' => 'USER_LOGIC/From Register24',
7664 
              'type' => 'UFix_32_0',
7665 
            },
7666 
            'direction' => 'in',
7667 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7668 
            'width' => 32,
7669 
          },
7670 
          'data_out_x13' => {
7671 
            'attributes' => {
7672 
              'bin_pt' => 0,
7673 
              'is_floating_block' => 1,
7674 
              'must_be_hdl_vector' => 1,
7675 
              'period' => 1.0,
7676 
              'port_id' => '16',
7677 
              'simulinkName' => 'USER_LOGIC/From Register25',
7678 
              'type' => 'UFix_1_0',
7679 
            },
7680 
            'direction' => 'in',
7681 
            'hdlType' => 'std_logic',
7682 
            'width' => 1,
7683 
          },
7684 
          'data_out_x14' => {
7685 
            'attributes' => {
7686 
              'bin_pt' => 0,
7687 
              'is_floating_block' => 1,
7688 
              'must_be_hdl_vector' => 1,
7689 
              'period' => 1.0,
7690 
              'port_id' => '17',
7691 
              'simulinkName' => 'USER_LOGIC/From Register26',
7692 
              'type' => 'UFix_32_0',
7693 
            },
7694 
            'direction' => 'in',
7695 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7696 
            'width' => 32,
7697 
          },
7698 
          'data_out_x15' => {
7699 
            'attributes' => {
7700 
              'bin_pt' => 0,
7701 
              'is_floating_block' => 1,
7702 
              'must_be_hdl_vector' => 1,
7703 
              'period' => 1.0,
7704 
              'port_id' => '18',
7705 
              'simulinkName' => 'USER_LOGIC/From Register27',
7706 
              'type' => 'UFix_1_0',
7707 
            },
7708 
            'direction' => 'in',
7709 
            'hdlType' => 'std_logic',
7710 
            'width' => 1,
7711 
          },
7712 
          'data_out_x16' => {
7713 
            'attributes' => {
7714 
              'bin_pt' => 0,
7715 
              'is_floating_block' => 1,
7716 
              'must_be_hdl_vector' => 1,
7717 
              'period' => 1.0,
7718 
              'port_id' => '19',
7719 
              'simulinkName' => 'USER_LOGIC/From Register28',
7720 
              'type' => 'UFix_32_0',
7721 
            },
7722 
            'direction' => 'in',
7723 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7724 
            'width' => 32,
7725 
          },
7726 
          'data_out_x17' => {
7727 
            'attributes' => {
7728 
              'bin_pt' => 0,
7729 
              'is_floating_block' => 1,
7730 
              'must_be_hdl_vector' => 1,
7731 
              'period' => 1.0,
7732 
              'port_id' => '20',
7733 
              'simulinkName' => 'USER_LOGIC/From Register29',
7734 
              'type' => 'UFix_1_0',
7735 
            },
7736 
            'direction' => 'in',
7737 
            'hdlType' => 'std_logic',
7738 
            'width' => 1,
7739 
          },
7740 
          'data_out_x18' => {
7741 
            'attributes' => {
7742 
              'bin_pt' => 0,
7743 
              'is_floating_block' => 1,
7744 
              'must_be_hdl_vector' => 1,
7745 
              'period' => 1.0,
7746 
              'port_id' => '21',
7747 
              'simulinkName' => 'USER_LOGIC/From Register3',
7748 
              'type' => 'UFix_32_0',
7749 
            },
7750 
            'direction' => 'in',
7751 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7752 
            'width' => 32,
7753 
          },
7754 
          'data_out_x19' => {
7755 
            'attributes' => {
7756 
              'bin_pt' => 0,
7757 
              'is_floating_block' => 1,
7758 
              'must_be_hdl_vector' => 1,
7759 
              'period' => 1.0,
7760 
              'port_id' => '22',
7761 
              'simulinkName' => 'USER_LOGIC/From Register30',
7762 
              'type' => 'UFix_32_0',
7763 
            },
7764 
            'direction' => 'in',
7765 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7766 
            'width' => 32,
7767 
          },
7768 
          'data_out_x2' => {
7769 
            'attributes' => {
7770 
              'bin_pt' => 0,
7771 
              'is_floating_block' => 1,
7772 
              'must_be_hdl_vector' => 1,
7773 
              'period' => 1.0,
7774 
              'port_id' => '7',
7775 
              'simulinkName' => 'USER_LOGIC/From Register13',
7776 
              'type' => 'UFix_32_0',
7777 
            },
7778 
            'direction' => 'in',
7779 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7780 
            'width' => 32,
7781 
          },
7782 
          'data_out_x20' => {
7783 
            'attributes' => {
7784 
              'bin_pt' => 0,
7785 
              'is_floating_block' => 1,
7786 
              'must_be_hdl_vector' => 1,
7787 
              'period' => 1.0,
7788 
              'port_id' => '23',
7789 
              'simulinkName' => 'USER_LOGIC/From Register31',
7790 
              'type' => 'UFix_1_0',
7791 
            },
7792 
            'direction' => 'in',
7793 
            'hdlType' => 'std_logic',
7794 
            'width' => 1,
7795 
          },
7796 
          'data_out_x21' => {
7797 
            'attributes' => {
7798 
              'bin_pt' => 0,
7799 
              'is_floating_block' => 1,
7800 
              'must_be_hdl_vector' => 1,
7801 
              'period' => 1.0,
7802 
              'port_id' => '24',
7803 
              'simulinkName' => 'USER_LOGIC/From Register32',
7804 
              'type' => 'UFix_32_0',
7805 
            },
7806 
            'direction' => 'in',
7807 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7808 
            'width' => 32,
7809 
          },
7810 
          'data_out_x22' => {
7811 
            'attributes' => {
7812 
              'bin_pt' => 0,
7813 
              'is_floating_block' => 1,
7814 
              'must_be_hdl_vector' => 1,
7815 
              'period' => 1.0,
7816 
              'port_id' => '25',
7817 
              'simulinkName' => 'USER_LOGIC/From Register33',
7818 
              'type' => 'UFix_1_0',
7819 
            },
7820 
            'direction' => 'in',
7821 
            'hdlType' => 'std_logic',
7822 
            'width' => 1,
7823 
          },
7824 
          'data_out_x23' => {
7825 
            'attributes' => {
7826 
              'bin_pt' => 0,
7827 
              'is_floating_block' => 1,
7828 
              'must_be_hdl_vector' => 1,
7829 
              'period' => 1.0,
7830 
              'port_id' => '26',
7831 
              'simulinkName' => 'USER_LOGIC/From Register4',
7832 
              'type' => 'UFix_1_0',
7833 
            },
7834 
            'direction' => 'in',
7835 
            'hdlType' => 'std_logic',
7836 
            'width' => 1,
7837 
          },
7838 
          'data_out_x24' => {
7839 
            'attributes' => {
7840 
              'bin_pt' => 0,
7841 
              'is_floating_block' => 1,
7842 
              'must_be_hdl_vector' => 1,
7843 
              'period' => 1.0,
7844 
              'port_id' => '27',
7845 
              'simulinkName' => 'USER_LOGIC/From Register5',
7846 
              'type' => 'UFix_32_0',
7847 
            },
7848 
            'direction' => 'in',
7849 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7850 
            'width' => 32,
7851 
          },
7852 
          'data_out_x25' => {
7853 
            'attributes' => {
7854 
              'bin_pt' => 0,
7855 
              'is_floating_block' => 1,
7856 
              'must_be_hdl_vector' => 1,
7857 
              'period' => 1.0,
7858 
              'port_id' => '28',
7859 
              'simulinkName' => 'USER_LOGIC/From Register6',
7860 
              'type' => 'UFix_1_0',
7861 
            },
7862 
            'direction' => 'in',
7863 
            'hdlType' => 'std_logic',
7864 
            'width' => 1,
7865 
          },
7866 
          'data_out_x26' => {
7867 
            'attributes' => {
7868 
              'bin_pt' => 0,
7869 
              'is_floating_block' => 1,
7870 
              'must_be_hdl_vector' => 1,
7871 
              'period' => 1.0,
7872 
              'port_id' => '29',
7873 
              'simulinkName' => 'USER_LOGIC/From Register7',
7874 
              'type' => 'UFix_32_0',
7875 
            },
7876 
            'direction' => 'in',
7877 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7878 
            'width' => 32,
7879 
          },
7880 
          'data_out_x27' => {
7881 
            'attributes' => {
7882 
              'bin_pt' => 0,
7883 
              'is_floating_block' => 1,
7884 
              'must_be_hdl_vector' => 1,
7885 
              'period' => 1.0,
7886 
              'port_id' => '30',
7887 
              'simulinkName' => 'USER_LOGIC/From Register8',
7888 
              'type' => 'UFix_1_0',
7889 
            },
7890 
            'direction' => 'in',
7891 
            'hdlType' => 'std_logic',
7892 
            'width' => 1,
7893 
          },
7894 
          'data_out_x28' => {
7895 
            'attributes' => {
7896 
              'bin_pt' => 0,
7897 
              'is_floating_block' => 1,
7898 
              'must_be_hdl_vector' => 1,
7899 
              'period' => 1.0,
7900 
              'port_id' => '31',
7901 
              'simulinkName' => 'USER_LOGIC/From Register9',
7902 
              'type' => 'UFix_32_0',
7903 
            },
7904 
            'direction' => 'in',
7905 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7906 
            'width' => 32,
7907 
          },
7908 
          'data_out_x3' => {
7909 
            'attributes' => {
7910 
              'bin_pt' => 0,
7911 
              'is_floating_block' => 1,
7912 
              'must_be_hdl_vector' => 1,
7913 
              'period' => 1.0,
7914 
              'port_id' => '8',
7915 
              'simulinkName' => 'USER_LOGIC/From Register14',
7916 
              'type' => 'UFix_1_0',
7917 
            },
7918 
            'direction' => 'in',
7919 
            'hdlType' => 'std_logic',
7920 
            'width' => 1,
7921 
          },
7922 
          'data_out_x6' => {
7923 
            'attributes' => {
7924 
              'bin_pt' => 0,
7925 
              'is_floating_block' => 1,
7926 
              'must_be_hdl_vector' => 1,
7927 
              'period' => 1.0,
7928 
              'port_id' => '9',
7929 
              'simulinkName' => 'USER_LOGIC/From Register17',
7930 
              'type' => 'UFix_32_0',
7931 
            },
7932 
            'direction' => 'in',
7933 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7934 
            'width' => 32,
7935 
          },
7936 
          'data_out_x7' => {
7937 
            'attributes' => {
7938 
              'bin_pt' => 0,
7939 
              'is_floating_block' => 1,
7940 
              'must_be_hdl_vector' => 1,
7941 
              'period' => 1.0,
7942 
              'port_id' => '10',
7943 
              'simulinkName' => 'USER_LOGIC/From Register18',
7944 
              'type' => 'UFix_1_0',
7945 
            },
7946 
            'direction' => 'in',
7947 
            'hdlType' => 'std_logic',
7948 
            'width' => 1,
7949 
          },
7950 
          'data_out_x8' => {
7951 
            'attributes' => {
7952 
              'bin_pt' => 0,
7953 
              'is_floating_block' => 1,
7954 
              'must_be_hdl_vector' => 1,
7955 
              'period' => 1.0,
7956 
              'port_id' => '11',
7957 
              'simulinkName' => 'USER_LOGIC/From Register20',
7958 
              'type' => 'UFix_32_0',
7959 
            },
7960 
            'direction' => 'in',
7961 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7962 
            'width' => 32,
7963 
          },
7964 
          'data_out_x9' => {
7965 
            'attributes' => {
7966 
              'bin_pt' => 0,
7967 
              'is_floating_block' => 1,
7968 
              'must_be_hdl_vector' => 1,
7969 
              'period' => 1.0,
7970 
              'port_id' => '12',
7971 
              'simulinkName' => 'USER_LOGIC/From Register21',
7972 
              'type' => 'UFix_1_0',
7973 
            },
7974 
            'direction' => 'in',
7975 
            'hdlType' => 'std_logic',
7976 
            'width' => 1,
7977 
          },
7978 
          'en' => {
7979 
            'attributes' => {
7980 
              'bin_pt' => 0,
7981 
              'is_floating_block' => 1,
7982 
              'must_be_hdl_vector' => 1,
7983 
              'period' => 1.0,
7984 
              'port_id' => '0',
7985 
              'simulinkName' => 'USER_LOGIC/en',
7986 
              'type' => 'Bool',
7987 
            },
7988 
            'direction' => 'out',
7989 
            'hdlType' => 'std_logic',
7990 
            'width' => 1,
7991 
          },
7992 
          'en_x0' => {
7993 
            'attributes' => {
7994 
              'bin_pt' => 0,
7995 
              'is_floating_block' => 1,
7996 
              'must_be_hdl_vector' => 1,
7997 
              'period' => 1.0,
7998 
              'port_id' => '0',
7999 
              'simulinkName' => 'USER_LOGIC/en',
8000 
              'type' => 'Bool',
8001 
            },
8002 
            'direction' => 'out',
8003 
            'hdlType' => 'std_logic',
8004 
            'width' => 1,
8005 
          },
8006 
          'en_x1' => {
8007 
            'attributes' => {
8008 
              'bin_pt' => 0,
8009 
              'is_floating_block' => 1,
8010 
              'must_be_hdl_vector' => 1,
8011 
              'period' => 1.0,
8012 
              'port_id' => '0',
8013 
              'simulinkName' => 'USER_LOGIC/en',
8014 
              'type' => 'Bool',
8015 
            },
8016 
            'direction' => 'out',
8017 
            'hdlType' => 'std_logic',
8018 
            'width' => 1,
8019 
          },
8020 
          'en_x10' => {
8021 
            'attributes' => {
8022 
              'bin_pt' => 0,
8023 
              'is_floating_block' => 1,
8024 
              'must_be_hdl_vector' => 1,
8025 
              'period' => 1.0,
8026 
              'port_id' => '0',
8027 
              'simulinkName' => 'USER_LOGIC/en',
8028 
              'type' => 'Bool',
8029 
            },
8030 
            'direction' => 'out',
8031 
            'hdlType' => 'std_logic',
8032 
            'width' => 1,
8033 
          },
8034 
          'en_x11' => {
8035 
            'attributes' => {
8036 
              'bin_pt' => 0,
8037 
              'is_floating_block' => 1,
8038 
              'must_be_hdl_vector' => 1,
8039 
              'period' => 1.0,
8040 
              'port_id' => '0',
8041 
              'simulinkName' => 'USER_LOGIC/en',
8042 
              'type' => 'Bool',
8043 
            },
8044 
            'direction' => 'out',
8045 
            'hdlType' => 'std_logic',
8046 
            'width' => 1,
8047 
          },
8048 
          'en_x12' => {
8049 
            'attributes' => {
8050 
              'bin_pt' => 0,
8051 
              'is_floating_block' => 1,
8052 
              'must_be_hdl_vector' => 1,
8053 
              'period' => 1.0,
8054 
              'port_id' => '0',
8055 
              'simulinkName' => 'USER_LOGIC/en',
8056 
              'type' => 'Bool',
8057 
            },
8058 
            'direction' => 'out',
8059 
            'hdlType' => 'std_logic',
8060 
            'width' => 1,
8061 
          },
8062 
          'en_x13' => {
8063 
            'attributes' => {
8064 
              'bin_pt' => 0,
8065 
              'is_floating_block' => 1,
8066 
              'must_be_hdl_vector' => 1,
8067 
              'period' => 1.0,
8068 
              'port_id' => '0',
8069 
              'simulinkName' => 'USER_LOGIC/en',
8070 
              'type' => 'Bool',
8071 
            },
8072 
            'direction' => 'out',
8073 
            'hdlType' => 'std_logic',
8074 
            'width' => 1,
8075 
          },
8076 
          'en_x14' => {
8077 
            'attributes' => {
8078 
              'bin_pt' => 0,
8079 
              'is_floating_block' => 1,
8080 
              'must_be_hdl_vector' => 1,
8081 
              'period' => 1.0,
8082 
              'port_id' => '0',
8083 
              'simulinkName' => 'USER_LOGIC/en',
8084 
              'type' => 'Bool',
8085 
            },
8086 
            'direction' => 'out',
8087 
            'hdlType' => 'std_logic',
8088 
            'width' => 1,
8089 
          },
8090 
          'en_x15' => {
8091 
            'attributes' => {
8092 
              'bin_pt' => 0,
8093 
              'is_floating_block' => 1,
8094 
              'must_be_hdl_vector' => 1,
8095 
              'period' => 1.0,
8096 
              'port_id' => '0',
8097 
              'simulinkName' => 'USER_LOGIC/en',
8098 
              'type' => 'Bool',
8099 
            },
8100 
            'direction' => 'out',
8101 
            'hdlType' => 'std_logic',
8102 
            'width' => 1,
8103 
          },
8104 
          'en_x16' => {
8105 
            'attributes' => {
8106 
              'bin_pt' => 0,
8107 
              'is_floating_block' => 1,
8108 
              'must_be_hdl_vector' => 1,
8109 
              'period' => 1.0,
8110 
              'port_id' => '0',
8111 
              'simulinkName' => 'USER_LOGIC/en',
8112 
              'type' => 'Bool',
8113 
            },
8114 
            'direction' => 'out',
8115 
            'hdlType' => 'std_logic',
8116 
            'width' => 1,
8117 
          },
8118 
          'en_x17' => {
8119 
            'attributes' => {
8120 
              'bin_pt' => 0,
8121 
              'is_floating_block' => 1,
8122 
              'must_be_hdl_vector' => 1,
8123 
              'period' => 1.0,
8124 
              'port_id' => '0',
8125 
              'simulinkName' => 'USER_LOGIC/en',
8126 
              'type' => 'Bool',
8127 
            },
8128 
            'direction' => 'out',
8129 
            'hdlType' => 'std_logic',
8130 
            'width' => 1,
8131 
          },
8132 
          'en_x18' => {
8133 
            'attributes' => {
8134 
              'bin_pt' => 0,
8135 
              'is_floating_block' => 1,
8136 
              'must_be_hdl_vector' => 1,
8137 
              'period' => 1.0,
8138 
              'port_id' => '0',
8139 
              'simulinkName' => 'USER_LOGIC/en',
8140 
              'type' => 'Bool',
8141 
            },
8142 
            'direction' => 'out',
8143 
            'hdlType' => 'std_logic',
8144 
            'width' => 1,
8145 
          },
8146 
          'en_x19' => {
8147 
            'attributes' => {
8148 
              'bin_pt' => 0,
8149 
              'is_floating_block' => 1,
8150 
              'must_be_hdl_vector' => 1,
8151 
              'period' => 1.0,
8152 
              'port_id' => '0',
8153 
              'simulinkName' => 'USER_LOGIC/en',
8154 
              'type' => 'Bool',
8155 
            },
8156 
            'direction' => 'out',
8157 
            'hdlType' => 'std_logic',
8158 
            'width' => 1,
8159 
          },
8160 
          'en_x2' => {
8161 
            'attributes' => {
8162 
              'bin_pt' => 0,
8163 
              'is_floating_block' => 1,
8164 
              'must_be_hdl_vector' => 1,
8165 
              'period' => 1.0,
8166 
              'port_id' => '0',
8167 
              'simulinkName' => 'USER_LOGIC/en',
8168 
              'type' => 'Bool',
8169 
            },
8170 
            'direction' => 'out',
8171 
            'hdlType' => 'std_logic',
8172 
            'width' => 1,
8173 
          },
8174 
          'en_x20' => {
8175 
            'attributes' => {
8176 
              'bin_pt' => 0,
8177 
              'is_floating_block' => 1,
8178 
              'must_be_hdl_vector' => 1,
8179 
              'period' => 1.0,
8180 
              'port_id' => '0',
8181 
              'simulinkName' => 'USER_LOGIC/en',
8182 
              'type' => 'Bool',
8183 
            },
8184 
            'direction' => 'out',
8185 
            'hdlType' => 'std_logic',
8186 
            'width' => 1,
8187 
          },
8188 
          'en_x21' => {
8189 
            'attributes' => {
8190 
              'bin_pt' => 0,
8191 
              'is_floating_block' => 1,
8192 
              'must_be_hdl_vector' => 1,
8193 
              'period' => 1.0,
8194 
              'port_id' => '0',
8195 
              'simulinkName' => 'USER_LOGIC/en',
8196 
              'type' => 'Bool',
8197 
            },
8198 
            'direction' => 'out',
8199 
            'hdlType' => 'std_logic',
8200 
            'width' => 1,
8201 
          },
8202 
          'en_x22' => {
8203 
            'attributes' => {
8204 
              'bin_pt' => 0,
8205 
              'is_floating_block' => 1,
8206 
              'must_be_hdl_vector' => 1,
8207 
              'period' => 1.0,
8208 
              'port_id' => '0',
8209 
              'simulinkName' => 'USER_LOGIC/en',
8210 
              'type' => 'Bool',
8211 
            },
8212 
            'direction' => 'out',
8213 
            'hdlType' => 'std_logic',
8214 
            'width' => 1,
8215 
          },
8216 
          'en_x23' => {
8217 
            'attributes' => {
8218 
              'bin_pt' => 0,
8219 
              'is_floating_block' => 1,
8220 
              'must_be_hdl_vector' => 1,
8221 
              'period' => 1.0,
8222 
              'port_id' => '0',
8223 
              'simulinkName' => 'USER_LOGIC/en',
8224 
              'type' => 'Bool',
8225 
            },
8226 
            'direction' => 'out',
8227 
            'hdlType' => 'std_logic',
8228 
            'width' => 1,
8229 
          },
8230 
          'en_x24' => {
8231 
            'attributes' => {
8232 
              'bin_pt' => 0,
8233 
              'is_floating_block' => 1,
8234 
              'must_be_hdl_vector' => 1,
8235 
              'period' => 1.0,
8236 
              'port_id' => '0',
8237 
              'simulinkName' => 'USER_LOGIC/en',
8238 
              'type' => 'Bool',
8239 
            },
8240 
            'direction' => 'out',
8241 
            'hdlType' => 'std_logic',
8242 
            'width' => 1,
8243 
          },
8244 
          'en_x25' => {
8245 
            'attributes' => {
8246 
              'bin_pt' => 0,
8247 
              'is_floating_block' => 1,
8248 
              'must_be_hdl_vector' => 1,
8249 
              'period' => 1.0,
8250 
              'port_id' => '0',
8251 
              'simulinkName' => 'USER_LOGIC/en',
8252 
              'type' => 'Bool',
8253 
            },
8254 
            'direction' => 'out',
8255 
            'hdlType' => 'std_logic',
8256 
            'width' => 1,
8257 
          },
8258 
          'en_x26' => {
8259 
            'attributes' => {
8260 
              'bin_pt' => 0,
8261 
              'is_floating_block' => 1,
8262 
              'must_be_hdl_vector' => 1,
8263 
              'period' => 1.0,
8264 
              'port_id' => '0',
8265 
              'simulinkName' => 'USER_LOGIC/en',
8266 
              'type' => 'Bool',
8267 
            },
8268 
            'direction' => 'out',
8269 
            'hdlType' => 'std_logic',
8270 
            'width' => 1,
8271 
          },
8272 
          'en_x3' => {
8273 
            'attributes' => {
8274 
              'bin_pt' => 0,
8275 
              'is_floating_block' => 1,
8276 
              'must_be_hdl_vector' => 1,
8277 
              'period' => 1.0,
8278 
              'port_id' => '0',
8279 
              'simulinkName' => 'USER_LOGIC/en',
8280 
              'type' => 'Bool',
8281 
            },
8282 
            'direction' => 'out',
8283 
            'hdlType' => 'std_logic',
8284 
            'width' => 1,
8285 
          },
8286 
          'en_x4' => {
8287 
            'attributes' => {
8288 
              'bin_pt' => 0,
8289 
              'is_floating_block' => 1,
8290 
              'must_be_hdl_vector' => 1,
8291 
              'period' => 1.0,
8292 
              'port_id' => '0',
8293 
              'simulinkName' => 'USER_LOGIC/en',
8294 
              'type' => 'Bool',
8295 
            },
8296 
            'direction' => 'out',
8297 
            'hdlType' => 'std_logic',
8298 
            'width' => 1,
8299 
          },
8300 
          'en_x5' => {
8301 
            'attributes' => {
8302 
              'bin_pt' => 0,
8303 
              'is_floating_block' => 1,
8304 
              'must_be_hdl_vector' => 1,
8305 
              'period' => 1.0,
8306 
              'port_id' => '0',
8307 
              'simulinkName' => 'USER_LOGIC/en',
8308 
              'type' => 'Bool',
8309 
            },
8310 
            'direction' => 'out',
8311 
            'hdlType' => 'std_logic',
8312 
            'width' => 1,
8313 
          },
8314 
          'en_x6' => {
8315 
            'attributes' => {
8316 
              'bin_pt' => 0,
8317 
              'is_floating_block' => 1,
8318 
              'must_be_hdl_vector' => 1,
8319 
              'period' => 1.0,
8320 
              'port_id' => '0',
8321 
              'simulinkName' => 'USER_LOGIC/en',
8322 
              'type' => 'Bool',
8323 
            },
8324 
            'direction' => 'out',
8325 
            'hdlType' => 'std_logic',
8326 
            'width' => 1,
8327 
          },
8328 
          'en_x7' => {
8329 
            'attributes' => {
8330 
              'bin_pt' => 0,
8331 
              'is_floating_block' => 1,
8332 
              'must_be_hdl_vector' => 1,
8333 
              'period' => 1.0,
8334 
              'port_id' => '0',
8335 
              'simulinkName' => 'USER_LOGIC/en',
8336 
              'type' => 'Bool',
8337 
            },
8338 
            'direction' => 'out',
8339 
            'hdlType' => 'std_logic',
8340 
            'width' => 1,
8341 
          },
8342 
          'en_x8' => {
8343 
            'attributes' => {
8344 
              'bin_pt' => 0,
8345 
              'is_floating_block' => 1,
8346 
              'must_be_hdl_vector' => 1,
8347 
              'period' => 1.0,
8348 
              'port_id' => '0',
8349 
              'simulinkName' => 'USER_LOGIC/en',
8350 
              'type' => 'Bool',
8351 
            },
8352 
            'direction' => 'out',
8353 
            'hdlType' => 'std_logic',
8354 
            'width' => 1,
8355 
          },
8356 
          'en_x9' => {
8357 
            'attributes' => {
8358 
              'bin_pt' => 0,
8359 
              'is_floating_block' => 1,
8360 
              'must_be_hdl_vector' => 1,
8361 
              'period' => 1.0,
8362 
              'port_id' => '0',
8363 
              'simulinkName' => 'USER_LOGIC/en',
8364 
              'type' => 'Bool',
8365 
            },
8366 
            'direction' => 'out',
8367 
            'hdlType' => 'std_logic',
8368 
            'width' => 1,
8369 
          },
8370 
          'fifo_rd_count' => {
8371 
            'attributes' => {
8372 
              'bin_pt' => 0,
8373 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_count.dat',
8374 
              'is_floating_block' => 1,
8375 
              'is_gateway_port' => 1,
8376 
              'must_be_hdl_vector' => 1,
8377 
              'period' => 1.0,
8378 
              'port_id' => '0',
8379 
              'simulinkName' => 'fifo_rd_count',
8380 
              'source_block' => '',
8381 
              'timingConstraint' => 'none',
8382 
              'type' => 'UFix_15_0',
8383 
            },
8384 
            'direction' => 'in',
8385 
            'hdlType' => 'std_logic_vector(14 downto 0)',
8386 
            'width' => 15,
8387 
          },
8388 
          'fifo_rd_dout' => {
8389 
            'attributes' => {
8390 
              'bin_pt' => 0,
8391 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_dout.dat',
8392 
              'is_floating_block' => 1,
8393 
              'is_gateway_port' => 1,
8394 
              'must_be_hdl_vector' => 1,
8395 
              'period' => 1.0,
8396 
              'port_id' => '1',
8397 
              'simulinkName' => 'USER_LOGIC/FIFO_rd_dout',
8398 
              'source_block' => 'USER_LOGIC',
8399 
              'timingConstraint' => 'none',
8400 
              'type' => 'UFix_72_0',
8401 
            },
8402 
            'direction' => 'in',
8403 
            'hdlType' => 'std_logic_vector(71 downto 0)',
8404 
            'width' => 72,
8405 
          },
8406 
          'fifo_rd_empty' => {
8407 
            'attributes' => {
8408 
              'bin_pt' => 0,
8409 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_empty.dat',
8410 
              'is_floating_block' => 1,
8411 
              'is_gateway_port' => 1,
8412 
              'must_be_hdl_vector' => 1,
8413 
              'period' => 1.0,
8414 
              'port_id' => '2',
8415 
              'simulinkName' => 'USER_LOGIC/FIFO_rd_empty',
8416 
              'source_block' => 'USER_LOGIC',
8417 
              'timingConstraint' => 'none',
8418 
              'type' => 'Bool',
8419 
            },
8420 
            'direction' => 'in',
8421 
            'hdlType' => 'std_logic',
8422 
            'width' => 1,
8423 
          },
8424 
          'fifo_rd_en' => {
8425 
            'attributes' => {
8426 
              'bin_pt' => 0,
8427 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_en.dat',
8428 
              'is_floating_block' => 1,
8429 
              'is_gateway_port' => 1,
8430 
              'must_be_hdl_vector' => 1,
8431 
              'period' => 1.0,
8432 
              'port_id' => '4',
8433 
              'simulinkName' => 'USER_LOGIC/FIFO_rd_en',
8434 
              'source_block' => 'USER_LOGIC',
8435 
              'timingConstraint' => 'none',
8436 
              'type' => 'Bool',
8437 
            },
8438 
            'direction' => 'out',
8439 
            'hdlType' => 'std_logic',
8440 
            'width' => 1,
8441 
          },
8442 
          'fifo_rd_pempty' => {
8443 
            'attributes' => {
8444 
              'bin_pt' => 0,
8445 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_pempty.dat',
8446 
              'is_floating_block' => 1,
8447 
              'is_gateway_port' => 1,
8448 
              'must_be_hdl_vector' => 1,
8449 
              'period' => 1.0,
8450 
              'port_id' => '0',
8451 
              'simulinkName' => 'fifo_rd_pempty',
8452 
              'source_block' => '',
8453 
              'timingConstraint' => 'none',
8454 
              'type' => 'Bool',
8455 
            },
8456 
            'direction' => 'in',
8457 
            'hdlType' => 'std_logic',
8458 
            'width' => 1,
8459 
          },
8460 
          'fifo_rd_valid' => {
8461 
            'attributes' => {
8462 
              'bin_pt' => 0,
8463 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_valid.dat',
8464 
              'is_floating_block' => 1,
8465 
              'is_gateway_port' => 1,
8466 
              'must_be_hdl_vector' => 1,
8467 
              'period' => 1.0,
8468 
              'port_id' => '3',
8469 
              'simulinkName' => 'USER_LOGIC/FIFO_rd_valid',
8470 
              'source_block' => 'USER_LOGIC',
8471 
              'timingConstraint' => 'none',
8472 
              'type' => 'Bool',
8473 
            },
8474 
            'direction' => 'in',
8475 
            'hdlType' => 'std_logic',
8476 
            'width' => 1,
8477 
          },
8478 
          'fifo_wr_count' => {
8479 
            'attributes' => {
8480 
              'bin_pt' => 0,
8481 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_count.dat',
8482 
              'is_floating_block' => 1,
8483 
              'is_gateway_port' => 1,
8484 
              'must_be_hdl_vector' => 1,
8485 
              'period' => 1.0,
8486 
              'port_id' => '0',
8487 
              'simulinkName' => 'fifo_wr_count',
8488 
              'source_block' => '',
8489 
              'timingConstraint' => 'none',
8490 
              'type' => 'UFix_15_0',
8491 
            },
8492 
            'direction' => 'in',
8493 
            'hdlType' => 'std_logic_vector(14 downto 0)',
8494 
            'width' => 15,
8495 
          },
8496 
          'fifo_wr_din' => {
8497 
            'attributes' => {
8498 
              'bin_pt' => 0,
8499 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_din.dat',
8500 
              'is_floating_block' => 1,
8501 
              'is_gateway_port' => 1,
8502 
              'must_be_hdl_vector' => 1,
8503 
              'period' => 1.0,
8504 
              'port_id' => '22',
8505 
              'simulinkName' => 'USER_LOGIC/FIFO_wr_din',
8506 
              'source_block' => 'USER_LOGIC',
8507 
              'timingConstraint' => 'none',
8508 
              'type' => 'UFix_72_0',
8509 
            },
8510 
            'direction' => 'out',
8511 
            'hdlType' => 'std_logic_vector(71 downto 0)',
8512 
            'width' => 72,
8513 
          },
8514 
          'fifo_wr_en' => {
8515 
            'attributes' => {
8516 
              'bin_pt' => 0,
8517 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_en.dat',
8518 
              'is_floating_block' => 1,
8519 
              'is_gateway_port' => 1,
8520 
              'must_be_hdl_vector' => 1,
8521 
              'period' => 1.0,
8522 
              'port_id' => '5',
8523 
              'simulinkName' => 'USER_LOGIC/FIFO_wr_en',
8524 
              'source_block' => 'USER_LOGIC',
8525 
              'timingConstraint' => 'none',
8526 
              'type' => 'Bool',
8527 
            },
8528 
            'direction' => 'out',
8529 
            'hdlType' => 'std_logic',
8530 
            'width' => 1,
8531 
          },
8532 
          'fifo_wr_full' => {
8533 
            'attributes' => {
8534 
              'bin_pt' => 0,
8535 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_full.dat',
8536 
              'is_floating_block' => 1,
8537 
              'is_gateway_port' => 1,
8538 
              'must_be_hdl_vector' => 1,
8539 
              'period' => 1.0,
8540 
              'port_id' => '0',
8541 
              'simulinkName' => 'fifo_wr_full',
8542 
              'source_block' => '',
8543 
              'timingConstraint' => 'none',
8544 
              'type' => 'Bool',
8545 
            },
8546 
            'direction' => 'in',
8547 
            'hdlType' => 'std_logic',
8548 
            'width' => 1,
8549 
          },
8550 
          'fifo_wr_pfull' => {
8551 
            'attributes' => {
8552 
              'bin_pt' => 0,
8553 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_pfull.dat',
8554 
              'is_floating_block' => 1,
8555 
              'is_gateway_port' => 1,
8556 
              'must_be_hdl_vector' => 1,
8557 
              'period' => 1.0,
8558 
              'port_id' => '0',
8559 
              'simulinkName' => 'fifo_wr_pfull',
8560 
              'source_block' => '',
8561 
              'timingConstraint' => 'none',
8562 
              'type' => 'Bool',
8563 
            },
8564 
            'direction' => 'in',
8565 
            'hdlType' => 'std_logic',
8566 
            'width' => 1,
8567 
          },
8568 
          'rst_i' => {
8569 
            'attributes' => {
8570 
              'bin_pt' => 0,
8571 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_i.dat',
8572 
              'is_floating_block' => 1,
8573 
              'is_gateway_port' => 1,
8574 
              'must_be_hdl_vector' => 1,
8575 
              'period' => 1.0,
8576 
              'port_id' => '32',
8577 
              'simulinkName' => 'USER_LOGIC/rst_i',
8578 
              'source_block' => 'USER_LOGIC',
8579 
              'timingConstraint' => 'none',
8580 
              'type' => 'Bool',
8581 
            },
8582 
            'direction' => 'in',
8583 
            'hdlType' => 'std_logic',
8584 
            'width' => 1,
8585 
          },
8586 
          'rst_o' => {
8587 
            'attributes' => {
8588 
              'bin_pt' => 0,
8589 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
8590 
              'is_floating_block' => 1,
8591 
              'is_gateway_port' => 1,
8592 
              'must_be_hdl_vector' => 1,
8593 
              'period' => 1.0,
8594 
              'port_id' => '19',
8595 
              'simulinkName' => 'USER_LOGIC/rst_o',
8596 
              'source_block' => 'USER_LOGIC',
8597 
              'timingConstraint' => 'none',
8598 
              'type' => 'Bool',
8599 
            },
8600 
            'direction' => 'out',
8601 
            'hdlType' => 'std_logic',
8602 
            'width' => 1,
8603 
          },
8604 
          'user_int_1o' => {
8605 
            'attributes' => {
8606 
              'bin_pt' => 0,
8607 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
8608 
              'is_floating_block' => 1,
8609 
              'is_gateway_port' => 1,
8610 
              'must_be_hdl_vector' => 1,
8611 
              'period' => 1.0,
8612 
              'port_id' => '20',
8613 
              'simulinkName' => 'USER_LOGIC/user_int_1o',
8614 
              'source_block' => 'USER_LOGIC',
8615 
              'timingConstraint' => 'none',
8616 
              'type' => 'Bool',
8617 
            },
8618 
            'direction' => 'out',
8619 
            'hdlType' => 'std_logic',
8620 
            'width' => 1,
8621 
          },
8622 
          'user_int_2o' => {
8623 
            'attributes' => {
8624 
              'bin_pt' => 0,
8625 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
8626 
              'is_floating_block' => 1,
8627 
              'is_gateway_port' => 1,
8628 
              'must_be_hdl_vector' => 1,
8629 
              'period' => 1.0,
8630 
              'port_id' => '30',
8631 
              'simulinkName' => 'USER_LOGIC/user_int_2o',
8632 
              'source_block' => 'USER_LOGIC',
8633 
              'timingConstraint' => 'none',
8634 
              'type' => 'Bool',
8635 
            },
8636 
            'direction' => 'out',
8637 
            'hdlType' => 'std_logic',
8638 
            'width' => 1,
8639 
          },
8640 
          'user_int_3o' => {
8641 
            'attributes' => {
8642 
              'bin_pt' => 0,
8643 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
8644 
              'is_floating_block' => 1,
8645 
              'is_gateway_port' => 1,
8646 
              'must_be_hdl_vector' => 1,
8647 
              'period' => 1.0,
8648 
              'port_id' => '25',
8649 
              'simulinkName' => 'USER_LOGIC/user_int_3o',
8650 
              'source_block' => 'USER_LOGIC',
8651 
              'timingConstraint' => 'none',
8652 
              'type' => 'Bool',
8653 
            },
8654 
            'direction' => 'out',
8655 
            'hdlType' => 'std_logic',
8656 
            'width' => 1,
8657 
          },
8658 
        },
8659 
      },
8660 
      'entityName' => 'user_logic',
8661 
    },
8662 
  },
8663 
}

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